1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Handle --with-cpu default option from configure script. */
36 #define OPTION_DEFAULT_SPECS \
37 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
38 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
39 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
40 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
42 /* Pass flags to gas indicating which type of processor we have. This
43 can be simplified when we can rely on the assembler supporting .cpu
44 and .arch directives. */
46 #define ASM_CPU_SPEC "\
47 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
48 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
49 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
50 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
51 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
54 #define ASM_SPEC "%(asm_cpu_spec)"
57 { "asm_cpu_spec", ASM_CPU_SPEC }, \
60 #define SUBTARGET_EXTRA_SPECS
62 /* Note that some other tm.h files include this one and then override
63 many of the definitions that relate to assembler syntax. */
65 #define TARGET_CPU_CPP_BUILTINS() \
68 builtin_define ("__m68k__"); \
69 builtin_define_std ("mc68000"); \
70 /* The other mc680x0 macros have traditionally been derived \
71 from the tuning setting. For example, -m68020-60 defines \
72 m68060, even though it generates pure 68020 code. */ \
76 builtin_define_std ("mc68010"); \
80 builtin_define_std ("mc68020"); \
84 builtin_define_std ("mc68030"); \
88 builtin_define_std ("mc68040"); \
92 builtin_define_std ("mc68060"); \
96 builtin_define_std ("mc68060"); \
99 builtin_define_std ("mc68040"); \
100 builtin_define_std ("mc68030"); \
101 builtin_define_std ("mc68020"); \
105 builtin_define_std ("mc68332"); \
106 builtin_define_std ("mcpu32"); \
107 builtin_define_std ("mc68020"); \
115 builtin_define ("__HAVE_68881__"); \
117 if (TARGET_COLDFIRE) \
119 builtin_define ("__mcoldfire__"); \
121 builtin_define ("__mcfisac__"); \
122 else if (TARGET_ISAB) \
124 builtin_define ("__mcfisab__"); \
125 /* ISA_B: Legacy 5407 defines. */ \
126 builtin_define ("__mcf5400__"); \
127 builtin_define ("__mcf5407__"); \
129 else if (TARGET_ISAAPLUS) \
131 builtin_define ("__mcfisaaplus__"); \
132 /* ISA_A+: legacy defines. */ \
133 builtin_define ("__mcf528x__"); \
134 builtin_define ("__mcf5200__"); \
138 builtin_define ("__mcfisaa__"); \
139 /* ISA_A: legacy defines. */ \
143 builtin_define ("__mcf5200__"); \
147 builtin_define ("__mcf5307__"); \
148 builtin_define ("__mcf5300__"); \
155 if (m68k_tune == ucfv4e) \
156 builtin_define ("__mcfv4e__"); \
159 if (TARGET_CF_HWDIV) \
160 builtin_define ("__mcfhwdiv__"); \
162 builtin_assert ("cpu=m68k"); \
163 builtin_assert ("machine=m68k"); \
167 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
169 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
170 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
171 #define INT_OP_NO_DOT 2 /* byte, short, long */
172 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
174 /* Set the default. */
175 #define INT_OP_GROUP INT_OP_DOT_WORD
177 /* Bit values used by m68k-devices.def to identify processor capabilities. */
178 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
179 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
180 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
181 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
182 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
183 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
184 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
185 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
186 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
187 #define FL_ISA_68000 (1 << 9)
188 #define FL_ISA_68010 (1 << 10)
189 #define FL_ISA_68020 (1 << 11)
190 #define FL_ISA_68040 (1 << 12)
191 #define FL_ISA_A (1 << 13)
192 #define FL_ISA_APLUS (1 << 14)
193 #define FL_ISA_B (1 << 15)
194 #define FL_ISA_C (1 << 16)
195 #define FL_MMU 0 /* Used by multilib machinery. */
197 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
198 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
199 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
200 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
201 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
202 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
204 /* Size (in bytes) of FPU registers. */
205 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
207 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
208 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
209 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
211 #define TUNE_68000 (m68k_tune == u68000)
212 #define TUNE_68010 (m68k_tune == u68010)
213 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
214 #define TUNE_68030 (m68k_tune == u68030 \
215 || m68k_tune == u68020_40 \
216 || m68k_tune == u68020_60)
217 #define TUNE_68040 (m68k_tune == u68040 \
218 || m68k_tune == u68020_40 \
219 || m68k_tune == u68020_60)
220 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
221 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
222 #define TUNE_CPU32 (m68k_tune == ucpu32)
223 #define TUNE_CFV2 (m68k_tune == ucfv2)
225 #define OVERRIDE_OPTIONS override_options()
227 /* These are meant to be redefined in the host dependent files */
228 #define SUBTARGET_OVERRIDE_OPTIONS
230 /* target machine storage layout */
232 #define LONG_DOUBLE_TYPE_SIZE 80
234 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
235 instructions, we get proper intermediate rounding, otherwise we
236 get extended precision results. */
237 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
239 #define BITS_BIG_ENDIAN 1
240 #define BYTES_BIG_ENDIAN 1
241 #define WORDS_BIG_ENDIAN 1
243 #define UNITS_PER_WORD 4
245 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
246 #define STACK_BOUNDARY 16
247 #define FUNCTION_BOUNDARY 16
248 #define EMPTY_FIELD_BOUNDARY 16
250 /* No data type wants to be aligned rounder than this.
251 Most published ABIs say that ints should be aligned on 16 bit
252 boundaries, but CPUs with 32-bit busses get better performance
253 aligned on 32-bit boundaries. ColdFires without a misalignment
254 module require 32-bit alignment. */
255 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
257 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
259 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
261 /* Define these to avoid dependence on meaning of `int'. */
262 #define WCHAR_TYPE "long int"
263 #define WCHAR_TYPE_SIZE 32
265 /* Maximum number of library IDs we permit with -mid-shared-library. */
266 #define MAX_LIBRARY_ID 255
269 /* Standard register usage. */
271 /* For the m68k, we give the data registers numbers 0-7,
272 the address registers numbers 010-017 (8-15),
273 and the 68881 floating point registers numbers 020-027 (16-24).
274 We also have a fake `arg-pointer' register 030 (25) used for
275 register elimination. */
276 #define FIRST_PSEUDO_REGISTER 25
278 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
279 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
281 /* 1 for registers that have pervasive standard uses
282 and are not available for the register allocator.
283 On the m68k, only the stack pointer is such.
284 Our fake arg-pointer is obviously fixed as well. */
285 #define FIXED_REGISTERS \
286 {/* Data registers. */ \
287 0, 0, 0, 0, 0, 0, 0, 0, \
289 /* Address registers. */ \
290 0, 0, 0, 0, 0, 0, 0, 1, \
292 /* Floating point registers \
294 0, 0, 0, 0, 0, 0, 0, 0, \
299 /* 1 for registers not available across function calls.
300 These must include the FIXED_REGISTERS and also any
301 registers that can be used without being saved.
302 The latter must include the registers where values are returned
303 and the register where structure-value addresses are passed.
304 Aside from that, you can include as many other registers as you like. */
305 #define CALL_USED_REGISTERS \
306 {/* Data registers. */ \
307 1, 1, 0, 0, 0, 0, 0, 0, \
309 /* Address registers. */ \
310 1, 1, 0, 0, 0, 0, 0, 1, \
312 /* Floating point registers \
314 1, 1, 0, 0, 0, 0, 0, 0, \
319 #define REG_ALLOC_ORDER \
320 { /* d0/d1/a0/a1 */ \
325 10, 11, 12, 13, 14, 15, 24, \
327 16, 17, 18, 19, 20, 21, 22, 23\
331 /* Make sure everything's fine if we *don't* have a given processor.
332 This assumes that putting a register in fixed_regs will keep the
333 compiler's mitts completely off it. We don't bother to zero it out
334 of register classes. */
335 #define CONDITIONAL_REGISTER_USAGE \
339 if (!TARGET_HARD_FLOAT) \
341 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
342 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
343 if (TEST_HARD_REG_BIT (x, i)) \
344 fixed_regs[i] = call_used_regs[i] = 1; \
346 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
347 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
348 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
351 /* On the m68k, ordinary registers hold 32 bits worth;
352 for the 68881 registers, a single register is always enough for
353 anything that can be stored in them at all. */
354 #define HARD_REGNO_NREGS(REGNO, MODE) \
355 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
356 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
358 /* A C expression that is nonzero if hard register NEW_REG can be
359 considered for use as a rename register for OLD_REG register. */
361 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
362 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
364 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
365 On the 68000, the cpu registers can hold any mode except bytes in
366 address registers, the 68881 registers can hold only SFmode or DFmode. */
368 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
369 m68k_regno_mode_ok ((REGNO), (MODE))
371 #define MODES_TIEABLE_P(MODE1, MODE2) \
372 (! TARGET_HARD_FLOAT \
373 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
374 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
375 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
376 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
378 /* Specify the registers used for certain standard purposes.
379 The values of these macros are register numbers. */
381 #define STACK_POINTER_REGNUM 15
383 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
384 ABI uses %a6 for shared library calls, therefore the frame
385 pointer is shifted to %a5 on this target. */
386 #define FRAME_POINTER_REGNUM 14
388 #define FRAME_POINTER_REQUIRED 0
390 /* Base register for access to arguments of the function.
391 * This isn't a hardware register. It will be eliminated to the
392 * stack pointer or frame pointer.
394 #define ARG_POINTER_REGNUM 24
396 #define STATIC_CHAIN_REGNUM 8
398 /* Register in which address to store a structure value
399 is passed to a function. */
400 #define M68K_STRUCT_VALUE_REGNUM 9
404 /* The m68k has three kinds of registers, so eight classes would be
405 a complete set. One of them is not needed. */
409 GENERAL_REGS, DATA_OR_FP_REGS,
410 ADDR_OR_FP_REGS, ALL_REGS,
413 #define N_REG_CLASSES (int) LIM_REG_CLASSES
415 #define REG_CLASS_NAMES \
416 { "NO_REGS", "DATA_REGS", \
417 "ADDR_REGS", "FP_REGS", \
418 "GENERAL_REGS", "DATA_OR_FP_REGS", \
419 "ADDR_OR_FP_REGS", "ALL_REGS" }
421 #define REG_CLASS_CONTENTS \
423 {0x00000000}, /* NO_REGS */ \
424 {0x000000ff}, /* DATA_REGS */ \
425 {0x0100ff00}, /* ADDR_REGS */ \
426 {0x00ff0000}, /* FP_REGS */ \
427 {0x0100ffff}, /* GENERAL_REGS */ \
428 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
429 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
430 {0x01ffffff}, /* ALL_REGS */ \
433 extern enum reg_class regno_reg_class[];
434 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
435 #define INDEX_REG_CLASS GENERAL_REGS
436 #define BASE_REG_CLASS ADDR_REGS
438 /* We do a trick here to modify the effective constraints on the
439 machine description; we zorch the constraint letters that aren't
440 appropriate for a specific target. This allows us to guarantee
441 that a specific kind of register will not be used for a given target
442 without fiddling with the register classes above. */
443 #define REG_CLASS_FROM_LETTER(C) \
444 ((C) == 'a' ? ADDR_REGS : \
445 ((C) == 'd' ? DATA_REGS : \
446 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
447 FP_REGS : NO_REGS) : \
450 /* For the m68k, `I' is used for the range 1 to 8
451 allowed as immediate shift counts and in addq.
452 `J' is used for the range of signed numbers that fit in 16 bits.
453 `K' is for numbers that moveq can't handle.
454 `L' is for range -8 to -1, range of values that can be added with subq.
455 `M' is for numbers that moveq+notb can't handle.
456 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
457 'O' is for 16 (for rotate using swap).
458 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
459 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
460 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
461 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
462 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
463 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
464 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
465 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
466 (C) == 'O' ? (VALUE) == 16 : \
467 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
469 /* "G" defines all of the floating constants that are *NOT* 68881
470 constants. This is so 68881 constants get reloaded and the
472 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
473 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
475 /* `Q' means address register indirect addressing mode.
476 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
477 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
478 `U' is for register offset addressing. */
479 #define EXTRA_CONSTRAINT(OP,CODE) \
482 && GET_CODE (OP) == MEM \
483 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
484 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
485 || GET_CODE (XEXP (OP, 0)) == CONST)) \
489 && (GET_CODE (OP) == SYMBOL_REF \
490 || GET_CODE (OP) == LABEL_REF \
491 || GET_CODE (OP) == CONST)) \
494 ? (GET_CODE (OP) == MEM \
495 && GET_CODE (XEXP (OP, 0)) == REG) \
498 ? (GET_CODE (OP) == MEM \
499 && GET_CODE (XEXP (OP, 0)) == PLUS \
500 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
501 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
505 /* On the m68k, use a data reg if possible when the
506 value is a constant in the range where moveq could be used
507 and we ensure that QImodes are reloaded into data regs. */
508 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
509 ((GET_CODE (X) == CONST_INT \
510 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
511 && (CLASS) != ADDR_REGS) \
513 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
515 : (GET_CODE (X) == CONST_DOUBLE \
516 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
517 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
518 ? FP_REGS : NO_REGS) \
520 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
521 || GET_CODE (X) == LABEL_REF)) \
525 /* Force QImode output reloads from subregs to be allocated to data regs,
526 since QImode stores from address regs are not supported. We make the
527 assumption that if the class is not ADDR_REGS, then it must be a superset
529 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
530 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
534 /* On the m68k, this is the size of MODE in words,
535 except in the FP regs, where a single reg is always enough. */
536 #define CLASS_MAX_NREGS(CLASS, MODE) \
537 ((CLASS) == FP_REGS ? 1 \
538 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
540 /* Moves between fp regs and other regs are two insns. */
541 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
542 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
543 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
546 /* Stack layout; function entry, exit and calling. */
548 #define STACK_GROWS_DOWNWARD
549 #define FRAME_GROWS_DOWNWARD 1
550 #define STARTING_FRAME_OFFSET 0
552 /* On the 680x0, sp@- in a byte insn really pushes a word.
553 On the ColdFire, sp@- in a byte insn pushes just a byte. */
554 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
556 #define FIRST_PARM_OFFSET(FNDECL) 8
558 /* On the 68000, the RTS insn cannot pop anything.
559 On the 68010, the RTD insn may be used to pop them if the number
560 of args is fixed, but if the number is variable then the caller
561 must pop them all. RTD can't be used for library calls now
562 because the library is compiled with the Unix compiler.
563 Use of RTD is a selectable option, since it is incompatible with
564 standard Unix calling sequences. If the option is not selected,
565 the caller must always pop the args. */
566 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
567 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
568 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
569 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
570 == void_type_node))) \
573 /* On the m68k the return value is always in D0. */
574 #define FUNCTION_VALUE(VALTYPE, FUNC) \
575 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
577 /* On the m68k the return value is always in D0. */
578 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
580 /* On the m68k, D0 is the only register used. */
581 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
583 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
584 more than one register.
585 XXX This macro is m68k specific and used only for m68kemb.h. */
586 #define NEEDS_UNTYPED_CALL 0
588 #define PCC_STATIC_STRUCT_RETURN
590 /* On the m68k, all arguments are usually pushed on the stack. */
591 #define FUNCTION_ARG_REGNO_P(N) 0
593 /* On the m68k, this is a single integer, which is a number of bytes
594 of arguments scanned so far. */
595 #define CUMULATIVE_ARGS int
597 /* On the m68k, the offset starts at 0. */
598 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
601 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
602 ((CUM) += ((MODE) != BLKmode \
603 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
604 : (int_size_in_bytes (TYPE) + 3) & ~3))
606 /* On the m68k all args are always pushed. */
607 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
609 #define FUNCTION_PROFILER(FILE, LABELNO) \
610 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
612 #define EXIT_IGNORE_STACK 1
614 /* Determine if the epilogue should be output as RTL.
615 You should override this if you define FUNCTION_EXTRA_EPILOGUE.
617 XXX This macro is m68k-specific and only used in m68k.md. */
618 #define USE_RETURN_INSN use_return_insn ()
620 /* Output assembler code for a block containing the constant parts
621 of a trampoline, leaving space for the variable parts.
623 On the m68k, the trampoline looks like this:
627 WARNING: Targets that may run on 68040+ cpus must arrange for
628 the instruction cache to be flushed. Previous incarnations of
629 the m68k trampoline code attempted to get around this by either
630 using an out-of-line transfer function or pc-relative data, but
631 the fact remains that the code to jump to the transfer function
632 or the code to load the pc-relative data needs to be flushed
633 just as much as the "variable" portion of the trampoline.
634 Recognizing that a cache flush is going to be required anyway,
635 dispense with such notions and build a smaller trampoline.
637 Since more instructions are required to move a template into
638 place than to create it on the spot, don't use a template. */
640 #define TRAMPOLINE_SIZE 12
641 #define TRAMPOLINE_ALIGNMENT 16
643 /* Targets redefine this to invoke code to either flush the cache,
644 or enable stack execution (or both). */
645 #ifndef FINALIZE_TRAMPOLINE
646 #define FINALIZE_TRAMPOLINE(TRAMP)
649 /* We generate a two-instructions program at address TRAMP :
652 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
654 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
655 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
656 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
658 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
659 FINALIZE_TRAMPOLINE(TRAMP); \
662 /* This is the library routine that is used to transfer control from the
663 trampoline to the actual nested function. It is defined for backward
664 compatibility, for linking with object code that used the old trampoline
667 A colon is used with no explicit operands to cause the template string
668 to be scanned for %-constructs.
670 The function name __transfer_from_trampoline is not actually used.
671 The function definition just permits use of "asm with operands"
672 (though the operand list is empty). */
673 #define TRANSFER_FROM_TRAMPOLINE \
675 __transfer_from_trampoline () \
677 register char *a0 asm ("%a0"); \
678 asm (GLOBAL_ASM_OP "___trampoline"); \
679 asm ("___trampoline:"); \
680 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
681 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
685 /* There are two registers that can always be eliminated on the m68k.
686 The frame pointer and the arg pointer can be replaced by either the
687 hard frame pointer or to the stack pointer, depending upon the
688 circumstances. The hard frame pointer is not used before reload and
689 so it is not eligible for elimination. */
690 #define ELIMINABLE_REGS \
691 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
692 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
693 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
695 #define CAN_ELIMINATE(FROM, TO) \
696 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
698 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
699 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
701 /* Addressing modes, and classification of registers for them. */
703 #define HAVE_POST_INCREMENT 1
704 #define HAVE_PRE_DECREMENT 1
706 /* Macros to check register numbers against specific register classes. */
708 #define REGNO_OK_FOR_INDEX_P(REGNO) \
709 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
710 #define REGNO_OK_FOR_BASE_P(REGNO) \
711 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
712 #define REGNO_OK_FOR_DATA_P(REGNO) \
713 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
714 #define REGNO_OK_FOR_FP_P(REGNO) \
715 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
717 /* Now macros that check whether X is a register and also,
718 strictly, whether it is in a specified class.
720 These macros are specific to the m68k, and may be used only
721 in code for printing assembler insns and in conditions for
722 define_optimization. */
724 /* 1 if X is a data register. */
725 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
727 /* 1 if X is an fp register. */
728 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
730 /* 1 if X is an address register */
731 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
734 #define MAX_REGS_PER_ADDRESS 2
736 #define CONSTANT_ADDRESS_P(X) \
737 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
738 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
739 || GET_CODE (X) == HIGH)
741 /* Nonzero if the constant value X is a legitimate general operand.
742 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
743 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
745 #ifndef REG_OK_STRICT
746 #define PCREL_GENERAL_OPERAND_OK 0
748 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
751 #define LEGITIMATE_PIC_OPERAND_P(X) \
752 (! symbolic_operand (X, VOIDmode) \
753 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
754 || PCREL_GENERAL_OPERAND_OK)
756 #ifndef REG_OK_STRICT
758 /* Nonzero if X is a hard reg that can be used as an index
759 or if it is a pseudo reg. */
760 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
761 /* Nonzero if X is a hard reg that can be used as a base reg
762 or if it is a pseudo reg. */
763 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
767 /* Nonzero if X is a hard reg that can be used as an index. */
768 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
769 /* Nonzero if X is a hard reg that can be used as a base reg. */
770 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
774 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
775 that is a valid memory address for an instruction.
776 The MODE argument is the machine mode for the MEM expression
777 that wants to use this address.
779 When generating PIC, an address involving a SYMBOL_REF is legitimate
780 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
781 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
782 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
784 Likewise for a LABEL_REF when generating PIC.
786 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
788 /* Allow SUBREG everywhere we allow REG. This results in better code. It
789 also makes function inlining work when inline functions are called with
790 arguments that are SUBREGs. */
792 #define LEGITIMATE_BASE_REG_P(X) \
793 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
794 || (GET_CODE (X) == SUBREG \
795 && GET_CODE (SUBREG_REG (X)) == REG \
796 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
798 #define INDIRECTABLE_1_ADDRESS_P(X) \
799 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
800 || LEGITIMATE_BASE_REG_P (X) \
801 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
802 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
803 || (GET_CODE (X) == PLUS \
804 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
805 && GET_CODE (XEXP (X, 1)) == CONST_INT \
807 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
808 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
809 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
810 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
811 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
813 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
814 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
816 /* Only labels on dispatch tables are valid for indexing from. */
817 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
819 if (GET_CODE (X) == LABEL_REF \
820 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
821 && GET_CODE (temp) == JUMP_INSN \
822 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
823 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
825 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
827 #define GO_IF_INDEXING(X, ADDR) \
828 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
829 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
830 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
831 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
833 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
834 { GO_IF_INDEXING (X, ADDR); \
835 if (GET_CODE (X) == PLUS) \
836 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
837 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
838 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
839 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
840 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
841 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
843 /* ColdFire/5200 does not allow HImode index registers. */
844 #define LEGITIMATE_INDEX_REG_P(X) \
845 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
846 || (! TARGET_COLDFIRE \
847 && GET_CODE (X) == SIGN_EXTEND \
848 && GET_CODE (XEXP (X, 0)) == REG \
849 && GET_MODE (XEXP (X, 0)) == HImode \
850 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
851 || (GET_CODE (X) == SUBREG \
852 && GET_CODE (SUBREG_REG (X)) == REG \
853 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
855 #define LEGITIMATE_INDEX_P(X) \
856 (LEGITIMATE_INDEX_REG_P (X) \
857 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
858 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
859 && GET_CODE (XEXP (X, 1)) == CONST_INT \
860 && (INTVAL (XEXP (X, 1)) == 2 \
861 || INTVAL (XEXP (X, 1)) == 4 \
862 || (INTVAL (XEXP (X, 1)) == 8 \
863 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
865 /* Coldfire FPU only accepts addressing modes 2-5 */
866 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
867 { if (LEGITIMATE_BASE_REG_P (X) \
868 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
869 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
870 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
871 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
872 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
875 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
876 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
877 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
879 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
883 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
884 GO_IF_INDEXED_ADDRESS (X, ADDR); \
885 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
886 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
887 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
891 /* Don't call memory_address_noforce for the address to fetch
892 the switch offset. This address is ok as it stands (see above),
893 but memory_address_noforce would alter it. */
894 #define PIC_CASE_VECTOR_ADDRESS(index) index
896 /* For the 68000, we handle X+REG by loading X into a register R and
897 using R+REG. R will go in an address reg and indexing will be used.
898 However, if REG is a broken-out memory address or multiplication,
899 nothing needs to be done because REG can certainly go in an address reg. */
900 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
901 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
902 { register int ch = (X) != (OLDX); \
903 if (GET_CODE (X) == PLUS) \
905 if (GET_CODE (XEXP (X, 0)) == MULT) \
906 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
907 if (GET_CODE (XEXP (X, 1)) == MULT) \
908 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
909 if (ch && GET_CODE (XEXP (X, 1)) == REG \
910 && GET_CODE (XEXP (X, 0)) == REG) \
911 { if (TARGET_COLDFIRE_FPU \
912 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
913 { COPY_ONCE (X); X = force_operand (X, 0);} \
915 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
916 if (GET_CODE (XEXP (X, 0)) == REG \
917 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
918 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
919 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
920 { register rtx temp = gen_reg_rtx (Pmode); \
921 register rtx val = force_operand (XEXP (X, 1), 0); \
922 emit_move_insn (temp, val); \
924 XEXP (X, 1) = temp; \
925 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
926 && GET_CODE (XEXP (X, 0)) == REG) \
927 X = force_operand (X, 0); \
929 else if (GET_CODE (XEXP (X, 1)) == REG \
930 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
931 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
932 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
933 { register rtx temp = gen_reg_rtx (Pmode); \
934 register rtx val = force_operand (XEXP (X, 0), 0); \
935 emit_move_insn (temp, val); \
937 XEXP (X, 0) = temp; \
938 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
939 && GET_CODE (XEXP (X, 1)) == REG) \
940 X = force_operand (X, 0); \
943 /* On the 68000, only predecrement and postincrement address depend thus
944 (the amount of decrement or increment being the length of the operand).
945 These are now treated generically in recog.c. */
946 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
948 #define CASE_VECTOR_MODE HImode
949 #define CASE_VECTOR_PC_RELATIVE 1
951 #define DEFAULT_SIGNED_CHAR 1
953 #define SLOW_BYTE_ACCESS 0
955 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
957 #define STORE_FLAG_VALUE (-1)
960 #define FUNCTION_MODE QImode
963 /* Tell final.c how to eliminate redundant test instructions. */
965 /* Here we define machine-dependent flags and fields in cc_status
966 (see `conditions.h'). */
968 /* Set if the cc value is actually in the 68881, so a floating point
969 conditional branch must be output. */
970 #define CC_IN_68881 04000
972 /* On the 68000, all the insns to store in an address register fail to
973 set the cc's. However, in some cases these instructions can make it
974 possibly invalid to use the saved cc's. In those cases we clear out
975 some or all of the saved cc's so they won't be used. */
976 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
978 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
979 do { if (cc_prev_status.flags & CC_IN_68881) \
981 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
983 return NORMAL; } while (0)
985 /* Control the assembler format that we output. */
987 #define ASM_APP_ON "#APP\n"
988 #define ASM_APP_OFF "#NO_APP\n"
989 #define TEXT_SECTION_ASM_OP "\t.text"
990 #define DATA_SECTION_ASM_OP "\t.data"
991 #define GLOBAL_ASM_OP "\t.globl\t"
992 #define REGISTER_PREFIX ""
993 #define LOCAL_LABEL_PREFIX ""
994 #define USER_LABEL_PREFIX "_"
995 #define IMMEDIATE_PREFIX "#"
997 #define REGISTER_NAMES \
998 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
999 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
1000 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
1001 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
1002 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
1003 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
1004 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
1005 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
1006 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
1008 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
1010 /* Return a register name by index, handling %fp nicely.
1011 We don't replace %fp for targets that don't map it to %a6
1012 since it may confuse GAS. */
1013 #define M68K_REGNAME(r) ( \
1014 ((FRAME_POINTER_REGNUM == 14) \
1015 && ((r) == FRAME_POINTER_REGNUM) \
1016 && frame_pointer_needed) ? \
1017 M68K_FP_REG_NAME : reg_names[(r)])
1019 /* On the Sun-3, the floating point registers have numbers
1020 18 to 25, not 16 to 23 as they do in the compiler. */
1021 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1023 /* Before the prologue, RA is at 0(%sp). */
1024 #define INCOMING_RETURN_ADDR_RTX \
1025 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1027 /* After the prologue, RA is at 4(AP) in the current frame. */
1028 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1030 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
1031 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1033 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1034 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1035 Instead use the identity mapping. */
1036 #define DWARF_FRAME_REGNUM(REG) REG
1038 /* Before the prologue, the top of the frame is at 4(%sp). */
1039 #define INCOMING_FRAME_SP_OFFSET 4
1041 /* Describe how we implement __builtin_eh_return. */
1042 #define EH_RETURN_DATA_REGNO(N) \
1043 ((N) < 2 ? (N) : INVALID_REGNUM)
1044 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1045 #define EH_RETURN_HANDLER_RTX \
1046 gen_rtx_MEM (Pmode, \
1047 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1048 plus_constant (EH_RETURN_STACKADJ_RTX, \
1051 /* Select a format to encode pointers in exception handling data. CODE
1052 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1053 true if the symbol may be affected by dynamic relocations. */
1054 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1056 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1059 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1060 asm_fprintf (FILE, "%U%s", NAME)
1062 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1063 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1065 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1066 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1067 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1068 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1070 /* The m68k does not use absolute case-vectors, but we must define this macro
1072 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1073 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1075 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1076 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1078 /* We don't have a way to align to more than a two-byte boundary, so do the
1079 best we can and don't complain. */
1080 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1082 fprintf (FILE, "\t.even\n");
1084 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1085 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1087 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1088 ( fputs (".comm ", (FILE)), \
1089 assemble_name ((FILE), (NAME)), \
1090 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1092 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1093 ( fputs (".lcomm ", (FILE)), \
1094 assemble_name ((FILE), (NAME)), \
1095 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1097 /* Output a float value (represented as a C double) as an immediate operand.
1098 This macro is m68k-specific. */
1099 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1104 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1105 asm_fprintf ((FILE), "%I0r%s", dstr); \
1110 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1111 asm_fprintf ((FILE), "%I0x%lx", l); \
1115 /* Output a double value (represented as a C double) as an immediate operand.
1116 This macro is m68k-specific. */
1117 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1118 do { char dstr[30]; \
1119 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1120 asm_fprintf (FILE, "%I0r%s", dstr); \
1123 /* Note, long double immediate operands are not actually
1124 generated by m68k.md. */
1125 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1126 do { char dstr[30]; \
1127 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1128 asm_fprintf (FILE, "%I0r%s", dstr); \
1131 /* On the 68000, we use several CODE characters:
1132 '.' for dot needed in Motorola-style opcode names.
1133 '-' for an operand pushing on the stack:
1134 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1135 '+' for an operand pushing on the stack:
1136 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1137 '@' for a reference to the top word on the stack:
1138 sp@, (sp) or (%sp) depending on the style of syntax.
1139 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1140 but & in SGS syntax).
1141 '!' for the fpcr register (used in some float-to-fixed conversions).
1142 '$' for the letter `s' in an op code, but only on the 68040.
1143 '&' for the letter `d' in an op code, but only on the 68040.
1144 '/' for register prefix needed by longlong.h.
1146 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1147 'd' to force memory addressing to be absolute, not relative.
1148 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1149 'o' for operands to go directly to output_operand_address (bypassing
1150 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1151 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1152 or print pair of registers as rx:ry. */
1154 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1155 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1156 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1157 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1160 /* See m68k.c for the m68k specific codes. */
1161 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1163 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1165 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1185 /* An enumeration of all supported target devices. */
1188 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1190 #include "m68k-devices.def"
1202 /* Variables in m68k.c; see there for details. */
1203 extern const char *m68k_library_id_string;
1204 extern int m68k_last_compare_had_fp_operands;
1205 extern enum target_device m68k_cpu;
1206 extern enum uarch_type m68k_tune;
1207 extern enum fpu_type m68k_fpu;
1208 extern unsigned int m68k_cpu_flags;