1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() \
31 builtin_define ("__m68k__"); \
32 builtin_define_std ("mc68000"); \
33 if (TARGET_68040_ONLY) \
36 builtin_define_std ("mc68060"); \
38 builtin_define_std ("mc68040"); \
40 else if (TARGET_68060) /* -m68020-60 */ \
42 builtin_define_std ("mc68060"); \
43 builtin_define_std ("mc68040"); \
44 builtin_define_std ("mc68030"); \
45 builtin_define_std ("mc68020"); \
47 else if (TARGET_68040) /* -m68020-40 */ \
49 builtin_define_std ("mc68040"); \
50 builtin_define_std ("mc68030"); \
51 builtin_define_std ("mc68020"); \
53 else if (TARGET_68030) \
54 builtin_define_std ("mc68030"); \
55 else if (TARGET_68020) \
56 builtin_define_std ("mc68020"); \
58 builtin_define ("__HAVE_68881__"); \
61 builtin_define_std ("mc68332"); \
62 builtin_define_std ("mcpu32"); \
64 if (TARGET_COLDFIRE) \
65 builtin_define ("__mcoldfire__"); \
67 builtin_define ("__mcf5200__"); \
70 builtin_define ("__mcf528x__"); \
71 builtin_define ("__mcf5200__"); \
75 builtin_define ("__mcf5300__"); \
76 builtin_define ("__mcf5307__"); \
80 builtin_define ("__mcf5400__"); \
81 builtin_define ("__mcf5407__"); \
83 if (TARGET_CF_HWDIV) \
84 builtin_define ("__mcfhwdiv__"); \
87 builtin_define ("__pic__"); \
89 builtin_define ("__PIC__"); \
91 builtin_assert ("cpu=m68k"); \
92 builtin_assert ("machine=m68k"); \
96 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
98 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
99 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
100 #define INT_OP_NO_DOT 2 /* byte, short, long */
101 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
103 /* Set the default */
104 #define INT_OP_GROUP INT_OP_DOT_WORD
106 /* Print subsidiary information on the compiler version in use. */
108 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
110 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
113 /* Run-time compilation parameters selecting different hardware subsets. */
115 extern int target_flags;
117 /* Macros used in the machine description to test the flags. */
119 /* Compile for a 68020 (not a 68000 or 68010). */
120 #define MASK_68020 (1<<0)
121 #define TARGET_68020 (target_flags & MASK_68020)
123 /* Compile for a 68030. This does not really make a difference in GCC,
124 it just enables the __mc68030__ predefine. */
125 #define MASK_68030 (1<<1)
126 #define TARGET_68030 (target_flags & MASK_68030)
128 /* Optimize for 68040, but still allow execution on 68020
129 (-m68020-40 or -m68040).
130 The 68040 will execute all 68030 and 68881/2 instructions, but some
131 of them must be emulated in software by the OS. When TARGET_68040 is
132 turned on, these instructions won't be used. This code will still
133 run on a 68030 and 68881/2. */
134 #define MASK_68040 (1<<2)
135 #define TARGET_68040 (target_flags & MASK_68040)
137 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
138 #define MASK_68040_ONLY (1<<3)
139 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
141 /* Optimize for 68060, but still allow execution on 68020
142 (-m68020-60 or -m68060).
143 The 68060 will execute all 68030 and 68881/2 instructions, but some
144 of them must be emulated in software by the OS. When TARGET_68060 is
145 turned on, these instructions won't be used. This code will still
146 run on a 68030 and 68881/2. */
147 #define MASK_68060 (1<<4)
148 #define TARGET_68060 (target_flags & MASK_68060)
150 /* Compile for mcf5200 */
151 #define MASK_5200 (1<<5)
152 #define TARGET_5200 (target_flags & MASK_5200)
154 /* Build for ColdFire v3 */
155 #define MASK_CFV3 (1<<6)
156 #define TARGET_CFV3 (target_flags & MASK_CFV3)
158 /* Build for ColdFire v4 */
159 #define MASK_CFV4 (1<<7)
160 #define TARGET_CFV4 (target_flags & MASK_CFV4)
162 /* Compile for ColdFire 528x */
163 #define MASK_528x (1<<8)
164 #define TARGET_528x (target_flags & MASK_528x)
166 /* Divide support for ColdFire */
167 #define MASK_CF_HWDIV (1<<9)
168 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
170 /* Compile 68881 insns for floating point (not library calls). */
171 #define MASK_68881 (1<<10)
172 #define TARGET_68881 (target_flags & MASK_68881)
174 /* Compile using 68020 bit-field insns. */
175 #define MASK_BITFIELD (1<<11)
176 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
178 /* Compile with 16-bit `int'. */
179 #define MASK_SHORT (1<<12)
180 #define TARGET_SHORT (target_flags & MASK_SHORT)
182 /* Align ints to a word boundary. This breaks compatibility with the
183 published ABI's for structures containing ints, but produces faster
184 code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
185 It's required for ColdFire cpus without a misalignment module. */
186 #define MASK_ALIGN_INT (1<<13)
187 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
189 /* Use PC-relative addressing modes (without using a global offset table).
190 The m68000 supports 16-bit PC-relative addressing.
191 The m68020 supports 32-bit PC-relative addressing
192 (using outer displacements).
194 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
195 treated as all containing an implicit PC-relative component, and hence
196 cannot be used directly as addresses for memory writes. See the comments
197 in m68k.c for more information. */
198 #define MASK_PCREL (1<<14)
199 #define TARGET_PCREL (target_flags & MASK_PCREL)
201 /* Relax strict alignment. */
202 #define MASK_NO_STRICT_ALIGNMENT (1<<15)
203 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
205 /* Compile using rtd insn calling sequence.
206 This will not work unless you use prototypes at least
207 for all functions that can take varying numbers of args. */
208 #define MASK_RTD (1<<16)
209 #define TARGET_RTD (target_flags & MASK_RTD)
211 /* Support A5 relative data seperate from text.
212 * This option implies -fPIC, however it inhibits the generation of the
213 * A5 save/restore in functions and the loading of a5 with a got pointer.
215 #define MASK_SEP_DATA (1<<17)
216 #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
218 /* Compile using library ID based shared libraries.
219 * Set a specific ID using the -mshared-library-id=xxx option.
221 #define MASK_ID_SHARED_LIBRARY (1<<18)
222 #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
224 /* Compile for a CPU32. A 68020 without bitfields is a good
225 heuristic for a CPU32. */
226 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
228 /* Is the target a ColdFire? */
229 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
230 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
232 /* Which bits can be set by specifying a ColdFire */
233 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
235 /* Macro to define tables used to set the flags.
236 This is a list in braces of pairs in braces,
237 each pair being { "NAME", VALUE }
238 where VALUE is the bits to set or minus the bits to clear.
239 An empty string NAME is used to identify the default VALUE. */
241 #define TARGET_SWITCHES \
242 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
243 N_("Generate code for a 68020") }, \
244 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
245 N_("Generate code for a 68020") }, \
246 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
247 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
248 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
249 |MASK_68020|MASK_BITFIELD|MASK_68881), \
250 N_("Generate code for a 68000") }, \
251 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
252 |MASK_68020|MASK_BITFIELD|MASK_68881), \
253 N_("Generate code for a 68000") }, \
254 { "bitfield", MASK_BITFIELD, \
255 N_("Use the bit-field instructions") }, \
256 { "nobitfield", - MASK_BITFIELD, \
257 N_("Do not use the bit-field instructions") }, \
258 { "short", MASK_SHORT, \
259 N_("Consider type `int' to be 16 bits wide") }, \
260 { "noshort", - MASK_SHORT, \
261 N_("Consider type `int' to be 32 bits wide") }, \
262 { "68881", MASK_68881, "" }, \
263 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
264 N_("Generate code with library calls for floating point") }, \
265 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
266 N_("Generate code for a 68040, without any new instructions") }, \
267 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
268 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
269 N_("Generate code for a 68060, without any new instructions") }, \
270 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
271 |MASK_68060), "" }, \
272 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
273 N_("Generate code for a 68030") }, \
274 { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \
275 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
276 N_("Generate code for a 68040") }, \
277 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
278 |MASK_68040_ONLY|MASK_68040), "" }, \
279 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
280 N_("Generate code for a 68060") }, \
281 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
282 |MASK_68040_ONLY|MASK_68060), "" }, \
283 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
284 |MASK_BITFIELD|MASK_68881), \
285 N_("Generate code for a 520X") }, \
286 { "5200", (MASK_5200), "" }, \
287 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
288 |MASK_BITFIELD|MASK_68881), \
289 N_("Generate code for a 5206e") }, \
290 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
291 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
292 |MASK_BITFIELD|MASK_68881), \
293 N_("Generate code for a 528x") }, \
294 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
295 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
296 |MASK_BITFIELD|MASK_68881), \
297 N_("Generate code for a 5307") }, \
298 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
299 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
300 |MASK_BITFIELD|MASK_68881), \
301 N_("Generate code for a 5407") }, \
302 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
304 N_("Generate code for a 68851") }, \
306 N_("Do no generate code for a 68851") }, \
307 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
308 |MASK_68020|MASK_BITFIELD|MASK_68881), \
309 N_("Generate code for a 68302") }, \
310 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
311 |MASK_BITFIELD|MASK_68881), \
312 N_("Generate code for a 68332") }, \
313 { "68332", MASK_68020, "" }, \
314 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
315 |MASK_BITFIELD|MASK_68881), \
316 N_("Generate code for a cpu32") }, \
317 { "cpu32", MASK_68020, "" }, \
318 { "align-int", MASK_ALIGN_INT, \
319 N_("Align variables on a 32-bit boundary") }, \
320 { "no-align-int", -MASK_ALIGN_INT, \
321 N_("Align variables on a 16-bit boundary") }, \
322 { "sep-data", MASK_SEP_DATA, \
323 N_("Enable separate data segment") }, \
324 { "no-sep-data", -MASK_SEP_DATA, \
325 N_("Disable separate data segment") }, \
326 { "id-shared-library", MASK_ID_SHARED_LIBRARY, \
327 N_("Enable ID based shared library") }, \
328 { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \
329 N_("Disable ID based shared library") }, \
330 { "pcrel", MASK_PCREL, \
331 N_("Generate pc-relative code") }, \
332 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
333 N_("Do not use unaligned memory references") }, \
334 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
335 N_("Use unaligned memory references") }, \
337 N_("Use different calling convention using 'rtd'") }, \
338 { "nortd", - MASK_RTD, \
339 N_("Use normal calling convention") }, \
341 { "", TARGET_DEFAULT, "" }}
342 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
344 /* This macro is similar to `TARGET_SWITCHES' but defines names of
345 command options that have values. Its definition is an
346 initializer with a subgrouping for each command option.
348 Each subgrouping contains a string constant, that defines the
349 fixed part of the option name, and the address of a variable. The
350 variable, type `char *', is set to the variable part of the given
351 option if the fixed part matches. The actual option name is made
352 by appending `-m' to the specified name. */
353 #define TARGET_OPTIONS \
354 { { "align-loops=", &m68k_align_loops_string, \
355 N_("Loop code aligned to this power of 2"), 0}, \
356 { "align-jumps=", &m68k_align_jumps_string, \
357 N_("Jump targets are aligned to this power of 2"), 0}, \
358 { "align-functions=", &m68k_align_funcs_string, \
359 N_("Function starts are aligned to this power of 2"), 0}, \
360 { "shared-library-id=", &m68k_library_id_string, \
361 N_("ID of shared library to build"), 0}, \
365 /* Sometimes certain combinations of command options do not make
366 sense on a particular target machine. You can define a macro
367 `OVERRIDE_OPTIONS' to take account of this. This macro, if
368 defined, is executed once just after all the command options have
371 Don't use this macro to turn on various extra optimizations for
372 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
374 #define OVERRIDE_OPTIONS override_options()
376 /* These are meant to be redefined in the host dependent files */
377 #define SUBTARGET_SWITCHES
378 #define SUBTARGET_OPTIONS
379 #define SUBTARGET_OVERRIDE_OPTIONS
381 /* target machine storage layout */
383 /* Define for XFmode extended real floating point support. */
384 #define LONG_DOUBLE_TYPE_SIZE 96
386 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
387 instructions, we get proper intermediate rounding, otherwise we
388 get extended precision results. */
389 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
391 /* Define this if most significant bit is lowest numbered
392 in instructions that operate on numbered bit-fields.
393 This is true for 68020 insns such as bfins and bfexts.
394 We make it true always by avoiding using the single-bit insns
395 except in special cases with constant bit numbers. */
396 #define BITS_BIG_ENDIAN 1
398 /* Define this if most significant byte of a word is the lowest numbered. */
399 /* That is true on the 68000. */
400 #define BYTES_BIG_ENDIAN 1
402 /* Define this if most significant word of a multiword number is the lowest
404 /* For 68000 we can decide arbitrarily
405 since there are no machine instructions for them.
406 So let's be consistent. */
407 #define WORDS_BIG_ENDIAN 1
409 /* Width of a word, in units (bytes). */
410 #define UNITS_PER_WORD 4
412 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
413 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
415 /* Boundary (in *bits*) on which stack pointer should be aligned. */
416 #define STACK_BOUNDARY 16
418 /* Allocation boundary (in *bits*) for the code of a function. */
419 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
421 /* Alignment of field after `int : 0' in a structure. */
422 #define EMPTY_FIELD_BOUNDARY 16
424 /* No data type wants to be aligned rounder than this.
425 Most published ABIs say that ints should be aligned on 16 bit
426 boundaries, but cpus with 32-bit busses get better performance
427 aligned on 32-bit boundaries. ColdFires without a misalignment
428 module require 32-bit alignment. */
429 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
431 /* Set this nonzero if move instructions will actually fail to work
432 when given unaligned data. */
433 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
435 /* Maximum power of 2 that code can be aligned to. */
436 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
438 /* Maximum number of library ids we permit */
439 #define MAX_LIBRARY_ID 255
441 /* Align loop starts for optimal branching. */
442 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
444 /* This is how to align an instruction for optimal branching. */
445 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
447 /* Define number of bits in most basic integer type.
448 (If undefined, default is BITS_PER_WORD). */
450 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
452 /* Define these to avoid dependence on meaning of `int'. */
454 #define WCHAR_TYPE "long int"
455 #define WCHAR_TYPE_SIZE 32
457 /* Standard register usage. */
459 /* Number of actual hardware registers.
460 The hardware registers are assigned numbers for the compiler
461 from 0 to just below FIRST_PSEUDO_REGISTER.
462 All registers that the compiler knows about must be given numbers,
463 even those that are not normally considered general registers.
464 For the 68000, we give the data registers numbers 0-7,
465 the address registers numbers 010-017,
466 and the 68881 floating point registers numbers 020-027. */
467 #define FIRST_PSEUDO_REGISTER 25
469 /* This defines the register which is used to hold the offset table for PIC. */
470 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
472 /* 1 for registers that have pervasive standard uses
473 and are not available for the register allocator.
474 On the 68000, only the stack pointer is such. */
476 #define FIXED_REGISTERS \
477 {/* Data registers. */ \
478 0, 0, 0, 0, 0, 0, 0, 0, \
480 /* Address registers. */ \
481 0, 0, 0, 0, 0, 0, 0, 1, \
483 /* Floating point registers \
485 0, 0, 0, 0, 0, 0, 0, 0 }
487 /* 1 for registers not available across function calls.
488 These must include the FIXED_REGISTERS and also any
489 registers that can be used without being saved.
490 The latter must include the registers where values are returned
491 and the register where structure-value addresses are passed.
492 Aside from that, you can include as many other registers as you like. */
493 #define CALL_USED_REGISTERS \
494 {1, 1, 0, 0, 0, 0, 0, 0, \
495 1, 1, 0, 0, 0, 0, 0, 1, \
496 1, 1, 0, 0, 0, 0, 0, 0 }
499 /* Make sure everything's fine if we *don't* have a given processor.
500 This assumes that putting a register in fixed_regs will keep the
501 compiler's mitts completely off it. We don't bother to zero it out
502 of register classes. */
504 #define CONDITIONAL_REGISTER_USAGE \
508 if (! TARGET_68881) \
510 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
511 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
512 if (TEST_HARD_REG_BIT (x, i)) \
513 fixed_regs[i] = call_used_regs[i] = 1; \
515 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
516 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
517 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
520 /* Return number of consecutive hard regs needed starting at reg REGNO
521 to hold something of mode MODE.
522 This is ordinarily the length in words of a value of mode MODE
523 but can be less for certain modes in special long registers.
525 On the 68000, ordinary registers hold 32 bits worth;
526 for the 68881 registers, a single register is always enough for
527 anything that can be stored in them at all. */
528 #define HARD_REGNO_NREGS(REGNO, MODE) \
529 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
530 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
532 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
533 On the 68000, the cpu registers can hold any mode but the 68881 registers
534 can hold only SFmode or DFmode. */
536 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
538 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
539 || ((REGNO) >= 16 && (REGNO) < 24 \
540 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
541 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
542 && GET_MODE_UNIT_SIZE (MODE) <= 12))
545 /* Value is 1 if it is a good idea to tie two pseudo registers
546 when one has mode MODE1 and one has mode MODE2.
547 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
548 for any hard reg, then this must be 0 for correct output. */
549 #define MODES_TIEABLE_P(MODE1, MODE2) \
551 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
552 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
553 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
554 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
556 /* Specify the registers used for certain standard purposes.
557 The values of these macros are register numbers. */
559 /* m68000 pc isn't overloaded on a register. */
560 /* #define PC_REGNUM */
562 /* Register to use for pushing function arguments. */
563 #define STACK_POINTER_REGNUM 15
565 /* Base register for access to local variables of the function. */
566 #define FRAME_POINTER_REGNUM 14
568 /* Value should be nonzero if functions must have frame pointers.
569 Zero means the frame pointer need not be set up (and parms
570 may be accessed via the stack pointer) in functions that seem suitable.
571 This is computed in `reload', in reload1.c. */
572 #define FRAME_POINTER_REQUIRED 0
574 /* Base register for access to arguments of the function.
575 * This isn't a hardware register. It will be eliminated to the
576 * stack pointer or frame pointer.
578 #define ARG_POINTER_REGNUM 24
580 /* Register in which static-chain is passed to a function. */
581 #define STATIC_CHAIN_REGNUM 8
583 /* Register in which address to store a structure value
584 is passed to a function. */
585 #define STRUCT_VALUE_REGNUM 9
587 /* Define the classes of registers for register constraints in the
588 machine description. Also define ranges of constants.
590 One of the classes must always be named ALL_REGS and include all hard regs.
591 If there is more than one class, another class must be named NO_REGS
592 and contain no registers.
594 The name GENERAL_REGS must be the name of a class (or an alias for
595 another name such as ALL_REGS). This is the class of registers
596 that is allowed by "g" or "r" in a register constraint.
597 Also, registers outside this class are allocated only when
598 instructions express preferences for them.
600 The classes must be numbered in nondecreasing order; that is,
601 a larger-numbered class must never be contained completely
602 in a smaller-numbered class.
604 For any two classes, it is very desirable that there be another
605 class that represents their union. */
607 /* The 68000 has three kinds of registers, so eight classes would be
608 a complete set. One of them is not needed. */
613 GENERAL_REGS, DATA_OR_FP_REGS,
614 ADDR_OR_FP_REGS, ALL_REGS,
617 #define N_REG_CLASSES (int) LIM_REG_CLASSES
619 /* Give names of register classes as strings for dump file. */
621 #define REG_CLASS_NAMES \
622 { "NO_REGS", "DATA_REGS", \
623 "ADDR_REGS", "FP_REGS", \
624 "GENERAL_REGS", "DATA_OR_FP_REGS", \
625 "ADDR_OR_FP_REGS", "ALL_REGS" }
627 /* Define which registers fit in which classes.
628 This is an initializer for a vector of HARD_REG_SET
629 of length N_REG_CLASSES. */
631 #define REG_CLASS_CONTENTS \
633 {0x00000000}, /* NO_REGS */ \
634 {0x000000ff}, /* DATA_REGS */ \
635 {0x0000ff00}, /* ADDR_REGS */ \
636 {0x00ff0000}, /* FP_REGS */ \
637 {0x0000ffff}, /* GENERAL_REGS */ \
638 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
639 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
640 {0x00ffffff}, /* ALL_REGS */ \
643 /* The same information, inverted:
644 Return the class number of the smallest class containing
645 reg number REGNO. This could be a conditional expression
646 or could index an array. */
648 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
650 /* The class value for index registers, and the one for base regs. */
652 #define INDEX_REG_CLASS GENERAL_REGS
653 #define BASE_REG_CLASS ADDR_REGS
655 /* Get reg_class from a letter such as appears in the machine description.
656 We do a trick here to modify the effective constraints on the
657 machine description; we zorch the constraint letters that aren't
658 appropriate for a specific target. This allows us to guarantee
659 that a specific kind of register will not be used for a given target
660 without fiddling with the register classes above. */
662 #define REG_CLASS_FROM_LETTER(C) \
663 ((C) == 'a' ? ADDR_REGS : \
664 ((C) == 'd' ? DATA_REGS : \
665 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
669 /* The letters I, J, K, L and M in a register constraint string
670 can be used to stand for particular ranges of immediate operands.
671 This macro defines what the ranges are.
672 C is the letter, and VALUE is a constant value.
673 Return 1 if VALUE is in the range specified by C.
675 For the 68000, `I' is used for the range 1 to 8
676 allowed as immediate shift counts and in addq.
677 `J' is used for the range of signed numbers that fit in 16 bits.
678 `K' is for numbers that moveq can't handle.
679 `L' is for range -8 to -1, range of values that can be added with subq.
680 `M' is for numbers that moveq+notb can't handle.
681 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
682 'O' is for 16 (for rotate using swap).
683 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
685 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
686 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
687 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
688 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
689 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
690 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
691 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
692 (C) == 'O' ? (VALUE) == 16 : \
693 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
696 * A small bit of explanation:
697 * "G" defines all of the floating constants that are *NOT* 68881
698 * constants. this is so 68881 constants get reloaded and the
701 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
702 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
704 /* A C expression that defines the optional machine-dependent constraint
705 letters that can be used to segregate specific types of operands,
706 usually memory references, for the target machine. It should return 1 if
707 VALUE corresponds to the operand type represented by the constraint letter
708 C. If C is not defined as an extra constraint, the value returned should
709 be 0 regardless of VALUE. */
711 /* Letters in the range `Q' through `U' may be defined in a
712 machine-dependent fashion to stand for arbitrary operand types.
713 The machine description macro `EXTRA_CONSTRAINT' is passed the
714 operand as its first argument and the constraint letter as its
717 `Q' means address register indirect addressing mode.
718 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
719 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
721 #define EXTRA_CONSTRAINT(OP,CODE) \
724 && GET_CODE (OP) == MEM \
725 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
726 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
727 || GET_CODE (XEXP (OP, 0)) == CONST)) \
731 && (GET_CODE (OP) == SYMBOL_REF \
732 || GET_CODE (OP) == LABEL_REF \
733 || GET_CODE (OP) == CONST)) \
736 ? (GET_CODE (OP) == MEM \
737 && GET_CODE (XEXP (OP, 0)) == REG) \
741 /* Given an rtx X being reloaded into a reg required to be
742 in class CLASS, return the class of reg to actually use.
743 In general this is just CLASS; but on some machines
744 in some cases it is preferable to use a more restrictive class.
745 On the 68000 series, use a data reg if possible when the
746 value is a constant in the range where moveq could be used
747 and we ensure that QImodes are reloaded into data regs. */
749 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
750 ((GET_CODE (X) == CONST_INT \
751 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
752 && (CLASS) != ADDR_REGS) \
754 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
756 : (GET_CODE (X) == CONST_DOUBLE \
757 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
758 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
759 ? FP_REGS : NO_REGS) \
761 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
762 || GET_CODE (X) == LABEL_REF)) \
766 /* Force QImode output reloads from subregs to be allocated to data regs,
767 since QImode stores from address regs are not supported. We make the
768 assumption that if the class is not ADDR_REGS, then it must be a superset
771 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
772 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
776 /* Return the maximum number of consecutive registers
777 needed to represent mode MODE in a register of class CLASS. */
778 /* On the 68000, this is the size of MODE in words,
779 except in the FP regs, where a single reg is always enough. */
780 #define CLASS_MAX_NREGS(CLASS, MODE) \
781 ((CLASS) == FP_REGS ? 1 \
782 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
784 /* Moves between fp regs and other regs are two insns. */
785 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
786 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
787 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
790 /* Stack layout; function entry, exit and calling. */
792 /* Define this if pushing a word on the stack
793 makes the stack pointer a smaller address. */
794 #define STACK_GROWS_DOWNWARD
796 /* Define this if the nominal address of the stack frame
797 is at the high-address end of the local variables;
798 that is, each additional local variable allocated
799 goes at a more negative offset in the frame. */
800 #define FRAME_GROWS_DOWNWARD
802 /* Offset within stack frame to start allocating local variables at.
803 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
804 first local allocated. Otherwise, it is the offset to the BEGINNING
805 of the first local allocated. */
806 #define STARTING_FRAME_OFFSET 0
808 /* If we generate an insn to push BYTES bytes,
809 this says how many the stack pointer really advances by.
810 On the 68000, sp@- in a byte insn really pushes a word.
811 On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */
812 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
814 /* We want to avoid trying to push bytes. */
815 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
816 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
817 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
819 /* Offset of first parameter from the argument pointer register value. */
820 #define FIRST_PARM_OFFSET(FNDECL) 8
822 /* Value is the number of byte of arguments automatically
823 popped when returning from a subroutine call.
824 FUNDECL is the declaration node of the function (as a tree),
825 FUNTYPE is the data type of the function (as a tree),
826 or for a library call it is an identifier node for the subroutine name.
827 SIZE is the number of bytes of arguments passed on the stack.
829 On the 68000, the RTS insn cannot pop anything.
830 On the 68010, the RTD insn may be used to pop them if the number
831 of args is fixed, but if the number is variable then the caller
832 must pop them all. RTD can't be used for library calls now
833 because the library is compiled with the Unix compiler.
834 Use of RTD is a selectable option, since it is incompatible with
835 standard Unix calling sequences. If the option is not selected,
836 the caller must always pop the args. */
838 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
839 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
840 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
841 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
842 == void_type_node))) \
845 /* Define how to find the value returned by a function.
846 VALTYPE is the data type of the value (as a tree).
847 If the precise function being called is known, FUNC is its FUNCTION_DECL;
848 otherwise, FUNC is 0. */
850 /* On the 68000 the return value is in D0 regardless. */
852 #define FUNCTION_VALUE(VALTYPE, FUNC) \
853 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
855 /* Define how to find the value returned by a library function
856 assuming the value has mode MODE. */
858 /* On the 68000 the return value is in D0 regardless. */
860 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
862 /* 1 if N is a possible register number for a function value.
863 On the 68000, d0 is the only register thus used. */
865 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
867 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
868 more than one register. */
870 #define NEEDS_UNTYPED_CALL 0
872 /* Define this if PCC uses the nonreentrant convention for returning
873 structure and union values. */
875 #define PCC_STATIC_STRUCT_RETURN
877 /* 1 if N is a possible register number for function argument passing.
878 On the 68000, no registers are used in this way. */
880 #define FUNCTION_ARG_REGNO_P(N) 0
882 /* Define a data type for recording info about an argument list
883 during the scan of that argument list. This data type should
884 hold all necessary information about the function itself
885 and about the args processed so far, enough to enable macros
886 such as FUNCTION_ARG to determine where the next arg should go.
888 On the m68k, this is a single integer, which is a number of bytes
889 of arguments scanned so far. */
891 #define CUMULATIVE_ARGS int
893 /* Initialize a variable CUM of type CUMULATIVE_ARGS
894 for a call to a function whose data type is FNTYPE.
895 For a library call, FNTYPE is 0.
897 On the m68k, the offset starts at 0. */
899 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
902 /* Update the data in CUM to advance over an argument
903 of mode MODE and data type TYPE.
904 (TYPE is null for libcalls where that information may not be available.) */
906 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
907 ((CUM) += ((MODE) != BLKmode \
908 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
909 : (int_size_in_bytes (TYPE) + 3) & ~3))
911 /* Define where to put the arguments to a function.
912 Value is zero to push the argument on the stack,
913 or a hard register in which to store the argument.
915 MODE is the argument's machine mode.
916 TYPE is the data type of the argument (as a tree).
917 This is null for libcalls where that information may
919 CUM is a variable of type CUMULATIVE_ARGS which gives info about
920 the preceding args and about the function being called.
921 NAMED is nonzero if this argument is a named parameter
922 (otherwise it is an extra parameter matching an ellipsis).
924 On the m68k all args are always pushed. */
926 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
928 /* For an arg passed partly in registers and partly in memory,
929 this is the number of registers used.
930 For args passed entirely in registers or entirely in memory, zero. */
932 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
934 /* Output assembler code to FILE to increment profiler label # LABELNO
935 for profiling a function entry. */
937 #define FUNCTION_PROFILER(FILE, LABELNO) \
938 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
940 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
941 the stack pointer does not matter. The value is tested only in
942 functions that have frame pointers.
943 No definition is equivalent to always zero. */
945 #define EXIT_IGNORE_STACK 1
947 /* This is a hook for other tm files to change. */
948 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
950 /* Determine if the epilogue should be output as RTL.
951 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
952 #define USE_RETURN_INSN use_return_insn ()
954 /* Output assembler code for a block containing the constant parts
955 of a trampoline, leaving space for the variable parts. */
957 /* On the 68k, the trampoline looks like this:
961 WARNING: Targets that may run on 68040+ cpus must arrange for
962 the instruction cache to be flushed. Previous incarnations of
963 the m68k trampoline code attempted to get around this by either
964 using an out-of-line transfer function or pc-relative data, but
965 the fact remains that the code to jump to the transfer function
966 or the code to load the pc-relative data needs to be flushed
967 just as much as the "variable" portion of the trampoline.
968 Recognizing that a cache flush is going to be required anyway,
969 dispense with such notions and build a smaller trampoline. */
971 /* Since more instructions are required to move a template into
972 place than to create it on the spot, don't use a template. */
974 /* Length in units of the trampoline for entering a nested function. */
976 #define TRAMPOLINE_SIZE 12
978 /* Alignment required for a trampoline in bits. */
980 #define TRAMPOLINE_ALIGNMENT 16
982 /* Targets redefine this to invoke code to either flush the cache,
983 or enable stack execution (or both). */
985 #ifndef FINALIZE_TRAMPOLINE
986 #define FINALIZE_TRAMPOLINE(TRAMP)
989 /* Emit RTL insns to initialize the variable parts of a trampoline.
990 FNADDR is an RTX for the address of the function's pure code.
991 CXT is an RTX for the static chain value for the function.
993 We generate a two-instructions program at address TRAMP :
997 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
999 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1000 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1001 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1003 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1004 FINALIZE_TRAMPOLINE(TRAMP); \
1007 /* This is the library routine that is used
1008 to transfer control from the trampoline
1009 to the actual nested function.
1010 It is defined for backward compatibility,
1011 for linking with object code that used the old
1012 trampoline definition. */
1014 /* A colon is used with no explicit operands
1015 to cause the template string to be scanned for %-constructs. */
1016 /* The function name __transfer_from_trampoline is not actually used.
1017 The function definition just permits use of "asm with operands"
1018 (though the operand list is empty). */
1019 #define TRANSFER_FROM_TRAMPOLINE \
1021 __transfer_from_trampoline () \
1023 register char *a0 asm ("%a0"); \
1024 asm (GLOBAL_ASM_OP "___trampoline"); \
1025 asm ("___trampoline:"); \
1026 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1027 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1031 /* Definitions for register eliminations.
1033 This is an array of structures. Each structure initializes one pair
1034 of eliminable registers. The "from" register number is given first,
1035 followed by "to". Eliminations of the same "from" register are listed
1036 in order of preference.
1038 There are two registers that can always be eliminated on the m68k.
1039 The frame pointer and the arg pointer can be replaced by either the
1040 hard frame pointer or to the stack pointer, depending upon the
1041 circumstances. The hard frame pointer is not used before reload and
1042 so it is not eligible for elimination. */
1044 #define ELIMINABLE_REGS \
1045 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1046 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
1047 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1049 /* Given FROM and TO register numbers, say whether this elimination is
1050 allowed. Frame pointer elimination is automatically handled.
1052 All other eliminations are valid. */
1054 #define CAN_ELIMINATE(FROM, TO) \
1055 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1057 /* Define the offset between two registers, one to be eliminated, and the other
1058 its replacement, at the start of a routine. */
1060 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1061 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1063 /* Addressing modes, and classification of registers for them. */
1065 #define HAVE_POST_INCREMENT 1
1067 #define HAVE_PRE_DECREMENT 1
1069 /* Macros to check register numbers against specific register classes. */
1071 /* These assume that REGNO is a hard or pseudo reg number.
1072 They give nonzero only if REGNO is a hard reg of the suitable class
1073 or a pseudo reg currently allocated to a suitable hard reg.
1074 Since they use reg_renumber, they are safe only once reg_renumber
1075 has been allocated, which happens in local-alloc.c. */
1077 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1078 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1079 #define REGNO_OK_FOR_BASE_P(REGNO) \
1080 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1081 #define REGNO_OK_FOR_DATA_P(REGNO) \
1082 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1083 #define REGNO_OK_FOR_FP_P(REGNO) \
1084 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1086 /* Now macros that check whether X is a register and also,
1087 strictly, whether it is in a specified class.
1089 These macros are specific to the 68000, and may be used only
1090 in code for printing assembler insns and in conditions for
1091 define_optimization. */
1093 /* 1 if X is a data register. */
1095 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1097 /* 1 if X is an fp register. */
1099 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1101 /* 1 if X is an address register */
1103 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1105 /* Maximum number of registers that can appear in a valid memory address. */
1107 #define MAX_REGS_PER_ADDRESS 2
1109 /* Recognize any constant value that is a valid address. */
1111 #define CONSTANT_ADDRESS_P(X) \
1112 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1113 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1114 || GET_CODE (X) == HIGH)
1116 /* Nonzero if the constant value X is a legitimate general operand.
1117 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1119 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1121 /* Nonzero if the constant value X is a legitimate general operand
1122 when generating PIC code. It is given that flag_pic is on and
1123 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1125 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1126 accepted by insn predicates, but which would otherwise fail the
1127 `general_operand' test. */
1129 #ifndef REG_OK_STRICT
1130 #define PCREL_GENERAL_OPERAND_OK 0
1132 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1135 #define LEGITIMATE_PIC_OPERAND_P(X) \
1136 (! symbolic_operand (X, VOIDmode) \
1137 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1138 || PCREL_GENERAL_OPERAND_OK)
1140 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1141 and check its validity for a certain class.
1142 We have two alternate definitions for each of them.
1143 The usual definition accepts all pseudo regs; the other rejects
1144 them unless they have been allocated suitable hard regs.
1145 The symbol REG_OK_STRICT causes the latter definition to be used.
1147 Most source files want to accept pseudo regs in the hope that
1148 they will get allocated to the class that the insn wants them to be in.
1149 Source files for reload pass need to be strict.
1150 After reload, it makes no difference, since pseudo regs have
1151 been eliminated by then. */
1153 #ifndef REG_OK_STRICT
1155 /* Nonzero if X is a hard reg that can be used as an index
1156 or if it is a pseudo reg. */
1157 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1158 /* Nonzero if X is a hard reg that can be used as a base reg
1159 or if it is a pseudo reg. */
1160 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1164 /* Nonzero if X is a hard reg that can be used as an index. */
1165 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1166 /* Nonzero if X is a hard reg that can be used as a base reg. */
1167 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1171 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1172 that is a valid memory address for an instruction.
1173 The MODE argument is the machine mode for the MEM expression
1174 that wants to use this address.
1176 When generating PIC, an address involving a SYMBOL_REF is legitimate
1177 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1178 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1179 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1181 Likewise for a LABEL_REF when generating PIC.
1183 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1185 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1186 also makes function inlining work when inline functions are called with
1187 arguments that are SUBREGs. */
1189 #define LEGITIMATE_BASE_REG_P(X) \
1190 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1191 || (GET_CODE (X) == SUBREG \
1192 && GET_CODE (SUBREG_REG (X)) == REG \
1193 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1195 #define INDIRECTABLE_1_ADDRESS_P(X) \
1196 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1197 || LEGITIMATE_BASE_REG_P (X) \
1198 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1199 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1200 || (GET_CODE (X) == PLUS \
1201 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1202 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1204 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1205 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1206 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1207 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1208 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1210 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1211 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1213 /* Only labels on dispatch tables are valid for indexing from. */
1214 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1216 if (GET_CODE (X) == LABEL_REF \
1217 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1218 && GET_CODE (temp) == JUMP_INSN \
1219 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1220 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1222 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1224 #define GO_IF_INDEXING(X, ADDR) \
1225 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1226 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1227 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1228 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1230 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1231 { GO_IF_INDEXING (X, ADDR); \
1232 if (GET_CODE (X) == PLUS) \
1233 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1234 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1235 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1236 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1237 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1238 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1240 /* ColdFire/5200 does not allow HImode index registers. */
1241 #define LEGITIMATE_INDEX_REG_P(X) \
1242 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1243 || (! TARGET_COLDFIRE \
1244 && GET_CODE (X) == SIGN_EXTEND \
1245 && GET_CODE (XEXP (X, 0)) == REG \
1246 && GET_MODE (XEXP (X, 0)) == HImode \
1247 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1248 || (GET_CODE (X) == SUBREG \
1249 && GET_CODE (SUBREG_REG (X)) == REG \
1250 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1252 #define LEGITIMATE_INDEX_P(X) \
1253 (LEGITIMATE_INDEX_REG_P (X) \
1254 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1255 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1256 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1257 && (INTVAL (XEXP (X, 1)) == 2 \
1258 || INTVAL (XEXP (X, 1)) == 4 \
1259 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1261 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1262 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1263 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1264 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1265 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1266 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1267 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1270 /* Don't call memory_address_noforce for the address to fetch
1271 the switch offset. This address is ok as it stands (see above),
1272 but memory_address_noforce would alter it. */
1273 #define PIC_CASE_VECTOR_ADDRESS(index) index
1275 /* Try machine-dependent ways of modifying an illegitimate address
1276 to be legitimate. If we find one, return the new, valid address.
1277 This macro is used in only one place: `memory_address' in explow.c.
1279 OLDX is the address as it was before break_out_memory_refs was called.
1280 In some cases it is useful to look at this to decide what needs to be done.
1282 MODE and WIN are passed so that this macro can use
1283 GO_IF_LEGITIMATE_ADDRESS.
1285 It is always safe for this macro to do nothing. It exists to recognize
1286 opportunities to optimize the output.
1288 For the 68000, we handle X+REG by loading X into a register R and
1289 using R+REG. R will go in an address reg and indexing will be used.
1290 However, if REG is a broken-out memory address or multiplication,
1291 nothing needs to be done because REG can certainly go in an address reg. */
1293 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1294 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1295 { register int ch = (X) != (OLDX); \
1296 if (GET_CODE (X) == PLUS) \
1298 if (GET_CODE (XEXP (X, 0)) == MULT) \
1299 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1300 if (GET_CODE (XEXP (X, 1)) == MULT) \
1301 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1302 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1303 && GET_CODE (XEXP (X, 0)) == REG) \
1305 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1306 if (GET_CODE (XEXP (X, 0)) == REG \
1307 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1308 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1309 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1310 { register rtx temp = gen_reg_rtx (Pmode); \
1311 register rtx val = force_operand (XEXP (X, 1), 0); \
1312 emit_move_insn (temp, val); \
1314 XEXP (X, 1) = temp; \
1316 else if (GET_CODE (XEXP (X, 1)) == REG \
1317 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1318 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1319 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1320 { register rtx temp = gen_reg_rtx (Pmode); \
1321 register rtx val = force_operand (XEXP (X, 0), 0); \
1322 emit_move_insn (temp, val); \
1324 XEXP (X, 0) = temp; \
1327 /* Go to LABEL if ADDR (a legitimate address expression)
1328 has an effect that depends on the machine mode it is used for.
1329 On the 68000, only predecrement and postincrement address depend thus
1330 (the amount of decrement or increment being the length of the operand). */
1332 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1333 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1335 /* Specify the machine mode that this machine uses
1336 for the index in the tablejump instruction. */
1337 #define CASE_VECTOR_MODE HImode
1339 /* Define as C expression which evaluates to nonzero if the tablejump
1340 instruction expects the table to contain offsets from the address of the
1342 Do not define this if the table should contain absolute addresses. */
1343 #define CASE_VECTOR_PC_RELATIVE 1
1345 /* Define this as 1 if `char' should by default be signed; else as 0. */
1346 #define DEFAULT_SIGNED_CHAR 1
1348 /* Don't cse the address of the function being compiled. */
1349 #define NO_RECURSIVE_FUNCTION_CSE
1351 /* Max number of bytes we can move from memory to memory
1352 in one reasonably fast instruction. */
1355 /* Nonzero if access to memory by bytes is slow and undesirable. */
1356 #define SLOW_BYTE_ACCESS 0
1358 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1359 is done just by pretending it is already truncated. */
1360 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1362 /* We assume that the store-condition-codes instructions store 0 for false
1363 and some other value for true. This is the value stored for true. */
1365 #define STORE_FLAG_VALUE (-1)
1367 /* When a prototype says `char' or `short', really pass an `int'. */
1368 #define PROMOTE_PROTOTYPES 1
1370 /* Specify the machine mode that pointers have.
1371 After generation of rtl, the compiler makes no further distinction
1372 between pointers and any other objects of this machine mode. */
1373 #define Pmode SImode
1375 /* A function address in a call instruction
1376 is a byte address (for indexing purposes)
1377 so give the MEM rtx a byte's mode. */
1378 #define FUNCTION_MODE QImode
1381 /* Tell final.c how to eliminate redundant test instructions. */
1383 /* Here we define machine-dependent flags and fields in cc_status
1384 (see `conditions.h'). */
1386 /* Set if the cc value is actually in the 68881, so a floating point
1387 conditional branch must be output. */
1388 #define CC_IN_68881 04000
1390 /* Store in cc_status the expressions that the condition codes will
1391 describe after execution of an instruction whose pattern is EXP.
1392 Do not alter them if the instruction would not alter the cc's. */
1394 /* On the 68000, all the insns to store in an address register fail to
1395 set the cc's. However, in some cases these instructions can make it
1396 possibly invalid to use the saved cc's. In those cases we clear out
1397 some or all of the saved cc's so they won't be used. */
1399 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1401 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1402 { if (cc_prev_status.flags & CC_IN_68881) \
1404 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1408 /* Control the assembler format that we output. */
1410 /* Output to assembler file text saying following lines
1411 may contain character constants, extra white space, comments, etc. */
1413 #define ASM_APP_ON "#APP\n"
1415 /* Output to assembler file text saying following lines
1416 no longer contain unusual constructs. */
1418 #define ASM_APP_OFF "#NO_APP\n"
1420 /* Output before read-only data. */
1422 #define TEXT_SECTION_ASM_OP "\t.text"
1424 /* Output before writable data. */
1426 #define DATA_SECTION_ASM_OP "\t.data"
1428 #define GLOBAL_ASM_OP "\t.globl\t"
1430 /* Here are four prefixes that are used by asm_fprintf to
1431 facilitate customization for alternate assembler syntaxes.
1432 Machines with no likelihood of an alternate syntax need not
1433 define these and need not use asm_fprintf. */
1435 /* The prefix for register names. Note that REGISTER_NAMES
1436 is supposed to include this prefix. */
1438 #define REGISTER_PREFIX ""
1440 /* The prefix for local labels. You should be able to define this as
1441 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1442 without having to make any other changes to account for the specific
1443 definition. Note it is a string literal, not interpreted by printf
1446 #define LOCAL_LABEL_PREFIX ""
1448 /* The prefix to add to user-visible assembler symbols. */
1450 #define USER_LABEL_PREFIX "_"
1452 /* The prefix for immediate operands. */
1454 #define IMMEDIATE_PREFIX "#"
1456 /* How to refer to registers in assembler output.
1457 This sequence is indexed by compiler's hard-register-number (see above). */
1459 #define REGISTER_NAMES \
1460 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1461 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1462 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" }
1464 /* How to renumber registers for dbx and gdb.
1465 On the Sun-3, the floating point registers have numbers
1466 18 to 25, not 16 to 23 as they do in the compiler. */
1468 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1470 /* Before the prologue, RA is at 0(%sp). */
1471 #define INCOMING_RETURN_ADDR_RTX \
1472 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1474 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1475 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1476 Instead use the identity mapping. */
1477 #define DWARF_FRAME_REGNUM(REG) REG
1479 /* Before the prologue, the top of the frame is at 4(%sp). */
1480 #define INCOMING_FRAME_SP_OFFSET 4
1482 /* Describe how we implement __builtin_eh_return. */
1483 #define EH_RETURN_DATA_REGNO(N) \
1484 ((N) < 2 ? (N) : INVALID_REGNUM)
1485 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1486 #define EH_RETURN_HANDLER_RTX \
1487 gen_rtx_MEM (Pmode, \
1488 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1489 plus_constant (EH_RETURN_STACKADJ_RTX, \
1492 /* Select a format to encode pointers in exception handling data. CODE
1493 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1494 true if the symbol may be affected by dynamic relocations. */
1495 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1497 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1500 /* This is how to output a reference to a user-level label named NAME.
1501 `assemble_name' uses this. */
1503 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1504 asm_fprintf (FILE, "%U%s", NAME)
1506 /* This is how to store into the string LABEL
1507 the symbol_ref name of an internal numbered label where
1508 PREFIX is the class of label and NUM is the number within the class.
1509 This is suitable for output with `assemble_name'. */
1511 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1512 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1514 /* This is how to output an insn to push a register on the stack.
1515 It need not be very fast code. */
1517 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1518 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1520 /* This is how to output an insn to pop a register from the stack.
1521 It need not be very fast code. */
1523 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1524 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1526 /* This is how to output an element of a case-vector that is absolute.
1527 (The 68000 does not use such vectors,
1528 but we must define this macro anyway.) */
1530 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1531 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1533 /* This is how to output an element of a case-vector that is relative. */
1535 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1536 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1538 /* This is how to output an assembler line
1539 that says to advance the location counter
1540 to a multiple of 2**LOG bytes. */
1542 /* We don't have a way to align to more than a two-byte boundary, so do the
1543 best we can and don't complain. */
1544 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1546 fprintf (FILE, "\t.even\n");
1548 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1549 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1551 /* This says how to output an assembler line
1552 to define a global common symbol. */
1554 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1555 ( fputs (".comm ", (FILE)), \
1556 assemble_name ((FILE), (NAME)), \
1557 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1559 /* This says how to output an assembler line
1560 to define a local common symbol. */
1562 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1563 ( fputs (".lcomm ", (FILE)), \
1564 assemble_name ((FILE), (NAME)), \
1565 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1567 /* Output a float value (represented as a C double) as an immediate operand.
1568 This macro is a 68k-specific macro. */
1570 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1575 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1576 asm_fprintf ((FILE), "%I0r%s", dstr); \
1581 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1582 asm_fprintf ((FILE), "%I0x%lx", l); \
1586 /* Output a double value (represented as a C double) as an immediate operand.
1587 This macro is a 68k-specific macro. */
1588 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1589 do { char dstr[30]; \
1590 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1591 asm_fprintf (FILE, "%I0r%s", dstr); \
1594 /* Note, long double immediate operands are not actually
1595 generated by m68k.md. */
1596 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1597 do { char dstr[30]; \
1598 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1599 asm_fprintf (FILE, "%I0r%s", dstr); \
1602 /* Print operand X (an rtx) in assembler syntax to file FILE.
1603 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1604 For `%' followed by punctuation, CODE is the punctuation and X is null.
1606 On the 68000, we use several CODE characters:
1607 '.' for dot needed in Motorola-style opcode names.
1608 '-' for an operand pushing on the stack:
1609 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1610 '+' for an operand pushing on the stack:
1611 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1612 '@' for a reference to the top word on the stack:
1613 sp@, (sp) or (%sp) depending on the style of syntax.
1614 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1615 but & in SGS syntax).
1616 '!' for the fpcr register (used in some float-to-fixed conversions).
1617 '$' for the letter `s' in an op code, but only on the 68040.
1618 '&' for the letter `d' in an op code, but only on the 68040.
1619 '/' for register prefix needed by longlong.h.
1621 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1622 'd' to force memory addressing to be absolute, not relative.
1623 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1624 'o' for operands to go directly to output_operand_address (bypassing
1625 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1626 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1627 or print pair of registers as rx:ry. */
1629 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1630 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1631 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1632 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1634 /* A C compound statement to output to stdio stream STREAM the
1635 assembler syntax for an instruction operand X. X is an RTL
1638 CODE is a value that can be used to specify one of several ways
1639 of printing the operand. It is used when identical operands
1640 must be printed differently depending on the context. CODE
1641 comes from the `%' specification that was used to request
1642 printing of the operand. If the specification was just `%DIGIT'
1643 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1644 is the ASCII code for LTR.
1646 If X is a register, this macro should print the register's name.
1647 The names can be found in an array `reg_names' whose type is
1648 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1650 When the machine description has a specification `%PUNCT' (a `%'
1651 followed by a punctuation character), this macro is called with
1652 a null pointer for X and the punctuation character for CODE.
1654 See m68k.c for the m68k specific codes. */
1656 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1658 /* A C compound statement to output to stdio stream STREAM the
1659 assembler syntax for an instruction operand that is a memory
1660 reference whose address is ADDR. ADDR is an RTL expression. */
1662 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1664 /* Variables in m68k.c */
1665 extern const char *m68k_align_loops_string;
1666 extern const char *m68k_align_jumps_string;
1667 extern const char *m68k_align_funcs_string;
1668 extern const char *m68k_library_id_string;
1669 extern int m68k_align_loops;
1670 extern int m68k_align_jumps;
1671 extern int m68k_align_funcs;
1672 extern int m68k_last_compare_had_fp_operands;
1675 /* Define the codes that are matched by predicates in m68k.c. */
1677 #define PREDICATE_CODES \
1678 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1679 LABEL_REF, SUBREG, REG, MEM}}, \
1680 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1681 {"memory_src_operand", {SUBREG, MEM}}, \
1682 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1683 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1684 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1685 {"const_sint32_operand", {CONST_INT}}, \
1686 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1688 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},