1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Note that some other tm.h files include this one and then override
36 many of the definitions that relate to assembler syntax. */
38 /* Target CPU builtins. */
39 #define TARGET_CPU_CPP_BUILTINS() \
42 builtin_define ("__m68k__"); \
43 builtin_define_std ("mc68000"); \
44 if (TARGET_68040_ONLY) \
47 builtin_define_std ("mc68060"); \
49 builtin_define_std ("mc68040"); \
51 else if (TARGET_68060) /* -m68020-60 */ \
53 builtin_define_std ("mc68060"); \
54 builtin_define_std ("mc68040"); \
55 builtin_define_std ("mc68030"); \
56 builtin_define_std ("mc68020"); \
58 else if (TARGET_68040) /* -m68020-40 */ \
60 builtin_define_std ("mc68040"); \
61 builtin_define_std ("mc68030"); \
62 builtin_define_std ("mc68020"); \
64 else if (TARGET_68030) \
65 builtin_define_std ("mc68030"); \
66 else if (TARGET_68020) \
67 builtin_define_std ("mc68020"); \
69 builtin_define ("__HAVE_68881__"); \
72 builtin_define_std ("mc68332"); \
73 builtin_define_std ("mcpu32"); \
75 if (TARGET_COLDFIRE) \
76 builtin_define ("__mcoldfire__"); \
78 builtin_define ("__mcf5200__"); \
81 builtin_define ("__mcf528x__"); \
82 builtin_define ("__mcf5200__"); \
86 builtin_define ("__mcf5300__"); \
87 builtin_define ("__mcf5307__"); \
91 builtin_define ("__mcf5400__"); \
92 builtin_define ("__mcf5407__"); \
94 if (TARGET_CF_HWDIV) \
95 builtin_define ("__mcfhwdiv__"); \
98 builtin_define ("__pic__"); \
100 builtin_define ("__PIC__"); \
102 builtin_assert ("cpu=m68k"); \
103 builtin_assert ("machine=m68k"); \
107 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
109 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
110 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
111 #define INT_OP_NO_DOT 2 /* byte, short, long */
112 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
114 /* Set the default */
115 #define INT_OP_GROUP INT_OP_DOT_WORD
117 /* Run-time compilation parameters selecting different hardware subsets. */
119 extern int target_flags;
121 /* Macros used in the machine description to test the flags. */
123 /* Compile for a 68020 (not a 68000 or 68010). */
124 #define MASK_68020 (1<<0)
125 #define TARGET_68020 (target_flags & MASK_68020)
127 /* Compile for a 68030. This does not really make a difference in GCC,
128 it just enables the __mc68030__ predefine. */
129 #define MASK_68030 (1<<1)
130 #define TARGET_68030 (target_flags & MASK_68030)
132 /* Optimize for 68040, but still allow execution on 68020
133 (-m68020-40 or -m68040).
134 The 68040 will execute all 68030 and 68881/2 instructions, but some
135 of them must be emulated in software by the OS. When TARGET_68040 is
136 turned on, these instructions won't be used. This code will still
137 run on a 68030 and 68881/2. */
138 #define MASK_68040 (1<<2)
139 #define TARGET_68040 (target_flags & MASK_68040)
141 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
142 #define MASK_68040_ONLY (1<<3)
143 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
145 /* Optimize for 68060, but still allow execution on 68020
146 (-m68020-60 or -m68060).
147 The 68060 will execute all 68030 and 68881/2 instructions, but some
148 of them must be emulated in software by the OS. When TARGET_68060 is
149 turned on, these instructions won't be used. This code will still
150 run on a 68030 and 68881/2. */
151 #define MASK_68060 (1<<4)
152 #define TARGET_68060 (target_flags & MASK_68060)
154 /* Compile for mcf5200 */
155 #define MASK_5200 (1<<5)
156 #define TARGET_5200 (target_flags & MASK_5200)
158 /* Build for ColdFire v3 */
159 #define MASK_CFV3 (1<<6)
160 #define TARGET_CFV3 (target_flags & MASK_CFV3)
162 /* Build for ColdFire v4 */
163 #define MASK_CFV4 (1<<7)
164 #define TARGET_CFV4 (target_flags & MASK_CFV4)
166 /* Compile for ColdFire 528x */
167 #define MASK_528x (1<<8)
168 #define TARGET_528x (target_flags & MASK_528x)
170 /* Divide support for ColdFire */
171 #define MASK_CF_HWDIV (1<<9)
172 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
174 /* Compile 68881 insns for floating point (not library calls). */
175 #define MASK_68881 (1<<10)
176 #define TARGET_68881 (target_flags & MASK_68881)
178 /* Compile using 68020 bit-field insns. */
179 #define MASK_BITFIELD (1<<11)
180 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
182 /* Compile with 16-bit `int'. */
183 #define MASK_SHORT (1<<12)
184 #define TARGET_SHORT (target_flags & MASK_SHORT)
186 /* Align ints to a word boundary. This breaks compatibility with the
187 published ABI's for structures containing ints, but produces faster
188 code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
189 It's required for ColdFire cpus without a misalignment module. */
190 #define MASK_ALIGN_INT (1<<13)
191 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
193 /* Use PC-relative addressing modes (without using a global offset table).
194 The m68000 supports 16-bit PC-relative addressing.
195 The m68020 supports 32-bit PC-relative addressing
196 (using outer displacements).
198 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
199 treated as all containing an implicit PC-relative component, and hence
200 cannot be used directly as addresses for memory writes. See the comments
201 in m68k.c for more information. */
202 #define MASK_PCREL (1<<14)
203 #define TARGET_PCREL (target_flags & MASK_PCREL)
205 /* Relax strict alignment. */
206 #define MASK_NO_STRICT_ALIGNMENT (1<<15)
207 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
209 /* Compile using rtd insn calling sequence.
210 This will not work unless you use prototypes at least
211 for all functions that can take varying numbers of args. */
212 #define MASK_RTD (1<<16)
213 #define TARGET_RTD (target_flags & MASK_RTD)
215 /* Support A5 relative data separate from text.
216 * This option implies -fPIC, however it inhibits the generation of the
217 * A5 save/restore in functions and the loading of a5 with a got pointer.
219 #define MASK_SEP_DATA (1<<17)
220 #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
222 /* Compile using library ID based shared libraries.
223 * Set a specific ID using the -mshared-library-id=xxx option.
225 #define MASK_ID_SHARED_LIBRARY (1<<18)
226 #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
228 /* Compile for a CPU32. A 68020 without bitfields is a good
229 heuristic for a CPU32. */
230 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
232 /* Is the target a ColdFire? */
233 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
234 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
236 /* Which bits can be set by specifying a ColdFire */
237 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
239 /* Macro to define tables used to set the flags.
240 This is a list in braces of pairs in braces,
241 each pair being { "NAME", VALUE }
242 where VALUE is the bits to set or minus the bits to clear.
243 An empty string NAME is used to identify the default VALUE. */
245 #define TARGET_SWITCHES \
246 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
247 N_("Generate code for a 68020") }, \
248 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
249 N_("Generate code for a 68020") }, \
250 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
251 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
252 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
253 |MASK_68020|MASK_BITFIELD|MASK_68881), \
254 N_("Generate code for a 68000") }, \
255 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
256 |MASK_68020|MASK_BITFIELD|MASK_68881), \
257 N_("Generate code for a 68000") }, \
258 { "bitfield", MASK_BITFIELD, \
259 N_("Use the bit-field instructions") }, \
260 { "nobitfield", - MASK_BITFIELD, \
261 N_("Do not use the bit-field instructions") }, \
262 { "short", MASK_SHORT, \
263 N_("Consider type `int' to be 16 bits wide") }, \
264 { "noshort", - MASK_SHORT, \
265 N_("Consider type `int' to be 32 bits wide") }, \
266 { "68881", MASK_68881, "" }, \
267 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
268 N_("Generate code with library calls for floating point") }, \
269 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
270 N_("Generate code for a 68040, without any new instructions") }, \
271 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
272 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
273 N_("Generate code for a 68060, without any new instructions") }, \
274 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
275 |MASK_68060), "" }, \
276 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
277 N_("Generate code for a 68030") }, \
278 { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \
279 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
280 N_("Generate code for a 68040") }, \
281 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
282 |MASK_68040_ONLY|MASK_68040), "" }, \
283 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
284 N_("Generate code for a 68060") }, \
285 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
286 |MASK_68040_ONLY|MASK_68060), "" }, \
287 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
288 |MASK_BITFIELD|MASK_68881), \
289 N_("Generate code for a 520X") }, \
290 { "5200", (MASK_5200), "" }, \
291 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
292 |MASK_BITFIELD|MASK_68881), \
293 N_("Generate code for a 5206e") }, \
294 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
295 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
296 |MASK_BITFIELD|MASK_68881), \
297 N_("Generate code for a 528x") }, \
298 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
299 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
300 |MASK_BITFIELD|MASK_68881), \
301 N_("Generate code for a 5307") }, \
302 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
303 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
304 |MASK_BITFIELD|MASK_68881), \
305 N_("Generate code for a 5407") }, \
306 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
308 N_("Generate code for a 68851") }, \
310 N_("Do no generate code for a 68851") }, \
311 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
312 |MASK_68020|MASK_BITFIELD|MASK_68881), \
313 N_("Generate code for a 68302") }, \
314 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
315 |MASK_BITFIELD|MASK_68881), \
316 N_("Generate code for a 68332") }, \
317 { "68332", MASK_68020, "" }, \
318 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
319 |MASK_BITFIELD|MASK_68881), \
320 N_("Generate code for a cpu32") }, \
321 { "cpu32", MASK_68020, "" }, \
322 { "align-int", MASK_ALIGN_INT, \
323 N_("Align variables on a 32-bit boundary") }, \
324 { "no-align-int", -MASK_ALIGN_INT, \
325 N_("Align variables on a 16-bit boundary") }, \
326 { "sep-data", MASK_SEP_DATA, \
327 N_("Enable separate data segment") }, \
328 { "no-sep-data", -MASK_SEP_DATA, \
329 N_("Disable separate data segment") }, \
330 { "id-shared-library", MASK_ID_SHARED_LIBRARY, \
331 N_("Enable ID based shared library") }, \
332 { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \
333 N_("Disable ID based shared library") }, \
334 { "pcrel", MASK_PCREL, \
335 N_("Generate pc-relative code") }, \
336 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
337 N_("Do not use unaligned memory references") }, \
338 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
339 N_("Use unaligned memory references") }, \
341 N_("Use different calling convention using 'rtd'") }, \
342 { "nortd", - MASK_RTD, \
343 N_("Use normal calling convention") }, \
345 { "", TARGET_DEFAULT, "" }}
346 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
348 /* This macro is similar to `TARGET_SWITCHES' but defines names of
349 command options that have values. Its definition is an
350 initializer with a subgrouping for each command option.
352 Each subgrouping contains a string constant, that defines the
353 fixed part of the option name, and the address of a variable. The
354 variable, type `char *', is set to the variable part of the given
355 option if the fixed part matches. The actual option name is made
356 by appending `-m' to the specified name. */
357 #define TARGET_OPTIONS \
358 { { "align-loops=", &m68k_align_loops_string, \
359 N_("Loop code aligned to this power of 2"), 0}, \
360 { "align-jumps=", &m68k_align_jumps_string, \
361 N_("Jump targets are aligned to this power of 2"), 0}, \
362 { "align-functions=", &m68k_align_funcs_string, \
363 N_("Function starts are aligned to this power of 2"), 0}, \
364 { "shared-library-id=", &m68k_library_id_string, \
365 N_("ID of shared library to build"), 0}, \
369 /* Sometimes certain combinations of command options do not make
370 sense on a particular target machine. You can define a macro
371 `OVERRIDE_OPTIONS' to take account of this. This macro, if
372 defined, is executed once just after all the command options have
375 Don't use this macro to turn on various extra optimizations for
376 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
378 #define OVERRIDE_OPTIONS override_options()
380 /* These are meant to be redefined in the host dependent files */
381 #define SUBTARGET_SWITCHES
382 #define SUBTARGET_OPTIONS
383 #define SUBTARGET_OVERRIDE_OPTIONS
385 /* target machine storage layout */
387 /* Define for XFmode extended real floating point support. */
388 #define LONG_DOUBLE_TYPE_SIZE 96
390 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
391 instructions, we get proper intermediate rounding, otherwise we
392 get extended precision results. */
393 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
395 /* Define this if most significant bit is lowest numbered
396 in instructions that operate on numbered bit-fields.
397 This is true for 68020 insns such as bfins and bfexts.
398 We make it true always by avoiding using the single-bit insns
399 except in special cases with constant bit numbers. */
400 #define BITS_BIG_ENDIAN 1
402 /* Define this if most significant byte of a word is the lowest numbered. */
403 /* That is true on the 68000. */
404 #define BYTES_BIG_ENDIAN 1
406 /* Define this if most significant word of a multiword number is the lowest
408 /* For 68000 we can decide arbitrarily
409 since there are no machine instructions for them.
410 So let's be consistent. */
411 #define WORDS_BIG_ENDIAN 1
413 /* Width of a word, in units (bytes). */
414 #define UNITS_PER_WORD 4
416 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
417 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
419 /* Boundary (in *bits*) on which stack pointer should be aligned. */
420 #define STACK_BOUNDARY 16
422 /* Allocation boundary (in *bits*) for the code of a function. */
423 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
425 /* Alignment of field after `int : 0' in a structure. */
426 #define EMPTY_FIELD_BOUNDARY 16
428 /* No data type wants to be aligned rounder than this.
429 Most published ABIs say that ints should be aligned on 16 bit
430 boundaries, but cpus with 32-bit busses get better performance
431 aligned on 32-bit boundaries. ColdFires without a misalignment
432 module require 32-bit alignment. */
433 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
435 /* Set this nonzero if move instructions will actually fail to work
436 when given unaligned data. */
437 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
439 /* Maximum power of 2 that code can be aligned to. */
440 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
442 /* Maximum number of library ids we permit */
443 #define MAX_LIBRARY_ID 255
445 /* Align loop starts for optimal branching. */
446 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
448 /* This is how to align an instruction for optimal branching. */
449 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
451 /* Define number of bits in most basic integer type.
452 (If undefined, default is BITS_PER_WORD). */
454 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
456 /* Define these to avoid dependence on meaning of `int'. */
458 #define WCHAR_TYPE "long int"
459 #define WCHAR_TYPE_SIZE 32
461 /* Standard register usage. */
463 /* Number of actual hardware registers.
464 The hardware registers are assigned numbers for the compiler
465 from 0 to just below FIRST_PSEUDO_REGISTER.
466 All registers that the compiler knows about must be given numbers,
467 even those that are not normally considered general registers.
468 For the 68000, we give the data registers numbers 0-7,
469 the address registers numbers 010-017,
470 and the 68881 floating point registers numbers 020-027. */
471 #define FIRST_PSEUDO_REGISTER 25
473 /* This defines the register which is used to hold the offset table for PIC. */
474 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
476 /* 1 for registers that have pervasive standard uses
477 and are not available for the register allocator.
478 On the 68000, only the stack pointer is such. */
480 #define FIXED_REGISTERS \
481 {/* Data registers. */ \
482 0, 0, 0, 0, 0, 0, 0, 0, \
484 /* Address registers. */ \
485 0, 0, 0, 0, 0, 0, 0, 1, \
487 /* Floating point registers \
489 0, 0, 0, 0, 0, 0, 0, 0 }
491 /* 1 for registers not available across function calls.
492 These must include the FIXED_REGISTERS and also any
493 registers that can be used without being saved.
494 The latter must include the registers where values are returned
495 and the register where structure-value addresses are passed.
496 Aside from that, you can include as many other registers as you like. */
497 #define CALL_USED_REGISTERS \
498 {1, 1, 0, 0, 0, 0, 0, 0, \
499 1, 1, 0, 0, 0, 0, 0, 1, \
500 1, 1, 0, 0, 0, 0, 0, 0 }
503 /* Make sure everything's fine if we *don't* have a given processor.
504 This assumes that putting a register in fixed_regs will keep the
505 compiler's mitts completely off it. We don't bother to zero it out
506 of register classes. */
508 #define CONDITIONAL_REGISTER_USAGE \
512 if (! TARGET_68881) \
514 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
515 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
516 if (TEST_HARD_REG_BIT (x, i)) \
517 fixed_regs[i] = call_used_regs[i] = 1; \
519 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
520 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
521 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
524 /* Return number of consecutive hard regs needed starting at reg REGNO
525 to hold something of mode MODE.
526 This is ordinarily the length in words of a value of mode MODE
527 but can be less for certain modes in special long registers.
529 On the 68000, ordinary registers hold 32 bits worth;
530 for the 68881 registers, a single register is always enough for
531 anything that can be stored in them at all. */
532 #define HARD_REGNO_NREGS(REGNO, MODE) \
533 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
534 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
536 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
537 On the 68000, the cpu registers can hold any mode but the 68881 registers
538 can hold only SFmode or DFmode. */
540 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
542 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
543 || ((REGNO) >= 16 && (REGNO) < 24 \
544 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
545 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
546 && GET_MODE_UNIT_SIZE (MODE) <= 12))
549 /* Value is 1 if it is a good idea to tie two pseudo registers
550 when one has mode MODE1 and one has mode MODE2.
551 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
552 for any hard reg, then this must be 0 for correct output. */
553 #define MODES_TIEABLE_P(MODE1, MODE2) \
555 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
556 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
557 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
558 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
560 /* Specify the registers used for certain standard purposes.
561 The values of these macros are register numbers. */
563 /* m68000 pc isn't overloaded on a register. */
564 /* #define PC_REGNUM */
566 /* Register to use for pushing function arguments. */
567 #define STACK_POINTER_REGNUM 15
569 /* Base register for access to local variables of the function. */
570 #define FRAME_POINTER_REGNUM 14
572 /* Value should be nonzero if functions must have frame pointers.
573 Zero means the frame pointer need not be set up (and parms
574 may be accessed via the stack pointer) in functions that seem suitable.
575 This is computed in `reload', in reload1.c. */
576 #define FRAME_POINTER_REQUIRED 0
578 /* Base register for access to arguments of the function.
579 * This isn't a hardware register. It will be eliminated to the
580 * stack pointer or frame pointer.
582 #define ARG_POINTER_REGNUM 24
584 /* Register in which static-chain is passed to a function. */
585 #define STATIC_CHAIN_REGNUM 8
587 /* Register in which address to store a structure value
588 is passed to a function. */
589 #define M68K_STRUCT_VALUE_REGNUM 9
591 /* Define the classes of registers for register constraints in the
592 machine description. Also define ranges of constants.
594 One of the classes must always be named ALL_REGS and include all hard regs.
595 If there is more than one class, another class must be named NO_REGS
596 and contain no registers.
598 The name GENERAL_REGS must be the name of a class (or an alias for
599 another name such as ALL_REGS). This is the class of registers
600 that is allowed by "g" or "r" in a register constraint.
601 Also, registers outside this class are allocated only when
602 instructions express preferences for them.
604 The classes must be numbered in nondecreasing order; that is,
605 a larger-numbered class must never be contained completely
606 in a smaller-numbered class.
608 For any two classes, it is very desirable that there be another
609 class that represents their union. */
611 /* The 68000 has three kinds of registers, so eight classes would be
612 a complete set. One of them is not needed. */
617 GENERAL_REGS, DATA_OR_FP_REGS,
618 ADDR_OR_FP_REGS, ALL_REGS,
621 #define N_REG_CLASSES (int) LIM_REG_CLASSES
623 /* Give names of register classes as strings for dump file. */
625 #define REG_CLASS_NAMES \
626 { "NO_REGS", "DATA_REGS", \
627 "ADDR_REGS", "FP_REGS", \
628 "GENERAL_REGS", "DATA_OR_FP_REGS", \
629 "ADDR_OR_FP_REGS", "ALL_REGS" }
631 /* Define which registers fit in which classes.
632 This is an initializer for a vector of HARD_REG_SET
633 of length N_REG_CLASSES. */
635 #define REG_CLASS_CONTENTS \
637 {0x00000000}, /* NO_REGS */ \
638 {0x000000ff}, /* DATA_REGS */ \
639 {0x0000ff00}, /* ADDR_REGS */ \
640 {0x00ff0000}, /* FP_REGS */ \
641 {0x0000ffff}, /* GENERAL_REGS */ \
642 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
643 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
644 {0x00ffffff}, /* ALL_REGS */ \
647 /* The same information, inverted:
648 Return the class number of the smallest class containing
649 reg number REGNO. This could be a conditional expression
650 or could index an array. */
652 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
654 /* The class value for index registers, and the one for base regs. */
656 #define INDEX_REG_CLASS GENERAL_REGS
657 #define BASE_REG_CLASS ADDR_REGS
659 /* Get reg_class from a letter such as appears in the machine description.
660 We do a trick here to modify the effective constraints on the
661 machine description; we zorch the constraint letters that aren't
662 appropriate for a specific target. This allows us to guarantee
663 that a specific kind of register will not be used for a given target
664 without fiddling with the register classes above. */
666 #define REG_CLASS_FROM_LETTER(C) \
667 ((C) == 'a' ? ADDR_REGS : \
668 ((C) == 'd' ? DATA_REGS : \
669 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
673 /* The letters I, J, K, L and M in a register constraint string
674 can be used to stand for particular ranges of immediate operands.
675 This macro defines what the ranges are.
676 C is the letter, and VALUE is a constant value.
677 Return 1 if VALUE is in the range specified by C.
679 For the 68000, `I' is used for the range 1 to 8
680 allowed as immediate shift counts and in addq.
681 `J' is used for the range of signed numbers that fit in 16 bits.
682 `K' is for numbers that moveq can't handle.
683 `L' is for range -8 to -1, range of values that can be added with subq.
684 `M' is for numbers that moveq+notb can't handle.
685 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
686 'O' is for 16 (for rotate using swap).
687 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
689 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
690 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
691 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
692 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
693 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
694 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
695 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
696 (C) == 'O' ? (VALUE) == 16 : \
697 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
700 * A small bit of explanation:
701 * "G" defines all of the floating constants that are *NOT* 68881
702 * constants. this is so 68881 constants get reloaded and the
705 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
706 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
708 /* A C expression that defines the optional machine-dependent constraint
709 letters that can be used to segregate specific types of operands,
710 usually memory references, for the target machine. It should return 1 if
711 VALUE corresponds to the operand type represented by the constraint letter
712 C. If C is not defined as an extra constraint, the value returned should
713 be 0 regardless of VALUE. */
715 /* Letters in the range `Q' through `U' may be defined in a
716 machine-dependent fashion to stand for arbitrary operand types.
717 The machine description macro `EXTRA_CONSTRAINT' is passed the
718 operand as its first argument and the constraint letter as its
721 `Q' means address register indirect addressing mode.
722 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
723 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
725 #define EXTRA_CONSTRAINT(OP,CODE) \
728 && GET_CODE (OP) == MEM \
729 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
730 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
731 || GET_CODE (XEXP (OP, 0)) == CONST)) \
735 && (GET_CODE (OP) == SYMBOL_REF \
736 || GET_CODE (OP) == LABEL_REF \
737 || GET_CODE (OP) == CONST)) \
740 ? (GET_CODE (OP) == MEM \
741 && GET_CODE (XEXP (OP, 0)) == REG) \
745 /* Given an rtx X being reloaded into a reg required to be
746 in class CLASS, return the class of reg to actually use.
747 In general this is just CLASS; but on some machines
748 in some cases it is preferable to use a more restrictive class.
749 On the 68000 series, use a data reg if possible when the
750 value is a constant in the range where moveq could be used
751 and we ensure that QImodes are reloaded into data regs. */
753 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
754 ((GET_CODE (X) == CONST_INT \
755 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
756 && (CLASS) != ADDR_REGS) \
758 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
760 : (GET_CODE (X) == CONST_DOUBLE \
761 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
762 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
763 ? FP_REGS : NO_REGS) \
765 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
766 || GET_CODE (X) == LABEL_REF)) \
770 /* Force QImode output reloads from subregs to be allocated to data regs,
771 since QImode stores from address regs are not supported. We make the
772 assumption that if the class is not ADDR_REGS, then it must be a superset
775 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
776 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
780 /* Return the maximum number of consecutive registers
781 needed to represent mode MODE in a register of class CLASS. */
782 /* On the 68000, this is the size of MODE in words,
783 except in the FP regs, where a single reg is always enough. */
784 #define CLASS_MAX_NREGS(CLASS, MODE) \
785 ((CLASS) == FP_REGS ? 1 \
786 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
788 /* Moves between fp regs and other regs are two insns. */
789 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
790 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
791 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
794 /* Stack layout; function entry, exit and calling. */
796 /* Define this if pushing a word on the stack
797 makes the stack pointer a smaller address. */
798 #define STACK_GROWS_DOWNWARD
800 /* Define this if the nominal address of the stack frame
801 is at the high-address end of the local variables;
802 that is, each additional local variable allocated
803 goes at a more negative offset in the frame. */
804 #define FRAME_GROWS_DOWNWARD
806 /* Offset within stack frame to start allocating local variables at.
807 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
808 first local allocated. Otherwise, it is the offset to the BEGINNING
809 of the first local allocated. */
810 #define STARTING_FRAME_OFFSET 0
812 /* If we generate an insn to push BYTES bytes,
813 this says how many the stack pointer really advances by.
814 On the 68000, sp@- in a byte insn really pushes a word.
815 On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */
816 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
818 /* We want to avoid trying to push bytes. */
819 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
820 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
821 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
823 /* Offset of first parameter from the argument pointer register value. */
824 #define FIRST_PARM_OFFSET(FNDECL) 8
826 /* Value is the number of byte of arguments automatically
827 popped when returning from a subroutine call.
828 FUNDECL is the declaration node of the function (as a tree),
829 FUNTYPE is the data type of the function (as a tree),
830 or for a library call it is an identifier node for the subroutine name.
831 SIZE is the number of bytes of arguments passed on the stack.
833 On the 68000, the RTS insn cannot pop anything.
834 On the 68010, the RTD insn may be used to pop them if the number
835 of args is fixed, but if the number is variable then the caller
836 must pop them all. RTD can't be used for library calls now
837 because the library is compiled with the Unix compiler.
838 Use of RTD is a selectable option, since it is incompatible with
839 standard Unix calling sequences. If the option is not selected,
840 the caller must always pop the args. */
842 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
843 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
844 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
845 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
846 == void_type_node))) \
849 /* Define how to find the value returned by a function.
850 VALTYPE is the data type of the value (as a tree).
851 If the precise function being called is known, FUNC is its FUNCTION_DECL;
852 otherwise, FUNC is 0. */
854 /* On the 68000 the return value is in D0 regardless. */
856 #define FUNCTION_VALUE(VALTYPE, FUNC) \
857 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
859 /* Define how to find the value returned by a library function
860 assuming the value has mode MODE. */
862 /* On the 68000 the return value is in D0 regardless. */
864 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
866 /* 1 if N is a possible register number for a function value.
867 On the 68000, d0 is the only register thus used. */
869 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
871 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
872 more than one register. */
874 #define NEEDS_UNTYPED_CALL 0
876 /* Define this if PCC uses the nonreentrant convention for returning
877 structure and union values. */
879 #define PCC_STATIC_STRUCT_RETURN
881 /* 1 if N is a possible register number for function argument passing.
882 On the 68000, no registers are used in this way. */
884 #define FUNCTION_ARG_REGNO_P(N) 0
886 /* Define a data type for recording info about an argument list
887 during the scan of that argument list. This data type should
888 hold all necessary information about the function itself
889 and about the args processed so far, enough to enable macros
890 such as FUNCTION_ARG to determine where the next arg should go.
892 On the m68k, this is a single integer, which is a number of bytes
893 of arguments scanned so far. */
895 #define CUMULATIVE_ARGS int
897 /* Initialize a variable CUM of type CUMULATIVE_ARGS
898 for a call to a function whose data type is FNTYPE.
899 For a library call, FNTYPE is 0.
901 On the m68k, the offset starts at 0. */
903 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
906 /* Update the data in CUM to advance over an argument
907 of mode MODE and data type TYPE.
908 (TYPE is null for libcalls where that information may not be available.) */
910 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
911 ((CUM) += ((MODE) != BLKmode \
912 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
913 : (int_size_in_bytes (TYPE) + 3) & ~3))
915 /* Define where to put the arguments to a function.
916 Value is zero to push the argument on the stack,
917 or a hard register in which to store the argument.
919 MODE is the argument's machine mode.
920 TYPE is the data type of the argument (as a tree).
921 This is null for libcalls where that information may
923 CUM is a variable of type CUMULATIVE_ARGS which gives info about
924 the preceding args and about the function being called.
925 NAMED is nonzero if this argument is a named parameter
926 (otherwise it is an extra parameter matching an ellipsis).
928 On the m68k all args are always pushed. */
930 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
932 /* For an arg passed partly in registers and partly in memory,
933 this is the number of registers used.
934 For args passed entirely in registers or entirely in memory, zero. */
936 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
938 /* Output assembler code to FILE to increment profiler label # LABELNO
939 for profiling a function entry. */
941 #define FUNCTION_PROFILER(FILE, LABELNO) \
942 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
944 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
945 the stack pointer does not matter. The value is tested only in
946 functions that have frame pointers.
947 No definition is equivalent to always zero. */
949 #define EXIT_IGNORE_STACK 1
951 /* This is a hook for other tm files to change. */
952 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
954 /* Determine if the epilogue should be output as RTL.
955 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
956 #define USE_RETURN_INSN use_return_insn ()
958 /* Output assembler code for a block containing the constant parts
959 of a trampoline, leaving space for the variable parts. */
961 /* On the 68k, the trampoline looks like this:
965 WARNING: Targets that may run on 68040+ cpus must arrange for
966 the instruction cache to be flushed. Previous incarnations of
967 the m68k trampoline code attempted to get around this by either
968 using an out-of-line transfer function or pc-relative data, but
969 the fact remains that the code to jump to the transfer function
970 or the code to load the pc-relative data needs to be flushed
971 just as much as the "variable" portion of the trampoline.
972 Recognizing that a cache flush is going to be required anyway,
973 dispense with such notions and build a smaller trampoline. */
975 /* Since more instructions are required to move a template into
976 place than to create it on the spot, don't use a template. */
978 /* Length in units of the trampoline for entering a nested function. */
980 #define TRAMPOLINE_SIZE 12
982 /* Alignment required for a trampoline in bits. */
984 #define TRAMPOLINE_ALIGNMENT 16
986 /* Targets redefine this to invoke code to either flush the cache,
987 or enable stack execution (or both). */
989 #ifndef FINALIZE_TRAMPOLINE
990 #define FINALIZE_TRAMPOLINE(TRAMP)
993 /* Emit RTL insns to initialize the variable parts of a trampoline.
994 FNADDR is an RTX for the address of the function's pure code.
995 CXT is an RTX for the static chain value for the function.
997 We generate a two-instructions program at address TRAMP :
1001 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1003 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1004 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1005 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1007 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1008 FINALIZE_TRAMPOLINE(TRAMP); \
1011 /* This is the library routine that is used
1012 to transfer control from the trampoline
1013 to the actual nested function.
1014 It is defined for backward compatibility,
1015 for linking with object code that used the old
1016 trampoline definition. */
1018 /* A colon is used with no explicit operands
1019 to cause the template string to be scanned for %-constructs. */
1020 /* The function name __transfer_from_trampoline is not actually used.
1021 The function definition just permits use of "asm with operands"
1022 (though the operand list is empty). */
1023 #define TRANSFER_FROM_TRAMPOLINE \
1025 __transfer_from_trampoline () \
1027 register char *a0 asm ("%a0"); \
1028 asm (GLOBAL_ASM_OP "___trampoline"); \
1029 asm ("___trampoline:"); \
1030 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1031 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1035 /* Definitions for register eliminations.
1037 This is an array of structures. Each structure initializes one pair
1038 of eliminable registers. The "from" register number is given first,
1039 followed by "to". Eliminations of the same "from" register are listed
1040 in order of preference.
1042 There are two registers that can always be eliminated on the m68k.
1043 The frame pointer and the arg pointer can be replaced by either the
1044 hard frame pointer or to the stack pointer, depending upon the
1045 circumstances. The hard frame pointer is not used before reload and
1046 so it is not eligible for elimination. */
1048 #define ELIMINABLE_REGS \
1049 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1050 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
1051 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1053 /* Given FROM and TO register numbers, say whether this elimination is
1054 allowed. Frame pointer elimination is automatically handled.
1056 All other eliminations are valid. */
1058 #define CAN_ELIMINATE(FROM, TO) \
1059 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1061 /* Define the offset between two registers, one to be eliminated, and the other
1062 its replacement, at the start of a routine. */
1064 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1065 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1067 /* Addressing modes, and classification of registers for them. */
1069 #define HAVE_POST_INCREMENT 1
1071 #define HAVE_PRE_DECREMENT 1
1073 /* Macros to check register numbers against specific register classes. */
1075 /* These assume that REGNO is a hard or pseudo reg number.
1076 They give nonzero only if REGNO is a hard reg of the suitable class
1077 or a pseudo reg currently allocated to a suitable hard reg.
1078 Since they use reg_renumber, they are safe only once reg_renumber
1079 has been allocated, which happens in local-alloc.c. */
1081 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1082 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1083 #define REGNO_OK_FOR_BASE_P(REGNO) \
1084 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1085 #define REGNO_OK_FOR_DATA_P(REGNO) \
1086 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1087 #define REGNO_OK_FOR_FP_P(REGNO) \
1088 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1090 /* Now macros that check whether X is a register and also,
1091 strictly, whether it is in a specified class.
1093 These macros are specific to the 68000, and may be used only
1094 in code for printing assembler insns and in conditions for
1095 define_optimization. */
1097 /* 1 if X is a data register. */
1099 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1101 /* 1 if X is an fp register. */
1103 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1105 /* 1 if X is an address register */
1107 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1109 /* Maximum number of registers that can appear in a valid memory address. */
1111 #define MAX_REGS_PER_ADDRESS 2
1113 /* Recognize any constant value that is a valid address. */
1115 #define CONSTANT_ADDRESS_P(X) \
1116 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1117 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1118 || GET_CODE (X) == HIGH)
1120 /* Nonzero if the constant value X is a legitimate general operand.
1121 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1123 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1125 /* Nonzero if the constant value X is a legitimate general operand
1126 when generating PIC code. It is given that flag_pic is on and
1127 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1129 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1130 accepted by insn predicates, but which would otherwise fail the
1131 `general_operand' test. */
1133 #ifndef REG_OK_STRICT
1134 #define PCREL_GENERAL_OPERAND_OK 0
1136 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1139 #define LEGITIMATE_PIC_OPERAND_P(X) \
1140 (! symbolic_operand (X, VOIDmode) \
1141 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1142 || PCREL_GENERAL_OPERAND_OK)
1144 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1145 and check its validity for a certain class.
1146 We have two alternate definitions for each of them.
1147 The usual definition accepts all pseudo regs; the other rejects
1148 them unless they have been allocated suitable hard regs.
1149 The symbol REG_OK_STRICT causes the latter definition to be used.
1151 Most source files want to accept pseudo regs in the hope that
1152 they will get allocated to the class that the insn wants them to be in.
1153 Source files for reload pass need to be strict.
1154 After reload, it makes no difference, since pseudo regs have
1155 been eliminated by then. */
1157 #ifndef REG_OK_STRICT
1159 /* Nonzero if X is a hard reg that can be used as an index
1160 or if it is a pseudo reg. */
1161 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1162 /* Nonzero if X is a hard reg that can be used as a base reg
1163 or if it is a pseudo reg. */
1164 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1168 /* Nonzero if X is a hard reg that can be used as an index. */
1169 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1170 /* Nonzero if X is a hard reg that can be used as a base reg. */
1171 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1175 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1176 that is a valid memory address for an instruction.
1177 The MODE argument is the machine mode for the MEM expression
1178 that wants to use this address.
1180 When generating PIC, an address involving a SYMBOL_REF is legitimate
1181 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1182 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1183 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1185 Likewise for a LABEL_REF when generating PIC.
1187 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1189 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1190 also makes function inlining work when inline functions are called with
1191 arguments that are SUBREGs. */
1193 #define LEGITIMATE_BASE_REG_P(X) \
1194 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1195 || (GET_CODE (X) == SUBREG \
1196 && GET_CODE (SUBREG_REG (X)) == REG \
1197 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1199 #define INDIRECTABLE_1_ADDRESS_P(X) \
1200 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1201 || LEGITIMATE_BASE_REG_P (X) \
1202 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1203 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1204 || (GET_CODE (X) == PLUS \
1205 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1206 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1208 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1209 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1210 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1211 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1212 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1214 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1215 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1217 /* Only labels on dispatch tables are valid for indexing from. */
1218 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1220 if (GET_CODE (X) == LABEL_REF \
1221 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1222 && GET_CODE (temp) == JUMP_INSN \
1223 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1224 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1226 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1228 #define GO_IF_INDEXING(X, ADDR) \
1229 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1230 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1231 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1232 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1234 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1235 { GO_IF_INDEXING (X, ADDR); \
1236 if (GET_CODE (X) == PLUS) \
1237 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1238 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1239 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1240 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1241 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1242 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1244 /* ColdFire/5200 does not allow HImode index registers. */
1245 #define LEGITIMATE_INDEX_REG_P(X) \
1246 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1247 || (! TARGET_COLDFIRE \
1248 && GET_CODE (X) == SIGN_EXTEND \
1249 && GET_CODE (XEXP (X, 0)) == REG \
1250 && GET_MODE (XEXP (X, 0)) == HImode \
1251 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1252 || (GET_CODE (X) == SUBREG \
1253 && GET_CODE (SUBREG_REG (X)) == REG \
1254 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1256 #define LEGITIMATE_INDEX_P(X) \
1257 (LEGITIMATE_INDEX_REG_P (X) \
1258 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1259 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1260 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1261 && (INTVAL (XEXP (X, 1)) == 2 \
1262 || INTVAL (XEXP (X, 1)) == 4 \
1263 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1265 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1266 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1267 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1268 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1269 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1270 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1271 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1274 /* Don't call memory_address_noforce for the address to fetch
1275 the switch offset. This address is ok as it stands (see above),
1276 but memory_address_noforce would alter it. */
1277 #define PIC_CASE_VECTOR_ADDRESS(index) index
1279 /* Try machine-dependent ways of modifying an illegitimate address
1280 to be legitimate. If we find one, return the new, valid address.
1281 This macro is used in only one place: `memory_address' in explow.c.
1283 OLDX is the address as it was before break_out_memory_refs was called.
1284 In some cases it is useful to look at this to decide what needs to be done.
1286 MODE and WIN are passed so that this macro can use
1287 GO_IF_LEGITIMATE_ADDRESS.
1289 It is always safe for this macro to do nothing. It exists to recognize
1290 opportunities to optimize the output.
1292 For the 68000, we handle X+REG by loading X into a register R and
1293 using R+REG. R will go in an address reg and indexing will be used.
1294 However, if REG is a broken-out memory address or multiplication,
1295 nothing needs to be done because REG can certainly go in an address reg. */
1297 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1298 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1299 { register int ch = (X) != (OLDX); \
1300 if (GET_CODE (X) == PLUS) \
1302 if (GET_CODE (XEXP (X, 0)) == MULT) \
1303 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1304 if (GET_CODE (XEXP (X, 1)) == MULT) \
1305 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1306 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1307 && GET_CODE (XEXP (X, 0)) == REG) \
1309 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1310 if (GET_CODE (XEXP (X, 0)) == REG \
1311 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1312 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1313 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1314 { register rtx temp = gen_reg_rtx (Pmode); \
1315 register rtx val = force_operand (XEXP (X, 1), 0); \
1316 emit_move_insn (temp, val); \
1318 XEXP (X, 1) = temp; \
1320 else if (GET_CODE (XEXP (X, 1)) == REG \
1321 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1322 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1323 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1324 { register rtx temp = gen_reg_rtx (Pmode); \
1325 register rtx val = force_operand (XEXP (X, 0), 0); \
1326 emit_move_insn (temp, val); \
1328 XEXP (X, 0) = temp; \
1331 /* Go to LABEL if ADDR (a legitimate address expression)
1332 has an effect that depends on the machine mode it is used for.
1333 On the 68000, only predecrement and postincrement address depend thus
1334 (the amount of decrement or increment being the length of the operand). */
1336 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1337 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1339 /* Specify the machine mode that this machine uses
1340 for the index in the tablejump instruction. */
1341 #define CASE_VECTOR_MODE HImode
1343 /* Define as C expression which evaluates to nonzero if the tablejump
1344 instruction expects the table to contain offsets from the address of the
1346 Do not define this if the table should contain absolute addresses. */
1347 #define CASE_VECTOR_PC_RELATIVE 1
1349 /* Define this as 1 if `char' should by default be signed; else as 0. */
1350 #define DEFAULT_SIGNED_CHAR 1
1352 /* Don't cse the address of the function being compiled. */
1353 #define NO_RECURSIVE_FUNCTION_CSE
1355 /* Max number of bytes we can move from memory to memory
1356 in one reasonably fast instruction. */
1359 /* Nonzero if access to memory by bytes is slow and undesirable. */
1360 #define SLOW_BYTE_ACCESS 0
1362 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1363 is done just by pretending it is already truncated. */
1364 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1366 /* We assume that the store-condition-codes instructions store 0 for false
1367 and some other value for true. This is the value stored for true. */
1369 #define STORE_FLAG_VALUE (-1)
1371 /* Specify the machine mode that pointers have.
1372 After generation of rtl, the compiler makes no further distinction
1373 between pointers and any other objects of this machine mode. */
1374 #define Pmode SImode
1376 /* A function address in a call instruction
1377 is a byte address (for indexing purposes)
1378 so give the MEM rtx a byte's mode. */
1379 #define FUNCTION_MODE QImode
1382 /* Tell final.c how to eliminate redundant test instructions. */
1384 /* Here we define machine-dependent flags and fields in cc_status
1385 (see `conditions.h'). */
1387 /* Set if the cc value is actually in the 68881, so a floating point
1388 conditional branch must be output. */
1389 #define CC_IN_68881 04000
1391 /* Store in cc_status the expressions that the condition codes will
1392 describe after execution of an instruction whose pattern is EXP.
1393 Do not alter them if the instruction would not alter the cc's. */
1395 /* On the 68000, all the insns to store in an address register fail to
1396 set the cc's. However, in some cases these instructions can make it
1397 possibly invalid to use the saved cc's. In those cases we clear out
1398 some or all of the saved cc's so they won't be used. */
1400 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1402 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1403 do { if (cc_prev_status.flags & CC_IN_68881) \
1405 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1407 return NORMAL; } while (0)
1409 /* Control the assembler format that we output. */
1411 /* Output to assembler file text saying following lines
1412 may contain character constants, extra white space, comments, etc. */
1414 #define ASM_APP_ON "#APP\n"
1416 /* Output to assembler file text saying following lines
1417 no longer contain unusual constructs. */
1419 #define ASM_APP_OFF "#NO_APP\n"
1421 /* Output before read-only data. */
1423 #define TEXT_SECTION_ASM_OP "\t.text"
1425 /* Output before writable data. */
1427 #define DATA_SECTION_ASM_OP "\t.data"
1429 #define GLOBAL_ASM_OP "\t.globl\t"
1431 /* Here are four prefixes that are used by asm_fprintf to
1432 facilitate customization for alternate assembler syntaxes.
1433 Machines with no likelihood of an alternate syntax need not
1434 define these and need not use asm_fprintf. */
1436 /* The prefix for register names. Note that REGISTER_NAMES
1437 is supposed to include this prefix. */
1439 #define REGISTER_PREFIX ""
1441 /* The prefix for local labels. You should be able to define this as
1442 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1443 without having to make any other changes to account for the specific
1444 definition. Note it is a string literal, not interpreted by printf
1447 #define LOCAL_LABEL_PREFIX ""
1449 /* The prefix to add to user-visible assembler symbols. */
1451 #define USER_LABEL_PREFIX "_"
1453 /* The prefix for immediate operands. */
1455 #define IMMEDIATE_PREFIX "#"
1457 /* How to refer to registers in assembler output.
1458 This sequence is indexed by compiler's hard-register-number (see above). */
1460 #define REGISTER_NAMES \
1461 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
1462 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
1463 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
1464 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
1465 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
1466 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
1467 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
1468 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
1469 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
1471 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
1473 /* Return a register name by index, handling %fp nicely.
1474 We don't replace %fp for targets that don't map it to %a6
1475 since it may confuse GAS. */
1476 #define M68K_REGNAME(r) ( \
1477 ((FRAME_POINTER_REGNUM == 14) \
1478 && ((r) == FRAME_POINTER_REGNUM) \
1479 && frame_pointer_needed) ? \
1480 M68K_FP_REG_NAME : reg_names[(r)])
1482 /* How to renumber registers for dbx and gdb.
1483 On the Sun-3, the floating point registers have numbers
1484 18 to 25, not 16 to 23 as they do in the compiler. */
1486 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1488 /* Before the prologue, RA is at 0(%sp). */
1489 #define INCOMING_RETURN_ADDR_RTX \
1490 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1492 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1493 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1494 Instead use the identity mapping. */
1495 #define DWARF_FRAME_REGNUM(REG) REG
1497 /* Before the prologue, the top of the frame is at 4(%sp). */
1498 #define INCOMING_FRAME_SP_OFFSET 4
1500 /* Describe how we implement __builtin_eh_return. */
1501 #define EH_RETURN_DATA_REGNO(N) \
1502 ((N) < 2 ? (N) : INVALID_REGNUM)
1503 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1504 #define EH_RETURN_HANDLER_RTX \
1505 gen_rtx_MEM (Pmode, \
1506 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1507 plus_constant (EH_RETURN_STACKADJ_RTX, \
1510 /* Select a format to encode pointers in exception handling data. CODE
1511 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1512 true if the symbol may be affected by dynamic relocations. */
1513 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1515 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1518 /* This is how to output a reference to a user-level label named NAME.
1519 `assemble_name' uses this. */
1521 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1522 asm_fprintf (FILE, "%U%s", NAME)
1524 /* This is how to store into the string LABEL
1525 the symbol_ref name of an internal numbered label where
1526 PREFIX is the class of label and NUM is the number within the class.
1527 This is suitable for output with `assemble_name'. */
1529 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1530 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1532 /* This is how to output an insn to push a register on the stack.
1533 It need not be very fast code. */
1535 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1536 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1538 /* This is how to output an insn to pop a register from the stack.
1539 It need not be very fast code. */
1541 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1542 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1544 /* This is how to output an element of a case-vector that is absolute.
1545 (The 68000 does not use such vectors,
1546 but we must define this macro anyway.) */
1548 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1549 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1551 /* This is how to output an element of a case-vector that is relative. */
1553 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1554 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1556 /* This is how to output an assembler line
1557 that says to advance the location counter
1558 to a multiple of 2**LOG bytes. */
1560 /* We don't have a way to align to more than a two-byte boundary, so do the
1561 best we can and don't complain. */
1562 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1564 fprintf (FILE, "\t.even\n");
1566 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1567 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1569 /* This says how to output an assembler line
1570 to define a global common symbol. */
1572 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1573 ( fputs (".comm ", (FILE)), \
1574 assemble_name ((FILE), (NAME)), \
1575 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1577 /* This says how to output an assembler line
1578 to define a local common symbol. */
1580 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1581 ( fputs (".lcomm ", (FILE)), \
1582 assemble_name ((FILE), (NAME)), \
1583 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1585 /* Output a float value (represented as a C double) as an immediate operand.
1586 This macro is a 68k-specific macro. */
1588 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1593 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1594 asm_fprintf ((FILE), "%I0r%s", dstr); \
1599 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1600 asm_fprintf ((FILE), "%I0x%lx", l); \
1604 /* Output a double value (represented as a C double) as an immediate operand.
1605 This macro is a 68k-specific macro. */
1606 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1607 do { char dstr[30]; \
1608 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1609 asm_fprintf (FILE, "%I0r%s", dstr); \
1612 /* Note, long double immediate operands are not actually
1613 generated by m68k.md. */
1614 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1615 do { char dstr[30]; \
1616 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1617 asm_fprintf (FILE, "%I0r%s", dstr); \
1620 /* Print operand X (an rtx) in assembler syntax to file FILE.
1621 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1622 For `%' followed by punctuation, CODE is the punctuation and X is null.
1624 On the 68000, we use several CODE characters:
1625 '.' for dot needed in Motorola-style opcode names.
1626 '-' for an operand pushing on the stack:
1627 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1628 '+' for an operand pushing on the stack:
1629 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1630 '@' for a reference to the top word on the stack:
1631 sp@, (sp) or (%sp) depending on the style of syntax.
1632 '!' for the fpcr register (used in some float-to-fixed conversions).
1633 '$' for the letter `s' in an op code, but only on the 68040.
1634 '&' for the letter `d' in an op code, but only on the 68040.
1635 '/' for register prefix needed by longlong.h.
1637 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1638 'd' to force memory addressing to be absolute, not relative.
1639 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1640 'o' for operands to go directly to output_operand_address (bypassing
1641 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1642 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1643 or print pair of registers as rx:ry. */
1645 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1646 ((CODE) == '.' || (CODE) == '-' || (CODE) == '+' || (CODE) == '@' \
1647 || (CODE) == '!' || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1649 /* A C compound statement to output to stdio stream STREAM the
1650 assembler syntax for an instruction operand X. X is an RTL
1653 CODE is a value that can be used to specify one of several ways
1654 of printing the operand. It is used when identical operands
1655 must be printed differently depending on the context. CODE
1656 comes from the `%' specification that was used to request
1657 printing of the operand. If the specification was just `%DIGIT'
1658 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1659 is the ASCII code for LTR.
1661 If X is a register, this macro should print the register's name.
1662 The names can be found in an array `reg_names' whose type is
1663 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1665 When the machine description has a specification `%PUNCT' (a `%'
1666 followed by a punctuation character), this macro is called with
1667 a null pointer for X and the punctuation character for CODE.
1669 See m68k.c for the m68k specific codes. */
1671 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1673 /* A C compound statement to output to stdio stream STREAM the
1674 assembler syntax for an instruction operand that is a memory
1675 reference whose address is ADDR. ADDR is an RTL expression. */
1677 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1679 /* Variables in m68k.c */
1680 extern const char *m68k_align_loops_string;
1681 extern const char *m68k_align_jumps_string;
1682 extern const char *m68k_align_funcs_string;
1683 extern const char *m68k_library_id_string;
1684 extern int m68k_align_loops;
1685 extern int m68k_align_jumps;
1686 extern int m68k_align_funcs;
1687 extern int m68k_last_compare_had_fp_operands;
1690 /* Define the codes that are matched by predicates in m68k.c. */
1692 #define PREDICATE_CODES \
1693 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1694 LABEL_REF, SUBREG, REG, MEM}}, \
1695 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1696 {"memory_src_operand", {SUBREG, MEM}}, \
1697 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1698 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1699 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1700 {"const_sint32_operand", {CONST_INT}}, \
1701 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1703 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},