1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Note that some other tm.h files include this one and then override
36 many of the definitions that relate to assembler syntax. */
38 /* Target CPU builtins. */
39 #define TARGET_CPU_CPP_BUILTINS() \
42 builtin_define ("__m68k__"); \
43 builtin_define_std ("mc68000"); \
44 if (TARGET_68040_ONLY) \
47 builtin_define_std ("mc68060"); \
49 builtin_define_std ("mc68040"); \
51 else if (TARGET_68060) /* -m68020-60 */ \
53 builtin_define_std ("mc68060"); \
54 builtin_define_std ("mc68040"); \
55 builtin_define_std ("mc68030"); \
56 builtin_define_std ("mc68020"); \
58 else if (TARGET_68040) /* -m68020-40 */ \
60 builtin_define_std ("mc68040"); \
61 builtin_define_std ("mc68030"); \
62 builtin_define_std ("mc68020"); \
64 else if (TARGET_68030) \
65 builtin_define_std ("mc68030"); \
66 else if (TARGET_68020) \
67 builtin_define_std ("mc68020"); \
69 builtin_define ("__HAVE_68881__"); \
72 builtin_define_std ("mc68332"); \
73 builtin_define_std ("mcpu32"); \
75 if (TARGET_COLDFIRE) \
76 builtin_define ("__mcoldfire__"); \
78 builtin_define ("__mcf5200__"); \
81 builtin_define ("__mcf528x__"); \
82 builtin_define ("__mcf5200__"); \
86 builtin_define ("__mcf5300__"); \
87 builtin_define ("__mcf5307__"); \
91 builtin_define ("__mcf5400__"); \
92 builtin_define ("__mcf5407__"); \
94 if (TARGET_CF_HWDIV) \
95 builtin_define ("__mcfhwdiv__"); \
98 builtin_define ("__pic__"); \
100 builtin_define ("__PIC__"); \
102 builtin_assert ("cpu=m68k"); \
103 builtin_assert ("machine=m68k"); \
107 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
109 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
110 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
111 #define INT_OP_NO_DOT 2 /* byte, short, long */
112 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
114 /* Set the default */
115 #define INT_OP_GROUP INT_OP_DOT_WORD
117 /* Run-time compilation parameters selecting different hardware subsets. */
119 extern int target_flags;
121 /* Macros used in the machine description to test the flags. */
123 /* Compile for a 68020 (not a 68000 or 68010). */
124 #define MASK_68020 (1<<0)
125 #define TARGET_68020 (target_flags & MASK_68020)
127 /* Compile for a 68030. This does not really make a difference in GCC,
128 it just enables the __mc68030__ predefine. */
129 #define MASK_68030 (1<<1)
130 #define TARGET_68030 (target_flags & MASK_68030)
132 /* Optimize for 68040, but still allow execution on 68020
133 (-m68020-40 or -m68040).
134 The 68040 will execute all 68030 and 68881/2 instructions, but some
135 of them must be emulated in software by the OS. When TARGET_68040 is
136 turned on, these instructions won't be used. This code will still
137 run on a 68030 and 68881/2. */
138 #define MASK_68040 (1<<2)
139 #define TARGET_68040 (target_flags & MASK_68040)
141 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
142 #define MASK_68040_ONLY (1<<3)
143 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
145 /* Optimize for 68060, but still allow execution on 68020
146 (-m68020-60 or -m68060).
147 The 68060 will execute all 68030 and 68881/2 instructions, but some
148 of them must be emulated in software by the OS. When TARGET_68060 is
149 turned on, these instructions won't be used. This code will still
150 run on a 68030 and 68881/2. */
151 #define MASK_68060 (1<<4)
152 #define TARGET_68060 (target_flags & MASK_68060)
154 /* Compile for mcf5200 */
155 #define MASK_5200 (1<<5)
156 #define TARGET_5200 (target_flags & MASK_5200)
158 /* Build for ColdFire v3 */
159 #define MASK_CFV3 (1<<6)
160 #define TARGET_CFV3 (target_flags & MASK_CFV3)
162 /* Build for ColdFire v4 */
163 #define MASK_CFV4 (1<<7)
164 #define TARGET_CFV4 (target_flags & MASK_CFV4)
166 /* Compile for ColdFire 528x */
167 #define MASK_528x (1<<8)
168 #define TARGET_528x (target_flags & MASK_528x)
170 /* Divide support for ColdFire */
171 #define MASK_CF_HWDIV (1<<9)
172 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
174 /* Compile 68881 insns for floating point (not library calls). */
175 #define MASK_68881 (1<<10)
176 #define TARGET_68881 (target_flags & MASK_68881)
178 /* Compile using 68020 bit-field insns. */
179 #define MASK_BITFIELD (1<<11)
180 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
182 /* Compile with 16-bit `int'. */
183 #define MASK_SHORT (1<<12)
184 #define TARGET_SHORT (target_flags & MASK_SHORT)
186 /* Align ints to a word boundary. This breaks compatibility with the
187 published ABI's for structures containing ints, but produces faster
188 code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
189 It's required for ColdFire cpus without a misalignment module. */
190 #define MASK_ALIGN_INT (1<<13)
191 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
193 /* Use PC-relative addressing modes (without using a global offset table).
194 The m68000 supports 16-bit PC-relative addressing.
195 The m68020 supports 32-bit PC-relative addressing
196 (using outer displacements).
198 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
199 treated as all containing an implicit PC-relative component, and hence
200 cannot be used directly as addresses for memory writes. See the comments
201 in m68k.c for more information. */
202 #define MASK_PCREL (1<<14)
203 #define TARGET_PCREL (target_flags & MASK_PCREL)
205 /* Relax strict alignment. */
206 #define MASK_NO_STRICT_ALIGNMENT (1<<15)
207 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
209 /* Compile using rtd insn calling sequence.
210 This will not work unless you use prototypes at least
211 for all functions that can take varying numbers of args. */
212 #define MASK_RTD (1<<16)
213 #define TARGET_RTD (target_flags & MASK_RTD)
215 /* Support A5 relative data separate from text.
216 * This option implies -fPIC, however it inhibits the generation of the
217 * A5 save/restore in functions and the loading of a5 with a got pointer.
219 #define MASK_SEP_DATA (1<<17)
220 #define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
222 /* Compile using library ID based shared libraries.
223 * Set a specific ID using the -mshared-library-id=xxx option.
225 #define MASK_ID_SHARED_LIBRARY (1<<18)
226 #define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
228 /* Compile for a CPU32. A 68020 without bitfields is a good
229 heuristic for a CPU32. */
230 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
232 /* Is the target a ColdFire? */
233 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
234 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
236 /* Which bits can be set by specifying a ColdFire */
237 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
239 /* Macro to define tables used to set the flags.
240 This is a list in braces of pairs in braces,
241 each pair being { "NAME", VALUE }
242 where VALUE is the bits to set or minus the bits to clear.
243 An empty string NAME is used to identify the default VALUE. */
245 #define TARGET_SWITCHES \
246 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
247 N_("Generate code for a 68020") }, \
248 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
249 N_("Generate code for a 68020") }, \
250 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
251 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
252 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
253 |MASK_68020|MASK_BITFIELD|MASK_68881), \
254 N_("Generate code for a 68000") }, \
255 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
256 |MASK_68020|MASK_BITFIELD|MASK_68881), \
257 N_("Generate code for a 68000") }, \
258 { "bitfield", MASK_BITFIELD, \
259 N_("Use the bit-field instructions") }, \
260 { "nobitfield", - MASK_BITFIELD, \
261 N_("Do not use the bit-field instructions") }, \
262 { "short", MASK_SHORT, \
263 N_("Consider type `int' to be 16 bits wide") }, \
264 { "noshort", - MASK_SHORT, \
265 N_("Consider type `int' to be 32 bits wide") }, \
266 { "68881", MASK_68881, "" }, \
267 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
268 N_("Generate code with library calls for floating point") }, \
269 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
270 N_("Generate code for a 68040, without any new instructions") }, \
271 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
272 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
273 N_("Generate code for a 68060, without any new instructions") }, \
274 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
275 |MASK_68060), "" }, \
276 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
277 N_("Generate code for a 68030") }, \
278 { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" }, \
279 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
280 N_("Generate code for a 68040") }, \
281 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
282 |MASK_68040_ONLY|MASK_68040), "" }, \
283 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
284 N_("Generate code for a 68060") }, \
285 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
286 |MASK_68040_ONLY|MASK_68060), "" }, \
287 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
288 |MASK_BITFIELD|MASK_68881), \
289 N_("Generate code for a 520X") }, \
290 { "5200", (MASK_5200), "" }, \
291 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
292 |MASK_BITFIELD|MASK_68881), \
293 N_("Generate code for a 5206e") }, \
294 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
295 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
296 |MASK_BITFIELD|MASK_68881), \
297 N_("Generate code for a 528x") }, \
298 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
299 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
300 |MASK_BITFIELD|MASK_68881), \
301 N_("Generate code for a 5307") }, \
302 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
303 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
304 |MASK_BITFIELD|MASK_68881), \
305 N_("Generate code for a 5407") }, \
306 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
308 N_("Generate code for a 68851") }, \
310 N_("Do no generate code for a 68851") }, \
311 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
312 |MASK_68020|MASK_BITFIELD|MASK_68881), \
313 N_("Generate code for a 68302") }, \
314 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
315 |MASK_BITFIELD|MASK_68881), \
316 N_("Generate code for a 68332") }, \
317 { "68332", MASK_68020, "" }, \
318 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
319 |MASK_BITFIELD|MASK_68881), \
320 N_("Generate code for a cpu32") }, \
321 { "cpu32", MASK_68020, "" }, \
322 { "align-int", MASK_ALIGN_INT, \
323 N_("Align variables on a 32-bit boundary") }, \
324 { "no-align-int", -MASK_ALIGN_INT, \
325 N_("Align variables on a 16-bit boundary") }, \
326 { "sep-data", MASK_SEP_DATA, \
327 N_("Enable separate data segment") }, \
328 { "no-sep-data", -MASK_SEP_DATA, \
329 N_("Disable separate data segment") }, \
330 { "id-shared-library", MASK_ID_SHARED_LIBRARY, \
331 N_("Enable ID based shared library") }, \
332 { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, \
333 N_("Disable ID based shared library") }, \
334 { "pcrel", MASK_PCREL, \
335 N_("Generate pc-relative code") }, \
336 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
337 N_("Do not use unaligned memory references") }, \
338 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
339 N_("Use unaligned memory references") }, \
341 N_("Use different calling convention using 'rtd'") }, \
342 { "nortd", - MASK_RTD, \
343 N_("Use normal calling convention") }, \
345 { "", TARGET_DEFAULT, "" }}
346 /* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc. */
348 /* This macro is similar to `TARGET_SWITCHES' but defines names of
349 command options that have values. Its definition is an
350 initializer with a subgrouping for each command option.
352 Each subgrouping contains a string constant, that defines the
353 fixed part of the option name, and the address of a variable. The
354 variable, type `char *', is set to the variable part of the given
355 option if the fixed part matches. The actual option name is made
356 by appending `-m' to the specified name. */
357 #define TARGET_OPTIONS \
359 { "shared-library-id=", &m68k_library_id_string, \
360 N_("ID of shared library to build"), 0}, \
364 /* Sometimes certain combinations of command options do not make
365 sense on a particular target machine. You can define a macro
366 `OVERRIDE_OPTIONS' to take account of this. This macro, if
367 defined, is executed once just after all the command options have
370 Don't use this macro to turn on various extra optimizations for
371 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
373 #define OVERRIDE_OPTIONS override_options()
375 /* These are meant to be redefined in the host dependent files */
376 #define SUBTARGET_SWITCHES
377 #define SUBTARGET_OPTIONS
378 #define SUBTARGET_OVERRIDE_OPTIONS
380 /* target machine storage layout */
382 /* Define for XFmode extended real floating point support. */
383 #define LONG_DOUBLE_TYPE_SIZE 96
385 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
386 instructions, we get proper intermediate rounding, otherwise we
387 get extended precision results. */
388 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
390 /* Define this if most significant bit is lowest numbered
391 in instructions that operate on numbered bit-fields.
392 This is true for 68020 insns such as bfins and bfexts.
393 We make it true always by avoiding using the single-bit insns
394 except in special cases with constant bit numbers. */
395 #define BITS_BIG_ENDIAN 1
397 /* Define this if most significant byte of a word is the lowest numbered. */
398 /* That is true on the 68000. */
399 #define BYTES_BIG_ENDIAN 1
401 /* Define this if most significant word of a multiword number is the lowest
403 /* For 68000 we can decide arbitrarily
404 since there are no machine instructions for them.
405 So let's be consistent. */
406 #define WORDS_BIG_ENDIAN 1
408 /* Width of a word, in units (bytes). */
409 #define UNITS_PER_WORD 4
411 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
412 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
414 /* Boundary (in *bits*) on which stack pointer should be aligned. */
415 #define STACK_BOUNDARY 16
417 /* Allocation boundary (in *bits*) for the code of a function. */
418 #define FUNCTION_BOUNDARY 16
420 /* Alignment of field after `int : 0' in a structure. */
421 #define EMPTY_FIELD_BOUNDARY 16
423 /* No data type wants to be aligned rounder than this.
424 Most published ABIs say that ints should be aligned on 16 bit
425 boundaries, but cpus with 32-bit busses get better performance
426 aligned on 32-bit boundaries. ColdFires without a misalignment
427 module require 32-bit alignment. */
428 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
430 /* Set this nonzero if move instructions will actually fail to work
431 when given unaligned data. */
432 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
434 /* Maximum power of 2 that code can be aligned to. */
435 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
437 /* Maximum number of library ids we permit */
438 #define MAX_LIBRARY_ID 255
440 /* Define number of bits in most basic integer type.
441 (If undefined, default is BITS_PER_WORD). */
443 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
445 /* Define these to avoid dependence on meaning of `int'. */
447 #define WCHAR_TYPE "long int"
448 #define WCHAR_TYPE_SIZE 32
450 /* Standard register usage. */
452 /* Number of actual hardware registers.
453 The hardware registers are assigned numbers for the compiler
454 from 0 to just below FIRST_PSEUDO_REGISTER.
455 All registers that the compiler knows about must be given numbers,
456 even those that are not normally considered general registers.
457 For the 68000, we give the data registers numbers 0-7,
458 the address registers numbers 010-017,
459 and the 68881 floating point registers numbers 020-027. */
460 #define FIRST_PSEUDO_REGISTER 25
462 /* This defines the register which is used to hold the offset table for PIC. */
463 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
465 /* 1 for registers that have pervasive standard uses
466 and are not available for the register allocator.
467 On the 68000, only the stack pointer is such. */
469 #define FIXED_REGISTERS \
470 {/* Data registers. */ \
471 0, 0, 0, 0, 0, 0, 0, 0, \
473 /* Address registers. */ \
474 0, 0, 0, 0, 0, 0, 0, 1, \
476 /* Floating point registers \
478 0, 0, 0, 0, 0, 0, 0, 0, \
483 /* 1 for registers not available across function calls.
484 These must include the FIXED_REGISTERS and also any
485 registers that can be used without being saved.
486 The latter must include the registers where values are returned
487 and the register where structure-value addresses are passed.
488 Aside from that, you can include as many other registers as you like. */
489 #define CALL_USED_REGISTERS \
490 {1, 1, 0, 0, 0, 0, 0, 0, \
491 1, 1, 0, 0, 0, 0, 0, 1, \
492 1, 1, 0, 0, 0, 0, 0, 0, 1 }
494 #define REG_ALLOC_ORDER \
495 { /* d0/d1/a0/a1 */ \
500 10, 11, 12, 13, 14, 15, 24, \
502 16, 17, 18, 19, 20, 21, 22, 23\
506 /* Make sure everything's fine if we *don't* have a given processor.
507 This assumes that putting a register in fixed_regs will keep the
508 compiler's mitts completely off it. We don't bother to zero it out
509 of register classes. */
511 #define CONDITIONAL_REGISTER_USAGE \
515 if (! TARGET_68881) \
517 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
518 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
519 if (TEST_HARD_REG_BIT (x, i)) \
520 fixed_regs[i] = call_used_regs[i] = 1; \
522 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
523 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
524 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
527 /* Return number of consecutive hard regs needed starting at reg REGNO
528 to hold something of mode MODE.
529 This is ordinarily the length in words of a value of mode MODE
530 but can be less for certain modes in special long registers.
532 On the 68000, ordinary registers hold 32 bits worth;
533 for the 68881 registers, a single register is always enough for
534 anything that can be stored in them at all. */
535 #define HARD_REGNO_NREGS(REGNO, MODE) \
536 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
537 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
539 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
540 On the 68000, the cpu registers can hold any mode but the 68881 registers
541 can hold only SFmode or DFmode. */
543 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
545 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
546 || ((REGNO) >= 16 && (REGNO) < 24 \
547 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
548 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
549 && GET_MODE_UNIT_SIZE (MODE) <= 12))
552 /* Value is 1 if it is a good idea to tie two pseudo registers
553 when one has mode MODE1 and one has mode MODE2.
554 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
555 for any hard reg, then this must be 0 for correct output. */
556 #define MODES_TIEABLE_P(MODE1, MODE2) \
558 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
559 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
560 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
561 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
563 /* Specify the registers used for certain standard purposes.
564 The values of these macros are register numbers. */
566 /* m68000 pc isn't overloaded on a register. */
567 /* #define PC_REGNUM */
569 /* Register to use for pushing function arguments. */
570 #define STACK_POINTER_REGNUM 15
572 /* Base register for access to local variables of the function. */
573 #define FRAME_POINTER_REGNUM 14
575 /* Value should be nonzero if functions must have frame pointers.
576 Zero means the frame pointer need not be set up (and parms
577 may be accessed via the stack pointer) in functions that seem suitable.
578 This is computed in `reload', in reload1.c. */
579 #define FRAME_POINTER_REQUIRED 0
581 /* Base register for access to arguments of the function.
582 * This isn't a hardware register. It will be eliminated to the
583 * stack pointer or frame pointer.
585 #define ARG_POINTER_REGNUM 24
587 /* Register in which static-chain is passed to a function. */
588 #define STATIC_CHAIN_REGNUM 8
590 /* Register in which address to store a structure value
591 is passed to a function. */
592 #define M68K_STRUCT_VALUE_REGNUM 9
594 /* Define the classes of registers for register constraints in the
595 machine description. Also define ranges of constants.
597 One of the classes must always be named ALL_REGS and include all hard regs.
598 If there is more than one class, another class must be named NO_REGS
599 and contain no registers.
601 The name GENERAL_REGS must be the name of a class (or an alias for
602 another name such as ALL_REGS). This is the class of registers
603 that is allowed by "g" or "r" in a register constraint.
604 Also, registers outside this class are allocated only when
605 instructions express preferences for them.
607 The classes must be numbered in nondecreasing order; that is,
608 a larger-numbered class must never be contained completely
609 in a smaller-numbered class.
611 For any two classes, it is very desirable that there be another
612 class that represents their union. */
614 /* The 68000 has three kinds of registers, so eight classes would be
615 a complete set. One of them is not needed. */
620 GENERAL_REGS, DATA_OR_FP_REGS,
621 ADDR_OR_FP_REGS, ALL_REGS,
624 #define N_REG_CLASSES (int) LIM_REG_CLASSES
626 /* Give names of register classes as strings for dump file. */
628 #define REG_CLASS_NAMES \
629 { "NO_REGS", "DATA_REGS", \
630 "ADDR_REGS", "FP_REGS", \
631 "GENERAL_REGS", "DATA_OR_FP_REGS", \
632 "ADDR_OR_FP_REGS", "ALL_REGS" }
634 /* Define which registers fit in which classes.
635 This is an initializer for a vector of HARD_REG_SET
636 of length N_REG_CLASSES. */
638 #define REG_CLASS_CONTENTS \
640 {0x00000000}, /* NO_REGS */ \
641 {0x000000ff}, /* DATA_REGS */ \
642 {0x0100ff00}, /* ADDR_REGS */ \
643 {0x00ff0000}, /* FP_REGS */ \
644 {0x0100ffff}, /* GENERAL_REGS */ \
645 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
646 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
647 {0x01ffffff}, /* ALL_REGS */ \
650 /* The same information, inverted:
651 Return the class number of the smallest class containing
652 reg number REGNO. This could be a conditional expression
653 or could index an array. */
655 extern enum reg_class regno_reg_class[];
656 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
658 /* The class value for index registers, and the one for base regs. */
660 #define INDEX_REG_CLASS GENERAL_REGS
661 #define BASE_REG_CLASS ADDR_REGS
663 /* Get reg_class from a letter such as appears in the machine description.
664 We do a trick here to modify the effective constraints on the
665 machine description; we zorch the constraint letters that aren't
666 appropriate for a specific target. This allows us to guarantee
667 that a specific kind of register will not be used for a given target
668 without fiddling with the register classes above. */
670 #define REG_CLASS_FROM_LETTER(C) \
671 ((C) == 'a' ? ADDR_REGS : \
672 ((C) == 'd' ? DATA_REGS : \
673 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
677 /* The letters I, J, K, L and M in a register constraint string
678 can be used to stand for particular ranges of immediate operands.
679 This macro defines what the ranges are.
680 C is the letter, and VALUE is a constant value.
681 Return 1 if VALUE is in the range specified by C.
683 For the 68000, `I' is used for the range 1 to 8
684 allowed as immediate shift counts and in addq.
685 `J' is used for the range of signed numbers that fit in 16 bits.
686 `K' is for numbers that moveq can't handle.
687 `L' is for range -8 to -1, range of values that can be added with subq.
688 `M' is for numbers that moveq+notb can't handle.
689 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
690 'O' is for 16 (for rotate using swap).
691 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
693 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
694 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
695 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
696 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
697 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
698 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
699 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
700 (C) == 'O' ? (VALUE) == 16 : \
701 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
704 * A small bit of explanation:
705 * "G" defines all of the floating constants that are *NOT* 68881
706 * constants. this is so 68881 constants get reloaded and the
709 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
710 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
712 /* A C expression that defines the optional machine-dependent constraint
713 letters that can be used to segregate specific types of operands,
714 usually memory references, for the target machine. It should return 1 if
715 VALUE corresponds to the operand type represented by the constraint letter
716 C. If C is not defined as an extra constraint, the value returned should
717 be 0 regardless of VALUE. */
719 /* Letters in the range `Q' through `U' may be defined in a
720 machine-dependent fashion to stand for arbitrary operand types.
721 The machine description macro `EXTRA_CONSTRAINT' is passed the
722 operand as its first argument and the constraint letter as its
725 `Q' means address register indirect addressing mode.
726 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
727 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
728 `U' is for register offset addressing. */
730 #define EXTRA_CONSTRAINT(OP,CODE) \
733 && GET_CODE (OP) == MEM \
734 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
735 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
736 || GET_CODE (XEXP (OP, 0)) == CONST)) \
740 && (GET_CODE (OP) == SYMBOL_REF \
741 || GET_CODE (OP) == LABEL_REF \
742 || GET_CODE (OP) == CONST)) \
745 ? (GET_CODE (OP) == MEM \
746 && GET_CODE (XEXP (OP, 0)) == REG) \
749 ? (GET_CODE (OP) == MEM \
750 && GET_CODE (XEXP (OP, 0)) == PLUS \
751 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
752 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
756 /* Given an rtx X being reloaded into a reg required to be
757 in class CLASS, return the class of reg to actually use.
758 In general this is just CLASS; but on some machines
759 in some cases it is preferable to use a more restrictive class.
760 On the 68000 series, use a data reg if possible when the
761 value is a constant in the range where moveq could be used
762 and we ensure that QImodes are reloaded into data regs. */
764 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
765 ((GET_CODE (X) == CONST_INT \
766 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
767 && (CLASS) != ADDR_REGS) \
769 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
771 : (GET_CODE (X) == CONST_DOUBLE \
772 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
773 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
774 ? FP_REGS : NO_REGS) \
776 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
777 || GET_CODE (X) == LABEL_REF)) \
781 /* Force QImode output reloads from subregs to be allocated to data regs,
782 since QImode stores from address regs are not supported. We make the
783 assumption that if the class is not ADDR_REGS, then it must be a superset
786 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
787 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
791 /* Return the maximum number of consecutive registers
792 needed to represent mode MODE in a register of class CLASS. */
793 /* On the 68000, this is the size of MODE in words,
794 except in the FP regs, where a single reg is always enough. */
795 #define CLASS_MAX_NREGS(CLASS, MODE) \
796 ((CLASS) == FP_REGS ? 1 \
797 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
799 /* Moves between fp regs and other regs are two insns. */
800 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
801 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
802 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
805 /* Stack layout; function entry, exit and calling. */
807 /* Define this if pushing a word on the stack
808 makes the stack pointer a smaller address. */
809 #define STACK_GROWS_DOWNWARD
811 /* Define this if the nominal address of the stack frame
812 is at the high-address end of the local variables;
813 that is, each additional local variable allocated
814 goes at a more negative offset in the frame. */
815 #define FRAME_GROWS_DOWNWARD
817 /* Offset within stack frame to start allocating local variables at.
818 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
819 first local allocated. Otherwise, it is the offset to the BEGINNING
820 of the first local allocated. */
821 #define STARTING_FRAME_OFFSET 0
823 /* If we generate an insn to push BYTES bytes,
824 this says how many the stack pointer really advances by.
825 On the 68000, sp@- in a byte insn really pushes a word.
826 On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */
827 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
829 /* We want to avoid trying to push bytes. */
830 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
831 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
832 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
834 /* Offset of first parameter from the argument pointer register value. */
835 #define FIRST_PARM_OFFSET(FNDECL) 8
837 /* Value is the number of byte of arguments automatically
838 popped when returning from a subroutine call.
839 FUNDECL is the declaration node of the function (as a tree),
840 FUNTYPE is the data type of the function (as a tree),
841 or for a library call it is an identifier node for the subroutine name.
842 SIZE is the number of bytes of arguments passed on the stack.
844 On the 68000, the RTS insn cannot pop anything.
845 On the 68010, the RTD insn may be used to pop them if the number
846 of args is fixed, but if the number is variable then the caller
847 must pop them all. RTD can't be used for library calls now
848 because the library is compiled with the Unix compiler.
849 Use of RTD is a selectable option, since it is incompatible with
850 standard Unix calling sequences. If the option is not selected,
851 the caller must always pop the args. */
853 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
854 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
855 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
856 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
857 == void_type_node))) \
860 /* Define how to find the value returned by a function.
861 VALTYPE is the data type of the value (as a tree).
862 If the precise function being called is known, FUNC is its FUNCTION_DECL;
863 otherwise, FUNC is 0. */
865 /* On the 68000 the return value is in D0 regardless. */
867 #define FUNCTION_VALUE(VALTYPE, FUNC) \
868 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
870 /* Define how to find the value returned by a library function
871 assuming the value has mode MODE. */
873 /* On the 68000 the return value is in D0 regardless. */
875 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
877 /* 1 if N is a possible register number for a function value.
878 On the 68000, d0 is the only register thus used. */
880 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
882 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
883 more than one register. */
885 #define NEEDS_UNTYPED_CALL 0
887 /* Define this if PCC uses the nonreentrant convention for returning
888 structure and union values. */
890 #define PCC_STATIC_STRUCT_RETURN
892 /* 1 if N is a possible register number for function argument passing.
893 On the 68000, no registers are used in this way. */
895 #define FUNCTION_ARG_REGNO_P(N) 0
897 /* Define a data type for recording info about an argument list
898 during the scan of that argument list. This data type should
899 hold all necessary information about the function itself
900 and about the args processed so far, enough to enable macros
901 such as FUNCTION_ARG to determine where the next arg should go.
903 On the m68k, this is a single integer, which is a number of bytes
904 of arguments scanned so far. */
906 #define CUMULATIVE_ARGS int
908 /* Initialize a variable CUM of type CUMULATIVE_ARGS
909 for a call to a function whose data type is FNTYPE.
910 For a library call, FNTYPE is 0.
912 On the m68k, the offset starts at 0. */
914 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
917 /* Update the data in CUM to advance over an argument
918 of mode MODE and data type TYPE.
919 (TYPE is null for libcalls where that information may not be available.) */
921 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
922 ((CUM) += ((MODE) != BLKmode \
923 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
924 : (int_size_in_bytes (TYPE) + 3) & ~3))
926 /* Define where to put the arguments to a function.
927 Value is zero to push the argument on the stack,
928 or a hard register in which to store the argument.
930 MODE is the argument's machine mode.
931 TYPE is the data type of the argument (as a tree).
932 This is null for libcalls where that information may
934 CUM is a variable of type CUMULATIVE_ARGS which gives info about
935 the preceding args and about the function being called.
936 NAMED is nonzero if this argument is a named parameter
937 (otherwise it is an extra parameter matching an ellipsis).
939 On the m68k all args are always pushed. */
941 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
943 /* For an arg passed partly in registers and partly in memory,
944 this is the number of registers used.
945 For args passed entirely in registers or entirely in memory, zero. */
947 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
949 /* Output assembler code to FILE to increment profiler label # LABELNO
950 for profiling a function entry. */
952 #define FUNCTION_PROFILER(FILE, LABELNO) \
953 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
955 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
956 the stack pointer does not matter. The value is tested only in
957 functions that have frame pointers.
958 No definition is equivalent to always zero. */
960 #define EXIT_IGNORE_STACK 1
962 /* This is a hook for other tm files to change. */
963 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
965 /* Determine if the epilogue should be output as RTL.
966 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
967 #define USE_RETURN_INSN use_return_insn ()
969 /* Output assembler code for a block containing the constant parts
970 of a trampoline, leaving space for the variable parts. */
972 /* On the 68k, the trampoline looks like this:
976 WARNING: Targets that may run on 68040+ cpus must arrange for
977 the instruction cache to be flushed. Previous incarnations of
978 the m68k trampoline code attempted to get around this by either
979 using an out-of-line transfer function or pc-relative data, but
980 the fact remains that the code to jump to the transfer function
981 or the code to load the pc-relative data needs to be flushed
982 just as much as the "variable" portion of the trampoline.
983 Recognizing that a cache flush is going to be required anyway,
984 dispense with such notions and build a smaller trampoline. */
986 /* Since more instructions are required to move a template into
987 place than to create it on the spot, don't use a template. */
989 /* Length in units of the trampoline for entering a nested function. */
991 #define TRAMPOLINE_SIZE 12
993 /* Alignment required for a trampoline in bits. */
995 #define TRAMPOLINE_ALIGNMENT 16
997 /* Targets redefine this to invoke code to either flush the cache,
998 or enable stack execution (or both). */
1000 #ifndef FINALIZE_TRAMPOLINE
1001 #define FINALIZE_TRAMPOLINE(TRAMP)
1004 /* Emit RTL insns to initialize the variable parts of a trampoline.
1005 FNADDR is an RTX for the address of the function's pure code.
1006 CXT is an RTX for the static chain value for the function.
1008 We generate a two-instructions program at address TRAMP :
1012 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1014 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
1015 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
1016 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
1018 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
1019 FINALIZE_TRAMPOLINE(TRAMP); \
1022 /* This is the library routine that is used
1023 to transfer control from the trampoline
1024 to the actual nested function.
1025 It is defined for backward compatibility,
1026 for linking with object code that used the old
1027 trampoline definition. */
1029 /* A colon is used with no explicit operands
1030 to cause the template string to be scanned for %-constructs. */
1031 /* The function name __transfer_from_trampoline is not actually used.
1032 The function definition just permits use of "asm with operands"
1033 (though the operand list is empty). */
1034 #define TRANSFER_FROM_TRAMPOLINE \
1036 __transfer_from_trampoline () \
1038 register char *a0 asm ("%a0"); \
1039 asm (GLOBAL_ASM_OP "___trampoline"); \
1040 asm ("___trampoline:"); \
1041 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1042 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1046 /* Definitions for register eliminations.
1048 This is an array of structures. Each structure initializes one pair
1049 of eliminable registers. The "from" register number is given first,
1050 followed by "to". Eliminations of the same "from" register are listed
1051 in order of preference.
1053 There are two registers that can always be eliminated on the m68k.
1054 The frame pointer and the arg pointer can be replaced by either the
1055 hard frame pointer or to the stack pointer, depending upon the
1056 circumstances. The hard frame pointer is not used before reload and
1057 so it is not eligible for elimination. */
1059 #define ELIMINABLE_REGS \
1060 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1061 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
1062 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1064 /* Given FROM and TO register numbers, say whether this elimination is
1065 allowed. Frame pointer elimination is automatically handled.
1067 All other eliminations are valid. */
1069 #define CAN_ELIMINATE(FROM, TO) \
1070 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1072 /* Define the offset between two registers, one to be eliminated, and the other
1073 its replacement, at the start of a routine. */
1075 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1076 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1078 /* Addressing modes, and classification of registers for them. */
1080 #define HAVE_POST_INCREMENT 1
1082 #define HAVE_PRE_DECREMENT 1
1084 /* Macros to check register numbers against specific register classes. */
1086 /* These assume that REGNO is a hard or pseudo reg number.
1087 They give nonzero only if REGNO is a hard reg of the suitable class
1088 or a pseudo reg currently allocated to a suitable hard reg.
1089 Since they use reg_renumber, they are safe only once reg_renumber
1090 has been allocated, which happens in local-alloc.c. */
1092 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1093 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1094 #define REGNO_OK_FOR_BASE_P(REGNO) \
1095 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1096 #define REGNO_OK_FOR_DATA_P(REGNO) \
1097 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1098 #define REGNO_OK_FOR_FP_P(REGNO) \
1099 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1101 /* Now macros that check whether X is a register and also,
1102 strictly, whether it is in a specified class.
1104 These macros are specific to the 68000, and may be used only
1105 in code for printing assembler insns and in conditions for
1106 define_optimization. */
1108 /* 1 if X is a data register. */
1110 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1112 /* 1 if X is an fp register. */
1114 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1116 /* 1 if X is an address register */
1118 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1120 /* Maximum number of registers that can appear in a valid memory address. */
1122 #define MAX_REGS_PER_ADDRESS 2
1124 /* Recognize any constant value that is a valid address. */
1126 #define CONSTANT_ADDRESS_P(X) \
1127 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1128 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1129 || GET_CODE (X) == HIGH)
1131 /* Nonzero if the constant value X is a legitimate general operand.
1132 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1134 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1136 /* Nonzero if the constant value X is a legitimate general operand
1137 when generating PIC code. It is given that flag_pic is on and
1138 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1140 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1141 accepted by insn predicates, but which would otherwise fail the
1142 `general_operand' test. */
1144 #ifndef REG_OK_STRICT
1145 #define PCREL_GENERAL_OPERAND_OK 0
1147 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1150 #define LEGITIMATE_PIC_OPERAND_P(X) \
1151 (! symbolic_operand (X, VOIDmode) \
1152 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1153 || PCREL_GENERAL_OPERAND_OK)
1155 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1156 and check its validity for a certain class.
1157 We have two alternate definitions for each of them.
1158 The usual definition accepts all pseudo regs; the other rejects
1159 them unless they have been allocated suitable hard regs.
1160 The symbol REG_OK_STRICT causes the latter definition to be used.
1162 Most source files want to accept pseudo regs in the hope that
1163 they will get allocated to the class that the insn wants them to be in.
1164 Source files for reload pass need to be strict.
1165 After reload, it makes no difference, since pseudo regs have
1166 been eliminated by then. */
1168 #ifndef REG_OK_STRICT
1170 /* Nonzero if X is a hard reg that can be used as an index
1171 or if it is a pseudo reg. */
1172 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1173 /* Nonzero if X is a hard reg that can be used as a base reg
1174 or if it is a pseudo reg. */
1175 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1179 /* Nonzero if X is a hard reg that can be used as an index. */
1180 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1181 /* Nonzero if X is a hard reg that can be used as a base reg. */
1182 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1186 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1187 that is a valid memory address for an instruction.
1188 The MODE argument is the machine mode for the MEM expression
1189 that wants to use this address.
1191 When generating PIC, an address involving a SYMBOL_REF is legitimate
1192 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1193 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1194 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1196 Likewise for a LABEL_REF when generating PIC.
1198 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1200 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1201 also makes function inlining work when inline functions are called with
1202 arguments that are SUBREGs. */
1204 #define LEGITIMATE_BASE_REG_P(X) \
1205 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1206 || (GET_CODE (X) == SUBREG \
1207 && GET_CODE (SUBREG_REG (X)) == REG \
1208 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1210 #define INDIRECTABLE_1_ADDRESS_P(X) \
1211 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1212 || LEGITIMATE_BASE_REG_P (X) \
1213 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1214 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1215 || (GET_CODE (X) == PLUS \
1216 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1217 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1219 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1220 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1221 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1222 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1223 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1225 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1226 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1228 /* Only labels on dispatch tables are valid for indexing from. */
1229 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1231 if (GET_CODE (X) == LABEL_REF \
1232 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1233 && GET_CODE (temp) == JUMP_INSN \
1234 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1235 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1237 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1239 #define GO_IF_INDEXING(X, ADDR) \
1240 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1241 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1242 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1243 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1245 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1246 { GO_IF_INDEXING (X, ADDR); \
1247 if (GET_CODE (X) == PLUS) \
1248 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1249 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1250 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1251 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1252 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1253 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1255 /* ColdFire/5200 does not allow HImode index registers. */
1256 #define LEGITIMATE_INDEX_REG_P(X) \
1257 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1258 || (! TARGET_COLDFIRE \
1259 && GET_CODE (X) == SIGN_EXTEND \
1260 && GET_CODE (XEXP (X, 0)) == REG \
1261 && GET_MODE (XEXP (X, 0)) == HImode \
1262 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1263 || (GET_CODE (X) == SUBREG \
1264 && GET_CODE (SUBREG_REG (X)) == REG \
1265 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1267 #define LEGITIMATE_INDEX_P(X) \
1268 (LEGITIMATE_INDEX_REG_P (X) \
1269 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1270 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1271 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1272 && (INTVAL (XEXP (X, 1)) == 2 \
1273 || INTVAL (XEXP (X, 1)) == 4 \
1274 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1276 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1277 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1278 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1279 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1280 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1281 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1282 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1285 /* Don't call memory_address_noforce for the address to fetch
1286 the switch offset. This address is ok as it stands (see above),
1287 but memory_address_noforce would alter it. */
1288 #define PIC_CASE_VECTOR_ADDRESS(index) index
1290 /* Try machine-dependent ways of modifying an illegitimate address
1291 to be legitimate. If we find one, return the new, valid address.
1292 This macro is used in only one place: `memory_address' in explow.c.
1294 OLDX is the address as it was before break_out_memory_refs was called.
1295 In some cases it is useful to look at this to decide what needs to be done.
1297 MODE and WIN are passed so that this macro can use
1298 GO_IF_LEGITIMATE_ADDRESS.
1300 It is always safe for this macro to do nothing. It exists to recognize
1301 opportunities to optimize the output.
1303 For the 68000, we handle X+REG by loading X into a register R and
1304 using R+REG. R will go in an address reg and indexing will be used.
1305 However, if REG is a broken-out memory address or multiplication,
1306 nothing needs to be done because REG can certainly go in an address reg. */
1308 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1309 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1310 { register int ch = (X) != (OLDX); \
1311 if (GET_CODE (X) == PLUS) \
1313 if (GET_CODE (XEXP (X, 0)) == MULT) \
1314 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1315 if (GET_CODE (XEXP (X, 1)) == MULT) \
1316 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1317 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1318 && GET_CODE (XEXP (X, 0)) == REG) \
1320 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1321 if (GET_CODE (XEXP (X, 0)) == REG \
1322 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1323 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1324 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1325 { register rtx temp = gen_reg_rtx (Pmode); \
1326 register rtx val = force_operand (XEXP (X, 1), 0); \
1327 emit_move_insn (temp, val); \
1329 XEXP (X, 1) = temp; \
1331 else if (GET_CODE (XEXP (X, 1)) == REG \
1332 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1333 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1334 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1335 { register rtx temp = gen_reg_rtx (Pmode); \
1336 register rtx val = force_operand (XEXP (X, 0), 0); \
1337 emit_move_insn (temp, val); \
1339 XEXP (X, 0) = temp; \
1342 /* Go to LABEL if ADDR (a legitimate address expression)
1343 has an effect that depends on the machine mode it is used for.
1344 On the 68000, only predecrement and postincrement address depend thus
1345 (the amount of decrement or increment being the length of the operand). */
1347 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1348 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1350 /* Specify the machine mode that this machine uses
1351 for the index in the tablejump instruction. */
1352 #define CASE_VECTOR_MODE HImode
1354 /* Define as C expression which evaluates to nonzero if the tablejump
1355 instruction expects the table to contain offsets from the address of the
1357 Do not define this if the table should contain absolute addresses. */
1358 #define CASE_VECTOR_PC_RELATIVE 1
1360 /* Define this as 1 if `char' should by default be signed; else as 0. */
1361 #define DEFAULT_SIGNED_CHAR 1
1363 /* Max number of bytes we can move from memory to memory
1364 in one reasonably fast instruction. */
1367 /* Nonzero if access to memory by bytes is slow and undesirable. */
1368 #define SLOW_BYTE_ACCESS 0
1370 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1371 is done just by pretending it is already truncated. */
1372 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1374 /* We assume that the store-condition-codes instructions store 0 for false
1375 and some other value for true. This is the value stored for true. */
1377 #define STORE_FLAG_VALUE (-1)
1379 /* Specify the machine mode that pointers have.
1380 After generation of rtl, the compiler makes no further distinction
1381 between pointers and any other objects of this machine mode. */
1382 #define Pmode SImode
1384 /* A function address in a call instruction
1385 is a byte address (for indexing purposes)
1386 so give the MEM rtx a byte's mode. */
1387 #define FUNCTION_MODE QImode
1390 /* Tell final.c how to eliminate redundant test instructions. */
1392 /* Here we define machine-dependent flags and fields in cc_status
1393 (see `conditions.h'). */
1395 /* Set if the cc value is actually in the 68881, so a floating point
1396 conditional branch must be output. */
1397 #define CC_IN_68881 04000
1399 /* Store in cc_status the expressions that the condition codes will
1400 describe after execution of an instruction whose pattern is EXP.
1401 Do not alter them if the instruction would not alter the cc's. */
1403 /* On the 68000, all the insns to store in an address register fail to
1404 set the cc's. However, in some cases these instructions can make it
1405 possibly invalid to use the saved cc's. In those cases we clear out
1406 some or all of the saved cc's so they won't be used. */
1408 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1410 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1411 do { if (cc_prev_status.flags & CC_IN_68881) \
1413 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1415 return NORMAL; } while (0)
1417 /* Control the assembler format that we output. */
1419 /* Output to assembler file text saying following lines
1420 may contain character constants, extra white space, comments, etc. */
1422 #define ASM_APP_ON "#APP\n"
1424 /* Output to assembler file text saying following lines
1425 no longer contain unusual constructs. */
1427 #define ASM_APP_OFF "#NO_APP\n"
1429 /* Output before read-only data. */
1431 #define TEXT_SECTION_ASM_OP "\t.text"
1433 /* Output before writable data. */
1435 #define DATA_SECTION_ASM_OP "\t.data"
1437 #define GLOBAL_ASM_OP "\t.globl\t"
1439 /* Here are four prefixes that are used by asm_fprintf to
1440 facilitate customization for alternate assembler syntaxes.
1441 Machines with no likelihood of an alternate syntax need not
1442 define these and need not use asm_fprintf. */
1444 /* The prefix for register names. Note that REGISTER_NAMES
1445 is supposed to include this prefix. */
1447 #define REGISTER_PREFIX ""
1449 /* The prefix for local labels. You should be able to define this as
1450 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1451 without having to make any other changes to account for the specific
1452 definition. Note it is a string literal, not interpreted by printf
1455 #define LOCAL_LABEL_PREFIX ""
1457 /* The prefix to add to user-visible assembler symbols. */
1459 #define USER_LABEL_PREFIX "_"
1461 /* The prefix for immediate operands. */
1463 #define IMMEDIATE_PREFIX "#"
1465 /* How to refer to registers in assembler output.
1466 This sequence is indexed by compiler's hard-register-number (see above). */
1468 #define REGISTER_NAMES \
1469 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
1470 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
1471 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
1472 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
1473 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
1474 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
1475 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
1476 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
1477 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
1479 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
1481 /* Return a register name by index, handling %fp nicely.
1482 We don't replace %fp for targets that don't map it to %a6
1483 since it may confuse GAS. */
1484 #define M68K_REGNAME(r) ( \
1485 ((FRAME_POINTER_REGNUM == 14) \
1486 && ((r) == FRAME_POINTER_REGNUM) \
1487 && frame_pointer_needed) ? \
1488 M68K_FP_REG_NAME : reg_names[(r)])
1490 /* How to renumber registers for dbx and gdb.
1491 On the Sun-3, the floating point registers have numbers
1492 18 to 25, not 16 to 23 as they do in the compiler. */
1494 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1496 /* Before the prologue, RA is at 0(%sp). */
1497 #define INCOMING_RETURN_ADDR_RTX \
1498 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1500 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1501 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1502 Instead use the identity mapping. */
1503 #define DWARF_FRAME_REGNUM(REG) REG
1505 /* Before the prologue, the top of the frame is at 4(%sp). */
1506 #define INCOMING_FRAME_SP_OFFSET 4
1508 /* Describe how we implement __builtin_eh_return. */
1509 #define EH_RETURN_DATA_REGNO(N) \
1510 ((N) < 2 ? (N) : INVALID_REGNUM)
1511 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1512 #define EH_RETURN_HANDLER_RTX \
1513 gen_rtx_MEM (Pmode, \
1514 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1515 plus_constant (EH_RETURN_STACKADJ_RTX, \
1518 /* Select a format to encode pointers in exception handling data. CODE
1519 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1520 true if the symbol may be affected by dynamic relocations. */
1521 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1523 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1526 /* This is how to output a reference to a user-level label named NAME.
1527 `assemble_name' uses this. */
1529 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1530 asm_fprintf (FILE, "%U%s", NAME)
1532 /* This is how to store into the string LABEL
1533 the symbol_ref name of an internal numbered label where
1534 PREFIX is the class of label and NUM is the number within the class.
1535 This is suitable for output with `assemble_name'. */
1537 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1538 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1540 /* This is how to output an insn to push a register on the stack.
1541 It need not be very fast code. */
1543 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1544 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1546 /* This is how to output an insn to pop a register from the stack.
1547 It need not be very fast code. */
1549 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1550 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1552 /* This is how to output an element of a case-vector that is absolute.
1553 (The 68000 does not use such vectors,
1554 but we must define this macro anyway.) */
1556 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1557 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1559 /* This is how to output an element of a case-vector that is relative. */
1561 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1562 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1564 /* This is how to output an assembler line
1565 that says to advance the location counter
1566 to a multiple of 2**LOG bytes. */
1568 /* We don't have a way to align to more than a two-byte boundary, so do the
1569 best we can and don't complain. */
1570 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1572 fprintf (FILE, "\t.even\n");
1574 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1575 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1577 /* This says how to output an assembler line
1578 to define a global common symbol. */
1580 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1581 ( fputs (".comm ", (FILE)), \
1582 assemble_name ((FILE), (NAME)), \
1583 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1585 /* This says how to output an assembler line
1586 to define a local common symbol. */
1588 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1589 ( fputs (".lcomm ", (FILE)), \
1590 assemble_name ((FILE), (NAME)), \
1591 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1593 /* Output a float value (represented as a C double) as an immediate operand.
1594 This macro is a 68k-specific macro. */
1596 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1601 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1602 asm_fprintf ((FILE), "%I0r%s", dstr); \
1607 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1608 asm_fprintf ((FILE), "%I0x%lx", l); \
1612 /* Output a double value (represented as a C double) as an immediate operand.
1613 This macro is a 68k-specific macro. */
1614 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1615 do { char dstr[30]; \
1616 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1617 asm_fprintf (FILE, "%I0r%s", dstr); \
1620 /* Note, long double immediate operands are not actually
1621 generated by m68k.md. */
1622 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1623 do { char dstr[30]; \
1624 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1625 asm_fprintf (FILE, "%I0r%s", dstr); \
1628 /* Print operand X (an rtx) in assembler syntax to file FILE.
1629 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1630 For `%' followed by punctuation, CODE is the punctuation and X is null.
1632 On the 68000, we use several CODE characters:
1633 '.' for dot needed in Motorola-style opcode names.
1634 '-' for an operand pushing on the stack:
1635 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1636 '+' for an operand pushing on the stack:
1637 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1638 '@' for a reference to the top word on the stack:
1639 sp@, (sp) or (%sp) depending on the style of syntax.
1640 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1641 but & in SGS syntax).
1642 '!' for the fpcr register (used in some float-to-fixed conversions).
1643 '$' for the letter `s' in an op code, but only on the 68040.
1644 '&' for the letter `d' in an op code, but only on the 68040.
1645 '/' for register prefix needed by longlong.h.
1647 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1648 'd' to force memory addressing to be absolute, not relative.
1649 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1650 'o' for operands to go directly to output_operand_address (bypassing
1651 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1652 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1653 or print pair of registers as rx:ry. */
1655 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1656 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1657 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1658 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1660 /* A C compound statement to output to stdio stream STREAM the
1661 assembler syntax for an instruction operand X. X is an RTL
1664 CODE is a value that can be used to specify one of several ways
1665 of printing the operand. It is used when identical operands
1666 must be printed differently depending on the context. CODE
1667 comes from the `%' specification that was used to request
1668 printing of the operand. If the specification was just `%DIGIT'
1669 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1670 is the ASCII code for LTR.
1672 If X is a register, this macro should print the register's name.
1673 The names can be found in an array `reg_names' whose type is
1674 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1676 When the machine description has a specification `%PUNCT' (a `%'
1677 followed by a punctuation character), this macro is called with
1678 a null pointer for X and the punctuation character for CODE.
1680 See m68k.c for the m68k specific codes. */
1682 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1684 /* A C compound statement to output to stdio stream STREAM the
1685 assembler syntax for an instruction operand that is a memory
1686 reference whose address is ADDR. ADDR is an RTL expression. */
1688 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1690 /* Variables in m68k.c */
1691 extern const char *m68k_library_id_string;
1692 extern int m68k_last_compare_had_fp_operands;
1695 /* Define the codes that are matched by predicates in m68k.c. */
1697 #define PREDICATE_CODES \
1698 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1699 LABEL_REF, SUBREG, REG, MEM}}, \
1700 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1701 {"memory_src_operand", {SUBREG, MEM}}, \
1702 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1703 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1704 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1705 {"const_sint32_operand", {CONST_INT}}, \
1706 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1708 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},