1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() \
31 builtin_define ("__m68k__"); \
32 builtin_define_std ("mc68000"); \
34 builtin_define_std ("mc68060"); \
35 else if (TARGET_68040) \
36 builtin_define_std ("mc68040"); \
37 else if (TARGET_68020) \
38 builtin_define_std ("mc68020"); \
40 builtin_define ("__HAVE_68881__"); \
43 builtin_define_std ("mc68332"); \
44 builtin_define_std ("mcpu32"); \
46 if (TARGET_COLDFIRE) \
47 builtin_define ("__mcoldfire__"); \
49 builtin_define ("__mcf5200__"); \
52 builtin_define ("__mcf528x__"); \
53 builtin_define ("__mcf5200__"); \
57 builtin_define ("__mcf5300__"); \
58 builtin_define ("__mcf5307__"); \
62 builtin_define ("__mcf5400__"); \
63 builtin_define ("__mcf5407__"); \
65 if (TARGET_CF_HWDIV) \
66 builtin_define ("__mcfhwdiv__"); \
68 builtin_define ("__pic__"); \
70 builtin_define ("__PIC__"); \
71 builtin_assert ("cpu=m68k"); \
72 builtin_assert ("machine=m68k"); \
77 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
79 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
80 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
81 #define INT_OP_NO_DOT 2 /* byte, short, long */
82 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
85 #define INT_OP_GROUP INT_OP_DOT_WORD
87 /* Print subsidiary information on the compiler version in use. */
89 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
91 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
94 /* Run-time compilation parameters selecting different hardware subsets. */
96 extern int target_flags;
98 /* Macros used in the machine description to test the flags. */
100 /* Compile for a 68020 (not a 68000 or 68010). */
102 #define TARGET_68020 (target_flags & MASK_68020)
104 /* Compile 68881 insns for floating point (not library calls). */
106 #define TARGET_68881 (target_flags & MASK_68881)
108 /* Compile using 68020 bit-field insns. */
109 #define MASK_BITFIELD 4
110 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
112 /* Compile using rtd insn calling sequence.
113 This will not work unless you use prototypes at least
114 for all functions that can take varying numbers of args. */
116 #define TARGET_RTD (target_flags & MASK_RTD)
118 /* Compile passing first two args in regs 0 and 1.
119 This exists only to test compiler features that will
120 be needed for RISC chips. It is not usable
121 and is not intended to be usable on this cpu. */
122 #define MASK_REGPARM 16
123 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
125 /* Compile with 16-bit `int'. */
126 #define MASK_SHORT 32
127 #define TARGET_SHORT (target_flags & MASK_SHORT)
129 /* Optimize for 68040, but still allow execution on 68020
130 (-m68020-40 or -m68040).
131 The 68040 will execute all 68030 and 68881/2 instructions, but some
132 of them must be emulated in software by the OS. When TARGET_68040 is
133 turned on, these instructions won't be used. This code will still
134 run on a 68030 and 68881/2. */
135 #define MASK_68040 256
136 #define TARGET_68040 (target_flags & MASK_68040)
138 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
139 #define MASK_68040_ONLY 512
140 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
142 /* Optimize for 68060, but still allow execution on 68020
143 (-m68020-60 or -m68060).
144 The 68060 will execute all 68030 and 68881/2 instructions, but some
145 of them must be emulated in software by the OS. When TARGET_68060 is
146 turned on, these instructions won't be used. This code will still
147 run on a 68030 and 68881/2. */
148 #define MASK_68060 1024
149 #define TARGET_68060 (target_flags & MASK_68060)
151 /* Compile for mcf5200 */
152 #define MASK_5200 2048
153 #define TARGET_5200 (target_flags & MASK_5200)
155 /* Align ints to a word boundary. This breaks compatibility with the
156 published ABI's for structures containing ints, but produces faster
157 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
158 It's required for coldfire cpus without a misalignment module. */
159 #define MASK_ALIGN_INT 4096
160 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
162 /* Compile for a CPU32 */
163 /* A 68020 without bitfields is a good heuristic for a CPU32 */
164 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
166 /* Use PC-relative addressing modes (without using a global offset table).
167 The m68000 supports 16-bit PC-relative addressing.
168 The m68020 supports 32-bit PC-relative addressing
169 (using outer displacements).
171 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
172 treated as all containing an implicit PC-relative component, and hence
173 cannot be used directly as addresses for memory writes. See the comments
174 in m68k.c for more information. */
175 #define MASK_PCREL 8192
176 #define TARGET_PCREL (target_flags & MASK_PCREL)
178 /* Relax strict alignment. */
179 #define MASK_NO_STRICT_ALIGNMENT 16384
180 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
182 /* Build for ColdFire v3 */
183 #define MASK_CFV3 0x8000
184 #define TARGET_CFV3 (target_flags & MASK_CFV3)
186 /* Build for ColdFire v4 */
187 #define MASK_CFV4 0x10000
188 #define TARGET_CFV4 (target_flags & MASK_CFV4)
190 /* Divide support for ColdFire */
191 #define MASK_CF_HWDIV 0x40000
192 #define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
194 /* Compile for mcf528x */
195 #define MASK_528x 0x80000
196 #define TARGET_528x (target_flags & MASK_528x)
199 /* Is the target a coldfire */
200 #define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
201 #define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
203 /* Which bits can be set by specifying a coldfire */
204 #define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
206 /* Macro to define tables used to set the flags.
207 This is a list in braces of pairs in braces,
208 each pair being { "NAME", VALUE }
209 where VALUE is the bits to set or minus the bits to clear.
210 An empty string NAME is used to identify the default VALUE. */
212 #define TARGET_SWITCHES \
213 { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
214 N_("Generate code for a 68020") }, \
215 { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
216 N_("Generate code for a 68020") }, \
217 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
218 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
219 { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
220 |MASK_68020|MASK_BITFIELD|MASK_68881), \
221 N_("Generate code for a 68000") }, \
222 { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
223 |MASK_68020|MASK_BITFIELD|MASK_68881), \
224 N_("Generate code for a 68000") }, \
225 { "bitfield", MASK_BITFIELD, \
226 N_("Use the bit-field instructions") }, \
227 { "nobitfield", - MASK_BITFIELD, \
228 N_("Do not use the bit-field instructions") }, \
230 N_("Use different calling convention using 'rtd'") }, \
231 { "nortd", - MASK_RTD, \
232 N_("Use normal calling convention") }, \
233 { "short", MASK_SHORT, \
234 N_("Consider type `int' to be 16 bits wide") }, \
235 { "noshort", - MASK_SHORT, \
236 N_("Consider type `int' to be 32 bits wide") }, \
237 { "68881", MASK_68881, "" }, \
238 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
239 N_("Generate code with library calls for floating point") }, \
240 { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
241 N_("Generate code for a 68040, without any new instructions") }, \
242 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
243 { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
244 N_("Generate code for a 68060, without any new instructions") }, \
245 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
246 |MASK_68060), "" }, \
247 { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
248 N_("Generate code for a 68030") }, \
249 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
250 { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
251 N_("Generate code for a 68040") }, \
252 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
253 |MASK_68040_ONLY|MASK_68040), "" }, \
254 { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
255 N_("Generate code for a 68060") }, \
256 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
257 |MASK_68040_ONLY|MASK_68060), "" }, \
258 { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
259 |MASK_BITFIELD|MASK_68881), \
260 N_("Generate code for a 520X") }, \
261 { "5200", (MASK_5200), "" }, \
262 { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
263 |MASK_BITFIELD|MASK_68881), \
264 N_("Generate code for a 5206e") }, \
265 { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
266 { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
267 |MASK_BITFIELD|MASK_68881), \
268 N_("Generate code for a 528x") }, \
269 { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
270 { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
271 |MASK_BITFIELD|MASK_68881), \
272 N_("Generate code for a 5307") }, \
273 { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
274 { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
275 |MASK_BITFIELD|MASK_68881), \
276 N_("Generate code for a 5407") }, \
277 { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
279 N_("Generate code for a 68851") }, \
281 N_("Do no generate code for a 68851") }, \
282 { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
283 |MASK_68020|MASK_BITFIELD|MASK_68881), \
284 N_("Generate code for a 68302") }, \
285 { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
286 |MASK_BITFIELD|MASK_68881), \
287 N_("Generate code for a 68332") }, \
288 { "68332", MASK_68020, "" }, \
289 { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
290 |MASK_BITFIELD|MASK_68881), \
291 N_("Generate code for a cpu32") }, \
292 { "cpu32", MASK_68020, "" }, \
293 { "align-int", MASK_ALIGN_INT, \
294 N_("Align variables on a 32-bit boundary") }, \
295 { "no-align-int", -MASK_ALIGN_INT, \
296 N_("Align variables on a 16-bit boundary") }, \
297 { "pcrel", MASK_PCREL, \
298 N_("Generate pc-relative code") }, \
299 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
300 N_("Do not use unaligned memory references") }, \
301 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
302 N_("Use unaligned memory references") }, \
304 { "", TARGET_DEFAULT, "" }}
305 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
307 /* This macro is similar to `TARGET_SWITCHES' but defines names of
308 command options that have values. Its definition is an
309 initializer with a subgrouping for each command option.
311 Each subgrouping contains a string constant, that defines the
312 fixed part of the option name, and the address of a variable. The
313 variable, type `char *', is set to the variable part of the given
314 option if the fixed part matches. The actual option name is made
315 by appending `-m' to the specified name. */
316 #define TARGET_OPTIONS \
317 { { "align-loops=", &m68k_align_loops_string, \
318 N_("Loop code aligned to this power of 2"), 0}, \
319 { "align-jumps=", &m68k_align_jumps_string, \
320 N_("Jump targets are aligned to this power of 2"), 0}, \
321 { "align-functions=", &m68k_align_funcs_string, \
322 N_("Function starts are aligned to this power of 2"), 0}, \
326 /* Sometimes certain combinations of command options do not make
327 sense on a particular target machine. You can define a macro
328 `OVERRIDE_OPTIONS' to take account of this. This macro, if
329 defined, is executed once just after all the command options have
332 Don't use this macro to turn on various extra optimizations for
333 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
335 #define OVERRIDE_OPTIONS override_options()
337 /* These are meant to be redefined in the host dependent files */
338 #define SUBTARGET_SWITCHES
339 #define SUBTARGET_OPTIONS
340 #define SUBTARGET_OVERRIDE_OPTIONS
342 /* target machine storage layout */
344 /* Define for XFmode extended real floating point support. */
345 #define LONG_DOUBLE_TYPE_SIZE 96
347 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
348 instructions, we get proper intermediate rounding, otherwise we
349 get extended precision results. */
350 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
352 /* Define this if most significant bit is lowest numbered
353 in instructions that operate on numbered bit-fields.
354 This is true for 68020 insns such as bfins and bfexts.
355 We make it true always by avoiding using the single-bit insns
356 except in special cases with constant bit numbers. */
357 #define BITS_BIG_ENDIAN 1
359 /* Define this if most significant byte of a word is the lowest numbered. */
360 /* That is true on the 68000. */
361 #define BYTES_BIG_ENDIAN 1
363 /* Define this if most significant word of a multiword number is the lowest
365 /* For 68000 we can decide arbitrarily
366 since there are no machine instructions for them.
367 So let's be consistent. */
368 #define WORDS_BIG_ENDIAN 1
370 /* Width of a word, in units (bytes). */
371 #define UNITS_PER_WORD 4
373 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
374 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
376 /* Boundary (in *bits*) on which stack pointer should be aligned. */
377 #define STACK_BOUNDARY 16
379 /* Allocation boundary (in *bits*) for the code of a function. */
380 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
382 /* Alignment of field after `int : 0' in a structure. */
383 #define EMPTY_FIELD_BOUNDARY 16
385 /* No data type wants to be aligned rounder than this.
386 Most published ABIs say that ints should be aligned on 16 bit
387 boundaries, but cpus with 32 bit busses get better performance
388 aligned on 32 bit boundaries. Coldfires without a misalignment
389 module require 32 bit alignment. */
390 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
392 /* Set this nonzero if move instructions will actually fail to work
393 when given unaligned data. */
394 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
396 /* Maximum power of 2 that code can be aligned to. */
397 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
399 /* Align loop starts for optimal branching. */
400 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
402 /* This is how to align an instruction for optimal branching. */
403 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
405 /* Define number of bits in most basic integer type.
406 (If undefined, default is BITS_PER_WORD). */
408 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
410 /* Define these to avoid dependence on meaning of `int'. */
412 #define WCHAR_TYPE "long int"
413 #define WCHAR_TYPE_SIZE 32
415 /* Standard register usage. */
417 /* Number of actual hardware registers.
418 The hardware registers are assigned numbers for the compiler
419 from 0 to just below FIRST_PSEUDO_REGISTER.
420 All registers that the compiler knows about must be given numbers,
421 even those that are not normally considered general registers.
422 For the 68000, we give the data registers numbers 0-7,
423 the address registers numbers 010-017,
424 and the 68881 floating point registers numbers 020-027. */
425 #define FIRST_PSEUDO_REGISTER 25
427 /* This defines the register which is used to hold the offset table for PIC. */
428 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
430 /* 1 for registers that have pervasive standard uses
431 and are not available for the register allocator.
432 On the 68000, only the stack pointer is such. */
434 #define FIXED_REGISTERS \
435 {/* Data registers. */ \
436 0, 0, 0, 0, 0, 0, 0, 0, \
438 /* Address registers. */ \
439 0, 0, 0, 0, 0, 0, 0, 1, \
441 /* Floating point registers \
443 0, 0, 0, 0, 0, 0, 0, 0 }
445 /* 1 for registers not available across function calls.
446 These must include the FIXED_REGISTERS and also any
447 registers that can be used without being saved.
448 The latter must include the registers where values are returned
449 and the register where structure-value addresses are passed.
450 Aside from that, you can include as many other registers as you like. */
451 #define CALL_USED_REGISTERS \
452 {1, 1, 0, 0, 0, 0, 0, 0, \
453 1, 1, 0, 0, 0, 0, 0, 1, \
454 1, 1, 0, 0, 0, 0, 0, 0 }
457 /* Make sure everything's fine if we *don't* have a given processor.
458 This assumes that putting a register in fixed_regs will keep the
459 compiler's mitts completely off it. We don't bother to zero it out
460 of register classes. */
462 #define CONDITIONAL_REGISTER_USAGE \
466 if (! TARGET_68881) \
468 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
469 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
470 if (TEST_HARD_REG_BIT (x, i)) \
471 fixed_regs[i] = call_used_regs[i] = 1; \
473 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
474 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
475 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
478 /* Return number of consecutive hard regs needed starting at reg REGNO
479 to hold something of mode MODE.
480 This is ordinarily the length in words of a value of mode MODE
481 but can be less for certain modes in special long registers.
483 On the 68000, ordinary registers hold 32 bits worth;
484 for the 68881 registers, a single register is always enough for
485 anything that can be stored in them at all. */
486 #define HARD_REGNO_NREGS(REGNO, MODE) \
487 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
488 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
490 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
491 On the 68000, the cpu registers can hold any mode but the 68881 registers
492 can hold only SFmode or DFmode. */
494 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
496 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
497 || ((REGNO) >= 16 && (REGNO) < 24 \
498 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
499 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
500 && GET_MODE_UNIT_SIZE (MODE) <= 12))
503 /* Value is 1 if it is a good idea to tie two pseudo registers
504 when one has mode MODE1 and one has mode MODE2.
505 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
506 for any hard reg, then this must be 0 for correct output. */
507 #define MODES_TIEABLE_P(MODE1, MODE2) \
509 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
510 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
511 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
512 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
514 /* Specify the registers used for certain standard purposes.
515 The values of these macros are register numbers. */
517 /* m68000 pc isn't overloaded on a register. */
518 /* #define PC_REGNUM */
520 /* Register to use for pushing function arguments. */
521 #define STACK_POINTER_REGNUM 15
523 /* Base register for access to local variables of the function. */
524 #define FRAME_POINTER_REGNUM 14
526 /* Value should be nonzero if functions must have frame pointers.
527 Zero means the frame pointer need not be set up (and parms
528 may be accessed via the stack pointer) in functions that seem suitable.
529 This is computed in `reload', in reload1.c. */
530 #define FRAME_POINTER_REQUIRED 0
532 /* Base register for access to arguments of the function.
533 * This isn't a hardware register. It will be eliminated to the
534 * stack pointer or frame pointer.
536 #define ARG_POINTER_REGNUM 24
538 /* Register in which static-chain is passed to a function. */
539 #define STATIC_CHAIN_REGNUM 8
541 /* Register in which address to store a structure value
542 is passed to a function. */
543 #define STRUCT_VALUE_REGNUM 9
545 /* Define the classes of registers for register constraints in the
546 machine description. Also define ranges of constants.
548 One of the classes must always be named ALL_REGS and include all hard regs.
549 If there is more than one class, another class must be named NO_REGS
550 and contain no registers.
552 The name GENERAL_REGS must be the name of a class (or an alias for
553 another name such as ALL_REGS). This is the class of registers
554 that is allowed by "g" or "r" in a register constraint.
555 Also, registers outside this class are allocated only when
556 instructions express preferences for them.
558 The classes must be numbered in nondecreasing order; that is,
559 a larger-numbered class must never be contained completely
560 in a smaller-numbered class.
562 For any two classes, it is very desirable that there be another
563 class that represents their union. */
565 /* The 68000 has three kinds of registers, so eight classes would be
566 a complete set. One of them is not needed. */
571 GENERAL_REGS, DATA_OR_FP_REGS,
572 ADDR_OR_FP_REGS, ALL_REGS,
575 #define N_REG_CLASSES (int) LIM_REG_CLASSES
577 /* Give names of register classes as strings for dump file. */
579 #define REG_CLASS_NAMES \
580 { "NO_REGS", "DATA_REGS", \
581 "ADDR_REGS", "FP_REGS", \
582 "GENERAL_REGS", "DATA_OR_FP_REGS", \
583 "ADDR_OR_FP_REGS", "ALL_REGS" }
585 /* Define which registers fit in which classes.
586 This is an initializer for a vector of HARD_REG_SET
587 of length N_REG_CLASSES. */
589 #define REG_CLASS_CONTENTS \
591 {0x00000000}, /* NO_REGS */ \
592 {0x000000ff}, /* DATA_REGS */ \
593 {0x0000ff00}, /* ADDR_REGS */ \
594 {0x00ff0000}, /* FP_REGS */ \
595 {0x0000ffff}, /* GENERAL_REGS */ \
596 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
597 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
598 {0x00ffffff}, /* ALL_REGS */ \
601 /* The same information, inverted:
602 Return the class number of the smallest class containing
603 reg number REGNO. This could be a conditional expression
604 or could index an array. */
606 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
608 /* The class value for index registers, and the one for base regs. */
610 #define INDEX_REG_CLASS GENERAL_REGS
611 #define BASE_REG_CLASS ADDR_REGS
613 /* Get reg_class from a letter such as appears in the machine description.
614 We do a trick here to modify the effective constraints on the
615 machine description; we zorch the constraint letters that aren't
616 appropriate for a specific target. This allows us to guarantee
617 that a specific kind of register will not be used for a given target
618 without fiddling with the register classes above. */
620 #define REG_CLASS_FROM_LETTER(C) \
621 ((C) == 'a' ? ADDR_REGS : \
622 ((C) == 'd' ? DATA_REGS : \
623 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
627 /* The letters I, J, K, L and M in a register constraint string
628 can be used to stand for particular ranges of immediate operands.
629 This macro defines what the ranges are.
630 C is the letter, and VALUE is a constant value.
631 Return 1 if VALUE is in the range specified by C.
633 For the 68000, `I' is used for the range 1 to 8
634 allowed as immediate shift counts and in addq.
635 `J' is used for the range of signed numbers that fit in 16 bits.
636 `K' is for numbers that moveq can't handle.
637 `L' is for range -8 to -1, range of values that can be added with subq.
638 `M' is for numbers that moveq+notb can't handle.
639 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
640 'O' is for 16 (for rotate using swap).
641 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
643 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
644 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
645 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
646 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
647 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
648 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
649 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
650 (C) == 'O' ? (VALUE) == 16 : \
651 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
654 * A small bit of explanation:
655 * "G" defines all of the floating constants that are *NOT* 68881
656 * constants. this is so 68881 constants get reloaded and the
659 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
660 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
662 /* A C expression that defines the optional machine-dependent constraint
663 letters that can be used to segregate specific types of operands,
664 usually memory references, for the target machine. It should return 1 if
665 VALUE corresponds to the operand type represented by the constraint letter
666 C. If C is not defined as an extra constraint, the value returned should
667 be 0 regardless of VALUE. */
669 /* Letters in the range `Q' through `U' may be defined in a
670 machine-dependent fashion to stand for arbitrary operand types.
671 The machine description macro `EXTRA_CONSTRAINT' is passed the
672 operand as its first argument and the constraint letter as its
675 `Q' means address register indirect addressing mode.
676 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
677 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
679 #define EXTRA_CONSTRAINT(OP,CODE) \
682 && GET_CODE (OP) == MEM \
683 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
684 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
685 || GET_CODE (XEXP (OP, 0)) == CONST)) \
689 && (GET_CODE (OP) == SYMBOL_REF \
690 || GET_CODE (OP) == LABEL_REF \
691 || GET_CODE (OP) == CONST)) \
694 ? (GET_CODE (OP) == MEM \
695 && GET_CODE (XEXP (OP, 0)) == REG) \
699 /* Given an rtx X being reloaded into a reg required to be
700 in class CLASS, return the class of reg to actually use.
701 In general this is just CLASS; but on some machines
702 in some cases it is preferable to use a more restrictive class.
703 On the 68000 series, use a data reg if possible when the
704 value is a constant in the range where moveq could be used
705 and we ensure that QImodes are reloaded into data regs. */
707 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
708 ((GET_CODE (X) == CONST_INT \
709 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
710 && (CLASS) != ADDR_REGS) \
712 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
714 : (GET_CODE (X) == CONST_DOUBLE \
715 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
716 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
717 ? FP_REGS : NO_REGS) \
719 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
720 || GET_CODE (X) == LABEL_REF)) \
724 /* Force QImode output reloads from subregs to be allocated to data regs,
725 since QImode stores from address regs are not supported. We make the
726 assumption that if the class is not ADDR_REGS, then it must be a superset
729 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
730 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
734 /* Return the maximum number of consecutive registers
735 needed to represent mode MODE in a register of class CLASS. */
736 /* On the 68000, this is the size of MODE in words,
737 except in the FP regs, where a single reg is always enough. */
738 #define CLASS_MAX_NREGS(CLASS, MODE) \
739 ((CLASS) == FP_REGS ? 1 \
740 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
742 /* Moves between fp regs and other regs are two insns. */
743 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
744 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
745 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
748 /* Stack layout; function entry, exit and calling. */
750 /* Define this if pushing a word on the stack
751 makes the stack pointer a smaller address. */
752 #define STACK_GROWS_DOWNWARD
754 /* Define this if the nominal address of the stack frame
755 is at the high-address end of the local variables;
756 that is, each additional local variable allocated
757 goes at a more negative offset in the frame. */
758 #define FRAME_GROWS_DOWNWARD
760 /* Offset within stack frame to start allocating local variables at.
761 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
762 first local allocated. Otherwise, it is the offset to the BEGINNING
763 of the first local allocated. */
764 #define STARTING_FRAME_OFFSET 0
766 /* If we generate an insn to push BYTES bytes,
767 this says how many the stack pointer really advances by.
768 On the 68000, sp@- in a byte insn really pushes a word.
769 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
770 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
772 /* We want to avoid trying to push bytes. */
773 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
774 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
775 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
777 /* Offset of first parameter from the argument pointer register value. */
778 #define FIRST_PARM_OFFSET(FNDECL) 8
780 /* Value is the number of byte of arguments automatically
781 popped when returning from a subroutine call.
782 FUNDECL is the declaration node of the function (as a tree),
783 FUNTYPE is the data type of the function (as a tree),
784 or for a library call it is an identifier node for the subroutine name.
785 SIZE is the number of bytes of arguments passed on the stack.
787 On the 68000, the RTS insn cannot pop anything.
788 On the 68010, the RTD insn may be used to pop them if the number
789 of args is fixed, but if the number is variable then the caller
790 must pop them all. RTD can't be used for library calls now
791 because the library is compiled with the Unix compiler.
792 Use of RTD is a selectable option, since it is incompatible with
793 standard Unix calling sequences. If the option is not selected,
794 the caller must always pop the args. */
796 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
797 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
798 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
799 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
800 == void_type_node))) \
803 /* Define how to find the value returned by a function.
804 VALTYPE is the data type of the value (as a tree).
805 If the precise function being called is known, FUNC is its FUNCTION_DECL;
806 otherwise, FUNC is 0. */
808 /* On the 68000 the return value is in D0 regardless. */
810 #define FUNCTION_VALUE(VALTYPE, FUNC) \
811 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
813 /* Define how to find the value returned by a library function
814 assuming the value has mode MODE. */
816 /* On the 68000 the return value is in D0 regardless. */
818 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
820 /* 1 if N is a possible register number for a function value.
821 On the 68000, d0 is the only register thus used. */
823 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
825 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
826 more than one register. */
828 #define NEEDS_UNTYPED_CALL 0
830 /* Define this if PCC uses the nonreentrant convention for returning
831 structure and union values. */
833 #define PCC_STATIC_STRUCT_RETURN
835 /* 1 if N is a possible register number for function argument passing.
836 On the 68000, no registers are used in this way. */
838 #define FUNCTION_ARG_REGNO_P(N) 0
840 /* Define a data type for recording info about an argument list
841 during the scan of that argument list. This data type should
842 hold all necessary information about the function itself
843 and about the args processed so far, enough to enable macros
844 such as FUNCTION_ARG to determine where the next arg should go.
846 On the m68k, this is a single integer, which is a number of bytes
847 of arguments scanned so far. */
849 #define CUMULATIVE_ARGS int
851 /* Initialize a variable CUM of type CUMULATIVE_ARGS
852 for a call to a function whose data type is FNTYPE.
853 For a library call, FNTYPE is 0.
855 On the m68k, the offset starts at 0. */
857 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
860 /* Update the data in CUM to advance over an argument
861 of mode MODE and data type TYPE.
862 (TYPE is null for libcalls where that information may not be available.) */
864 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
865 ((CUM) += ((MODE) != BLKmode \
866 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
867 : (int_size_in_bytes (TYPE) + 3) & ~3))
869 /* Define where to put the arguments to a function.
870 Value is zero to push the argument on the stack,
871 or a hard register in which to store the argument.
873 MODE is the argument's machine mode.
874 TYPE is the data type of the argument (as a tree).
875 This is null for libcalls where that information may
877 CUM is a variable of type CUMULATIVE_ARGS which gives info about
878 the preceding args and about the function being called.
879 NAMED is nonzero if this argument is a named parameter
880 (otherwise it is an extra parameter matching an ellipsis). */
882 /* On the 68000 all args are pushed, except if -mregparm is specified
883 then the first two words of arguments are passed in d0, d1.
884 *NOTE* -mregparm does not work.
885 It exists only to test register calling conventions. */
887 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
888 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
890 /* For an arg passed partly in registers and partly in memory,
891 this is the number of registers used.
892 For args passed entirely in registers or entirely in memory, zero. */
894 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
895 ((TARGET_REGPARM && (CUM) < 8 \
896 && 8 < ((CUM) + ((MODE) == BLKmode \
897 ? int_size_in_bytes (TYPE) \
898 : GET_MODE_SIZE (MODE)))) \
901 /* Output assembler code to FILE to increment profiler label # LABELNO
902 for profiling a function entry. */
904 #define FUNCTION_PROFILER(FILE, LABELNO) \
905 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
907 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
908 the stack pointer does not matter. The value is tested only in
909 functions that have frame pointers.
910 No definition is equivalent to always zero. */
912 #define EXIT_IGNORE_STACK 1
914 /* This is a hook for other tm files to change. */
915 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
917 /* Determine if the epilogue should be output as RTL.
918 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
919 #define USE_RETURN_INSN use_return_insn ()
921 /* Output assembler code for a block containing the constant parts
922 of a trampoline, leaving space for the variable parts. */
924 /* On the 68k, the trampoline looks like this:
928 WARNING: Targets that may run on 68040+ cpus must arrange for
929 the instruction cache to be flushed. Previous incarnations of
930 the m68k trampoline code attempted to get around this by either
931 using an out-of-line transfer function or pc-relative data, but
932 the fact remains that the code to jump to the transfer function
933 or the code to load the pc-relative data needs to be flushed
934 just as much as the "variable" portion of the trampoline.
935 Recognizing that a cache flush is going to be required anyway,
936 dispense with such notions and build a smaller trampoline. */
938 /* Since more instructions are required to move a template into
939 place than to create it on the spot, don't use a template. */
941 /* Length in units of the trampoline for entering a nested function. */
943 #define TRAMPOLINE_SIZE 12
945 /* Alignment required for a trampoline in bits. */
947 #define TRAMPOLINE_ALIGNMENT 16
949 /* Targets redefine this to invoke code to either flush the cache,
950 or enable stack execution (or both). */
952 #ifndef FINALIZE_TRAMPOLINE
953 #define FINALIZE_TRAMPOLINE(TRAMP)
956 /* Emit RTL insns to initialize the variable parts of a trampoline.
957 FNADDR is an RTX for the address of the function's pure code.
958 CXT is an RTX for the static chain value for the function.
960 We generate a two-instructions program at address TRAMP :
964 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
966 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
967 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
968 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
970 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
971 FINALIZE_TRAMPOLINE(TRAMP); \
974 /* This is the library routine that is used
975 to transfer control from the trampoline
976 to the actual nested function.
977 It is defined for backward compatibility,
978 for linking with object code that used the old
979 trampoline definition. */
981 /* A colon is used with no explicit operands
982 to cause the template string to be scanned for %-constructs. */
983 /* The function name __transfer_from_trampoline is not actually used.
984 The function definition just permits use of "asm with operands"
985 (though the operand list is empty). */
986 #define TRANSFER_FROM_TRAMPOLINE \
988 __transfer_from_trampoline () \
990 register char *a0 asm ("%a0"); \
991 asm (GLOBAL_ASM_OP "___trampoline"); \
992 asm ("___trampoline:"); \
993 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
994 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
998 /* Definitions for register eliminations.
1000 This is an array of structures. Each structure initializes one pair
1001 of eliminable registers. The "from" register number is given first,
1002 followed by "to". Eliminations of the same "from" register are listed
1003 in order of preference.
1005 There are two registers that can always be eliminated on the m68k.
1006 The frame pointer and the arg pointer can be replaced by either the
1007 hard frame pointer or to the stack pointer, depending upon the
1008 circumstances. The hard frame pointer is not used before reload and
1009 so it is not eligible for elimination. */
1011 #define ELIMINABLE_REGS \
1012 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1013 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
1014 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
1016 /* Given FROM and TO register numbers, say whether this elimination is
1017 allowed. Frame pointer elimination is automatically handled.
1019 All other eliminations are valid. */
1021 #define CAN_ELIMINATE(FROM, TO) \
1022 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1024 /* Define the offset between two registers, one to be eliminated, and the other
1025 its replacement, at the start of a routine. */
1027 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1028 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
1030 /* Addressing modes, and classification of registers for them. */
1032 #define HAVE_POST_INCREMENT 1
1034 #define HAVE_PRE_DECREMENT 1
1036 /* Macros to check register numbers against specific register classes. */
1038 /* These assume that REGNO is a hard or pseudo reg number.
1039 They give nonzero only if REGNO is a hard reg of the suitable class
1040 or a pseudo reg currently allocated to a suitable hard reg.
1041 Since they use reg_renumber, they are safe only once reg_renumber
1042 has been allocated, which happens in local-alloc.c. */
1044 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1045 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1046 #define REGNO_OK_FOR_BASE_P(REGNO) \
1047 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1048 #define REGNO_OK_FOR_DATA_P(REGNO) \
1049 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1050 #define REGNO_OK_FOR_FP_P(REGNO) \
1051 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1053 /* Now macros that check whether X is a register and also,
1054 strictly, whether it is in a specified class.
1056 These macros are specific to the 68000, and may be used only
1057 in code for printing assembler insns and in conditions for
1058 define_optimization. */
1060 /* 1 if X is a data register. */
1062 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1064 /* 1 if X is an fp register. */
1066 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1068 /* 1 if X is an address register */
1070 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1072 /* Maximum number of registers that can appear in a valid memory address. */
1074 #define MAX_REGS_PER_ADDRESS 2
1076 /* Recognize any constant value that is a valid address. */
1078 #define CONSTANT_ADDRESS_P(X) \
1079 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1080 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1081 || GET_CODE (X) == HIGH)
1083 /* Nonzero if the constant value X is a legitimate general operand.
1084 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1086 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
1088 /* Nonzero if the constant value X is a legitimate general operand
1089 when generating PIC code. It is given that flag_pic is on and
1090 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1092 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1093 accepted by insn predicates, but which would otherwise fail the
1094 `general_operand' test. */
1096 #ifndef REG_OK_STRICT
1097 #define PCREL_GENERAL_OPERAND_OK 0
1099 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1102 #define LEGITIMATE_PIC_OPERAND_P(X) \
1103 (! symbolic_operand (X, VOIDmode) \
1104 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1105 || PCREL_GENERAL_OPERAND_OK)
1107 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1108 and check its validity for a certain class.
1109 We have two alternate definitions for each of them.
1110 The usual definition accepts all pseudo regs; the other rejects
1111 them unless they have been allocated suitable hard regs.
1112 The symbol REG_OK_STRICT causes the latter definition to be used.
1114 Most source files want to accept pseudo regs in the hope that
1115 they will get allocated to the class that the insn wants them to be in.
1116 Source files for reload pass need to be strict.
1117 After reload, it makes no difference, since pseudo regs have
1118 been eliminated by then. */
1120 #ifndef REG_OK_STRICT
1122 /* Nonzero if X is a hard reg that can be used as an index
1123 or if it is a pseudo reg. */
1124 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1125 /* Nonzero if X is a hard reg that can be used as a base reg
1126 or if it is a pseudo reg. */
1127 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1131 /* Nonzero if X is a hard reg that can be used as an index. */
1132 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1133 /* Nonzero if X is a hard reg that can be used as a base reg. */
1134 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1138 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1139 that is a valid memory address for an instruction.
1140 The MODE argument is the machine mode for the MEM expression
1141 that wants to use this address.
1143 When generating PIC, an address involving a SYMBOL_REF is legitimate
1144 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1145 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1146 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1148 Likewise for a LABEL_REF when generating PIC.
1150 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1152 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1153 also makes function inlining work when inline functions are called with
1154 arguments that are SUBREGs. */
1156 #define LEGITIMATE_BASE_REG_P(X) \
1157 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1158 || (GET_CODE (X) == SUBREG \
1159 && GET_CODE (SUBREG_REG (X)) == REG \
1160 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1162 #define INDIRECTABLE_1_ADDRESS_P(X) \
1163 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1164 || LEGITIMATE_BASE_REG_P (X) \
1165 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1166 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1167 || (GET_CODE (X) == PLUS \
1168 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1169 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1171 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1172 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1173 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1174 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1175 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1177 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1178 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1180 /* Only labels on dispatch tables are valid for indexing from. */
1181 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1183 if (GET_CODE (X) == LABEL_REF \
1184 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1185 && GET_CODE (temp) == JUMP_INSN \
1186 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1187 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1189 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1191 #define GO_IF_INDEXING(X, ADDR) \
1192 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1193 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1194 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1195 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1197 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1198 { GO_IF_INDEXING (X, ADDR); \
1199 if (GET_CODE (X) == PLUS) \
1200 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1201 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1202 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1203 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1204 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1205 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1207 /* coldfire/5200 does not allow HImode index registers. */
1208 #define LEGITIMATE_INDEX_REG_P(X) \
1209 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1210 || (! TARGET_COLDFIRE \
1211 && GET_CODE (X) == SIGN_EXTEND \
1212 && GET_CODE (XEXP (X, 0)) == REG \
1213 && GET_MODE (XEXP (X, 0)) == HImode \
1214 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1215 || (GET_CODE (X) == SUBREG \
1216 && GET_CODE (SUBREG_REG (X)) == REG \
1217 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1219 #define LEGITIMATE_INDEX_P(X) \
1220 (LEGITIMATE_INDEX_REG_P (X) \
1221 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1222 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1223 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1224 && (INTVAL (XEXP (X, 1)) == 2 \
1225 || INTVAL (XEXP (X, 1)) == 4 \
1226 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1228 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1229 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1230 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1231 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1232 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1233 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1234 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1237 /* Don't call memory_address_noforce for the address to fetch
1238 the switch offset. This address is ok as it stands (see above),
1239 but memory_address_noforce would alter it. */
1240 #define PIC_CASE_VECTOR_ADDRESS(index) index
1242 /* Try machine-dependent ways of modifying an illegitimate address
1243 to be legitimate. If we find one, return the new, valid address.
1244 This macro is used in only one place: `memory_address' in explow.c.
1246 OLDX is the address as it was before break_out_memory_refs was called.
1247 In some cases it is useful to look at this to decide what needs to be done.
1249 MODE and WIN are passed so that this macro can use
1250 GO_IF_LEGITIMATE_ADDRESS.
1252 It is always safe for this macro to do nothing. It exists to recognize
1253 opportunities to optimize the output.
1255 For the 68000, we handle X+REG by loading X into a register R and
1256 using R+REG. R will go in an address reg and indexing will be used.
1257 However, if REG is a broken-out memory address or multiplication,
1258 nothing needs to be done because REG can certainly go in an address reg. */
1260 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1261 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1262 { register int ch = (X) != (OLDX); \
1263 if (GET_CODE (X) == PLUS) \
1265 if (GET_CODE (XEXP (X, 0)) == MULT) \
1266 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1267 if (GET_CODE (XEXP (X, 1)) == MULT) \
1268 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1269 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1270 && GET_CODE (XEXP (X, 0)) == REG) \
1272 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1273 if (GET_CODE (XEXP (X, 0)) == REG \
1274 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1275 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1276 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1277 { register rtx temp = gen_reg_rtx (Pmode); \
1278 register rtx val = force_operand (XEXP (X, 1), 0); \
1279 emit_move_insn (temp, val); \
1281 XEXP (X, 1) = temp; \
1283 else if (GET_CODE (XEXP (X, 1)) == REG \
1284 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1285 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1286 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1287 { register rtx temp = gen_reg_rtx (Pmode); \
1288 register rtx val = force_operand (XEXP (X, 0), 0); \
1289 emit_move_insn (temp, val); \
1291 XEXP (X, 0) = temp; \
1294 /* Go to LABEL if ADDR (a legitimate address expression)
1295 has an effect that depends on the machine mode it is used for.
1296 On the 68000, only predecrement and postincrement address depend thus
1297 (the amount of decrement or increment being the length of the operand). */
1299 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1300 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1302 /* Specify the machine mode that this machine uses
1303 for the index in the tablejump instruction. */
1304 #define CASE_VECTOR_MODE HImode
1306 /* Define as C expression which evaluates to nonzero if the tablejump
1307 instruction expects the table to contain offsets from the address of the
1309 Do not define this if the table should contain absolute addresses. */
1310 #define CASE_VECTOR_PC_RELATIVE 1
1312 /* Define this as 1 if `char' should by default be signed; else as 0. */
1313 #define DEFAULT_SIGNED_CHAR 1
1315 /* Don't cse the address of the function being compiled. */
1316 #define NO_RECURSIVE_FUNCTION_CSE
1318 /* Max number of bytes we can move from memory to memory
1319 in one reasonably fast instruction. */
1322 /* Nonzero if access to memory by bytes is slow and undesirable. */
1323 #define SLOW_BYTE_ACCESS 0
1325 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1326 is done just by pretending it is already truncated. */
1327 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1329 /* We assume that the store-condition-codes instructions store 0 for false
1330 and some other value for true. This is the value stored for true. */
1332 #define STORE_FLAG_VALUE (-1)
1334 /* When a prototype says `char' or `short', really pass an `int'. */
1335 #define PROMOTE_PROTOTYPES 1
1337 /* Specify the machine mode that pointers have.
1338 After generation of rtl, the compiler makes no further distinction
1339 between pointers and any other objects of this machine mode. */
1340 #define Pmode SImode
1342 /* A function address in a call instruction
1343 is a byte address (for indexing purposes)
1344 so give the MEM rtx a byte's mode. */
1345 #define FUNCTION_MODE QImode
1348 /* Tell final.c how to eliminate redundant test instructions. */
1350 /* Here we define machine-dependent flags and fields in cc_status
1351 (see `conditions.h'). */
1353 /* Set if the cc value is actually in the 68881, so a floating point
1354 conditional branch must be output. */
1355 #define CC_IN_68881 04000
1357 /* Store in cc_status the expressions that the condition codes will
1358 describe after execution of an instruction whose pattern is EXP.
1359 Do not alter them if the instruction would not alter the cc's. */
1361 /* On the 68000, all the insns to store in an address register fail to
1362 set the cc's. However, in some cases these instructions can make it
1363 possibly invalid to use the saved cc's. In those cases we clear out
1364 some or all of the saved cc's so they won't be used. */
1366 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1368 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1369 { if (cc_prev_status.flags & CC_IN_68881) \
1371 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1375 /* Control the assembler format that we output. */
1377 /* Output to assembler file text saying following lines
1378 may contain character constants, extra white space, comments, etc. */
1380 #define ASM_APP_ON "#APP\n"
1382 /* Output to assembler file text saying following lines
1383 no longer contain unusual constructs. */
1385 #define ASM_APP_OFF "#NO_APP\n"
1387 /* Output before read-only data. */
1389 #define TEXT_SECTION_ASM_OP "\t.text"
1391 /* Output before writable data. */
1393 #define DATA_SECTION_ASM_OP "\t.data"
1395 #define GLOBAL_ASM_OP "\t.globl\t"
1397 /* Here are four prefixes that are used by asm_fprintf to
1398 facilitate customization for alternate assembler syntaxes.
1399 Machines with no likelihood of an alternate syntax need not
1400 define these and need not use asm_fprintf. */
1402 /* The prefix for register names. Note that REGISTER_NAMES
1403 is supposed to include this prefix. */
1405 #define REGISTER_PREFIX ""
1407 /* The prefix for local labels. You should be able to define this as
1408 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1409 without having to make any other changes to account for the specific
1410 definition. Note it is a string literal, not interpreted by printf
1413 #define LOCAL_LABEL_PREFIX ""
1415 /* The prefix to add to user-visible assembler symbols. */
1417 #define USER_LABEL_PREFIX "_"
1419 /* The prefix for immediate operands. */
1421 #define IMMEDIATE_PREFIX "#"
1423 /* How to refer to registers in assembler output.
1424 This sequence is indexed by compiler's hard-register-number (see above). */
1426 #define REGISTER_NAMES \
1427 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1428 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1429 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" }
1431 /* How to renumber registers for dbx and gdb.
1432 On the Sun-3, the floating point registers have numbers
1433 18 to 25, not 16 to 23 as they do in the compiler. */
1435 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1437 /* Before the prologue, RA is at 0(%sp). */
1438 #define INCOMING_RETURN_ADDR_RTX \
1439 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1441 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1442 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1443 Instead use the identity mapping. */
1444 #define DWARF_FRAME_REGNUM(REG) REG
1446 /* Before the prologue, the top of the frame is at 4(%sp). */
1447 #define INCOMING_FRAME_SP_OFFSET 4
1449 /* Describe how we implement __builtin_eh_return. */
1450 #define EH_RETURN_DATA_REGNO(N) \
1451 ((N) < 2 ? (N) : INVALID_REGNUM)
1452 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1453 #define EH_RETURN_HANDLER_RTX \
1454 gen_rtx_MEM (Pmode, \
1455 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1456 plus_constant (EH_RETURN_STACKADJ_RTX, \
1459 /* Select a format to encode pointers in exception handling data. CODE
1460 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1461 true if the symbol may be affected by dynamic relocations. */
1462 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1464 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1467 /* This is how to output a reference to a user-level label named NAME.
1468 `assemble_name' uses this. */
1470 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1471 asm_fprintf (FILE, "%U%s", NAME)
1473 /* This is how to store into the string LABEL
1474 the symbol_ref name of an internal numbered label where
1475 PREFIX is the class of label and NUM is the number within the class.
1476 This is suitable for output with `assemble_name'. */
1478 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1479 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1481 /* This is how to output an insn to push a register on the stack.
1482 It need not be very fast code. */
1484 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1485 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1487 /* This is how to output an insn to pop a register from the stack.
1488 It need not be very fast code. */
1490 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1491 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1493 /* This is how to output an element of a case-vector that is absolute.
1494 (The 68000 does not use such vectors,
1495 but we must define this macro anyway.) */
1497 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1498 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1500 /* This is how to output an element of a case-vector that is relative. */
1502 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1503 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1505 /* This is how to output an assembler line
1506 that says to advance the location counter
1507 to a multiple of 2**LOG bytes. */
1509 /* We don't have a way to align to more than a two-byte boundary, so do the
1510 best we can and don't complain. */
1511 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1513 fprintf (FILE, "\t.even\n");
1515 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1516 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1518 /* This says how to output an assembler line
1519 to define a global common symbol. */
1521 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1522 ( fputs (".comm ", (FILE)), \
1523 assemble_name ((FILE), (NAME)), \
1524 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1526 /* This says how to output an assembler line
1527 to define a local common symbol. */
1529 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1530 ( fputs (".lcomm ", (FILE)), \
1531 assemble_name ((FILE), (NAME)), \
1532 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1534 /* Output a float value (represented as a C double) as an immediate operand.
1535 This macro is a 68k-specific macro. */
1537 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1542 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1543 asm_fprintf ((FILE), "%I0r%s", dstr); \
1548 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1549 asm_fprintf ((FILE), "%I0x%lx", l); \
1553 /* Output a double value (represented as a C double) as an immediate operand.
1554 This macro is a 68k-specific macro. */
1555 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1556 do { char dstr[30]; \
1557 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1558 asm_fprintf (FILE, "%I0r%s", dstr); \
1561 /* Note, long double immediate operands are not actually
1562 generated by m68k.md. */
1563 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1564 do { char dstr[30]; \
1565 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1566 asm_fprintf (FILE, "%I0r%s", dstr); \
1569 /* Print operand X (an rtx) in assembler syntax to file FILE.
1570 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1571 For `%' followed by punctuation, CODE is the punctuation and X is null.
1573 On the 68000, we use several CODE characters:
1574 '.' for dot needed in Motorola-style opcode names.
1575 '-' for an operand pushing on the stack:
1576 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1577 '+' for an operand pushing on the stack:
1578 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1579 '@' for a reference to the top word on the stack:
1580 sp@, (sp) or (%sp) depending on the style of syntax.
1581 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1582 but & in SGS syntax).
1583 '!' for the fpcr register (used in some float-to-fixed conversions).
1584 '$' for the letter `s' in an op code, but only on the 68040.
1585 '&' for the letter `d' in an op code, but only on the 68040.
1586 '/' for register prefix needed by longlong.h.
1588 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1589 'd' to force memory addressing to be absolute, not relative.
1590 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1591 'o' for operands to go directly to output_operand_address (bypassing
1592 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1593 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1594 or print pair of registers as rx:ry. */
1596 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1597 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1598 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1599 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1601 /* A C compound statement to output to stdio stream STREAM the
1602 assembler syntax for an instruction operand X. X is an RTL
1605 CODE is a value that can be used to specify one of several ways
1606 of printing the operand. It is used when identical operands
1607 must be printed differently depending on the context. CODE
1608 comes from the `%' specification that was used to request
1609 printing of the operand. If the specification was just `%DIGIT'
1610 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1611 is the ASCII code for LTR.
1613 If X is a register, this macro should print the register's name.
1614 The names can be found in an array `reg_names' whose type is
1615 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1617 When the machine description has a specification `%PUNCT' (a `%'
1618 followed by a punctuation character), this macro is called with
1619 a null pointer for X and the punctuation character for CODE.
1621 See m68k.c for the m68k specific codes. */
1623 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1625 /* A C compound statement to output to stdio stream STREAM the
1626 assembler syntax for an instruction operand that is a memory
1627 reference whose address is ADDR. ADDR is an RTL expression. */
1629 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1631 /* Variables in m68k.c */
1632 extern const char *m68k_align_loops_string;
1633 extern const char *m68k_align_jumps_string;
1634 extern const char *m68k_align_funcs_string;
1635 extern int m68k_align_loops;
1636 extern int m68k_align_jumps;
1637 extern int m68k_align_funcs;
1638 extern int m68k_last_compare_had_fp_operands;
1641 /* Define the codes that are matched by predicates in m68k.c. */
1643 #define PREDICATE_CODES \
1644 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1645 LABEL_REF, SUBREG, REG, MEM}}, \
1646 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1647 {"memory_src_operand", {SUBREG, MEM}}, \
1648 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1649 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1650 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1651 {"const_sint32_operand", {CONST_INT}}, \
1652 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1654 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},