1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Handle --with-cpu default option from configure script. */
36 #define OPTION_DEFAULT_SPECS \
37 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
38 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
39 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
40 -%(VALUE)}}}}}}}}}}}}}}}}}}}" },
42 /* Note that some other tm.h files include this one and then override
43 many of the definitions that relate to assembler syntax. */
45 #define TARGET_CPU_CPP_BUILTINS() \
48 builtin_define ("__m68k__"); \
49 builtin_define_std ("mc68000"); \
50 if (TARGET_68040_ONLY) \
53 builtin_define_std ("mc68060"); \
55 builtin_define_std ("mc68040"); \
57 else if (TUNE_68060) /* -m68020-60 */ \
59 builtin_define_std ("mc68060"); \
60 builtin_define_std ("mc68040"); \
61 builtin_define_std ("mc68030"); \
62 builtin_define_std ("mc68020"); \
64 else if (TUNE_68040) /* -m68020-40 */ \
66 builtin_define_std ("mc68040"); \
67 builtin_define_std ("mc68030"); \
68 builtin_define_std ("mc68020"); \
70 else if (TUNE_68030) \
71 builtin_define_std ("mc68030"); \
72 else if (TARGET_68020) \
73 builtin_define_std ("mc68020"); \
74 else if (TUNE_68010) \
75 builtin_define_std ("mc68010"); \
77 builtin_define ("__HAVE_68881__"); \
80 builtin_define_std ("mc68332"); \
81 builtin_define_std ("mcpu32"); \
83 if (TARGET_COLDFIRE) \
84 builtin_define ("__mcoldfire__"); \
86 builtin_define ("__mcf5200__"); \
89 builtin_define ("__mcf528x__"); \
90 builtin_define ("__mcf5200__"); \
94 builtin_define ("__mcf5300__"); \
95 builtin_define ("__mcf5307__"); \
99 builtin_define ("__mcf5400__"); \
100 builtin_define ("__mcf5407__"); \
104 builtin_define ("__mcfv4e__"); \
106 if (TARGET_CF_HWDIV) \
107 builtin_define ("__mcfhwdiv__"); \
108 builtin_assert ("cpu=m68k"); \
109 builtin_assert ("machine=m68k"); \
113 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
115 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
116 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
117 #define INT_OP_NO_DOT 2 /* byte, short, long */
118 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
120 /* Set the default. */
121 #define INT_OP_GROUP INT_OP_DOT_WORD
123 /* Compile for a CPU32. A 68020 without bitfields is a good
124 heuristic for a CPU32. */
125 #define TUNE_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
127 /* Is the target a ColdFire? */
128 #define MASK_COLDFIRE \
129 (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4 | MASK_CFV4E)
130 #define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0)
132 #define TARGET_COLDFIRE_FPU TARGET_CFV4E
134 #define TARGET_HARD_FLOAT (TARGET_68881 || TARGET_COLDFIRE_FPU)
135 /* Size (in bytes) of FPU registers. */
136 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
138 #define TARGET_ISAB TARGET_CFV4
140 #define TUNE_68000_10 (!TARGET_68020 && !TARGET_COLDFIRE)
141 #define TUNE_68010 TARGET_68010
142 #define TUNE_68030 TARGET_68030
143 #define TUNE_68040 TARGET_68040
144 #define TUNE_68060 TARGET_68060
145 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
146 #define TUNE_CFV2 TARGET_5200
148 #define OVERRIDE_OPTIONS override_options()
150 /* These are meant to be redefined in the host dependent files */
151 #define SUBTARGET_OVERRIDE_OPTIONS
153 /* target machine storage layout */
155 #define LONG_DOUBLE_TYPE_SIZE 80
157 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
158 instructions, we get proper intermediate rounding, otherwise we
159 get extended precision results. */
160 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2)
162 #define BITS_BIG_ENDIAN 1
163 #define BYTES_BIG_ENDIAN 1
164 #define WORDS_BIG_ENDIAN 1
166 #define UNITS_PER_WORD 4
168 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
169 #define STACK_BOUNDARY 16
170 #define FUNCTION_BOUNDARY 16
171 #define EMPTY_FIELD_BOUNDARY 16
173 /* No data type wants to be aligned rounder than this.
174 Most published ABIs say that ints should be aligned on 16 bit
175 boundaries, but CPUs with 32-bit busses get better performance
176 aligned on 32-bit boundaries. ColdFires without a misalignment
177 module require 32-bit alignment. */
178 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
180 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
182 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
184 /* Define these to avoid dependence on meaning of `int'. */
185 #define WCHAR_TYPE "long int"
186 #define WCHAR_TYPE_SIZE 32
188 /* Maximum number of library IDs we permit with -mid-shared-library. */
189 #define MAX_LIBRARY_ID 255
192 /* Standard register usage. */
194 /* For the m68k, we give the data registers numbers 0-7,
195 the address registers numbers 010-017 (8-15),
196 and the 68881 floating point registers numbers 020-027 (16-24).
197 We also have a fake `arg-pointer' register 030 (25) used for
198 register elimination. */
199 #define FIRST_PSEUDO_REGISTER 25
201 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
202 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
204 /* 1 for registers that have pervasive standard uses
205 and are not available for the register allocator.
206 On the m68k, only the stack pointer is such.
207 Our fake arg-pointer is obviously fixed as well. */
208 #define FIXED_REGISTERS \
209 {/* Data registers. */ \
210 0, 0, 0, 0, 0, 0, 0, 0, \
212 /* Address registers. */ \
213 0, 0, 0, 0, 0, 0, 0, 1, \
215 /* Floating point registers \
217 0, 0, 0, 0, 0, 0, 0, 0, \
222 /* 1 for registers not available across function calls.
223 These must include the FIXED_REGISTERS and also any
224 registers that can be used without being saved.
225 The latter must include the registers where values are returned
226 and the register where structure-value addresses are passed.
227 Aside from that, you can include as many other registers as you like. */
228 #define CALL_USED_REGISTERS \
229 {/* Data registers. */ \
230 1, 1, 0, 0, 0, 0, 0, 0, \
232 /* Address registers. */ \
233 1, 1, 0, 0, 0, 0, 0, 1, \
235 /* Floating point registers \
237 1, 1, 0, 0, 0, 0, 0, 0, \
242 #define REG_ALLOC_ORDER \
243 { /* d0/d1/a0/a1 */ \
248 10, 11, 12, 13, 14, 15, 24, \
250 16, 17, 18, 19, 20, 21, 22, 23\
254 /* Make sure everything's fine if we *don't* have a given processor.
255 This assumes that putting a register in fixed_regs will keep the
256 compiler's mitts completely off it. We don't bother to zero it out
257 of register classes. */
258 #define CONDITIONAL_REGISTER_USAGE \
262 if (!TARGET_HARD_FLOAT) \
264 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
265 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
266 if (TEST_HARD_REG_BIT (x, i)) \
267 fixed_regs[i] = call_used_regs[i] = 1; \
269 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
270 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
271 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
274 /* On the m68k, ordinary registers hold 32 bits worth;
275 for the 68881 registers, a single register is always enough for
276 anything that can be stored in them at all. */
277 #define HARD_REGNO_NREGS(REGNO, MODE) \
278 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
279 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
281 /* A C expression that is nonzero if hard register NEW_REG can be
282 considered for use as a rename register for OLD_REG register. */
284 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
285 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
287 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
288 On the 68000, the cpu registers can hold any mode except bytes in
289 address registers, the 68881 registers can hold only SFmode or DFmode. */
291 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
292 m68k_regno_mode_ok ((REGNO), (MODE))
294 #define MODES_TIEABLE_P(MODE1, MODE2) \
295 (! TARGET_HARD_FLOAT \
296 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
297 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
298 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
299 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
301 /* Specify the registers used for certain standard purposes.
302 The values of these macros are register numbers. */
304 #define STACK_POINTER_REGNUM 15
306 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
307 ABI uses %a6 for shared library calls, therefore the frame
308 pointer is shifted to %a5 on this target. */
309 #define FRAME_POINTER_REGNUM 14
311 #define FRAME_POINTER_REQUIRED 0
313 /* Base register for access to arguments of the function.
314 * This isn't a hardware register. It will be eliminated to the
315 * stack pointer or frame pointer.
317 #define ARG_POINTER_REGNUM 24
319 #define STATIC_CHAIN_REGNUM 8
321 /* Register in which address to store a structure value
322 is passed to a function. */
323 #define M68K_STRUCT_VALUE_REGNUM 9
327 /* The m68k has three kinds of registers, so eight classes would be
328 a complete set. One of them is not needed. */
332 GENERAL_REGS, DATA_OR_FP_REGS,
333 ADDR_OR_FP_REGS, ALL_REGS,
336 #define N_REG_CLASSES (int) LIM_REG_CLASSES
338 #define REG_CLASS_NAMES \
339 { "NO_REGS", "DATA_REGS", \
340 "ADDR_REGS", "FP_REGS", \
341 "GENERAL_REGS", "DATA_OR_FP_REGS", \
342 "ADDR_OR_FP_REGS", "ALL_REGS" }
344 #define REG_CLASS_CONTENTS \
346 {0x00000000}, /* NO_REGS */ \
347 {0x000000ff}, /* DATA_REGS */ \
348 {0x0100ff00}, /* ADDR_REGS */ \
349 {0x00ff0000}, /* FP_REGS */ \
350 {0x0100ffff}, /* GENERAL_REGS */ \
351 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
352 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
353 {0x01ffffff}, /* ALL_REGS */ \
356 extern enum reg_class regno_reg_class[];
357 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
358 #define INDEX_REG_CLASS GENERAL_REGS
359 #define BASE_REG_CLASS ADDR_REGS
361 /* We do a trick here to modify the effective constraints on the
362 machine description; we zorch the constraint letters that aren't
363 appropriate for a specific target. This allows us to guarantee
364 that a specific kind of register will not be used for a given target
365 without fiddling with the register classes above. */
366 #define REG_CLASS_FROM_LETTER(C) \
367 ((C) == 'a' ? ADDR_REGS : \
368 ((C) == 'd' ? DATA_REGS : \
369 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
370 FP_REGS : NO_REGS) : \
373 /* For the m68k, `I' is used for the range 1 to 8
374 allowed as immediate shift counts and in addq.
375 `J' is used for the range of signed numbers that fit in 16 bits.
376 `K' is for numbers that moveq can't handle.
377 `L' is for range -8 to -1, range of values that can be added with subq.
378 `M' is for numbers that moveq+notb can't handle.
379 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
380 'O' is for 16 (for rotate using swap).
381 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
382 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
383 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
384 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
385 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
386 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
387 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
388 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
389 (C) == 'O' ? (VALUE) == 16 : \
390 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
392 /* "G" defines all of the floating constants that are *NOT* 68881
393 constants. This is so 68881 constants get reloaded and the
395 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
396 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
398 /* `Q' means address register indirect addressing mode.
399 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
400 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
401 `U' is for register offset addressing. */
402 #define EXTRA_CONSTRAINT(OP,CODE) \
405 && GET_CODE (OP) == MEM \
406 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
407 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
408 || GET_CODE (XEXP (OP, 0)) == CONST)) \
412 && (GET_CODE (OP) == SYMBOL_REF \
413 || GET_CODE (OP) == LABEL_REF \
414 || GET_CODE (OP) == CONST)) \
417 ? (GET_CODE (OP) == MEM \
418 && GET_CODE (XEXP (OP, 0)) == REG) \
421 ? (GET_CODE (OP) == MEM \
422 && GET_CODE (XEXP (OP, 0)) == PLUS \
423 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
424 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
428 /* On the m68k, use a data reg if possible when the
429 value is a constant in the range where moveq could be used
430 and we ensure that QImodes are reloaded into data regs. */
431 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
432 ((GET_CODE (X) == CONST_INT \
433 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
434 && (CLASS) != ADDR_REGS) \
436 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
438 : (GET_CODE (X) == CONST_DOUBLE \
439 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
440 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
441 ? FP_REGS : NO_REGS) \
443 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
444 || GET_CODE (X) == LABEL_REF)) \
448 /* Force QImode output reloads from subregs to be allocated to data regs,
449 since QImode stores from address regs are not supported. We make the
450 assumption that if the class is not ADDR_REGS, then it must be a superset
452 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
453 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
457 /* On the m68k, this is the size of MODE in words,
458 except in the FP regs, where a single reg is always enough. */
459 #define CLASS_MAX_NREGS(CLASS, MODE) \
460 ((CLASS) == FP_REGS ? 1 \
461 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
463 /* Moves between fp regs and other regs are two insns. */
464 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
465 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
466 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
469 /* Stack layout; function entry, exit and calling. */
471 #define STACK_GROWS_DOWNWARD
472 #define FRAME_GROWS_DOWNWARD 1
473 #define STARTING_FRAME_OFFSET 0
475 /* On the 680x0, sp@- in a byte insn really pushes a word.
476 On the ColdFire, sp@- in a byte insn pushes just a byte. */
477 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
479 #define FIRST_PARM_OFFSET(FNDECL) 8
481 /* On the 68000, the RTS insn cannot pop anything.
482 On the 68010, the RTD insn may be used to pop them if the number
483 of args is fixed, but if the number is variable then the caller
484 must pop them all. RTD can't be used for library calls now
485 because the library is compiled with the Unix compiler.
486 Use of RTD is a selectable option, since it is incompatible with
487 standard Unix calling sequences. If the option is not selected,
488 the caller must always pop the args. */
489 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
490 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
491 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
492 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
493 == void_type_node))) \
496 /* On the m68k the return value is always in D0. */
497 #define FUNCTION_VALUE(VALTYPE, FUNC) \
498 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
500 /* On the m68k the return value is always in D0. */
501 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
503 /* On the m68k, D0 is the only register used. */
504 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
506 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
507 more than one register.
508 XXX This macro is m68k specific and used only for m68kemb.h. */
509 #define NEEDS_UNTYPED_CALL 0
511 #define PCC_STATIC_STRUCT_RETURN
513 /* On the m68k, all arguments are usually pushed on the stack. */
514 #define FUNCTION_ARG_REGNO_P(N) 0
516 /* On the m68k, this is a single integer, which is a number of bytes
517 of arguments scanned so far. */
518 #define CUMULATIVE_ARGS int
520 /* On the m68k, the offset starts at 0. */
521 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
524 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
525 ((CUM) += ((MODE) != BLKmode \
526 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
527 : (int_size_in_bytes (TYPE) + 3) & ~3))
529 /* On the m68k all args are always pushed. */
530 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
532 #define FUNCTION_PROFILER(FILE, LABELNO) \
533 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
535 #define EXIT_IGNORE_STACK 1
537 /* Determine if the epilogue should be output as RTL.
538 You should override this if you define FUNCTION_EXTRA_EPILOGUE.
540 XXX This macro is m68k-specific and only used in m68k.md. */
541 #define USE_RETURN_INSN use_return_insn ()
543 /* Output assembler code for a block containing the constant parts
544 of a trampoline, leaving space for the variable parts.
546 On the m68k, the trampoline looks like this:
550 WARNING: Targets that may run on 68040+ cpus must arrange for
551 the instruction cache to be flushed. Previous incarnations of
552 the m68k trampoline code attempted to get around this by either
553 using an out-of-line transfer function or pc-relative data, but
554 the fact remains that the code to jump to the transfer function
555 or the code to load the pc-relative data needs to be flushed
556 just as much as the "variable" portion of the trampoline.
557 Recognizing that a cache flush is going to be required anyway,
558 dispense with such notions and build a smaller trampoline.
560 Since more instructions are required to move a template into
561 place than to create it on the spot, don't use a template. */
563 #define TRAMPOLINE_SIZE 12
564 #define TRAMPOLINE_ALIGNMENT 16
566 /* Targets redefine this to invoke code to either flush the cache,
567 or enable stack execution (or both). */
568 #ifndef FINALIZE_TRAMPOLINE
569 #define FINALIZE_TRAMPOLINE(TRAMP)
572 /* We generate a two-instructions program at address TRAMP :
575 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
577 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
578 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
579 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
581 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
582 FINALIZE_TRAMPOLINE(TRAMP); \
585 /* This is the library routine that is used to transfer control from the
586 trampoline to the actual nested function. It is defined for backward
587 compatibility, for linking with object code that used the old trampoline
590 A colon is used with no explicit operands to cause the template string
591 to be scanned for %-constructs.
593 The function name __transfer_from_trampoline is not actually used.
594 The function definition just permits use of "asm with operands"
595 (though the operand list is empty). */
596 #define TRANSFER_FROM_TRAMPOLINE \
598 __transfer_from_trampoline () \
600 register char *a0 asm ("%a0"); \
601 asm (GLOBAL_ASM_OP "___trampoline"); \
602 asm ("___trampoline:"); \
603 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
604 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
608 /* There are two registers that can always be eliminated on the m68k.
609 The frame pointer and the arg pointer can be replaced by either the
610 hard frame pointer or to the stack pointer, depending upon the
611 circumstances. The hard frame pointer is not used before reload and
612 so it is not eligible for elimination. */
613 #define ELIMINABLE_REGS \
614 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
615 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
616 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
618 #define CAN_ELIMINATE(FROM, TO) \
619 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
621 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
622 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
624 /* Addressing modes, and classification of registers for them. */
626 #define HAVE_POST_INCREMENT 1
627 #define HAVE_PRE_DECREMENT 1
629 /* Macros to check register numbers against specific register classes. */
631 #define REGNO_OK_FOR_INDEX_P(REGNO) \
632 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
633 #define REGNO_OK_FOR_BASE_P(REGNO) \
634 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
635 #define REGNO_OK_FOR_DATA_P(REGNO) \
636 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
637 #define REGNO_OK_FOR_FP_P(REGNO) \
638 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
640 /* Now macros that check whether X is a register and also,
641 strictly, whether it is in a specified class.
643 These macros are specific to the m68k, and may be used only
644 in code for printing assembler insns and in conditions for
645 define_optimization. */
647 /* 1 if X is a data register. */
648 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
650 /* 1 if X is an fp register. */
651 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
653 /* 1 if X is an address register */
654 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
657 #define MAX_REGS_PER_ADDRESS 2
659 #define CONSTANT_ADDRESS_P(X) \
660 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
661 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
662 || GET_CODE (X) == HIGH)
664 /* Nonzero if the constant value X is a legitimate general operand.
665 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
666 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
668 #ifndef REG_OK_STRICT
669 #define PCREL_GENERAL_OPERAND_OK 0
671 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
674 #define LEGITIMATE_PIC_OPERAND_P(X) \
675 (! symbolic_operand (X, VOIDmode) \
676 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
677 || PCREL_GENERAL_OPERAND_OK)
679 #ifndef REG_OK_STRICT
681 /* Nonzero if X is a hard reg that can be used as an index
682 or if it is a pseudo reg. */
683 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
684 /* Nonzero if X is a hard reg that can be used as a base reg
685 or if it is a pseudo reg. */
686 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
690 /* Nonzero if X is a hard reg that can be used as an index. */
691 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
692 /* Nonzero if X is a hard reg that can be used as a base reg. */
693 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
697 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
698 that is a valid memory address for an instruction.
699 The MODE argument is the machine mode for the MEM expression
700 that wants to use this address.
702 When generating PIC, an address involving a SYMBOL_REF is legitimate
703 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
704 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
705 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
707 Likewise for a LABEL_REF when generating PIC.
709 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
711 /* Allow SUBREG everywhere we allow REG. This results in better code. It
712 also makes function inlining work when inline functions are called with
713 arguments that are SUBREGs. */
715 #define LEGITIMATE_BASE_REG_P(X) \
716 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
717 || (GET_CODE (X) == SUBREG \
718 && GET_CODE (SUBREG_REG (X)) == REG \
719 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
721 #define INDIRECTABLE_1_ADDRESS_P(X) \
722 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
723 || LEGITIMATE_BASE_REG_P (X) \
724 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
725 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
726 || (GET_CODE (X) == PLUS \
727 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
728 && GET_CODE (XEXP (X, 1)) == CONST_INT \
730 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
731 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
732 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
733 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
734 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
736 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
737 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
739 /* Only labels on dispatch tables are valid for indexing from. */
740 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
742 if (GET_CODE (X) == LABEL_REF \
743 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
744 && GET_CODE (temp) == JUMP_INSN \
745 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
746 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
748 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
750 #define GO_IF_INDEXING(X, ADDR) \
751 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
752 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
753 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
754 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
756 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
757 { GO_IF_INDEXING (X, ADDR); \
758 if (GET_CODE (X) == PLUS) \
759 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
760 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
761 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
762 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
763 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
764 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
766 /* ColdFire/5200 does not allow HImode index registers. */
767 #define LEGITIMATE_INDEX_REG_P(X) \
768 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
769 || (! TARGET_COLDFIRE \
770 && GET_CODE (X) == SIGN_EXTEND \
771 && GET_CODE (XEXP (X, 0)) == REG \
772 && GET_MODE (XEXP (X, 0)) == HImode \
773 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
774 || (GET_CODE (X) == SUBREG \
775 && GET_CODE (SUBREG_REG (X)) == REG \
776 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
778 #define LEGITIMATE_INDEX_P(X) \
779 (LEGITIMATE_INDEX_REG_P (X) \
780 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
781 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
782 && GET_CODE (XEXP (X, 1)) == CONST_INT \
783 && (INTVAL (XEXP (X, 1)) == 2 \
784 || INTVAL (XEXP (X, 1)) == 4 \
785 || (INTVAL (XEXP (X, 1)) == 8 \
786 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
788 /* Coldfire FPU only accepts addressing modes 2-5 */
789 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
790 { if (LEGITIMATE_BASE_REG_P (X) \
791 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
792 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
793 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
794 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
795 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
798 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
799 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
800 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
802 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
806 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
807 GO_IF_INDEXED_ADDRESS (X, ADDR); \
808 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
809 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
810 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
814 /* Don't call memory_address_noforce for the address to fetch
815 the switch offset. This address is ok as it stands (see above),
816 but memory_address_noforce would alter it. */
817 #define PIC_CASE_VECTOR_ADDRESS(index) index
819 /* For the 68000, we handle X+REG by loading X into a register R and
820 using R+REG. R will go in an address reg and indexing will be used.
821 However, if REG is a broken-out memory address or multiplication,
822 nothing needs to be done because REG can certainly go in an address reg. */
823 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
824 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
825 { register int ch = (X) != (OLDX); \
826 if (GET_CODE (X) == PLUS) \
828 if (GET_CODE (XEXP (X, 0)) == MULT) \
829 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
830 if (GET_CODE (XEXP (X, 1)) == MULT) \
831 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
832 if (ch && GET_CODE (XEXP (X, 1)) == REG \
833 && GET_CODE (XEXP (X, 0)) == REG) \
834 { if (TARGET_COLDFIRE_FPU \
835 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
836 { COPY_ONCE (X); X = force_operand (X, 0);} \
838 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
839 if (GET_CODE (XEXP (X, 0)) == REG \
840 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
841 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
842 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
843 { register rtx temp = gen_reg_rtx (Pmode); \
844 register rtx val = force_operand (XEXP (X, 1), 0); \
845 emit_move_insn (temp, val); \
847 XEXP (X, 1) = temp; \
848 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
849 && GET_CODE (XEXP (X, 0)) == REG) \
850 X = force_operand (X, 0); \
852 else if (GET_CODE (XEXP (X, 1)) == REG \
853 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
854 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
855 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
856 { register rtx temp = gen_reg_rtx (Pmode); \
857 register rtx val = force_operand (XEXP (X, 0), 0); \
858 emit_move_insn (temp, val); \
860 XEXP (X, 0) = temp; \
861 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
862 && GET_CODE (XEXP (X, 1)) == REG) \
863 X = force_operand (X, 0); \
866 /* On the 68000, only predecrement and postincrement address depend thus
867 (the amount of decrement or increment being the length of the operand).
868 These are now treated generically in recog.c. */
869 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
871 #define CASE_VECTOR_MODE HImode
872 #define CASE_VECTOR_PC_RELATIVE 1
874 #define DEFAULT_SIGNED_CHAR 1
876 #define SLOW_BYTE_ACCESS 0
878 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
880 #define STORE_FLAG_VALUE (-1)
883 #define FUNCTION_MODE QImode
886 /* Tell final.c how to eliminate redundant test instructions. */
888 /* Here we define machine-dependent flags and fields in cc_status
889 (see `conditions.h'). */
891 /* Set if the cc value is actually in the 68881, so a floating point
892 conditional branch must be output. */
893 #define CC_IN_68881 04000
895 /* On the 68000, all the insns to store in an address register fail to
896 set the cc's. However, in some cases these instructions can make it
897 possibly invalid to use the saved cc's. In those cases we clear out
898 some or all of the saved cc's so they won't be used. */
899 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
901 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
902 do { if (cc_prev_status.flags & CC_IN_68881) \
904 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
906 return NORMAL; } while (0)
908 /* Control the assembler format that we output. */
910 #define ASM_APP_ON "#APP\n"
911 #define ASM_APP_OFF "#NO_APP\n"
912 #define TEXT_SECTION_ASM_OP "\t.text"
913 #define DATA_SECTION_ASM_OP "\t.data"
914 #define GLOBAL_ASM_OP "\t.globl\t"
915 #define REGISTER_PREFIX ""
916 #define LOCAL_LABEL_PREFIX ""
917 #define USER_LABEL_PREFIX "_"
918 #define IMMEDIATE_PREFIX "#"
920 #define REGISTER_NAMES \
921 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
922 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
923 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
924 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
925 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
926 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
927 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
928 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
929 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
931 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
933 /* Return a register name by index, handling %fp nicely.
934 We don't replace %fp for targets that don't map it to %a6
935 since it may confuse GAS. */
936 #define M68K_REGNAME(r) ( \
937 ((FRAME_POINTER_REGNUM == 14) \
938 && ((r) == FRAME_POINTER_REGNUM) \
939 && frame_pointer_needed) ? \
940 M68K_FP_REG_NAME : reg_names[(r)])
942 /* On the Sun-3, the floating point registers have numbers
943 18 to 25, not 16 to 23 as they do in the compiler. */
944 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
946 /* Before the prologue, RA is at 0(%sp). */
947 #define INCOMING_RETURN_ADDR_RTX \
948 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
950 /* After the prologue, RA is at 4(AP) in the current frame. */
951 #define RETURN_ADDR_RTX(COUNT, FRAME) \
953 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
954 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
956 /* We must not use the DBX register numbers for the DWARF 2 CFA column
957 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
958 Instead use the identity mapping. */
959 #define DWARF_FRAME_REGNUM(REG) REG
961 /* Before the prologue, the top of the frame is at 4(%sp). */
962 #define INCOMING_FRAME_SP_OFFSET 4
964 /* Describe how we implement __builtin_eh_return. */
965 #define EH_RETURN_DATA_REGNO(N) \
966 ((N) < 2 ? (N) : INVALID_REGNUM)
967 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
968 #define EH_RETURN_HANDLER_RTX \
969 gen_rtx_MEM (Pmode, \
970 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
971 plus_constant (EH_RETURN_STACKADJ_RTX, \
974 /* Select a format to encode pointers in exception handling data. CODE
975 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
976 true if the symbol may be affected by dynamic relocations. */
977 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
979 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
982 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
983 asm_fprintf (FILE, "%U%s", NAME)
985 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
986 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
988 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
989 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
990 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
991 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
993 /* The m68k does not use absolute case-vectors, but we must define this macro
995 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
996 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
998 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
999 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1001 /* We don't have a way to align to more than a two-byte boundary, so do the
1002 best we can and don't complain. */
1003 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1005 fprintf (FILE, "\t.even\n");
1007 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1008 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1010 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1011 ( fputs (".comm ", (FILE)), \
1012 assemble_name ((FILE), (NAME)), \
1013 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1015 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1016 ( fputs (".lcomm ", (FILE)), \
1017 assemble_name ((FILE), (NAME)), \
1018 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1020 /* Output a float value (represented as a C double) as an immediate operand.
1021 This macro is m68k-specific. */
1022 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1027 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1028 asm_fprintf ((FILE), "%I0r%s", dstr); \
1033 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1034 asm_fprintf ((FILE), "%I0x%lx", l); \
1038 /* Output a double value (represented as a C double) as an immediate operand.
1039 This macro is m68k-specific. */
1040 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1041 do { char dstr[30]; \
1042 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1043 asm_fprintf (FILE, "%I0r%s", dstr); \
1046 /* Note, long double immediate operands are not actually
1047 generated by m68k.md. */
1048 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1049 do { char dstr[30]; \
1050 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1051 asm_fprintf (FILE, "%I0r%s", dstr); \
1054 /* On the 68000, we use several CODE characters:
1055 '.' for dot needed in Motorola-style opcode names.
1056 '-' for an operand pushing on the stack:
1057 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1058 '+' for an operand pushing on the stack:
1059 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1060 '@' for a reference to the top word on the stack:
1061 sp@, (sp) or (%sp) depending on the style of syntax.
1062 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1063 but & in SGS syntax).
1064 '!' for the fpcr register (used in some float-to-fixed conversions).
1065 '$' for the letter `s' in an op code, but only on the 68040.
1066 '&' for the letter `d' in an op code, but only on the 68040.
1067 '/' for register prefix needed by longlong.h.
1069 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1070 'd' to force memory addressing to be absolute, not relative.
1071 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1072 'o' for operands to go directly to output_operand_address (bypassing
1073 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1074 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1075 or print pair of registers as rx:ry. */
1077 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1078 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1079 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1080 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1083 /* See m68k.c for the m68k specific codes. */
1084 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1086 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1088 /* Variables in m68k.c */
1089 extern const char *m68k_library_id_string;
1090 extern int m68k_last_compare_had_fp_operands;