1 /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2 Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Note that some other tm.h files include this one and then override
23 many of the definitions that relate to assembler syntax. */
26 /* Names to predefine in the preprocessor for this target machine. */
28 /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
30 /* Print subsidiary information on the compiler version in use. */
32 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
34 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
37 /* Define SUPPORT_SUN_FPA to include support for generating code for
38 the Sun Floating Point Accelerator, an optional product for Sun 3
39 machines. By default, it is not defined. Avoid defining it unless
40 you need to output code for the Sun3+FPA architecture, as it has the
41 effect of slowing down the register set operations in hard-reg-set.h
42 (total number of registers will exceed number of bits in a long,
43 if defined, causing the set operations to expand to loops).
44 SUPPORT_SUN_FPA is typically defined in sun3.h. */
46 /* Run-time compilation parameters selecting different hardware subsets. */
48 extern int target_flags;
50 /* Macros used in the machine description to test the flags. */
52 /* Compile for a 68020 (not a 68000 or 68010). */
54 #define TARGET_68020 (target_flags & MASK_68020)
56 /* Compile 68881 insns for floating point (not library calls). */
58 #define TARGET_68881 (target_flags & MASK_68881)
60 /* Compile using 68020 bitfield insns. */
61 #define MASK_BITFIELD 4
62 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
64 /* Compile using rtd insn calling sequence.
65 This will not work unless you use prototypes at least
66 for all functions that can take varying numbers of args. */
68 #define TARGET_RTD (target_flags & MASK_RTD)
70 /* Compile passing first two args in regs 0 and 1.
71 This exists only to test compiler features that will
72 be needed for RISC chips. It is not usable
73 and is not intended to be usable on this cpu. */
74 #define MASK_REGPARM 16
75 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
77 /* Compile with 16-bit `int'. */
79 #define TARGET_SHORT (target_flags & MASK_SHORT)
81 /* Compile with special insns for Sun FPA. */
83 #define TARGET_FPA (target_flags & MASK_FPA)
85 /* Compile (actually, link) for Sun SKY board. */
87 #define TARGET_SKY (target_flags & MASK_SKY)
89 /* Optimize for 68040, but still allow execution on 68020
90 (-m68020-40 or -m68040).
91 The 68040 will execute all 68030 and 68881/2 instructions, but some
92 of them must be emulated in software by the OS. When TARGET_68040 is
93 turned on, these instructions won't be used. This code will still
94 run on a 68030 and 68881/2. */
95 #define MASK_68040 256
96 #define TARGET_68040 (target_flags & MASK_68040)
98 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
99 #define MASK_68040_ONLY 512
100 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
102 /* Optimize for 68060, but still allow execution on 68020
103 (-m68020-60 or -m68060).
104 The 68060 will execute all 68030 and 68881/2 instructions, but some
105 of them must be emulated in software by the OS. When TARGET_68060 is
106 turned on, these instructions won't be used. This code will still
107 run on a 68030 and 68881/2. */
108 #define MASK_68060 1024
109 #define TARGET_68060 (target_flags & MASK_68060)
111 /* Compile for mcf5200 */
112 #define MASK_5200 2048
113 #define TARGET_5200 (target_flags & MASK_5200)
115 /* Align ints to a word boundary. This breaks compatibility with the
116 published ABI's for structures containing ints, but produces faster
117 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
118 It's required for coldfire cpus without a misalignment module. */
119 #define MASK_ALIGN_INT 4096
120 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
122 /* Compile for a CPU32 */
123 /* A 68020 without bitfields is a good heuristic for a CPU32 */
124 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
126 /* Macro to define tables used to set the flags.
127 This is a list in braces of pairs in braces,
128 each pair being { "NAME", VALUE }
129 where VALUE is the bits to set or minus the bits to clear.
130 An empty string NAME is used to identify the default VALUE. */
132 #define TARGET_SWITCHES \
133 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
134 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
135 { "68020", (MASK_68020|MASK_BITFIELD)}, \
136 { "c68020", (MASK_68020|MASK_BITFIELD)}, \
137 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
138 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
139 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
140 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
141 { "bitfield", MASK_BITFIELD}, \
142 { "nobitfield", - MASK_BITFIELD}, \
143 { "rtd", MASK_RTD}, \
144 { "nortd", - MASK_RTD}, \
145 { "short", MASK_SHORT}, \
146 { "noshort", - MASK_SHORT}, \
147 { "fpa", -(MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
148 { "fpa", MASK_FPA}, \
149 { "nofpa", - MASK_FPA}, \
150 { "sky", -(MASK_FPA|MASK_68040_ONLY|MASK_68881)}, \
151 { "sky", MASK_SKY}, \
152 { "nosky", - MASK_SKY}, \
153 { "68881" - (MASK_FPA|MASK_SKY)}, \
154 { "68881", MASK_68881}, \
155 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881)}, \
156 { "68020-40", -(MASK_5200|MASK_68060)}, \
157 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040)}, \
158 { "68020-60", -(MASK_5200|MASK_68040)}, \
159 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68060)}, \
160 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY)}, \
161 { "68030", (MASK_68020|MASK_BITFIELD)}, \
162 { "68040", - (MASK_5200|MASK_68060)}, \
163 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
164 |MASK_68040_ONLY|MASK_68040)}, \
165 { "68060", - (MASK_5200|MASK_68040)}, \
166 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
167 |MASK_68040_ONLY|MASK_68060)}, \
168 { "5200", - (MASK_68060|MASK_68040|MASK_68020|MASK_BITFIELD \
170 { "5200", (MASK_5200)}, \
173 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
174 |MASK_68020|MASK_BITFIELD|MASK_68881)}, \
175 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
176 |MASK_BITFIELD|MASK_68881)}, \
177 { "68332", MASK_68020}, \
178 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
179 |MASK_BITFIELD|MASK_68881)}, \
180 { "cpu32", MASK_68020}, \
181 { "align-int", MASK_ALIGN_INT }, \
182 { "no-align-int", -MASK_ALIGN_INT }, \
184 { "", TARGET_DEFAULT}}
185 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
187 /* This macro is similar to `TARGET_SWITCHES' but defines names of
188 command options that have values. Its definition is an
189 initializer with a subgrouping for each command option.
191 Each subgrouping contains a string constant, that defines the
192 fixed part of the option name, and the address of a variable. The
193 variable, type `char *', is set to the variable part of the given
194 option if the fixed part matches. The actual option name is made
195 by appending `-m' to the specified name. */
196 #define TARGET_OPTIONS \
197 { { "align-loops=", &m68k_align_loops_string }, \
198 { "align-jumps=", &m68k_align_jumps_string }, \
199 { "align-functions=", &m68k_align_funcs_string }, \
203 /* Sometimes certain combinations of command options do not make
204 sense on a particular target machine. You can define a macro
205 `OVERRIDE_OPTIONS' to take account of this. This macro, if
206 defined, is executed once just after all the command options have
209 Don't use this macro to turn on various extra optimizations for
210 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
212 #define OVERRIDE_OPTIONS \
214 override_options(); \
215 if (! TARGET_68020 && flag_pic == 2) \
216 error("-fPIC is not currently supported on the 68000 or 68010\n"); \
217 SUBTARGET_OVERRIDE_OPTIONS; \
220 /* These are meant to be redefined in the host dependent files */
221 #define SUBTARGET_SWITCHES
222 #define SUBTARGET_OPTIONS
223 #define SUBTARGET_OVERRIDE_OPTIONS
225 /* target machine storage layout */
227 /* Define for XFmode extended real floating point support.
228 This will automatically cause REAL_ARITHMETIC to be defined. */
229 #define LONG_DOUBLE_TYPE_SIZE 96
231 /* Define if you don't want extended real, but do want to use the
232 software floating point emulator for REAL_ARITHMETIC and
233 decimal <-> binary conversion. */
234 /* #define REAL_ARITHMETIC */
236 /* Define this if most significant bit is lowest numbered
237 in instructions that operate on numbered bit-fields.
238 This is true for 68020 insns such as bfins and bfexts.
239 We make it true always by avoiding using the single-bit insns
240 except in special cases with constant bit numbers. */
241 #define BITS_BIG_ENDIAN 1
243 /* Define this if most significant byte of a word is the lowest numbered. */
244 /* That is true on the 68000. */
245 #define BYTES_BIG_ENDIAN 1
247 /* Define this if most significant word of a multiword number is the lowest
249 /* For 68000 we can decide arbitrarily
250 since there are no machine instructions for them.
251 So let's be consistent. */
252 #define WORDS_BIG_ENDIAN 1
254 /* number of bits in an addressable storage unit */
255 #define BITS_PER_UNIT 8
257 /* Width in bits of a "word", which is the contents of a machine register.
258 Note that this is not necessarily the width of data type `int';
259 if using 16-bit ints on a 68000, this would still be 32.
260 But on a machine with 16-bit registers, this would be 16. */
261 #define BITS_PER_WORD 32
263 /* Width of a word, in units (bytes). */
264 #define UNITS_PER_WORD 4
266 /* Width in bits of a pointer.
267 See also the macro `Pmode' defined below. */
268 #define POINTER_SIZE 32
270 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
271 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
273 /* Boundary (in *bits*) on which stack pointer should be aligned. */
274 #define STACK_BOUNDARY 16
276 /* Allocation boundary (in *bits*) for the code of a function. */
277 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
279 /* Alignment of field after `int : 0' in a structure. */
280 #define EMPTY_FIELD_BOUNDARY 16
282 /* No data type wants to be aligned rounder than this.
283 Most published ABIs say that ints should be aligned on 16 bit
284 boundaries, but cpus with 32 bit busses get better performance
285 aligned on 32 bit boundaries. Coldfires without a misalignment
286 module require 32 bit alignment. */
287 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
289 /* Set this nonzero if move instructions will actually fail to work
290 when given unaligned data. */
291 #define STRICT_ALIGNMENT 1
293 /* Maximum power of 2 that code can be aligned to. */
294 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
296 /* Align loop starts for optimal branching. */
297 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
299 /* This is how to align an instruction for optimal branching. */
300 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
302 #define SELECT_RTX_SECTION(MODE, X) \
305 readonly_data_section(); \
306 else if (LEGITIMATE_PIC_OPERAND_P (X)) \
307 readonly_data_section(); \
312 /* Define number of bits in most basic integer type.
313 (If undefined, default is BITS_PER_WORD). */
315 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
317 /* Define these to avoid dependence on meaning of `int'.
318 Note that WCHAR_TYPE_SIZE is used in cexp.y,
319 where TARGET_SHORT is not available. */
321 #define WCHAR_TYPE "long int"
322 #define WCHAR_TYPE_SIZE 32
324 /* Standard register usage. */
326 /* Number of actual hardware registers.
327 The hardware registers are assigned numbers for the compiler
328 from 0 to just below FIRST_PSEUDO_REGISTER.
329 All registers that the compiler knows about must be given numbers,
330 even those that are not normally considered general registers.
331 For the 68000, we give the data registers numbers 0-7,
332 the address registers numbers 010-017,
333 and the 68881 floating point registers numbers 020-027. */
334 #ifndef SUPPORT_SUN_FPA
335 #define FIRST_PSEUDO_REGISTER 24
337 #define FIRST_PSEUDO_REGISTER 56
340 /* This defines the register which is used to hold the offset table for PIC. */
341 #define PIC_OFFSET_TABLE_REGNUM 13
343 /* Used to output a (use pic_offset_table_rtx) so that we
344 always save/restore a5 in functions that use PIC relocation
345 at *any* time during the compilation process. */
346 #define FINALIZE_PIC finalize_pic()
348 #ifndef SUPPORT_SUN_FPA
350 /* 1 for registers that have pervasive standard uses
351 and are not available for the register allocator.
352 On the 68000, only the stack pointer is such. */
354 #define FIXED_REGISTERS \
355 {/* Data registers. */ \
356 0, 0, 0, 0, 0, 0, 0, 0, \
358 /* Address registers. */ \
359 0, 0, 0, 0, 0, 0, 0, 1, \
361 /* Floating point registers \
363 0, 0, 0, 0, 0, 0, 0, 0 }
365 /* 1 for registers not available across function calls.
366 These must include the FIXED_REGISTERS and also any
367 registers that can be used without being saved.
368 The latter must include the registers where values are returned
369 and the register where structure-value addresses are passed.
370 Aside from that, you can include as many other registers as you like. */
371 #define CALL_USED_REGISTERS \
372 {1, 1, 0, 0, 0, 0, 0, 0, \
373 1, 1, 0, 0, 0, 0, 0, 1, \
374 1, 1, 0, 0, 0, 0, 0, 0 }
376 #else /* SUPPORT_SUN_FPA */
378 /* 1 for registers that have pervasive standard uses
379 and are not available for the register allocator.
380 On the 68000, only the stack pointer is such. */
382 /* fpa0 is also reserved so that it can be used to move data back and
383 forth between high fpa regs and everything else. */
385 #define FIXED_REGISTERS \
386 {/* Data registers. */ \
387 0, 0, 0, 0, 0, 0, 0, 0, \
389 /* Address registers. */ \
390 0, 0, 0, 0, 0, 0, 0, 1, \
392 /* Floating point registers \
394 0, 0, 0, 0, 0, 0, 0, 0, \
396 /* Sun3 FPA registers. */ \
397 1, 0, 0, 0, 0, 0, 0, 0, \
398 0, 0, 0, 0, 0, 0, 0, 0, \
399 0, 0, 0, 0, 0, 0, 0, 0, \
400 0, 0, 0, 0, 0, 0, 0, 0 }
402 /* 1 for registers not available across function calls.
403 These must include the FIXED_REGISTERS and also any
404 registers that can be used without being saved.
405 The latter must include the registers where values are returned
406 and the register where structure-value addresses are passed.
407 Aside from that, you can include as many other registers as you like. */
408 #define CALL_USED_REGISTERS \
409 {1, 1, 0, 0, 0, 0, 0, 0, \
410 1, 1, 0, 0, 0, 0, 0, 1, \
411 1, 1, 0, 0, 0, 0, 0, 0, \
412 /* FPA registers. */ \
413 1, 1, 1, 1, 0, 0, 0, 0, \
414 0, 0, 0, 0, 0, 0, 0, 0, \
415 0, 0, 0, 0, 0, 0, 0, 0, \
416 0, 0, 0, 0, 0, 0, 0, 0 }
418 #endif /* defined SUPPORT_SUN_FPA */
421 /* Make sure everything's fine if we *don't* have a given processor.
422 This assumes that putting a register in fixed_regs will keep the
423 compiler's mitts completely off it. We don't bother to zero it out
424 of register classes. If neither TARGET_FPA or TARGET_68881 is set,
425 the compiler won't touch since no instructions that use these
426 registers will be valid. */
428 #ifdef SUPPORT_SUN_FPA
430 #define CONDITIONAL_REGISTER_USAGE \
436 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
437 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
438 if (TEST_HARD_REG_BIT (x, i)) \
439 fixed_regs[i] = call_used_regs[i] = 1; \
443 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
444 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
445 if (TEST_HARD_REG_BIT (x, i)) \
446 fixed_regs[i] = call_used_regs[i] = 1; \
450 #endif /* defined SUPPORT_SUN_FPA */
452 /* Return number of consecutive hard regs needed starting at reg REGNO
453 to hold something of mode MODE.
454 This is ordinarily the length in words of a value of mode MODE
455 but can be less for certain modes in special long registers.
457 On the 68000, ordinary registers hold 32 bits worth;
458 for the 68881 registers, a single register is always enough for
459 anything that can be stored in them at all. */
460 #define HARD_REGNO_NREGS(REGNO, MODE) \
461 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
462 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
464 #ifndef SUPPORT_SUN_FPA
466 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
467 On the 68000, the cpu registers can hold any mode but the 68881 registers
468 can hold only SFmode or DFmode. The 68881 registers can't hold anything
469 if 68881 use is disabled. */
471 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
473 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \
476 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
477 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)))
479 #else /* defined SUPPORT_SUN_FPA */
481 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
482 On the 68000, the cpu registers can hold any mode but the 68881 registers
483 can hold only SFmode or DFmode. And the 68881 registers can't hold anything
484 if 68881 use is disabled. However, the Sun FPA register can
485 (apparently) hold whatever you feel like putting in them.
486 If using the fpa, don't put a double in d7/a0. */
488 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
491 && GET_MODE_CLASS ((MODE)) != MODE_INT \
492 && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
493 && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
494 && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
496 ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
497 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
498 : ((REGNO) < 56 ? TARGET_FPA : 0)))
500 #endif /* defined SUPPORT_SUN_FPA */
502 /* Value is 1 if it is a good idea to tie two pseudo registers
503 when one has mode MODE1 and one has mode MODE2.
504 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
505 for any hard reg, then this must be 0 for correct output. */
506 #define MODES_TIEABLE_P(MODE1, MODE2) \
508 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
509 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
510 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
511 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
513 /* Specify the registers used for certain standard purposes.
514 The values of these macros are register numbers. */
516 /* m68000 pc isn't overloaded on a register. */
517 /* #define PC_REGNUM */
519 /* Register to use for pushing function arguments. */
520 #define STACK_POINTER_REGNUM 15
522 /* Base register for access to local variables of the function. */
523 #define FRAME_POINTER_REGNUM 14
525 /* Value should be nonzero if functions must have frame pointers.
526 Zero means the frame pointer need not be set up (and parms
527 may be accessed via the stack pointer) in functions that seem suitable.
528 This is computed in `reload', in reload1.c. */
529 #define FRAME_POINTER_REQUIRED 0
531 /* Base register for access to arguments of the function. */
532 #define ARG_POINTER_REGNUM 14
534 /* Register in which static-chain is passed to a function. */
535 #define STATIC_CHAIN_REGNUM 8
537 /* Register in which address to store a structure value
538 is passed to a function. */
539 #define STRUCT_VALUE_REGNUM 9
541 /* Define the classes of registers for register constraints in the
542 machine description. Also define ranges of constants.
544 One of the classes must always be named ALL_REGS and include all hard regs.
545 If there is more than one class, another class must be named NO_REGS
546 and contain no registers.
548 The name GENERAL_REGS must be the name of a class (or an alias for
549 another name such as ALL_REGS). This is the class of registers
550 that is allowed by "g" or "r" in a register constraint.
551 Also, registers outside this class are allocated only when
552 instructions express preferences for them.
554 The classes must be numbered in nondecreasing order; that is,
555 a larger-numbered class must never be contained completely
556 in a smaller-numbered class.
558 For any two classes, it is very desirable that there be another
559 class that represents their union. */
561 /* The 68000 has three kinds of registers, so eight classes would be
562 a complete set. One of them is not needed. */
564 #ifndef SUPPORT_SUN_FPA
569 GENERAL_REGS, DATA_OR_FP_REGS,
570 ADDR_OR_FP_REGS, ALL_REGS,
573 #define N_REG_CLASSES (int) LIM_REG_CLASSES
575 /* Give names of register classes as strings for dump file. */
577 #define REG_CLASS_NAMES \
578 { "NO_REGS", "DATA_REGS", \
579 "ADDR_REGS", "FP_REGS", \
580 "GENERAL_REGS", "DATA_OR_FP_REGS", \
581 "ADDR_OR_FP_REGS", "ALL_REGS" }
583 /* Define which registers fit in which classes.
584 This is an initializer for a vector of HARD_REG_SET
585 of length N_REG_CLASSES. */
587 #define REG_CLASS_CONTENTS \
589 0x00000000, /* NO_REGS */ \
590 0x000000ff, /* DATA_REGS */ \
591 0x0000ff00, /* ADDR_REGS */ \
592 0x00ff0000, /* FP_REGS */ \
593 0x0000ffff, /* GENERAL_REGS */ \
594 0x00ff00ff, /* DATA_OR_FP_REGS */ \
595 0x00ffff00, /* ADDR_OR_FP_REGS */ \
596 0x00ffffff, /* ALL_REGS */ \
599 /* The same information, inverted:
600 Return the class number of the smallest class containing
601 reg number REGNO. This could be a conditional expression
602 or could index an array. */
604 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
606 #else /* defined SUPPORT_SUN_FPA */
609 * Notes on final choices:
611 * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
613 * 2) Removed all unions that involve address registers with
614 * floating point registers (left in unions of address and data with
616 * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
617 * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
618 * 4) Left in everything else.
620 enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
621 FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
622 DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
623 GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
626 #define N_REG_CLASSES (int) LIM_REG_CLASSES
628 /* Give names of register classes as strings for dump file. */
630 #define REG_CLASS_NAMES \
631 { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
632 "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
633 "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
634 "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
636 /* Define which registers fit in which classes.
637 This is an initializer for a vector of HARD_REG_SET
638 of length N_REG_CLASSES. */
640 #define REG_CLASS_CONTENTS \
642 {0, 0}, /* NO_REGS */ \
643 {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
644 {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
645 {0x00ff0000, 0x00000000}, /* FP_REGS */ \
646 {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
647 {0x000000ff, 0x00000000}, /* DATA_REGS */ \
648 {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
649 {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
650 {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
651 {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
652 {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
653 {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
654 {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
655 {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
658 /* The same information, inverted:
659 Return the class number of the smallest class containing
660 reg number REGNO. This could be a conditional expression
661 or could index an array. */
663 extern enum reg_class regno_reg_class[];
664 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
666 #endif /* SUPPORT_SUN_FPA */
668 /* The class value for index registers, and the one for base regs. */
670 #define INDEX_REG_CLASS GENERAL_REGS
671 #define BASE_REG_CLASS ADDR_REGS
673 /* Get reg_class from a letter such as appears in the machine description.
674 We do a trick here to modify the effective constraints on the
675 machine description; we zorch the constraint letters that aren't
676 appropriate for a specific target. This allows us to guarantee
677 that a specific kind of register will not be used for a given target
678 without fiddling with the register classes above. */
680 #ifndef SUPPORT_SUN_FPA
682 #define REG_CLASS_FROM_LETTER(C) \
683 ((C) == 'a' ? ADDR_REGS : \
684 ((C) == 'd' ? DATA_REGS : \
685 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
689 #else /* defined SUPPORT_SUN_FPA */
691 #define REG_CLASS_FROM_LETTER(C) \
692 ((C) == 'a' ? ADDR_REGS : \
693 ((C) == 'd' ? DATA_REGS : \
694 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
696 ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
698 ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
702 #endif /* defined SUPPORT_SUN_FPA */
704 /* The letters I, J, K, L and M in a register constraint string
705 can be used to stand for particular ranges of immediate operands.
706 This macro defines what the ranges are.
707 C is the letter, and VALUE is a constant value.
708 Return 1 if VALUE is in the range specified by C.
710 For the 68000, `I' is used for the range 1 to 8
711 allowed as immediate shift counts and in addq.
712 `J' is used for the range of signed numbers that fit in 16 bits.
713 `K' is for numbers that moveq can't handle.
714 `L' is for range -8 to -1, range of values that can be added with subq.
715 `M' is for numbers that moveq+notb can't handle.
716 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
717 'O' is for 16 (for rotate using swap).
718 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
720 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
721 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
722 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
723 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
724 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
725 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
726 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
727 (C) == 'O' ? (VALUE) == 16 : \
728 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
731 * A small bit of explanation:
732 * "G" defines all of the floating constants that are *NOT* 68881
733 * constants. this is so 68881 constants get reloaded and the
734 * fpmovecr is used. "H" defines *only* the class of constants that
735 * the fpa can use, because these can be gotten at in any fpa
736 * instruction and there is no need to force reloads.
738 #ifndef SUPPORT_SUN_FPA
739 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
740 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
741 #else /* defined SUPPORT_SUN_FPA */
742 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
743 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
744 (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
745 #endif /* defined SUPPORT_SUN_FPA */
747 /* A C expression that defines the optional machine-dependent constraint
748 letters that can be used to segregate specific types of operands,
749 usually memory references, for the target machine. It should return 1 if
750 VALUE corresponds to the operand type represented by the constraint letter
751 C. If C is not defined as an extra constraint, the value returned should
752 be 0 regardless of VALUE. */
754 /* For the m68k, `Q' means address register indirect addressing mode. */
756 #define EXTRA_CONSTRAINT(OP, C) \
757 ((C) == 'Q' ? (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) : \
760 /* Given an rtx X being reloaded into a reg required to be
761 in class CLASS, return the class of reg to actually use.
762 In general this is just CLASS; but on some machines
763 in some cases it is preferable to use a more restrictive class.
764 On the 68000 series, use a data reg if possible when the
765 value is a constant in the range where moveq could be used
766 and we ensure that QImodes are reloaded into data regs.
767 Also, if a floating constant needs reloading, put it in memory.
768 Don't do this for !G constants, since all patterns in the md file
769 expect them to be loaded into a register via fpmovecr. See above. */
771 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
772 ((GET_CODE (X) == CONST_INT \
773 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
774 && (CLASS) != ADDR_REGS) \
776 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
778 : (GET_CODE (X) == CONST_DOUBLE \
779 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
780 ? (! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G') \
781 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
782 ? FP_REGS : NO_REGS) \
785 /* Force QImode output reloads from subregs to be allocated to data regs,
786 since QImode stores from address regs are not supported. We make the
787 assumption that if the class is not ADDR_REGS, then it must be a superset
790 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
791 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
795 /* Return the maximum number of consecutive registers
796 needed to represent mode MODE in a register of class CLASS. */
797 /* On the 68000, this is the size of MODE in words,
798 except in the FP regs, where a single reg is always enough. */
799 #ifndef SUPPORT_SUN_FPA
801 #define CLASS_MAX_NREGS(CLASS, MODE) \
802 ((CLASS) == FP_REGS ? 1 \
803 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
805 /* Moves between fp regs and other regs are two insns. */
806 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
807 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
808 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
811 #else /* defined SUPPORT_SUN_FPA */
813 #define CLASS_MAX_NREGS(CLASS, MODE) \
814 ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
815 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
817 /* Moves between fp regs and other regs are two insns. */
818 /* Likewise for high fpa regs and other regs. */
819 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
820 ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
821 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
822 || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
823 || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
826 #endif /* define SUPPORT_SUN_FPA */
828 /* Stack layout; function entry, exit and calling. */
830 /* Define this if pushing a word on the stack
831 makes the stack pointer a smaller address. */
832 #define STACK_GROWS_DOWNWARD
834 /* Nonzero if we need to generate stack-probe insns.
835 On most systems they are not needed.
836 When they are needed, define this as the stack offset to probe at. */
839 /* Define this if the nominal address of the stack frame
840 is at the high-address end of the local variables;
841 that is, each additional local variable allocated
842 goes at a more negative offset in the frame. */
843 #define FRAME_GROWS_DOWNWARD
845 /* Offset within stack frame to start allocating local variables at.
846 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
847 first local allocated. Otherwise, it is the offset to the BEGINNING
848 of the first local allocated. */
849 #define STARTING_FRAME_OFFSET 0
851 /* If we generate an insn to push BYTES bytes,
852 this says how many the stack pointer really advances by.
853 On the 68000, sp@- in a byte insn really pushes a word.
854 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
855 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
857 /* Offset of first parameter from the argument pointer register value. */
858 #define FIRST_PARM_OFFSET(FNDECL) 8
860 /* Value is the number of byte of arguments automatically
861 popped when returning from a subroutine call.
862 FUNDECL is the declaration node of the function (as a tree),
863 FUNTYPE is the data type of the function (as a tree),
864 or for a library call it is an identifier node for the subroutine name.
865 SIZE is the number of bytes of arguments passed on the stack.
867 On the 68000, the RTS insn cannot pop anything.
868 On the 68010, the RTD insn may be used to pop them if the number
869 of args is fixed, but if the number is variable then the caller
870 must pop them all. RTD can't be used for library calls now
871 because the library is compiled with the Unix compiler.
872 Use of RTD is a selectable option, since it is incompatible with
873 standard Unix calling sequences. If the option is not selected,
874 the caller must always pop the args. */
876 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
877 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
878 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
879 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
880 == void_type_node))) \
883 /* Define how to find the value returned by a function.
884 VALTYPE is the data type of the value (as a tree).
885 If the precise function being called is known, FUNC is its FUNCTION_DECL;
886 otherwise, FUNC is 0. */
888 /* On the 68000 the return value is in D0 regardless. */
890 #define FUNCTION_VALUE(VALTYPE, FUNC) \
891 gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
893 /* Define how to find the value returned by a library function
894 assuming the value has mode MODE. */
896 /* On the 68000 the return value is in D0 regardless. */
898 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
900 /* 1 if N is a possible register number for a function value.
901 On the 68000, d0 is the only register thus used. */
903 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
905 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
906 more than one register. */
908 #define NEEDS_UNTYPED_CALL 0
910 /* Define this if PCC uses the nonreentrant convention for returning
911 structure and union values. */
913 #define PCC_STATIC_STRUCT_RETURN
915 /* 1 if N is a possible register number for function argument passing.
916 On the 68000, no registers are used in this way. */
918 #define FUNCTION_ARG_REGNO_P(N) 0
920 /* Define a data type for recording info about an argument list
921 during the scan of that argument list. This data type should
922 hold all necessary information about the function itself
923 and about the args processed so far, enough to enable macros
924 such as FUNCTION_ARG to determine where the next arg should go.
926 On the m68k, this is a single integer, which is a number of bytes
927 of arguments scanned so far. */
929 #define CUMULATIVE_ARGS int
931 /* Initialize a variable CUM of type CUMULATIVE_ARGS
932 for a call to a function whose data type is FNTYPE.
933 For a library call, FNTYPE is 0.
935 On the m68k, the offset starts at 0. */
937 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
940 /* Update the data in CUM to advance over an argument
941 of mode MODE and data type TYPE.
942 (TYPE is null for libcalls where that information may not be available.) */
944 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
945 ((CUM) += ((MODE) != BLKmode \
946 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
947 : (int_size_in_bytes (TYPE) + 3) & ~3))
949 /* Define where to put the arguments to a function.
950 Value is zero to push the argument on the stack,
951 or a hard register in which to store the argument.
953 MODE is the argument's machine mode.
954 TYPE is the data type of the argument (as a tree).
955 This is null for libcalls where that information may
957 CUM is a variable of type CUMULATIVE_ARGS which gives info about
958 the preceding args and about the function being called.
959 NAMED is nonzero if this argument is a named parameter
960 (otherwise it is an extra parameter matching an ellipsis). */
962 /* On the 68000 all args are pushed, except if -mregparm is specified
963 then the first two words of arguments are passed in d0, d1.
964 *NOTE* -mregparm does not work.
965 It exists only to test register calling conventions. */
967 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
968 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
970 /* For an arg passed partly in registers and partly in memory,
971 this is the number of registers used.
972 For args passed entirely in registers or entirely in memory, zero. */
974 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
975 ((TARGET_REGPARM && (CUM) < 8 \
976 && 8 < ((CUM) + ((MODE) == BLKmode \
977 ? int_size_in_bytes (TYPE) \
978 : GET_MODE_SIZE (MODE)))) \
981 /* Generate the assembly code for function entry. */
982 #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
984 /* Output assembler code to FILE to increment profiler label # LABELNO
985 for profiling a function entry. */
987 #define FUNCTION_PROFILER(FILE, LABELNO) \
988 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
990 /* Output assembler code to FILE to initialize this source file's
991 basic block profiling info, if that has not already been done. */
993 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
996 switch (profile_block_flag) \
999 asm_fprintf (FILE, "\tpea %d\n\tpea %LLPBX0\n\tjsr %U__bb_init_trace_func\n\taddql %I8,%Rsp\n", \
1000 (BLOCK_OR_LABEL)); \
1004 asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
1005 (BLOCK_OR_LABEL), (BLOCK_OR_LABEL)); \
1011 /* Output assembler code to FILE to increment the counter for
1012 the BLOCKNO'th basic block in this source file. */
1014 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1017 switch (profile_block_flag) \
1020 asm_fprintf (FILE, "\tmovel %Ra1,%Rsp@-\n\tlea ___bb,%Ra1\n\tmovel %I%d,%Ra1@(0)\n\tmovel %I%LLPBX0,%Ra1@(4)\n\tmovel %Rsp@+,%Ra1\n\tjsr %U__bb_trace_func\n", \
1025 asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO); \
1031 /* Output assembler code to FILE to indicate return from
1032 a function during basic block profiling. */
1034 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1035 asm_fprintf (FILE, "\tjsr %U__bb_trace_ret\n");
1037 /* Save all registers which may be clobbered by a function call.
1038 MACHINE_STATE_SAVE and MACHINE_STATE_RESTORE are target-code macros,
1039 used in libgcc2.c. They may not refer to TARGET_* macros !!! */
1040 #if defined (__mc68010__) || defined(mc68010) \
1041 || defined(__mc68020__) || defined(mc68020) \
1042 || defined(__mc68030__) || defined(mc68030) \
1043 || defined(__mc68040__) || defined(mc68040) \
1044 || defined(__mcpu32__) || defined(mcpu32)
1045 #define MACHINE_STATE_m68010_up
1049 #if defined(__mcf5200__)
1050 #define MACHINE_STATE_SAVE(id) \
1052 asm ("sub.l 20,%sp"); \
1053 asm ("movm.l &0x0303,4(%sp)"); \
1054 asm ("move.w %ccr,%d0"); \
1055 asm ("movm.l &0x0001,(%sp)"); \
1057 #else /* !__mcf5200__ */
1058 #if defined(MACHINE_STATE_m68010_up)
1060 /* HPUX assembler does not accept %ccr. */
1061 #define MACHINE_STATE_SAVE(id) \
1063 asm ("move.w %cc,-(%sp)"); \
1064 asm ("movm.l &0xc0c0,-(%sp)"); \
1066 #else /* ! __HPUX_ASM__ */
1067 #define MACHINE_STATE_SAVE(id) \
1069 asm ("move.w %ccr,-(%sp)"); \
1070 asm ("movm.l &0xc0c0,-(%sp)"); \
1072 #endif /* __HPUX_ASM__ */
1073 #else /* !MACHINE_STATE_m68010_up */
1074 #define MACHINE_STATE_SAVE(id) \
1076 asm ("move.w %sr,-(%sp)"); \
1077 asm ("movm.l &0xc0c0,-(%sp)"); \
1079 #endif /* MACHINE_STATE_m68010_up */
1080 #endif /* __mcf5200__ */
1081 #else /* !MOTOROLA */
1082 #if defined(__mcf5200__)
1083 #define MACHINE_STATE_SAVE(id) \
1085 asm ("subl %#20,%/sp" : ); \
1086 asm ("movml %/d0/%/d1/%/a0/%/a1,%/sp@(4)" : ); \
1087 asm ("movew %/cc,%/d0" : ); \
1088 asm ("movml %/d0,%/sp@" : ); \
1090 #else /* !__mcf5200__ */
1091 #if defined(MACHINE_STATE_m68010_up)
1092 #define MACHINE_STATE_SAVE(id) \
1094 asm ("movew %/cc,%/sp@-" : ); \
1095 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1097 #else /* !MACHINE_STATE_m68010_up */
1098 #define MACHINE_STATE_SAVE(id) \
1100 asm ("movew %/sr,%/sp@-" : ); \
1101 asm ("moveml %/d0/%/d1/%/a0/%/a1,%/sp@-" : ); \
1103 #endif /* MACHINE_STATE_m68010_up */
1104 #endif /* __mcf5200__ */
1105 #endif /* MOTOROLA */
1107 /* Restore all registers saved by MACHINE_STATE_SAVE. */
1110 #if defined(__mcf5200__)
1111 #define MACHINE_STATE_RESTORE(id) \
1113 asm ("movm.l (%sp),&0x0001"); \
1114 asm ("move.w %d0,%ccr"); \
1115 asm ("movm.l 4(%sp),&0x0303"); \
1116 asm ("add.l 20,%sp"); \
1118 #else /* !__mcf5200__ */
1120 /* HPUX assembler does not accept %ccr. */
1121 #define MACHINE_STATE_RESTORE(id) \
1123 asm ("movm.l (%sp)+,&0x0303"); \
1124 asm ("move.w (%sp)+,%cc"); \
1126 #else /* ! __HPUX_ASM__ */
1127 #define MACHINE_STATE_RESTORE(id) \
1129 asm ("movm.l (%sp)+,&0x0303"); \
1130 asm ("move.w (%sp)+,%ccr"); \
1132 #endif /* __HPUX_ASM__ */
1133 #endif /* __mcf5200__ */
1134 #else /* !MOTOROLA */
1135 #if defined(__mcf5200__)
1136 #define MACHINE_STATE_RESTORE(id) \
1138 asm ("movml %/sp@,%/d0" : ); \
1139 asm ("movew %/d0,%/cc" : ); \
1140 asm ("movml %/sp@(4),%/d0/%/d1/%/a0/%/a1" : ); \
1141 asm ("addl %#20,%/sp" : ); \
1143 #else /* !__mcf5200__ */
1144 #define MACHINE_STATE_RESTORE(id) \
1146 asm ("moveml %/sp@+,%/d0/%/d1/%/a0/%/a1" : ); \
1147 asm ("movew %/sp@+,%/cc" : ); \
1149 #endif /* __mcf5200__ */
1150 #endif /* MOTOROLA */
1152 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1153 the stack pointer does not matter. The value is tested only in
1154 functions that have frame pointers.
1155 No definition is equivalent to always zero. */
1157 #define EXIT_IGNORE_STACK 1
1159 /* Generate the assembly code for function exit. */
1160 #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
1162 /* This is a hook for other tm files to change. */
1163 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
1165 /* Determine if the epilogue should be output as RTL.
1166 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1167 #define USE_RETURN_INSN use_return_insn ()
1169 /* Store in the variable DEPTH the initial difference between the
1170 frame pointer reg contents and the stack pointer reg contents,
1171 as of the start of the function body. This depends on the layout
1172 of the fixed parts of the stack frame and on how registers are saved.
1174 On the 68k, if we have a frame, we must add one word to its length
1175 to allow for the place that a6 is stored when we do have a frame pointer.
1176 Otherwise, we would need to compute the offset from the frame pointer
1177 of a local variable as a function of frame_pointer_needed, which
1180 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1183 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1184 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1186 for (regno = 0; regno < 16; regno++) \
1187 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1189 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1190 + (get_frame_size () == 0 ? 0 : 4)); \
1193 /* Output assembler code for a block containing the constant parts
1194 of a trampoline, leaving space for the variable parts. */
1196 /* On the 68k, the trampoline looks like this:
1200 WARNING: Targets that may run on 68040+ cpus must arrange for
1201 the instruction cache to be flushed. Previous incarnations of
1202 the m68k trampoline code attempted to get around this by either
1203 using an out-of-line transfer function or pc-relative data, but
1204 the fact remains that the code to jump to the transfer function
1205 or the code to load the pc-relative data needs to be flushed
1206 just as much as the "variable" portion of the trampoline.
1207 Recognizing that a cache flush is going to be required anyway,
1208 dispense with such notions and build a smaller trampoline. */
1210 /* Since more instructions are required to move a template into
1211 place than to create it on the spot, don't use a template. */
1213 /* Length in units of the trampoline for entering a nested function. */
1215 #define TRAMPOLINE_SIZE 12
1217 /* Alignment required for a trampoline in bits. */
1219 #define TRAMPOLINE_ALIGNMENT 16
1221 /* Targets redefine this to invoke code to either flush the cache,
1222 or enable stack execution (or both). */
1224 #ifndef FINALIZE_TRAMPOLINE
1225 #define FINALIZE_TRAMPOLINE(TRAMP)
1228 /* Emit RTL insns to initialize the variable parts of a trampoline.
1229 FNADDR is an RTX for the address of the function's pure code.
1230 CXT is an RTX for the static chain value for the function.
1232 We generate a two-instructions program at address TRAMP :
1236 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1238 emit_move_insn (gen_rtx (MEM, HImode, TRAMP), GEN_INT(0x207C)); \
1239 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), CXT); \
1240 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 6)), \
1242 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), FNADDR); \
1243 FINALIZE_TRAMPOLINE(TRAMP); \
1246 /* This is the library routine that is used
1247 to transfer control from the trampoline
1248 to the actual nested function.
1249 It is defined for backward compatibility,
1250 for linking with object code that used the old
1251 trampoline definition. */
1253 /* A colon is used with no explicit operands
1254 to cause the template string to be scanned for %-constructs. */
1255 /* The function name __transfer_from_trampoline is not actually used.
1256 The function definition just permits use of "asm with operands"
1257 (though the operand list is empty). */
1258 #define TRANSFER_FROM_TRAMPOLINE \
1260 __transfer_from_trampoline () \
1262 register char *a0 asm ("%a0"); \
1263 asm (GLOBAL_ASM_OP " ___trampoline"); \
1264 asm ("___trampoline:"); \
1265 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
1266 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1270 /* Addressing modes, and classification of registers for them. */
1272 #define HAVE_POST_INCREMENT
1273 /* #define HAVE_POST_DECREMENT */
1275 #define HAVE_PRE_DECREMENT
1276 /* #define HAVE_PRE_INCREMENT */
1278 /* Macros to check register numbers against specific register classes. */
1280 /* These assume that REGNO is a hard or pseudo reg number.
1281 They give nonzero only if REGNO is a hard reg of the suitable class
1282 or a pseudo reg currently allocated to a suitable hard reg.
1283 Since they use reg_renumber, they are safe only once reg_renumber
1284 has been allocated, which happens in local-alloc.c. */
1286 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1287 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1288 #define REGNO_OK_FOR_BASE_P(REGNO) \
1289 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1290 #define REGNO_OK_FOR_DATA_P(REGNO) \
1291 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1292 #define REGNO_OK_FOR_FP_P(REGNO) \
1293 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1294 #ifdef SUPPORT_SUN_FPA
1295 #define REGNO_OK_FOR_FPA_P(REGNO) \
1296 (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1299 /* Now macros that check whether X is a register and also,
1300 strictly, whether it is in a specified class.
1302 These macros are specific to the 68000, and may be used only
1303 in code for printing assembler insns and in conditions for
1304 define_optimization. */
1306 /* 1 if X is a data register. */
1308 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1310 /* 1 if X is an fp register. */
1312 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1314 /* 1 if X is an address register */
1316 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1318 #ifdef SUPPORT_SUN_FPA
1319 /* 1 if X is a register in the Sun FPA. */
1320 #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1322 /* Answer must be no if we don't have an FPA. */
1323 #define FPA_REG_P(X) 0
1326 /* Maximum number of registers that can appear in a valid memory address. */
1328 #define MAX_REGS_PER_ADDRESS 2
1330 /* Recognize any constant value that is a valid address. */
1332 #define CONSTANT_ADDRESS_P(X) \
1333 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1334 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1335 || GET_CODE (X) == HIGH)
1337 /* Nonzero if the constant value X is a legitimate general operand.
1338 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1340 #define LEGITIMATE_CONSTANT_P(X) 1
1342 /* Nonzero if the constant value X is a legitimate general operand
1343 when generating PIC code. It is given that flag_pic is on and
1344 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1346 #define LEGITIMATE_PIC_OPERAND_P(X) \
1347 ((! symbolic_operand (X, VOIDmode) \
1348 && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \
1349 && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \
1350 && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \
1352 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)))
1354 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1355 and check its validity for a certain class.
1356 We have two alternate definitions for each of them.
1357 The usual definition accepts all pseudo regs; the other rejects
1358 them unless they have been allocated suitable hard regs.
1359 The symbol REG_OK_STRICT causes the latter definition to be used.
1361 Most source files want to accept pseudo regs in the hope that
1362 they will get allocated to the class that the insn wants them to be in.
1363 Source files for reload pass need to be strict.
1364 After reload, it makes no difference, since pseudo regs have
1365 been eliminated by then. */
1367 #ifndef REG_OK_STRICT
1369 /* Nonzero if X is a hard reg that can be used as an index
1370 or if it is a pseudo reg. */
1371 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1372 /* Nonzero if X is a hard reg that can be used as a base reg
1373 or if it is a pseudo reg. */
1374 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1378 /* Nonzero if X is a hard reg that can be used as an index. */
1379 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1380 /* Nonzero if X is a hard reg that can be used as a base reg. */
1381 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1385 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1386 that is a valid memory address for an instruction.
1387 The MODE argument is the machine mode for the MEM expression
1388 that wants to use this address.
1390 When generating PIC, an address involving a SYMBOL_REF is legitimate
1391 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1392 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1393 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1395 Likewise for a LABEL_REF when generating PIC.
1397 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1399 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1400 also makes function inlining work when inline functions are called with
1401 arguments that are SUBREGs. */
1403 #define LEGITIMATE_BASE_REG_P(X) \
1404 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1405 || (GET_CODE (X) == SUBREG \
1406 && GET_CODE (SUBREG_REG (X)) == REG \
1407 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1409 #define INDIRECTABLE_1_ADDRESS_P(X) \
1410 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1411 || LEGITIMATE_BASE_REG_P (X) \
1412 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1413 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1414 || (GET_CODE (X) == PLUS \
1415 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1416 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1417 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \
1418 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1419 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1420 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1421 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \
1424 /* This should replace the last two (non-pic) lines
1425 except that Sun's assembler does not seem to handle such operands. */
1426 && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \
1427 : (GET_CODE (XEXP (X, 1)) == CONST_INT \
1428 && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))))
1432 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1433 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1435 /* Only labels on dispatch tables are valid for indexing from. */
1436 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1438 if (GET_CODE (X) == LABEL_REF \
1439 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1440 && GET_CODE (temp) == JUMP_INSN \
1441 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1442 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1444 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1446 #define GO_IF_INDEXING(X, ADDR) \
1447 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1448 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1449 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1450 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1452 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1453 { GO_IF_INDEXING (X, ADDR); \
1454 if (GET_CODE (X) == PLUS) \
1455 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1456 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1457 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1458 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1459 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1460 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1462 #define LEGITIMATE_INDEX_REG_P(X) \
1463 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1464 || (GET_CODE (X) == SIGN_EXTEND \
1465 && GET_CODE (XEXP (X, 0)) == REG \
1466 && GET_MODE (XEXP (X, 0)) == HImode \
1467 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1468 || (GET_CODE (X) == SUBREG \
1469 && GET_CODE (SUBREG_REG (X)) == REG \
1470 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1472 #define LEGITIMATE_INDEX_P(X) \
1473 (LEGITIMATE_INDEX_REG_P (X) \
1474 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1475 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1476 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1477 && (INTVAL (XEXP (X, 1)) == 2 \
1478 || INTVAL (XEXP (X, 1)) == 4 \
1479 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1481 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1482 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1483 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1484 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1485 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1486 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1487 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1490 /* Don't call memory_address_noforce for the address to fetch
1491 the switch offset. This address is ok as it stands (see above),
1492 but memory_address_noforce would alter it. */
1493 #define PIC_CASE_VECTOR_ADDRESS(index) index
1495 /* Try machine-dependent ways of modifying an illegitimate address
1496 to be legitimate. If we find one, return the new, valid address.
1497 This macro is used in only one place: `memory_address' in explow.c.
1499 OLDX is the address as it was before break_out_memory_refs was called.
1500 In some cases it is useful to look at this to decide what needs to be done.
1502 MODE and WIN are passed so that this macro can use
1503 GO_IF_LEGITIMATE_ADDRESS.
1505 It is always safe for this macro to do nothing. It exists to recognize
1506 opportunities to optimize the output.
1508 For the 68000, we handle X+REG by loading X into a register R and
1509 using R+REG. R will go in an address reg and indexing will be used.
1510 However, if REG is a broken-out memory address or multiplication,
1511 nothing needs to be done because REG can certainly go in an address reg. */
1513 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1514 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1515 { register int ch = (X) != (OLDX); \
1516 if (GET_CODE (X) == PLUS) \
1518 if (GET_CODE (XEXP (X, 0)) == MULT) \
1519 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1520 if (GET_CODE (XEXP (X, 1)) == MULT) \
1521 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1522 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1523 && GET_CODE (XEXP (X, 0)) == REG) \
1525 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1526 if (GET_CODE (XEXP (X, 0)) == REG \
1527 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1528 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1529 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1530 { register rtx temp = gen_reg_rtx (Pmode); \
1531 register rtx val = force_operand (XEXP (X, 1), 0); \
1532 emit_move_insn (temp, val); \
1534 XEXP (X, 1) = temp; \
1536 else if (GET_CODE (XEXP (X, 1)) == REG \
1537 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1538 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1539 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1540 { register rtx temp = gen_reg_rtx (Pmode); \
1541 register rtx val = force_operand (XEXP (X, 0), 0); \
1542 emit_move_insn (temp, val); \
1544 XEXP (X, 0) = temp; \
1547 /* Go to LABEL if ADDR (a legitimate address expression)
1548 has an effect that depends on the machine mode it is used for.
1549 On the 68000, only predecrement and postincrement address depend thus
1550 (the amount of decrement or increment being the length of the operand). */
1552 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1553 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1555 /* Specify the machine mode that this machine uses
1556 for the index in the tablejump instruction. */
1557 #define CASE_VECTOR_MODE HImode
1559 /* Define as C expression which evaluates to nonzero if the tablejump
1560 instruction expects the table to contain offsets from the address of the
1562 Do not define this if the table should contain absolute addresses. */
1563 #define CASE_VECTOR_PC_RELATIVE 1
1565 /* Specify the tree operation to be used to convert reals to integers. */
1566 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1568 /* This is the kind of divide that is easiest to do in the general case. */
1569 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1571 /* Define this as 1 if `char' should by default be signed; else as 0. */
1572 #define DEFAULT_SIGNED_CHAR 1
1574 /* Don't cse the address of the function being compiled. */
1575 #define NO_RECURSIVE_FUNCTION_CSE
1577 /* Max number of bytes we can move from memory to memory
1578 in one reasonably fast instruction. */
1581 /* Define this if zero-extension is slow (more than one real instruction). */
1582 #define SLOW_ZERO_EXTEND
1584 /* Nonzero if access to memory by bytes is slow and undesirable. */
1585 #define SLOW_BYTE_ACCESS 0
1587 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1588 is done just by pretending it is already truncated. */
1589 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1591 /* We assume that the store-condition-codes instructions store 0 for false
1592 and some other value for true. This is the value stored for true. */
1594 #define STORE_FLAG_VALUE -1
1596 /* When a prototype says `char' or `short', really pass an `int'. */
1597 #define PROMOTE_PROTOTYPES
1599 /* Specify the machine mode that pointers have.
1600 After generation of rtl, the compiler makes no further distinction
1601 between pointers and any other objects of this machine mode. */
1602 #define Pmode SImode
1604 /* A function address in a call instruction
1605 is a byte address (for indexing purposes)
1606 so give the MEM rtx a byte's mode. */
1607 #define FUNCTION_MODE QImode
1609 /* Compute the cost of computing a constant rtl expression RTX
1610 whose rtx-code is CODE. The body of this macro is a portion
1611 of a switch statement. If the code is computed here,
1612 return it with a return statement. Otherwise, break from the switch. */
1614 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1616 /* Constant zero is super cheap due to clr instruction. */ \
1617 if (RTX == const0_rtx) return 0; \
1618 /* if ((OUTER_CODE) == SET) */ \
1619 return const_int_cost(RTX); \
1624 case CONST_DOUBLE: \
1627 /* Compute the cost of various arithmetic operations.
1628 These are vaguely right for a 68020. */
1629 /* The costs for long multiply have been adjusted to
1630 work properly in synth_mult on the 68020,
1631 relative to an average of the time for add and the time for shift,
1632 taking away a little more because sometimes move insns are needed. */
1633 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1634 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1635 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1636 #define DIVW_COST (TARGET_68020 ? 27 : 12)
1638 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1640 /* An lea costs about three times as much as a simple add. */ \
1641 if (GET_MODE (X) == SImode \
1642 && GET_CODE (XEXP (X, 1)) == REG \
1643 && GET_CODE (XEXP (X, 0)) == MULT \
1644 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1645 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1646 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1647 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1648 || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1649 return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1655 return COSTS_N_INSNS(1); \
1656 if (! TARGET_68020) \
1658 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1660 if (INTVAL (XEXP (X, 1)) < 16) \
1661 return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \
1663 /* We're using clrw + swap for these cases. */ \
1664 return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \
1666 return COSTS_N_INSNS (10); /* worst case */ \
1668 /* A shift by a big integer takes an extra instruction. */ \
1669 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1670 && (INTVAL (XEXP (X, 1)) == 16)) \
1671 return COSTS_N_INSNS (2); /* clrw;swap */ \
1672 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1673 && !(INTVAL (XEXP (X, 1)) > 0 \
1674 && INTVAL (XEXP (X, 1)) <= 8)) \
1675 return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1678 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1679 || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \
1680 && GET_MODE (X) == SImode) \
1681 return COSTS_N_INSNS (MULW_COST); \
1682 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1683 return COSTS_N_INSNS (MULW_COST); \
1685 return COSTS_N_INSNS (MULL_COST); \
1690 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1691 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1692 return COSTS_N_INSNS (43); /* div.l */
1694 /* Tell final.c how to eliminate redundant test instructions. */
1696 /* Here we define machine-dependent flags and fields in cc_status
1697 (see `conditions.h'). */
1699 /* Set if the cc value is actually in the 68881, so a floating point
1700 conditional branch must be output. */
1701 #define CC_IN_68881 04000
1703 /* Store in cc_status the expressions that the condition codes will
1704 describe after execution of an instruction whose pattern is EXP.
1705 Do not alter them if the instruction would not alter the cc's. */
1707 /* On the 68000, all the insns to store in an address register fail to
1708 set the cc's. However, in some cases these instructions can make it
1709 possibly invalid to use the saved cc's. In those cases we clear out
1710 some or all of the saved cc's so they won't be used. */
1712 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1714 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1715 { if (cc_prev_status.flags & CC_IN_68881) \
1717 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1721 /* Control the assembler format that we output. */
1723 /* Output at beginning of assembler file. */
1725 #define ASM_FILE_START(FILE) \
1726 fprintf (FILE, "#NO_APP\n");
1728 /* Output to assembler file text saying following lines
1729 may contain character constants, extra white space, comments, etc. */
1731 #define ASM_APP_ON "#APP\n"
1733 /* Output to assembler file text saying following lines
1734 no longer contain unusual constructs. */
1736 #define ASM_APP_OFF "#NO_APP\n"
1738 /* Output before read-only data. */
1740 #define TEXT_SECTION_ASM_OP ".text"
1742 /* Output before writable data. */
1744 #define DATA_SECTION_ASM_OP ".data"
1746 /* Here are four prefixes that are used by asm_fprintf to
1747 facilitate customization for alternate assembler syntaxes.
1748 Machines with no likelihood of an alternate syntax need not
1749 define these and need not use asm_fprintf. */
1751 /* The prefix for register names. Note that REGISTER_NAMES
1752 is supposed to include this prefix. */
1754 #define REGISTER_PREFIX ""
1756 /* The prefix for local labels. You should be able to define this as
1757 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1758 without having to make any other changes to account for the specific
1759 definition. Note it is a string literal, not interpreted by printf
1762 #define LOCAL_LABEL_PREFIX ""
1764 /* The prefix to add to user-visible assembler symbols. */
1766 #define USER_LABEL_PREFIX "_"
1768 /* The prefix for immediate operands. */
1770 #define IMMEDIATE_PREFIX "#"
1772 /* How to refer to registers in assembler output.
1773 This sequence is indexed by compiler's hard-register-number (see above). */
1775 #ifndef SUPPORT_SUN_FPA
1777 #define REGISTER_NAMES \
1778 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1779 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1780 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1782 #else /* SUPPORTED_SUN_FPA */
1784 #define REGISTER_NAMES \
1785 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1786 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1787 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1788 "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1789 "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1790 "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1791 "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1793 #endif /* defined SUPPORT_SUN_FPA */
1795 /* How to renumber registers for dbx and gdb.
1796 On the Sun-3, the floating point registers have numbers
1797 18 to 25, not 16 to 23 as they do in the compiler. */
1799 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1801 /* Before the prologue, RA is at 0(%sp). */
1802 #define INCOMING_RETURN_ADDR_RTX \
1803 gen_rtx (MEM, VOIDmode, gen_rtx (REG, VOIDmode, STACK_POINTER_REGNUM))
1805 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1806 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1807 Instead use the identity mapping. */
1808 #define DWARF_FRAME_REGNUM(REG) REG
1810 /* Before the prologue, the top of the frame is at 4(%sp). */
1811 #define INCOMING_FRAME_SP_OFFSET 4
1813 /* This is how to output the definition of a user-level label named NAME,
1814 such as the label on a static function or variable NAME. */
1816 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1817 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1819 /* This is how to output a command to make the user-level label named NAME
1820 defined for reference from other files. */
1822 #define GLOBAL_ASM_OP ".globl"
1823 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1824 do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \
1825 assemble_name (FILE, NAME); \
1826 fputs ("\n", FILE);} while (0)
1828 /* This is how to output a reference to a user-level label named NAME.
1829 `assemble_name' uses this. */
1831 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1832 asm_fprintf (FILE, "%0U%s", NAME)
1834 /* This is how to output an internal numbered label where
1835 PREFIX is the class of label and NUM is the number within the class. */
1837 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1838 asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1840 /* This is how to store into the string LABEL
1841 the symbol_ref name of an internal numbered label where
1842 PREFIX is the class of label and NUM is the number within the class.
1843 This is suitable for output with `assemble_name'. */
1845 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1846 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
1848 /* This is how to output a `long double' extended real constant. */
1850 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1852 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
1853 if (sizeof (int) == sizeof (long)) \
1854 fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \
1856 fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \
1859 /* This is how to output an assembler line defining a `double' constant. */
1861 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1862 do { char dstr[30]; \
1863 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
1864 fprintf (FILE, "\t.double 0r%s\n", dstr); \
1867 /* This is how to output an assembler line defining a `float' constant. */
1869 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1871 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1872 if (sizeof (int) == sizeof (long)) \
1873 fprintf (FILE, "\t.long 0x%x\n", l); \
1875 fprintf (FILE, "\t.long 0x%lx\n", l); \
1878 /* This is how to output an assembler line defining an `int' constant. */
1880 #define ASM_OUTPUT_INT(FILE,VALUE) \
1881 ( fprintf (FILE, "\t.long "), \
1882 output_addr_const (FILE, (VALUE)), \
1883 fprintf (FILE, "\n"))
1885 /* Likewise for `char' and `short' constants. */
1887 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1888 ( fprintf (FILE, "\t.word "), \
1889 output_addr_const (FILE, (VALUE)), \
1890 fprintf (FILE, "\n"))
1892 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1893 ( fprintf (FILE, "\t.byte "), \
1894 output_addr_const (FILE, (VALUE)), \
1895 fprintf (FILE, "\n"))
1897 /* This is how to output an assembler line for a numeric constant byte. */
1899 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1900 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1902 /* This is how to output an insn to push a register on the stack.
1903 It need not be very fast code. */
1905 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1906 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1908 /* This is how to output an insn to pop a register from the stack.
1909 It need not be very fast code. */
1911 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1912 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1914 /* This is how to output an element of a case-vector that is absolute.
1915 (The 68000 does not use such vectors,
1916 but we must define this macro anyway.) */
1918 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1919 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1921 /* This is how to output an element of a case-vector that is relative. */
1923 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1924 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1926 /* This is how to output an assembler line
1927 that says to advance the location counter
1928 to a multiple of 2**LOG bytes. */
1930 /* We don't have a way to align to more than a two-byte boundary, so do the
1931 best we can and don't complain. */
1932 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1934 fprintf (FILE, "\t.even\n");
1936 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1937 fprintf (FILE, "\t.skip %u\n", (SIZE))
1939 /* This says how to output an assembler line
1940 to define a global common symbol. */
1942 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1943 ( fputs (".comm ", (FILE)), \
1944 assemble_name ((FILE), (NAME)), \
1945 fprintf ((FILE), ",%u\n", (ROUNDED)))
1947 /* This says how to output an assembler line
1948 to define a local common symbol. */
1950 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1951 ( fputs (".lcomm ", (FILE)), \
1952 assemble_name ((FILE), (NAME)), \
1953 fprintf ((FILE), ",%u\n", (ROUNDED)))
1955 /* Store in OUTPUT a string (made with alloca) containing
1956 an assembler-name for a local static variable named NAME.
1957 LABELNO is an integer which is different for each call. */
1959 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1960 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1961 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1963 /* Define the parentheses used to group arithmetic operations
1964 in assembler code. */
1966 #define ASM_OPEN_PAREN "("
1967 #define ASM_CLOSE_PAREN ")"
1969 /* Define results of standard character escape sequences. */
1970 #define TARGET_BELL 007
1971 #define TARGET_BS 010
1972 #define TARGET_TAB 011
1973 #define TARGET_NEWLINE 012
1974 #define TARGET_VT 013
1975 #define TARGET_FF 014
1976 #define TARGET_CR 015
1978 /* Output a float value (represented as a C double) as an immediate operand.
1979 This macro is a 68k-specific macro. */
1981 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1986 REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \
1987 asm_fprintf ((FILE), "%I0r%s", dstr); \
1992 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1993 if (sizeof (int) == sizeof (long)) \
1994 asm_fprintf ((FILE), "%I0x%x", l); \
1996 asm_fprintf ((FILE), "%I0x%lx", l); \
2000 /* Output a double value (represented as a C double) as an immediate operand.
2001 This macro is a 68k-specific macro. */
2002 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
2003 do { char dstr[30]; \
2004 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2005 asm_fprintf (FILE, "%I0r%s", dstr); \
2008 /* Note, long double immediate operands are not actually
2009 generated by m68k.md. */
2010 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
2011 do { char dstr[30]; \
2012 REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \
2013 asm_fprintf (FILE, "%I0r%s", dstr); \
2016 /* Print operand X (an rtx) in assembler syntax to file FILE.
2017 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2018 For `%' followed by punctuation, CODE is the punctuation and X is null.
2020 On the 68000, we use several CODE characters:
2021 '.' for dot needed in Motorola-style opcode names.
2022 '-' for an operand pushing on the stack:
2023 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2024 '+' for an operand pushing on the stack:
2025 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2026 '@' for a reference to the top word on the stack:
2027 sp@, (sp) or (%sp) depending on the style of syntax.
2028 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2029 but & in SGS syntax).
2030 '!' for the fpcr register (used in some float-to-fixed conversions).
2031 '$' for the letter `s' in an op code, but only on the 68040.
2032 '&' for the letter `d' in an op code, but only on the 68040.
2033 '/' for register prefix needed by longlong.h.
2035 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2036 'd' to force memory addressing to be absolute, not relative.
2037 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2038 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2039 than directly). Second part of 'y' below.
2040 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2041 or print pair of registers as rx:ry.
2042 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2043 CONST_DOUBLE's as SunFPA constant RAM registers if
2044 possible, so it should not be used except for the SunFPA. */
2046 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2047 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
2048 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
2049 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
2051 /* A C compound statement to output to stdio stream STREAM the
2052 assembler syntax for an instruction operand X. X is an RTL
2055 CODE is a value that can be used to specify one of several ways
2056 of printing the operand. It is used when identical operands
2057 must be printed differently depending on the context. CODE
2058 comes from the `%' specification that was used to request
2059 printing of the operand. If the specification was just `%DIGIT'
2060 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2061 is the ASCII code for LTR.
2063 If X is a register, this macro should print the register's name.
2064 The names can be found in an array `reg_names' whose type is
2065 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2067 When the machine description has a specification `%PUNCT' (a `%'
2068 followed by a punctuation character), this macro is called with
2069 a null pointer for X and the punctuation character for CODE.
2071 See m68k.c for the m68k specific codes. */
2073 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2075 /* A C compound statement to output to stdio stream STREAM the
2076 assembler syntax for an instruction operand that is a memory
2077 reference whose address is ADDR. ADDR is an RTL expression.
2079 On some machines, the syntax for a symbolic address depends on
2080 the section that the address refers to. On these machines,
2081 define the macro `ENCODE_SECTION_INFO' to store the information
2082 into the `symbol_ref', and then check for it here. */
2084 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2086 /* Define functions defined in aux-output.c and used in templates. */
2088 extern char *output_move_const_into_data_reg ();
2089 extern char *output_move_simode_const ();
2090 extern char *output_move_simode ();
2091 extern char *output_move_himode ();
2092 extern char *output_move_qimode ();
2093 extern char *output_move_stricthi ();
2094 extern char *output_move_strictqi ();
2095 extern char *output_move_double ();
2096 extern char *output_move_const_single ();
2097 extern char *output_move_const_double ();
2098 extern char *output_btst ();
2099 extern char *output_scc_di ();
2100 extern char *output_addsi3 ();
2101 extern char *output_andsi3 ();
2102 extern char *output_iorsi3 ();
2103 extern char *output_xorsi3 ();
2105 /* Variables in m68k.c */
2106 extern char *m68k_align_loops_string;
2107 extern char *m68k_align_jumps_string;
2108 extern char *m68k_align_funcs_string;
2109 extern int m68k_align_loops;
2110 extern int m68k_align_jumps;
2111 extern int m68k_align_funcs;
2112 extern int m68k_last_compare_had_fp_operands;
OSDN Git Service
