1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
40 #include "target-def.h"
43 /* Needed for use_return_insn. */
46 #ifdef SUPPORT_SUN_FPA
48 /* Index into this array by (register number >> 3) to find the
49 smallest class which contains that register. */
50 const enum reg_class regno_reg_class[]
51 = { DATA_REGS, ADDR_REGS, FP_REGS,
52 LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
54 #endif /* defined SUPPORT_SUN_FPA */
56 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
57 if SGS_SWITCH_TABLE. */
58 int switch_table_difference_label_flag;
60 static rtx find_addr_reg PARAMS ((rtx));
61 static const char *singlemove_string PARAMS ((rtx *));
62 static void m68k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
63 static void m68k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
64 static void m68k_coff_asm_named_section PARAMS ((const char *, unsigned int));
65 #ifdef CTOR_LIST_BEGIN
66 static void m68k_svr3_asm_out_constructor PARAMS ((rtx, int));
70 /* Alignment to use for loops and jumps */
71 /* Specify power of two alignment used for loops. */
72 const char *m68k_align_loops_string;
73 /* Specify power of two alignment used for non-loop jumps. */
74 const char *m68k_align_jumps_string;
75 /* Specify power of two alignment used for functions. */
76 const char *m68k_align_funcs_string;
78 /* Specify power of two alignment used for loops. */
80 /* Specify power of two alignment used for non-loop jumps. */
82 /* Specify power of two alignment used for functions. */
85 /* Nonzero if the last compare/test insn had FP operands. The
86 sCC expanders peek at this to determine what to do for the
87 68060, which has no fsCC instructions. */
88 int m68k_last_compare_had_fp_operands;
90 /* Initialize the GCC target structure. */
92 #if INT_OP_GROUP == INT_OP_DOT_WORD
93 #undef TARGET_ASM_ALIGNED_HI_OP
94 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
97 #if INT_OP_GROUP == INT_OP_NO_DOT
98 #undef TARGET_ASM_BYTE_OP
99 #define TARGET_ASM_BYTE_OP "\tbyte\t"
100 #undef TARGET_ASM_ALIGNED_HI_OP
101 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
102 #undef TARGET_ASM_ALIGNED_SI_OP
103 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
106 #if INT_OP_GROUP == INT_OP_DC
107 #undef TARGET_ASM_BYTE_OP
108 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
109 #undef TARGET_ASM_ALIGNED_HI_OP
110 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
111 #undef TARGET_ASM_ALIGNED_SI_OP
112 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
115 #undef TARGET_ASM_UNALIGNED_HI_OP
116 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
117 #undef TARGET_ASM_UNALIGNED_SI_OP
118 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
120 #undef TARGET_ASM_FUNCTION_PROLOGUE
121 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
122 #undef TARGET_ASM_FUNCTION_EPILOGUE
123 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
125 struct gcc_target targetm = TARGET_INITIALIZER;
127 /* Sometimes certain combinations of command options do not make
128 sense on a particular target machine. You can define a macro
129 `OVERRIDE_OPTIONS' to take account of this. This macro, if
130 defined, is executed once just after all the command options have
133 Don't use this macro to turn on various extra optimizations for
134 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
144 /* Validate -malign-loops= value, or provide default */
145 m68k_align_loops = def_align;
146 if (m68k_align_loops_string)
148 i = atoi (m68k_align_loops_string);
149 if (i < 1 || i > MAX_CODE_ALIGN)
150 error ("-malign-loops=%d is not between 1 and %d", i, MAX_CODE_ALIGN);
152 m68k_align_loops = i;
155 /* Validate -malign-jumps= value, or provide default */
156 m68k_align_jumps = def_align;
157 if (m68k_align_jumps_string)
159 i = atoi (m68k_align_jumps_string);
160 if (i < 1 || i > MAX_CODE_ALIGN)
161 error ("-malign-jumps=%d is not between 1 and %d", i, MAX_CODE_ALIGN);
163 m68k_align_jumps = i;
166 /* Validate -malign-functions= value, or provide default */
167 m68k_align_funcs = def_align;
168 if (m68k_align_funcs_string)
170 i = atoi (m68k_align_funcs_string);
171 if (i < 1 || i > MAX_CODE_ALIGN)
172 error ("-malign-functions=%d is not between 1 and %d",
175 m68k_align_funcs = i;
178 /* Tell the compiler which flavor of XFmode we're using. */
179 real_format_for_mode[XFmode - QFmode] = &ieee_extended_motorola_format;
182 /* This function generates the assembly code for function entry.
183 STREAM is a stdio stream to output the code to.
184 SIZE is an int: how many units of temporary storage to allocate.
185 Refer to the array `regs_ever_live' to determine which registers
186 to save; `regs_ever_live[I]' is nonzero if register number I
187 is ever used in the function. This function is responsible for
188 knowing which registers should not be saved even if used. */
191 /* Note that the order of the bit mask for fmovem is the opposite
192 of the order for movem! */
197 m68k_output_function_prologue (stream, size)
202 register int mask = 0;
203 HOST_WIDE_INT fsize = ((size) + 3) & -4;
205 /* unos stack probe */
208 fprintf (stream, "\tmovel sp,a0\n");
209 fprintf (stream, "\taddl $-%d,a0\n", 2048 + fsize);
210 fprintf (stream, "\ttstb (a0)\n");
213 fprintf (stream, "\ttstb -%d(sp)\n", 2048 + fsize);
215 if (frame_pointer_needed)
217 if (TARGET_68020 || fsize < 0x8000)
218 fprintf (stream, "\tlink a6,$%d\n", -fsize);
220 fprintf (stream, "\tlink a6,$0\n\tsubl $%d,sp\n", fsize);
224 /* Adding negative number is faster on the 68040. */
225 if (fsize + 4 < 0x8000)
226 fprintf (stream, "\tadd.w #%d,sp\n", - (fsize + 4));
228 fprintf (stream, "\tadd.l #%d,sp\n", - (fsize + 4));
231 for (regno = 16; regno < 24; regno++)
232 if (regs_ever_live[regno] && ! call_used_regs[regno])
233 mask |= 1 << (regno - 16);
235 if ((mask & 0xff) != 0)
236 fprintf (stream, "\tfmovem $0x%x,-(sp)\n", mask & 0xff);
239 for (regno = 0; regno < 16; regno++)
240 if (regs_ever_live[regno] && ! call_used_regs[regno])
241 mask |= 1 << (15 - regno);
242 if (frame_pointer_needed)
243 mask &= ~ (1 << (15-FRAME_POINTER_REGNUM));
245 if (exact_log2 (mask) >= 0)
246 fprintf (stream, "\tmovel %s,-(sp)\n", reg_names[15 - exact_log2 (mask)]);
248 fprintf (stream, "\tmovem $0x%x,-(sp)\n", mask);
254 m68k_output_function_prologue (stream, size)
259 register int mask = 0;
260 int num_saved_regs = 0;
261 HOST_WIDE_INT fsize = (size + 3) & -4;
262 HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET;
263 HOST_WIDE_INT cfa_store_offset = cfa_offset;
265 /* If the stack limit is a symbol, we can check it here,
266 before actually allocating the space. */
267 if (current_function_limit_stack
268 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
270 #if defined (MOTOROLA)
271 asm_fprintf (stream, "\tcmp.l %0I%s+%d,%Rsp\n\ttrapcs\n",
272 XSTR (stack_limit_rtx, 0), fsize + 4);
274 asm_fprintf (stream, "\tcmpl %0I%s+%d,%Rsp\n\ttrapcs\n",
275 XSTR (stack_limit_rtx, 0), fsize + 4);
279 if (frame_pointer_needed)
281 if (fsize == 0 && TARGET_68040)
283 /* on the 68040, pea + move is faster than link.w 0 */
285 fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
286 reg_names[FRAME_POINTER_REGNUM],
287 reg_names[STACK_POINTER_REGNUM],
288 reg_names[FRAME_POINTER_REGNUM]);
290 fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
291 reg_names[FRAME_POINTER_REGNUM],
292 reg_names[STACK_POINTER_REGNUM],
293 reg_names[FRAME_POINTER_REGNUM]);
296 else if (fsize < 0x8000)
299 asm_fprintf (stream, "\tlink.w %s,%0I%d\n",
300 reg_names[FRAME_POINTER_REGNUM], -fsize);
302 asm_fprintf (stream, "\tlink %s,%0I%d\n",
303 reg_names[FRAME_POINTER_REGNUM], -fsize);
306 else if (TARGET_68020)
309 asm_fprintf (stream, "\tlink.l %s,%0I%d\n",
310 reg_names[FRAME_POINTER_REGNUM], -fsize);
312 asm_fprintf (stream, "\tlink %s,%0I%d\n",
313 reg_names[FRAME_POINTER_REGNUM], -fsize);
318 /* Adding negative number is faster on the 68040. */
320 asm_fprintf (stream, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
321 reg_names[FRAME_POINTER_REGNUM], -fsize);
323 asm_fprintf (stream, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
324 reg_names[FRAME_POINTER_REGNUM], -fsize);
327 if (dwarf2out_do_frame ())
330 l = (char *) dwarf2out_cfi_label ();
331 cfa_store_offset += 4;
332 cfa_offset = cfa_store_offset;
333 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
334 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
335 cfa_store_offset += fsize;
340 if (fsize + 4 < 0x8000)
347 /* asm_fprintf() cannot handle %. */
349 asm_fprintf (stream, "\tsubq.w %0I%d,%Rsp\n", fsize + 4);
351 asm_fprintf (stream, "\tsubqw %0I%d,%Rsp\n", fsize + 4);
356 /* asm_fprintf() cannot handle %. */
358 asm_fprintf (stream, "\tsubq.l %0I%d,%Rsp\n", fsize + 4);
360 asm_fprintf (stream, "\tsubql %0I%d,%Rsp\n", fsize + 4);
364 else if (fsize + 4 <= 16 && TARGET_CPU32)
366 /* On the CPU32 it is faster to use two subqw instructions to
367 subtract a small integer (8 < N <= 16) to a register. */
368 /* asm_fprintf() cannot handle %. */
370 asm_fprintf (stream, "\tsubq.w %0I8,%Rsp\n\tsubq.w %0I%d,%Rsp\n",
373 asm_fprintf (stream, "\tsubqw %0I8,%Rsp\n\tsubqw %0I%d,%Rsp\n",
378 #endif /* not NO_ADDSUB_Q */
381 /* Adding negative number is faster on the 68040. */
382 /* asm_fprintf() cannot handle %. */
384 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", - (fsize + 4));
386 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", - (fsize + 4));
392 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", - (fsize + 4));
394 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", - (fsize + 4));
400 /* asm_fprintf() cannot handle %. */
402 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", - (fsize + 4));
404 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", - (fsize + 4));
407 if (dwarf2out_do_frame ())
409 cfa_store_offset += fsize;
410 cfa_offset = cfa_store_offset;
411 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
414 #ifdef SUPPORT_SUN_FPA
415 for (regno = 24; regno < 56; regno++)
416 if (regs_ever_live[regno] && ! call_used_regs[regno])
419 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
422 asm_fprintf (stream, "\tfpmoved %s,%Rsp@-\n",
425 if (dwarf2out_do_frame ())
427 char *l = dwarf2out_cfi_label ();
429 cfa_store_offset += 8;
430 if (! frame_pointer_needed)
432 cfa_offset = cfa_store_offset;
433 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
435 dwarf2out_reg_save (l, regno, -cfa_store_offset);
441 for (regno = 16; regno < 24; regno++)
442 if (regs_ever_live[regno] && ! call_used_regs[regno])
444 mask |= 1 << (regno - 16);
447 if ((mask & 0xff) != 0)
450 asm_fprintf (stream, "\tfmovm %0I0x%x,-(%Rsp)\n", mask & 0xff);
452 asm_fprintf (stream, "\tfmovem %0I0x%x,%Rsp@-\n", mask & 0xff);
454 if (dwarf2out_do_frame ())
456 char *l = (char *) dwarf2out_cfi_label ();
459 cfa_store_offset += num_saved_regs * 12;
460 if (! frame_pointer_needed)
462 cfa_offset = cfa_store_offset;
463 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
465 for (regno = 16, n_regs = 0; regno < 24; regno++)
466 if (mask & (1 << (regno - 16)))
467 dwarf2out_reg_save (l, regno,
468 -cfa_store_offset + n_regs++ * 12);
474 for (regno = 0; regno < 16; regno++)
475 if (regs_ever_live[regno] && ! call_used_regs[regno])
477 mask |= 1 << (15 - regno);
480 if (frame_pointer_needed)
482 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
485 if (flag_pic && current_function_uses_pic_offset_table)
487 mask |= 1 << (15 - PIC_OFFSET_TABLE_REGNUM);
493 asm_fprintf (stream, "\ttst.l %d(%Rsp)\n", NEED_PROBE - num_saved_regs * 4);
495 asm_fprintf (stream, "\ttstl %Rsp@(%d)\n", NEED_PROBE - num_saved_regs * 4);
499 /* If the stack limit is not a symbol, check it here.
500 This has the disadvantage that it may be too late... */
501 if (current_function_limit_stack)
503 if (REG_P (stack_limit_rtx))
505 #if defined (MOTOROLA)
506 asm_fprintf (stream, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
507 reg_names[REGNO (stack_limit_rtx)]);
509 asm_fprintf (stream, "\tcmpl %s,%Rsp\n\ttrapcs\n",
510 reg_names[REGNO (stack_limit_rtx)]);
513 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
514 warning ("stack limit expression is not supported");
517 if (num_saved_regs <= 2)
519 /* Store each separately in the same order moveml uses.
520 Using two movel instructions instead of a single moveml
521 is about 15% faster for the 68020 and 68030 at no expense
526 /* Undo the work from above. */
527 for (i = 0; i< 16; i++)
532 "\t%Omove.l %s,-(%Rsp)\n",
534 "\tmovel %s,%Rsp@-\n",
537 if (dwarf2out_do_frame ())
539 char *l = (char *) dwarf2out_cfi_label ();
541 cfa_store_offset += 4;
542 if (! frame_pointer_needed)
544 cfa_offset = cfa_store_offset;
545 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
547 dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
555 /* The coldfire does not support the predecrement form of the
556 movml instruction, so we must adjust the stack pointer and
557 then use the plain address register indirect mode. We also
558 have to invert the register save mask to use the new mode.
560 FIXME: if num_saved_regs was calculated earlier, we could
561 combine the stack pointer adjustment with any adjustment
562 done when the initial stack frame is created. This would
563 save an instruction */
568 for (i = 0; i < 16; i++)
570 newmask |= (1 << (15-i));
573 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
574 asm_fprintf (stream, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask);
576 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
577 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@\n", newmask);
583 asm_fprintf (stream, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask);
585 asm_fprintf (stream, "\tmoveml %0I0x%x,%Rsp@-\n", mask);
588 if (dwarf2out_do_frame ())
590 char *l = (char *) dwarf2out_cfi_label ();
593 cfa_store_offset += num_saved_regs * 4;
594 if (! frame_pointer_needed)
596 cfa_offset = cfa_store_offset;
597 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
599 for (regno = 0, n_regs = 0; regno < 16; regno++)
600 if (mask & (1 << (15 - regno)))
601 dwarf2out_reg_save (l, regno,
602 -cfa_store_offset + n_regs++ * 4);
605 if (flag_pic && current_function_uses_pic_offset_table)
608 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
609 reg_names[PIC_OFFSET_TABLE_REGNUM]);
611 asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
612 reg_names[PIC_OFFSET_TABLE_REGNUM]);
613 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
614 reg_names[PIC_OFFSET_TABLE_REGNUM],
615 reg_names[PIC_OFFSET_TABLE_REGNUM]);
621 /* Return true if this function's epilogue can be output as RTL. */
628 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
631 /* Copied from output_function_epilogue (). We should probably create a
632 separate layout routine to perform the common work. */
634 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
635 if (regs_ever_live[regno] && ! call_used_regs[regno])
638 if (flag_pic && current_function_uses_pic_offset_table)
644 /* This function generates the assembly code for function exit,
645 on machines that need it.
647 The function epilogue should not depend on the current stack pointer!
648 It should use the frame pointer only, if there is a frame pointer.
649 This is mandatory because of alloca; we also take advantage of it to
650 omit stack adjustments before returning. */
655 m68k_output_function_epilogue (stream, size)
660 register int mask, fmask;
662 HOST_WIDE_INT offset, foffset, fpoffset;
663 HOST_WIDE_INT fsize = ((size) + 3) & -4;
666 nregs = 0; fmask = 0; fpoffset = 0;
667 for (regno = 16; regno < 24; regno++)
668 if (regs_ever_live[regno] && ! call_used_regs[regno])
671 fmask |= 1 << (23 - regno);
674 foffset = fpoffset + nregs * 12;
676 if (frame_pointer_needed)
677 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
679 for (regno = 0; regno < 16; regno++)
680 if (regs_ever_live[regno] && ! call_used_regs[regno])
686 offset = foffset + nregs * 4;
687 if (offset + fsize >= 0x8000
688 && frame_pointer_needed
689 && (mask || fmask || fpoffset))
691 fprintf (stream, "\tmovel $%d,a0\n", -fsize);
695 if (exact_log2 (mask) >= 0)
698 fprintf (stream, "\tmovel -%d(a6,a0.l),%s\n",
699 offset + fsize, reg_names[exact_log2 (mask)]);
700 else if (! frame_pointer_needed)
701 fprintf (stream, "\tmovel (sp)+,%s\n",
702 reg_names[exact_log2 (mask)]);
704 fprintf (stream, "\tmovel -%d(a6),%s\n",
705 offset + fsize, reg_names[exact_log2 (mask)]);
710 fprintf (stream, "\tmovem -%d(a6,a0.l),$0x%x\n",
711 offset + fsize, mask);
712 else if (! frame_pointer_needed)
713 fprintf (stream, "\tmovem (sp)+,$0x%x\n", mask);
715 fprintf (stream, "\tmovem -%d(a6),$0x%x\n",
716 offset + fsize, mask);
722 fprintf (stream, "\tfmovem -%d(a6,a0.l),$0x%x\n",
723 foffset + fsize, fmask);
724 else if (! frame_pointer_needed)
725 fprintf (stream, "\tfmovem (sp)+,$0x%x\n", fmask);
727 fprintf (stream, "\tfmovem -%d(a6),$0x%x\n",
728 foffset + fsize, fmask);
732 for (regno = 55; regno >= 24; regno--)
733 if (regs_ever_live[regno] && ! call_used_regs[regno])
736 fprintf(stream, "\tfpmoved -%d(a6,a0.l), %s\n",
737 fpoffset + fsize, reg_names[regno]);
738 else if (! frame_pointer_needed)
739 fprintf(stream, "\tfpmoved (sp)+, %s\n",
742 fprintf(stream, "\tfpmoved -%d(a6), %s\n",
743 fpoffset + fsize, reg_names[regno]);
747 if (frame_pointer_needed)
748 fprintf (stream, "\tunlk a6\n");
751 if (fsize + 4 < 0x8000)
752 fprintf (stream, "\tadd.w #%d,sp\n", fsize + 4);
754 fprintf (stream, "\tadd.l #%d,sp\n", fsize + 4);
757 if (current_function_pops_args)
758 fprintf (stream, "\trtd $%d\n", current_function_pops_args);
760 fprintf (stream, "\trts\n");
766 m68k_output_function_epilogue (stream, size)
771 register int mask, fmask;
773 HOST_WIDE_INT offset, foffset, fpoffset;
774 HOST_WIDE_INT fsize = (size + 3) & -4;
776 rtx insn = get_last_insn ();
777 int restore_from_sp = 0;
779 /* If the last insn was a BARRIER, we don't have to write any code. */
780 if (GET_CODE (insn) == NOTE)
781 insn = prev_nonnote_insn (insn);
782 if (insn && GET_CODE (insn) == BARRIER)
784 /* Output just a no-op so that debuggers don't get confused
785 about which function the pc is in at this address. */
786 fprintf (stream, "\tnop\n");
790 #ifdef FUNCTION_EXTRA_EPILOGUE
791 FUNCTION_EXTRA_EPILOGUE (stream, size);
793 nregs = 0; fmask = 0; fpoffset = 0;
794 #ifdef SUPPORT_SUN_FPA
795 for (regno = 24 ; regno < 56 ; regno++)
796 if (regs_ever_live[regno] && ! call_used_regs[regno])
798 fpoffset = nregs * 8;
803 for (regno = 16; regno < 24; regno++)
804 if (regs_ever_live[regno] && ! call_used_regs[regno])
807 fmask |= 1 << (23 - regno);
810 foffset = fpoffset + nregs * 12;
812 if (frame_pointer_needed)
813 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
814 for (regno = 0; regno < 16; regno++)
815 if (regs_ever_live[regno] && ! call_used_regs[regno])
820 if (flag_pic && current_function_uses_pic_offset_table)
823 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
825 offset = foffset + nregs * 4;
826 /* FIXME : leaf_function_p below is too strong.
827 What we really need to know there is if there could be pending
828 stack adjustment needed at that point. */
829 restore_from_sp = ! frame_pointer_needed
830 || (! current_function_calls_alloca && leaf_function_p ());
831 if (offset + fsize >= 0x8000
833 && (mask || fmask || fpoffset))
836 asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
838 asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
842 if (TARGET_5200 || nregs <= 2)
844 /* Restore each separately in the same order moveml does.
845 Using two movel instructions instead of a single moveml
846 is about 15% faster for the 68020 and 68030 at no expense
851 /* Undo the work from above. */
852 for (i = 0; i< 16; i++)
858 asm_fprintf (stream, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
860 reg_names[FRAME_POINTER_REGNUM],
863 asm_fprintf (stream, "\tmovel %s@(-%d,%Ra1:l),%s\n",
864 reg_names[FRAME_POINTER_REGNUM],
865 offset + fsize, reg_names[i]);
868 else if (restore_from_sp)
871 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
874 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
881 asm_fprintf (stream, "\t%Omove.l -%d(%s),%s\n",
883 reg_names[FRAME_POINTER_REGNUM],
886 fprintf (stream, "\tmovel %s@(-%d),%s\n",
887 reg_names[FRAME_POINTER_REGNUM],
888 offset + fsize, reg_names[i]);
899 asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
901 reg_names[FRAME_POINTER_REGNUM],
904 asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
905 reg_names[FRAME_POINTER_REGNUM],
906 offset + fsize, mask);
909 else if (restore_from_sp)
912 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
914 asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
920 asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
922 reg_names[FRAME_POINTER_REGNUM],
925 asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
926 reg_names[FRAME_POINTER_REGNUM],
927 offset + fsize, mask);
936 asm_fprintf (stream, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
938 reg_names[FRAME_POINTER_REGNUM],
941 asm_fprintf (stream, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
942 reg_names[FRAME_POINTER_REGNUM],
943 foffset + fsize, fmask);
946 else if (restore_from_sp)
949 asm_fprintf (stream, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask);
951 asm_fprintf (stream, "\tfmovem %Rsp@+,%0I0x%x\n", fmask);
957 asm_fprintf (stream, "\tfmovm -%d(%s),%0I0x%x\n",
959 reg_names[FRAME_POINTER_REGNUM],
962 asm_fprintf (stream, "\tfmovem %s@(-%d),%0I0x%x\n",
963 reg_names[FRAME_POINTER_REGNUM],
964 foffset + fsize, fmask);
969 for (regno = 55; regno >= 24; regno--)
970 if (regs_ever_live[regno] && ! call_used_regs[regno])
975 asm_fprintf (stream, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
977 reg_names[FRAME_POINTER_REGNUM],
980 asm_fprintf (stream, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
981 reg_names[FRAME_POINTER_REGNUM],
982 fpoffset + fsize, reg_names[regno]);
985 else if (restore_from_sp)
988 asm_fprintf (stream, "\tfpmovd (%Rsp)+,%s\n",
991 asm_fprintf (stream, "\tfpmoved %Rsp@+, %s\n",
998 fprintf (stream, "\tfpmovd -%d(%s), %s\n",
1000 reg_names[FRAME_POINTER_REGNUM],
1003 fprintf (stream, "\tfpmoved %s@(-%d), %s\n",
1004 reg_names[FRAME_POINTER_REGNUM],
1005 fpoffset + fsize, reg_names[regno]);
1010 if (frame_pointer_needed)
1011 fprintf (stream, "\tunlk %s\n",
1012 reg_names[FRAME_POINTER_REGNUM]);
1021 asm_fprintf (stream, "\taddq.w %0I%d,%Rsp\n", fsize + 4);
1023 asm_fprintf (stream, "\taddqw %0I%d,%Rsp\n", fsize + 4);
1029 asm_fprintf (stream, "\taddq.l %0I%d,%Rsp\n", fsize + 4);
1031 asm_fprintf (stream, "\taddql %0I%d,%Rsp\n", fsize + 4);
1035 else if (fsize + 4 <= 16 && TARGET_CPU32)
1037 /* On the CPU32 it is faster to use two addqw instructions to
1038 add a small integer (8 < N <= 16) to a register. */
1039 /* asm_fprintf() cannot handle %. */
1041 asm_fprintf (stream, "\taddq.w %0I8,%Rsp\n\taddq.w %0I%d,%Rsp\n",
1044 asm_fprintf (stream, "\taddqw %0I8,%Rsp\n\taddqw %0I%d,%Rsp\n",
1049 #endif /* not NO_ADDSUB_Q */
1050 if (fsize + 4 < 0x8000)
1054 /* asm_fprintf() cannot handle %. */
1056 asm_fprintf (stream, "\tadd.w %0I%d,%Rsp\n", fsize + 4);
1058 asm_fprintf (stream, "\taddw %0I%d,%Rsp\n", fsize + 4);
1064 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", fsize + 4);
1066 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", fsize + 4);
1072 /* asm_fprintf() cannot handle %. */
1074 asm_fprintf (stream, "\tadd.l %0I%d,%Rsp\n", fsize + 4);
1076 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
1080 if (current_function_pops_args)
1081 asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
1083 fprintf (stream, "\trts\n");
1087 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1090 not_sp_operand (op, mode)
1092 enum machine_mode mode;
1094 return op != stack_pointer_rtx && nonimmediate_operand (op, mode);
1097 /* Return TRUE if X is a valid comparison operator for the dbcc
1100 Note it rejects floating point comparison operators.
1101 (In the future we could use Fdbcc).
1103 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1106 valid_dbcc_comparison_p (x, mode)
1108 enum machine_mode mode ATTRIBUTE_UNUSED;
1110 switch (GET_CODE (x))
1112 case EQ: case NE: case GTU: case LTU:
1116 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1118 case GT: case LT: case GE: case LE:
1119 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1125 /* Return nonzero if flags are currently in the 68881 flag register. */
1129 /* We could add support for these in the future */
1130 return cc_status.flags & CC_IN_68881;
1133 /* Output a dbCC; jCC sequence. Note we do not handle the
1134 floating point version of this sequence (Fdbcc). We also
1135 do not handle alternative conditions when CC_NO_OVERFLOW is
1136 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1137 kick those out before we get here. */
1140 output_dbcc_and_branch (operands)
1143 switch (GET_CODE (operands[3]))
1147 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
1149 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1155 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
1157 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1163 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
1165 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1171 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
1173 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1179 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
1181 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1187 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
1189 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1195 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
1197 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1203 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
1205 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1211 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
1213 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1219 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
1221 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1229 /* If the decrement is to be done in SImode, then we have
1230 to compensate for the fact that dbcc decrements in HImode. */
1231 switch (GET_MODE (operands[0]))
1235 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
1237 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
1250 output_scc_di(op, operand1, operand2, dest)
1257 enum rtx_code op_code = GET_CODE (op);
1259 /* This does not produce a useful cc. */
1262 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1263 below. Swap the operands and change the op if these requirements
1264 are not fulfilled. */
1265 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1269 operand1 = operand2;
1271 op_code = swap_condition (op_code);
1273 loperands[0] = operand1;
1274 if (GET_CODE (operand1) == REG)
1275 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1277 loperands[1] = adjust_address (operand1, SImode, 4);
1278 if (operand2 != const0_rtx)
1280 loperands[2] = operand2;
1281 if (GET_CODE (operand2) == REG)
1282 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1284 loperands[3] = adjust_address (operand2, SImode, 4);
1286 loperands[4] = gen_label_rtx();
1287 if (operand2 != const0_rtx)
1290 #ifdef SGS_CMP_ORDER
1291 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
1293 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
1296 #ifdef SGS_CMP_ORDER
1297 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
1299 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1305 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0]))
1306 output_asm_insn ("tst%.l %0", loperands);
1309 #ifdef SGS_CMP_ORDER
1310 output_asm_insn ("cmp%.w %0,%#0", loperands);
1312 output_asm_insn ("cmp%.w %#0,%0", loperands);
1317 output_asm_insn ("jbne %l4", loperands);
1319 output_asm_insn ("jne %l4", loperands);
1322 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1]))
1323 output_asm_insn ("tst%.l %1", loperands);
1326 #ifdef SGS_CMP_ORDER
1327 output_asm_insn ("cmp%.w %1,%#0", loperands);
1329 output_asm_insn ("cmp%.w %#0,%1", loperands);
1334 loperands[5] = dest;
1339 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1340 CODE_LABEL_NUMBER (loperands[4]));
1341 output_asm_insn ("seq %5", loperands);
1345 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1346 CODE_LABEL_NUMBER (loperands[4]));
1347 output_asm_insn ("sne %5", loperands);
1351 loperands[6] = gen_label_rtx();
1353 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1355 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1357 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1358 CODE_LABEL_NUMBER (loperands[4]));
1359 output_asm_insn ("sgt %5", loperands);
1360 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1361 CODE_LABEL_NUMBER (loperands[6]));
1365 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1366 CODE_LABEL_NUMBER (loperands[4]));
1367 output_asm_insn ("shi %5", loperands);
1371 loperands[6] = gen_label_rtx();
1373 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1375 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1377 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1378 CODE_LABEL_NUMBER (loperands[4]));
1379 output_asm_insn ("slt %5", loperands);
1380 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1381 CODE_LABEL_NUMBER (loperands[6]));
1385 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1386 CODE_LABEL_NUMBER (loperands[4]));
1387 output_asm_insn ("scs %5", loperands);
1391 loperands[6] = gen_label_rtx();
1393 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1395 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1397 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1398 CODE_LABEL_NUMBER (loperands[4]));
1399 output_asm_insn ("sge %5", loperands);
1400 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1401 CODE_LABEL_NUMBER (loperands[6]));
1405 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1406 CODE_LABEL_NUMBER (loperands[4]));
1407 output_asm_insn ("scc %5", loperands);
1411 loperands[6] = gen_label_rtx();
1413 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1415 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1417 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1418 CODE_LABEL_NUMBER (loperands[4]));
1419 output_asm_insn ("sle %5", loperands);
1420 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1421 CODE_LABEL_NUMBER (loperands[6]));
1425 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1426 CODE_LABEL_NUMBER (loperands[4]));
1427 output_asm_insn ("sls %5", loperands);
1437 output_btst (operands, countop, dataop, insn, signpos)
1439 rtx countop, dataop;
1443 operands[0] = countop;
1444 operands[1] = dataop;
1446 if (GET_CODE (countop) == CONST_INT)
1448 register int count = INTVAL (countop);
1449 /* If COUNT is bigger than size of storage unit in use,
1450 advance to the containing unit of same size. */
1451 if (count > signpos)
1453 int offset = (count & ~signpos) / 8;
1454 count = count & signpos;
1455 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1457 if (count == signpos)
1458 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1460 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1462 /* These three statements used to use next_insns_test_no...
1463 but it appears that this should do the same job. */
1465 && next_insn_tests_no_inequality (insn))
1468 && next_insn_tests_no_inequality (insn))
1471 && next_insn_tests_no_inequality (insn))
1474 cc_status.flags = CC_NOT_NEGATIVE;
1476 return "btst %0,%1";
1479 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1480 reference and a constant. */
1483 symbolic_operand (op, mode)
1485 enum machine_mode mode ATTRIBUTE_UNUSED;
1487 switch (GET_CODE (op))
1495 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1496 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1497 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1499 #if 0 /* Deleted, with corresponding change in m68k.h,
1500 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1502 return GET_MODE (op) == mode;
1510 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1513 extend_operator(x, mode)
1515 enum machine_mode mode;
1517 if (mode != VOIDmode && GET_MODE(x) != mode)
1519 switch (GET_CODE(x))
1530 /* Legitimize PIC addresses. If the address is already
1531 position-independent, we return ORIG. Newly generated
1532 position-independent addresses go to REG. If we need more
1533 than one register, we lose.
1535 An address is legitimized by making an indirect reference
1536 through the Global Offset Table with the name of the symbol
1539 The assembler and linker are responsible for placing the
1540 address of the symbol in the GOT. The function prologue
1541 is responsible for initializing a5 to the starting address
1544 The assembler is also responsible for translating a symbol name
1545 into a constant displacement from the start of the GOT.
1547 A quick example may make things a little clearer:
1549 When not generating PIC code to store the value 12345 into _foo
1550 we would generate the following code:
1554 When generating PIC two transformations are made. First, the compiler
1555 loads the address of foo into a register. So the first transformation makes:
1560 The code in movsi will intercept the lea instruction and call this
1561 routine which will transform the instructions into:
1563 movel a5@(_foo:w), a0
1567 That (in a nutshell) is how *all* symbol and label references are
1571 legitimize_pic_address (orig, mode, reg)
1573 enum machine_mode mode ATTRIBUTE_UNUSED;
1577 /* First handle a simple SYMBOL_REF or LABEL_REF */
1578 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1583 pic_ref = gen_rtx_MEM (Pmode,
1584 gen_rtx_PLUS (Pmode,
1585 pic_offset_table_rtx, orig));
1586 current_function_uses_pic_offset_table = 1;
1587 RTX_UNCHANGING_P (pic_ref) = 1;
1588 emit_move_insn (reg, pic_ref);
1591 else if (GET_CODE (orig) == CONST)
1595 /* Make sure this is CONST has not already been legitimized */
1596 if (GET_CODE (XEXP (orig, 0)) == PLUS
1597 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1603 /* legitimize both operands of the PLUS */
1604 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1606 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1607 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1608 base == reg ? 0 : reg);
1612 if (GET_CODE (orig) == CONST_INT)
1613 return plus_constant (base, INTVAL (orig));
1614 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1615 /* Likewise, should we set special REG_NOTEs here? */
1621 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1623 static CONST_METHOD const_method PARAMS ((rtx));
1625 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1628 const_method (constant)
1634 i = INTVAL (constant);
1638 /* The Coldfire doesn't have byte or word operations. */
1639 /* FIXME: This may not be useful for the m68060 either */
1642 /* if -256 < N < 256 but N is not in range for a moveq
1643 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1644 if (USE_MOVQ (i ^ 0xff))
1646 /* Likewise, try with not.w */
1647 if (USE_MOVQ (i ^ 0xffff))
1649 /* This is the only value where neg.w is useful */
1652 /* Try also with swap */
1654 if (USE_MOVQ ((u >> 16) | (u << 16)))
1657 /* Otherwise, use move.l */
1662 const_int_cost (constant)
1665 switch (const_method (constant))
1668 /* Constants between -128 and 127 are cheap due to moveq */
1674 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1684 output_move_const_into_data_reg (operands)
1689 i = INTVAL (operands[1]);
1690 switch (const_method (operands[1]))
1693 #if defined (MOTOROLA) && !defined (CRDS)
1694 return "moveq%.l %1,%0";
1696 return "moveq %1,%0";
1699 operands[1] = GEN_INT (i ^ 0xff);
1700 #if defined (MOTOROLA) && !defined (CRDS)
1701 return "moveq%.l %1,%0\n\tnot%.b %0";
1703 return "moveq %1,%0\n\tnot%.b %0";
1706 operands[1] = GEN_INT (i ^ 0xffff);
1707 #if defined (MOTOROLA) && !defined (CRDS)
1708 return "moveq%.l %1,%0\n\tnot%.w %0";
1710 return "moveq %1,%0\n\tnot%.w %0";
1713 #if defined (MOTOROLA) && !defined (CRDS)
1714 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1716 return "moveq %#-128,%0\n\tneg%.w %0";
1722 operands[1] = GEN_INT ((u << 16) | (u >> 16));
1723 #if defined (MOTOROLA) && !defined (CRDS)
1724 return "moveq%.l %1,%0\n\tswap %0";
1726 return "moveq %1,%0\n\tswap %0";
1730 return "move%.l %1,%0";
1737 output_move_simode_const (operands)
1740 if (operands[1] == const0_rtx
1741 && (DATA_REG_P (operands[0])
1742 || GET_CODE (operands[0]) == MEM)
1743 /* clr insns on 68000 read before writing.
1744 This isn't so on the 68010, but we have no TARGET_68010. */
1745 && ((TARGET_68020 || TARGET_5200)
1746 || !(GET_CODE (operands[0]) == MEM
1747 && MEM_VOLATILE_P (operands[0]))))
1749 else if (operands[1] == const0_rtx
1750 && ADDRESS_REG_P (operands[0]))
1751 return "sub%.l %0,%0";
1752 else if (DATA_REG_P (operands[0]))
1753 return output_move_const_into_data_reg (operands);
1754 else if (ADDRESS_REG_P (operands[0])
1755 && INTVAL (operands[1]) < 0x8000
1756 && INTVAL (operands[1]) >= -0x8000)
1757 return "move%.w %1,%0";
1758 else if (GET_CODE (operands[0]) == MEM
1759 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1760 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1761 && INTVAL (operands[1]) < 0x8000
1762 && INTVAL (operands[1]) >= -0x8000)
1764 return "move%.l %1,%0";
1768 output_move_simode (operands)
1771 if (GET_CODE (operands[1]) == CONST_INT)
1772 return output_move_simode_const (operands);
1773 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1774 || GET_CODE (operands[1]) == CONST)
1775 && push_operand (operands[0], SImode))
1777 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1778 || GET_CODE (operands[1]) == CONST)
1779 && ADDRESS_REG_P (operands[0]))
1780 return "lea %a1,%0";
1781 return "move%.l %1,%0";
1785 output_move_himode (operands)
1788 if (GET_CODE (operands[1]) == CONST_INT)
1790 if (operands[1] == const0_rtx
1791 && (DATA_REG_P (operands[0])
1792 || GET_CODE (operands[0]) == MEM)
1793 /* clr insns on 68000 read before writing.
1794 This isn't so on the 68010, but we have no TARGET_68010. */
1795 && ((TARGET_68020 || TARGET_5200)
1796 || !(GET_CODE (operands[0]) == MEM
1797 && MEM_VOLATILE_P (operands[0]))))
1799 else if (operands[1] == const0_rtx
1800 && ADDRESS_REG_P (operands[0]))
1801 return "sub%.l %0,%0";
1802 else if (DATA_REG_P (operands[0])
1803 && INTVAL (operands[1]) < 128
1804 && INTVAL (operands[1]) >= -128)
1806 #if defined(MOTOROLA) && !defined(CRDS)
1807 return "moveq%.l %1,%0";
1809 return "moveq %1,%0";
1812 else if (INTVAL (operands[1]) < 0x8000
1813 && INTVAL (operands[1]) >= -0x8000)
1814 return "move%.w %1,%0";
1816 else if (CONSTANT_P (operands[1]))
1817 return "move%.l %1,%0";
1819 /* Recognize the insn before a tablejump, one that refers
1820 to a table of offsets. Such an insn will need to refer
1821 to a label on the insn. So output one. Use the label-number
1822 of the table of offsets to generate this label. This code,
1823 and similar code below, assumes that there will be at most one
1824 reference to each table. */
1825 if (GET_CODE (operands[1]) == MEM
1826 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1827 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1828 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1830 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1831 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1833 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1834 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1836 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1837 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1838 #endif /* not SGS */
1839 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1840 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "LI",
1841 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1842 #ifdef SGS_SWITCH_TABLES
1843 /* Set flag saying we need to define the symbol
1844 LD%n (with value L%n-LI%n) at the end of the switch table. */
1845 switch_table_difference_label_flag = 1;
1846 #endif /* SGS_SWITCH_TABLES */
1847 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1849 #endif /* SGS_NO_LI */
1850 return "move%.w %1,%0";
1854 output_move_qimode (operands)
1859 /* This is probably useless, since it loses for pushing a struct
1860 of several bytes a byte at a time. */
1861 /* 68k family always modifies the stack pointer by at least 2, even for
1862 byte pushes. The 5200 (coldfire) does not do this. */
1863 if (GET_CODE (operands[0]) == MEM
1864 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1865 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1866 && ! ADDRESS_REG_P (operands[1])
1869 xoperands[1] = operands[1];
1871 = gen_rtx_MEM (QImode,
1872 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
1873 /* Just pushing a byte puts it in the high byte of the halfword. */
1874 /* We must put it in the low-order, high-numbered byte. */
1875 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1877 xoperands[3] = stack_pointer_rtx;
1879 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1881 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1885 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
1889 /* clr and st insns on 68000 read before writing.
1890 This isn't so on the 68010, but we have no TARGET_68010. */
1891 if (!ADDRESS_REG_P (operands[0])
1892 && ((TARGET_68020 || TARGET_5200)
1893 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1895 if (operands[1] == const0_rtx)
1897 if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1898 && GET_CODE (operands[1]) == CONST_INT
1899 && (INTVAL (operands[1]) & 255) == 255)
1905 if (GET_CODE (operands[1]) == CONST_INT
1906 && DATA_REG_P (operands[0])
1907 && INTVAL (operands[1]) < 128
1908 && INTVAL (operands[1]) >= -128)
1910 #if defined(MOTOROLA) && !defined(CRDS)
1911 return "moveq%.l %1,%0";
1913 return "moveq %1,%0";
1916 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
1917 return "sub%.l %0,%0";
1918 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1919 return "move%.l %1,%0";
1920 /* 68k family (including the 5200 coldfire) does not support byte moves to
1921 from address registers. */
1922 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1923 return "move%.w %1,%0";
1924 return "move%.b %1,%0";
1928 output_move_stricthi (operands)
1931 if (operands[1] == const0_rtx
1932 /* clr insns on 68000 read before writing.
1933 This isn't so on the 68010, but we have no TARGET_68010. */
1934 && ((TARGET_68020 || TARGET_5200)
1935 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1937 return "move%.w %1,%0";
1941 output_move_strictqi (operands)
1944 if (operands[1] == const0_rtx
1945 /* clr insns on 68000 read before writing.
1946 This isn't so on the 68010, but we have no TARGET_68010. */
1947 && ((TARGET_68020 || TARGET_5200)
1948 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1950 return "move%.b %1,%0";
1953 /* Return the best assembler insn template
1954 for moving operands[1] into operands[0] as a fullword. */
1957 singlemove_string (operands)
1960 #ifdef SUPPORT_SUN_FPA
1961 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1962 return "fpmoves %1,%0";
1964 if (GET_CODE (operands[1]) == CONST_INT)
1965 return output_move_simode_const (operands);
1966 return "move%.l %1,%0";
1970 /* Output assembler code to perform a doubleword move insn
1971 with operands OPERANDS. */
1974 output_move_double (operands)
1979 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1984 rtx addreg0 = 0, addreg1 = 0;
1985 int dest_overlapped_low = 0;
1986 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1991 /* First classify both operands. */
1993 if (REG_P (operands[0]))
1995 else if (offsettable_memref_p (operands[0]))
1997 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1999 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2001 else if (GET_CODE (operands[0]) == MEM)
2006 if (REG_P (operands[1]))
2008 else if (CONSTANT_P (operands[1]))
2010 else if (offsettable_memref_p (operands[1]))
2012 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2014 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2016 else if (GET_CODE (operands[1]) == MEM)
2021 /* Check for the cases that the operand constraints are not
2022 supposed to allow to happen. Abort if we get one,
2023 because generating code for these cases is painful. */
2025 if (optype0 == RNDOP || optype1 == RNDOP)
2028 /* If one operand is decrementing and one is incrementing
2029 decrement the former register explicitly
2030 and change that operand into ordinary indexing. */
2032 if (optype0 == PUSHOP && optype1 == POPOP)
2034 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2036 output_asm_insn ("sub%.l %#12,%0", operands);
2038 output_asm_insn ("subq%.l %#8,%0", operands);
2039 if (GET_MODE (operands[1]) == XFmode)
2040 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2041 else if (GET_MODE (operands[0]) == DFmode)
2042 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2044 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2047 if (optype0 == POPOP && optype1 == PUSHOP)
2049 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2051 output_asm_insn ("sub%.l %#12,%1", operands);
2053 output_asm_insn ("subq%.l %#8,%1", operands);
2054 if (GET_MODE (operands[1]) == XFmode)
2055 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2056 else if (GET_MODE (operands[1]) == DFmode)
2057 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2059 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2063 /* If an operand is an unoffsettable memory ref, find a register
2064 we can increment temporarily to make it refer to the second word. */
2066 if (optype0 == MEMOP)
2067 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2069 if (optype1 == MEMOP)
2070 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2072 /* Ok, we can do one word at a time.
2073 Normally we do the low-numbered word first,
2074 but if either operand is autodecrementing then we
2075 do the high-numbered word first.
2077 In either case, set up in LATEHALF the operands to use
2078 for the high-numbered word and in some cases alter the
2079 operands in OPERANDS to be suitable for the low-numbered word. */
2083 if (optype0 == REGOP)
2085 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2086 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2088 else if (optype0 == OFFSOP)
2090 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2091 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2095 middlehalf[0] = operands[0];
2096 latehalf[0] = operands[0];
2099 if (optype1 == REGOP)
2101 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2102 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2104 else if (optype1 == OFFSOP)
2106 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2107 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2109 else if (optype1 == CNSTOP)
2111 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2116 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2117 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2118 operands[1] = GEN_INT (l[0]);
2119 middlehalf[1] = GEN_INT (l[1]);
2120 latehalf[1] = GEN_INT (l[2]);
2122 else if (CONSTANT_P (operands[1]))
2124 /* actually, no non-CONST_DOUBLE constant should ever
2127 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
2128 latehalf[1] = constm1_rtx;
2130 latehalf[1] = const0_rtx;
2135 middlehalf[1] = operands[1];
2136 latehalf[1] = operands[1];
2140 /* size is not 12: */
2142 if (optype0 == REGOP)
2143 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2144 else if (optype0 == OFFSOP)
2145 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2147 latehalf[0] = operands[0];
2149 if (optype1 == REGOP)
2150 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2151 else if (optype1 == OFFSOP)
2152 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2153 else if (optype1 == CNSTOP)
2154 split_double (operands[1], &operands[1], &latehalf[1]);
2156 latehalf[1] = operands[1];
2159 /* If insn is effectively movd N(sp),-(sp) then we will do the
2160 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2161 for the low word as well, to compensate for the first decrement of sp. */
2162 if (optype0 == PUSHOP
2163 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2164 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2165 operands[1] = middlehalf[1] = latehalf[1];
2167 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2168 if the upper part of reg N does not appear in the MEM, arrange to
2169 emit the move late-half first. Otherwise, compute the MEM address
2170 into the upper part of N and use that as a pointer to the memory
2172 if (optype0 == REGOP
2173 && (optype1 == OFFSOP || optype1 == MEMOP))
2175 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2177 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2178 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2180 /* If both halves of dest are used in the src memory address,
2181 compute the address into latehalf of dest.
2182 Note that this can't happen if the dest is two data regs. */
2184 xops[0] = latehalf[0];
2185 xops[1] = XEXP (operands[1], 0);
2186 output_asm_insn ("lea %a1,%0", xops);
2187 if (GET_MODE (operands[1]) == XFmode )
2189 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2190 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2191 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2195 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2196 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2200 && reg_overlap_mentioned_p (middlehalf[0],
2201 XEXP (operands[1], 0)))
2203 /* Check for two regs used by both source and dest.
2204 Note that this can't happen if the dest is all data regs.
2205 It can happen if the dest is d6, d7, a0.
2206 But in that case, latehalf is an addr reg, so
2207 the code at compadr does ok. */
2209 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2210 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2213 /* JRV says this can't happen: */
2214 if (addreg0 || addreg1)
2217 /* Only the middle reg conflicts; simply put it last. */
2218 output_asm_insn (singlemove_string (operands), operands);
2219 output_asm_insn (singlemove_string (latehalf), latehalf);
2220 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2223 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2224 /* If the low half of dest is mentioned in the source memory
2225 address, the arrange to emit the move late half first. */
2226 dest_overlapped_low = 1;
2229 /* If one or both operands autodecrementing,
2230 do the two words, high-numbered first. */
2232 /* Likewise, the first move would clobber the source of the second one,
2233 do them in the other order. This happens only for registers;
2234 such overlap can't happen in memory unless the user explicitly
2235 sets it up, and that is an undefined circumstance. */
2237 if (optype0 == PUSHOP || optype1 == PUSHOP
2238 || (optype0 == REGOP && optype1 == REGOP
2239 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2240 || REGNO (operands[0]) == REGNO (latehalf[1])))
2241 || dest_overlapped_low)
2243 /* Make any unoffsettable addresses point at high-numbered word. */
2247 output_asm_insn ("addq%.l %#8,%0", &addreg0);
2249 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2254 output_asm_insn ("addq%.l %#8,%0", &addreg1);
2256 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2260 output_asm_insn (singlemove_string (latehalf), latehalf);
2262 /* Undo the adds we just did. */
2264 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2266 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2270 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2272 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2274 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2277 /* Do low-numbered word. */
2278 return singlemove_string (operands);
2281 /* Normal case: do the two words, low-numbered first. */
2283 output_asm_insn (singlemove_string (operands), operands);
2285 /* Do the middle one of the three words for long double */
2289 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2291 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2293 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2296 /* Make any unoffsettable addresses point at high-numbered word. */
2298 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2300 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2303 output_asm_insn (singlemove_string (latehalf), latehalf);
2305 /* Undo the adds we just did. */
2309 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2311 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2316 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2318 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2324 /* Return a REG that occurs in ADDR with coefficient 1.
2325 ADDR can be effectively incremented by incrementing REG. */
2328 find_addr_reg (addr)
2331 while (GET_CODE (addr) == PLUS)
2333 if (GET_CODE (XEXP (addr, 0)) == REG)
2334 addr = XEXP (addr, 0);
2335 else if (GET_CODE (XEXP (addr, 1)) == REG)
2336 addr = XEXP (addr, 1);
2337 else if (CONSTANT_P (XEXP (addr, 0)))
2338 addr = XEXP (addr, 1);
2339 else if (CONSTANT_P (XEXP (addr, 1)))
2340 addr = XEXP (addr, 0);
2344 if (GET_CODE (addr) == REG)
2349 /* Output assembler code to perform a 32 bit 3 operand add. */
2352 output_addsi3 (operands)
2355 if (! operands_match_p (operands[0], operands[1]))
2357 if (!ADDRESS_REG_P (operands[1]))
2359 rtx tmp = operands[1];
2361 operands[1] = operands[2];
2365 /* These insns can result from reloads to access
2366 stack slots over 64k from the frame pointer. */
2367 if (GET_CODE (operands[2]) == CONST_INT
2368 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2369 return "move%.l %2,%0\n\tadd%.l %1,%0";
2371 if (GET_CODE (operands[2]) == REG)
2372 return "lea 0(%1,%2.l),%0";
2374 return "lea %c2(%1),%0";
2377 if (GET_CODE (operands[2]) == REG)
2378 return "lea (%1,%2.l),%0";
2380 return "lea (%c2,%1),%0";
2381 #else /* not MOTOROLA (MIT syntax) */
2382 if (GET_CODE (operands[2]) == REG)
2383 return "lea %1@(0,%2:l),%0";
2385 return "lea %1@(%c2),%0";
2386 #endif /* not MOTOROLA */
2387 #endif /* not SGS */
2389 if (GET_CODE (operands[2]) == CONST_INT)
2392 if (INTVAL (operands[2]) > 0
2393 && INTVAL (operands[2]) <= 8)
2394 return "addq%.l %2,%0";
2395 if (INTVAL (operands[2]) < 0
2396 && INTVAL (operands[2]) >= -8)
2398 operands[2] = GEN_INT (- INTVAL (operands[2]));
2399 return "subq%.l %2,%0";
2401 /* On the CPU32 it is faster to use two addql instructions to
2402 add a small integer (8 < N <= 16) to a register.
2403 Likewise for subql. */
2404 if (TARGET_CPU32 && REG_P (operands[0]))
2406 if (INTVAL (operands[2]) > 8
2407 && INTVAL (operands[2]) <= 16)
2409 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2410 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2412 if (INTVAL (operands[2]) < -8
2413 && INTVAL (operands[2]) >= -16)
2415 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2416 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2420 if (ADDRESS_REG_P (operands[0])
2421 && INTVAL (operands[2]) >= -0x8000
2422 && INTVAL (operands[2]) < 0x8000)
2425 return "add%.w %2,%0";
2428 return "lea (%c2,%0),%0";
2430 return "lea %0@(%c2),%0";
2434 return "add%.l %2,%0";
2437 /* Store in cc_status the expressions that the condition codes will
2438 describe after execution of an instruction whose pattern is EXP.
2439 Do not alter them if the instruction would not alter the cc's. */
2441 /* On the 68000, all the insns to store in an address register fail to
2442 set the cc's. However, in some cases these instructions can make it
2443 possibly invalid to use the saved cc's. In those cases we clear out
2444 some or all of the saved cc's so they won't be used. */
2447 notice_update_cc (exp, insn)
2451 /* If the cc is being set from the fpa and the expression is not an
2452 explicit floating point test instruction (which has code to deal with
2453 this), reinit the CC. */
2454 if (((cc_status.value1 && FPA_REG_P (cc_status.value1))
2455 || (cc_status.value2 && FPA_REG_P (cc_status.value2)))
2456 && !(GET_CODE (exp) == PARALLEL
2457 && GET_CODE (XVECEXP (exp, 0, 0)) == SET
2458 && XEXP (XVECEXP (exp, 0, 0), 0) == cc0_rtx))
2462 else if (GET_CODE (exp) == SET)
2464 if (GET_CODE (SET_SRC (exp)) == CALL)
2468 else if (ADDRESS_REG_P (SET_DEST (exp)))
2470 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
2471 cc_status.value1 = 0;
2472 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
2473 cc_status.value2 = 0;
2475 else if (!FP_REG_P (SET_DEST (exp))
2476 && SET_DEST (exp) != cc0_rtx
2477 && (FP_REG_P (SET_SRC (exp))
2478 || GET_CODE (SET_SRC (exp)) == FIX
2479 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2480 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2484 /* A pair of move insns doesn't produce a useful overall cc. */
2485 else if (!FP_REG_P (SET_DEST (exp))
2486 && !FP_REG_P (SET_SRC (exp))
2487 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2488 && (GET_CODE (SET_SRC (exp)) == REG
2489 || GET_CODE (SET_SRC (exp)) == MEM
2490 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2494 else if (GET_CODE (SET_SRC (exp)) == CALL)
2498 else if (XEXP (exp, 0) != pc_rtx)
2500 cc_status.flags = 0;
2501 cc_status.value1 = XEXP (exp, 0);
2502 cc_status.value2 = XEXP (exp, 1);
2505 else if (GET_CODE (exp) == PARALLEL
2506 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2508 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2510 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2512 cc_status.flags = 0;
2513 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2514 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2519 if (cc_status.value2 != 0
2520 && ADDRESS_REG_P (cc_status.value2)
2521 && GET_MODE (cc_status.value2) == QImode)
2523 if (cc_status.value2 != 0
2524 && !(cc_status.value1 && FPA_REG_P (cc_status.value1)))
2525 switch (GET_CODE (cc_status.value2))
2527 case PLUS: case MINUS: case MULT:
2528 case DIV: case UDIV: case MOD: case UMOD: case NEG:
2529 #if 0 /* These instructions always clear the overflow bit */
2530 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
2531 case ROTATE: case ROTATERT:
2533 if (GET_MODE (cc_status.value2) != VOIDmode)
2534 cc_status.flags |= CC_NO_OVERFLOW;
2537 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2538 ends with a move insn moving r2 in r2's mode.
2539 Thus, the cc's are set for r2.
2540 This can set N bit spuriously. */
2541 cc_status.flags |= CC_NOT_NEGATIVE;
2546 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2548 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2549 cc_status.value2 = 0;
2550 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2551 || (cc_status.value2 && FP_REG_P (cc_status.value2)))
2552 && !((cc_status.value1 && FPA_REG_P (cc_status.value1))
2553 || (cc_status.value2 && FPA_REG_P (cc_status.value2))))
2554 cc_status.flags = CC_IN_68881;
2558 output_move_const_double (operands)
2561 #ifdef SUPPORT_SUN_FPA
2562 if (TARGET_FPA && FPA_REG_P (operands[0]))
2564 int code = standard_sun_fpa_constant_p (operands[1]);
2568 static char buf[40];
2570 sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
2573 return "fpmove%.d %1,%0";
2578 int code = standard_68881_constant_p (operands[1]);
2582 static char buf[40];
2584 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2587 return "fmove%.d %1,%0";
2592 output_move_const_single (operands)
2595 #ifdef SUPPORT_SUN_FPA
2598 int code = standard_sun_fpa_constant_p (operands[1]);
2602 static char buf[40];
2604 sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
2607 return "fpmove%.s %1,%0";
2610 #endif /* defined SUPPORT_SUN_FPA */
2612 int code = standard_68881_constant_p (operands[1]);
2616 static char buf[40];
2618 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2621 return "fmove%.s %f1,%0";
2625 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2626 from the "fmovecr" instruction.
2627 The value, anded with 0xff, gives the code to use in fmovecr
2628 to get the desired constant. */
2630 /* This code has been fixed for cross-compilation. */
2632 static int inited_68881_table = 0;
2634 static const char *const strings_68881[7] = {
2644 static const int codes_68881[7] = {
2654 REAL_VALUE_TYPE values_68881[7];
2656 /* Set up values_68881 array by converting the decimal values
2657 strings_68881 to binary. */
2664 enum machine_mode mode;
2667 for (i = 0; i < 7; i++)
2671 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2672 values_68881[i] = r;
2674 inited_68881_table = 1;
2678 standard_68881_constant_p (x)
2684 #ifdef NO_ASM_FMOVECR
2688 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2689 used at all on those chips. */
2690 if (TARGET_68040 || TARGET_68060)
2693 if (! inited_68881_table)
2694 init_68881_table ();
2696 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2698 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2700 for (i = 0; i < 6; i++)
2702 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
2703 return (codes_68881[i]);
2706 if (GET_MODE (x) == SFmode)
2709 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2710 return (codes_68881[6]);
2712 /* larger powers of ten in the constants ram are not used
2713 because they are not equal to a `double' C constant. */
2717 /* If X is a floating-point constant, return the logarithm of X base 2,
2718 or 0 if X is not a power of 2. */
2721 floating_exact_log2 (x)
2724 REAL_VALUE_TYPE r, r1;
2727 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2729 if (REAL_VALUES_LESS (r, dconst1))
2732 exp = real_exponent (&r);
2733 real_2expN (&r1, exp);
2734 if (REAL_VALUES_EQUAL (r1, r))
2740 #ifdef SUPPORT_SUN_FPA
2741 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2742 from the Sun FPA's constant RAM.
2743 The value returned, anded with 0x1ff, gives the code to use in fpmove
2744 to get the desired constant. */
2746 static int inited_FPA_table = 0;
2748 static const char *const strings_FPA[38] = {
2749 /* small rationals */
2762 /* Decimal equivalents of double precision values */
2763 "2.718281828459045091", /* D_E */
2764 "6.283185307179586477", /* 2 pi */
2765 "3.141592653589793116", /* D_PI */
2766 "1.570796326794896619", /* pi/2 */
2767 "1.414213562373095145", /* D_SQRT2 */
2768 "0.7071067811865475244", /* 1/sqrt(2) */
2769 "-1.570796326794896619", /* -pi/2 */
2770 "1.442695040888963387", /* D_LOG2ofE */
2771 "3.321928024887362182", /* D_LOG2of10 */
2772 "0.6931471805599452862", /* D_LOGEof2 */
2773 "2.302585092994045901", /* D_LOGEof10 */
2774 "0.3010299956639811980", /* D_LOG10of2 */
2775 "0.4342944819032518167", /* D_LOG10ofE */
2776 /* Decimal equivalents of single precision values */
2777 "2.718281745910644531", /* S_E */
2778 "6.283185307179586477", /* 2 pi */
2779 "3.141592741012573242", /* S_PI */
2780 "1.570796326794896619", /* pi/2 */
2781 "1.414213538169860840", /* S_SQRT2 */
2782 "0.7071067811865475244", /* 1/sqrt(2) */
2783 "-1.570796326794896619", /* -pi/2 */
2784 "1.442695021629333496", /* S_LOG2ofE */
2785 "3.321928024291992188", /* S_LOG2of10 */
2786 "0.6931471824645996094", /* S_LOGEof2 */
2787 "2.302585124969482442", /* S_LOGEof10 */
2788 "0.3010300099849700928", /* S_LOG10of2 */
2789 "0.4342944920063018799", /* S_LOG10ofE */
2793 static const int codes_FPA[38] = {
2794 /* small rationals */
2807 /* double precision */
2821 /* single precision */
2837 REAL_VALUE_TYPE values_FPA[38];
2839 /* This code has been fixed for cross-compilation. */
2841 static void init_FPA_table PARAMS ((void));
2845 enum machine_mode mode;
2850 for (i = 0; i < 38; i++)
2854 r = REAL_VALUE_ATOF (strings_FPA[i], mode);
2857 inited_FPA_table = 1;
2862 standard_sun_fpa_constant_p (x)
2868 if (! inited_FPA_table)
2871 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2873 for (i=0; i<12; i++)
2875 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2876 return (codes_FPA[i]);
2879 if (GET_MODE (x) == SFmode)
2881 for (i=25; i<38; i++)
2883 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2884 return (codes_FPA[i]);
2889 for (i=12; i<25; i++)
2891 if (REAL_VALUES_EQUAL (r, values_FPA[i]))
2892 return (codes_FPA[i]);
2897 #endif /* define SUPPORT_SUN_FPA */
2899 /* A C compound statement to output to stdio stream STREAM the
2900 assembler syntax for an instruction operand X. X is an RTL
2903 CODE is a value that can be used to specify one of several ways
2904 of printing the operand. It is used when identical operands
2905 must be printed differently depending on the context. CODE
2906 comes from the `%' specification that was used to request
2907 printing of the operand. If the specification was just `%DIGIT'
2908 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2909 is the ASCII code for LTR.
2911 If X is a register, this macro should print the register's name.
2912 The names can be found in an array `reg_names' whose type is
2913 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2915 When the machine description has a specification `%PUNCT' (a `%'
2916 followed by a punctuation character), this macro is called with
2917 a null pointer for X and the punctuation character for CODE.
2919 The m68k specific codes are:
2921 '.' for dot needed in Motorola-style opcode names.
2922 '-' for an operand pushing on the stack:
2923 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2924 '+' for an operand pushing on the stack:
2925 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2926 '@' for a reference to the top word on the stack:
2927 sp@, (sp) or (%sp) depending on the style of syntax.
2928 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2929 but & in SGS syntax, $ in CRDS/UNOS syntax).
2930 '!' for the cc register (used in an `and to cc' insn).
2931 '$' for the letter `s' in an op code, but only on the 68040.
2932 '&' for the letter `d' in an op code, but only on the 68040.
2933 '/' for register prefix needed by longlong.h.
2935 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2936 'd' to force memory addressing to be absolute, not relative.
2937 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2938 'o' for operands to go directly to output_operand_address (bypassing
2939 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2940 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2941 than directly). Second part of 'y' below.
2942 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2943 or print pair of registers as rx:ry.
2944 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2945 CONST_DOUBLE's as SunFPA constant RAM registers if
2946 possible, so it should not be used except for the SunFPA.
2951 print_operand (file, op, letter)
2952 FILE *file; /* file to write to */
2953 rtx op; /* operand to print */
2954 int letter; /* %<letter> or 0 */
2956 #ifdef SUPPORT_SUN_FPA
2962 #if defined (MOTOROLA) && !defined (CRDS)
2963 fprintf (file, ".");
2966 else if (letter == '#')
2968 asm_fprintf (file, "%0I");
2970 else if (letter == '-')
2973 asm_fprintf (file, "-(%Rsp)");
2975 asm_fprintf (file, "%Rsp@-");
2978 else if (letter == '+')
2981 asm_fprintf (file, "(%Rsp)+");
2983 asm_fprintf (file, "%Rsp@+");
2986 else if (letter == '@')
2989 asm_fprintf (file, "(%Rsp)");
2991 asm_fprintf (file, "%Rsp@");
2994 else if (letter == '!')
2996 asm_fprintf (file, "%Rfpcr");
2998 else if (letter == '$')
3000 if (TARGET_68040_ONLY)
3002 fprintf (file, "s");
3005 else if (letter == '&')
3007 if (TARGET_68040_ONLY)
3009 fprintf (file, "d");
3012 else if (letter == '/')
3014 asm_fprintf (file, "%R");
3016 else if (letter == 'o')
3018 /* This is only for direct addresses with TARGET_PCREL */
3019 if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
3022 output_addr_const (file, XEXP (op, 0));
3024 else if (GET_CODE (op) == REG)
3026 #ifdef SUPPORT_SUN_FPA
3028 && (letter == 'y' || letter == 'x')
3029 && GET_MODE (op) == DFmode)
3031 fprintf (file, "%s:%s", reg_names[REGNO (op)],
3032 reg_names[REGNO (op)+1]);
3038 /* Print out the second register name of a register pair.
3039 I.e., R (6) => 7. */
3040 fputs (reg_names[REGNO (op) + 1], file);
3042 fputs (reg_names[REGNO (op)], file);
3045 else if (GET_CODE (op) == MEM)
3047 output_address (XEXP (op, 0));
3048 if (letter == 'd' && ! TARGET_68020
3049 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3050 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3051 && INTVAL (XEXP (op, 0)) < 0x8000
3052 && INTVAL (XEXP (op, 0)) >= -0x8000))
3055 fprintf (file, ".l");
3057 fprintf (file, ":l");
3061 #ifdef SUPPORT_SUN_FPA
3062 else if ((letter == 'y' || letter == 'w')
3063 && GET_CODE (op) == CONST_DOUBLE
3064 && (i = standard_sun_fpa_constant_p (op)))
3066 fprintf (file, "%%%d", i & 0x1ff);
3069 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3072 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3073 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3075 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3078 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3079 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3081 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3084 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3085 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3089 /* Use `print_operand_address' instead of `output_addr_const'
3090 to ensure that we print relevant PIC stuff. */
3091 asm_fprintf (file, "%0I");
3093 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3094 print_operand_address (file, op);
3096 output_addr_const (file, op);
3101 /* A C compound statement to output to stdio stream STREAM the
3102 assembler syntax for an instruction operand that is a memory
3103 reference whose address is ADDR. ADDR is an RTL expression.
3105 Note that this contains a kludge that knows that the only reason
3106 we have an address (plus (label_ref...) (reg...)) when not generating
3107 PIC code is in the insn before a tablejump, and we know that m68k.md
3108 generates a label LInnn: on such an insn.
3110 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3111 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3113 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3114 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3115 we want. This difference can be accommodated by using an assembler
3116 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3117 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3118 macro. See m68k/sgs.h for an example; for versions without the bug.
3119 Some assemblers refuse all the above solutions. The workaround is to
3120 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3123 They also do not like things like "pea 1.w", so we simple leave off
3124 the .w on small constants.
3126 This routine is responsible for distinguishing between -fpic and -fPIC
3127 style relocations in an address. When generating -fpic code the
3128 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
3129 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
3131 #ifndef ASM_OUTPUT_CASE_FETCH
3134 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3135 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
3137 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3138 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
3141 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
3142 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
3144 #endif /* ASM_OUTPUT_CASE_FETCH */
3147 print_operand_address (file, addr)
3151 register rtx reg1, reg2, breg, ireg;
3154 switch (GET_CODE (addr))
3158 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
3160 fprintf (file, "%s@", reg_names[REGNO (addr)]);
3165 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
3167 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
3172 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
3174 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
3178 reg1 = reg2 = ireg = breg = offset = 0;
3179 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
3181 offset = XEXP (addr, 0);
3182 addr = XEXP (addr, 1);
3184 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
3186 offset = XEXP (addr, 1);
3187 addr = XEXP (addr, 0);
3189 if (GET_CODE (addr) != PLUS)
3193 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
3195 reg1 = XEXP (addr, 0);
3196 addr = XEXP (addr, 1);
3198 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
3200 reg1 = XEXP (addr, 1);
3201 addr = XEXP (addr, 0);
3203 else if (GET_CODE (XEXP (addr, 0)) == MULT)
3205 reg1 = XEXP (addr, 0);
3206 addr = XEXP (addr, 1);
3208 else if (GET_CODE (XEXP (addr, 1)) == MULT)
3210 reg1 = XEXP (addr, 1);
3211 addr = XEXP (addr, 0);
3213 else if (GET_CODE (XEXP (addr, 0)) == REG)
3215 reg1 = XEXP (addr, 0);
3216 addr = XEXP (addr, 1);
3218 else if (GET_CODE (XEXP (addr, 1)) == REG)
3220 reg1 = XEXP (addr, 1);
3221 addr = XEXP (addr, 0);
3223 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
3224 || GET_CODE (addr) == SIGN_EXTEND)
3236 #if 0 /* for OLD_INDEXING */
3237 else if (GET_CODE (addr) == PLUS)
3239 if (GET_CODE (XEXP (addr, 0)) == REG)
3241 reg2 = XEXP (addr, 0);
3242 addr = XEXP (addr, 1);
3244 else if (GET_CODE (XEXP (addr, 1)) == REG)
3246 reg2 = XEXP (addr, 1);
3247 addr = XEXP (addr, 0);
3259 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
3260 || GET_CODE (reg1) == MULT))
3261 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
3266 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
3271 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
3272 && ! (flag_pic && ireg == pic_offset_table_rtx))
3275 if (GET_CODE (ireg) == MULT)
3277 scale = INTVAL (XEXP (ireg, 1));
3278 ireg = XEXP (ireg, 0);
3280 if (GET_CODE (ireg) == SIGN_EXTEND)
3282 ASM_OUTPUT_CASE_FETCH (file,
3283 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3284 reg_names[REGNO (XEXP (ireg, 0))]);
3285 fprintf (file, "w");
3289 ASM_OUTPUT_CASE_FETCH (file,
3290 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3291 reg_names[REGNO (ireg)]);
3292 fprintf (file, "l");
3297 fprintf (file, "*%d", scale);
3299 fprintf (file, ":%d", scale);
3305 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
3306 && ! (flag_pic && breg == pic_offset_table_rtx))
3308 ASM_OUTPUT_CASE_FETCH (file,
3309 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3310 reg_names[REGNO (breg)]);
3311 fprintf (file, "l)");
3314 if (ireg != 0 || breg != 0)
3321 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
3328 output_addr_const (file, addr);
3329 if (flag_pic && (breg == pic_offset_table_rtx))
3331 fprintf (file, "@GOT");
3333 fprintf (file, ".w");
3336 fprintf (file, "(%s", reg_names[REGNO (breg)]);
3342 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
3345 output_addr_const (file, addr);
3346 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
3347 fprintf (file, ":w");
3348 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
3349 fprintf (file, ":l");
3351 if (addr != 0 && ireg != 0)
3356 if (ireg != 0 && GET_CODE (ireg) == MULT)
3358 scale = INTVAL (XEXP (ireg, 1));
3359 ireg = XEXP (ireg, 0);
3361 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
3364 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
3366 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
3372 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3374 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3380 fprintf (file, "*%d", scale);
3382 fprintf (file, ":%d", scale);
3388 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
3389 && ! (flag_pic && reg1 == pic_offset_table_rtx))
3391 ASM_OUTPUT_CASE_FETCH (file,
3392 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3393 reg_names[REGNO (reg1)]);
3394 fprintf (file, "l)");
3397 /* FALL-THROUGH (is this really what we want?) */
3399 if (GET_CODE (addr) == CONST_INT
3400 && INTVAL (addr) < 0x8000
3401 && INTVAL (addr) >= -0x8000)
3405 /* Many SGS assemblers croak on size specifiers for constants. */
3406 fprintf (file, "%d", (int) INTVAL (addr));
3408 fprintf (file, "%d.w", (int) INTVAL (addr));
3411 fprintf (file, "%d:w", (int) INTVAL (addr));
3414 else if (GET_CODE (addr) == CONST_INT)
3416 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3418 else if (TARGET_PCREL)
3421 output_addr_const (file, addr);
3423 asm_fprintf (file, ":w,%Rpc)");
3425 asm_fprintf (file, ":l,%Rpc)");
3429 /* Special case for SYMBOL_REF if the symbol name ends in
3430 `.<letter>', this can be mistaken as a size suffix. Put
3431 the name in parentheses. */
3432 if (GET_CODE (addr) == SYMBOL_REF
3433 && strlen (XSTR (addr, 0)) > 2
3434 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3437 output_addr_const (file, addr);
3441 output_addr_const (file, addr);
3447 /* Check for cases where a clr insns can be omitted from code using
3448 strict_low_part sets. For example, the second clrl here is not needed:
3449 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3451 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3452 insn we are checking for redundancy. TARGET is the register set by the
3456 strict_low_part_peephole_ok (mode, first_insn, target)
3457 enum machine_mode mode;
3463 p = prev_nonnote_insn (first_insn);
3467 /* If it isn't an insn, then give up. */
3468 if (GET_CODE (p) != INSN)
3471 if (reg_set_p (target, p))
3473 rtx set = single_set (p);
3476 /* If it isn't an easy to recognize insn, then give up. */
3480 dest = SET_DEST (set);
3482 /* If this sets the entire target register to zero, then our
3483 first_insn is redundant. */
3484 if (rtx_equal_p (dest, target)
3485 && SET_SRC (set) == const0_rtx)
3487 else if (GET_CODE (dest) == STRICT_LOW_PART
3488 && GET_CODE (XEXP (dest, 0)) == REG
3489 && REGNO (XEXP (dest, 0)) == REGNO (target)
3490 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3491 <= GET_MODE_SIZE (mode)))
3492 /* This is a strict low part set which modifies less than
3493 we are using, so it is safe. */
3499 p = prev_nonnote_insn (p);
3506 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3507 range carefully since this predicate is used in DImode contexts. Also, we
3508 need some extra crud to make it work when hosted on 64-bit machines. */
3511 const_uint32_operand (op, mode)
3513 enum machine_mode mode;
3515 /* It doesn't make sense to ask this question with a mode that is
3516 not larger than 32 bits. */
3517 if (GET_MODE_BITSIZE (mode) <= 32)
3520 #if HOST_BITS_PER_WIDE_INT > 32
3521 /* All allowed constants will fit a CONST_INT. */
3522 return (GET_CODE (op) == CONST_INT
3523 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3525 return (GET_CODE (op) == CONST_INT
3526 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3530 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3531 to check the range carefully since this predicate is used in DImode
3535 const_sint32_operand (op, mode)
3537 enum machine_mode mode;
3539 /* It doesn't make sense to ask this question with a mode that is
3540 not larger than 32 bits. */
3541 if (GET_MODE_BITSIZE (mode) <= 32)
3544 /* All allowed constants will fit a CONST_INT. */
3545 return (GET_CODE (op) == CONST_INT
3546 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3549 /* Operand predicates for implementing asymmetric pc-relative addressing
3550 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3551 when used as a source operand, but not as a destintation operand.
3553 We model this by restricting the meaning of the basic predicates
3554 (general_operand, memory_operand, etc) to forbid the use of this
3555 addressing mode, and then define the following predicates that permit
3556 this addressing mode. These predicates can then be used for the
3557 source operands of the appropriate instructions.
3559 n.b. While it is theoretically possible to change all machine patterns
3560 to use this addressing more where permitted by the architecture,
3561 it has only been implemented for "common" cases: SImode, HImode, and
3562 QImode operands, and only for the principle operations that would
3563 require this addressing mode: data movement and simple integer operations.
3565 In parallel with these new predicates, two new constraint letters
3566 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3567 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3568 In the pcrel case 's' is only valid in combination with 'a' registers.
3569 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3570 of how these constraints are used.
3572 The use of these predicates is strictly optional, though patterns that
3573 don't will cause an extra reload register to be allocated where one
3576 lea (abc:w,%pc),%a0 ; need to reload address
3577 moveq &1,%d1 ; since write to pc-relative space
3578 movel %d1,%a0@ ; is not allowed
3580 lea (abc:w,%pc),%a1 ; no need to reload address here
3581 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3583 For more info, consult tiemann@cygnus.com.
3586 All of the ugliness with predicates and constraints is due to the
3587 simple fact that the m68k does not allow a pc-relative addressing
3588 mode as a destination. gcc does not distinguish between source and
3589 destination addresses. Hence, if we claim that pc-relative address
3590 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3591 end up with invalid code. To get around this problem, we left
3592 pc-relative modes as invalid addresses, and then added special
3593 predicates and constraints to accept them.
3595 A cleaner way to handle this is to modify gcc to distinguish
3596 between source and destination addresses. We can then say that
3597 pc-relative is a valid source address but not a valid destination
3598 address, and hopefully avoid a lot of the predicate and constraint
3599 hackery. Unfortunately, this would be a pretty big change. It would
3600 be a useful change for a number of ports, but there aren't any current
3601 plans to undertake this.
3603 ***************************************************************************/
3606 /* Special case of a general operand that's used as a source operand.
3607 Use this to permit reads from PC-relative memory when -mpcrel
3611 general_src_operand (op, mode)
3613 enum machine_mode mode;
3616 && GET_CODE (op) == MEM
3617 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3618 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3619 || GET_CODE (XEXP (op, 0)) == CONST))
3621 return general_operand (op, mode);
3624 /* Special case of a nonimmediate operand that's used as a source.
3625 Use this to permit reads from PC-relative memory when -mpcrel
3629 nonimmediate_src_operand (op, mode)
3631 enum machine_mode mode;
3633 if (TARGET_PCREL && GET_CODE (op) == MEM
3634 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3635 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3636 || GET_CODE (XEXP (op, 0)) == CONST))
3638 return nonimmediate_operand (op, mode);
3641 /* Special case of a memory operand that's used as a source.
3642 Use this to permit reads from PC-relative memory when -mpcrel
3646 memory_src_operand (op, mode)
3648 enum machine_mode mode;
3650 if (TARGET_PCREL && GET_CODE (op) == MEM
3651 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3652 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3653 || GET_CODE (XEXP (op, 0)) == CONST))
3655 return memory_operand (op, mode);
3658 /* Predicate that accepts only a pc-relative address. This is needed
3659 because pc-relative addresses don't satisfy the predicate
3660 "general_src_operand". */
3663 pcrel_address (op, mode)
3665 enum machine_mode mode ATTRIBUTE_UNUSED;
3667 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF
3668 || GET_CODE (op) == CONST);
3672 output_andsi3 (operands)
3676 if (GET_CODE (operands[2]) == CONST_INT
3677 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3678 && (DATA_REG_P (operands[0])
3679 || offsettable_memref_p (operands[0]))
3682 if (GET_CODE (operands[0]) != REG)
3683 operands[0] = adjust_address (operands[0], HImode, 2);
3684 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
3685 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3687 if (operands[2] == const0_rtx)
3689 return "and%.w %2,%0";
3691 if (GET_CODE (operands[2]) == CONST_INT
3692 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3693 && (DATA_REG_P (operands[0])
3694 || offsettable_memref_p (operands[0])))
3696 if (DATA_REG_P (operands[0]))
3698 operands[1] = GEN_INT (logval);
3702 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3703 operands[1] = GEN_INT (logval % 8);
3705 /* This does not set condition codes in a standard way. */
3707 return "bclr %1,%0";
3709 return "and%.l %2,%0";
3713 output_iorsi3 (operands)
3716 register int logval;
3717 if (GET_CODE (operands[2]) == CONST_INT
3718 && INTVAL (operands[2]) >> 16 == 0
3719 && (DATA_REG_P (operands[0])
3720 || offsettable_memref_p (operands[0]))
3723 if (GET_CODE (operands[0]) != REG)
3724 operands[0] = adjust_address (operands[0], HImode, 2);
3725 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3727 if (INTVAL (operands[2]) == 0xffff)
3728 return "mov%.w %2,%0";
3729 return "or%.w %2,%0";
3731 if (GET_CODE (operands[2]) == CONST_INT
3732 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3733 && (DATA_REG_P (operands[0])
3734 || offsettable_memref_p (operands[0])))
3736 if (DATA_REG_P (operands[0]))
3737 operands[1] = GEN_INT (logval);
3740 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3741 operands[1] = GEN_INT (logval % 8);
3744 return "bset %1,%0";
3746 return "or%.l %2,%0";
3750 output_xorsi3 (operands)
3753 register int logval;
3754 if (GET_CODE (operands[2]) == CONST_INT
3755 && INTVAL (operands[2]) >> 16 == 0
3756 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
3759 if (! DATA_REG_P (operands[0]))
3760 operands[0] = adjust_address (operands[0], HImode, 2);
3761 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3763 if (INTVAL (operands[2]) == 0xffff)
3765 return "eor%.w %2,%0";
3767 if (GET_CODE (operands[2]) == CONST_INT
3768 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3769 && (DATA_REG_P (operands[0])
3770 || offsettable_memref_p (operands[0])))
3772 if (DATA_REG_P (operands[0]))
3773 operands[1] = GEN_INT (logval);
3776 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3777 operands[1] = GEN_INT (logval % 8);
3780 return "bchg %1,%0";
3782 return "eor%.l %2,%0";
3785 /* Output assembly to switch to section NAME with attribute FLAGS. */
3788 m68k_coff_asm_named_section (name, flags)
3794 if (flags & SECTION_WRITE)
3799 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
3802 #ifdef CTOR_LIST_BEGIN
3804 m68k_svr3_asm_out_constructor (symbol, priority)
3806 int priority ATTRIBUTE_UNUSED;
3811 xop[0] = gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx));
3814 output_asm_insn (output_move_simode (xop), xop);