1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
45 /* Needed for use_return_insn. */
48 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
49 if SGS_SWITCH_TABLE. */
50 int switch_table_difference_label_flag;
52 static rtx find_addr_reg PARAMS ((rtx));
53 static const char *singlemove_string PARAMS ((rtx *));
54 static void m68k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
55 static void m68k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
56 static void m68k_coff_asm_named_section PARAMS ((const char *, unsigned int));
57 #ifdef CTOR_LIST_BEGIN
58 static void m68k_svr3_asm_out_constructor PARAMS ((rtx, int));
61 static void m68k_hp320_internal_label PARAMS ((FILE *, const char *, unsigned long));
62 static void m68k_hp320_file_start PARAMS ((void));
64 static void m68k_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
65 HOST_WIDE_INT, tree));
66 static int m68k_save_reg PARAMS ((unsigned int));
67 static int const_int_cost PARAMS ((rtx));
68 static bool m68k_rtx_costs PARAMS ((rtx, int, int, int *));
71 /* Alignment to use for loops and jumps */
72 /* Specify power of two alignment used for loops. */
73 const char *m68k_align_loops_string;
74 /* Specify power of two alignment used for non-loop jumps. */
75 const char *m68k_align_jumps_string;
76 /* Specify power of two alignment used for functions. */
77 const char *m68k_align_funcs_string;
79 /* Specify power of two alignment used for loops. */
81 /* Specify power of two alignment used for non-loop jumps. */
83 /* Specify power of two alignment used for functions. */
86 /* Nonzero if the last compare/test insn had FP operands. The
87 sCC expanders peek at this to determine what to do for the
88 68060, which has no fsCC instructions. */
89 int m68k_last_compare_had_fp_operands;
91 /* Initialize the GCC target structure. */
93 #if INT_OP_GROUP == INT_OP_DOT_WORD
94 #undef TARGET_ASM_ALIGNED_HI_OP
95 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
98 #if INT_OP_GROUP == INT_OP_NO_DOT
99 #undef TARGET_ASM_BYTE_OP
100 #define TARGET_ASM_BYTE_OP "\tbyte\t"
101 #undef TARGET_ASM_ALIGNED_HI_OP
102 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
103 #undef TARGET_ASM_ALIGNED_SI_OP
104 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
107 #if INT_OP_GROUP == INT_OP_DC
108 #undef TARGET_ASM_BYTE_OP
109 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
112 #undef TARGET_ASM_ALIGNED_SI_OP
113 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
116 #undef TARGET_ASM_UNALIGNED_HI_OP
117 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
118 #undef TARGET_ASM_UNALIGNED_SI_OP
119 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
121 #undef TARGET_ASM_FUNCTION_PROLOGUE
122 #define TARGET_ASM_FUNCTION_PROLOGUE m68k_output_function_prologue
123 #undef TARGET_ASM_FUNCTION_EPILOGUE
124 #define TARGET_ASM_FUNCTION_EPILOGUE m68k_output_function_epilogue
126 #undef TARGET_ASM_INTERNAL_LABEL
127 #define TARGET_ASM_INTERNAL_LABEL m68k_hp320_internal_label
130 #undef TARGET_ASM_OUTPUT_MI_THUNK
131 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
132 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
133 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
135 #undef TARGET_ASM_FILE_START_APP_OFF
136 #define TARGET_ASM_FILE_START_APP_OFF true
138 #undef TARGET_RTX_COSTS
139 #define TARGET_RTX_COSTS m68k_rtx_costs
141 struct gcc_target targetm = TARGET_INITIALIZER;
143 /* Sometimes certain combinations of command options do not make
144 sense on a particular target machine. You can define a macro
145 `OVERRIDE_OPTIONS' to take account of this. This macro, if
146 defined, is executed once just after all the command options have
149 Don't use this macro to turn on various extra optimizations for
150 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
160 /* Validate -malign-loops= value, or provide default */
161 m68k_align_loops = def_align;
162 if (m68k_align_loops_string)
164 i = atoi (m68k_align_loops_string);
165 if (i < 1 || i > MAX_CODE_ALIGN)
166 error ("-malign-loops=%d is not between 1 and %d", i, MAX_CODE_ALIGN);
168 m68k_align_loops = i;
171 /* Validate -malign-jumps= value, or provide default */
172 m68k_align_jumps = def_align;
173 if (m68k_align_jumps_string)
175 i = atoi (m68k_align_jumps_string);
176 if (i < 1 || i > MAX_CODE_ALIGN)
177 error ("-malign-jumps=%d is not between 1 and %d", i, MAX_CODE_ALIGN);
179 m68k_align_jumps = i;
182 /* Validate -malign-functions= value, or provide default */
183 m68k_align_funcs = def_align;
184 if (m68k_align_funcs_string)
186 i = atoi (m68k_align_funcs_string);
187 if (i < 1 || i > MAX_CODE_ALIGN)
188 error ("-malign-functions=%d is not between 1 and %d",
191 m68k_align_funcs = i;
194 /* -fPIC uses 32-bit pc-relative displacements, which don't exist
196 if (! TARGET_68020 && flag_pic == 2)
197 error("-fPIC is not currently supported on the 68000 or 68010\n");
199 /* ??? A historic way of turning on pic, or is this intended to
200 be an embedded thing that doesn't have the same name binding
201 significance that it does on hosted ELF systems? */
202 if (TARGET_PCREL && flag_pic == 0)
205 /* Turn off function cse if we are doing PIC. We always want function call
206 to be done as `bsr foo@PLTPC', so it will force the assembler to create
207 the PLT entry for `foo'. Doing function cse will cause the address of
208 `foo' to be loaded into a register, which is exactly what we want to
209 avoid when we are doing PIC on svr4 m68k. */
211 flag_no_function_cse = 1;
213 SUBTARGET_OVERRIDE_OPTIONS;
215 /* Tell the compiler which flavor of XFmode we're using. */
216 real_format_for_mode[XFmode - QFmode] = &ieee_extended_motorola_format;
219 /* Return 1 if we need to save REGNO. */
221 m68k_save_reg (regno)
224 if (flag_pic && current_function_uses_pic_offset_table
225 && regno == PIC_OFFSET_TABLE_REGNUM)
228 if (current_function_calls_eh_return)
233 unsigned int test = EH_RETURN_DATA_REGNO (i);
234 if (test == INVALID_REGNUM)
241 return (regs_ever_live[regno]
242 && !call_used_regs[regno]
243 && !fixed_regs[regno]
244 && !(regno == FRAME_POINTER_REGNUM && frame_pointer_needed));
247 /* This function generates the assembly code for function entry.
248 STREAM is a stdio stream to output the code to.
249 SIZE is an int: how many units of temporary storage to allocate.
250 Refer to the array `regs_ever_live' to determine which registers
251 to save; `regs_ever_live[I]' is nonzero if register number I
252 is ever used in the function. This function is responsible for
253 knowing which registers should not be saved even if used. */
256 /* Note that the order of the bit mask for fmovem is the opposite
257 of the order for movem! */
260 m68k_output_function_prologue (stream, size)
265 register int mask = 0;
266 int num_saved_regs = 0;
267 HOST_WIDE_INT fsize = (size + 3) & -4;
268 HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET;
269 HOST_WIDE_INT cfa_store_offset = cfa_offset;
271 /* If the stack limit is a symbol, we can check it here,
272 before actually allocating the space. */
273 if (current_function_limit_stack
274 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
276 #if defined (MOTOROLA)
277 asm_fprintf (stream, "\tcmp.l %I%s+%wd,%Rsp\n\ttrapcs\n",
278 XSTR (stack_limit_rtx, 0), fsize + 4);
280 asm_fprintf (stream, "\tcmpl %I%s+%wd,%Rsp\n\ttrapcs\n",
281 XSTR (stack_limit_rtx, 0), fsize + 4);
285 if (frame_pointer_needed)
287 if (fsize == 0 && TARGET_68040)
289 /* on the 68040, pea + move is faster than link.w 0 */
291 fprintf (stream, "\tpea (%s)\n\tmove.l %s,%s\n",
292 reg_names[FRAME_POINTER_REGNUM],
293 reg_names[STACK_POINTER_REGNUM],
294 reg_names[FRAME_POINTER_REGNUM]);
296 fprintf (stream, "\tpea %s@\n\tmovel %s,%s\n",
297 reg_names[FRAME_POINTER_REGNUM],
298 reg_names[STACK_POINTER_REGNUM],
299 reg_names[FRAME_POINTER_REGNUM]);
302 else if (fsize < 0x8000)
305 asm_fprintf (stream, "\tlink.w %s,%I%wd\n",
306 reg_names[FRAME_POINTER_REGNUM], -fsize);
308 asm_fprintf (stream, "\tlink %s,%I%wd\n",
309 reg_names[FRAME_POINTER_REGNUM], -fsize);
312 else if (TARGET_68020)
315 asm_fprintf (stream, "\tlink.l %s,%I%wd\n",
316 reg_names[FRAME_POINTER_REGNUM], -fsize);
318 asm_fprintf (stream, "\tlink %s,%I%wd\n",
319 reg_names[FRAME_POINTER_REGNUM], -fsize);
324 /* Adding negative number is faster on the 68040. */
326 asm_fprintf (stream, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
327 reg_names[FRAME_POINTER_REGNUM], -fsize);
329 asm_fprintf (stream, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
330 reg_names[FRAME_POINTER_REGNUM], -fsize);
333 if (dwarf2out_do_frame ())
336 l = (char *) dwarf2out_cfi_label ();
337 cfa_store_offset += 4;
338 cfa_offset = cfa_store_offset;
339 dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
340 dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
341 cfa_store_offset += fsize;
346 if (fsize + 4 < 0x8000)
350 if (!TARGET_COLDFIRE)
352 /* asm_fprintf() cannot handle %. */
354 asm_fprintf (stream, "\tsubq.w %I%wd,%Rsp\n", fsize + 4);
356 asm_fprintf (stream, "\tsubqw %I%wd,%Rsp\n", fsize + 4);
361 /* asm_fprintf() cannot handle %. */
363 asm_fprintf (stream, "\tsubq.l %I%wd,%Rsp\n", fsize + 4);
365 asm_fprintf (stream, "\tsubql %I%wd,%Rsp\n", fsize + 4);
369 else if (fsize + 4 <= 16 && TARGET_CPU32)
371 /* On the CPU32 it is faster to use two subqw instructions to
372 subtract a small integer (8 < N <= 16) to a register. */
373 /* asm_fprintf() cannot handle %. */
376 "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
379 asm_fprintf (stream, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
383 else if (TARGET_68040)
385 /* Adding negative number is faster on the 68040. */
386 /* asm_fprintf() cannot handle %. */
388 asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", - (fsize + 4));
390 asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", - (fsize + 4));
396 asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", - (fsize + 4));
398 asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", - (fsize + 4));
404 /* asm_fprintf() cannot handle %. */
406 asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", - (fsize + 4));
408 asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", - (fsize + 4));
411 if (dwarf2out_do_frame ())
413 cfa_store_offset += fsize + 4;
414 cfa_offset = cfa_store_offset;
415 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
420 for (regno = 16; regno < 24; regno++)
421 if (m68k_save_reg (regno))
423 mask |= 1 << (regno - 16);
426 if ((mask & 0xff) != 0)
429 asm_fprintf (stream, "\tfmovm %I0x%x,-(%Rsp)\n", mask & 0xff);
431 asm_fprintf (stream, "\tfmovem %I0x%x,%Rsp@-\n", mask & 0xff);
433 if (dwarf2out_do_frame ())
435 char *l = (char *) dwarf2out_cfi_label ();
438 cfa_store_offset += num_saved_regs * 12;
439 if (! frame_pointer_needed)
441 cfa_offset = cfa_store_offset;
442 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
444 for (regno = 16, n_regs = 0; regno < 24; regno++)
445 if (mask & (1 << (regno - 16)))
446 dwarf2out_reg_save (l, regno,
447 -cfa_store_offset + n_regs++ * 12);
453 for (regno = 0; regno < 16; regno++)
454 if (m68k_save_reg (regno))
456 mask |= 1 << (15 - regno);
460 /* If the stack limit is not a symbol, check it here.
461 This has the disadvantage that it may be too late... */
462 if (current_function_limit_stack)
464 if (REG_P (stack_limit_rtx))
466 #if defined (MOTOROLA)
467 asm_fprintf (stream, "\tcmp.l %s,%Rsp\n\ttrapcs\n",
468 reg_names[REGNO (stack_limit_rtx)]);
470 asm_fprintf (stream, "\tcmpl %s,%Rsp\n\ttrapcs\n",
471 reg_names[REGNO (stack_limit_rtx)]);
474 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
475 warning ("stack limit expression is not supported");
478 if (num_saved_regs <= 2)
480 /* Store each separately in the same order moveml uses.
481 Using two movel instructions instead of a single moveml
482 is about 15% faster for the 68020 and 68030 at no expense
487 /* Undo the work from above. */
488 for (i = 0; i< 16; i++)
493 "\t%Omove.l %s,-(%Rsp)\n",
495 "\tmovel %s,%Rsp@-\n",
498 if (dwarf2out_do_frame ())
500 char *l = (char *) dwarf2out_cfi_label ();
502 cfa_store_offset += 4;
503 if (! frame_pointer_needed)
505 cfa_offset = cfa_store_offset;
506 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
508 dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
516 /* The coldfire does not support the predecrement form of the
517 movml instruction, so we must adjust the stack pointer and
518 then use the plain address register indirect mode. We also
519 have to invert the register save mask to use the new mode.
521 FIXME: if num_saved_regs was calculated earlier, we could
522 combine the stack pointer adjustment with any adjustment
523 done when the initial stack frame is created. This would
524 save an instruction */
529 for (i = 0; i < 16; i++)
531 newmask |= (1 << (15-i));
534 asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
535 asm_fprintf (stream, "\tmovm.l %I0x%x,(%Rsp)\n", newmask);
537 asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
538 asm_fprintf (stream, "\tmoveml %I0x%x,%Rsp@\n", newmask);
544 asm_fprintf (stream, "\tmovm.l %I0x%x,-(%Rsp)\n", mask);
546 asm_fprintf (stream, "\tmoveml %I0x%x,%Rsp@-\n", mask);
549 if (dwarf2out_do_frame ())
551 char *l = (char *) dwarf2out_cfi_label ();
554 cfa_store_offset += num_saved_regs * 4;
555 if (! frame_pointer_needed)
557 cfa_offset = cfa_store_offset;
558 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
560 for (regno = 0, n_regs = 0; regno < 16; regno++)
561 if (mask & (1 << (15 - regno)))
562 dwarf2out_reg_save (l, regno,
563 -cfa_store_offset + n_regs++ * 4);
566 if (flag_pic && current_function_uses_pic_offset_table)
569 asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
570 reg_names[PIC_OFFSET_TABLE_REGNUM]);
572 asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
573 reg_names[PIC_OFFSET_TABLE_REGNUM]);
574 asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
575 reg_names[PIC_OFFSET_TABLE_REGNUM],
576 reg_names[PIC_OFFSET_TABLE_REGNUM]);
581 /* Return true if this function's epilogue can be output as RTL. */
588 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
591 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
592 if (m68k_save_reg (regno))
598 /* This function generates the assembly code for function exit,
599 on machines that need it.
601 The function epilogue should not depend on the current stack pointer!
602 It should use the frame pointer only, if there is a frame pointer.
603 This is mandatory because of alloca; we also take advantage of it to
604 omit stack adjustments before returning. */
607 m68k_output_function_epilogue (stream, size)
612 register int mask, fmask;
614 HOST_WIDE_INT offset, foffset;
615 HOST_WIDE_INT fsize = (size + 3) & -4;
617 rtx insn = get_last_insn ();
618 int restore_from_sp = 0;
620 /* If the last insn was a BARRIER, we don't have to write any code. */
621 if (GET_CODE (insn) == NOTE)
622 insn = prev_nonnote_insn (insn);
623 if (insn && GET_CODE (insn) == BARRIER)
625 /* Output just a no-op so that debuggers don't get confused
626 about which function the pc is in at this address. */
627 fprintf (stream, "\tnop\n");
631 #ifdef FUNCTION_EXTRA_EPILOGUE
632 FUNCTION_EXTRA_EPILOGUE (stream, size);
634 nregs = 0; fmask = 0;
637 for (regno = 16; regno < 24; regno++)
638 if (m68k_save_reg (regno))
641 fmask |= 1 << (23 - regno);
644 foffset = nregs * 12;
646 for (regno = 0; regno < 16; regno++)
647 if (m68k_save_reg (regno))
652 offset = foffset + nregs * 4;
653 /* FIXME : leaf_function_p below is too strong.
654 What we really need to know there is if there could be pending
655 stack adjustment needed at that point. */
656 restore_from_sp = ! frame_pointer_needed
657 || (! current_function_calls_alloca && leaf_function_p ());
658 if (offset + fsize >= 0x8000
663 asm_fprintf (stream, "\t%Omove.l %I%wd,%Ra1\n", -fsize);
665 asm_fprintf (stream, "\tmovel %I%wd,%Ra1\n", -fsize);
669 if (TARGET_COLDFIRE || nregs <= 2)
671 /* Restore each separately in the same order moveml does.
672 Using two movel instructions instead of a single moveml
673 is about 15% faster for the 68020 and 68030 at no expense
678 /* Undo the work from above. */
679 for (i = 0; i< 16; i++)
685 asm_fprintf (stream, "\t%Omove.l -%wd(%s,%Ra1.l),%s\n",
687 reg_names[FRAME_POINTER_REGNUM],
690 asm_fprintf (stream, "\tmovel %s@(-%wd,%Ra1:l),%s\n",
691 reg_names[FRAME_POINTER_REGNUM],
692 offset + fsize, reg_names[i]);
695 else if (restore_from_sp)
698 asm_fprintf (stream, "\t%Omove.l (%Rsp)+,%s\n",
701 asm_fprintf (stream, "\tmovel %Rsp@+,%s\n",
708 asm_fprintf (stream, "\t%Omove.l -%wd(%s),%s\n",
710 reg_names[FRAME_POINTER_REGNUM],
713 asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n",
714 reg_names[FRAME_POINTER_REGNUM],
715 offset + fsize, reg_names[i]);
726 asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
728 reg_names[FRAME_POINTER_REGNUM],
731 asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
732 reg_names[FRAME_POINTER_REGNUM],
733 offset + fsize, mask);
736 else if (restore_from_sp)
739 asm_fprintf (stream, "\tmovm.l (%Rsp)+,%I0x%x\n", mask);
741 asm_fprintf (stream, "\tmoveml %Rsp@+,%I0x%x\n", mask);
747 asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
749 reg_names[FRAME_POINTER_REGNUM],
752 asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
753 reg_names[FRAME_POINTER_REGNUM],
754 offset + fsize, mask);
763 asm_fprintf (stream, "\tfmovm -%wd(%s,%Ra1.l),%I0x%x\n",
765 reg_names[FRAME_POINTER_REGNUM],
768 asm_fprintf (stream, "\tfmovem %s@(-%wd,%Ra1:l),%I0x%x\n",
769 reg_names[FRAME_POINTER_REGNUM],
770 foffset + fsize, fmask);
773 else if (restore_from_sp)
776 asm_fprintf (stream, "\tfmovm (%Rsp)+,%I0x%x\n", fmask);
778 asm_fprintf (stream, "\tfmovem %Rsp@+,%I0x%x\n", fmask);
784 asm_fprintf (stream, "\tfmovm -%wd(%s),%I0x%x\n",
786 reg_names[FRAME_POINTER_REGNUM],
789 asm_fprintf (stream, "\tfmovem %s@(-%wd),%I0x%x\n",
790 reg_names[FRAME_POINTER_REGNUM],
791 foffset + fsize, fmask);
795 if (frame_pointer_needed)
796 fprintf (stream, "\tunlk %s\n",
797 reg_names[FRAME_POINTER_REGNUM]);
802 if (!TARGET_COLDFIRE)
805 asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize + 4);
807 asm_fprintf (stream, "\taddqw %I%wd,%Rsp\n", fsize + 4);
813 asm_fprintf (stream, "\taddq.l %I%wd,%Rsp\n", fsize + 4);
815 asm_fprintf (stream, "\taddql %I%wd,%Rsp\n", fsize + 4);
819 else if (fsize + 4 <= 16 && TARGET_CPU32)
821 /* On the CPU32 it is faster to use two addqw instructions to
822 add a small integer (8 < N <= 16) to a register. */
823 /* asm_fprintf() cannot handle %. */
825 asm_fprintf (stream, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
828 asm_fprintf (stream, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
832 else if (fsize + 4 < 0x8000)
836 /* asm_fprintf() cannot handle %. */
838 asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", fsize + 4);
840 asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", fsize + 4);
846 asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", fsize + 4);
848 asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", fsize + 4);
854 /* asm_fprintf() cannot handle %. */
856 asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", fsize + 4);
858 asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", fsize + 4);
862 if (current_function_calls_eh_return)
865 asm_fprintf (stream, "\tadd.l %Ra0,%Rsp\n");
867 asm_fprintf (stream, "\taddl %Ra0,%Rsp\n");
870 if (current_function_pops_args)
871 asm_fprintf (stream, "\trtd %I%d\n", current_function_pops_args);
873 fprintf (stream, "\trts\n");
876 /* Similar to general_operand, but exclude stack_pointer_rtx. */
879 not_sp_operand (op, mode)
881 enum machine_mode mode;
883 return op != stack_pointer_rtx && nonimmediate_operand (op, mode);
886 /* Return TRUE if X is a valid comparison operator for the dbcc
889 Note it rejects floating point comparison operators.
890 (In the future we could use Fdbcc).
892 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
895 valid_dbcc_comparison_p (x, mode)
897 enum machine_mode mode ATTRIBUTE_UNUSED;
899 switch (GET_CODE (x))
901 case EQ: case NE: case GTU: case LTU:
905 /* Reject some when CC_NO_OVERFLOW is set. This may be over
907 case GT: case LT: case GE: case LE:
908 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
914 /* Return nonzero if flags are currently in the 68881 flag register. */
918 /* We could add support for these in the future */
919 return cc_status.flags & CC_IN_68881;
922 /* Output a dbCC; jCC sequence. Note we do not handle the
923 floating point version of this sequence (Fdbcc). We also
924 do not handle alternative conditions when CC_NO_OVERFLOW is
925 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
926 kick those out before we get here. */
929 output_dbcc_and_branch (operands)
932 switch (GET_CODE (operands[3]))
936 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands);
938 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
944 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands);
946 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
952 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands);
954 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
960 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands);
962 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
968 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands);
970 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
976 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands);
978 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
984 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands);
986 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
992 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands);
994 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1000 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands);
1002 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1008 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands);
1010 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1018 /* If the decrement is to be done in SImode, then we have
1019 to compensate for the fact that dbcc decrements in HImode. */
1020 switch (GET_MODE (operands[0]))
1024 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands);
1026 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands);
1039 output_scc_di(op, operand1, operand2, dest)
1046 enum rtx_code op_code = GET_CODE (op);
1048 /* This does not produce a useful cc. */
1051 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1052 below. Swap the operands and change the op if these requirements
1053 are not fulfilled. */
1054 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1058 operand1 = operand2;
1060 op_code = swap_condition (op_code);
1062 loperands[0] = operand1;
1063 if (GET_CODE (operand1) == REG)
1064 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1066 loperands[1] = adjust_address (operand1, SImode, 4);
1067 if (operand2 != const0_rtx)
1069 loperands[2] = operand2;
1070 if (GET_CODE (operand2) == REG)
1071 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1073 loperands[3] = adjust_address (operand2, SImode, 4);
1075 loperands[4] = gen_label_rtx();
1076 if (operand2 != const0_rtx)
1079 #ifdef SGS_CMP_ORDER
1080 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands);
1082 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands);
1085 #ifdef SGS_CMP_ORDER
1086 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands);
1088 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1094 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1095 output_asm_insn ("tst%.l %0", loperands);
1098 #ifdef SGS_CMP_ORDER
1099 output_asm_insn ("cmp%.w %0,%#0", loperands);
1101 output_asm_insn ("cmp%.w %#0,%0", loperands);
1106 output_asm_insn ("jbne %l4", loperands);
1108 output_asm_insn ("jne %l4", loperands);
1111 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1112 output_asm_insn ("tst%.l %1", loperands);
1115 #ifdef SGS_CMP_ORDER
1116 output_asm_insn ("cmp%.w %1,%#0", loperands);
1118 output_asm_insn ("cmp%.w %#0,%1", loperands);
1123 loperands[5] = dest;
1128 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1129 CODE_LABEL_NUMBER (loperands[4]));
1130 output_asm_insn ("seq %5", loperands);
1134 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1135 CODE_LABEL_NUMBER (loperands[4]));
1136 output_asm_insn ("sne %5", loperands);
1140 loperands[6] = gen_label_rtx();
1142 output_asm_insn ("shi %5\n\tjbra %l6", loperands);
1144 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1146 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1147 CODE_LABEL_NUMBER (loperands[4]));
1148 output_asm_insn ("sgt %5", loperands);
1149 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1150 CODE_LABEL_NUMBER (loperands[6]));
1154 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1155 CODE_LABEL_NUMBER (loperands[4]));
1156 output_asm_insn ("shi %5", loperands);
1160 loperands[6] = gen_label_rtx();
1162 output_asm_insn ("scs %5\n\tjbra %l6", loperands);
1164 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1166 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1167 CODE_LABEL_NUMBER (loperands[4]));
1168 output_asm_insn ("slt %5", loperands);
1169 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1170 CODE_LABEL_NUMBER (loperands[6]));
1174 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1175 CODE_LABEL_NUMBER (loperands[4]));
1176 output_asm_insn ("scs %5", loperands);
1180 loperands[6] = gen_label_rtx();
1182 output_asm_insn ("scc %5\n\tjbra %l6", loperands);
1184 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1186 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1187 CODE_LABEL_NUMBER (loperands[4]));
1188 output_asm_insn ("sge %5", loperands);
1189 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1190 CODE_LABEL_NUMBER (loperands[6]));
1194 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1195 CODE_LABEL_NUMBER (loperands[4]));
1196 output_asm_insn ("scc %5", loperands);
1200 loperands[6] = gen_label_rtx();
1202 output_asm_insn ("sls %5\n\tjbra %l6", loperands);
1204 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1206 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1207 CODE_LABEL_NUMBER (loperands[4]));
1208 output_asm_insn ("sle %5", loperands);
1209 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1210 CODE_LABEL_NUMBER (loperands[6]));
1214 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1215 CODE_LABEL_NUMBER (loperands[4]));
1216 output_asm_insn ("sls %5", loperands);
1226 output_btst (operands, countop, dataop, insn, signpos)
1228 rtx countop, dataop;
1232 operands[0] = countop;
1233 operands[1] = dataop;
1235 if (GET_CODE (countop) == CONST_INT)
1237 register int count = INTVAL (countop);
1238 /* If COUNT is bigger than size of storage unit in use,
1239 advance to the containing unit of same size. */
1240 if (count > signpos)
1242 int offset = (count & ~signpos) / 8;
1243 count = count & signpos;
1244 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1246 if (count == signpos)
1247 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1249 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1251 /* These three statements used to use next_insns_test_no...
1252 but it appears that this should do the same job. */
1254 && next_insn_tests_no_inequality (insn))
1257 && next_insn_tests_no_inequality (insn))
1260 && next_insn_tests_no_inequality (insn))
1263 cc_status.flags = CC_NOT_NEGATIVE;
1265 return "btst %0,%1";
1268 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1269 reference and a constant. */
1272 symbolic_operand (op, mode)
1274 enum machine_mode mode ATTRIBUTE_UNUSED;
1276 switch (GET_CODE (op))
1284 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1285 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1286 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1288 #if 0 /* Deleted, with corresponding change in m68k.h,
1289 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1291 return GET_MODE (op) == mode;
1299 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1302 extend_operator(x, mode)
1304 enum machine_mode mode;
1306 if (mode != VOIDmode && GET_MODE(x) != mode)
1308 switch (GET_CODE(x))
1319 /* Legitimize PIC addresses. If the address is already
1320 position-independent, we return ORIG. Newly generated
1321 position-independent addresses go to REG. If we need more
1322 than one register, we lose.
1324 An address is legitimized by making an indirect reference
1325 through the Global Offset Table with the name of the symbol
1328 The assembler and linker are responsible for placing the
1329 address of the symbol in the GOT. The function prologue
1330 is responsible for initializing a5 to the starting address
1333 The assembler is also responsible for translating a symbol name
1334 into a constant displacement from the start of the GOT.
1336 A quick example may make things a little clearer:
1338 When not generating PIC code to store the value 12345 into _foo
1339 we would generate the following code:
1343 When generating PIC two transformations are made. First, the compiler
1344 loads the address of foo into a register. So the first transformation makes:
1349 The code in movsi will intercept the lea instruction and call this
1350 routine which will transform the instructions into:
1352 movel a5@(_foo:w), a0
1356 That (in a nutshell) is how *all* symbol and label references are
1360 legitimize_pic_address (orig, mode, reg)
1362 enum machine_mode mode ATTRIBUTE_UNUSED;
1366 /* First handle a simple SYMBOL_REF or LABEL_REF */
1367 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1372 pic_ref = gen_rtx_MEM (Pmode,
1373 gen_rtx_PLUS (Pmode,
1374 pic_offset_table_rtx, orig));
1375 current_function_uses_pic_offset_table = 1;
1376 RTX_UNCHANGING_P (pic_ref) = 1;
1377 emit_move_insn (reg, pic_ref);
1380 else if (GET_CODE (orig) == CONST)
1384 /* Make sure this is CONST has not already been legitimized */
1385 if (GET_CODE (XEXP (orig, 0)) == PLUS
1386 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1392 /* legitimize both operands of the PLUS */
1393 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1395 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1396 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1397 base == reg ? 0 : reg);
1401 if (GET_CODE (orig) == CONST_INT)
1402 return plus_constant (base, INTVAL (orig));
1403 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1404 /* Likewise, should we set special REG_NOTEs here? */
1410 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
1412 static CONST_METHOD const_method PARAMS ((rtx));
1414 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1417 const_method (constant)
1423 i = INTVAL (constant);
1427 /* The Coldfire doesn't have byte or word operations. */
1428 /* FIXME: This may not be useful for the m68060 either */
1429 if (!TARGET_COLDFIRE)
1431 /* if -256 < N < 256 but N is not in range for a moveq
1432 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1433 if (USE_MOVQ (i ^ 0xff))
1435 /* Likewise, try with not.w */
1436 if (USE_MOVQ (i ^ 0xffff))
1438 /* This is the only value where neg.w is useful */
1441 /* Try also with swap */
1443 if (USE_MOVQ ((u >> 16) | (u << 16)))
1446 /* Otherwise, use move.l */
1451 const_int_cost (constant)
1454 switch (const_method (constant))
1457 /* Constants between -128 and 127 are cheap due to moveq */
1463 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1473 m68k_rtx_costs (x, code, outer_code, total)
1475 int code, outer_code;
1481 /* Constant zero is super cheap due to clr instruction. */
1482 if (x == const0_rtx)
1485 *total = const_int_cost (x);
1495 /* Make 0.0 cheaper than other floating constants to
1496 encourage creating tstsf and tstdf insns. */
1497 if (outer_code == COMPARE
1498 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
1504 /* These are vaguely right for a 68020. */
1505 /* The costs for long multiply have been adjusted to work properly
1506 in synth_mult on the 68020, relative to an average of the time
1507 for add and the time for shift, taking away a little more because
1508 sometimes move insns are needed. */
1509 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1510 #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
1511 #define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1512 TARGET_CFV3 ? 2 : 5)
1513 #define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1516 /* An lea costs about three times as much as a simple add. */
1517 if (GET_MODE (x) == SImode
1518 && GET_CODE (XEXP (x, 1)) == REG
1519 && GET_CODE (XEXP (x, 0)) == MULT
1520 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1521 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1522 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
1523 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
1524 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
1526 /* lea an@(dx:l:i),am */
1527 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
1537 *total = COSTS_N_INSNS(1);
1540 if (! TARGET_68020 && ! TARGET_COLDFIRE)
1542 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1544 if (INTVAL (XEXP (x, 1)) < 16)
1545 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
1547 /* We're using clrw + swap for these cases. */
1548 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
1551 *total = COSTS_N_INSNS (10); /* worst case */
1554 /* A shift by a big integer takes an extra instruction. */
1555 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1556 && (INTVAL (XEXP (x, 1)) == 16))
1558 *total = COSTS_N_INSNS (2); /* clrw;swap */
1561 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1562 && !(INTVAL (XEXP (x, 1)) > 0
1563 && INTVAL (XEXP (x, 1)) <= 8))
1565 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
1571 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
1572 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
1573 && GET_MODE (x) == SImode)
1574 *total = COSTS_N_INSNS (MULW_COST);
1575 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
1576 *total = COSTS_N_INSNS (MULW_COST);
1578 *total = COSTS_N_INSNS (MULL_COST);
1585 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
1586 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
1587 else if (TARGET_CF_HWDIV)
1588 *total = COSTS_N_INSNS (18);
1590 *total = COSTS_N_INSNS (43); /* div.l */
1599 output_move_const_into_data_reg (operands)
1604 i = INTVAL (operands[1]);
1605 switch (const_method (operands[1]))
1608 return "moveq %1,%0";
1610 operands[1] = GEN_INT (i ^ 0xff);
1611 return "moveq %1,%0\n\tnot%.b %0";
1613 operands[1] = GEN_INT (i ^ 0xffff);
1614 return "moveq %1,%0\n\tnot%.w %0";
1616 return "moveq %#-128,%0\n\tneg%.w %0";
1621 operands[1] = GEN_INT ((u << 16) | (u >> 16));
1622 return "moveq %1,%0\n\tswap %0";
1625 return "move%.l %1,%0";
1632 output_move_simode_const (operands)
1635 if (operands[1] == const0_rtx
1636 && (DATA_REG_P (operands[0])
1637 || GET_CODE (operands[0]) == MEM)
1638 /* clr insns on 68000 read before writing.
1639 This isn't so on the 68010, but we have no TARGET_68010. */
1640 && ((TARGET_68020 || TARGET_COLDFIRE)
1641 || !(GET_CODE (operands[0]) == MEM
1642 && MEM_VOLATILE_P (operands[0]))))
1644 else if (operands[1] == const0_rtx
1645 && ADDRESS_REG_P (operands[0]))
1646 return "sub%.l %0,%0";
1647 else if (DATA_REG_P (operands[0]))
1648 return output_move_const_into_data_reg (operands);
1649 else if (ADDRESS_REG_P (operands[0])
1650 && INTVAL (operands[1]) < 0x8000
1651 && INTVAL (operands[1]) >= -0x8000)
1652 return "move%.w %1,%0";
1653 else if (GET_CODE (operands[0]) == MEM
1654 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1655 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
1656 && INTVAL (operands[1]) < 0x8000
1657 && INTVAL (operands[1]) >= -0x8000)
1659 return "move%.l %1,%0";
1663 output_move_simode (operands)
1666 if (GET_CODE (operands[1]) == CONST_INT)
1667 return output_move_simode_const (operands);
1668 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1669 || GET_CODE (operands[1]) == CONST)
1670 && push_operand (operands[0], SImode))
1672 else if ((GET_CODE (operands[1]) == SYMBOL_REF
1673 || GET_CODE (operands[1]) == CONST)
1674 && ADDRESS_REG_P (operands[0]))
1675 return "lea %a1,%0";
1676 return "move%.l %1,%0";
1680 output_move_himode (operands)
1683 if (GET_CODE (operands[1]) == CONST_INT)
1685 if (operands[1] == const0_rtx
1686 && (DATA_REG_P (operands[0])
1687 || GET_CODE (operands[0]) == MEM)
1688 /* clr insns on 68000 read before writing.
1689 This isn't so on the 68010, but we have no TARGET_68010. */
1690 && ((TARGET_68020 || TARGET_COLDFIRE)
1691 || !(GET_CODE (operands[0]) == MEM
1692 && MEM_VOLATILE_P (operands[0]))))
1694 else if (operands[1] == const0_rtx
1695 && ADDRESS_REG_P (operands[0]))
1696 return "sub%.l %0,%0";
1697 else if (DATA_REG_P (operands[0])
1698 && INTVAL (operands[1]) < 128
1699 && INTVAL (operands[1]) >= -128)
1701 return "moveq %1,%0";
1703 else if (INTVAL (operands[1]) < 0x8000
1704 && INTVAL (operands[1]) >= -0x8000)
1705 return "move%.w %1,%0";
1707 else if (CONSTANT_P (operands[1]))
1708 return "move%.l %1,%0";
1709 /* Recognize the insn before a tablejump, one that refers
1710 to a table of offsets. Such an insn will need to refer
1711 to a label on the insn. So output one. Use the label-number
1712 of the table of offsets to generate this label. This code,
1713 and similar code below, assumes that there will be at most one
1714 reference to each table. */
1715 if (GET_CODE (operands[1]) == MEM
1716 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1717 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
1718 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
1720 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
1721 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1723 asm_fprintf (asm_out_file, "\tset %LLI%d,.+2\n",
1724 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1726 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
1727 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1728 #endif /* not SGS */
1729 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1730 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
1731 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
1732 #ifdef SGS_SWITCH_TABLES
1733 /* Set flag saying we need to define the symbol
1734 LD%n (with value L%n-LI%n) at the end of the switch table. */
1735 switch_table_difference_label_flag = 1;
1736 #endif /* SGS_SWITCH_TABLES */
1737 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1739 return "move%.w %1,%0";
1743 output_move_qimode (operands)
1748 /* This is probably useless, since it loses for pushing a struct
1749 of several bytes a byte at a time. */
1750 /* 68k family always modifies the stack pointer by at least 2, even for
1751 byte pushes. The 5200 (coldfire) does not do this. */
1752 if (GET_CODE (operands[0]) == MEM
1753 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1754 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1755 && ! ADDRESS_REG_P (operands[1])
1756 && ! TARGET_COLDFIRE)
1758 xoperands[1] = operands[1];
1760 = gen_rtx_MEM (QImode,
1761 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx, const1_rtx));
1762 /* Just pushing a byte puts it in the high byte of the halfword. */
1763 /* We must put it in the low-order, high-numbered byte. */
1764 if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
1766 xoperands[3] = stack_pointer_rtx;
1767 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
1770 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
1774 /* clr and st insns on 68000 read before writing.
1775 This isn't so on the 68010, but we have no TARGET_68010. */
1776 if (!ADDRESS_REG_P (operands[0])
1777 && ((TARGET_68020 || TARGET_COLDFIRE)
1778 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1780 if (operands[1] == const0_rtx)
1782 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
1783 && GET_CODE (operands[1]) == CONST_INT
1784 && (INTVAL (operands[1]) & 255) == 255)
1790 if (GET_CODE (operands[1]) == CONST_INT
1791 && DATA_REG_P (operands[0])
1792 && INTVAL (operands[1]) < 128
1793 && INTVAL (operands[1]) >= -128)
1795 return "moveq %1,%0";
1797 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
1798 return "sub%.l %0,%0";
1799 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1800 return "move%.l %1,%0";
1801 /* 68k family (including the 5200 coldfire) does not support byte moves to
1802 from address registers. */
1803 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1804 return "move%.w %1,%0";
1805 return "move%.b %1,%0";
1809 output_move_stricthi (operands)
1812 if (operands[1] == const0_rtx
1813 /* clr insns on 68000 read before writing.
1814 This isn't so on the 68010, but we have no TARGET_68010. */
1815 && ((TARGET_68020 || TARGET_COLDFIRE)
1816 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1818 return "move%.w %1,%0";
1822 output_move_strictqi (operands)
1825 if (operands[1] == const0_rtx
1826 /* clr insns on 68000 read before writing.
1827 This isn't so on the 68010, but we have no TARGET_68010. */
1828 && ((TARGET_68020 || TARGET_COLDFIRE)
1829 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1831 return "move%.b %1,%0";
1834 /* Return the best assembler insn template
1835 for moving operands[1] into operands[0] as a fullword. */
1838 singlemove_string (operands)
1841 if (GET_CODE (operands[1]) == CONST_INT)
1842 return output_move_simode_const (operands);
1843 return "move%.l %1,%0";
1847 /* Output assembler code to perform a doubleword move insn
1848 with operands OPERANDS. */
1851 output_move_double (operands)
1856 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
1861 rtx addreg0 = 0, addreg1 = 0;
1862 int dest_overlapped_low = 0;
1863 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
1868 /* First classify both operands. */
1870 if (REG_P (operands[0]))
1872 else if (offsettable_memref_p (operands[0]))
1874 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1876 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1878 else if (GET_CODE (operands[0]) == MEM)
1883 if (REG_P (operands[1]))
1885 else if (CONSTANT_P (operands[1]))
1887 else if (offsettable_memref_p (operands[1]))
1889 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
1891 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1893 else if (GET_CODE (operands[1]) == MEM)
1898 /* Check for the cases that the operand constraints are not
1899 supposed to allow to happen. Abort if we get one,
1900 because generating code for these cases is painful. */
1902 if (optype0 == RNDOP || optype1 == RNDOP)
1905 /* If one operand is decrementing and one is incrementing
1906 decrement the former register explicitly
1907 and change that operand into ordinary indexing. */
1909 if (optype0 == PUSHOP && optype1 == POPOP)
1911 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1913 output_asm_insn ("sub%.l %#12,%0", operands);
1915 output_asm_insn ("subq%.l %#8,%0", operands);
1916 if (GET_MODE (operands[1]) == XFmode)
1917 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
1918 else if (GET_MODE (operands[0]) == DFmode)
1919 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
1921 operands[0] = gen_rtx_MEM (DImode, operands[0]);
1924 if (optype0 == POPOP && optype1 == PUSHOP)
1926 operands[1] = XEXP (XEXP (operands[1], 0), 0);
1928 output_asm_insn ("sub%.l %#12,%1", operands);
1930 output_asm_insn ("subq%.l %#8,%1", operands);
1931 if (GET_MODE (operands[1]) == XFmode)
1932 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
1933 else if (GET_MODE (operands[1]) == DFmode)
1934 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
1936 operands[1] = gen_rtx_MEM (DImode, operands[1]);
1940 /* If an operand is an unoffsettable memory ref, find a register
1941 we can increment temporarily to make it refer to the second word. */
1943 if (optype0 == MEMOP)
1944 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1946 if (optype1 == MEMOP)
1947 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1949 /* Ok, we can do one word at a time.
1950 Normally we do the low-numbered word first,
1951 but if either operand is autodecrementing then we
1952 do the high-numbered word first.
1954 In either case, set up in LATEHALF the operands to use
1955 for the high-numbered word and in some cases alter the
1956 operands in OPERANDS to be suitable for the low-numbered word. */
1960 if (optype0 == REGOP)
1962 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
1963 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1965 else if (optype0 == OFFSOP)
1967 middlehalf[0] = adjust_address (operands[0], SImode, 4);
1968 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
1972 middlehalf[0] = operands[0];
1973 latehalf[0] = operands[0];
1976 if (optype1 == REGOP)
1978 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1979 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1981 else if (optype1 == OFFSOP)
1983 middlehalf[1] = adjust_address (operands[1], SImode, 4);
1984 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
1986 else if (optype1 == CNSTOP)
1988 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1993 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1994 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1995 operands[1] = GEN_INT (l[0]);
1996 middlehalf[1] = GEN_INT (l[1]);
1997 latehalf[1] = GEN_INT (l[2]);
1999 else if (CONSTANT_P (operands[1]))
2001 /* actually, no non-CONST_DOUBLE constant should ever
2004 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
2005 latehalf[1] = constm1_rtx;
2007 latehalf[1] = const0_rtx;
2012 middlehalf[1] = operands[1];
2013 latehalf[1] = operands[1];
2017 /* size is not 12: */
2019 if (optype0 == REGOP)
2020 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2021 else if (optype0 == OFFSOP)
2022 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2024 latehalf[0] = operands[0];
2026 if (optype1 == REGOP)
2027 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2028 else if (optype1 == OFFSOP)
2029 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2030 else if (optype1 == CNSTOP)
2031 split_double (operands[1], &operands[1], &latehalf[1]);
2033 latehalf[1] = operands[1];
2036 /* If insn is effectively movd N(sp),-(sp) then we will do the
2037 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2038 for the low word as well, to compensate for the first decrement of sp. */
2039 if (optype0 == PUSHOP
2040 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2041 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2042 operands[1] = middlehalf[1] = latehalf[1];
2044 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2045 if the upper part of reg N does not appear in the MEM, arrange to
2046 emit the move late-half first. Otherwise, compute the MEM address
2047 into the upper part of N and use that as a pointer to the memory
2049 if (optype0 == REGOP
2050 && (optype1 == OFFSOP || optype1 == MEMOP))
2052 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2054 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2055 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2057 /* If both halves of dest are used in the src memory address,
2058 compute the address into latehalf of dest.
2059 Note that this can't happen if the dest is two data regs. */
2061 xops[0] = latehalf[0];
2062 xops[1] = XEXP (operands[1], 0);
2063 output_asm_insn ("lea %a1,%0", xops);
2064 if (GET_MODE (operands[1]) == XFmode )
2066 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2067 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2068 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2072 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2073 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2077 && reg_overlap_mentioned_p (middlehalf[0],
2078 XEXP (operands[1], 0)))
2080 /* Check for two regs used by both source and dest.
2081 Note that this can't happen if the dest is all data regs.
2082 It can happen if the dest is d6, d7, a0.
2083 But in that case, latehalf is an addr reg, so
2084 the code at compadr does ok. */
2086 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2087 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2090 /* JRV says this can't happen: */
2091 if (addreg0 || addreg1)
2094 /* Only the middle reg conflicts; simply put it last. */
2095 output_asm_insn (singlemove_string (operands), operands);
2096 output_asm_insn (singlemove_string (latehalf), latehalf);
2097 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2100 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2101 /* If the low half of dest is mentioned in the source memory
2102 address, the arrange to emit the move late half first. */
2103 dest_overlapped_low = 1;
2106 /* If one or both operands autodecrementing,
2107 do the two words, high-numbered first. */
2109 /* Likewise, the first move would clobber the source of the second one,
2110 do them in the other order. This happens only for registers;
2111 such overlap can't happen in memory unless the user explicitly
2112 sets it up, and that is an undefined circumstance. */
2114 if (optype0 == PUSHOP || optype1 == PUSHOP
2115 || (optype0 == REGOP && optype1 == REGOP
2116 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2117 || REGNO (operands[0]) == REGNO (latehalf[1])))
2118 || dest_overlapped_low)
2120 /* Make any unoffsettable addresses point at high-numbered word. */
2124 output_asm_insn ("addq%.l %#8,%0", &addreg0);
2126 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2131 output_asm_insn ("addq%.l %#8,%0", &addreg1);
2133 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2137 output_asm_insn (singlemove_string (latehalf), latehalf);
2139 /* Undo the adds we just did. */
2141 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2143 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2147 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2149 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2151 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2154 /* Do low-numbered word. */
2155 return singlemove_string (operands);
2158 /* Normal case: do the two words, low-numbered first. */
2160 output_asm_insn (singlemove_string (operands), operands);
2162 /* Do the middle one of the three words for long double */
2166 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2168 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2170 output_asm_insn (singlemove_string (middlehalf), middlehalf);
2173 /* Make any unoffsettable addresses point at high-numbered word. */
2175 output_asm_insn ("addq%.l %#4,%0", &addreg0);
2177 output_asm_insn ("addq%.l %#4,%0", &addreg1);
2180 output_asm_insn (singlemove_string (latehalf), latehalf);
2182 /* Undo the adds we just did. */
2186 output_asm_insn ("subq%.l %#8,%0", &addreg0);
2188 output_asm_insn ("subq%.l %#4,%0", &addreg0);
2193 output_asm_insn ("subq%.l %#8,%0", &addreg1);
2195 output_asm_insn ("subq%.l %#4,%0", &addreg1);
2201 /* Return a REG that occurs in ADDR with coefficient 1.
2202 ADDR can be effectively incremented by incrementing REG. */
2205 find_addr_reg (addr)
2208 while (GET_CODE (addr) == PLUS)
2210 if (GET_CODE (XEXP (addr, 0)) == REG)
2211 addr = XEXP (addr, 0);
2212 else if (GET_CODE (XEXP (addr, 1)) == REG)
2213 addr = XEXP (addr, 1);
2214 else if (CONSTANT_P (XEXP (addr, 0)))
2215 addr = XEXP (addr, 1);
2216 else if (CONSTANT_P (XEXP (addr, 1)))
2217 addr = XEXP (addr, 0);
2221 if (GET_CODE (addr) == REG)
2226 /* Output assembler code to perform a 32 bit 3 operand add. */
2229 output_addsi3 (operands)
2232 if (! operands_match_p (operands[0], operands[1]))
2234 if (!ADDRESS_REG_P (operands[1]))
2236 rtx tmp = operands[1];
2238 operands[1] = operands[2];
2242 /* These insns can result from reloads to access
2243 stack slots over 64k from the frame pointer. */
2244 if (GET_CODE (operands[2]) == CONST_INT
2245 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2246 return "move%.l %2,%0\n\tadd%.l %1,%0";
2248 if (GET_CODE (operands[2]) == REG)
2249 return "lea 0(%1,%2.l),%0";
2251 return "lea %c2(%1),%0";
2254 if (GET_CODE (operands[2]) == REG)
2255 return "lea (%1,%2.l),%0";
2257 return "lea (%c2,%1),%0";
2258 #else /* not MOTOROLA (MIT syntax) */
2259 if (GET_CODE (operands[2]) == REG)
2260 return "lea %1@(0,%2:l),%0";
2262 return "lea %1@(%c2),%0";
2263 #endif /* not MOTOROLA */
2264 #endif /* not SGS */
2266 if (GET_CODE (operands[2]) == CONST_INT)
2268 if (INTVAL (operands[2]) > 0
2269 && INTVAL (operands[2]) <= 8)
2270 return "addq%.l %2,%0";
2271 if (INTVAL (operands[2]) < 0
2272 && INTVAL (operands[2]) >= -8)
2274 operands[2] = GEN_INT (- INTVAL (operands[2]));
2275 return "subq%.l %2,%0";
2277 /* On the CPU32 it is faster to use two addql instructions to
2278 add a small integer (8 < N <= 16) to a register.
2279 Likewise for subql. */
2280 if (TARGET_CPU32 && REG_P (operands[0]))
2282 if (INTVAL (operands[2]) > 8
2283 && INTVAL (operands[2]) <= 16)
2285 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2286 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2288 if (INTVAL (operands[2]) < -8
2289 && INTVAL (operands[2]) >= -16)
2291 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2292 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2295 if (ADDRESS_REG_P (operands[0])
2296 && INTVAL (operands[2]) >= -0x8000
2297 && INTVAL (operands[2]) < 0x8000)
2300 return "add%.w %2,%0";
2303 return "lea (%c2,%0),%0";
2305 return "lea %0@(%c2),%0";
2309 return "add%.l %2,%0";
2312 /* Store in cc_status the expressions that the condition codes will
2313 describe after execution of an instruction whose pattern is EXP.
2314 Do not alter them if the instruction would not alter the cc's. */
2316 /* On the 68000, all the insns to store in an address register fail to
2317 set the cc's. However, in some cases these instructions can make it
2318 possibly invalid to use the saved cc's. In those cases we clear out
2319 some or all of the saved cc's so they won't be used. */
2322 notice_update_cc (exp, insn)
2326 if (GET_CODE (exp) == SET)
2328 if (GET_CODE (SET_SRC (exp)) == CALL)
2332 else if (ADDRESS_REG_P (SET_DEST (exp)))
2334 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
2335 cc_status.value1 = 0;
2336 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
2337 cc_status.value2 = 0;
2339 else if (!FP_REG_P (SET_DEST (exp))
2340 && SET_DEST (exp) != cc0_rtx
2341 && (FP_REG_P (SET_SRC (exp))
2342 || GET_CODE (SET_SRC (exp)) == FIX
2343 || GET_CODE (SET_SRC (exp)) == FLOAT_TRUNCATE
2344 || GET_CODE (SET_SRC (exp)) == FLOAT_EXTEND))
2348 /* A pair of move insns doesn't produce a useful overall cc. */
2349 else if (!FP_REG_P (SET_DEST (exp))
2350 && !FP_REG_P (SET_SRC (exp))
2351 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
2352 && (GET_CODE (SET_SRC (exp)) == REG
2353 || GET_CODE (SET_SRC (exp)) == MEM
2354 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
2358 else if (GET_CODE (SET_SRC (exp)) == CALL)
2362 else if (XEXP (exp, 0) != pc_rtx)
2364 cc_status.flags = 0;
2365 cc_status.value1 = XEXP (exp, 0);
2366 cc_status.value2 = XEXP (exp, 1);
2369 else if (GET_CODE (exp) == PARALLEL
2370 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
2372 if (ADDRESS_REG_P (XEXP (XVECEXP (exp, 0, 0), 0)))
2374 else if (XEXP (XVECEXP (exp, 0, 0), 0) != pc_rtx)
2376 cc_status.flags = 0;
2377 cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
2378 cc_status.value2 = XEXP (XVECEXP (exp, 0, 0), 1);
2383 if (cc_status.value2 != 0
2384 && ADDRESS_REG_P (cc_status.value2)
2385 && GET_MODE (cc_status.value2) == QImode)
2387 if (cc_status.value2 != 0)
2388 switch (GET_CODE (cc_status.value2))
2390 case PLUS: case MINUS: case MULT:
2391 case DIV: case UDIV: case MOD: case UMOD: case NEG:
2392 #if 0 /* These instructions always clear the overflow bit */
2393 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
2394 case ROTATE: case ROTATERT:
2396 if (GET_MODE (cc_status.value2) != VOIDmode)
2397 cc_status.flags |= CC_NO_OVERFLOW;
2400 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2401 ends with a move insn moving r2 in r2's mode.
2402 Thus, the cc's are set for r2.
2403 This can set N bit spuriously. */
2404 cc_status.flags |= CC_NOT_NEGATIVE;
2409 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
2411 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
2412 cc_status.value2 = 0;
2413 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
2414 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
2415 cc_status.flags = CC_IN_68881;
2419 output_move_const_double (operands)
2422 int code = standard_68881_constant_p (operands[1]);
2426 static char buf[40];
2428 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2431 return "fmove%.d %1,%0";
2435 output_move_const_single (operands)
2438 int code = standard_68881_constant_p (operands[1]);
2442 static char buf[40];
2444 sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
2447 return "fmove%.s %f1,%0";
2450 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2451 from the "fmovecr" instruction.
2452 The value, anded with 0xff, gives the code to use in fmovecr
2453 to get the desired constant. */
2455 /* This code has been fixed for cross-compilation. */
2457 static int inited_68881_table = 0;
2459 static const char *const strings_68881[7] = {
2469 static const int codes_68881[7] = {
2479 REAL_VALUE_TYPE values_68881[7];
2481 /* Set up values_68881 array by converting the decimal values
2482 strings_68881 to binary. */
2489 enum machine_mode mode;
2492 for (i = 0; i < 7; i++)
2496 r = REAL_VALUE_ATOF (strings_68881[i], mode);
2497 values_68881[i] = r;
2499 inited_68881_table = 1;
2503 standard_68881_constant_p (x)
2509 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
2510 used at all on those chips. */
2511 if (TARGET_68040 || TARGET_68060)
2514 if (! inited_68881_table)
2515 init_68881_table ();
2517 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2519 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
2521 for (i = 0; i < 6; i++)
2523 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
2524 return (codes_68881[i]);
2527 if (GET_MODE (x) == SFmode)
2530 if (REAL_VALUES_EQUAL (r, values_68881[6]))
2531 return (codes_68881[6]);
2533 /* larger powers of ten in the constants ram are not used
2534 because they are not equal to a `double' C constant. */
2538 /* If X is a floating-point constant, return the logarithm of X base 2,
2539 or 0 if X is not a power of 2. */
2542 floating_exact_log2 (x)
2545 REAL_VALUE_TYPE r, r1;
2548 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2550 if (REAL_VALUES_LESS (r, dconst1))
2553 exp = real_exponent (&r);
2554 real_2expN (&r1, exp);
2555 if (REAL_VALUES_EQUAL (r1, r))
2561 /* A C compound statement to output to stdio stream STREAM the
2562 assembler syntax for an instruction operand X. X is an RTL
2565 CODE is a value that can be used to specify one of several ways
2566 of printing the operand. It is used when identical operands
2567 must be printed differently depending on the context. CODE
2568 comes from the `%' specification that was used to request
2569 printing of the operand. If the specification was just `%DIGIT'
2570 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2571 is the ASCII code for LTR.
2573 If X is a register, this macro should print the register's name.
2574 The names can be found in an array `reg_names' whose type is
2575 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2577 When the machine description has a specification `%PUNCT' (a `%'
2578 followed by a punctuation character), this macro is called with
2579 a null pointer for X and the punctuation character for CODE.
2581 The m68k specific codes are:
2583 '.' for dot needed in Motorola-style opcode names.
2584 '-' for an operand pushing on the stack:
2585 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2586 '+' for an operand pushing on the stack:
2587 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2588 '@' for a reference to the top word on the stack:
2589 sp@, (sp) or (%sp) depending on the style of syntax.
2590 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2591 but & in SGS syntax).
2592 '!' for the cc register (used in an `and to cc' insn).
2593 '$' for the letter `s' in an op code, but only on the 68040.
2594 '&' for the letter `d' in an op code, but only on the 68040.
2595 '/' for register prefix needed by longlong.h.
2597 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2598 'd' to force memory addressing to be absolute, not relative.
2599 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2600 'o' for operands to go directly to output_operand_address (bypassing
2601 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
2602 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2603 or print pair of registers as rx:ry.
2608 print_operand (file, op, letter)
2609 FILE *file; /* file to write to */
2610 rtx op; /* operand to print */
2611 int letter; /* %<letter> or 0 */
2615 #if defined (MOTOROLA)
2616 fprintf (file, ".");
2619 else if (letter == '#')
2621 asm_fprintf (file, "%I");
2623 else if (letter == '-')
2626 asm_fprintf (file, "-(%Rsp)");
2628 asm_fprintf (file, "%Rsp@-");
2631 else if (letter == '+')
2634 asm_fprintf (file, "(%Rsp)+");
2636 asm_fprintf (file, "%Rsp@+");
2639 else if (letter == '@')
2642 asm_fprintf (file, "(%Rsp)");
2644 asm_fprintf (file, "%Rsp@");
2647 else if (letter == '!')
2649 asm_fprintf (file, "%Rfpcr");
2651 else if (letter == '$')
2653 if (TARGET_68040_ONLY)
2655 fprintf (file, "s");
2658 else if (letter == '&')
2660 if (TARGET_68040_ONLY)
2662 fprintf (file, "d");
2665 else if (letter == '/')
2667 asm_fprintf (file, "%R");
2669 else if (letter == 'o')
2671 /* This is only for direct addresses with TARGET_PCREL */
2672 if (GET_CODE (op) != MEM || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
2675 output_addr_const (file, XEXP (op, 0));
2677 else if (GET_CODE (op) == REG)
2680 /* Print out the second register name of a register pair.
2681 I.e., R (6) => 7. */
2682 fputs (reg_names[REGNO (op) + 1], file);
2684 fputs (reg_names[REGNO (op)], file);
2686 else if (GET_CODE (op) == MEM)
2688 output_address (XEXP (op, 0));
2689 if (letter == 'd' && ! TARGET_68020
2690 && CONSTANT_ADDRESS_P (XEXP (op, 0))
2691 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
2692 && INTVAL (XEXP (op, 0)) < 0x8000
2693 && INTVAL (XEXP (op, 0)) >= -0x8000))
2696 fprintf (file, ".l");
2698 fprintf (file, ":l");
2702 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
2705 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2706 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
2708 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
2711 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2712 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
2714 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
2717 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
2718 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
2722 /* Use `print_operand_address' instead of `output_addr_const'
2723 to ensure that we print relevant PIC stuff. */
2724 asm_fprintf (file, "%I");
2726 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
2727 print_operand_address (file, op);
2729 output_addr_const (file, op);
2734 /* A C compound statement to output to stdio stream STREAM the
2735 assembler syntax for an instruction operand that is a memory
2736 reference whose address is ADDR. ADDR is an RTL expression.
2738 Note that this contains a kludge that knows that the only reason
2739 we have an address (plus (label_ref...) (reg...)) when not generating
2740 PIC code is in the insn before a tablejump, and we know that m68k.md
2741 generates a label LInnn: on such an insn.
2743 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2744 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2746 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2747 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2748 we want. This difference can be accommodated by using an assembler
2749 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2750 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2751 macro. See m68k/sgs.h for an example; for versions without the bug.
2752 Some assemblers refuse all the above solutions. The workaround is to
2753 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2756 They also do not like things like "pea 1.w", so we simple leave off
2757 the .w on small constants.
2759 This routine is responsible for distinguishing between -fpic and -fPIC
2760 style relocations in an address. When generating -fpic code the
2761 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2762 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2764 #ifndef ASM_OUTPUT_CASE_FETCH
2767 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2768 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2770 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2771 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2774 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2775 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2777 #endif /* ASM_OUTPUT_CASE_FETCH */
2780 print_operand_address (file, addr)
2784 register rtx reg1, reg2, breg, ireg;
2787 switch (GET_CODE (addr))
2791 fprintf (file, "(%s)", reg_names[REGNO (addr)]);
2793 fprintf (file, "%s@", reg_names[REGNO (addr)]);
2798 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
2800 fprintf (file, "%s@-", reg_names[REGNO (XEXP (addr, 0))]);
2805 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
2807 fprintf (file, "%s@+", reg_names[REGNO (XEXP (addr, 0))]);
2811 reg1 = reg2 = ireg = breg = offset = 0;
2812 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)))
2814 offset = XEXP (addr, 0);
2815 addr = XEXP (addr, 1);
2817 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)))
2819 offset = XEXP (addr, 1);
2820 addr = XEXP (addr, 0);
2822 if (GET_CODE (addr) != PLUS)
2826 else if (GET_CODE (XEXP (addr, 0)) == SIGN_EXTEND)
2828 reg1 = XEXP (addr, 0);
2829 addr = XEXP (addr, 1);
2831 else if (GET_CODE (XEXP (addr, 1)) == SIGN_EXTEND)
2833 reg1 = XEXP (addr, 1);
2834 addr = XEXP (addr, 0);
2836 else if (GET_CODE (XEXP (addr, 0)) == MULT)
2838 reg1 = XEXP (addr, 0);
2839 addr = XEXP (addr, 1);
2841 else if (GET_CODE (XEXP (addr, 1)) == MULT)
2843 reg1 = XEXP (addr, 1);
2844 addr = XEXP (addr, 0);
2846 else if (GET_CODE (XEXP (addr, 0)) == REG)
2848 reg1 = XEXP (addr, 0);
2849 addr = XEXP (addr, 1);
2851 else if (GET_CODE (XEXP (addr, 1)) == REG)
2853 reg1 = XEXP (addr, 1);
2854 addr = XEXP (addr, 0);
2856 if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT
2857 || GET_CODE (addr) == SIGN_EXTEND)
2869 #if 0 /* for OLD_INDEXING */
2870 else if (GET_CODE (addr) == PLUS)
2872 if (GET_CODE (XEXP (addr, 0)) == REG)
2874 reg2 = XEXP (addr, 0);
2875 addr = XEXP (addr, 1);
2877 else if (GET_CODE (XEXP (addr, 1)) == REG)
2879 reg2 = XEXP (addr, 1);
2880 addr = XEXP (addr, 0);
2892 if ((reg1 && (GET_CODE (reg1) == SIGN_EXTEND
2893 || GET_CODE (reg1) == MULT))
2894 || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2))))
2899 else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1)))
2904 if (ireg != 0 && breg == 0 && GET_CODE (addr) == LABEL_REF
2905 && ! (flag_pic && ireg == pic_offset_table_rtx))
2908 if (GET_CODE (ireg) == MULT)
2910 scale = INTVAL (XEXP (ireg, 1));
2911 ireg = XEXP (ireg, 0);
2913 if (GET_CODE (ireg) == SIGN_EXTEND)
2915 ASM_OUTPUT_CASE_FETCH (file,
2916 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2917 reg_names[REGNO (XEXP (ireg, 0))]);
2918 fprintf (file, "w");
2922 ASM_OUTPUT_CASE_FETCH (file,
2923 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2924 reg_names[REGNO (ireg)]);
2925 fprintf (file, "l");
2930 fprintf (file, "*%d", scale);
2932 fprintf (file, ":%d", scale);
2938 if (breg != 0 && ireg == 0 && GET_CODE (addr) == LABEL_REF
2939 && ! (flag_pic && breg == pic_offset_table_rtx))
2941 ASM_OUTPUT_CASE_FETCH (file,
2942 CODE_LABEL_NUMBER (XEXP (addr, 0)),
2943 reg_names[REGNO (breg)]);
2944 fprintf (file, "l)");
2947 if (ireg != 0 || breg != 0)
2954 if (! flag_pic && addr && GET_CODE (addr) == LABEL_REF)
2961 output_addr_const (file, addr);
2962 if (flag_pic && (breg == pic_offset_table_rtx))
2964 fprintf (file, "@GOT");
2966 fprintf (file, ".w");
2969 fprintf (file, "(%s", reg_names[REGNO (breg)]);
2975 fprintf (file, "%s@(", reg_names[REGNO (breg)]);
2978 output_addr_const (file, addr);
2979 if ((flag_pic == 1) && (breg == pic_offset_table_rtx))
2980 fprintf (file, ":w");
2981 if ((flag_pic == 2) && (breg == pic_offset_table_rtx))
2982 fprintf (file, ":l");
2984 if (addr != 0 && ireg != 0)
2989 if (ireg != 0 && GET_CODE (ireg) == MULT)
2991 scale = INTVAL (XEXP (ireg, 1));
2992 ireg = XEXP (ireg, 0);
2994 if (ireg != 0 && GET_CODE (ireg) == SIGN_EXTEND)
2997 fprintf (file, "%s.w", reg_names[REGNO (XEXP (ireg, 0))]);
2999 fprintf (file, "%s:w", reg_names[REGNO (XEXP (ireg, 0))]);
3005 fprintf (file, "%s.l", reg_names[REGNO (ireg)]);
3007 fprintf (file, "%s:l", reg_names[REGNO (ireg)]);
3013 fprintf (file, "*%d", scale);
3015 fprintf (file, ":%d", scale);
3021 else if (reg1 != 0 && GET_CODE (addr) == LABEL_REF
3022 && ! (flag_pic && reg1 == pic_offset_table_rtx))
3024 ASM_OUTPUT_CASE_FETCH (file,
3025 CODE_LABEL_NUMBER (XEXP (addr, 0)),
3026 reg_names[REGNO (reg1)]);
3027 fprintf (file, "l)");
3030 /* FALL-THROUGH (is this really what we want?) */
3032 if (GET_CODE (addr) == CONST_INT
3033 && INTVAL (addr) < 0x8000
3034 && INTVAL (addr) >= -0x8000)
3038 /* Many SGS assemblers croak on size specifiers for constants. */
3039 fprintf (file, "%d", (int) INTVAL (addr));
3041 fprintf (file, "%d.w", (int) INTVAL (addr));
3044 fprintf (file, "%d:w", (int) INTVAL (addr));
3047 else if (GET_CODE (addr) == CONST_INT)
3049 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3051 else if (TARGET_PCREL)
3054 output_addr_const (file, addr);
3056 asm_fprintf (file, ":w,%Rpc)");
3058 asm_fprintf (file, ":l,%Rpc)");
3062 /* Special case for SYMBOL_REF if the symbol name ends in
3063 `.<letter>', this can be mistaken as a size suffix. Put
3064 the name in parentheses. */
3065 if (GET_CODE (addr) == SYMBOL_REF
3066 && strlen (XSTR (addr, 0)) > 2
3067 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3070 output_addr_const (file, addr);
3074 output_addr_const (file, addr);
3080 /* Check for cases where a clr insns can be omitted from code using
3081 strict_low_part sets. For example, the second clrl here is not needed:
3082 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3084 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3085 insn we are checking for redundancy. TARGET is the register set by the
3089 strict_low_part_peephole_ok (mode, first_insn, target)
3090 enum machine_mode mode;
3096 p = prev_nonnote_insn (first_insn);
3100 /* If it isn't an insn, then give up. */
3101 if (GET_CODE (p) != INSN)
3104 if (reg_set_p (target, p))
3106 rtx set = single_set (p);
3109 /* If it isn't an easy to recognize insn, then give up. */
3113 dest = SET_DEST (set);
3115 /* If this sets the entire target register to zero, then our
3116 first_insn is redundant. */
3117 if (rtx_equal_p (dest, target)
3118 && SET_SRC (set) == const0_rtx)
3120 else if (GET_CODE (dest) == STRICT_LOW_PART
3121 && GET_CODE (XEXP (dest, 0)) == REG
3122 && REGNO (XEXP (dest, 0)) == REGNO (target)
3123 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
3124 <= GET_MODE_SIZE (mode)))
3125 /* This is a strict low part set which modifies less than
3126 we are using, so it is safe. */
3132 p = prev_nonnote_insn (p);
3139 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3140 range carefully since this predicate is used in DImode contexts. Also, we
3141 need some extra crud to make it work when hosted on 64-bit machines. */
3144 const_uint32_operand (op, mode)
3146 enum machine_mode mode;
3148 /* It doesn't make sense to ask this question with a mode that is
3149 not larger than 32 bits. */
3150 if (GET_MODE_BITSIZE (mode) <= 32)
3153 #if HOST_BITS_PER_WIDE_INT > 32
3154 /* All allowed constants will fit a CONST_INT. */
3155 return (GET_CODE (op) == CONST_INT
3156 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
3158 return (GET_CODE (op) == CONST_INT
3159 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
3163 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3164 to check the range carefully since this predicate is used in DImode
3168 const_sint32_operand (op, mode)
3170 enum machine_mode mode;
3172 /* It doesn't make sense to ask this question with a mode that is
3173 not larger than 32 bits. */
3174 if (GET_MODE_BITSIZE (mode) <= 32)
3177 /* All allowed constants will fit a CONST_INT. */
3178 return (GET_CODE (op) == CONST_INT
3179 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
3182 /* Operand predicates for implementing asymmetric pc-relative addressing
3183 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
3184 when used as a source operand, but not as a destination operand.
3186 We model this by restricting the meaning of the basic predicates
3187 (general_operand, memory_operand, etc) to forbid the use of this
3188 addressing mode, and then define the following predicates that permit
3189 this addressing mode. These predicates can then be used for the
3190 source operands of the appropriate instructions.
3192 n.b. While it is theoretically possible to change all machine patterns
3193 to use this addressing more where permitted by the architecture,
3194 it has only been implemented for "common" cases: SImode, HImode, and
3195 QImode operands, and only for the principle operations that would
3196 require this addressing mode: data movement and simple integer operations.
3198 In parallel with these new predicates, two new constraint letters
3199 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
3200 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
3201 In the pcrel case 's' is only valid in combination with 'a' registers.
3202 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
3203 of how these constraints are used.
3205 The use of these predicates is strictly optional, though patterns that
3206 don't will cause an extra reload register to be allocated where one
3209 lea (abc:w,%pc),%a0 ; need to reload address
3210 moveq &1,%d1 ; since write to pc-relative space
3211 movel %d1,%a0@ ; is not allowed
3213 lea (abc:w,%pc),%a1 ; no need to reload address here
3214 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
3216 For more info, consult tiemann@cygnus.com.
3219 All of the ugliness with predicates and constraints is due to the
3220 simple fact that the m68k does not allow a pc-relative addressing
3221 mode as a destination. gcc does not distinguish between source and
3222 destination addresses. Hence, if we claim that pc-relative address
3223 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
3224 end up with invalid code. To get around this problem, we left
3225 pc-relative modes as invalid addresses, and then added special
3226 predicates and constraints to accept them.
3228 A cleaner way to handle this is to modify gcc to distinguish
3229 between source and destination addresses. We can then say that
3230 pc-relative is a valid source address but not a valid destination
3231 address, and hopefully avoid a lot of the predicate and constraint
3232 hackery. Unfortunately, this would be a pretty big change. It would
3233 be a useful change for a number of ports, but there aren't any current
3234 plans to undertake this.
3236 ***************************************************************************/
3239 /* Special case of a general operand that's used as a source operand.
3240 Use this to permit reads from PC-relative memory when -mpcrel
3244 general_src_operand (op, mode)
3246 enum machine_mode mode;
3249 && GET_CODE (op) == MEM
3250 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3251 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3252 || GET_CODE (XEXP (op, 0)) == CONST))
3254 return general_operand (op, mode);
3257 /* Special case of a nonimmediate operand that's used as a source.
3258 Use this to permit reads from PC-relative memory when -mpcrel
3262 nonimmediate_src_operand (op, mode)
3264 enum machine_mode mode;
3266 if (TARGET_PCREL && GET_CODE (op) == MEM
3267 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3268 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3269 || GET_CODE (XEXP (op, 0)) == CONST))
3271 return nonimmediate_operand (op, mode);
3274 /* Special case of a memory operand that's used as a source.
3275 Use this to permit reads from PC-relative memory when -mpcrel
3279 memory_src_operand (op, mode)
3281 enum machine_mode mode;
3283 if (TARGET_PCREL && GET_CODE (op) == MEM
3284 && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
3285 || GET_CODE (XEXP (op, 0)) == LABEL_REF
3286 || GET_CODE (XEXP (op, 0)) == CONST))
3288 return memory_operand (op, mode);
3291 /* Predicate that accepts only a pc-relative address. This is needed
3292 because pc-relative addresses don't satisfy the predicate
3293 "general_src_operand". */
3296 pcrel_address (op, mode)
3298 enum machine_mode mode ATTRIBUTE_UNUSED;
3300 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF
3301 || GET_CODE (op) == CONST);
3305 output_andsi3 (operands)
3309 if (GET_CODE (operands[2]) == CONST_INT
3310 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3311 && (DATA_REG_P (operands[0])
3312 || offsettable_memref_p (operands[0]))
3313 && !TARGET_COLDFIRE)
3315 if (GET_CODE (operands[0]) != REG)
3316 operands[0] = adjust_address (operands[0], HImode, 2);
3317 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
3318 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3320 if (operands[2] == const0_rtx)
3322 return "and%.w %2,%0";
3324 if (GET_CODE (operands[2]) == CONST_INT
3325 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3326 && (DATA_REG_P (operands[0])
3327 || offsettable_memref_p (operands[0])))
3329 if (DATA_REG_P (operands[0]))
3331 operands[1] = GEN_INT (logval);
3335 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3336 operands[1] = GEN_INT (logval % 8);
3338 /* This does not set condition codes in a standard way. */
3340 return "bclr %1,%0";
3342 return "and%.l %2,%0";
3346 output_iorsi3 (operands)
3349 register int logval;
3350 if (GET_CODE (operands[2]) == CONST_INT
3351 && INTVAL (operands[2]) >> 16 == 0
3352 && (DATA_REG_P (operands[0])
3353 || offsettable_memref_p (operands[0]))
3354 && !TARGET_COLDFIRE)
3356 if (GET_CODE (operands[0]) != REG)
3357 operands[0] = adjust_address (operands[0], HImode, 2);
3358 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3360 if (INTVAL (operands[2]) == 0xffff)
3361 return "mov%.w %2,%0";
3362 return "or%.w %2,%0";
3364 if (GET_CODE (operands[2]) == CONST_INT
3365 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3366 && (DATA_REG_P (operands[0])
3367 || offsettable_memref_p (operands[0])))
3369 if (DATA_REG_P (operands[0]))
3370 operands[1] = GEN_INT (logval);
3373 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3374 operands[1] = GEN_INT (logval % 8);
3377 return "bset %1,%0";
3379 return "or%.l %2,%0";
3383 output_xorsi3 (operands)
3386 register int logval;
3387 if (GET_CODE (operands[2]) == CONST_INT
3388 && INTVAL (operands[2]) >> 16 == 0
3389 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
3390 && !TARGET_COLDFIRE)
3392 if (! DATA_REG_P (operands[0]))
3393 operands[0] = adjust_address (operands[0], HImode, 2);
3394 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3396 if (INTVAL (operands[2]) == 0xffff)
3398 return "eor%.w %2,%0";
3400 if (GET_CODE (operands[2]) == CONST_INT
3401 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3402 && (DATA_REG_P (operands[0])
3403 || offsettable_memref_p (operands[0])))
3405 if (DATA_REG_P (operands[0]))
3406 operands[1] = GEN_INT (logval);
3409 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
3410 operands[1] = GEN_INT (logval % 8);
3413 return "bchg %1,%0";
3415 return "eor%.l %2,%0";
3418 /* Output assembly to switch to section NAME with attribute FLAGS. */
3421 m68k_coff_asm_named_section (name, flags)
3427 if (flags & SECTION_WRITE)
3432 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
3435 #ifdef CTOR_LIST_BEGIN
3437 m68k_svr3_asm_out_constructor (symbol, priority)
3439 int priority ATTRIBUTE_UNUSED;
3444 xop[0] = gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx));
3447 output_asm_insn (output_move_simode (xop), xop);
3453 m68k_hp320_internal_label (stream, prefix, labelno)
3456 unsigned long labelno;
3458 if (prefix[0] == 'L' && prefix[1] == 'I')
3459 fprintf(stream, "\tset %s%ld,.+2\n", prefix, labelno);
3461 fprintf (stream, "%s%ld:\n", prefix, labelno);
3465 m68k_hp320_file_start ()
3467 /* version 1: 68010.
3468 2: 68020 without FPU.
3469 3: 68020 with FPU. */
3470 fprintf (asm_out_file, "\tversion %d\n",
3471 TARGET_68020 ? (TARGET_68881 ? 3 : 2) : 1);
3476 m68k_output_mi_thunk (file, thunk, delta, vcall_offset, function)
3478 tree thunk ATTRIBUTE_UNUSED;
3479 HOST_WIDE_INT delta;
3480 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
3486 if (delta > 0 && delta <= 8)
3488 asm_fprintf (file, "\taddq.l %I%d,4(%Rsp)\n", (int) delta);
3490 asm_fprintf (file, "\taddql %I%d,%Rsp@(4)\n", (int) delta);
3492 else if (delta < 0 && delta >= -8)
3494 asm_fprintf (file, "\tsubq.l %I%d,4(%Rsp)\n", (int) -delta);
3496 asm_fprintf (file, "\tsubql %I%d,%Rsp@(4)\n", (int) -delta);
3500 asm_fprintf (file, "\tadd.l %I%wd,4(%Rsp)\n", delta);
3502 asm_fprintf (file, "\taddl %I%wd,%Rsp@(4)\n", delta);
3505 xops[0] = DECL_RTL (function);
3507 /* Logic taken from call patterns in m68k.md. */
3519 fmt = "bra.l %0@PLTPC";
3521 fmt = "bra %0@PLTPC";
3535 #if defined (MOTOROLA) && !defined (USE_GAS)
3542 output_asm_insn (fmt, xops);