1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
47 enum reg_class regno_reg_class[] =
49 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
50 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
51 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
52 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
53 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
54 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
59 /* The minimum number of integer registers that we want to save with the
60 movem instruction. Using two movel instructions instead of a single
61 moveml is about 15% faster for the 68020 and 68030 at no expense in
63 #define MIN_MOVEM_REGS 3
65 /* The minimum number of floating point registers that we want to save
66 with the fmovem instruction. */
67 #define MIN_FMOVEM_REGS 1
69 /* Structure describing stack frame layout. */
72 /* Stack pointer to frame pointer offset. */
75 /* Offset of FPU registers. */
76 HOST_WIDE_INT foffset;
78 /* Frame size in bytes (rounded up). */
81 /* Data and address register. */
83 unsigned int reg_mask;
87 unsigned int fpu_mask;
89 /* Offsets relative to ARG_POINTER. */
90 HOST_WIDE_INT frame_pointer_offset;
91 HOST_WIDE_INT stack_pointer_offset;
93 /* Function which the above information refers to. */
97 /* Current frame information calculated by m68k_compute_frame_layout(). */
98 static struct m68k_frame current_frame;
100 /* Structure describing an m68k address.
102 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
103 with null fields evaluating to 0. Here:
105 - BASE satisfies m68k_legitimate_base_reg_p
106 - INDEX satisfies m68k_legitimate_index_reg_p
107 - OFFSET satisfies m68k_legitimate_constant_address_p
109 INDEX is either HImode or SImode. The other fields are SImode.
111 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
112 the address is (BASE)+. */
113 struct m68k_address {
121 static bool m68k_handle_option (size_t, const char *, int);
122 static rtx find_addr_reg (rtx);
123 static const char *singlemove_string (rtx *);
124 #ifdef M68K_TARGET_COFF
125 static void m68k_coff_asm_named_section (const char *, unsigned int, tree);
126 #endif /* M68K_TARGET_COFF */
127 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree);
129 static rtx m68k_struct_value_rtx (tree, int);
130 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
131 tree args, int flags,
133 static void m68k_compute_frame_layout (void);
134 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
135 static bool m68k_ok_for_sibcall_p (tree, tree);
136 static bool m68k_rtx_costs (rtx, int, int, int *);
137 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
138 static bool m68k_return_in_memory (tree, tree);
142 /* Specify the identification number of the library being built */
143 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
145 /* Nonzero if the last compare/test insn had FP operands. The
146 sCC expanders peek at this to determine what to do for the
147 68060, which has no fsCC instructions. */
148 int m68k_last_compare_had_fp_operands;
150 /* Initialize the GCC target structure. */
152 #if INT_OP_GROUP == INT_OP_DOT_WORD
153 #undef TARGET_ASM_ALIGNED_HI_OP
154 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
157 #if INT_OP_GROUP == INT_OP_NO_DOT
158 #undef TARGET_ASM_BYTE_OP
159 #define TARGET_ASM_BYTE_OP "\tbyte\t"
160 #undef TARGET_ASM_ALIGNED_HI_OP
161 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
162 #undef TARGET_ASM_ALIGNED_SI_OP
163 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
166 #if INT_OP_GROUP == INT_OP_DC
167 #undef TARGET_ASM_BYTE_OP
168 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
169 #undef TARGET_ASM_ALIGNED_HI_OP
170 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
171 #undef TARGET_ASM_ALIGNED_SI_OP
172 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
175 #undef TARGET_ASM_UNALIGNED_HI_OP
176 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
177 #undef TARGET_ASM_UNALIGNED_SI_OP
178 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
180 #undef TARGET_ASM_OUTPUT_MI_THUNK
181 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
182 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
183 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
185 #undef TARGET_ASM_FILE_START_APP_OFF
186 #define TARGET_ASM_FILE_START_APP_OFF true
188 #undef TARGET_HANDLE_OPTION
189 #define TARGET_HANDLE_OPTION m68k_handle_option
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS m68k_rtx_costs
194 #undef TARGET_ATTRIBUTE_TABLE
195 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
197 #undef TARGET_PROMOTE_PROTOTYPES
198 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
200 #undef TARGET_STRUCT_VALUE_RTX
201 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
203 #undef TARGET_CANNOT_FORCE_CONST_MEM
204 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
206 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
207 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
209 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
210 #undef TARGET_RETURN_IN_MEMORY
211 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
214 static const struct attribute_spec m68k_attribute_table[] =
216 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
217 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
218 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
219 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
220 { NULL, 0, 0, false, false, false, NULL }
223 struct gcc_target targetm = TARGET_INITIALIZER;
225 /* Base flags for 68k ISAs. */
226 #define FL_FOR_isa_00 FL_ISA_68000
227 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
228 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
229 generated 68881 code for 68020 and 68030 targets unless explicitly told
231 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
232 | FL_BITFIELD | FL_68881)
233 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
234 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
236 /* Base flags for ColdFire ISAs. */
237 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
238 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
239 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
240 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
241 /* ISA_C is not upwardly compatible with ISA_B. */
242 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
246 /* Traditional 68000 instruction sets. */
252 /* ColdFire instruction set variants. */
260 /* Information about one of the -march, -mcpu or -mtune arguments. */
261 struct m68k_target_selection
263 /* The argument being described. */
266 /* For -mcpu, this is the device selected by the option.
267 For -mtune and -march, it is a representative device
268 for the microarchitecture or ISA respectively. */
269 enum target_device device;
271 /* The M68K_DEVICE fields associated with DEVICE. See the comment
272 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
274 enum uarch_type microarch;
279 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
280 static const struct m68k_target_selection all_devices[] =
282 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
283 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
284 #include "m68k-devices.def"
286 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
289 /* A list of all ISAs, mapping each one to a representative device.
290 Used for -march selection. */
291 static const struct m68k_target_selection all_isas[] =
293 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
294 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
295 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
296 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
297 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
298 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
299 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
300 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
302 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
304 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
305 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
307 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
310 /* A list of all microarchitectures, mapping each one to a representative
311 device. Used for -mtune selection. */
312 static const struct m68k_target_selection all_microarchs[] =
314 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
315 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
316 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
317 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
318 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
319 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
320 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
321 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
322 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
323 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
324 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
325 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
327 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
328 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
332 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
335 /* The entries associated with the -mcpu, -march and -mtune settings,
336 or null for options that have not been used. */
337 const struct m68k_target_selection *m68k_cpu_entry;
338 const struct m68k_target_selection *m68k_arch_entry;
339 const struct m68k_target_selection *m68k_tune_entry;
341 /* Which CPU we are generating code for. */
342 enum target_device m68k_cpu;
344 /* Which microarchitecture to tune for. */
345 enum uarch_type m68k_tune;
347 /* Which FPU to use. */
348 enum fpu_type m68k_fpu;
350 /* The set of FL_* flags that apply to the target processor. */
351 unsigned int m68k_cpu_flags;
353 /* Asm templates for calling or jumping to an arbitrary symbolic address,
354 or NULL if such calls or jumps are not supported. The address is held
356 const char *m68k_symbolic_call;
357 const char *m68k_symbolic_jump;
359 /* Enum variable that corresponds to m68k_symbolic_call values. */
360 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
363 /* See whether TABLE has an entry with name NAME. Return true and
364 store the entry in *ENTRY if so, otherwise return false and
365 leave *ENTRY alone. */
368 m68k_find_selection (const struct m68k_target_selection **entry,
369 const struct m68k_target_selection *table,
374 for (i = 0; table[i].name; i++)
375 if (strcmp (table[i].name, name) == 0)
383 /* Implement TARGET_HANDLE_OPTION. */
386 m68k_handle_option (size_t code, const char *arg, int value)
391 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
394 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
397 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
400 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
403 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
406 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
409 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
412 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
415 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
419 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
422 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
426 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
429 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
431 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
434 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
436 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
439 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
442 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
445 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
448 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
452 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
454 case OPT_mshared_library_id_:
455 if (value > MAX_LIBRARY_ID)
456 error ("-mshared-library-id=%s is not between 0 and %d",
457 arg, MAX_LIBRARY_ID);
459 asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
467 /* Sometimes certain combinations of command options do not make
468 sense on a particular target machine. You can define a macro
469 `OVERRIDE_OPTIONS' to take account of this. This macro, if
470 defined, is executed once just after all the command options have
473 Don't use this macro to turn on various extra optimizations for
474 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
477 override_options (void)
479 const struct m68k_target_selection *entry;
480 unsigned long target_mask;
488 -march=ARCH should generate code that runs any processor
489 implementing architecture ARCH. -mcpu=CPU should override -march
490 and should generate code that runs on processor CPU, making free
491 use of any instructions that CPU understands. -mtune=UARCH applies
492 on top of -mcpu or -march and optimizes the code for UARCH. It does
493 not change the target architecture. */
496 /* Complain if the -march setting is for a different microarchitecture,
497 or includes flags that the -mcpu setting doesn't. */
499 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
500 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
501 warning (0, "-mcpu=%s conflicts with -march=%s",
502 m68k_cpu_entry->name, m68k_arch_entry->name);
504 entry = m68k_cpu_entry;
507 entry = m68k_arch_entry;
510 entry = all_devices + TARGET_CPU_DEFAULT;
512 m68k_cpu_flags = entry->flags;
514 /* Use the architecture setting to derive default values for
518 /* ColdFire is lenient about alignment. */
519 if (!TARGET_COLDFIRE)
520 target_mask |= MASK_STRICT_ALIGNMENT;
522 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
523 target_mask |= MASK_BITFIELD;
524 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
525 target_mask |= MASK_CF_HWDIV;
526 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
527 target_mask |= MASK_HARD_FLOAT;
528 target_flags |= target_mask & ~target_flags_explicit;
530 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
531 m68k_cpu = entry->device;
533 m68k_tune = m68k_tune_entry->microarch;
534 #ifdef M68K_DEFAULT_TUNE
535 else if (!m68k_cpu_entry && !m68k_arch_entry)
536 m68k_tune = M68K_DEFAULT_TUNE;
539 m68k_tune = entry->microarch;
541 /* Set the type of FPU. */
542 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
543 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
546 /* Sanity check to ensure that msep-data and mid-sahred-library are not
547 * both specified together. Doing so simply doesn't make sense.
549 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
550 error ("cannot specify both -msep-data and -mid-shared-library");
552 /* If we're generating code for a separate A5 relative data segment,
553 * we've got to enable -fPIC as well. This might be relaxable to
554 * -fpic but it hasn't been tested properly.
556 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
559 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
560 error if the target does not support them. */
561 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
562 error ("-mpcrel -fPIC is not currently supported on selected cpu");
564 /* ??? A historic way of turning on pic, or is this intended to
565 be an embedded thing that doesn't have the same name binding
566 significance that it does on hosted ELF systems? */
567 if (TARGET_PCREL && flag_pic == 0)
572 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
574 m68k_symbolic_jump = "jra %a0";
576 else if (TARGET_ID_SHARED_LIBRARY)
577 /* All addresses must be loaded from the GOT. */
579 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
582 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
584 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
587 /* No unconditional long branch */;
588 else if (TARGET_PCREL)
589 m68k_symbolic_jump = "bra%.l %c0";
591 m68k_symbolic_jump = "bra%.l %p0";
592 /* Turn off function cse if we are doing PIC. We always want
593 function call to be done as `bsr foo@PLTPC'. */
594 /* ??? It's traditional to do this for -mpcrel too, but it isn't
595 clear how intentional that is. */
596 flag_no_function_cse = 1;
599 switch (m68k_symbolic_call_var)
601 case M68K_SYMBOLIC_CALL_JSR:
602 m68k_symbolic_call = "jsr %a0";
605 case M68K_SYMBOLIC_CALL_BSR_C:
606 m68k_symbolic_call = "bsr%.l %c0";
609 case M68K_SYMBOLIC_CALL_BSR_P:
610 m68k_symbolic_call = "bsr%.l %p0";
613 case M68K_SYMBOLIC_CALL_NONE:
614 gcc_assert (m68k_symbolic_call == NULL);
621 SUBTARGET_OVERRIDE_OPTIONS;
623 /* Setup scheduling options. */
625 m68k_sched_cpu = CPU_CF_V2;
628 m68k_sched_cpu = CPU_UNKNOWN;
629 flag_schedule_insns = 0;
630 flag_schedule_insns_after_reload = 0;
631 flag_modulo_sched = 0;
635 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
636 given argument and NAME is the argument passed to -mcpu. Return NULL
637 if -mcpu was not passed. */
640 m68k_cpp_cpu_ident (const char *prefix)
644 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
647 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
648 given argument and NAME is the name of the representative device for
649 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
652 m68k_cpp_cpu_family (const char *prefix)
656 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
659 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
660 "interrupt_handler" attribute and interrupt_thread if FUNC has an
661 "interrupt_thread" attribute. Otherwise, return
662 m68k_fk_normal_function. */
664 enum m68k_function_kind
665 m68k_get_function_kind (tree func)
669 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
671 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
673 return m68k_fk_interrupt_handler;
675 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
677 return m68k_fk_interrupt_handler;
679 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
681 return m68k_fk_interrupt_thread;
683 return m68k_fk_normal_function;
686 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
687 struct attribute_spec.handler. */
689 m68k_handle_fndecl_attribute (tree *node, tree name,
690 tree args ATTRIBUTE_UNUSED,
691 int flags ATTRIBUTE_UNUSED,
694 if (TREE_CODE (*node) != FUNCTION_DECL)
696 warning (OPT_Wattributes, "%qs attribute only applies to functions",
697 IDENTIFIER_POINTER (name));
698 *no_add_attrs = true;
701 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
703 error ("multiple interrupt attributes not allowed");
704 *no_add_attrs = true;
708 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
710 error ("interrupt_thread is available only on fido");
711 *no_add_attrs = true;
718 m68k_compute_frame_layout (void)
722 enum m68k_function_kind func_kind =
723 m68k_get_function_kind (current_function_decl);
724 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
725 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
727 /* Only compute the frame once per function.
728 Don't cache information until reload has been completed. */
729 if (current_frame.funcdef_no == current_function_funcdef_no
733 current_frame.size = (get_frame_size () + 3) & -4;
737 /* Interrupt thread does not need to save any register. */
738 if (!interrupt_thread)
739 for (regno = 0; regno < 16; regno++)
740 if (m68k_save_reg (regno, interrupt_handler))
742 mask |= 1 << (regno - D0_REG);
745 current_frame.offset = saved * 4;
746 current_frame.reg_no = saved;
747 current_frame.reg_mask = mask;
749 current_frame.foffset = 0;
751 if (TARGET_HARD_FLOAT)
753 /* Interrupt thread does not need to save any register. */
754 if (!interrupt_thread)
755 for (regno = 16; regno < 24; regno++)
756 if (m68k_save_reg (regno, interrupt_handler))
758 mask |= 1 << (regno - FP0_REG);
761 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
762 current_frame.offset += current_frame.foffset;
764 current_frame.fpu_no = saved;
765 current_frame.fpu_mask = mask;
767 /* Remember what function this frame refers to. */
768 current_frame.funcdef_no = current_function_funcdef_no;
772 m68k_initial_elimination_offset (int from, int to)
775 /* The arg pointer points 8 bytes before the start of the arguments,
776 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
777 frame pointer in most frames. */
778 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
779 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
780 return argptr_offset;
782 m68k_compute_frame_layout ();
784 gcc_assert (to == STACK_POINTER_REGNUM);
787 case ARG_POINTER_REGNUM:
788 return current_frame.offset + current_frame.size - argptr_offset;
789 case FRAME_POINTER_REGNUM:
790 return current_frame.offset + current_frame.size;
796 /* Refer to the array `regs_ever_live' to determine which registers
797 to save; `regs_ever_live[I]' is nonzero if register number I
798 is ever used in the function. This function is responsible for
799 knowing which registers should not be saved even if used.
800 Return true if we need to save REGNO. */
803 m68k_save_reg (unsigned int regno, bool interrupt_handler)
805 if (flag_pic && regno == PIC_REG)
807 if (current_function_saves_all_registers)
809 if (current_function_uses_pic_offset_table)
811 /* Reload may introduce constant pool references into a function
812 that thitherto didn't need a PIC register. Note that the test
813 above will not catch that case because we will only set
814 current_function_uses_pic_offset_table when emitting
815 the address reloads. */
816 if (current_function_uses_const_pool)
820 if (current_function_calls_eh_return)
825 unsigned int test = EH_RETURN_DATA_REGNO (i);
826 if (test == INVALID_REGNUM)
833 /* Fixed regs we never touch. */
834 if (fixed_regs[regno])
837 /* The frame pointer (if it is such) is handled specially. */
838 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
841 /* Interrupt handlers must also save call_used_regs
842 if they are live or when calling nested functions. */
843 if (interrupt_handler)
845 if (df_regs_ever_live_p (regno))
848 if (!current_function_is_leaf && call_used_regs[regno])
852 /* Never need to save registers that aren't touched. */
853 if (!df_regs_ever_live_p (regno))
856 /* Otherwise save everything that isn't call-clobbered. */
857 return !call_used_regs[regno];
860 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
861 the lowest memory address. COUNT is the number of registers to be
862 moved, with register REGNO + I being moved if bit I of MASK is set.
863 STORE_P specifies the direction of the move and ADJUST_STACK_P says
864 whether or not this is pre-decrement (if STORE_P) or post-increment
865 (if !STORE_P) operation. */
868 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
869 unsigned int count, unsigned int regno,
870 unsigned int mask, bool store_p, bool adjust_stack_p)
873 rtx body, addr, src, operands[2];
874 enum machine_mode mode;
876 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
877 mode = reg_raw_mode[regno];
882 src = plus_constant (base, (count
883 * GET_MODE_SIZE (mode)
884 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
885 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
888 for (; mask != 0; mask >>= 1, regno++)
891 addr = plus_constant (base, offset);
892 operands[!store_p] = gen_frame_mem (mode, addr);
893 operands[store_p] = gen_rtx_REG (mode, regno);
894 XVECEXP (body, 0, i++)
895 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
896 offset += GET_MODE_SIZE (mode);
898 gcc_assert (i == XVECLEN (body, 0));
900 return emit_insn (body);
903 /* Make INSN a frame-related instruction. */
906 m68k_set_frame_related (rtx insn)
911 RTX_FRAME_RELATED_P (insn) = 1;
912 body = PATTERN (insn);
913 if (GET_CODE (body) == PARALLEL)
914 for (i = 0; i < XVECLEN (body, 0); i++)
915 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
918 /* Emit RTL for the "prologue" define_expand. */
921 m68k_expand_prologue (void)
923 HOST_WIDE_INT fsize_with_regs;
924 rtx limit, src, dest, insn;
926 m68k_compute_frame_layout ();
928 /* If the stack limit is a symbol, we can check it here,
929 before actually allocating the space. */
930 if (current_function_limit_stack
931 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
933 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
934 if (!LEGITIMATE_CONSTANT_P (limit))
936 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
937 limit = gen_rtx_REG (Pmode, D0_REG);
939 emit_insn (gen_cmpsi (stack_pointer_rtx, limit));
940 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
941 cc0_rtx, const0_rtx),
945 fsize_with_regs = current_frame.size;
948 /* ColdFire's move multiple instructions do not allow pre-decrement
949 addressing. Add the size of movem saves to the initial stack
950 allocation instead. */
951 if (current_frame.reg_no >= MIN_MOVEM_REGS)
952 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
953 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
954 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
957 if (frame_pointer_needed)
959 if (fsize_with_regs == 0 && TUNE_68040)
961 /* On the 68040, two separate moves are faster than link.w 0. */
962 dest = gen_frame_mem (Pmode,
963 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
964 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
965 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
968 else if (fsize_with_regs < 0x8000 || TARGET_68020)
969 m68k_set_frame_related
970 (emit_insn (gen_link (frame_pointer_rtx,
971 GEN_INT (-4 - fsize_with_regs))));
974 m68k_set_frame_related
975 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
976 m68k_set_frame_related
977 (emit_insn (gen_addsi3 (stack_pointer_rtx,
979 GEN_INT (-fsize_with_regs))));
982 else if (fsize_with_regs != 0)
983 m68k_set_frame_related
984 (emit_insn (gen_addsi3 (stack_pointer_rtx,
986 GEN_INT (-fsize_with_regs))));
988 if (current_frame.fpu_mask)
990 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
992 m68k_set_frame_related
993 (m68k_emit_movem (stack_pointer_rtx,
994 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
995 current_frame.fpu_no, FP0_REG,
996 current_frame.fpu_mask, true, true));
1001 /* If we're using moveml to save the integer registers,
1002 the stack pointer will point to the bottom of the moveml
1003 save area. Find the stack offset of the first FP register. */
1004 if (current_frame.reg_no < MIN_MOVEM_REGS)
1007 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1008 m68k_set_frame_related
1009 (m68k_emit_movem (stack_pointer_rtx, offset,
1010 current_frame.fpu_no, FP0_REG,
1011 current_frame.fpu_mask, true, false));
1015 /* If the stack limit is not a symbol, check it here.
1016 This has the disadvantage that it may be too late... */
1017 if (current_function_limit_stack)
1019 if (REG_P (stack_limit_rtx))
1021 emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx));
1022 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1023 cc0_rtx, const0_rtx),
1026 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1027 warning (0, "stack limit expression is not supported");
1030 if (current_frame.reg_no < MIN_MOVEM_REGS)
1032 /* Store each register separately in the same order moveml does. */
1035 for (i = 16; i-- > 0; )
1036 if (current_frame.reg_mask & (1 << i))
1038 src = gen_rtx_REG (SImode, D0_REG + i);
1039 dest = gen_frame_mem (SImode,
1040 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1041 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1046 if (TARGET_COLDFIRE)
1047 /* The required register save space has already been allocated.
1048 The first register should be stored at (%sp). */
1049 m68k_set_frame_related
1050 (m68k_emit_movem (stack_pointer_rtx, 0,
1051 current_frame.reg_no, D0_REG,
1052 current_frame.reg_mask, true, false));
1054 m68k_set_frame_related
1055 (m68k_emit_movem (stack_pointer_rtx,
1056 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1057 current_frame.reg_no, D0_REG,
1058 current_frame.reg_mask, true, true));
1063 && current_function_uses_pic_offset_table)
1064 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
1067 /* Return true if a simple (return) instruction is sufficient for this
1068 instruction (i.e. if no epilogue is needed). */
1071 m68k_use_return_insn (void)
1073 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1076 m68k_compute_frame_layout ();
1077 return current_frame.offset == 0;
1080 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1081 SIBCALL_P says which.
1083 The function epilogue should not depend on the current stack pointer!
1084 It should use the frame pointer only, if there is a frame pointer.
1085 This is mandatory because of alloca; we also take advantage of it to
1086 omit stack adjustments before returning. */
1089 m68k_expand_epilogue (bool sibcall_p)
1091 HOST_WIDE_INT fsize, fsize_with_regs;
1092 bool big, restore_from_sp;
1094 m68k_compute_frame_layout ();
1096 fsize = current_frame.size;
1098 restore_from_sp = false;
1100 /* FIXME : current_function_is_leaf below is too strong.
1101 What we really need to know there is if there could be pending
1102 stack adjustment needed at that point. */
1103 restore_from_sp = (!frame_pointer_needed
1104 || (!current_function_calls_alloca
1105 && current_function_is_leaf));
1107 /* fsize_with_regs is the size we need to adjust the sp when
1108 popping the frame. */
1109 fsize_with_regs = fsize;
1110 if (TARGET_COLDFIRE && restore_from_sp)
1112 /* ColdFire's move multiple instructions do not allow post-increment
1113 addressing. Add the size of movem loads to the final deallocation
1115 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1116 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1117 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1118 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1121 if (current_frame.offset + fsize >= 0x8000
1123 && (current_frame.reg_mask || current_frame.fpu_mask))
1126 && (current_frame.reg_no >= MIN_MOVEM_REGS
1127 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1129 /* ColdFire's move multiple instructions do not support the
1130 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1131 stack-based restore. */
1132 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1133 GEN_INT (-(current_frame.offset + fsize)));
1134 emit_insn (gen_addsi3 (stack_pointer_rtx,
1135 gen_rtx_REG (Pmode, A1_REG),
1136 frame_pointer_rtx));
1137 restore_from_sp = true;
1141 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1147 if (current_frame.reg_no < MIN_MOVEM_REGS)
1149 /* Restore each register separately in the same order moveml does. */
1151 HOST_WIDE_INT offset;
1153 offset = current_frame.offset + fsize;
1154 for (i = 0; i < 16; i++)
1155 if (current_frame.reg_mask & (1 << i))
1161 /* Generate the address -OFFSET(%fp,%a1.l). */
1162 addr = gen_rtx_REG (Pmode, A1_REG);
1163 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1164 addr = plus_constant (addr, -offset);
1166 else if (restore_from_sp)
1167 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1169 addr = plus_constant (frame_pointer_rtx, -offset);
1170 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1171 gen_frame_mem (SImode, addr));
1172 offset -= GET_MODE_SIZE (SImode);
1175 else if (current_frame.reg_mask)
1178 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1179 gen_rtx_REG (Pmode, A1_REG),
1181 -(current_frame.offset + fsize),
1182 current_frame.reg_no, D0_REG,
1183 current_frame.reg_mask, false, false);
1184 else if (restore_from_sp)
1185 m68k_emit_movem (stack_pointer_rtx, 0,
1186 current_frame.reg_no, D0_REG,
1187 current_frame.reg_mask, false,
1190 m68k_emit_movem (frame_pointer_rtx,
1191 -(current_frame.offset + fsize),
1192 current_frame.reg_no, D0_REG,
1193 current_frame.reg_mask, false, false);
1196 if (current_frame.fpu_no > 0)
1199 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1200 gen_rtx_REG (Pmode, A1_REG),
1202 -(current_frame.foffset + fsize),
1203 current_frame.fpu_no, FP0_REG,
1204 current_frame.fpu_mask, false, false);
1205 else if (restore_from_sp)
1207 if (TARGET_COLDFIRE)
1211 /* If we used moveml to restore the integer registers, the
1212 stack pointer will still point to the bottom of the moveml
1213 save area. Find the stack offset of the first FP
1215 if (current_frame.reg_no < MIN_MOVEM_REGS)
1218 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1219 m68k_emit_movem (stack_pointer_rtx, offset,
1220 current_frame.fpu_no, FP0_REG,
1221 current_frame.fpu_mask, false, false);
1224 m68k_emit_movem (stack_pointer_rtx, 0,
1225 current_frame.fpu_no, FP0_REG,
1226 current_frame.fpu_mask, false, true);
1229 m68k_emit_movem (frame_pointer_rtx,
1230 -(current_frame.foffset + fsize),
1231 current_frame.fpu_no, FP0_REG,
1232 current_frame.fpu_mask, false, false);
1235 if (frame_pointer_needed)
1236 emit_insn (gen_unlink (frame_pointer_rtx));
1237 else if (fsize_with_regs)
1238 emit_insn (gen_addsi3 (stack_pointer_rtx,
1240 GEN_INT (fsize_with_regs)));
1242 if (current_function_calls_eh_return)
1243 emit_insn (gen_addsi3 (stack_pointer_rtx,
1245 EH_RETURN_STACKADJ_RTX));
1248 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1251 /* Return true if X is a valid comparison operator for the dbcc
1254 Note it rejects floating point comparison operators.
1255 (In the future we could use Fdbcc).
1257 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1260 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1262 switch (GET_CODE (x))
1264 case EQ: case NE: case GTU: case LTU:
1268 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1270 case GT: case LT: case GE: case LE:
1271 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1277 /* Return nonzero if flags are currently in the 68881 flag register. */
1279 flags_in_68881 (void)
1281 /* We could add support for these in the future */
1282 return cc_status.flags & CC_IN_68881;
1285 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1288 m68k_ok_for_sibcall_p (tree decl, tree exp)
1290 enum m68k_function_kind kind;
1292 /* We cannot use sibcalls for nested functions because we use the
1293 static chain register for indirect calls. */
1294 if (CALL_EXPR_STATIC_CHAIN (exp))
1297 kind = m68k_get_function_kind (current_function_decl);
1298 if (kind == m68k_fk_normal_function)
1299 /* We can always sibcall from a normal function, because it's
1300 undefined if it is calling an interrupt function. */
1303 /* Otherwise we can only sibcall if the function kind is known to be
1305 if (decl && m68k_get_function_kind (decl) == kind)
1311 /* Convert X to a legitimate function call memory reference and return the
1315 m68k_legitimize_call_address (rtx x)
1317 gcc_assert (MEM_P (x));
1318 if (call_operand (XEXP (x, 0), VOIDmode))
1320 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1323 /* Likewise for sibling calls. */
1326 m68k_legitimize_sibcall_address (rtx x)
1328 gcc_assert (MEM_P (x));
1329 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1332 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1333 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1336 /* Output a dbCC; jCC sequence. Note we do not handle the
1337 floating point version of this sequence (Fdbcc). We also
1338 do not handle alternative conditions when CC_NO_OVERFLOW is
1339 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1340 kick those out before we get here. */
1343 output_dbcc_and_branch (rtx *operands)
1345 switch (GET_CODE (operands[3]))
1348 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1352 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1356 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1360 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1364 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1368 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1372 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1376 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1380 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1384 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1391 /* If the decrement is to be done in SImode, then we have
1392 to compensate for the fact that dbcc decrements in HImode. */
1393 switch (GET_MODE (operands[0]))
1396 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1408 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1411 enum rtx_code op_code = GET_CODE (op);
1413 /* This does not produce a useful cc. */
1416 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1417 below. Swap the operands and change the op if these requirements
1418 are not fulfilled. */
1419 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1423 operand1 = operand2;
1425 op_code = swap_condition (op_code);
1427 loperands[0] = operand1;
1428 if (GET_CODE (operand1) == REG)
1429 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1431 loperands[1] = adjust_address (operand1, SImode, 4);
1432 if (operand2 != const0_rtx)
1434 loperands[2] = operand2;
1435 if (GET_CODE (operand2) == REG)
1436 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1438 loperands[3] = adjust_address (operand2, SImode, 4);
1440 loperands[4] = gen_label_rtx ();
1441 if (operand2 != const0_rtx)
1442 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1445 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1446 output_asm_insn ("tst%.l %0", loperands);
1448 output_asm_insn ("cmp%.w #0,%0", loperands);
1450 output_asm_insn ("jne %l4", loperands);
1452 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1453 output_asm_insn ("tst%.l %1", loperands);
1455 output_asm_insn ("cmp%.w #0,%1", loperands);
1458 loperands[5] = dest;
1463 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1464 CODE_LABEL_NUMBER (loperands[4]));
1465 output_asm_insn ("seq %5", loperands);
1469 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1470 CODE_LABEL_NUMBER (loperands[4]));
1471 output_asm_insn ("sne %5", loperands);
1475 loperands[6] = gen_label_rtx ();
1476 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1477 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1478 CODE_LABEL_NUMBER (loperands[4]));
1479 output_asm_insn ("sgt %5", loperands);
1480 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1481 CODE_LABEL_NUMBER (loperands[6]));
1485 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1486 CODE_LABEL_NUMBER (loperands[4]));
1487 output_asm_insn ("shi %5", loperands);
1491 loperands[6] = gen_label_rtx ();
1492 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1493 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1494 CODE_LABEL_NUMBER (loperands[4]));
1495 output_asm_insn ("slt %5", loperands);
1496 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1497 CODE_LABEL_NUMBER (loperands[6]));
1501 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1502 CODE_LABEL_NUMBER (loperands[4]));
1503 output_asm_insn ("scs %5", loperands);
1507 loperands[6] = gen_label_rtx ();
1508 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1509 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1510 CODE_LABEL_NUMBER (loperands[4]));
1511 output_asm_insn ("sge %5", loperands);
1512 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1513 CODE_LABEL_NUMBER (loperands[6]));
1517 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1518 CODE_LABEL_NUMBER (loperands[4]));
1519 output_asm_insn ("scc %5", loperands);
1523 loperands[6] = gen_label_rtx ();
1524 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1525 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1526 CODE_LABEL_NUMBER (loperands[4]));
1527 output_asm_insn ("sle %5", loperands);
1528 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1529 CODE_LABEL_NUMBER (loperands[6]));
1533 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1534 CODE_LABEL_NUMBER (loperands[4]));
1535 output_asm_insn ("sls %5", loperands);
1545 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1547 operands[0] = countop;
1548 operands[1] = dataop;
1550 if (GET_CODE (countop) == CONST_INT)
1552 register int count = INTVAL (countop);
1553 /* If COUNT is bigger than size of storage unit in use,
1554 advance to the containing unit of same size. */
1555 if (count > signpos)
1557 int offset = (count & ~signpos) / 8;
1558 count = count & signpos;
1559 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1561 if (count == signpos)
1562 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1564 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1566 /* These three statements used to use next_insns_test_no...
1567 but it appears that this should do the same job. */
1569 && next_insn_tests_no_inequality (insn))
1572 && next_insn_tests_no_inequality (insn))
1575 && next_insn_tests_no_inequality (insn))
1577 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1578 On some m68k variants unfortunately that's slower than btst.
1579 On 68000 and higher, that should also work for all HImode operands. */
1580 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1582 if (count == 3 && DATA_REG_P (operands[1])
1583 && next_insn_tests_no_inequality (insn))
1585 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1586 return "move%.w %1,%%ccr";
1588 if (count == 2 && DATA_REG_P (operands[1])
1589 && next_insn_tests_no_inequality (insn))
1591 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1592 return "move%.w %1,%%ccr";
1594 /* count == 1 followed by bvc/bvs and
1595 count == 0 followed by bcc/bcs are also possible, but need
1596 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1599 cc_status.flags = CC_NOT_NEGATIVE;
1601 return "btst %0,%1";
1604 /* Return true if X is a legitimate base register. STRICT_P says
1605 whether we need strict checking. */
1608 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1610 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1611 if (!strict_p && GET_CODE (x) == SUBREG)
1616 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1617 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1620 /* Return true if X is a legitimate index register. STRICT_P says
1621 whether we need strict checking. */
1624 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1626 if (!strict_p && GET_CODE (x) == SUBREG)
1631 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1632 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1635 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1636 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1637 ADDRESS if so. STRICT_P says whether we need strict checking. */
1640 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1644 /* Check for a scale factor. */
1646 if ((TARGET_68020 || TARGET_COLDFIRE)
1647 && GET_CODE (x) == MULT
1648 && GET_CODE (XEXP (x, 1)) == CONST_INT
1649 && (INTVAL (XEXP (x, 1)) == 2
1650 || INTVAL (XEXP (x, 1)) == 4
1651 || (INTVAL (XEXP (x, 1)) == 8
1652 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1654 scale = INTVAL (XEXP (x, 1));
1658 /* Check for a word extension. */
1659 if (!TARGET_COLDFIRE
1660 && GET_CODE (x) == SIGN_EXTEND
1661 && GET_MODE (XEXP (x, 0)) == HImode)
1664 if (m68k_legitimate_index_reg_p (x, strict_p))
1666 address->scale = scale;
1674 /* Return true if X is an illegitimate symbolic constant. */
1677 m68k_illegitimate_symbolic_constant_p (rtx x)
1681 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1683 split_const (x, &base, &offset);
1684 if (GET_CODE (base) == SYMBOL_REF
1685 && !offset_within_block_p (base, INTVAL (offset)))
1691 /* Return true if X is a legitimate constant address that can reach
1692 bytes in the range [X, X + REACH). STRICT_P says whether we need
1696 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1700 if (!CONSTANT_ADDRESS_P (x))
1704 && !(strict_p && TARGET_PCREL)
1705 && symbolic_operand (x, VOIDmode))
1708 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1710 split_const (x, &base, &offset);
1711 if (GET_CODE (base) == SYMBOL_REF
1712 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1719 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1720 labels will become jump tables. */
1723 m68k_jump_table_ref_p (rtx x)
1725 if (GET_CODE (x) != LABEL_REF)
1729 if (!NEXT_INSN (x) && !PREV_INSN (x))
1732 x = next_nonnote_insn (x);
1733 return x && JUMP_TABLE_DATA_P (x);
1736 /* Return true if X is a legitimate address for values of mode MODE.
1737 STRICT_P says whether strict checking is needed. If the address
1738 is valid, describe its components in *ADDRESS. */
1741 m68k_decompose_address (enum machine_mode mode, rtx x,
1742 bool strict_p, struct m68k_address *address)
1746 memset (address, 0, sizeof (*address));
1748 if (mode == BLKmode)
1751 reach = GET_MODE_SIZE (mode);
1753 /* Check for (An) (mode 2). */
1754 if (m68k_legitimate_base_reg_p (x, strict_p))
1760 /* Check for -(An) and (An)+ (modes 3 and 4). */
1761 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1762 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1764 address->code = GET_CODE (x);
1765 address->base = XEXP (x, 0);
1769 /* Check for (d16,An) (mode 5). */
1770 if (GET_CODE (x) == PLUS
1771 && GET_CODE (XEXP (x, 1)) == CONST_INT
1772 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
1773 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1775 address->base = XEXP (x, 0);
1776 address->offset = XEXP (x, 1);
1780 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1781 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1784 && GET_CODE (x) == PLUS
1785 && XEXP (x, 0) == pic_offset_table_rtx
1786 && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
1787 || GET_CODE (XEXP (x, 1)) == LABEL_REF))
1789 address->base = XEXP (x, 0);
1790 address->offset = XEXP (x, 1);
1794 /* The ColdFire FPU only accepts addressing modes 2-5. */
1795 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1798 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1799 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1800 All these modes are variations of mode 7. */
1801 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
1803 address->offset = x;
1807 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1810 ??? do_tablejump creates these addresses before placing the target
1811 label, so we have to assume that unplaced labels are jump table
1812 references. It seems unlikely that we would ever generate indexed
1813 accesses to unplaced labels in other cases. */
1814 if (GET_CODE (x) == PLUS
1815 && m68k_jump_table_ref_p (XEXP (x, 1))
1816 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1818 address->offset = XEXP (x, 1);
1822 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1823 (bd,An,Xn.SIZE*SCALE) addresses. */
1827 /* Check for a nonzero base displacement. */
1828 if (GET_CODE (x) == PLUS
1829 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
1831 address->offset = XEXP (x, 1);
1835 /* Check for a suppressed index register. */
1836 if (m68k_legitimate_base_reg_p (x, strict_p))
1842 /* Check for a suppressed base register. Do not allow this case
1843 for non-symbolic offsets as it effectively gives gcc freedom
1844 to treat data registers as base registers, which can generate
1847 && symbolic_operand (address->offset, VOIDmode)
1848 && m68k_decompose_index (x, strict_p, address))
1853 /* Check for a nonzero base displacement. */
1854 if (GET_CODE (x) == PLUS
1855 && GET_CODE (XEXP (x, 1)) == CONST_INT
1856 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
1858 address->offset = XEXP (x, 1);
1863 /* We now expect the sum of a base and an index. */
1864 if (GET_CODE (x) == PLUS)
1866 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
1867 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
1869 address->base = XEXP (x, 0);
1873 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
1874 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1876 address->base = XEXP (x, 1);
1883 /* Return true if X is a legitimate address for values of mode MODE.
1884 STRICT_P says whether strict checking is needed. */
1887 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1889 struct m68k_address address;
1891 return m68k_decompose_address (mode, x, strict_p, &address);
1894 /* Return true if X is a memory, describing its address in ADDRESS if so.
1895 Apply strict checking if called during or after reload. */
1898 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
1901 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
1902 reload_in_progress || reload_completed,
1906 /* Return true if X matches the 'Q' constraint. It must be a memory
1907 with a base address and no constant offset or index. */
1910 m68k_matches_q_p (rtx x)
1912 struct m68k_address address;
1914 return (m68k_legitimate_mem_p (x, &address)
1915 && address.code == UNKNOWN
1921 /* Return true if X matches the 'U' constraint. It must be a base address
1922 with a constant offset and no index. */
1925 m68k_matches_u_p (rtx x)
1927 struct m68k_address address;
1929 return (m68k_legitimate_mem_p (x, &address)
1930 && address.code == UNKNOWN
1936 /* Legitimize PIC addresses. If the address is already
1937 position-independent, we return ORIG. Newly generated
1938 position-independent addresses go to REG. If we need more
1939 than one register, we lose.
1941 An address is legitimized by making an indirect reference
1942 through the Global Offset Table with the name of the symbol
1945 The assembler and linker are responsible for placing the
1946 address of the symbol in the GOT. The function prologue
1947 is responsible for initializing a5 to the starting address
1950 The assembler is also responsible for translating a symbol name
1951 into a constant displacement from the start of the GOT.
1953 A quick example may make things a little clearer:
1955 When not generating PIC code to store the value 12345 into _foo
1956 we would generate the following code:
1960 When generating PIC two transformations are made. First, the compiler
1961 loads the address of foo into a register. So the first transformation makes:
1966 The code in movsi will intercept the lea instruction and call this
1967 routine which will transform the instructions into:
1969 movel a5@(_foo:w), a0
1973 That (in a nutshell) is how *all* symbol and label references are
1977 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
1982 /* First handle a simple SYMBOL_REF or LABEL_REF */
1983 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1987 pic_ref = gen_rtx_MEM (Pmode,
1988 gen_rtx_PLUS (Pmode,
1989 pic_offset_table_rtx, orig));
1990 current_function_uses_pic_offset_table = 1;
1991 MEM_READONLY_P (pic_ref) = 1;
1992 emit_move_insn (reg, pic_ref);
1995 else if (GET_CODE (orig) == CONST)
1999 /* Make sure this has not already been legitimized. */
2000 if (GET_CODE (XEXP (orig, 0)) == PLUS
2001 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2006 /* legitimize both operands of the PLUS */
2007 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2009 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2010 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2011 base == reg ? 0 : reg);
2013 if (GET_CODE (orig) == CONST_INT)
2014 return plus_constant (base, INTVAL (orig));
2015 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2016 /* Likewise, should we set special REG_NOTEs here? */
2023 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2025 /* Return the type of move that should be used for integer I. */
2028 m68k_const_method (HOST_WIDE_INT i)
2035 /* The ColdFire doesn't have byte or word operations. */
2036 /* FIXME: This may not be useful for the m68060 either. */
2037 if (!TARGET_COLDFIRE)
2039 /* if -256 < N < 256 but N is not in range for a moveq
2040 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2041 if (USE_MOVQ (i ^ 0xff))
2043 /* Likewise, try with not.w */
2044 if (USE_MOVQ (i ^ 0xffff))
2046 /* This is the only value where neg.w is useful */
2051 /* Try also with swap. */
2053 if (USE_MOVQ ((u >> 16) | (u << 16)))
2058 /* Try using MVZ/MVS with an immediate value to load constants. */
2059 if (i >= 0 && i <= 65535)
2061 if (i >= -32768 && i <= 32767)
2065 /* Otherwise, use move.l */
2069 /* Return the cost of moving constant I into a data register. */
2072 const_int_cost (HOST_WIDE_INT i)
2074 switch (m68k_const_method (i))
2077 /* Constants between -128 and 127 are cheap due to moveq. */
2085 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2095 m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
2100 /* Constant zero is super cheap due to clr instruction. */
2101 if (x == const0_rtx)
2104 *total = const_int_cost (INTVAL (x));
2114 /* Make 0.0 cheaper than other floating constants to
2115 encourage creating tstsf and tstdf insns. */
2116 if (outer_code == COMPARE
2117 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2123 /* These are vaguely right for a 68020. */
2124 /* The costs for long multiply have been adjusted to work properly
2125 in synth_mult on the 68020, relative to an average of the time
2126 for add and the time for shift, taking away a little more because
2127 sometimes move insns are needed. */
2128 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2134 : TARGET_COLDFIRE ? 3 : 13)
2139 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2140 : TARGET_COLDFIRE ? 2 : 8)
2143 (TARGET_CF_HWDIV ? 11 \
2144 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2147 /* An lea costs about three times as much as a simple add. */
2148 if (GET_MODE (x) == SImode
2149 && GET_CODE (XEXP (x, 1)) == REG
2150 && GET_CODE (XEXP (x, 0)) == MULT
2151 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2152 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2153 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2154 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2155 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2157 /* lea an@(dx:l:i),am */
2158 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2168 *total = COSTS_N_INSNS(1);
2173 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2175 if (INTVAL (XEXP (x, 1)) < 16)
2176 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2178 /* We're using clrw + swap for these cases. */
2179 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2182 *total = COSTS_N_INSNS (10); /* Worst case. */
2185 /* A shift by a big integer takes an extra instruction. */
2186 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2187 && (INTVAL (XEXP (x, 1)) == 16))
2189 *total = COSTS_N_INSNS (2); /* clrw;swap */
2192 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2193 && !(INTVAL (XEXP (x, 1)) > 0
2194 && INTVAL (XEXP (x, 1)) <= 8))
2196 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2202 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2203 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2204 && GET_MODE (x) == SImode)
2205 *total = COSTS_N_INSNS (MULW_COST);
2206 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2207 *total = COSTS_N_INSNS (MULW_COST);
2209 *total = COSTS_N_INSNS (MULL_COST);
2216 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2217 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2218 else if (TARGET_CF_HWDIV)
2219 *total = COSTS_N_INSNS (18);
2221 *total = COSTS_N_INSNS (43); /* div.l */
2229 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2233 output_move_const_into_data_reg (rtx *operands)
2237 i = INTVAL (operands[1]);
2238 switch (m68k_const_method (i))
2241 return "mvzw %1,%0";
2243 return "mvsw %1,%0";
2245 return "moveq %1,%0";
2248 operands[1] = GEN_INT (i ^ 0xff);
2249 return "moveq %1,%0\n\tnot%.b %0";
2252 operands[1] = GEN_INT (i ^ 0xffff);
2253 return "moveq %1,%0\n\tnot%.w %0";
2256 return "moveq #-128,%0\n\tneg%.w %0";
2261 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2262 return "moveq %1,%0\n\tswap %0";
2265 return "move%.l %1,%0";
2271 /* Return true if I can be handled by ISA B's mov3q instruction. */
2274 valid_mov3q_const (HOST_WIDE_INT i)
2276 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
2279 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2280 I is the value of OPERANDS[1]. */
2283 output_move_simode_const (rtx *operands)
2289 src = INTVAL (operands[1]);
2291 && (DATA_REG_P (dest) || MEM_P (dest))
2292 /* clr insns on 68000 read before writing. */
2293 && ((TARGET_68010 || TARGET_COLDFIRE)
2294 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
2296 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
2297 return "mov3q%.l %1,%0";
2298 else if (src == 0 && ADDRESS_REG_P (dest))
2299 return "sub%.l %0,%0";
2300 else if (DATA_REG_P (dest))
2301 return output_move_const_into_data_reg (operands);
2302 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
2304 if (valid_mov3q_const (src))
2305 return "mov3q%.l %1,%0";
2306 return "move%.w %1,%0";
2308 else if (MEM_P (dest)
2309 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
2310 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
2311 && IN_RANGE (src, -0x8000, 0x7fff))
2313 if (valid_mov3q_const (src))
2314 return "mov3q%.l %1,%-";
2317 return "move%.l %1,%0";
2321 output_move_simode (rtx *operands)
2323 if (GET_CODE (operands[1]) == CONST_INT)
2324 return output_move_simode_const (operands);
2325 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2326 || GET_CODE (operands[1]) == CONST)
2327 && push_operand (operands[0], SImode))
2329 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2330 || GET_CODE (operands[1]) == CONST)
2331 && ADDRESS_REG_P (operands[0]))
2332 return "lea %a1,%0";
2333 return "move%.l %1,%0";
2337 output_move_himode (rtx *operands)
2339 if (GET_CODE (operands[1]) == CONST_INT)
2341 if (operands[1] == const0_rtx
2342 && (DATA_REG_P (operands[0])
2343 || GET_CODE (operands[0]) == MEM)
2344 /* clr insns on 68000 read before writing. */
2345 && ((TARGET_68010 || TARGET_COLDFIRE)
2346 || !(GET_CODE (operands[0]) == MEM
2347 && MEM_VOLATILE_P (operands[0]))))
2349 else if (operands[1] == const0_rtx
2350 && ADDRESS_REG_P (operands[0]))
2351 return "sub%.l %0,%0";
2352 else if (DATA_REG_P (operands[0])
2353 && INTVAL (operands[1]) < 128
2354 && INTVAL (operands[1]) >= -128)
2355 return "moveq %1,%0";
2356 else if (INTVAL (operands[1]) < 0x8000
2357 && INTVAL (operands[1]) >= -0x8000)
2358 return "move%.w %1,%0";
2360 else if (CONSTANT_P (operands[1]))
2361 return "move%.l %1,%0";
2362 /* Recognize the insn before a tablejump, one that refers
2363 to a table of offsets. Such an insn will need to refer
2364 to a label on the insn. So output one. Use the label-number
2365 of the table of offsets to generate this label. This code,
2366 and similar code below, assumes that there will be at most one
2367 reference to each table. */
2368 if (GET_CODE (operands[1]) == MEM
2369 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2370 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
2371 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
2373 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
2375 asm_fprintf (asm_out_file, "\t.set %LLI%d,.+2\n",
2376 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
2378 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
2379 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
2381 return "move%.w %1,%0";
2385 output_move_qimode (rtx *operands)
2387 /* 68k family always modifies the stack pointer by at least 2, even for
2388 byte pushes. The 5200 (ColdFire) does not do this. */
2390 /* This case is generated by pushqi1 pattern now. */
2391 gcc_assert (!(GET_CODE (operands[0]) == MEM
2392 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
2393 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
2394 && ! ADDRESS_REG_P (operands[1])
2395 && ! TARGET_COLDFIRE));
2397 /* clr and st insns on 68000 read before writing. */
2398 if (!ADDRESS_REG_P (operands[0])
2399 && ((TARGET_68010 || TARGET_COLDFIRE)
2400 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2402 if (operands[1] == const0_rtx)
2404 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
2405 && GET_CODE (operands[1]) == CONST_INT
2406 && (INTVAL (operands[1]) & 255) == 255)
2412 if (GET_CODE (operands[1]) == CONST_INT
2413 && DATA_REG_P (operands[0])
2414 && INTVAL (operands[1]) < 128
2415 && INTVAL (operands[1]) >= -128)
2416 return "moveq %1,%0";
2417 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
2418 return "sub%.l %0,%0";
2419 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
2420 return "move%.l %1,%0";
2421 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2422 from address registers. */
2423 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
2424 return "move%.w %1,%0";
2425 return "move%.b %1,%0";
2429 output_move_stricthi (rtx *operands)
2431 if (operands[1] == const0_rtx
2432 /* clr insns on 68000 read before writing. */
2433 && ((TARGET_68010 || TARGET_COLDFIRE)
2434 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2436 return "move%.w %1,%0";
2440 output_move_strictqi (rtx *operands)
2442 if (operands[1] == const0_rtx
2443 /* clr insns on 68000 read before writing. */
2444 && ((TARGET_68010 || TARGET_COLDFIRE)
2445 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2447 return "move%.b %1,%0";
2450 /* Return the best assembler insn template
2451 for moving operands[1] into operands[0] as a fullword. */
2454 singlemove_string (rtx *operands)
2456 if (GET_CODE (operands[1]) == CONST_INT)
2457 return output_move_simode_const (operands);
2458 return "move%.l %1,%0";
2462 /* Output assembler or rtl code to perform a doubleword move insn
2463 with operands OPERANDS.
2464 Pointers to 3 helper functions should be specified:
2465 HANDLE_REG_ADJUST to adjust a register by a small value,
2466 HANDLE_COMPADR to compute an address and
2467 HANDLE_MOVSI to move 4 bytes. */
2470 handle_move_double (rtx operands[2],
2471 void (*handle_reg_adjust) (rtx, int),
2472 void (*handle_compadr) (rtx [2]),
2473 void (*handle_movsi) (rtx [2]))
2477 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
2482 rtx addreg0 = 0, addreg1 = 0;
2483 int dest_overlapped_low = 0;
2484 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2489 /* First classify both operands. */
2491 if (REG_P (operands[0]))
2493 else if (offsettable_memref_p (operands[0]))
2495 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2497 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2499 else if (GET_CODE (operands[0]) == MEM)
2504 if (REG_P (operands[1]))
2506 else if (CONSTANT_P (operands[1]))
2508 else if (offsettable_memref_p (operands[1]))
2510 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2512 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2514 else if (GET_CODE (operands[1]) == MEM)
2519 /* Check for the cases that the operand constraints are not supposed
2520 to allow to happen. Generating code for these cases is
2522 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
2524 /* If one operand is decrementing and one is incrementing
2525 decrement the former register explicitly
2526 and change that operand into ordinary indexing. */
2528 if (optype0 == PUSHOP && optype1 == POPOP)
2530 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2532 handle_reg_adjust (operands[0], -size);
2534 if (GET_MODE (operands[1]) == XFmode)
2535 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2536 else if (GET_MODE (operands[0]) == DFmode)
2537 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2539 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2542 if (optype0 == POPOP && optype1 == PUSHOP)
2544 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2546 handle_reg_adjust (operands[1], -size);
2548 if (GET_MODE (operands[1]) == XFmode)
2549 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2550 else if (GET_MODE (operands[1]) == DFmode)
2551 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2553 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2557 /* If an operand is an unoffsettable memory ref, find a register
2558 we can increment temporarily to make it refer to the second word. */
2560 if (optype0 == MEMOP)
2561 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2563 if (optype1 == MEMOP)
2564 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2566 /* Ok, we can do one word at a time.
2567 Normally we do the low-numbered word first,
2568 but if either operand is autodecrementing then we
2569 do the high-numbered word first.
2571 In either case, set up in LATEHALF the operands to use
2572 for the high-numbered word and in some cases alter the
2573 operands in OPERANDS to be suitable for the low-numbered word. */
2577 if (optype0 == REGOP)
2579 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2580 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2582 else if (optype0 == OFFSOP)
2584 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2585 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2589 middlehalf[0] = adjust_address (operands[0], SImode, 0);
2590 latehalf[0] = adjust_address (operands[0], SImode, 0);
2593 if (optype1 == REGOP)
2595 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2596 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2598 else if (optype1 == OFFSOP)
2600 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2601 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2603 else if (optype1 == CNSTOP)
2605 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2610 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2611 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2612 operands[1] = GEN_INT (l[0]);
2613 middlehalf[1] = GEN_INT (l[1]);
2614 latehalf[1] = GEN_INT (l[2]);
2618 /* No non-CONST_DOUBLE constant should ever appear
2620 gcc_assert (!CONSTANT_P (operands[1]));
2625 middlehalf[1] = adjust_address (operands[1], SImode, 0);
2626 latehalf[1] = adjust_address (operands[1], SImode, 0);
2630 /* size is not 12: */
2632 if (optype0 == REGOP)
2633 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2634 else if (optype0 == OFFSOP)
2635 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2637 latehalf[0] = adjust_address (operands[0], SImode, 0);
2639 if (optype1 == REGOP)
2640 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2641 else if (optype1 == OFFSOP)
2642 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2643 else if (optype1 == CNSTOP)
2644 split_double (operands[1], &operands[1], &latehalf[1]);
2646 latehalf[1] = adjust_address (operands[1], SImode, 0);
2649 /* If insn is effectively movd N(sp),-(sp) then we will do the
2650 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2651 for the low word as well, to compensate for the first decrement of sp. */
2652 if (optype0 == PUSHOP
2653 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2654 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2655 operands[1] = middlehalf[1] = latehalf[1];
2657 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2658 if the upper part of reg N does not appear in the MEM, arrange to
2659 emit the move late-half first. Otherwise, compute the MEM address
2660 into the upper part of N and use that as a pointer to the memory
2662 if (optype0 == REGOP
2663 && (optype1 == OFFSOP || optype1 == MEMOP))
2665 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2667 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2668 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2670 /* If both halves of dest are used in the src memory address,
2671 compute the address into latehalf of dest.
2672 Note that this can't happen if the dest is two data regs. */
2674 xops[0] = latehalf[0];
2675 xops[1] = XEXP (operands[1], 0);
2677 handle_compadr (xops);
2678 if (GET_MODE (operands[1]) == XFmode)
2680 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2681 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2682 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2686 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2687 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2691 && reg_overlap_mentioned_p (middlehalf[0],
2692 XEXP (operands[1], 0)))
2694 /* Check for two regs used by both source and dest.
2695 Note that this can't happen if the dest is all data regs.
2696 It can happen if the dest is d6, d7, a0.
2697 But in that case, latehalf is an addr reg, so
2698 the code at compadr does ok. */
2700 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2701 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2704 /* JRV says this can't happen: */
2705 gcc_assert (!addreg0 && !addreg1);
2707 /* Only the middle reg conflicts; simply put it last. */
2708 handle_movsi (operands);
2709 handle_movsi (latehalf);
2710 handle_movsi (middlehalf);
2714 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2715 /* If the low half of dest is mentioned in the source memory
2716 address, the arrange to emit the move late half first. */
2717 dest_overlapped_low = 1;
2720 /* If one or both operands autodecrementing,
2721 do the two words, high-numbered first. */
2723 /* Likewise, the first move would clobber the source of the second one,
2724 do them in the other order. This happens only for registers;
2725 such overlap can't happen in memory unless the user explicitly
2726 sets it up, and that is an undefined circumstance. */
2728 if (optype0 == PUSHOP || optype1 == PUSHOP
2729 || (optype0 == REGOP && optype1 == REGOP
2730 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2731 || REGNO (operands[0]) == REGNO (latehalf[1])))
2732 || dest_overlapped_low)
2734 /* Make any unoffsettable addresses point at high-numbered word. */
2736 handle_reg_adjust (addreg0, size - 4);
2738 handle_reg_adjust (addreg1, size - 4);
2741 handle_movsi (latehalf);
2743 /* Undo the adds we just did. */
2745 handle_reg_adjust (addreg0, -4);
2747 handle_reg_adjust (addreg1, -4);
2751 handle_movsi (middlehalf);
2754 handle_reg_adjust (addreg0, -4);
2756 handle_reg_adjust (addreg1, -4);
2759 /* Do low-numbered word. */
2761 handle_movsi (operands);
2765 /* Normal case: do the two words, low-numbered first. */
2767 handle_movsi (operands);
2769 /* Do the middle one of the three words for long double */
2773 handle_reg_adjust (addreg0, 4);
2775 handle_reg_adjust (addreg1, 4);
2777 handle_movsi (middlehalf);
2780 /* Make any unoffsettable addresses point at high-numbered word. */
2782 handle_reg_adjust (addreg0, 4);
2784 handle_reg_adjust (addreg1, 4);
2787 handle_movsi (latehalf);
2789 /* Undo the adds we just did. */
2791 handle_reg_adjust (addreg0, -(size - 4));
2793 handle_reg_adjust (addreg1, -(size - 4));
2798 /* Output assembler code to adjust REG by N. */
2800 output_reg_adjust (rtx reg, int n)
2804 gcc_assert (GET_MODE (reg) == SImode
2805 && -12 <= n && n != 0 && n <= 12);
2810 s = "add%.l #12,%0";
2814 s = "addq%.l #8,%0";
2818 s = "addq%.l #4,%0";
2822 s = "sub%.l #12,%0";
2826 s = "subq%.l #8,%0";
2830 s = "subq%.l #4,%0";
2838 output_asm_insn (s, ®);
2841 /* Emit rtl code to adjust REG by N. */
2843 emit_reg_adjust (rtx reg1, int n)
2847 gcc_assert (GET_MODE (reg1) == SImode
2848 && -12 <= n && n != 0 && n <= 12);
2850 reg1 = copy_rtx (reg1);
2851 reg2 = copy_rtx (reg1);
2854 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
2856 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
2861 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
2863 output_compadr (rtx operands[2])
2865 output_asm_insn ("lea %a1,%0", operands);
2868 /* Output the best assembler insn for moving operands[1] into operands[0]
2871 output_movsi (rtx operands[2])
2873 output_asm_insn (singlemove_string (operands), operands);
2876 /* Copy OP and change its mode to MODE. */
2878 copy_operand (rtx op, enum machine_mode mode)
2880 /* ??? This looks really ugly. There must be a better way
2881 to change a mode on the operand. */
2882 if (GET_MODE (op) != VOIDmode)
2885 op = gen_rtx_REG (mode, REGNO (op));
2889 PUT_MODE (op, mode);
2896 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
2898 emit_movsi (rtx operands[2])
2900 operands[0] = copy_operand (operands[0], SImode);
2901 operands[1] = copy_operand (operands[1], SImode);
2903 emit_insn (gen_movsi (operands[0], operands[1]));
2906 /* Output assembler code to perform a doubleword move insn
2907 with operands OPERANDS. */
2909 output_move_double (rtx *operands)
2911 handle_move_double (operands,
2912 output_reg_adjust, output_compadr, output_movsi);
2917 /* Output rtl code to perform a doubleword move insn
2918 with operands OPERANDS. */
2920 m68k_emit_move_double (rtx operands[2])
2922 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
2925 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2926 new rtx with the correct mode. */
2929 force_mode (enum machine_mode mode, rtx orig)
2931 if (mode == GET_MODE (orig))
2934 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
2937 return gen_rtx_REG (mode, REGNO (orig));
2941 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2943 return reg_renumber && FP_REG_P (op);
2946 /* Emit insns to move operands[1] into operands[0].
2948 Return 1 if we have written out everything that needs to be done to
2949 do the move. Otherwise, return 0 and the caller will emit the move
2952 Note SCRATCH_REG may not be in the proper mode depending on how it
2953 will be used. This routine is responsible for creating a new copy
2954 of SCRATCH_REG in the proper mode. */
2957 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
2959 register rtx operand0 = operands[0];
2960 register rtx operand1 = operands[1];
2964 && reload_in_progress && GET_CODE (operand0) == REG
2965 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2966 operand0 = reg_equiv_mem[REGNO (operand0)];
2967 else if (scratch_reg
2968 && reload_in_progress && GET_CODE (operand0) == SUBREG
2969 && GET_CODE (SUBREG_REG (operand0)) == REG
2970 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
2972 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2973 the code which tracks sets/uses for delete_output_reload. */
2974 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
2975 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
2976 SUBREG_BYTE (operand0));
2977 operand0 = alter_subreg (&temp);
2981 && reload_in_progress && GET_CODE (operand1) == REG
2982 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
2983 operand1 = reg_equiv_mem[REGNO (operand1)];
2984 else if (scratch_reg
2985 && reload_in_progress && GET_CODE (operand1) == SUBREG
2986 && GET_CODE (SUBREG_REG (operand1)) == REG
2987 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
2989 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2990 the code which tracks sets/uses for delete_output_reload. */
2991 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
2992 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
2993 SUBREG_BYTE (operand1));
2994 operand1 = alter_subreg (&temp);
2997 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
2998 && ((tem = find_replacement (&XEXP (operand0, 0)))
2999 != XEXP (operand0, 0)))
3000 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3001 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3002 && ((tem = find_replacement (&XEXP (operand1, 0)))
3003 != XEXP (operand1, 0)))
3004 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3006 /* Handle secondary reloads for loads/stores of FP registers where
3007 the address is symbolic by using the scratch register */
3008 if (fp_reg_operand (operand0, mode)
3009 && ((GET_CODE (operand1) == MEM
3010 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3011 || ((GET_CODE (operand1) == SUBREG
3012 && GET_CODE (XEXP (operand1, 0)) == MEM
3013 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3016 if (GET_CODE (operand1) == SUBREG)
3017 operand1 = XEXP (operand1, 0);
3019 /* SCRATCH_REG will hold an address. We want
3020 it in SImode regardless of what mode it was originally given
3022 scratch_reg = force_mode (SImode, scratch_reg);
3024 /* D might not fit in 14 bits either; for such cases load D into
3026 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3028 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3029 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3031 XEXP (XEXP (operand1, 0), 0),
3035 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3036 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3037 gen_rtx_MEM (mode, scratch_reg)));
3040 else if (fp_reg_operand (operand1, mode)
3041 && ((GET_CODE (operand0) == MEM
3042 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3043 || ((GET_CODE (operand0) == SUBREG)
3044 && GET_CODE (XEXP (operand0, 0)) == MEM
3045 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3048 if (GET_CODE (operand0) == SUBREG)
3049 operand0 = XEXP (operand0, 0);
3051 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3052 it in SIMODE regardless of what mode it was originally given
3054 scratch_reg = force_mode (SImode, scratch_reg);
3056 /* D might not fit in 14 bits either; for such cases load D into
3058 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3060 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3061 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3064 XEXP (XEXP (operand0, 0),
3069 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3070 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3074 /* Handle secondary reloads for loads of FP registers from constant
3075 expressions by forcing the constant into memory.
3077 use scratch_reg to hold the address of the memory location.
3079 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3080 NO_REGS when presented with a const_int and an register class
3081 containing only FP registers. Doing so unfortunately creates
3082 more problems than it solves. Fix this for 2.5. */
3083 else if (fp_reg_operand (operand0, mode)
3084 && CONSTANT_P (operand1)
3089 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3090 it in SIMODE regardless of what mode it was originally given
3092 scratch_reg = force_mode (SImode, scratch_reg);
3094 /* Force the constant into memory and put the address of the
3095 memory location into scratch_reg. */
3096 xoperands[0] = scratch_reg;
3097 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3098 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3100 /* Now load the destination register. */
3101 emit_insn (gen_rtx_SET (mode, operand0,
3102 gen_rtx_MEM (mode, scratch_reg)));
3106 /* Now have insn-emit do whatever it normally does. */
3110 /* Split one or more DImode RTL references into pairs of SImode
3111 references. The RTL can be REG, offsettable MEM, integer constant, or
3112 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3113 split and "num" is its length. lo_half and hi_half are output arrays
3114 that parallel "operands". */
3117 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3121 rtx op = operands[num];
3123 /* simplify_subreg refuses to split volatile memory addresses,
3124 but we still have to handle it. */
3125 if (GET_CODE (op) == MEM)
3127 lo_half[num] = adjust_address (op, SImode, 4);
3128 hi_half[num] = adjust_address (op, SImode, 0);
3132 lo_half[num] = simplify_gen_subreg (SImode, op,
3133 GET_MODE (op) == VOIDmode
3134 ? DImode : GET_MODE (op), 4);
3135 hi_half[num] = simplify_gen_subreg (SImode, op,
3136 GET_MODE (op) == VOIDmode
3137 ? DImode : GET_MODE (op), 0);
3142 /* Split X into a base and a constant offset, storing them in *BASE
3143 and *OFFSET respectively. */
3146 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3149 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3151 *offset += INTVAL (XEXP (x, 1));
3157 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3158 instruction. STORE_P says whether the move is a load or store.
3160 If the instruction uses post-increment or pre-decrement addressing,
3161 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3162 adjustment. This adjustment will be made by the first element of
3163 PARALLEL, with the loads or stores starting at element 1. If the
3164 instruction does not use post-increment or pre-decrement addressing,
3165 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3166 start at element 0. */
3169 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3170 HOST_WIDE_INT automod_offset, bool store_p)
3172 rtx base, mem_base, set, mem, reg, last_reg;
3173 HOST_WIDE_INT offset, mem_offset;
3175 enum reg_class rclass;
3177 len = XVECLEN (pattern, 0);
3178 first = (automod_base != NULL);
3182 /* Stores must be pre-decrement and loads must be post-increment. */
3183 if (store_p != (automod_offset < 0))
3186 /* Work out the base and offset for lowest memory location. */
3187 base = automod_base;
3188 offset = (automod_offset < 0 ? automod_offset : 0);
3192 /* Allow any valid base and offset in the first access. */
3199 for (i = first; i < len; i++)
3201 /* We need a plain SET. */
3202 set = XVECEXP (pattern, 0, i);
3203 if (GET_CODE (set) != SET)
3206 /* Check that we have a memory location... */
3207 mem = XEXP (set, !store_p);
3208 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3211 /* ...with the right address. */
3214 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3215 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3216 There are no mode restrictions for 680x0 besides the
3217 automodification rules enforced above. */
3219 && !m68k_legitimate_base_reg_p (base, reload_completed))
3224 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3225 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3229 /* Check that we have a register of the required mode and class. */
3230 reg = XEXP (set, store_p);
3232 || !HARD_REGISTER_P (reg)
3233 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3238 /* The register must belong to RCLASS and have a higher number
3239 than the register in the previous SET. */
3240 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3241 || REGNO (last_reg) >= REGNO (reg))
3246 /* Work out which register class we need. */
3247 if (INT_REGNO_P (REGNO (reg)))
3248 rclass = GENERAL_REGS;
3249 else if (FP_REGNO_P (REGNO (reg)))
3256 offset += GET_MODE_SIZE (GET_MODE (reg));
3259 /* If we have an automodification, check whether the final offset is OK. */
3260 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3263 /* Reject unprofitable cases. */
3264 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3270 /* Return the assembly code template for a movem or fmovem instruction
3271 whose pattern is given by PATTERN. Store the template's operands
3274 If the instruction uses post-increment or pre-decrement addressing,
3275 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3276 is true if this is a store instruction. */
3279 m68k_output_movem (rtx *operands, rtx pattern,
3280 HOST_WIDE_INT automod_offset, bool store_p)
3285 gcc_assert (GET_CODE (pattern) == PARALLEL);
3287 first = (automod_offset != 0);
3288 for (i = first; i < XVECLEN (pattern, 0); i++)
3290 /* When using movem with pre-decrement addressing, register X + D0_REG
3291 is controlled by bit 15 - X. For all other addressing modes,
3292 register X + D0_REG is controlled by bit X. Confusingly, the
3293 register mask for fmovem is in the opposite order to that for
3297 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
3298 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
3299 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
3300 if (automod_offset < 0)
3302 if (FP_REGNO_P (regno))
3303 mask |= 1 << (regno - FP0_REG);
3305 mask |= 1 << (15 - (regno - D0_REG));
3309 if (FP_REGNO_P (regno))
3310 mask |= 1 << (7 - (regno - FP0_REG));
3312 mask |= 1 << (regno - D0_REG);
3317 if (automod_offset == 0)
3318 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
3319 else if (automod_offset < 0)
3320 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3322 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3323 operands[1] = GEN_INT (mask);
3324 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
3327 return MOTOROLA ? "fmovm %1,%a0" : "fmovem %1,%a0";
3329 return MOTOROLA ? "fmovm %a0,%1" : "fmovem %a0,%1";
3334 return MOTOROLA ? "movm.l %1,%a0" : "moveml %1,%a0";
3336 return MOTOROLA ? "movm.l %a0,%1" : "moveml %a0,%1";
3340 /* Return a REG that occurs in ADDR with coefficient 1.
3341 ADDR can be effectively incremented by incrementing REG. */
3344 find_addr_reg (rtx addr)
3346 while (GET_CODE (addr) == PLUS)
3348 if (GET_CODE (XEXP (addr, 0)) == REG)
3349 addr = XEXP (addr, 0);
3350 else if (GET_CODE (XEXP (addr, 1)) == REG)
3351 addr = XEXP (addr, 1);
3352 else if (CONSTANT_P (XEXP (addr, 0)))
3353 addr = XEXP (addr, 1);
3354 else if (CONSTANT_P (XEXP (addr, 1)))
3355 addr = XEXP (addr, 0);
3359 gcc_assert (GET_CODE (addr) == REG);
3363 /* Output assembler code to perform a 32-bit 3-operand add. */
3366 output_addsi3 (rtx *operands)
3368 if (! operands_match_p (operands[0], operands[1]))
3370 if (!ADDRESS_REG_P (operands[1]))
3372 rtx tmp = operands[1];
3374 operands[1] = operands[2];
3378 /* These insns can result from reloads to access
3379 stack slots over 64k from the frame pointer. */
3380 if (GET_CODE (operands[2]) == CONST_INT
3381 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
3382 return "move%.l %2,%0\n\tadd%.l %1,%0";
3383 if (GET_CODE (operands[2]) == REG)
3384 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3385 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3387 if (GET_CODE (operands[2]) == CONST_INT)
3389 if (INTVAL (operands[2]) > 0
3390 && INTVAL (operands[2]) <= 8)
3391 return "addq%.l %2,%0";
3392 if (INTVAL (operands[2]) < 0
3393 && INTVAL (operands[2]) >= -8)
3395 operands[2] = GEN_INT (- INTVAL (operands[2]));
3396 return "subq%.l %2,%0";
3398 /* On the CPU32 it is faster to use two addql instructions to
3399 add a small integer (8 < N <= 16) to a register.
3400 Likewise for subql. */
3401 if (TUNE_CPU32 && REG_P (operands[0]))
3403 if (INTVAL (operands[2]) > 8
3404 && INTVAL (operands[2]) <= 16)
3406 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
3407 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3409 if (INTVAL (operands[2]) < -8
3410 && INTVAL (operands[2]) >= -16)
3412 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
3413 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3416 if (ADDRESS_REG_P (operands[0])
3417 && INTVAL (operands[2]) >= -0x8000
3418 && INTVAL (operands[2]) < 0x8000)
3421 return "add%.w %2,%0";
3423 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3426 return "add%.l %2,%0";
3429 /* Store in cc_status the expressions that the condition codes will
3430 describe after execution of an instruction whose pattern is EXP.
3431 Do not alter them if the instruction would not alter the cc's. */
3433 /* On the 68000, all the insns to store in an address register fail to
3434 set the cc's. However, in some cases these instructions can make it
3435 possibly invalid to use the saved cc's. In those cases we clear out
3436 some or all of the saved cc's so they won't be used. */
3439 notice_update_cc (rtx exp, rtx insn)
3441 if (GET_CODE (exp) == SET)
3443 if (GET_CODE (SET_SRC (exp)) == CALL)
3445 else if (ADDRESS_REG_P (SET_DEST (exp)))
3447 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
3448 cc_status.value1 = 0;
3449 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
3450 cc_status.value2 = 0;
3452 /* fmoves to memory or data registers do not set the condition
3453 codes. Normal moves _do_ set the condition codes, but not in
3454 a way that is appropriate for comparison with 0, because -0.0
3455 would be treated as a negative nonzero number. Note that it
3456 isn't appropriate to conditionalize this restriction on
3457 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3458 we care about the difference between -0.0 and +0.0. */
3459 else if (!FP_REG_P (SET_DEST (exp))
3460 && SET_DEST (exp) != cc0_rtx
3461 && (FP_REG_P (SET_SRC (exp))
3462 || GET_CODE (SET_SRC (exp)) == FIX
3463 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
3465 /* A pair of move insns doesn't produce a useful overall cc. */
3466 else if (!FP_REG_P (SET_DEST (exp))
3467 && !FP_REG_P (SET_SRC (exp))
3468 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
3469 && (GET_CODE (SET_SRC (exp)) == REG
3470 || GET_CODE (SET_SRC (exp)) == MEM
3471 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
3473 else if (SET_DEST (exp) != pc_rtx)
3475 cc_status.flags = 0;
3476 cc_status.value1 = SET_DEST (exp);
3477 cc_status.value2 = SET_SRC (exp);
3480 else if (GET_CODE (exp) == PARALLEL
3481 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3483 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
3484 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
3486 if (ADDRESS_REG_P (dest))
3488 else if (dest != pc_rtx)
3490 cc_status.flags = 0;
3491 cc_status.value1 = dest;
3492 cc_status.value2 = src;
3497 if (cc_status.value2 != 0
3498 && ADDRESS_REG_P (cc_status.value2)
3499 && GET_MODE (cc_status.value2) == QImode)
3501 if (cc_status.value2 != 0)
3502 switch (GET_CODE (cc_status.value2))
3504 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
3505 case ROTATE: case ROTATERT:
3506 /* These instructions always clear the overflow bit, and set
3507 the carry to the bit shifted out. */
3508 /* ??? We don't currently have a way to signal carry not valid,
3509 nor do we check for it in the branch insns. */
3513 case PLUS: case MINUS: case MULT:
3514 case DIV: case UDIV: case MOD: case UMOD: case NEG:
3515 if (GET_MODE (cc_status.value2) != VOIDmode)
3516 cc_status.flags |= CC_NO_OVERFLOW;
3519 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3520 ends with a move insn moving r2 in r2's mode.
3521 Thus, the cc's are set for r2.
3522 This can set N bit spuriously. */
3523 cc_status.flags |= CC_NOT_NEGATIVE;
3528 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
3530 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
3531 cc_status.value2 = 0;
3532 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
3533 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
3534 cc_status.flags = CC_IN_68881;
3538 output_move_const_double (rtx *operands)
3540 int code = standard_68881_constant_p (operands[1]);
3544 static char buf[40];
3546 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3549 return "fmove%.d %1,%0";
3553 output_move_const_single (rtx *operands)
3555 int code = standard_68881_constant_p (operands[1]);
3559 static char buf[40];
3561 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3564 return "fmove%.s %f1,%0";
3567 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3568 from the "fmovecr" instruction.
3569 The value, anded with 0xff, gives the code to use in fmovecr
3570 to get the desired constant. */
3572 /* This code has been fixed for cross-compilation. */
3574 static int inited_68881_table = 0;
3576 static const char *const strings_68881[7] = {
3586 static const int codes_68881[7] = {
3596 REAL_VALUE_TYPE values_68881[7];
3598 /* Set up values_68881 array by converting the decimal values
3599 strings_68881 to binary. */
3602 init_68881_table (void)
3606 enum machine_mode mode;
3609 for (i = 0; i < 7; i++)
3613 r = REAL_VALUE_ATOF (strings_68881[i], mode);
3614 values_68881[i] = r;
3616 inited_68881_table = 1;
3620 standard_68881_constant_p (rtx x)
3625 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3626 used at all on those chips. */
3630 if (! inited_68881_table)
3631 init_68881_table ();
3633 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3635 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3637 for (i = 0; i < 6; i++)
3639 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
3640 return (codes_68881[i]);
3643 if (GET_MODE (x) == SFmode)
3646 if (REAL_VALUES_EQUAL (r, values_68881[6]))
3647 return (codes_68881[6]);
3649 /* larger powers of ten in the constants ram are not used
3650 because they are not equal to a `double' C constant. */
3654 /* If X is a floating-point constant, return the logarithm of X base 2,
3655 or 0 if X is not a power of 2. */
3658 floating_exact_log2 (rtx x)
3660 REAL_VALUE_TYPE r, r1;
3663 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3665 if (REAL_VALUES_LESS (r, dconst1))
3668 exp = real_exponent (&r);
3669 real_2expN (&r1, exp, DFmode);
3670 if (REAL_VALUES_EQUAL (r1, r))
3676 /* A C compound statement to output to stdio stream STREAM the
3677 assembler syntax for an instruction operand X. X is an RTL
3680 CODE is a value that can be used to specify one of several ways
3681 of printing the operand. It is used when identical operands
3682 must be printed differently depending on the context. CODE
3683 comes from the `%' specification that was used to request
3684 printing of the operand. If the specification was just `%DIGIT'
3685 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3686 is the ASCII code for LTR.
3688 If X is a register, this macro should print the register's name.
3689 The names can be found in an array `reg_names' whose type is
3690 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3692 When the machine description has a specification `%PUNCT' (a `%'
3693 followed by a punctuation character), this macro is called with
3694 a null pointer for X and the punctuation character for CODE.
3696 The m68k specific codes are:
3698 '.' for dot needed in Motorola-style opcode names.
3699 '-' for an operand pushing on the stack:
3700 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3701 '+' for an operand pushing on the stack:
3702 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3703 '@' for a reference to the top word on the stack:
3704 sp@, (sp) or (%sp) depending on the style of syntax.
3705 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3706 but & in SGS syntax).
3707 '!' for the cc register (used in an `and to cc' insn).
3708 '$' for the letter `s' in an op code, but only on the 68040.
3709 '&' for the letter `d' in an op code, but only on the 68040.
3710 '/' for register prefix needed by longlong.h.
3711 '?' for m68k_library_id_string
3713 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3714 'd' to force memory addressing to be absolute, not relative.
3715 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3716 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3717 or print pair of registers as rx:ry.
3718 'p' print an address with @PLTPC attached, but only if the operand
3719 is not locally-bound. */
3722 print_operand (FILE *file, rtx op, int letter)
3727 fprintf (file, ".");
3729 else if (letter == '#')
3730 asm_fprintf (file, "%I");
3731 else if (letter == '-')
3732 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
3733 else if (letter == '+')
3734 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
3735 else if (letter == '@')
3736 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
3737 else if (letter == '!')
3738 asm_fprintf (file, "%Rfpcr");
3739 else if (letter == '$')
3742 fprintf (file, "s");
3744 else if (letter == '&')
3747 fprintf (file, "d");
3749 else if (letter == '/')
3750 asm_fprintf (file, "%R");
3751 else if (letter == '?')
3752 asm_fprintf (file, m68k_library_id_string);
3753 else if (letter == 'p')
3755 output_addr_const (file, op);
3756 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
3757 fprintf (file, "@PLTPC");
3759 else if (GET_CODE (op) == REG)
3762 /* Print out the second register name of a register pair.
3763 I.e., R (6) => 7. */
3764 fputs (M68K_REGNAME(REGNO (op) + 1), file);
3766 fputs (M68K_REGNAME(REGNO (op)), file);
3768 else if (GET_CODE (op) == MEM)
3770 output_address (XEXP (op, 0));
3771 if (letter == 'd' && ! TARGET_68020
3772 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3773 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3774 && INTVAL (XEXP (op, 0)) < 0x8000
3775 && INTVAL (XEXP (op, 0)) >= -0x8000))
3776 fprintf (file, MOTOROLA ? ".l" : ":l");
3778 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3781 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3782 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3784 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3787 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3788 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3790 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3793 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3794 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3798 /* Use `print_operand_address' instead of `output_addr_const'
3799 to ensure that we print relevant PIC stuff. */
3800 asm_fprintf (file, "%I");
3802 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3803 print_operand_address (file, op);
3805 output_addr_const (file, op);
3810 /* A C compound statement to output to stdio stream STREAM the
3811 assembler syntax for an instruction operand that is a memory
3812 reference whose address is ADDR. ADDR is an RTL expression.
3814 Note that this contains a kludge that knows that the only reason
3815 we have an address (plus (label_ref...) (reg...)) when not generating
3816 PIC code is in the insn before a tablejump, and we know that m68k.md
3817 generates a label LInnn: on such an insn.
3819 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3820 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3822 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
3823 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
3824 we want. This difference can be accommodated by using an assembler
3825 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
3826 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
3827 macro. See m68k/sgs.h for an example; for versions without the bug.
3828 Some assemblers refuse all the above solutions. The workaround is to
3829 emit "K(pc,d0.l*2)" with K being a small constant known to give the
3832 They also do not like things like "pea 1.w", so we simple leave off
3833 the .w on small constants.
3835 This routine is responsible for distinguishing between -fpic and -fPIC
3836 style relocations in an address. When generating -fpic code the
3837 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3838 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3841 print_operand_address (FILE *file, rtx addr)
3843 struct m68k_address address;
3845 if (!m68k_decompose_address (QImode, addr, true, &address))
3848 if (address.code == PRE_DEC)
3849 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
3850 M68K_REGNAME (REGNO (address.base)));
3851 else if (address.code == POST_INC)
3852 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
3853 M68K_REGNAME (REGNO (address.base)));
3854 else if (!address.base && !address.index)
3856 /* A constant address. */
3857 gcc_assert (address.offset == addr);
3858 if (GET_CODE (addr) == CONST_INT)
3860 /* (xxx).w or (xxx).l. */
3861 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
3862 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
3864 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3866 else if (TARGET_PCREL)
3868 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3870 output_addr_const (file, addr);
3871 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3875 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3876 name ends in `.<letter>', as the last 2 characters can be
3877 mistaken as a size suffix. Put the name in parentheses. */
3878 if (GET_CODE (addr) == SYMBOL_REF
3879 && strlen (XSTR (addr, 0)) > 2
3880 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3883 output_addr_const (file, addr);
3887 output_addr_const (file, addr);
3894 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3895 label being accessed, otherwise it is -1. */
3896 labelno = (address.offset
3898 && GET_CODE (address.offset) == LABEL_REF
3899 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
3903 /* Print the "offset(base" component. */
3905 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,", labelno, labelno);
3910 output_addr_const (file, address.offset);
3911 if (flag_pic && address.base == pic_offset_table_rtx)
3913 fprintf (file, "@GOT");
3914 if (flag_pic == 1 && TARGET_68020)
3915 fprintf (file, ".w");
3920 fputs (M68K_REGNAME (REGNO (address.base)), file);
3922 /* Print the ",index" component, if any. */
3927 fprintf (file, "%s.%c",
3928 M68K_REGNAME (REGNO (address.index)),
3929 GET_MODE (address.index) == HImode ? 'w' : 'l');
3930 if (address.scale != 1)
3931 fprintf (file, "*%d", address.scale);
3935 else /* !MOTOROLA */
3937 if (!address.offset && !address.index)
3938 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
3941 /* Print the "base@(offset" component. */
3943 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b", labelno, labelno);
3947 fputs (M68K_REGNAME (REGNO (address.base)), file);
3948 fprintf (file, "@(");
3951 output_addr_const (file, address.offset);
3952 if (address.base == pic_offset_table_rtx && TARGET_68020)
3956 fprintf (file, ":w"); break;
3958 fprintf (file, ":l"); break;
3964 /* Print the ",index" component, if any. */
3967 fprintf (file, ",%s:%c",
3968 M68K_REGNAME (REGNO (address.index)),
3969 GET_MODE (address.index) == HImode ? 'w' : 'l');
3970 if (address.scale != 1)
3971 fprintf (file, ":%d", address.scale);
3979 /* Check for cases where a clr insns can be omitted from code using
3980 strict_low_part sets. For example, the second clrl here is not needed:
3981 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3983 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3984 insn we are checking for redundancy. TARGET is the register set by the
3988 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
3993 p = prev_nonnote_insn (first_insn);
3997 /* If it isn't an insn, then give up. */
3998 if (GET_CODE (p) != INSN)
4001 if (reg_set_p (target, p))
4003 rtx set = single_set (p);
4006 /* If it isn't an easy to recognize insn, then give up. */
4010 dest = SET_DEST (set);
4012 /* If this sets the entire target register to zero, then our
4013 first_insn is redundant. */
4014 if (rtx_equal_p (dest, target)
4015 && SET_SRC (set) == const0_rtx)
4017 else if (GET_CODE (dest) == STRICT_LOW_PART
4018 && GET_CODE (XEXP (dest, 0)) == REG
4019 && REGNO (XEXP (dest, 0)) == REGNO (target)
4020 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4021 <= GET_MODE_SIZE (mode)))
4022 /* This is a strict low part set which modifies less than
4023 we are using, so it is safe. */
4029 p = prev_nonnote_insn (p);
4035 /* Operand predicates for implementing asymmetric pc-relative addressing
4036 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4037 when used as a source operand, but not as a destination operand.
4039 We model this by restricting the meaning of the basic predicates
4040 (general_operand, memory_operand, etc) to forbid the use of this
4041 addressing mode, and then define the following predicates that permit
4042 this addressing mode. These predicates can then be used for the
4043 source operands of the appropriate instructions.
4045 n.b. While it is theoretically possible to change all machine patterns
4046 to use this addressing more where permitted by the architecture,
4047 it has only been implemented for "common" cases: SImode, HImode, and
4048 QImode operands, and only for the principle operations that would
4049 require this addressing mode: data movement and simple integer operations.
4051 In parallel with these new predicates, two new constraint letters
4052 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4053 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4054 In the pcrel case 's' is only valid in combination with 'a' registers.
4055 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4056 of how these constraints are used.
4058 The use of these predicates is strictly optional, though patterns that
4059 don't will cause an extra reload register to be allocated where one
4062 lea (abc:w,%pc),%a0 ; need to reload address
4063 moveq &1,%d1 ; since write to pc-relative space
4064 movel %d1,%a0@ ; is not allowed
4066 lea (abc:w,%pc),%a1 ; no need to reload address here
4067 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4069 For more info, consult tiemann@cygnus.com.
4072 All of the ugliness with predicates and constraints is due to the
4073 simple fact that the m68k does not allow a pc-relative addressing
4074 mode as a destination. gcc does not distinguish between source and
4075 destination addresses. Hence, if we claim that pc-relative address
4076 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4077 end up with invalid code. To get around this problem, we left
4078 pc-relative modes as invalid addresses, and then added special
4079 predicates and constraints to accept them.
4081 A cleaner way to handle this is to modify gcc to distinguish
4082 between source and destination addresses. We can then say that
4083 pc-relative is a valid source address but not a valid destination
4084 address, and hopefully avoid a lot of the predicate and constraint
4085 hackery. Unfortunately, this would be a pretty big change. It would
4086 be a useful change for a number of ports, but there aren't any current
4087 plans to undertake this.
4089 ***************************************************************************/
4093 output_andsi3 (rtx *operands)
4096 if (GET_CODE (operands[2]) == CONST_INT
4097 && (INTVAL (operands[2]) | 0xffff) == -1
4098 && (DATA_REG_P (operands[0])
4099 || offsettable_memref_p (operands[0]))
4100 && !TARGET_COLDFIRE)
4102 if (GET_CODE (operands[0]) != REG)
4103 operands[0] = adjust_address (operands[0], HImode, 2);
4104 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4105 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4107 if (operands[2] == const0_rtx)
4109 return "and%.w %2,%0";
4111 if (GET_CODE (operands[2]) == CONST_INT
4112 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
4113 && (DATA_REG_P (operands[0])
4114 || offsettable_memref_p (operands[0])))
4116 if (DATA_REG_P (operands[0]))
4117 operands[1] = GEN_INT (logval);
4120 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4121 operands[1] = GEN_INT (logval % 8);
4123 /* This does not set condition codes in a standard way. */
4125 return "bclr %1,%0";
4127 return "and%.l %2,%0";
4131 output_iorsi3 (rtx *operands)
4133 register int logval;
4134 if (GET_CODE (operands[2]) == CONST_INT
4135 && INTVAL (operands[2]) >> 16 == 0
4136 && (DATA_REG_P (operands[0])
4137 || offsettable_memref_p (operands[0]))
4138 && !TARGET_COLDFIRE)
4140 if (GET_CODE (operands[0]) != REG)
4141 operands[0] = adjust_address (operands[0], HImode, 2);
4142 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4144 if (INTVAL (operands[2]) == 0xffff)
4145 return "mov%.w %2,%0";
4146 return "or%.w %2,%0";
4148 if (GET_CODE (operands[2]) == CONST_INT
4149 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4150 && (DATA_REG_P (operands[0])
4151 || offsettable_memref_p (operands[0])))
4153 if (DATA_REG_P (operands[0]))
4154 operands[1] = GEN_INT (logval);
4157 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4158 operands[1] = GEN_INT (logval % 8);
4161 return "bset %1,%0";
4163 return "or%.l %2,%0";
4167 output_xorsi3 (rtx *operands)
4169 register int logval;
4170 if (GET_CODE (operands[2]) == CONST_INT
4171 && INTVAL (operands[2]) >> 16 == 0
4172 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
4173 && !TARGET_COLDFIRE)
4175 if (! DATA_REG_P (operands[0]))
4176 operands[0] = adjust_address (operands[0], HImode, 2);
4177 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4179 if (INTVAL (operands[2]) == 0xffff)
4181 return "eor%.w %2,%0";
4183 if (GET_CODE (operands[2]) == CONST_INT
4184 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4185 && (DATA_REG_P (operands[0])
4186 || offsettable_memref_p (operands[0])))
4188 if (DATA_REG_P (operands[0]))
4189 operands[1] = GEN_INT (logval);
4192 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4193 operands[1] = GEN_INT (logval % 8);
4196 return "bchg %1,%0";
4198 return "eor%.l %2,%0";
4201 /* Return the instruction that should be used for a call to address X,
4202 which is known to be in operand 0. */
4207 if (symbolic_operand (x, VOIDmode))
4208 return m68k_symbolic_call;
4213 /* Likewise sibling calls. */
4216 output_sibcall (rtx x)
4218 if (symbolic_operand (x, VOIDmode))
4219 return m68k_symbolic_jump;
4224 #ifdef M68K_TARGET_COFF
4226 /* Output assembly to switch to section NAME with attribute FLAGS. */
4229 m68k_coff_asm_named_section (const char *name, unsigned int flags,
4230 tree decl ATTRIBUTE_UNUSED)
4234 if (flags & SECTION_WRITE)
4239 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
4242 #endif /* M68K_TARGET_COFF */
4245 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
4246 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4249 rtx this_slot, offset, addr, mem, insn;
4251 /* Pretend to be a post-reload pass while generating rtl. */
4252 reload_completed = 1;
4254 /* The "this" pointer is stored at 4(%sp). */
4255 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
4257 /* Add DELTA to THIS. */
4260 /* Make the offset a legitimate operand for memory addition. */
4261 offset = GEN_INT (delta);
4262 if ((delta < -8 || delta > 8)
4263 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
4265 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
4266 offset = gen_rtx_REG (Pmode, D0_REG);
4268 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4269 copy_rtx (this_slot), offset));
4272 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4273 if (vcall_offset != 0)
4275 /* Set the static chain register to *THIS. */
4276 emit_move_insn (static_chain_rtx, this_slot);
4277 emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx));
4279 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4280 addr = plus_constant (static_chain_rtx, vcall_offset);
4281 if (!m68k_legitimate_address_p (Pmode, addr, true))
4283 emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr));
4284 addr = static_chain_rtx;
4287 /* Load the offset into %d0 and add it to THIS. */
4288 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
4289 gen_rtx_MEM (Pmode, addr));
4290 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4291 copy_rtx (this_slot),
4292 gen_rtx_REG (Pmode, D0_REG)));
4295 /* Jump to the target function. Use a sibcall if direct jumps are
4296 allowed, otherwise load the address into a register first. */
4297 mem = DECL_RTL (function);
4298 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
4300 gcc_assert (flag_pic);
4302 if (!TARGET_SEP_DATA)
4304 /* Use the static chain register as a temporary (call-clobbered)
4305 GOT pointer for this function. We can use the static chain
4306 register because it isn't live on entry to the thunk. */
4307 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
4308 emit_insn (gen_load_got (pic_offset_table_rtx));
4310 legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx);
4311 mem = replace_equiv_address (mem, static_chain_rtx);
4313 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
4314 SIBLING_CALL_P (insn) = 1;
4316 /* Run just enough of rest_of_compilation. */
4317 insn = get_insns ();
4318 split_all_insns_noflow ();
4319 final_start_function (insn, file, 1);
4320 final (insn, file, 1);
4321 final_end_function ();
4323 /* Clean up the vars set above. */
4324 reload_completed = 0;
4326 /* Restore the original PIC register. */
4328 SET_REGNO (pic_offset_table_rtx, PIC_REG);
4331 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4334 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4335 int incoming ATTRIBUTE_UNUSED)
4337 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
4340 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4342 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4343 unsigned int new_reg)
4346 /* Interrupt functions can only use registers that have already been
4347 saved by the prologue, even if they would normally be
4350 if ((m68k_get_function_kind (current_function_decl)
4351 == m68k_fk_interrupt_handler)
4352 && !df_regs_ever_live_p (new_reg))
4358 /* Value is true if hard register REGNO can hold a value of machine-mode
4359 MODE. On the 68000, we let the cpu registers can hold any mode, but
4360 restrict the 68881 registers to floating-point modes. */
4363 m68k_regno_mode_ok (int regno, enum machine_mode mode)
4365 if (DATA_REGNO_P (regno))
4367 /* Data Registers, can hold aggregate if fits in. */
4368 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
4371 else if (ADDRESS_REGNO_P (regno))
4373 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
4376 else if (FP_REGNO_P (regno))
4378 /* FPU registers, hold float or complex float of long double or
4380 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4381 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4382 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
4388 /* Implement SECONDARY_RELOAD_CLASS. */
4391 m68k_secondary_reload_class (enum reg_class rclass,
4392 enum machine_mode mode, rtx x)
4396 regno = true_regnum (x);
4398 /* If one operand of a movqi is an address register, the other
4399 operand must be a general register or constant. Other types
4400 of operand must be reloaded through a data register. */
4401 if (GET_MODE_SIZE (mode) == 1
4402 && reg_classes_intersect_p (rclass, ADDR_REGS)
4403 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
4406 /* PC-relative addresses must be loaded into an address register first. */
4408 && !reg_class_subset_p (rclass, ADDR_REGS)
4409 && symbolic_operand (x, VOIDmode))
4415 /* Implement PREFERRED_RELOAD_CLASS. */
4418 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
4420 enum reg_class secondary_class;
4422 /* If RCLASS might need a secondary reload, try restricting it to
4423 a class that doesn't. */
4424 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
4425 if (secondary_class != NO_REGS
4426 && reg_class_subset_p (secondary_class, rclass))
4427 return secondary_class;
4429 /* Prefer to use moveq for in-range constants. */
4430 if (GET_CODE (x) == CONST_INT
4431 && reg_class_subset_p (DATA_REGS, rclass)
4432 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
4435 /* ??? Do we really need this now? */
4436 if (GET_CODE (x) == CONST_DOUBLE
4437 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4439 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
4448 /* Return floating point values in a 68881 register. This makes 68881 code
4449 a little bit faster. It also makes -msoft-float code incompatible with
4450 hard-float code, so people have to be careful not to mix the two.
4451 For ColdFire it was decided the ABI incompatibility is undesirable.
4452 If there is need for a hard-float ABI it is probably worth doing it
4453 properly and also passing function arguments in FP registers. */
4455 m68k_libcall_value (enum machine_mode mode)
4462 return gen_rtx_REG (mode, FP0_REG);
4467 return gen_rtx_REG (mode, D0_REG);
4471 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
4473 enum machine_mode mode;
4475 mode = TYPE_MODE (valtype);
4481 return gen_rtx_REG (mode, FP0_REG);
4487 /* If the function returns a pointer, push that into %a0. */
4488 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
4489 /* For compatibility with the large body of existing code which
4490 does not always properly declare external functions returning
4491 pointer types, the m68k/SVR4 convention is to copy the value
4492 returned for pointer functions from a0 to d0 in the function
4493 epilogue, so that callers that have neglected to properly
4494 declare the callee can still find the correct return value in
4496 return gen_rtx_PARALLEL
4499 gen_rtx_EXPR_LIST (VOIDmode,
4500 gen_rtx_REG (mode, A0_REG),
4502 gen_rtx_EXPR_LIST (VOIDmode,
4503 gen_rtx_REG (mode, D0_REG),
4505 else if (POINTER_TYPE_P (valtype))
4506 return gen_rtx_REG (mode, A0_REG);
4508 return gen_rtx_REG (mode, D0_REG);
4511 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4512 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4514 m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4516 enum machine_mode mode = TYPE_MODE (type);
4518 if (mode == BLKmode)
4521 /* If TYPE's known alignment is less than the alignment of MODE that
4522 would contain the structure, then return in memory. We need to
4523 do so to maintain the compatibility between code compiled with
4524 -mstrict-align and that compiled with -mno-strict-align. */
4525 if (AGGREGATE_TYPE_P (type)
4526 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
4533 /* CPU to schedule the program for. */
4534 enum attr_cpu m68k_sched_cpu;
4545 /* Implicit mem reference (e.g. stack). */
4548 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4551 /* Memory with offset but without indexing. EA mode 5. */
4554 /* Memory with indexing. EA mode 6. */
4557 /* Memory referenced by absolute address. EA mode 7. */
4560 /* Immediate operand that doesn't require extension word. */
4563 /* Immediate 16 bit operand. */
4566 /* Immediate 32 bit operand. */
4570 /* True if current insn doesn't have complete pipeline description. */
4571 static bool sched_guess_p;
4573 /* Return type of memory ADDR_RTX refers to. */
4574 static enum attr_op_type
4575 sched_address_type (enum machine_mode mode, rtx addr_rtx)
4577 struct m68k_address address;
4579 if (!m68k_decompose_address (mode, addr_rtx,
4580 reload_completed, &address))
4582 gcc_assert (sched_guess_p);
4583 /* Reload will likely fix the address to be in the register. */
4584 return OP_TYPE_MEM234;
4587 if (address.scale != 0)
4588 return OP_TYPE_MEM6;
4590 if (address.base != NULL_RTX)
4592 if (address.offset == NULL_RTX)
4593 return OP_TYPE_MEM234;
4595 return OP_TYPE_MEM5;
4598 gcc_assert (address.offset != NULL_RTX);
4600 return OP_TYPE_MEM7;
4603 /* Return type of the operand OP.
4604 If ADDRESS_P is true, return type of memory location OP refers to. */
4605 static enum attr_op_type
4606 sched_operand_type (rtx op, bool address_p)
4608 gcc_assert (op != NULL_RTX);
4611 return sched_address_type (QImode, op);
4613 if (memory_operand (op, VOIDmode))
4614 return sched_address_type (GET_MODE (op), XEXP (op, 0));
4616 if (register_operand (op, VOIDmode))
4619 if (GET_CODE (op) == CONST_INT)
4621 /* ??? Below condition should probably check if the operation is
4622 signed or unsigned. */
4623 if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff))
4624 return OP_TYPE_IMM_W;
4626 return OP_TYPE_IMM_L;
4629 if (GET_CODE (op) == CONST_DOUBLE)
4631 switch (GET_MODE (op))
4634 return OP_TYPE_IMM_W;
4638 return OP_TYPE_IMM_L;
4645 if (symbolic_operand (op, VOIDmode)
4648 switch (GET_MODE (op))
4651 return OP_TYPE_IMM_Q;
4654 return OP_TYPE_IMM_W;
4657 return OP_TYPE_IMM_L;
4660 if (GET_CODE (op) == SYMBOL_REF)
4661 /* ??? Just a guess. Probably we can guess better using length
4662 attribute of the instructions. */
4663 return OP_TYPE_IMM_W;
4665 return OP_TYPE_IMM_L;
4669 gcc_assert (sched_guess_p);
4674 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4675 If ADDRESS_P is true, return type of memory location operand refers to. */
4676 static enum attr_op_type
4677 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
4681 extract_constrain_insn_cached (insn);
4684 i = get_attr_opx (insn);
4686 i = get_attr_opy (insn);
4688 if (i >= recog_data.n_operands)
4690 gcc_assert (sched_guess_p);
4694 return sched_operand_type (recog_data.operand[i], address_p);
4697 /* Implement opx_type attribute.
4698 Return type of INSN's operand X.
4699 If ADDRESS_P is true, return type of memory location operand refers to. */
4701 m68k_sched_attr_opx_type (rtx insn, int address_p)
4703 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4705 switch (sched_attr_op_type (insn, true, address_p != 0))
4708 return OPX_TYPE_REG;
4711 return OPX_TYPE_MEM1;
4713 case OP_TYPE_MEM234:
4714 return OPX_TYPE_MEM234;
4717 return OPX_TYPE_MEM5;
4720 return OPX_TYPE_MEM6;
4723 return OPX_TYPE_MEM7;
4726 return OPX_TYPE_IMM_Q;
4729 return OPX_TYPE_IMM_W;
4732 return OPX_TYPE_IMM_L;
4740 /* Implement opy_type attribute.
4741 Return type of INSN's operand Y.
4742 If ADDRESS_P is true, return type of memory location operand refers to. */
4744 m68k_sched_attr_opy_type (rtx insn, int address_p)
4746 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4748 switch (sched_attr_op_type (insn, false, address_p != 0))
4751 return OPY_TYPE_REG;
4754 return OPY_TYPE_MEM1;
4756 case OP_TYPE_MEM234:
4757 return OPY_TYPE_MEM234;
4760 return OPY_TYPE_MEM5;
4763 return OPY_TYPE_MEM6;
4766 return OPY_TYPE_MEM7;
4769 return OPY_TYPE_IMM_Q;
4772 return OPY_TYPE_IMM_W;
4775 return OPY_TYPE_IMM_L;
4783 /* Return the size of INSN. */
4785 m68k_sched_attr_size (rtx insn)
4789 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4791 switch (get_attr_type1 (insn))
4802 switch (get_attr_opx_type (insn))
4807 case OPX_TYPE_MEM234:
4808 case OPY_TYPE_IMM_Q:
4813 /* Here we assume that most absolute references are short. */
4815 case OPY_TYPE_IMM_W:
4819 case OPY_TYPE_IMM_L:
4827 switch (get_attr_opy_type (insn))
4832 case OPY_TYPE_MEM234:
4833 case OPY_TYPE_IMM_Q:
4838 /* Here we assume that most absolute references are short. */
4840 case OPY_TYPE_IMM_W:
4844 case OPY_TYPE_IMM_L:
4854 gcc_assert (sched_guess_p);
4862 /* Implement op_mem attribute. */
4864 m68k_sched_attr_op_mem (rtx insn)
4866 enum attr_opy_mem opy;
4867 enum attr_opx_mem opx;
4869 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4871 opy = get_attr_opy_mem (insn);
4872 opx = get_attr_opx_mem (insn);
4874 if (opy == OPY_MEM_R && opx == OPX_MEM_R)
4877 if (opy == OPY_MEM_R && opx == OPX_MEM_M)
4879 switch (get_attr_opx_access (insn))
4891 gcc_assert (sched_guess_p);
4892 return OP_MEM_UNKNOWN;
4896 if (opy == OPY_MEM_R && opx == OPX_MEM_I)
4898 switch (get_attr_opx_access (insn))
4910 gcc_assert (sched_guess_p);
4911 return OP_MEM_UNKNOWN;
4915 if (opy == OPY_MEM_M && opx == OPX_MEM_R)
4918 if (opy == OPY_MEM_M && opx == OPX_MEM_M)
4920 switch (get_attr_opx_access (insn))
4926 gcc_assert (sched_guess_p);
4927 return OP_MEM_UNKNOWN;
4931 if (opy == OPY_MEM_M && opx == OPX_MEM_I)
4933 switch (get_attr_opx_access (insn))
4939 gcc_assert (sched_guess_p);
4940 return OP_MEM_UNKNOWN;
4944 if (opy == OPY_MEM_I && opx == OPX_MEM_R)
4948 if (opy == OPY_MEM_I && opx == OPX_MEM_M)
4950 switch (get_attr_opx_access (insn))
4956 gcc_assert (sched_guess_p);
4957 return OP_MEM_UNKNOWN;
4961 gcc_assert (sched_guess_p);
4962 return OP_MEM_UNKNOWN;
4965 /* Jump instructions types. Indexed by INSN_UID.
4966 The same rtl insn can be expanded into different asm instructions
4967 depending on the cc0_status. To properly determine type of jump
4968 instructions we scan instruction stream and map jumps types to this
4970 static enum attr_type *sched_branch_type;
4972 /* Return the type of the jump insn. */
4974 m68k_sched_branch_type (rtx insn)
4976 enum attr_type type;
4978 type = sched_branch_type[INSN_UID (insn)];
4980 gcc_assert (type != 0);