1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
50 enum reg_class regno_reg_class[] =
52 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
53 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
54 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
55 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
56 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
57 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
62 /* The minimum number of integer registers that we want to save with the
63 movem instruction. Using two movel instructions instead of a single
64 moveml is about 15% faster for the 68020 and 68030 at no expense in
66 #define MIN_MOVEM_REGS 3
68 /* The minimum number of floating point registers that we want to save
69 with the fmovem instruction. */
70 #define MIN_FMOVEM_REGS 1
72 /* Structure describing stack frame layout. */
75 /* Stack pointer to frame pointer offset. */
78 /* Offset of FPU registers. */
79 HOST_WIDE_INT foffset;
81 /* Frame size in bytes (rounded up). */
84 /* Data and address register. */
86 unsigned int reg_mask;
90 unsigned int fpu_mask;
92 /* Offsets relative to ARG_POINTER. */
93 HOST_WIDE_INT frame_pointer_offset;
94 HOST_WIDE_INT stack_pointer_offset;
96 /* Function which the above information refers to. */
100 /* Current frame information calculated by m68k_compute_frame_layout(). */
101 static struct m68k_frame current_frame;
103 /* Structure describing an m68k address.
105 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
106 with null fields evaluating to 0. Here:
108 - BASE satisfies m68k_legitimate_base_reg_p
109 - INDEX satisfies m68k_legitimate_index_reg_p
110 - OFFSET satisfies m68k_legitimate_constant_address_p
112 INDEX is either HImode or SImode. The other fields are SImode.
114 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
115 the address is (BASE)+. */
116 struct m68k_address {
124 static int m68k_sched_adjust_cost (rtx, rtx, rtx, int);
125 static int m68k_sched_variable_issue (FILE *, int, rtx, int);
126 static void m68k_sched_md_init_global (FILE *, int, int);
127 static void m68k_sched_md_finish_global (FILE *, int);
128 static void m68k_sched_md_init (FILE *, int, int);
129 static void m68k_sched_dfa_pre_advance_cycle (void);
130 static void m68k_sched_dfa_post_advance_cycle (void);
132 static bool m68k_handle_option (size_t, const char *, int);
133 static rtx find_addr_reg (rtx);
134 static const char *singlemove_string (rtx *);
135 #ifdef M68K_TARGET_COFF
136 static void m68k_coff_asm_named_section (const char *, unsigned int, tree);
137 #endif /* M68K_TARGET_COFF */
138 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
139 HOST_WIDE_INT, tree);
140 static rtx m68k_struct_value_rtx (tree, int);
141 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
142 tree args, int flags,
144 static void m68k_compute_frame_layout (void);
145 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
146 static bool m68k_ok_for_sibcall_p (tree, tree);
147 static bool m68k_rtx_costs (rtx, int, int, int *);
148 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
149 static bool m68k_return_in_memory (tree, tree);
153 /* Specify the identification number of the library being built */
154 const char *m68k_library_id_string = "_current_shared_library_a5_offset_";
156 /* Nonzero if the last compare/test insn had FP operands. The
157 sCC expanders peek at this to determine what to do for the
158 68060, which has no fsCC instructions. */
159 int m68k_last_compare_had_fp_operands;
161 /* Initialize the GCC target structure. */
163 #if INT_OP_GROUP == INT_OP_DOT_WORD
164 #undef TARGET_ASM_ALIGNED_HI_OP
165 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
168 #if INT_OP_GROUP == INT_OP_NO_DOT
169 #undef TARGET_ASM_BYTE_OP
170 #define TARGET_ASM_BYTE_OP "\tbyte\t"
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
173 #undef TARGET_ASM_ALIGNED_SI_OP
174 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
177 #if INT_OP_GROUP == INT_OP_DC
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
186 #undef TARGET_ASM_UNALIGNED_HI_OP
187 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
188 #undef TARGET_ASM_UNALIGNED_SI_OP
189 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_OUTPUT_MI_THUNK
192 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
193 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
194 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
196 #undef TARGET_ASM_FILE_START_APP_OFF
197 #define TARGET_ASM_FILE_START_APP_OFF true
199 #undef TARGET_SCHED_ADJUST_COST
200 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
202 #undef TARGET_SCHED_VARIABLE_ISSUE
203 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
205 #undef TARGET_SCHED_INIT_GLOBAL
206 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
208 #undef TARGET_SCHED_FINISH_GLOBAL
209 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
211 #undef TARGET_SCHED_INIT
212 #define TARGET_SCHED_INIT m68k_sched_md_init
214 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
215 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
217 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
218 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
220 #undef TARGET_HANDLE_OPTION
221 #define TARGET_HANDLE_OPTION m68k_handle_option
223 #undef TARGET_RTX_COSTS
224 #define TARGET_RTX_COSTS m68k_rtx_costs
226 #undef TARGET_ATTRIBUTE_TABLE
227 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
229 #undef TARGET_PROMOTE_PROTOTYPES
230 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
232 #undef TARGET_STRUCT_VALUE_RTX
233 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
235 #undef TARGET_CANNOT_FORCE_CONST_MEM
236 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_illegitimate_symbolic_constant_p
238 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
239 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
241 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
242 #undef TARGET_RETURN_IN_MEMORY
243 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
246 static const struct attribute_spec m68k_attribute_table[] =
248 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
249 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
250 { "interrupt_handler", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
251 { "interrupt_thread", 0, 0, true, false, false, m68k_handle_fndecl_attribute },
252 { NULL, 0, 0, false, false, false, NULL }
255 struct gcc_target targetm = TARGET_INITIALIZER;
257 /* Base flags for 68k ISAs. */
258 #define FL_FOR_isa_00 FL_ISA_68000
259 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
260 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
261 generated 68881 code for 68020 and 68030 targets unless explicitly told
263 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
264 | FL_BITFIELD | FL_68881)
265 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
266 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
268 /* Base flags for ColdFire ISAs. */
269 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
270 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
271 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
272 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
273 /* ISA_C is not upwardly compatible with ISA_B. */
274 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
278 /* Traditional 68000 instruction sets. */
284 /* ColdFire instruction set variants. */
292 /* Information about one of the -march, -mcpu or -mtune arguments. */
293 struct m68k_target_selection
295 /* The argument being described. */
298 /* For -mcpu, this is the device selected by the option.
299 For -mtune and -march, it is a representative device
300 for the microarchitecture or ISA respectively. */
301 enum target_device device;
303 /* The M68K_DEVICE fields associated with DEVICE. See the comment
304 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
306 enum uarch_type microarch;
311 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
312 static const struct m68k_target_selection all_devices[] =
314 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
315 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
316 #include "m68k-devices.def"
318 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
321 /* A list of all ISAs, mapping each one to a representative device.
322 Used for -march selection. */
323 static const struct m68k_target_selection all_isas[] =
325 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
326 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
327 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
328 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
329 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
330 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
331 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
332 { "isaa", mcf5206e, NULL, ucfv2, isa_a, (FL_FOR_isa_a
334 { "isaaplus", mcf5271, NULL, ucfv2, isa_aplus, (FL_FOR_isa_aplus
336 { "isab", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
337 { "isac", unk_device, NULL, ucfv4, isa_c, (FL_FOR_isa_c
339 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
342 /* A list of all microarchitectures, mapping each one to a representative
343 device. Used for -mtune selection. */
344 static const struct m68k_target_selection all_microarchs[] =
346 { "68000", m68000, NULL, u68000, isa_00, FL_FOR_isa_00 },
347 { "68010", m68010, NULL, u68010, isa_10, FL_FOR_isa_10 },
348 { "68020", m68020, NULL, u68020, isa_20, FL_FOR_isa_20 },
349 { "68020-40", m68020, NULL, u68020_40, isa_20, FL_FOR_isa_20 },
350 { "68020-60", m68020, NULL, u68020_60, isa_20, FL_FOR_isa_20 },
351 { "68030", m68030, NULL, u68030, isa_20, FL_FOR_isa_20 },
352 { "68040", m68040, NULL, u68040, isa_40, FL_FOR_isa_40 },
353 { "68060", m68060, NULL, u68060, isa_40, FL_FOR_isa_40 },
354 { "cpu32", cpu32, NULL, ucpu32, isa_20, FL_FOR_isa_cpu32 },
355 { "cfv1", mcf51qe, NULL, ucfv1, isa_c, FL_FOR_isa_c },
356 { "cfv2", mcf5206, NULL, ucfv2, isa_a, FL_FOR_isa_a },
357 { "cfv3", mcf5307, NULL, ucfv3, isa_a, (FL_FOR_isa_a
359 { "cfv4", mcf5407, NULL, ucfv4, isa_b, FL_FOR_isa_b },
360 { "cfv4e", mcf547x, NULL, ucfv4e, isa_b, (FL_FOR_isa_b
364 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
367 /* The entries associated with the -mcpu, -march and -mtune settings,
368 or null for options that have not been used. */
369 const struct m68k_target_selection *m68k_cpu_entry;
370 const struct m68k_target_selection *m68k_arch_entry;
371 const struct m68k_target_selection *m68k_tune_entry;
373 /* Which CPU we are generating code for. */
374 enum target_device m68k_cpu;
376 /* Which microarchitecture to tune for. */
377 enum uarch_type m68k_tune;
379 /* Which FPU to use. */
380 enum fpu_type m68k_fpu;
382 /* The set of FL_* flags that apply to the target processor. */
383 unsigned int m68k_cpu_flags;
385 /* Asm templates for calling or jumping to an arbitrary symbolic address,
386 or NULL if such calls or jumps are not supported. The address is held
388 const char *m68k_symbolic_call;
389 const char *m68k_symbolic_jump;
391 /* Enum variable that corresponds to m68k_symbolic_call values. */
392 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
395 /* See whether TABLE has an entry with name NAME. Return true and
396 store the entry in *ENTRY if so, otherwise return false and
397 leave *ENTRY alone. */
400 m68k_find_selection (const struct m68k_target_selection **entry,
401 const struct m68k_target_selection *table,
406 for (i = 0; table[i].name; i++)
407 if (strcmp (table[i].name, name) == 0)
415 /* Implement TARGET_HANDLE_OPTION. */
418 m68k_handle_option (size_t code, const char *arg, int value)
423 return m68k_find_selection (&m68k_arch_entry, all_isas, arg);
426 return m68k_find_selection (&m68k_cpu_entry, all_devices, arg);
429 return m68k_find_selection (&m68k_tune_entry, all_microarchs, arg);
432 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206");
435 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5206e");
438 return m68k_find_selection (&m68k_cpu_entry, all_devices, "528x");
441 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5307");
444 return m68k_find_selection (&m68k_cpu_entry, all_devices, "5407");
447 return m68k_find_selection (&m68k_cpu_entry, all_devices, "547x");
451 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68000");
454 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68010");
458 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68020");
461 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
463 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
466 return (m68k_find_selection (&m68k_tune_entry, all_microarchs,
468 && m68k_find_selection (&m68k_cpu_entry, all_devices, "68020"));
471 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68030");
474 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68040");
477 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68060");
480 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68302");
484 return m68k_find_selection (&m68k_cpu_entry, all_devices, "68332");
486 case OPT_mshared_library_id_:
487 if (value > MAX_LIBRARY_ID)
488 error ("-mshared-library-id=%s is not between 0 and %d",
489 arg, MAX_LIBRARY_ID);
491 asprintf ((char **) &m68k_library_id_string, "%d", (value * -4) - 4);
499 /* Sometimes certain combinations of command options do not make
500 sense on a particular target machine. You can define a macro
501 `OVERRIDE_OPTIONS' to take account of this. This macro, if
502 defined, is executed once just after all the command options have
505 Don't use this macro to turn on various extra optimizations for
506 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
509 override_options (void)
511 const struct m68k_target_selection *entry;
512 unsigned long target_mask;
520 -march=ARCH should generate code that runs any processor
521 implementing architecture ARCH. -mcpu=CPU should override -march
522 and should generate code that runs on processor CPU, making free
523 use of any instructions that CPU understands. -mtune=UARCH applies
524 on top of -mcpu or -march and optimizes the code for UARCH. It does
525 not change the target architecture. */
528 /* Complain if the -march setting is for a different microarchitecture,
529 or includes flags that the -mcpu setting doesn't. */
531 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
532 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
533 warning (0, "-mcpu=%s conflicts with -march=%s",
534 m68k_cpu_entry->name, m68k_arch_entry->name);
536 entry = m68k_cpu_entry;
539 entry = m68k_arch_entry;
542 entry = all_devices + TARGET_CPU_DEFAULT;
544 m68k_cpu_flags = entry->flags;
546 /* Use the architecture setting to derive default values for
550 /* ColdFire is lenient about alignment. */
551 if (!TARGET_COLDFIRE)
552 target_mask |= MASK_STRICT_ALIGNMENT;
554 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
555 target_mask |= MASK_BITFIELD;
556 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
557 target_mask |= MASK_CF_HWDIV;
558 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
559 target_mask |= MASK_HARD_FLOAT;
560 target_flags |= target_mask & ~target_flags_explicit;
562 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
563 m68k_cpu = entry->device;
565 m68k_tune = m68k_tune_entry->microarch;
566 #ifdef M68K_DEFAULT_TUNE
567 else if (!m68k_cpu_entry && !m68k_arch_entry)
568 m68k_tune = M68K_DEFAULT_TUNE;
571 m68k_tune = entry->microarch;
573 /* Set the type of FPU. */
574 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
575 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
578 /* Sanity check to ensure that msep-data and mid-sahred-library are not
579 * both specified together. Doing so simply doesn't make sense.
581 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
582 error ("cannot specify both -msep-data and -mid-shared-library");
584 /* If we're generating code for a separate A5 relative data segment,
585 * we've got to enable -fPIC as well. This might be relaxable to
586 * -fpic but it hasn't been tested properly.
588 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
591 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
592 error if the target does not support them. */
593 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
594 error ("-mpcrel -fPIC is not currently supported on selected cpu");
596 /* ??? A historic way of turning on pic, or is this intended to
597 be an embedded thing that doesn't have the same name binding
598 significance that it does on hosted ELF systems? */
599 if (TARGET_PCREL && flag_pic == 0)
604 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
606 m68k_symbolic_jump = "jra %a0";
608 else if (TARGET_ID_SHARED_LIBRARY)
609 /* All addresses must be loaded from the GOT. */
611 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
614 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
616 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
619 /* No unconditional long branch */;
620 else if (TARGET_PCREL)
621 m68k_symbolic_jump = "bra%.l %c0";
623 m68k_symbolic_jump = "bra%.l %p0";
624 /* Turn off function cse if we are doing PIC. We always want
625 function call to be done as `bsr foo@PLTPC'. */
626 /* ??? It's traditional to do this for -mpcrel too, but it isn't
627 clear how intentional that is. */
628 flag_no_function_cse = 1;
631 switch (m68k_symbolic_call_var)
633 case M68K_SYMBOLIC_CALL_JSR:
634 m68k_symbolic_call = "jsr %a0";
637 case M68K_SYMBOLIC_CALL_BSR_C:
638 m68k_symbolic_call = "bsr%.l %c0";
641 case M68K_SYMBOLIC_CALL_BSR_P:
642 m68k_symbolic_call = "bsr%.l %p0";
645 case M68K_SYMBOLIC_CALL_NONE:
646 gcc_assert (m68k_symbolic_call == NULL);
653 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
654 if (align_labels > 2)
656 warning (0, "-falign-labels=%d is not supported", align_labels);
661 warning (0, "-falign-loops=%d is not supported", align_loops);
666 SUBTARGET_OVERRIDE_OPTIONS;
668 /* Setup scheduling options. */
670 m68k_sched_cpu = CPU_CF_V2;
673 m68k_sched_cpu = CPU_UNKNOWN;
674 flag_schedule_insns = 0;
675 flag_schedule_insns_after_reload = 0;
676 flag_modulo_sched = 0;
680 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
681 given argument and NAME is the argument passed to -mcpu. Return NULL
682 if -mcpu was not passed. */
685 m68k_cpp_cpu_ident (const char *prefix)
689 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
692 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
693 given argument and NAME is the name of the representative device for
694 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
697 m68k_cpp_cpu_family (const char *prefix)
701 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
704 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
705 "interrupt_handler" attribute and interrupt_thread if FUNC has an
706 "interrupt_thread" attribute. Otherwise, return
707 m68k_fk_normal_function. */
709 enum m68k_function_kind
710 m68k_get_function_kind (tree func)
714 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
716 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
718 return m68k_fk_interrupt_handler;
720 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
722 return m68k_fk_interrupt_handler;
724 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
726 return m68k_fk_interrupt_thread;
728 return m68k_fk_normal_function;
731 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
732 struct attribute_spec.handler. */
734 m68k_handle_fndecl_attribute (tree *node, tree name,
735 tree args ATTRIBUTE_UNUSED,
736 int flags ATTRIBUTE_UNUSED,
739 if (TREE_CODE (*node) != FUNCTION_DECL)
741 warning (OPT_Wattributes, "%qs attribute only applies to functions",
742 IDENTIFIER_POINTER (name));
743 *no_add_attrs = true;
746 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
748 error ("multiple interrupt attributes not allowed");
749 *no_add_attrs = true;
753 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
755 error ("interrupt_thread is available only on fido");
756 *no_add_attrs = true;
763 m68k_compute_frame_layout (void)
767 enum m68k_function_kind func_kind =
768 m68k_get_function_kind (current_function_decl);
769 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
770 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
772 /* Only compute the frame once per function.
773 Don't cache information until reload has been completed. */
774 if (current_frame.funcdef_no == current_function_funcdef_no
778 current_frame.size = (get_frame_size () + 3) & -4;
782 /* Interrupt thread does not need to save any register. */
783 if (!interrupt_thread)
784 for (regno = 0; regno < 16; regno++)
785 if (m68k_save_reg (regno, interrupt_handler))
787 mask |= 1 << (regno - D0_REG);
790 current_frame.offset = saved * 4;
791 current_frame.reg_no = saved;
792 current_frame.reg_mask = mask;
794 current_frame.foffset = 0;
796 if (TARGET_HARD_FLOAT)
798 /* Interrupt thread does not need to save any register. */
799 if (!interrupt_thread)
800 for (regno = 16; regno < 24; regno++)
801 if (m68k_save_reg (regno, interrupt_handler))
803 mask |= 1 << (regno - FP0_REG);
806 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
807 current_frame.offset += current_frame.foffset;
809 current_frame.fpu_no = saved;
810 current_frame.fpu_mask = mask;
812 /* Remember what function this frame refers to. */
813 current_frame.funcdef_no = current_function_funcdef_no;
817 m68k_initial_elimination_offset (int from, int to)
820 /* The arg pointer points 8 bytes before the start of the arguments,
821 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
822 frame pointer in most frames. */
823 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
824 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
825 return argptr_offset;
827 m68k_compute_frame_layout ();
829 gcc_assert (to == STACK_POINTER_REGNUM);
832 case ARG_POINTER_REGNUM:
833 return current_frame.offset + current_frame.size - argptr_offset;
834 case FRAME_POINTER_REGNUM:
835 return current_frame.offset + current_frame.size;
841 /* Refer to the array `regs_ever_live' to determine which registers
842 to save; `regs_ever_live[I]' is nonzero if register number I
843 is ever used in the function. This function is responsible for
844 knowing which registers should not be saved even if used.
845 Return true if we need to save REGNO. */
848 m68k_save_reg (unsigned int regno, bool interrupt_handler)
850 if (flag_pic && regno == PIC_REG)
852 if (current_function_saves_all_registers)
854 if (current_function_uses_pic_offset_table)
856 /* Reload may introduce constant pool references into a function
857 that thitherto didn't need a PIC register. Note that the test
858 above will not catch that case because we will only set
859 current_function_uses_pic_offset_table when emitting
860 the address reloads. */
861 if (current_function_uses_const_pool)
865 if (current_function_calls_eh_return)
870 unsigned int test = EH_RETURN_DATA_REGNO (i);
871 if (test == INVALID_REGNUM)
878 /* Fixed regs we never touch. */
879 if (fixed_regs[regno])
882 /* The frame pointer (if it is such) is handled specially. */
883 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
886 /* Interrupt handlers must also save call_used_regs
887 if they are live or when calling nested functions. */
888 if (interrupt_handler)
890 if (df_regs_ever_live_p (regno))
893 if (!current_function_is_leaf && call_used_regs[regno])
897 /* Never need to save registers that aren't touched. */
898 if (!df_regs_ever_live_p (regno))
901 /* Otherwise save everything that isn't call-clobbered. */
902 return !call_used_regs[regno];
905 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
906 the lowest memory address. COUNT is the number of registers to be
907 moved, with register REGNO + I being moved if bit I of MASK is set.
908 STORE_P specifies the direction of the move and ADJUST_STACK_P says
909 whether or not this is pre-decrement (if STORE_P) or post-increment
910 (if !STORE_P) operation. */
913 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
914 unsigned int count, unsigned int regno,
915 unsigned int mask, bool store_p, bool adjust_stack_p)
918 rtx body, addr, src, operands[2];
919 enum machine_mode mode;
921 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
922 mode = reg_raw_mode[regno];
927 src = plus_constant (base, (count
928 * GET_MODE_SIZE (mode)
929 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
930 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src);
933 for (; mask != 0; mask >>= 1, regno++)
936 addr = plus_constant (base, offset);
937 operands[!store_p] = gen_frame_mem (mode, addr);
938 operands[store_p] = gen_rtx_REG (mode, regno);
939 XVECEXP (body, 0, i++)
940 = gen_rtx_SET (VOIDmode, operands[0], operands[1]);
941 offset += GET_MODE_SIZE (mode);
943 gcc_assert (i == XVECLEN (body, 0));
945 return emit_insn (body);
948 /* Make INSN a frame-related instruction. */
951 m68k_set_frame_related (rtx insn)
956 RTX_FRAME_RELATED_P (insn) = 1;
957 body = PATTERN (insn);
958 if (GET_CODE (body) == PARALLEL)
959 for (i = 0; i < XVECLEN (body, 0); i++)
960 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
963 /* Emit RTL for the "prologue" define_expand. */
966 m68k_expand_prologue (void)
968 HOST_WIDE_INT fsize_with_regs;
969 rtx limit, src, dest, insn;
971 m68k_compute_frame_layout ();
973 /* If the stack limit is a symbol, we can check it here,
974 before actually allocating the space. */
975 if (current_function_limit_stack
976 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
978 limit = plus_constant (stack_limit_rtx, current_frame.size + 4);
979 if (!LEGITIMATE_CONSTANT_P (limit))
981 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
982 limit = gen_rtx_REG (Pmode, D0_REG);
984 emit_insn (gen_cmpsi (stack_pointer_rtx, limit));
985 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
986 cc0_rtx, const0_rtx),
990 fsize_with_regs = current_frame.size;
993 /* ColdFire's move multiple instructions do not allow pre-decrement
994 addressing. Add the size of movem saves to the initial stack
995 allocation instead. */
996 if (current_frame.reg_no >= MIN_MOVEM_REGS)
997 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
998 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
999 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1002 if (frame_pointer_needed)
1004 if (fsize_with_regs == 0 && TUNE_68040)
1006 /* On the 68040, two separate moves are faster than link.w 0. */
1007 dest = gen_frame_mem (Pmode,
1008 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1009 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1010 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1011 stack_pointer_rtx));
1013 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1014 m68k_set_frame_related
1015 (emit_insn (gen_link (frame_pointer_rtx,
1016 GEN_INT (-4 - fsize_with_regs))));
1019 m68k_set_frame_related
1020 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1021 m68k_set_frame_related
1022 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1024 GEN_INT (-fsize_with_regs))));
1027 else if (fsize_with_regs != 0)
1028 m68k_set_frame_related
1029 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1031 GEN_INT (-fsize_with_regs))));
1033 if (current_frame.fpu_mask)
1035 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1037 m68k_set_frame_related
1038 (m68k_emit_movem (stack_pointer_rtx,
1039 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1040 current_frame.fpu_no, FP0_REG,
1041 current_frame.fpu_mask, true, true));
1046 /* If we're using moveml to save the integer registers,
1047 the stack pointer will point to the bottom of the moveml
1048 save area. Find the stack offset of the first FP register. */
1049 if (current_frame.reg_no < MIN_MOVEM_REGS)
1052 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1053 m68k_set_frame_related
1054 (m68k_emit_movem (stack_pointer_rtx, offset,
1055 current_frame.fpu_no, FP0_REG,
1056 current_frame.fpu_mask, true, false));
1060 /* If the stack limit is not a symbol, check it here.
1061 This has the disadvantage that it may be too late... */
1062 if (current_function_limit_stack)
1064 if (REG_P (stack_limit_rtx))
1066 emit_insn (gen_cmpsi (stack_pointer_rtx, stack_limit_rtx));
1067 emit_insn (gen_conditional_trap (gen_rtx_LTU (VOIDmode,
1068 cc0_rtx, const0_rtx),
1071 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1072 warning (0, "stack limit expression is not supported");
1075 if (current_frame.reg_no < MIN_MOVEM_REGS)
1077 /* Store each register separately in the same order moveml does. */
1080 for (i = 16; i-- > 0; )
1081 if (current_frame.reg_mask & (1 << i))
1083 src = gen_rtx_REG (SImode, D0_REG + i);
1084 dest = gen_frame_mem (SImode,
1085 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1086 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1091 if (TARGET_COLDFIRE)
1092 /* The required register save space has already been allocated.
1093 The first register should be stored at (%sp). */
1094 m68k_set_frame_related
1095 (m68k_emit_movem (stack_pointer_rtx, 0,
1096 current_frame.reg_no, D0_REG,
1097 current_frame.reg_mask, true, false));
1099 m68k_set_frame_related
1100 (m68k_emit_movem (stack_pointer_rtx,
1101 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1102 current_frame.reg_no, D0_REG,
1103 current_frame.reg_mask, true, true));
1108 && current_function_uses_pic_offset_table)
1109 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
1112 /* Return true if a simple (return) instruction is sufficient for this
1113 instruction (i.e. if no epilogue is needed). */
1116 m68k_use_return_insn (void)
1118 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1121 m68k_compute_frame_layout ();
1122 return current_frame.offset == 0;
1125 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1126 SIBCALL_P says which.
1128 The function epilogue should not depend on the current stack pointer!
1129 It should use the frame pointer only, if there is a frame pointer.
1130 This is mandatory because of alloca; we also take advantage of it to
1131 omit stack adjustments before returning. */
1134 m68k_expand_epilogue (bool sibcall_p)
1136 HOST_WIDE_INT fsize, fsize_with_regs;
1137 bool big, restore_from_sp;
1139 m68k_compute_frame_layout ();
1141 fsize = current_frame.size;
1143 restore_from_sp = false;
1145 /* FIXME : current_function_is_leaf below is too strong.
1146 What we really need to know there is if there could be pending
1147 stack adjustment needed at that point. */
1148 restore_from_sp = (!frame_pointer_needed
1149 || (!current_function_calls_alloca
1150 && current_function_is_leaf));
1152 /* fsize_with_regs is the size we need to adjust the sp when
1153 popping the frame. */
1154 fsize_with_regs = fsize;
1155 if (TARGET_COLDFIRE && restore_from_sp)
1157 /* ColdFire's move multiple instructions do not allow post-increment
1158 addressing. Add the size of movem loads to the final deallocation
1160 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1161 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1162 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1163 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1166 if (current_frame.offset + fsize >= 0x8000
1168 && (current_frame.reg_mask || current_frame.fpu_mask))
1171 && (current_frame.reg_no >= MIN_MOVEM_REGS
1172 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1174 /* ColdFire's move multiple instructions do not support the
1175 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1176 stack-based restore. */
1177 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1178 GEN_INT (-(current_frame.offset + fsize)));
1179 emit_insn (gen_addsi3 (stack_pointer_rtx,
1180 gen_rtx_REG (Pmode, A1_REG),
1181 frame_pointer_rtx));
1182 restore_from_sp = true;
1186 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1192 if (current_frame.reg_no < MIN_MOVEM_REGS)
1194 /* Restore each register separately in the same order moveml does. */
1196 HOST_WIDE_INT offset;
1198 offset = current_frame.offset + fsize;
1199 for (i = 0; i < 16; i++)
1200 if (current_frame.reg_mask & (1 << i))
1206 /* Generate the address -OFFSET(%fp,%a1.l). */
1207 addr = gen_rtx_REG (Pmode, A1_REG);
1208 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1209 addr = plus_constant (addr, -offset);
1211 else if (restore_from_sp)
1212 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1214 addr = plus_constant (frame_pointer_rtx, -offset);
1215 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1216 gen_frame_mem (SImode, addr));
1217 offset -= GET_MODE_SIZE (SImode);
1220 else if (current_frame.reg_mask)
1223 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1224 gen_rtx_REG (Pmode, A1_REG),
1226 -(current_frame.offset + fsize),
1227 current_frame.reg_no, D0_REG,
1228 current_frame.reg_mask, false, false);
1229 else if (restore_from_sp)
1230 m68k_emit_movem (stack_pointer_rtx, 0,
1231 current_frame.reg_no, D0_REG,
1232 current_frame.reg_mask, false,
1235 m68k_emit_movem (frame_pointer_rtx,
1236 -(current_frame.offset + fsize),
1237 current_frame.reg_no, D0_REG,
1238 current_frame.reg_mask, false, false);
1241 if (current_frame.fpu_no > 0)
1244 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1245 gen_rtx_REG (Pmode, A1_REG),
1247 -(current_frame.foffset + fsize),
1248 current_frame.fpu_no, FP0_REG,
1249 current_frame.fpu_mask, false, false);
1250 else if (restore_from_sp)
1252 if (TARGET_COLDFIRE)
1256 /* If we used moveml to restore the integer registers, the
1257 stack pointer will still point to the bottom of the moveml
1258 save area. Find the stack offset of the first FP
1260 if (current_frame.reg_no < MIN_MOVEM_REGS)
1263 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1264 m68k_emit_movem (stack_pointer_rtx, offset,
1265 current_frame.fpu_no, FP0_REG,
1266 current_frame.fpu_mask, false, false);
1269 m68k_emit_movem (stack_pointer_rtx, 0,
1270 current_frame.fpu_no, FP0_REG,
1271 current_frame.fpu_mask, false, true);
1274 m68k_emit_movem (frame_pointer_rtx,
1275 -(current_frame.foffset + fsize),
1276 current_frame.fpu_no, FP0_REG,
1277 current_frame.fpu_mask, false, false);
1280 if (frame_pointer_needed)
1281 emit_insn (gen_unlink (frame_pointer_rtx));
1282 else if (fsize_with_regs)
1283 emit_insn (gen_addsi3 (stack_pointer_rtx,
1285 GEN_INT (fsize_with_regs)));
1287 if (current_function_calls_eh_return)
1288 emit_insn (gen_addsi3 (stack_pointer_rtx,
1290 EH_RETURN_STACKADJ_RTX));
1293 emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1296 /* Return true if X is a valid comparison operator for the dbcc
1299 Note it rejects floating point comparison operators.
1300 (In the future we could use Fdbcc).
1302 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1305 valid_dbcc_comparison_p_2 (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1307 switch (GET_CODE (x))
1309 case EQ: case NE: case GTU: case LTU:
1313 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1315 case GT: case LT: case GE: case LE:
1316 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1322 /* Return nonzero if flags are currently in the 68881 flag register. */
1324 flags_in_68881 (void)
1326 /* We could add support for these in the future */
1327 return cc_status.flags & CC_IN_68881;
1330 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1333 m68k_ok_for_sibcall_p (tree decl, tree exp)
1335 enum m68k_function_kind kind;
1337 /* We cannot use sibcalls for nested functions because we use the
1338 static chain register for indirect calls. */
1339 if (CALL_EXPR_STATIC_CHAIN (exp))
1342 kind = m68k_get_function_kind (current_function_decl);
1343 if (kind == m68k_fk_normal_function)
1344 /* We can always sibcall from a normal function, because it's
1345 undefined if it is calling an interrupt function. */
1348 /* Otherwise we can only sibcall if the function kind is known to be
1350 if (decl && m68k_get_function_kind (decl) == kind)
1356 /* Convert X to a legitimate function call memory reference and return the
1360 m68k_legitimize_call_address (rtx x)
1362 gcc_assert (MEM_P (x));
1363 if (call_operand (XEXP (x, 0), VOIDmode))
1365 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1368 /* Likewise for sibling calls. */
1371 m68k_legitimize_sibcall_address (rtx x)
1373 gcc_assert (MEM_P (x));
1374 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1377 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1378 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1381 /* Output a dbCC; jCC sequence. Note we do not handle the
1382 floating point version of this sequence (Fdbcc). We also
1383 do not handle alternative conditions when CC_NO_OVERFLOW is
1384 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1385 kick those out before we get here. */
1388 output_dbcc_and_branch (rtx *operands)
1390 switch (GET_CODE (operands[3]))
1393 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1397 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1401 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1405 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1409 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1413 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1417 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1421 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1425 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1429 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1436 /* If the decrement is to be done in SImode, then we have
1437 to compensate for the fact that dbcc decrements in HImode. */
1438 switch (GET_MODE (operands[0]))
1441 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1453 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1456 enum rtx_code op_code = GET_CODE (op);
1458 /* This does not produce a useful cc. */
1461 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1462 below. Swap the operands and change the op if these requirements
1463 are not fulfilled. */
1464 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1468 operand1 = operand2;
1470 op_code = swap_condition (op_code);
1472 loperands[0] = operand1;
1473 if (GET_CODE (operand1) == REG)
1474 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1476 loperands[1] = adjust_address (operand1, SImode, 4);
1477 if (operand2 != const0_rtx)
1479 loperands[2] = operand2;
1480 if (GET_CODE (operand2) == REG)
1481 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1483 loperands[3] = adjust_address (operand2, SImode, 4);
1485 loperands[4] = gen_label_rtx ();
1486 if (operand2 != const0_rtx)
1487 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1490 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1491 output_asm_insn ("tst%.l %0", loperands);
1493 output_asm_insn ("cmp%.w #0,%0", loperands);
1495 output_asm_insn ("jne %l4", loperands);
1497 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1498 output_asm_insn ("tst%.l %1", loperands);
1500 output_asm_insn ("cmp%.w #0,%1", loperands);
1503 loperands[5] = dest;
1508 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1509 CODE_LABEL_NUMBER (loperands[4]));
1510 output_asm_insn ("seq %5", loperands);
1514 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1515 CODE_LABEL_NUMBER (loperands[4]));
1516 output_asm_insn ("sne %5", loperands);
1520 loperands[6] = gen_label_rtx ();
1521 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1522 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1523 CODE_LABEL_NUMBER (loperands[4]));
1524 output_asm_insn ("sgt %5", loperands);
1525 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1526 CODE_LABEL_NUMBER (loperands[6]));
1530 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1531 CODE_LABEL_NUMBER (loperands[4]));
1532 output_asm_insn ("shi %5", loperands);
1536 loperands[6] = gen_label_rtx ();
1537 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1538 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1539 CODE_LABEL_NUMBER (loperands[4]));
1540 output_asm_insn ("slt %5", loperands);
1541 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1542 CODE_LABEL_NUMBER (loperands[6]));
1546 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1547 CODE_LABEL_NUMBER (loperands[4]));
1548 output_asm_insn ("scs %5", loperands);
1552 loperands[6] = gen_label_rtx ();
1553 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1554 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1555 CODE_LABEL_NUMBER (loperands[4]));
1556 output_asm_insn ("sge %5", loperands);
1557 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1558 CODE_LABEL_NUMBER (loperands[6]));
1562 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1563 CODE_LABEL_NUMBER (loperands[4]));
1564 output_asm_insn ("scc %5", loperands);
1568 loperands[6] = gen_label_rtx ();
1569 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1570 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1571 CODE_LABEL_NUMBER (loperands[4]));
1572 output_asm_insn ("sle %5", loperands);
1573 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1574 CODE_LABEL_NUMBER (loperands[6]));
1578 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1579 CODE_LABEL_NUMBER (loperands[4]));
1580 output_asm_insn ("sls %5", loperands);
1590 output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
1592 operands[0] = countop;
1593 operands[1] = dataop;
1595 if (GET_CODE (countop) == CONST_INT)
1597 register int count = INTVAL (countop);
1598 /* If COUNT is bigger than size of storage unit in use,
1599 advance to the containing unit of same size. */
1600 if (count > signpos)
1602 int offset = (count & ~signpos) / 8;
1603 count = count & signpos;
1604 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1606 if (count == signpos)
1607 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1609 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1611 /* These three statements used to use next_insns_test_no...
1612 but it appears that this should do the same job. */
1614 && next_insn_tests_no_inequality (insn))
1617 && next_insn_tests_no_inequality (insn))
1620 && next_insn_tests_no_inequality (insn))
1622 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1623 On some m68k variants unfortunately that's slower than btst.
1624 On 68000 and higher, that should also work for all HImode operands. */
1625 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1627 if (count == 3 && DATA_REG_P (operands[1])
1628 && next_insn_tests_no_inequality (insn))
1630 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1631 return "move%.w %1,%%ccr";
1633 if (count == 2 && DATA_REG_P (operands[1])
1634 && next_insn_tests_no_inequality (insn))
1636 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1637 return "move%.w %1,%%ccr";
1639 /* count == 1 followed by bvc/bvs and
1640 count == 0 followed by bcc/bcs are also possible, but need
1641 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1644 cc_status.flags = CC_NOT_NEGATIVE;
1646 return "btst %0,%1";
1649 /* Return true if X is a legitimate base register. STRICT_P says
1650 whether we need strict checking. */
1653 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1655 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1656 if (!strict_p && GET_CODE (x) == SUBREG)
1661 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1662 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1665 /* Return true if X is a legitimate index register. STRICT_P says
1666 whether we need strict checking. */
1669 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1671 if (!strict_p && GET_CODE (x) == SUBREG)
1676 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1677 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1680 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1681 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1682 ADDRESS if so. STRICT_P says whether we need strict checking. */
1685 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1689 /* Check for a scale factor. */
1691 if ((TARGET_68020 || TARGET_COLDFIRE)
1692 && GET_CODE (x) == MULT
1693 && GET_CODE (XEXP (x, 1)) == CONST_INT
1694 && (INTVAL (XEXP (x, 1)) == 2
1695 || INTVAL (XEXP (x, 1)) == 4
1696 || (INTVAL (XEXP (x, 1)) == 8
1697 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1699 scale = INTVAL (XEXP (x, 1));
1703 /* Check for a word extension. */
1704 if (!TARGET_COLDFIRE
1705 && GET_CODE (x) == SIGN_EXTEND
1706 && GET_MODE (XEXP (x, 0)) == HImode)
1709 if (m68k_legitimate_index_reg_p (x, strict_p))
1711 address->scale = scale;
1719 /* Return true if X is an illegitimate symbolic constant. */
1722 m68k_illegitimate_symbolic_constant_p (rtx x)
1726 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1728 split_const (x, &base, &offset);
1729 if (GET_CODE (base) == SYMBOL_REF
1730 && !offset_within_block_p (base, INTVAL (offset)))
1736 /* Return true if X is a legitimate constant address that can reach
1737 bytes in the range [X, X + REACH). STRICT_P says whether we need
1741 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1745 if (!CONSTANT_ADDRESS_P (x))
1749 && !(strict_p && TARGET_PCREL)
1750 && symbolic_operand (x, VOIDmode))
1753 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1755 split_const (x, &base, &offset);
1756 if (GET_CODE (base) == SYMBOL_REF
1757 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1764 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1765 labels will become jump tables. */
1768 m68k_jump_table_ref_p (rtx x)
1770 if (GET_CODE (x) != LABEL_REF)
1774 if (!NEXT_INSN (x) && !PREV_INSN (x))
1777 x = next_nonnote_insn (x);
1778 return x && JUMP_TABLE_DATA_P (x);
1781 /* Return true if X is a legitimate address for values of mode MODE.
1782 STRICT_P says whether strict checking is needed. If the address
1783 is valid, describe its components in *ADDRESS. */
1786 m68k_decompose_address (enum machine_mode mode, rtx x,
1787 bool strict_p, struct m68k_address *address)
1791 memset (address, 0, sizeof (*address));
1793 if (mode == BLKmode)
1796 reach = GET_MODE_SIZE (mode);
1798 /* Check for (An) (mode 2). */
1799 if (m68k_legitimate_base_reg_p (x, strict_p))
1805 /* Check for -(An) and (An)+ (modes 3 and 4). */
1806 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
1807 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1809 address->code = GET_CODE (x);
1810 address->base = XEXP (x, 0);
1814 /* Check for (d16,An) (mode 5). */
1815 if (GET_CODE (x) == PLUS
1816 && GET_CODE (XEXP (x, 1)) == CONST_INT
1817 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
1818 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
1820 address->base = XEXP (x, 0);
1821 address->offset = XEXP (x, 1);
1825 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1826 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1829 && GET_CODE (x) == PLUS
1830 && XEXP (x, 0) == pic_offset_table_rtx
1831 && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
1832 || GET_CODE (XEXP (x, 1)) == LABEL_REF))
1834 address->base = XEXP (x, 0);
1835 address->offset = XEXP (x, 1);
1839 /* The ColdFire FPU only accepts addressing modes 2-5. */
1840 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1843 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1844 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1845 All these modes are variations of mode 7. */
1846 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
1848 address->offset = x;
1852 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1855 ??? do_tablejump creates these addresses before placing the target
1856 label, so we have to assume that unplaced labels are jump table
1857 references. It seems unlikely that we would ever generate indexed
1858 accesses to unplaced labels in other cases. */
1859 if (GET_CODE (x) == PLUS
1860 && m68k_jump_table_ref_p (XEXP (x, 1))
1861 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1863 address->offset = XEXP (x, 1);
1867 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1868 (bd,An,Xn.SIZE*SCALE) addresses. */
1872 /* Check for a nonzero base displacement. */
1873 if (GET_CODE (x) == PLUS
1874 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
1876 address->offset = XEXP (x, 1);
1880 /* Check for a suppressed index register. */
1881 if (m68k_legitimate_base_reg_p (x, strict_p))
1887 /* Check for a suppressed base register. Do not allow this case
1888 for non-symbolic offsets as it effectively gives gcc freedom
1889 to treat data registers as base registers, which can generate
1892 && symbolic_operand (address->offset, VOIDmode)
1893 && m68k_decompose_index (x, strict_p, address))
1898 /* Check for a nonzero base displacement. */
1899 if (GET_CODE (x) == PLUS
1900 && GET_CODE (XEXP (x, 1)) == CONST_INT
1901 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
1903 address->offset = XEXP (x, 1);
1908 /* We now expect the sum of a base and an index. */
1909 if (GET_CODE (x) == PLUS)
1911 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
1912 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
1914 address->base = XEXP (x, 0);
1918 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
1919 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
1921 address->base = XEXP (x, 1);
1928 /* Return true if X is a legitimate address for values of mode MODE.
1929 STRICT_P says whether strict checking is needed. */
1932 m68k_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1934 struct m68k_address address;
1936 return m68k_decompose_address (mode, x, strict_p, &address);
1939 /* Return true if X is a memory, describing its address in ADDRESS if so.
1940 Apply strict checking if called during or after reload. */
1943 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
1946 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
1947 reload_in_progress || reload_completed,
1951 /* Return true if X matches the 'Q' constraint. It must be a memory
1952 with a base address and no constant offset or index. */
1955 m68k_matches_q_p (rtx x)
1957 struct m68k_address address;
1959 return (m68k_legitimate_mem_p (x, &address)
1960 && address.code == UNKNOWN
1966 /* Return true if X matches the 'U' constraint. It must be a base address
1967 with a constant offset and no index. */
1970 m68k_matches_u_p (rtx x)
1972 struct m68k_address address;
1974 return (m68k_legitimate_mem_p (x, &address)
1975 && address.code == UNKNOWN
1981 /* Legitimize PIC addresses. If the address is already
1982 position-independent, we return ORIG. Newly generated
1983 position-independent addresses go to REG. If we need more
1984 than one register, we lose.
1986 An address is legitimized by making an indirect reference
1987 through the Global Offset Table with the name of the symbol
1990 The assembler and linker are responsible for placing the
1991 address of the symbol in the GOT. The function prologue
1992 is responsible for initializing a5 to the starting address
1995 The assembler is also responsible for translating a symbol name
1996 into a constant displacement from the start of the GOT.
1998 A quick example may make things a little clearer:
2000 When not generating PIC code to store the value 12345 into _foo
2001 we would generate the following code:
2005 When generating PIC two transformations are made. First, the compiler
2006 loads the address of foo into a register. So the first transformation makes:
2011 The code in movsi will intercept the lea instruction and call this
2012 routine which will transform the instructions into:
2014 movel a5@(_foo:w), a0
2018 That (in a nutshell) is how *all* symbol and label references are
2022 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
2027 /* First handle a simple SYMBOL_REF or LABEL_REF */
2028 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2032 pic_ref = gen_rtx_MEM (Pmode,
2033 gen_rtx_PLUS (Pmode,
2034 pic_offset_table_rtx, orig));
2035 current_function_uses_pic_offset_table = 1;
2036 MEM_READONLY_P (pic_ref) = 1;
2037 emit_move_insn (reg, pic_ref);
2040 else if (GET_CODE (orig) == CONST)
2044 /* Make sure this has not already been legitimized. */
2045 if (GET_CODE (XEXP (orig, 0)) == PLUS
2046 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2051 /* legitimize both operands of the PLUS */
2052 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2054 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2055 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2056 base == reg ? 0 : reg);
2058 if (GET_CODE (orig) == CONST_INT)
2059 return plus_constant (base, INTVAL (orig));
2060 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2061 /* Likewise, should we set special REG_NOTEs here? */
2068 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2070 /* Return the type of move that should be used for integer I. */
2073 m68k_const_method (HOST_WIDE_INT i)
2080 /* The ColdFire doesn't have byte or word operations. */
2081 /* FIXME: This may not be useful for the m68060 either. */
2082 if (!TARGET_COLDFIRE)
2084 /* if -256 < N < 256 but N is not in range for a moveq
2085 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2086 if (USE_MOVQ (i ^ 0xff))
2088 /* Likewise, try with not.w */
2089 if (USE_MOVQ (i ^ 0xffff))
2091 /* This is the only value where neg.w is useful */
2096 /* Try also with swap. */
2098 if (USE_MOVQ ((u >> 16) | (u << 16)))
2103 /* Try using MVZ/MVS with an immediate value to load constants. */
2104 if (i >= 0 && i <= 65535)
2106 if (i >= -32768 && i <= 32767)
2110 /* Otherwise, use move.l */
2114 /* Return the cost of moving constant I into a data register. */
2117 const_int_cost (HOST_WIDE_INT i)
2119 switch (m68k_const_method (i))
2122 /* Constants between -128 and 127 are cheap due to moveq. */
2130 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2140 m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
2145 /* Constant zero is super cheap due to clr instruction. */
2146 if (x == const0_rtx)
2149 *total = const_int_cost (INTVAL (x));
2159 /* Make 0.0 cheaper than other floating constants to
2160 encourage creating tstsf and tstdf insns. */
2161 if (outer_code == COMPARE
2162 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2168 /* These are vaguely right for a 68020. */
2169 /* The costs for long multiply have been adjusted to work properly
2170 in synth_mult on the 68020, relative to an average of the time
2171 for add and the time for shift, taking away a little more because
2172 sometimes move insns are needed. */
2173 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2179 : TARGET_COLDFIRE ? 3 : 13)
2184 : TUNE_68000_10 || TUNE_CFV2 ? 5 \
2185 : TARGET_COLDFIRE ? 2 : 8)
2188 (TARGET_CF_HWDIV ? 11 \
2189 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2192 /* An lea costs about three times as much as a simple add. */
2193 if (GET_MODE (x) == SImode
2194 && GET_CODE (XEXP (x, 1)) == REG
2195 && GET_CODE (XEXP (x, 0)) == MULT
2196 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2197 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2198 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2199 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2200 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2202 /* lea an@(dx:l:i),am */
2203 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2213 *total = COSTS_N_INSNS(1);
2218 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2220 if (INTVAL (XEXP (x, 1)) < 16)
2221 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2223 /* We're using clrw + swap for these cases. */
2224 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2227 *total = COSTS_N_INSNS (10); /* Worst case. */
2230 /* A shift by a big integer takes an extra instruction. */
2231 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2232 && (INTVAL (XEXP (x, 1)) == 16))
2234 *total = COSTS_N_INSNS (2); /* clrw;swap */
2237 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2238 && !(INTVAL (XEXP (x, 1)) > 0
2239 && INTVAL (XEXP (x, 1)) <= 8))
2241 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2247 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2248 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2249 && GET_MODE (x) == SImode)
2250 *total = COSTS_N_INSNS (MULW_COST);
2251 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2252 *total = COSTS_N_INSNS (MULW_COST);
2254 *total = COSTS_N_INSNS (MULL_COST);
2261 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
2262 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2263 else if (TARGET_CF_HWDIV)
2264 *total = COSTS_N_INSNS (18);
2266 *total = COSTS_N_INSNS (43); /* div.l */
2274 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2278 output_move_const_into_data_reg (rtx *operands)
2282 i = INTVAL (operands[1]);
2283 switch (m68k_const_method (i))
2286 return "mvzw %1,%0";
2288 return "mvsw %1,%0";
2290 return "moveq %1,%0";
2293 operands[1] = GEN_INT (i ^ 0xff);
2294 return "moveq %1,%0\n\tnot%.b %0";
2297 operands[1] = GEN_INT (i ^ 0xffff);
2298 return "moveq %1,%0\n\tnot%.w %0";
2301 return "moveq #-128,%0\n\tneg%.w %0";
2306 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2307 return "moveq %1,%0\n\tswap %0";
2310 return "move%.l %1,%0";
2316 /* Return true if I can be handled by ISA B's mov3q instruction. */
2319 valid_mov3q_const (HOST_WIDE_INT i)
2321 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
2324 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2325 I is the value of OPERANDS[1]. */
2328 output_move_simode_const (rtx *operands)
2334 src = INTVAL (operands[1]);
2336 && (DATA_REG_P (dest) || MEM_P (dest))
2337 /* clr insns on 68000 read before writing. */
2338 && ((TARGET_68010 || TARGET_COLDFIRE)
2339 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
2341 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
2342 return "mov3q%.l %1,%0";
2343 else if (src == 0 && ADDRESS_REG_P (dest))
2344 return "sub%.l %0,%0";
2345 else if (DATA_REG_P (dest))
2346 return output_move_const_into_data_reg (operands);
2347 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
2349 if (valid_mov3q_const (src))
2350 return "mov3q%.l %1,%0";
2351 return "move%.w %1,%0";
2353 else if (MEM_P (dest)
2354 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
2355 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
2356 && IN_RANGE (src, -0x8000, 0x7fff))
2358 if (valid_mov3q_const (src))
2359 return "mov3q%.l %1,%-";
2362 return "move%.l %1,%0";
2366 output_move_simode (rtx *operands)
2368 if (GET_CODE (operands[1]) == CONST_INT)
2369 return output_move_simode_const (operands);
2370 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2371 || GET_CODE (operands[1]) == CONST)
2372 && push_operand (operands[0], SImode))
2374 else if ((GET_CODE (operands[1]) == SYMBOL_REF
2375 || GET_CODE (operands[1]) == CONST)
2376 && ADDRESS_REG_P (operands[0]))
2377 return "lea %a1,%0";
2378 return "move%.l %1,%0";
2382 output_move_himode (rtx *operands)
2384 if (GET_CODE (operands[1]) == CONST_INT)
2386 if (operands[1] == const0_rtx
2387 && (DATA_REG_P (operands[0])
2388 || GET_CODE (operands[0]) == MEM)
2389 /* clr insns on 68000 read before writing. */
2390 && ((TARGET_68010 || TARGET_COLDFIRE)
2391 || !(GET_CODE (operands[0]) == MEM
2392 && MEM_VOLATILE_P (operands[0]))))
2394 else if (operands[1] == const0_rtx
2395 && ADDRESS_REG_P (operands[0]))
2396 return "sub%.l %0,%0";
2397 else if (DATA_REG_P (operands[0])
2398 && INTVAL (operands[1]) < 128
2399 && INTVAL (operands[1]) >= -128)
2400 return "moveq %1,%0";
2401 else if (INTVAL (operands[1]) < 0x8000
2402 && INTVAL (operands[1]) >= -0x8000)
2403 return "move%.w %1,%0";
2405 else if (CONSTANT_P (operands[1]))
2406 return "move%.l %1,%0";
2407 return "move%.w %1,%0";
2411 output_move_qimode (rtx *operands)
2413 /* 68k family always modifies the stack pointer by at least 2, even for
2414 byte pushes. The 5200 (ColdFire) does not do this. */
2416 /* This case is generated by pushqi1 pattern now. */
2417 gcc_assert (!(GET_CODE (operands[0]) == MEM
2418 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
2419 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
2420 && ! ADDRESS_REG_P (operands[1])
2421 && ! TARGET_COLDFIRE));
2423 /* clr and st insns on 68000 read before writing. */
2424 if (!ADDRESS_REG_P (operands[0])
2425 && ((TARGET_68010 || TARGET_COLDFIRE)
2426 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2428 if (operands[1] == const0_rtx)
2430 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
2431 && GET_CODE (operands[1]) == CONST_INT
2432 && (INTVAL (operands[1]) & 255) == 255)
2438 if (GET_CODE (operands[1]) == CONST_INT
2439 && DATA_REG_P (operands[0])
2440 && INTVAL (operands[1]) < 128
2441 && INTVAL (operands[1]) >= -128)
2442 return "moveq %1,%0";
2443 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
2444 return "sub%.l %0,%0";
2445 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
2446 return "move%.l %1,%0";
2447 /* 68k family (including the 5200 ColdFire) does not support byte moves to
2448 from address registers. */
2449 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
2450 return "move%.w %1,%0";
2451 return "move%.b %1,%0";
2455 output_move_stricthi (rtx *operands)
2457 if (operands[1] == const0_rtx
2458 /* clr insns on 68000 read before writing. */
2459 && ((TARGET_68010 || TARGET_COLDFIRE)
2460 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2462 return "move%.w %1,%0";
2466 output_move_strictqi (rtx *operands)
2468 if (operands[1] == const0_rtx
2469 /* clr insns on 68000 read before writing. */
2470 && ((TARGET_68010 || TARGET_COLDFIRE)
2471 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2473 return "move%.b %1,%0";
2476 /* Return the best assembler insn template
2477 for moving operands[1] into operands[0] as a fullword. */
2480 singlemove_string (rtx *operands)
2482 if (GET_CODE (operands[1]) == CONST_INT)
2483 return output_move_simode_const (operands);
2484 return "move%.l %1,%0";
2488 /* Output assembler or rtl code to perform a doubleword move insn
2489 with operands OPERANDS.
2490 Pointers to 3 helper functions should be specified:
2491 HANDLE_REG_ADJUST to adjust a register by a small value,
2492 HANDLE_COMPADR to compute an address and
2493 HANDLE_MOVSI to move 4 bytes. */
2496 handle_move_double (rtx operands[2],
2497 void (*handle_reg_adjust) (rtx, int),
2498 void (*handle_compadr) (rtx [2]),
2499 void (*handle_movsi) (rtx [2]))
2503 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
2508 rtx addreg0 = 0, addreg1 = 0;
2509 int dest_overlapped_low = 0;
2510 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
2515 /* First classify both operands. */
2517 if (REG_P (operands[0]))
2519 else if (offsettable_memref_p (operands[0]))
2521 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2523 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2525 else if (GET_CODE (operands[0]) == MEM)
2530 if (REG_P (operands[1]))
2532 else if (CONSTANT_P (operands[1]))
2534 else if (offsettable_memref_p (operands[1]))
2536 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2538 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2540 else if (GET_CODE (operands[1]) == MEM)
2545 /* Check for the cases that the operand constraints are not supposed
2546 to allow to happen. Generating code for these cases is
2548 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
2550 /* If one operand is decrementing and one is incrementing
2551 decrement the former register explicitly
2552 and change that operand into ordinary indexing. */
2554 if (optype0 == PUSHOP && optype1 == POPOP)
2556 operands[0] = XEXP (XEXP (operands[0], 0), 0);
2558 handle_reg_adjust (operands[0], -size);
2560 if (GET_MODE (operands[1]) == XFmode)
2561 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
2562 else if (GET_MODE (operands[0]) == DFmode)
2563 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
2565 operands[0] = gen_rtx_MEM (DImode, operands[0]);
2568 if (optype0 == POPOP && optype1 == PUSHOP)
2570 operands[1] = XEXP (XEXP (operands[1], 0), 0);
2572 handle_reg_adjust (operands[1], -size);
2574 if (GET_MODE (operands[1]) == XFmode)
2575 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
2576 else if (GET_MODE (operands[1]) == DFmode)
2577 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
2579 operands[1] = gen_rtx_MEM (DImode, operands[1]);
2583 /* If an operand is an unoffsettable memory ref, find a register
2584 we can increment temporarily to make it refer to the second word. */
2586 if (optype0 == MEMOP)
2587 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2589 if (optype1 == MEMOP)
2590 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2592 /* Ok, we can do one word at a time.
2593 Normally we do the low-numbered word first,
2594 but if either operand is autodecrementing then we
2595 do the high-numbered word first.
2597 In either case, set up in LATEHALF the operands to use
2598 for the high-numbered word and in some cases alter the
2599 operands in OPERANDS to be suitable for the low-numbered word. */
2603 if (optype0 == REGOP)
2605 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
2606 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2608 else if (optype0 == OFFSOP)
2610 middlehalf[0] = adjust_address (operands[0], SImode, 4);
2611 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2615 middlehalf[0] = adjust_address (operands[0], SImode, 0);
2616 latehalf[0] = adjust_address (operands[0], SImode, 0);
2619 if (optype1 == REGOP)
2621 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
2622 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2624 else if (optype1 == OFFSOP)
2626 middlehalf[1] = adjust_address (operands[1], SImode, 4);
2627 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2629 else if (optype1 == CNSTOP)
2631 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2636 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
2637 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
2638 operands[1] = GEN_INT (l[0]);
2639 middlehalf[1] = GEN_INT (l[1]);
2640 latehalf[1] = GEN_INT (l[2]);
2644 /* No non-CONST_DOUBLE constant should ever appear
2646 gcc_assert (!CONSTANT_P (operands[1]));
2651 middlehalf[1] = adjust_address (operands[1], SImode, 0);
2652 latehalf[1] = adjust_address (operands[1], SImode, 0);
2656 /* size is not 12: */
2658 if (optype0 == REGOP)
2659 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2660 else if (optype0 == OFFSOP)
2661 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
2663 latehalf[0] = adjust_address (operands[0], SImode, 0);
2665 if (optype1 == REGOP)
2666 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2667 else if (optype1 == OFFSOP)
2668 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
2669 else if (optype1 == CNSTOP)
2670 split_double (operands[1], &operands[1], &latehalf[1]);
2672 latehalf[1] = adjust_address (operands[1], SImode, 0);
2675 /* If insn is effectively movd N(sp),-(sp) then we will do the
2676 high word first. We should use the adjusted operand 1 (which is N+4(sp))
2677 for the low word as well, to compensate for the first decrement of sp. */
2678 if (optype0 == PUSHOP
2679 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
2680 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
2681 operands[1] = middlehalf[1] = latehalf[1];
2683 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
2684 if the upper part of reg N does not appear in the MEM, arrange to
2685 emit the move late-half first. Otherwise, compute the MEM address
2686 into the upper part of N and use that as a pointer to the memory
2688 if (optype0 == REGOP
2689 && (optype1 == OFFSOP || optype1 == MEMOP))
2691 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
2693 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2694 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2696 /* If both halves of dest are used in the src memory address,
2697 compute the address into latehalf of dest.
2698 Note that this can't happen if the dest is two data regs. */
2700 xops[0] = latehalf[0];
2701 xops[1] = XEXP (operands[1], 0);
2703 handle_compadr (xops);
2704 if (GET_MODE (operands[1]) == XFmode)
2706 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
2707 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
2708 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2712 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
2713 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
2717 && reg_overlap_mentioned_p (middlehalf[0],
2718 XEXP (operands[1], 0)))
2720 /* Check for two regs used by both source and dest.
2721 Note that this can't happen if the dest is all data regs.
2722 It can happen if the dest is d6, d7, a0.
2723 But in that case, latehalf is an addr reg, so
2724 the code at compadr does ok. */
2726 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
2727 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
2730 /* JRV says this can't happen: */
2731 gcc_assert (!addreg0 && !addreg1);
2733 /* Only the middle reg conflicts; simply put it last. */
2734 handle_movsi (operands);
2735 handle_movsi (latehalf);
2736 handle_movsi (middlehalf);
2740 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
2741 /* If the low half of dest is mentioned in the source memory
2742 address, the arrange to emit the move late half first. */
2743 dest_overlapped_low = 1;
2746 /* If one or both operands autodecrementing,
2747 do the two words, high-numbered first. */
2749 /* Likewise, the first move would clobber the source of the second one,
2750 do them in the other order. This happens only for registers;
2751 such overlap can't happen in memory unless the user explicitly
2752 sets it up, and that is an undefined circumstance. */
2754 if (optype0 == PUSHOP || optype1 == PUSHOP
2755 || (optype0 == REGOP && optype1 == REGOP
2756 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
2757 || REGNO (operands[0]) == REGNO (latehalf[1])))
2758 || dest_overlapped_low)
2760 /* Make any unoffsettable addresses point at high-numbered word. */
2762 handle_reg_adjust (addreg0, size - 4);
2764 handle_reg_adjust (addreg1, size - 4);
2767 handle_movsi (latehalf);
2769 /* Undo the adds we just did. */
2771 handle_reg_adjust (addreg0, -4);
2773 handle_reg_adjust (addreg1, -4);
2777 handle_movsi (middlehalf);
2780 handle_reg_adjust (addreg0, -4);
2782 handle_reg_adjust (addreg1, -4);
2785 /* Do low-numbered word. */
2787 handle_movsi (operands);
2791 /* Normal case: do the two words, low-numbered first. */
2793 handle_movsi (operands);
2795 /* Do the middle one of the three words for long double */
2799 handle_reg_adjust (addreg0, 4);
2801 handle_reg_adjust (addreg1, 4);
2803 handle_movsi (middlehalf);
2806 /* Make any unoffsettable addresses point at high-numbered word. */
2808 handle_reg_adjust (addreg0, 4);
2810 handle_reg_adjust (addreg1, 4);
2813 handle_movsi (latehalf);
2815 /* Undo the adds we just did. */
2817 handle_reg_adjust (addreg0, -(size - 4));
2819 handle_reg_adjust (addreg1, -(size - 4));
2824 /* Output assembler code to adjust REG by N. */
2826 output_reg_adjust (rtx reg, int n)
2830 gcc_assert (GET_MODE (reg) == SImode
2831 && -12 <= n && n != 0 && n <= 12);
2836 s = "add%.l #12,%0";
2840 s = "addq%.l #8,%0";
2844 s = "addq%.l #4,%0";
2848 s = "sub%.l #12,%0";
2852 s = "subq%.l #8,%0";
2856 s = "subq%.l #4,%0";
2864 output_asm_insn (s, ®);
2867 /* Emit rtl code to adjust REG by N. */
2869 emit_reg_adjust (rtx reg1, int n)
2873 gcc_assert (GET_MODE (reg1) == SImode
2874 && -12 <= n && n != 0 && n <= 12);
2876 reg1 = copy_rtx (reg1);
2877 reg2 = copy_rtx (reg1);
2880 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
2882 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
2887 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
2889 output_compadr (rtx operands[2])
2891 output_asm_insn ("lea %a1,%0", operands);
2894 /* Output the best assembler insn for moving operands[1] into operands[0]
2897 output_movsi (rtx operands[2])
2899 output_asm_insn (singlemove_string (operands), operands);
2902 /* Copy OP and change its mode to MODE. */
2904 copy_operand (rtx op, enum machine_mode mode)
2906 /* ??? This looks really ugly. There must be a better way
2907 to change a mode on the operand. */
2908 if (GET_MODE (op) != VOIDmode)
2911 op = gen_rtx_REG (mode, REGNO (op));
2915 PUT_MODE (op, mode);
2922 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
2924 emit_movsi (rtx operands[2])
2926 operands[0] = copy_operand (operands[0], SImode);
2927 operands[1] = copy_operand (operands[1], SImode);
2929 emit_insn (gen_movsi (operands[0], operands[1]));
2932 /* Output assembler code to perform a doubleword move insn
2933 with operands OPERANDS. */
2935 output_move_double (rtx *operands)
2937 handle_move_double (operands,
2938 output_reg_adjust, output_compadr, output_movsi);
2943 /* Output rtl code to perform a doubleword move insn
2944 with operands OPERANDS. */
2946 m68k_emit_move_double (rtx operands[2])
2948 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
2951 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
2952 new rtx with the correct mode. */
2955 force_mode (enum machine_mode mode, rtx orig)
2957 if (mode == GET_MODE (orig))
2960 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
2963 return gen_rtx_REG (mode, REGNO (orig));
2967 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2969 return reg_renumber && FP_REG_P (op);
2972 /* Emit insns to move operands[1] into operands[0].
2974 Return 1 if we have written out everything that needs to be done to
2975 do the move. Otherwise, return 0 and the caller will emit the move
2978 Note SCRATCH_REG may not be in the proper mode depending on how it
2979 will be used. This routine is responsible for creating a new copy
2980 of SCRATCH_REG in the proper mode. */
2983 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
2985 register rtx operand0 = operands[0];
2986 register rtx operand1 = operands[1];
2990 && reload_in_progress && GET_CODE (operand0) == REG
2991 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2992 operand0 = reg_equiv_mem[REGNO (operand0)];
2993 else if (scratch_reg
2994 && reload_in_progress && GET_CODE (operand0) == SUBREG
2995 && GET_CODE (SUBREG_REG (operand0)) == REG
2996 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
2998 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
2999 the code which tracks sets/uses for delete_output_reload. */
3000 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3001 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
3002 SUBREG_BYTE (operand0));
3003 operand0 = alter_subreg (&temp);
3007 && reload_in_progress && GET_CODE (operand1) == REG
3008 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3009 operand1 = reg_equiv_mem[REGNO (operand1)];
3010 else if (scratch_reg
3011 && reload_in_progress && GET_CODE (operand1) == SUBREG
3012 && GET_CODE (SUBREG_REG (operand1)) == REG
3013 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3015 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3016 the code which tracks sets/uses for delete_output_reload. */
3017 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3018 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
3019 SUBREG_BYTE (operand1));
3020 operand1 = alter_subreg (&temp);
3023 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3024 && ((tem = find_replacement (&XEXP (operand0, 0)))
3025 != XEXP (operand0, 0)))
3026 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3027 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3028 && ((tem = find_replacement (&XEXP (operand1, 0)))
3029 != XEXP (operand1, 0)))
3030 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3032 /* Handle secondary reloads for loads/stores of FP registers where
3033 the address is symbolic by using the scratch register */
3034 if (fp_reg_operand (operand0, mode)
3035 && ((GET_CODE (operand1) == MEM
3036 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3037 || ((GET_CODE (operand1) == SUBREG
3038 && GET_CODE (XEXP (operand1, 0)) == MEM
3039 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3042 if (GET_CODE (operand1) == SUBREG)
3043 operand1 = XEXP (operand1, 0);
3045 /* SCRATCH_REG will hold an address. We want
3046 it in SImode regardless of what mode it was originally given
3048 scratch_reg = force_mode (SImode, scratch_reg);
3050 /* D might not fit in 14 bits either; for such cases load D into
3052 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3054 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3055 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3057 XEXP (XEXP (operand1, 0), 0),
3061 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3062 emit_insn (gen_rtx_SET (VOIDmode, operand0,
3063 gen_rtx_MEM (mode, scratch_reg)));
3066 else if (fp_reg_operand (operand1, mode)
3067 && ((GET_CODE (operand0) == MEM
3068 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3069 || ((GET_CODE (operand0) == SUBREG)
3070 && GET_CODE (XEXP (operand0, 0)) == MEM
3071 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3074 if (GET_CODE (operand0) == SUBREG)
3075 operand0 = XEXP (operand0, 0);
3077 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3078 it in SIMODE regardless of what mode it was originally given
3080 scratch_reg = force_mode (SImode, scratch_reg);
3082 /* D might not fit in 14 bits either; for such cases load D into
3084 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3086 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3087 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3090 XEXP (XEXP (operand0, 0),
3095 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3096 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
3100 /* Handle secondary reloads for loads of FP registers from constant
3101 expressions by forcing the constant into memory.
3103 use scratch_reg to hold the address of the memory location.
3105 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3106 NO_REGS when presented with a const_int and an register class
3107 containing only FP registers. Doing so unfortunately creates
3108 more problems than it solves. Fix this for 2.5. */
3109 else if (fp_reg_operand (operand0, mode)
3110 && CONSTANT_P (operand1)
3115 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3116 it in SIMODE regardless of what mode it was originally given
3118 scratch_reg = force_mode (SImode, scratch_reg);
3120 /* Force the constant into memory and put the address of the
3121 memory location into scratch_reg. */
3122 xoperands[0] = scratch_reg;
3123 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3124 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1]));
3126 /* Now load the destination register. */
3127 emit_insn (gen_rtx_SET (mode, operand0,
3128 gen_rtx_MEM (mode, scratch_reg)));
3132 /* Now have insn-emit do whatever it normally does. */
3136 /* Split one or more DImode RTL references into pairs of SImode
3137 references. The RTL can be REG, offsettable MEM, integer constant, or
3138 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3139 split and "num" is its length. lo_half and hi_half are output arrays
3140 that parallel "operands". */
3143 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3147 rtx op = operands[num];
3149 /* simplify_subreg refuses to split volatile memory addresses,
3150 but we still have to handle it. */
3151 if (GET_CODE (op) == MEM)
3153 lo_half[num] = adjust_address (op, SImode, 4);
3154 hi_half[num] = adjust_address (op, SImode, 0);
3158 lo_half[num] = simplify_gen_subreg (SImode, op,
3159 GET_MODE (op) == VOIDmode
3160 ? DImode : GET_MODE (op), 4);
3161 hi_half[num] = simplify_gen_subreg (SImode, op,
3162 GET_MODE (op) == VOIDmode
3163 ? DImode : GET_MODE (op), 0);
3168 /* Split X into a base and a constant offset, storing them in *BASE
3169 and *OFFSET respectively. */
3172 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3175 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3177 *offset += INTVAL (XEXP (x, 1));
3183 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3184 instruction. STORE_P says whether the move is a load or store.
3186 If the instruction uses post-increment or pre-decrement addressing,
3187 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3188 adjustment. This adjustment will be made by the first element of
3189 PARALLEL, with the loads or stores starting at element 1. If the
3190 instruction does not use post-increment or pre-decrement addressing,
3191 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3192 start at element 0. */
3195 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3196 HOST_WIDE_INT automod_offset, bool store_p)
3198 rtx base, mem_base, set, mem, reg, last_reg;
3199 HOST_WIDE_INT offset, mem_offset;
3201 enum reg_class rclass;
3203 len = XVECLEN (pattern, 0);
3204 first = (automod_base != NULL);
3208 /* Stores must be pre-decrement and loads must be post-increment. */
3209 if (store_p != (automod_offset < 0))
3212 /* Work out the base and offset for lowest memory location. */
3213 base = automod_base;
3214 offset = (automod_offset < 0 ? automod_offset : 0);
3218 /* Allow any valid base and offset in the first access. */
3225 for (i = first; i < len; i++)
3227 /* We need a plain SET. */
3228 set = XVECEXP (pattern, 0, i);
3229 if (GET_CODE (set) != SET)
3232 /* Check that we have a memory location... */
3233 mem = XEXP (set, !store_p);
3234 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3237 /* ...with the right address. */
3240 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3241 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3242 There are no mode restrictions for 680x0 besides the
3243 automodification rules enforced above. */
3245 && !m68k_legitimate_base_reg_p (base, reload_completed))
3250 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3251 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3255 /* Check that we have a register of the required mode and class. */
3256 reg = XEXP (set, store_p);
3258 || !HARD_REGISTER_P (reg)
3259 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3264 /* The register must belong to RCLASS and have a higher number
3265 than the register in the previous SET. */
3266 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3267 || REGNO (last_reg) >= REGNO (reg))
3272 /* Work out which register class we need. */
3273 if (INT_REGNO_P (REGNO (reg)))
3274 rclass = GENERAL_REGS;
3275 else if (FP_REGNO_P (REGNO (reg)))
3282 offset += GET_MODE_SIZE (GET_MODE (reg));
3285 /* If we have an automodification, check whether the final offset is OK. */
3286 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3289 /* Reject unprofitable cases. */
3290 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3296 /* Return the assembly code template for a movem or fmovem instruction
3297 whose pattern is given by PATTERN. Store the template's operands
3300 If the instruction uses post-increment or pre-decrement addressing,
3301 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3302 is true if this is a store instruction. */
3305 m68k_output_movem (rtx *operands, rtx pattern,
3306 HOST_WIDE_INT automod_offset, bool store_p)
3311 gcc_assert (GET_CODE (pattern) == PARALLEL);
3313 first = (automod_offset != 0);
3314 for (i = first; i < XVECLEN (pattern, 0); i++)
3316 /* When using movem with pre-decrement addressing, register X + D0_REG
3317 is controlled by bit 15 - X. For all other addressing modes,
3318 register X + D0_REG is controlled by bit X. Confusingly, the
3319 register mask for fmovem is in the opposite order to that for
3323 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
3324 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
3325 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
3326 if (automod_offset < 0)
3328 if (FP_REGNO_P (regno))
3329 mask |= 1 << (regno - FP0_REG);
3331 mask |= 1 << (15 - (regno - D0_REG));
3335 if (FP_REGNO_P (regno))
3336 mask |= 1 << (7 - (regno - FP0_REG));
3338 mask |= 1 << (regno - D0_REG);
3343 if (automod_offset == 0)
3344 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
3345 else if (automod_offset < 0)
3346 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3348 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
3349 operands[1] = GEN_INT (mask);
3350 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
3353 return "fmovem %1,%a0";
3355 return "fmovem %a0,%1";
3360 return "movem%.l %1,%a0";
3362 return "movem%.l %a0,%1";
3366 /* Return a REG that occurs in ADDR with coefficient 1.
3367 ADDR can be effectively incremented by incrementing REG. */
3370 find_addr_reg (rtx addr)
3372 while (GET_CODE (addr) == PLUS)
3374 if (GET_CODE (XEXP (addr, 0)) == REG)
3375 addr = XEXP (addr, 0);
3376 else if (GET_CODE (XEXP (addr, 1)) == REG)
3377 addr = XEXP (addr, 1);
3378 else if (CONSTANT_P (XEXP (addr, 0)))
3379 addr = XEXP (addr, 1);
3380 else if (CONSTANT_P (XEXP (addr, 1)))
3381 addr = XEXP (addr, 0);
3385 gcc_assert (GET_CODE (addr) == REG);
3389 /* Output assembler code to perform a 32-bit 3-operand add. */
3392 output_addsi3 (rtx *operands)
3394 if (! operands_match_p (operands[0], operands[1]))
3396 if (!ADDRESS_REG_P (operands[1]))
3398 rtx tmp = operands[1];
3400 operands[1] = operands[2];
3404 /* These insns can result from reloads to access
3405 stack slots over 64k from the frame pointer. */
3406 if (GET_CODE (operands[2]) == CONST_INT
3407 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
3408 return "move%.l %2,%0\n\tadd%.l %1,%0";
3409 if (GET_CODE (operands[2]) == REG)
3410 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
3411 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
3413 if (GET_CODE (operands[2]) == CONST_INT)
3415 if (INTVAL (operands[2]) > 0
3416 && INTVAL (operands[2]) <= 8)
3417 return "addq%.l %2,%0";
3418 if (INTVAL (operands[2]) < 0
3419 && INTVAL (operands[2]) >= -8)
3421 operands[2] = GEN_INT (- INTVAL (operands[2]));
3422 return "subq%.l %2,%0";
3424 /* On the CPU32 it is faster to use two addql instructions to
3425 add a small integer (8 < N <= 16) to a register.
3426 Likewise for subql. */
3427 if (TUNE_CPU32 && REG_P (operands[0]))
3429 if (INTVAL (operands[2]) > 8
3430 && INTVAL (operands[2]) <= 16)
3432 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
3433 return "addq%.l #8,%0\n\taddq%.l %2,%0";
3435 if (INTVAL (operands[2]) < -8
3436 && INTVAL (operands[2]) >= -16)
3438 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
3439 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
3442 if (ADDRESS_REG_P (operands[0])
3443 && INTVAL (operands[2]) >= -0x8000
3444 && INTVAL (operands[2]) < 0x8000)
3447 return "add%.w %2,%0";
3449 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
3452 return "add%.l %2,%0";
3455 /* Store in cc_status the expressions that the condition codes will
3456 describe after execution of an instruction whose pattern is EXP.
3457 Do not alter them if the instruction would not alter the cc's. */
3459 /* On the 68000, all the insns to store in an address register fail to
3460 set the cc's. However, in some cases these instructions can make it
3461 possibly invalid to use the saved cc's. In those cases we clear out
3462 some or all of the saved cc's so they won't be used. */
3465 notice_update_cc (rtx exp, rtx insn)
3467 if (GET_CODE (exp) == SET)
3469 if (GET_CODE (SET_SRC (exp)) == CALL)
3471 else if (ADDRESS_REG_P (SET_DEST (exp)))
3473 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
3474 cc_status.value1 = 0;
3475 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
3476 cc_status.value2 = 0;
3478 /* fmoves to memory or data registers do not set the condition
3479 codes. Normal moves _do_ set the condition codes, but not in
3480 a way that is appropriate for comparison with 0, because -0.0
3481 would be treated as a negative nonzero number. Note that it
3482 isn't appropriate to conditionalize this restriction on
3483 HONOR_SIGNED_ZEROS because that macro merely indicates whether
3484 we care about the difference between -0.0 and +0.0. */
3485 else if (!FP_REG_P (SET_DEST (exp))
3486 && SET_DEST (exp) != cc0_rtx
3487 && (FP_REG_P (SET_SRC (exp))
3488 || GET_CODE (SET_SRC (exp)) == FIX
3489 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
3491 /* A pair of move insns doesn't produce a useful overall cc. */
3492 else if (!FP_REG_P (SET_DEST (exp))
3493 && !FP_REG_P (SET_SRC (exp))
3494 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
3495 && (GET_CODE (SET_SRC (exp)) == REG
3496 || GET_CODE (SET_SRC (exp)) == MEM
3497 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
3499 else if (SET_DEST (exp) != pc_rtx)
3501 cc_status.flags = 0;
3502 cc_status.value1 = SET_DEST (exp);
3503 cc_status.value2 = SET_SRC (exp);
3506 else if (GET_CODE (exp) == PARALLEL
3507 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
3509 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
3510 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
3512 if (ADDRESS_REG_P (dest))
3514 else if (dest != pc_rtx)
3516 cc_status.flags = 0;
3517 cc_status.value1 = dest;
3518 cc_status.value2 = src;
3523 if (cc_status.value2 != 0
3524 && ADDRESS_REG_P (cc_status.value2)
3525 && GET_MODE (cc_status.value2) == QImode)
3527 if (cc_status.value2 != 0)
3528 switch (GET_CODE (cc_status.value2))
3530 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
3531 case ROTATE: case ROTATERT:
3532 /* These instructions always clear the overflow bit, and set
3533 the carry to the bit shifted out. */
3534 /* ??? We don't currently have a way to signal carry not valid,
3535 nor do we check for it in the branch insns. */
3539 case PLUS: case MINUS: case MULT:
3540 case DIV: case UDIV: case MOD: case UMOD: case NEG:
3541 if (GET_MODE (cc_status.value2) != VOIDmode)
3542 cc_status.flags |= CC_NO_OVERFLOW;
3545 /* (SET r1 (ZERO_EXTEND r2)) on this machine
3546 ends with a move insn moving r2 in r2's mode.
3547 Thus, the cc's are set for r2.
3548 This can set N bit spuriously. */
3549 cc_status.flags |= CC_NOT_NEGATIVE;
3554 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
3556 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
3557 cc_status.value2 = 0;
3558 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
3559 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
3560 cc_status.flags = CC_IN_68881;
3561 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
3562 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
3564 cc_status.flags = CC_IN_68881;
3565 if (!FP_REG_P (XEXP (cc_status.value2, 0)))
3566 cc_status.flags |= CC_REVERSED;
3571 output_move_const_double (rtx *operands)
3573 int code = standard_68881_constant_p (operands[1]);
3577 static char buf[40];
3579 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3582 return "fmove%.d %1,%0";
3586 output_move_const_single (rtx *operands)
3588 int code = standard_68881_constant_p (operands[1]);
3592 static char buf[40];
3594 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
3597 return "fmove%.s %f1,%0";
3600 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
3601 from the "fmovecr" instruction.
3602 The value, anded with 0xff, gives the code to use in fmovecr
3603 to get the desired constant. */
3605 /* This code has been fixed for cross-compilation. */
3607 static int inited_68881_table = 0;
3609 static const char *const strings_68881[7] = {
3619 static const int codes_68881[7] = {
3629 REAL_VALUE_TYPE values_68881[7];
3631 /* Set up values_68881 array by converting the decimal values
3632 strings_68881 to binary. */
3635 init_68881_table (void)
3639 enum machine_mode mode;
3642 for (i = 0; i < 7; i++)
3646 r = REAL_VALUE_ATOF (strings_68881[i], mode);
3647 values_68881[i] = r;
3649 inited_68881_table = 1;
3653 standard_68881_constant_p (rtx x)
3658 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
3659 used at all on those chips. */
3663 if (! inited_68881_table)
3664 init_68881_table ();
3666 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3668 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
3670 for (i = 0; i < 6; i++)
3672 if (REAL_VALUES_IDENTICAL (r, values_68881[i]))
3673 return (codes_68881[i]);
3676 if (GET_MODE (x) == SFmode)
3679 if (REAL_VALUES_EQUAL (r, values_68881[6]))
3680 return (codes_68881[6]);
3682 /* larger powers of ten in the constants ram are not used
3683 because they are not equal to a `double' C constant. */
3687 /* If X is a floating-point constant, return the logarithm of X base 2,
3688 or 0 if X is not a power of 2. */
3691 floating_exact_log2 (rtx x)
3693 REAL_VALUE_TYPE r, r1;
3696 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3698 if (REAL_VALUES_LESS (r, dconst1))
3701 exp = real_exponent (&r);
3702 real_2expN (&r1, exp, DFmode);
3703 if (REAL_VALUES_EQUAL (r1, r))
3709 /* A C compound statement to output to stdio stream STREAM the
3710 assembler syntax for an instruction operand X. X is an RTL
3713 CODE is a value that can be used to specify one of several ways
3714 of printing the operand. It is used when identical operands
3715 must be printed differently depending on the context. CODE
3716 comes from the `%' specification that was used to request
3717 printing of the operand. If the specification was just `%DIGIT'
3718 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3719 is the ASCII code for LTR.
3721 If X is a register, this macro should print the register's name.
3722 The names can be found in an array `reg_names' whose type is
3723 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3725 When the machine description has a specification `%PUNCT' (a `%'
3726 followed by a punctuation character), this macro is called with
3727 a null pointer for X and the punctuation character for CODE.
3729 The m68k specific codes are:
3731 '.' for dot needed in Motorola-style opcode names.
3732 '-' for an operand pushing on the stack:
3733 sp@-, -(sp) or -(%sp) depending on the style of syntax.
3734 '+' for an operand pushing on the stack:
3735 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
3736 '@' for a reference to the top word on the stack:
3737 sp@, (sp) or (%sp) depending on the style of syntax.
3738 '#' for an immediate operand prefix (# in MIT and Motorola syntax
3739 but & in SGS syntax).
3740 '!' for the cc register (used in an `and to cc' insn).
3741 '$' for the letter `s' in an op code, but only on the 68040.
3742 '&' for the letter `d' in an op code, but only on the 68040.
3743 '/' for register prefix needed by longlong.h.
3744 '?' for m68k_library_id_string
3746 'b' for byte insn (no effect, on the Sun; this is for the ISI).
3747 'd' to force memory addressing to be absolute, not relative.
3748 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
3749 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
3750 or print pair of registers as rx:ry.
3751 'p' print an address with @PLTPC attached, but only if the operand
3752 is not locally-bound. */
3755 print_operand (FILE *file, rtx op, int letter)
3760 fprintf (file, ".");
3762 else if (letter == '#')
3763 asm_fprintf (file, "%I");
3764 else if (letter == '-')
3765 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
3766 else if (letter == '+')
3767 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
3768 else if (letter == '@')
3769 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
3770 else if (letter == '!')
3771 asm_fprintf (file, "%Rfpcr");
3772 else if (letter == '$')
3775 fprintf (file, "s");
3777 else if (letter == '&')
3780 fprintf (file, "d");
3782 else if (letter == '/')
3783 asm_fprintf (file, "%R");
3784 else if (letter == '?')
3785 asm_fprintf (file, m68k_library_id_string);
3786 else if (letter == 'p')
3788 output_addr_const (file, op);
3789 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
3790 fprintf (file, "@PLTPC");
3792 else if (GET_CODE (op) == REG)
3795 /* Print out the second register name of a register pair.
3796 I.e., R (6) => 7. */
3797 fputs (M68K_REGNAME(REGNO (op) + 1), file);
3799 fputs (M68K_REGNAME(REGNO (op)), file);
3801 else if (GET_CODE (op) == MEM)
3803 output_address (XEXP (op, 0));
3804 if (letter == 'd' && ! TARGET_68020
3805 && CONSTANT_ADDRESS_P (XEXP (op, 0))
3806 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
3807 && INTVAL (XEXP (op, 0)) < 0x8000
3808 && INTVAL (XEXP (op, 0)) >= -0x8000))
3809 fprintf (file, MOTOROLA ? ".l" : ":l");
3811 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
3814 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3815 ASM_OUTPUT_FLOAT_OPERAND (letter, file, r);
3817 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
3820 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3821 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file, r);
3823 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
3826 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
3827 ASM_OUTPUT_DOUBLE_OPERAND (file, r);
3831 /* Use `print_operand_address' instead of `output_addr_const'
3832 to ensure that we print relevant PIC stuff. */
3833 asm_fprintf (file, "%I");
3835 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
3836 print_operand_address (file, op);
3838 output_addr_const (file, op);
3843 /* A C compound statement to output to stdio stream STREAM the
3844 assembler syntax for an instruction operand that is a memory
3845 reference whose address is ADDR. ADDR is an RTL expression.
3847 Note that this contains a kludge that knows that the only reason
3848 we have an address (plus (label_ref...) (reg...)) when not generating
3849 PIC code is in the insn before a tablejump, and we know that m68k.md
3850 generates a label LInnn: on such an insn.
3852 It is possible for PIC to generate a (plus (label_ref...) (reg...))
3853 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
3855 This routine is responsible for distinguishing between -fpic and -fPIC
3856 style relocations in an address. When generating -fpic code the
3857 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
3858 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
3861 print_operand_address (FILE *file, rtx addr)
3863 struct m68k_address address;
3865 if (!m68k_decompose_address (QImode, addr, true, &address))
3868 if (address.code == PRE_DEC)
3869 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
3870 M68K_REGNAME (REGNO (address.base)));
3871 else if (address.code == POST_INC)
3872 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
3873 M68K_REGNAME (REGNO (address.base)));
3874 else if (!address.base && !address.index)
3876 /* A constant address. */
3877 gcc_assert (address.offset == addr);
3878 if (GET_CODE (addr) == CONST_INT)
3880 /* (xxx).w or (xxx).l. */
3881 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
3882 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
3884 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
3886 else if (TARGET_PCREL)
3888 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
3890 output_addr_const (file, addr);
3891 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
3895 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
3896 name ends in `.<letter>', as the last 2 characters can be
3897 mistaken as a size suffix. Put the name in parentheses. */
3898 if (GET_CODE (addr) == SYMBOL_REF
3899 && strlen (XSTR (addr, 0)) > 2
3900 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
3903 output_addr_const (file, addr);
3907 output_addr_const (file, addr);
3914 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
3915 label being accessed, otherwise it is -1. */
3916 labelno = (address.offset
3918 && GET_CODE (address.offset) == LABEL_REF
3919 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
3923 /* Print the "offset(base" component. */
3925 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
3930 output_addr_const (file, address.offset);
3931 if (flag_pic && address.base == pic_offset_table_rtx)
3933 fprintf (file, "@GOT");
3934 if (flag_pic == 1 && TARGET_68020)
3935 fprintf (file, ".w");
3940 fputs (M68K_REGNAME (REGNO (address.base)), file);
3942 /* Print the ",index" component, if any. */
3947 fprintf (file, "%s.%c",
3948 M68K_REGNAME (REGNO (address.index)),
3949 GET_MODE (address.index) == HImode ? 'w' : 'l');
3950 if (address.scale != 1)
3951 fprintf (file, "*%d", address.scale);
3955 else /* !MOTOROLA */
3957 if (!address.offset && !address.index)
3958 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
3961 /* Print the "base@(offset" component. */
3963 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
3967 fputs (M68K_REGNAME (REGNO (address.base)), file);
3968 fprintf (file, "@(");
3971 output_addr_const (file, address.offset);
3972 if (address.base == pic_offset_table_rtx && TARGET_68020)
3976 fprintf (file, ":w"); break;
3978 fprintf (file, ":l"); break;
3984 /* Print the ",index" component, if any. */
3987 fprintf (file, ",%s:%c",
3988 M68K_REGNAME (REGNO (address.index)),
3989 GET_MODE (address.index) == HImode ? 'w' : 'l');
3990 if (address.scale != 1)
3991 fprintf (file, ":%d", address.scale);
3999 /* Check for cases where a clr insns can be omitted from code using
4000 strict_low_part sets. For example, the second clrl here is not needed:
4001 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4003 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4004 insn we are checking for redundancy. TARGET is the register set by the
4008 strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
4013 while ((p = PREV_INSN (p)))
4015 if (NOTE_INSN_BASIC_BLOCK_P (p))
4021 /* If it isn't an insn, then give up. */
4025 if (reg_set_p (target, p))
4027 rtx set = single_set (p);
4030 /* If it isn't an easy to recognize insn, then give up. */
4034 dest = SET_DEST (set);
4036 /* If this sets the entire target register to zero, then our
4037 first_insn is redundant. */
4038 if (rtx_equal_p (dest, target)
4039 && SET_SRC (set) == const0_rtx)
4041 else if (GET_CODE (dest) == STRICT_LOW_PART
4042 && GET_CODE (XEXP (dest, 0)) == REG
4043 && REGNO (XEXP (dest, 0)) == REGNO (target)
4044 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4045 <= GET_MODE_SIZE (mode)))
4046 /* This is a strict low part set which modifies less than
4047 we are using, so it is safe. */
4057 /* Operand predicates for implementing asymmetric pc-relative addressing
4058 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4059 when used as a source operand, but not as a destination operand.
4061 We model this by restricting the meaning of the basic predicates
4062 (general_operand, memory_operand, etc) to forbid the use of this
4063 addressing mode, and then define the following predicates that permit
4064 this addressing mode. These predicates can then be used for the
4065 source operands of the appropriate instructions.
4067 n.b. While it is theoretically possible to change all machine patterns
4068 to use this addressing more where permitted by the architecture,
4069 it has only been implemented for "common" cases: SImode, HImode, and
4070 QImode operands, and only for the principle operations that would
4071 require this addressing mode: data movement and simple integer operations.
4073 In parallel with these new predicates, two new constraint letters
4074 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4075 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4076 In the pcrel case 's' is only valid in combination with 'a' registers.
4077 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4078 of how these constraints are used.
4080 The use of these predicates is strictly optional, though patterns that
4081 don't will cause an extra reload register to be allocated where one
4084 lea (abc:w,%pc),%a0 ; need to reload address
4085 moveq &1,%d1 ; since write to pc-relative space
4086 movel %d1,%a0@ ; is not allowed
4088 lea (abc:w,%pc),%a1 ; no need to reload address here
4089 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4091 For more info, consult tiemann@cygnus.com.
4094 All of the ugliness with predicates and constraints is due to the
4095 simple fact that the m68k does not allow a pc-relative addressing
4096 mode as a destination. gcc does not distinguish between source and
4097 destination addresses. Hence, if we claim that pc-relative address
4098 modes are valid, e.g. GO_IF_LEGITIMATE_ADDRESS accepts them, then we
4099 end up with invalid code. To get around this problem, we left
4100 pc-relative modes as invalid addresses, and then added special
4101 predicates and constraints to accept them.
4103 A cleaner way to handle this is to modify gcc to distinguish
4104 between source and destination addresses. We can then say that
4105 pc-relative is a valid source address but not a valid destination
4106 address, and hopefully avoid a lot of the predicate and constraint
4107 hackery. Unfortunately, this would be a pretty big change. It would
4108 be a useful change for a number of ports, but there aren't any current
4109 plans to undertake this.
4111 ***************************************************************************/
4115 output_andsi3 (rtx *operands)
4118 if (GET_CODE (operands[2]) == CONST_INT
4119 && (INTVAL (operands[2]) | 0xffff) == -1
4120 && (DATA_REG_P (operands[0])
4121 || offsettable_memref_p (operands[0]))
4122 && !TARGET_COLDFIRE)
4124 if (GET_CODE (operands[0]) != REG)
4125 operands[0] = adjust_address (operands[0], HImode, 2);
4126 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4127 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4129 if (operands[2] == const0_rtx)
4131 return "and%.w %2,%0";
4133 if (GET_CODE (operands[2]) == CONST_INT
4134 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
4135 && (DATA_REG_P (operands[0])
4136 || offsettable_memref_p (operands[0])))
4138 if (DATA_REG_P (operands[0]))
4139 operands[1] = GEN_INT (logval);
4142 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4143 operands[1] = GEN_INT (logval % 8);
4145 /* This does not set condition codes in a standard way. */
4147 return "bclr %1,%0";
4149 return "and%.l %2,%0";
4153 output_iorsi3 (rtx *operands)
4155 register int logval;
4156 if (GET_CODE (operands[2]) == CONST_INT
4157 && INTVAL (operands[2]) >> 16 == 0
4158 && (DATA_REG_P (operands[0])
4159 || offsettable_memref_p (operands[0]))
4160 && !TARGET_COLDFIRE)
4162 if (GET_CODE (operands[0]) != REG)
4163 operands[0] = adjust_address (operands[0], HImode, 2);
4164 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4166 if (INTVAL (operands[2]) == 0xffff)
4167 return "mov%.w %2,%0";
4168 return "or%.w %2,%0";
4170 if (GET_CODE (operands[2]) == CONST_INT
4171 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4172 && (DATA_REG_P (operands[0])
4173 || offsettable_memref_p (operands[0])))
4175 if (DATA_REG_P (operands[0]))
4176 operands[1] = GEN_INT (logval);
4179 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4180 operands[1] = GEN_INT (logval % 8);
4183 return "bset %1,%0";
4185 return "or%.l %2,%0";
4189 output_xorsi3 (rtx *operands)
4191 register int logval;
4192 if (GET_CODE (operands[2]) == CONST_INT
4193 && INTVAL (operands[2]) >> 16 == 0
4194 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
4195 && !TARGET_COLDFIRE)
4197 if (! DATA_REG_P (operands[0]))
4198 operands[0] = adjust_address (operands[0], HImode, 2);
4199 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4201 if (INTVAL (operands[2]) == 0xffff)
4203 return "eor%.w %2,%0";
4205 if (GET_CODE (operands[2]) == CONST_INT
4206 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
4207 && (DATA_REG_P (operands[0])
4208 || offsettable_memref_p (operands[0])))
4210 if (DATA_REG_P (operands[0]))
4211 operands[1] = GEN_INT (logval);
4214 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4215 operands[1] = GEN_INT (logval % 8);
4218 return "bchg %1,%0";
4220 return "eor%.l %2,%0";
4223 /* Return the instruction that should be used for a call to address X,
4224 which is known to be in operand 0. */
4229 if (symbolic_operand (x, VOIDmode))
4230 return m68k_symbolic_call;
4235 /* Likewise sibling calls. */
4238 output_sibcall (rtx x)
4240 if (symbolic_operand (x, VOIDmode))
4241 return m68k_symbolic_jump;
4246 #ifdef M68K_TARGET_COFF
4248 /* Output assembly to switch to section NAME with attribute FLAGS. */
4251 m68k_coff_asm_named_section (const char *name, unsigned int flags,
4252 tree decl ATTRIBUTE_UNUSED)
4256 if (flags & SECTION_WRITE)
4261 fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
4264 #endif /* M68K_TARGET_COFF */
4267 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
4268 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
4271 rtx this_slot, offset, addr, mem, insn;
4273 /* Pretend to be a post-reload pass while generating rtl. */
4274 reload_completed = 1;
4276 /* The "this" pointer is stored at 4(%sp). */
4277 this_slot = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 4));
4279 /* Add DELTA to THIS. */
4282 /* Make the offset a legitimate operand for memory addition. */
4283 offset = GEN_INT (delta);
4284 if ((delta < -8 || delta > 8)
4285 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
4287 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
4288 offset = gen_rtx_REG (Pmode, D0_REG);
4290 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4291 copy_rtx (this_slot), offset));
4294 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
4295 if (vcall_offset != 0)
4297 /* Set the static chain register to *THIS. */
4298 emit_move_insn (static_chain_rtx, this_slot);
4299 emit_move_insn (static_chain_rtx, gen_rtx_MEM (Pmode, static_chain_rtx));
4301 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
4302 addr = plus_constant (static_chain_rtx, vcall_offset);
4303 if (!m68k_legitimate_address_p (Pmode, addr, true))
4305 emit_insn (gen_rtx_SET (VOIDmode, static_chain_rtx, addr));
4306 addr = static_chain_rtx;
4309 /* Load the offset into %d0 and add it to THIS. */
4310 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
4311 gen_rtx_MEM (Pmode, addr));
4312 emit_insn (gen_add3_insn (copy_rtx (this_slot),
4313 copy_rtx (this_slot),
4314 gen_rtx_REG (Pmode, D0_REG)));
4317 /* Jump to the target function. Use a sibcall if direct jumps are
4318 allowed, otherwise load the address into a register first. */
4319 mem = DECL_RTL (function);
4320 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
4322 gcc_assert (flag_pic);
4324 if (!TARGET_SEP_DATA)
4326 /* Use the static chain register as a temporary (call-clobbered)
4327 GOT pointer for this function. We can use the static chain
4328 register because it isn't live on entry to the thunk. */
4329 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
4330 emit_insn (gen_load_got (pic_offset_table_rtx));
4332 legitimize_pic_address (XEXP (mem, 0), Pmode, static_chain_rtx);
4333 mem = replace_equiv_address (mem, static_chain_rtx);
4335 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
4336 SIBLING_CALL_P (insn) = 1;
4338 /* Run just enough of rest_of_compilation. */
4339 insn = get_insns ();
4340 split_all_insns_noflow ();
4341 final_start_function (insn, file, 1);
4342 final (insn, file, 1);
4343 final_end_function ();
4345 /* Clean up the vars set above. */
4346 reload_completed = 0;
4348 /* Restore the original PIC register. */
4350 SET_REGNO (pic_offset_table_rtx, PIC_REG);
4351 free_after_compilation (cfun);
4354 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4357 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
4358 int incoming ATTRIBUTE_UNUSED)
4360 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
4363 /* Return nonzero if register old_reg can be renamed to register new_reg. */
4365 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
4366 unsigned int new_reg)
4369 /* Interrupt functions can only use registers that have already been
4370 saved by the prologue, even if they would normally be
4373 if ((m68k_get_function_kind (current_function_decl)
4374 == m68k_fk_interrupt_handler)
4375 && !df_regs_ever_live_p (new_reg))
4381 /* Value is true if hard register REGNO can hold a value of machine-mode
4382 MODE. On the 68000, we let the cpu registers can hold any mode, but
4383 restrict the 68881 registers to floating-point modes. */
4386 m68k_regno_mode_ok (int regno, enum machine_mode mode)
4388 if (DATA_REGNO_P (regno))
4390 /* Data Registers, can hold aggregate if fits in. */
4391 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
4394 else if (ADDRESS_REGNO_P (regno))
4396 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
4399 else if (FP_REGNO_P (regno))
4401 /* FPU registers, hold float or complex float of long double or
4403 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
4404 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4405 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
4411 /* Implement SECONDARY_RELOAD_CLASS. */
4414 m68k_secondary_reload_class (enum reg_class rclass,
4415 enum machine_mode mode, rtx x)
4419 regno = true_regnum (x);
4421 /* If one operand of a movqi is an address register, the other
4422 operand must be a general register or constant. Other types
4423 of operand must be reloaded through a data register. */
4424 if (GET_MODE_SIZE (mode) == 1
4425 && reg_classes_intersect_p (rclass, ADDR_REGS)
4426 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
4429 /* PC-relative addresses must be loaded into an address register first. */
4431 && !reg_class_subset_p (rclass, ADDR_REGS)
4432 && symbolic_operand (x, VOIDmode))
4438 /* Implement PREFERRED_RELOAD_CLASS. */
4441 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
4443 enum reg_class secondary_class;
4445 /* If RCLASS might need a secondary reload, try restricting it to
4446 a class that doesn't. */
4447 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
4448 if (secondary_class != NO_REGS
4449 && reg_class_subset_p (secondary_class, rclass))
4450 return secondary_class;
4452 /* Prefer to use moveq for in-range constants. */
4453 if (GET_CODE (x) == CONST_INT
4454 && reg_class_subset_p (DATA_REGS, rclass)
4455 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
4458 /* ??? Do we really need this now? */
4459 if (GET_CODE (x) == CONST_DOUBLE
4460 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4462 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
4471 /* Return floating point values in a 68881 register. This makes 68881 code
4472 a little bit faster. It also makes -msoft-float code incompatible with
4473 hard-float code, so people have to be careful not to mix the two.
4474 For ColdFire it was decided the ABI incompatibility is undesirable.
4475 If there is need for a hard-float ABI it is probably worth doing it
4476 properly and also passing function arguments in FP registers. */
4478 m68k_libcall_value (enum machine_mode mode)
4485 return gen_rtx_REG (mode, FP0_REG);
4490 return gen_rtx_REG (mode, D0_REG);
4494 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
4496 enum machine_mode mode;
4498 mode = TYPE_MODE (valtype);
4504 return gen_rtx_REG (mode, FP0_REG);
4510 /* If the function returns a pointer, push that into %a0. */
4511 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
4512 /* For compatibility with the large body of existing code which
4513 does not always properly declare external functions returning
4514 pointer types, the m68k/SVR4 convention is to copy the value
4515 returned for pointer functions from a0 to d0 in the function
4516 epilogue, so that callers that have neglected to properly
4517 declare the callee can still find the correct return value in
4519 return gen_rtx_PARALLEL
4522 gen_rtx_EXPR_LIST (VOIDmode,
4523 gen_rtx_REG (mode, A0_REG),
4525 gen_rtx_EXPR_LIST (VOIDmode,
4526 gen_rtx_REG (mode, D0_REG),
4528 else if (POINTER_TYPE_P (valtype))
4529 return gen_rtx_REG (mode, A0_REG);
4531 return gen_rtx_REG (mode, D0_REG);
4534 /* Worker function for TARGET_RETURN_IN_MEMORY. */
4535 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
4537 m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4539 enum machine_mode mode = TYPE_MODE (type);
4541 if (mode == BLKmode)
4544 /* If TYPE's known alignment is less than the alignment of MODE that
4545 would contain the structure, then return in memory. We need to
4546 do so to maintain the compatibility between code compiled with
4547 -mstrict-align and that compiled with -mno-strict-align. */
4548 if (AGGREGATE_TYPE_P (type)
4549 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
4556 /* CPU to schedule the program for. */
4557 enum attr_cpu m68k_sched_cpu;
4568 /* Implicit mem reference (e.g. stack). */
4571 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
4574 /* Memory with offset but without indexing. EA mode 5. */
4577 /* Memory with indexing. EA mode 6. */
4580 /* Memory referenced by absolute address. EA mode 7. */
4583 /* Immediate operand that doesn't require extension word. */
4586 /* Immediate 16 bit operand. */
4589 /* Immediate 32 bit operand. */
4593 /* True if current insn doesn't have complete pipeline description. */
4594 static bool sched_guess_p;
4596 /* Return type of memory ADDR_RTX refers to. */
4597 static enum attr_op_type
4598 sched_address_type (enum machine_mode mode, rtx addr_rtx)
4600 struct m68k_address address;
4602 if (!m68k_decompose_address (mode, addr_rtx,
4603 reload_completed, &address))
4605 gcc_assert (sched_guess_p);
4606 /* Reload will likely fix the address to be in the register. */
4607 return OP_TYPE_MEM234;
4610 if (address.scale != 0)
4611 return OP_TYPE_MEM6;
4613 if (address.base != NULL_RTX)
4615 if (address.offset == NULL_RTX)
4616 return OP_TYPE_MEM234;
4618 return OP_TYPE_MEM5;
4621 gcc_assert (address.offset != NULL_RTX);
4623 return OP_TYPE_MEM7;
4626 /* Return type of the operand OP.
4627 If ADDRESS_P is true, return type of memory location OP refers to. */
4628 static enum attr_op_type
4629 sched_operand_type (rtx op, bool address_p)
4631 gcc_assert (op != NULL_RTX);
4634 return sched_address_type (QImode, op);
4636 if (memory_operand (op, VOIDmode))
4637 return sched_address_type (GET_MODE (op), XEXP (op, 0));
4639 if (register_operand (op, VOIDmode))
4642 if (GET_CODE (op) == CONST_INT)
4644 /* ??? Below condition should probably check if the operation is
4645 signed or unsigned. */
4646 if (IN_RANGE (INTVAL (op), -0x8000, 0x7fff))
4647 return OP_TYPE_IMM_W;
4649 return OP_TYPE_IMM_L;
4652 if (GET_CODE (op) == CONST_DOUBLE)
4654 switch (GET_MODE (op))
4657 return OP_TYPE_IMM_W;
4661 return OP_TYPE_IMM_L;
4668 if (symbolic_operand (op, VOIDmode)
4671 switch (GET_MODE (op))
4674 return OP_TYPE_IMM_Q;
4677 return OP_TYPE_IMM_W;
4680 return OP_TYPE_IMM_L;
4683 if (GET_CODE (op) == SYMBOL_REF)
4684 /* ??? Just a guess. Probably we can guess better using length
4685 attribute of the instructions. */
4686 return OP_TYPE_IMM_W;
4688 return OP_TYPE_IMM_L;
4692 gcc_assert (sched_guess_p);
4697 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
4698 If ADDRESS_P is true, return type of memory location operand refers to. */
4699 static enum attr_op_type
4700 sched_attr_op_type (rtx insn, bool opx_p, bool address_p)
4704 extract_constrain_insn_cached (insn);
4707 i = get_attr_opx (insn);
4709 i = get_attr_opy (insn);
4711 if (i >= recog_data.n_operands)
4713 gcc_assert (sched_guess_p);
4717 return sched_operand_type (recog_data.operand[i], address_p);
4720 /* Implement opx_type attribute.
4721 Return type of INSN's operand X.
4722 If ADDRESS_P is true, return type of memory location operand refers to. */
4724 m68k_sched_attr_opx_type (rtx insn, int address_p)
4726 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4728 switch (sched_attr_op_type (insn, true, address_p != 0))
4731 return OPX_TYPE_REG;
4734 return OPX_TYPE_MEM1;
4736 case OP_TYPE_MEM234:
4737 return OPX_TYPE_MEM234;
4740 return OPX_TYPE_MEM5;
4743 return OPX_TYPE_MEM6;
4746 return OPX_TYPE_MEM7;
4749 return OPX_TYPE_IMM_Q;
4752 return OPX_TYPE_IMM_W;
4755 return OPX_TYPE_IMM_L;
4763 /* Implement opy_type attribute.
4764 Return type of INSN's operand Y.
4765 If ADDRESS_P is true, return type of memory location operand refers to. */
4767 m68k_sched_attr_opy_type (rtx insn, int address_p)
4769 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4771 switch (sched_attr_op_type (insn, false, address_p != 0))
4774 return OPY_TYPE_REG;
4777 return OPY_TYPE_MEM1;
4779 case OP_TYPE_MEM234:
4780 return OPY_TYPE_MEM234;
4783 return OPY_TYPE_MEM5;
4786 return OPY_TYPE_MEM6;
4789 return OPY_TYPE_MEM7;
4792 return OPY_TYPE_IMM_Q;
4795 return OPY_TYPE_IMM_W;
4798 return OPY_TYPE_IMM_L;
4806 /* Return the size of INSN. */
4808 m68k_sched_attr_size (rtx insn)
4812 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4814 switch (get_attr_type1 (insn))
4825 switch (get_attr_opx_type (insn))
4830 case OPX_TYPE_MEM234:
4831 case OPY_TYPE_IMM_Q:
4836 /* Here we assume that most absolute references are short. */
4838 case OPY_TYPE_IMM_W:
4842 case OPY_TYPE_IMM_L:
4850 switch (get_attr_opy_type (insn))
4855 case OPY_TYPE_MEM234:
4856 case OPY_TYPE_IMM_Q:
4861 /* Here we assume that most absolute references are short. */
4863 case OPY_TYPE_IMM_W:
4867 case OPY_TYPE_IMM_L:
4877 gcc_assert (sched_guess_p);
4885 /* Implement op_mem attribute. */
4887 m68k_sched_attr_op_mem (rtx insn)
4889 enum attr_opy_mem opy;
4890 enum attr_opx_mem opx;
4892 sched_guess_p = (get_attr_guess (insn) == GUESS_YES);
4894 opy = get_attr_opy_mem (insn);
4895 opx = get_attr_opx_mem (insn);
4897 if (opy == OPY_MEM_R && opx == OPX_MEM_R)
4900 if (opy == OPY_MEM_R && opx == OPX_MEM_M)
4902 switch (get_attr_opx_access (insn))
4914 gcc_assert (sched_guess_p);
4915 return OP_MEM_UNKNOWN;
4919 if (opy == OPY_MEM_R && opx == OPX_MEM_I)
4921 switch (get_attr_opx_access (insn))
4933 gcc_assert (sched_guess_p);
4934 return OP_MEM_UNKNOWN;
4938 if (opy == OPY_MEM_M && opx == OPX_MEM_R)
4941 if (opy == OPY_MEM_M && opx == OPX_MEM_M)
4943 switch (get_attr_opx_access (insn))
4949 gcc_assert (sched_guess_p);
4950 return OP_MEM_UNKNOWN;
4954 if (opy == OPY_MEM_M && opx == OPX_MEM_I)
4956 switch (get_attr_opx_access (insn))
4962 gcc_assert (sched_guess_p);
4963 return OP_MEM_UNKNOWN;
4967 if (opy == OPY_MEM_I && opx == OPX_MEM_R)
4971 if (opy == OPY_MEM_I && opx == OPX_MEM_M)
4973 switch (get_attr_opx_access (insn))
4979 gcc_assert (sched_guess_p);
4980 return OP_MEM_UNKNOWN;
4984 gcc_assert (sched_guess_p);
4985 return OP_MEM_UNKNOWN;
4988 /* Jump instructions types. Indexed by INSN_UID.
4989 The same rtl insn can be expanded into different asm instructions
4990 depending on the cc0_status. To properly determine type of jump
4991 instructions we scan instruction stream and map jumps types to this
4993 static enum attr_type *sched_branch_type;
4995 /* Return the type of the jump insn. */
4997 m68k_sched_branch_type (rtx insn)
4999 enum attr_type type;
5001 type = sched_branch_type[INSN_UID (insn)];
5003 gcc_assert (type != 0);
5008 /* Implement type2 attribute. */
5010 m68k_sched_attr_type2 (rtx insn)
5012 switch (get_attr_type1 (insn))
5014 case TYPE1_ALU_REG1:
5015 case TYPE1_ALU_REGX:
5048 return TYPE2_MOVE_L;
5064 gcc_assert (get_attr_guess (insn) == GUESS_YES);
5065 return TYPE2_UNKNOWN;
5069 /* An empty state that is used in m68k_sched_adjust_cost. */
5070 static state_t sched_adjust_cost_state;
5072 /* Implement adjust_cost scheduler hook.
5073 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5075 m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
5080 if (recog_memoized (def_insn) < 0
5081 || recog_memoized (insn) < 0)
5084 /* Don't try to issue INSN earlier than DFA permits.
5085 This is especially useful for instructions that write to memory,
5086 as their true dependence (default) latency is better to be set to 0
5087 to workaround alias analysis limitations.
5088 This is, in fact, a machine independent tweak, so, probably,
5089 it should be moved to haifa-sched.c: insn_cost (). */
5091 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
5098 /* Size of the instruction buffer in words. */
5099 static int sched_ib_size;
5101 /* Number of filled words in the instruction buffer. */
5102 static int sched_ib_filled;
5104 /* An insn that reserves (marks empty) one word in the instruction buffer. */
5105 static rtx sched_ib_insn;
5107 /* ID of memory unit. */
5108 static int sched_mem_unit_code;
5110 /* Implementation of the targetm.sched.variable_issue () hook.
5111 It is called after INSN was issued. It returns the number of insns
5112 that can possibly get scheduled on the current cycle.
5113 It is used here to determine the effect of INSN on the instruction
5116 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
5117 int sched_verbose ATTRIBUTE_UNUSED,
5118 rtx insn, int can_issue_more)
5122 if (recog_memoized (insn) >= 0)
5124 insn_size = get_attr_size (insn);
5126 gcc_assert (insn_size <= sched_ib_filled);
5130 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
5131 || asm_noperands (PATTERN (insn)) >= 0)
5132 insn_size = sched_ib_filled;
5136 sched_ib_filled -= insn_size;
5138 return can_issue_more;
5141 /* Statistics gatherer. */
5145 /* Something needs to be done for this insn. */
5148 /* Support for this insn is complete. */
5151 /* This insn didn't require much effort to support it. */
5153 } sched_dump_class_def;
5155 /* Pointer to functions that classifies insns into 3 above classes. */
5156 typedef sched_dump_class_def (*sched_dump_class_func_t) (rtx);
5158 /* Return statistical type of INSN regarding splits. */
5159 static sched_dump_class_def
5160 sched_dump_split_class (rtx insn)
5164 i = recog_memoized (insn);
5165 gcc_assert (i >= 0);
5167 switch (get_attr_split (insn))
5170 return SCHED_DUMP_TODO;
5173 return SCHED_DUMP_DONE;
5176 return SCHED_DUMP_NOTHING;
5183 /* ID of the guess unit. */
5184 static int sched_dump_dfa_guess_unit_code;
5186 /* DFA state for use in sched_dump_dfa_class (). */
5187 static state_t sched_dump_dfa_state;
5189 /* Return statistical type of INSN regarding DFA reservations. */
5190 static sched_dump_class_def
5191 sched_dump_dfa_class (rtx insn)
5195 i = recog_memoized (insn);
5196 gcc_assert (i >= 0 && insn_has_dfa_reservation_p (insn));
5198 if (sched_dump_split_class (insn) == SCHED_DUMP_TODO)
5199 /* Insn is not yet ready for reservations. */
5200 return SCHED_DUMP_NOTHING;
5202 state_reset (sched_dump_dfa_state);
5204 if (state_transition (sched_dump_dfa_state, insn) >= 0)
5207 if (cpu_unit_reservation_p (sched_dump_dfa_state,
5208 sched_dump_dfa_guess_unit_code))
5209 return SCHED_DUMP_TODO;
5211 return SCHED_DUMP_DONE;
5214 /* Dump statistics on current function into file DUMP_FILENAME and prefix
5215 each entry with PREFIX.
5216 Instructions are classified with DUMP_CLASS. */
5218 m68k_sched_dump (sched_dump_class_func_t dump_class,
5219 const char *prefix, FILE *dump)
5227 gcc_assert (dump != NULL);
5229 present = sbitmap_alloc (CODE_FOR_nothing);
5230 sbitmap_zero (present);
5232 todos = xcalloc (CODE_FOR_nothing, sizeof (*todos));
5233 dones = xcalloc (CODE_FOR_nothing, sizeof (*dones));
5234 nothings = xcalloc (CODE_FOR_nothing, sizeof (*nothings));
5236 /* Gather statistics. */
5237 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
5239 if (INSN_P (insn) && recog_memoized (insn) >= 0)
5241 enum insn_code code;
5243 code = INSN_CODE (insn);
5244 gcc_assert (code < CODE_FOR_nothing);
5246 SET_BIT (present, code);
5248 switch (dump_class (insn))
5250 case SCHED_DUMP_TODO:
5254 case SCHED_DUMP_DONE:
5258 case SCHED_DUMP_NOTHING:
5265 /* Print statisctics. */
5268 sbitmap_iterator si;
5277 EXECUTE_IF_SET_IN_SBITMAP (present, 0, i, si)
5282 enum insn_code code;
5284 code = (enum insn_code) i;
5288 nothing = nothings[code];
5292 total_nothing += nothing;
5297 "%s: %3d: %d / %d / %d ;",
5298 prefix, code, todo, done, nothing);
5303 name = get_insn_name (code);
5306 fprintf (dump, " {%s}\n", name);
5308 fprintf (dump, " {unknown}\n");
5313 gcc_assert (CODE_FOR_nothing < 999);
5316 "%s: 999: %d / %d / %d ; {total}\n",
5317 prefix, total_todo, total_done, total_nothing);
5327 sbitmap_free (present);
5331 /* Implementation of targetm.sched.md_init_global () hook.
5332 It is invoked once per scheduling pass and is used here
5333 to initialize scheduler constants. */
5335 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
5336 int sched_verbose ATTRIBUTE_UNUSED,
5337 int n_insns ATTRIBUTE_UNUSED)
5339 /* Init branch types. */
5343 sched_branch_type = xcalloc (get_max_uid () + 1,
5344 sizeof (*sched_branch_type));
5346 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
5349 /* !!! FIXME: Implement real scan here. */
5350 sched_branch_type[INSN_UID (insn)] = TYPE_BCC;
5354 if (reload_completed && sched_verbose >= 8)
5355 /* Dump statistics. */
5357 m68k_sched_dump (sched_dump_split_class, "m68k_sched_split",
5360 sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_v2_guess");
5361 sched_dump_dfa_state = alloca (state_size ());
5363 m68k_sched_dump (sched_dump_dfa_class, "m68k_sched_dfa",
5366 sched_dump_dfa_state = NULL;
5367 sched_dump_dfa_guess_unit_code = 0;
5370 /* Setup target cpu. */
5371 switch (m68k_sched_cpu)
5375 sched_mem_unit_code = get_cpu_unit_code ("cf_v2_mem");
5382 sched_adjust_cost_state = xmalloc (state_size ());
5383 state_reset (sched_adjust_cost_state);
5386 emit_insn (gen_ib ());
5387 sched_ib_insn = get_insns ();
5391 /* Scheduling pass is now finished. Free/reset static variables. */
5393 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
5394 int verbose ATTRIBUTE_UNUSED)
5396 sched_ib_insn = NULL;
5398 free (sched_adjust_cost_state);
5399 sched_adjust_cost_state = NULL;
5401 sched_mem_unit_code = 0;
5404 free (sched_branch_type);
5405 sched_branch_type = NULL;
5408 /* Implementation of targetm.sched.md_init () hook.
5409 It is invoked each time scheduler starts on the new block (basic block or
5410 extended basic block). */
5412 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
5413 int sched_verbose ATTRIBUTE_UNUSED,
5414 int n_insns ATTRIBUTE_UNUSED)
5416 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
5417 the first cycle. Workaround that. */
5418 sched_ib_filled = -2;
5421 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
5422 It is invoked just before current cycle finishes and is used here
5423 to track if instruction buffer got its two words this cycle. */
5425 m68k_sched_dfa_pre_advance_cycle (void)
5427 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
5429 sched_ib_filled += 2;
5431 if (sched_ib_filled > sched_ib_size)
5432 sched_ib_filled = sched_ib_size;
5436 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
5437 It is invoked just after new cycle begins and is used here
5438 to setup number of filled words in the instruction buffer so that
5439 instructions which won't have all their words prefetched would be
5440 stalled for a cycle. */
5442 m68k_sched_dfa_post_advance_cycle (void)
5447 /* Setup number of prefetched instruction words in the instruction
5449 for (i = sched_ib_filled, n = sched_ib_size; i < n; ++i)
5451 if (state_transition (curr_state, sched_ib_insn) >= 0)