1 ;; ColdFire V1, V2 and V3 DFA description.
2 ;; Copyright (C) 2007 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 ;; Boston, MA 02110-1301, USA.
22 ;; Intruction types recognized by DFA.
23 ;; This attribute correspond to type1 attribute with the exceptions below.
24 ;; omove - optimized move. All explicit loads on cfv1 and long explicit
25 ;; loads on cfv2 execute one cycle faster then they should.
26 ;; Supposedly, that is due to combined instruction decoding
27 ;; and address generation phases.
28 ;; ??? To let genattrtab live, implement this attribute in C.
30 "alu, alu_reg, bcc, bra, call, jmp, lea, mul_l, mul_w, omove, pea,
32 (symbol_ref "m68k_sched_attr_type2 (insn)"))
35 (define_automaton "cf_ib")
37 ;; These pseudo units are used to model instruction buffer of ColdFire cores.
38 ;; Instruction of size N can be issued only when cf_ib_wN is available.
39 (define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cf_ib")
41 ;; Instruction occupies 1 word in the instruction buffer.
42 (define_reservation "cf_ib1" "cf_ib_w1")
43 ;; Instruction occupies 2 words in the instruction buffer.
44 (define_reservation "cf_ib2" "cf_ib_w1+cf_ib_w2")
45 ;; Instruction occupies 3 words in the instruction buffer.
46 (define_reservation "cf_ib3" "cf_ib_w1+cf_ib_w2+cf_ib_w3")
48 ;; This reservation is used at the start of each cycle to setup the maximal
49 ;; length of instruction that can be issued on current cycle.
50 ;; E.g., when this reservation is applied for the first time, cf_ib_w3
51 ;; resource is marked busy, thus filtering out all 3-word insns.
53 ;; This reservation requires deterministic automaton.
55 ;; At each cycle, given that memory bus is available (i.e., there is no
56 ;; pending memory operation), instruction fetch pipeline (IFP) prefetches
57 ;; two instruction words into instruction buffer (IB).
58 (define_insn_reservation "cf_ib1" 0
59 (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
60 (eq_attr "type" "ib"))
61 "cf_ib_w3|cf_ib_w2|cf_ib_w1")
63 ;; Operand Execution Pipeline
64 (define_automaton "cf_oep")
66 (define_cpu_unit "cf_dsoc, cf_agex" "cf_oep")
68 ;; A memory unit that is reffered to as 'certain hardware resources' in
69 ;; ColdFire reference manuals. This unit remains occupied for two cycles
70 ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
71 ;; two consecutive stores.
72 (define_automaton "cf_chr")
74 (define_cpu_unit "cf_chr" "cf_chr")
77 (define_automaton "cf_mem")
79 ;; When memory bus is subscribed, that implies that instruction buffer won't
80 ;; get its portion this cycle. To model that we query if cf_mem unit is
81 ;; subscribed and adjust number of prefetched instruction words accordingly.
83 (define_query_cpu_unit "cf_mem1, cf_mem2" "cf_mem")
85 (define_reservation "cf_mem" "cf_mem1+cf_mem2")
87 ;; Register to register move.
89 (define_reservation "cfv123_alu_00"
92 ;; Load from a memory location.
94 (define_reservation "cfv12_alu_10"
95 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex")
97 (define_reservation "cfv12_omove_10"
98 "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex")
100 (define_reservation "cfv3_alu_10"
101 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
103 (define_reservation "cfv3_omove_10"
104 "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
106 ;; Load from an indexed location.
108 (define_reservation "cfv12_alu_i0"
109 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
111 (define_reservation "cfv12_omove_i0"
112 "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
114 (define_reservation "cfv3_alu_i0"
115 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
117 (define_reservation "cfv3_omove_i0"
118 "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
120 ;; Store to a memory location.
122 (define_reservation "cfv12_alu_01"
123 "cf_dsoc+cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
125 (define_reservation "cfv3_alu_01"
126 "cf_dsoc+cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
128 ;; Store to an indexed location.
130 (define_reservation "cfv12_alu_0i"
131 "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
133 (define_reservation "cfv3_alu_0i"
134 "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
136 ;; Load from a memory location and store to a memory location.
138 (define_reservation "cfv12_alu_11"
139 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
141 (define_reservation "cfv12_omove_11"
142 "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
144 (define_reservation "cfv3_alu_11"
145 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
147 (define_reservation "cfv3_omove_11"
148 "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
150 ;; Load from an indexed location and store to a memory location.
152 (define_reservation "cfv12_alu_i1"
153 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
155 (define_reservation "cfv12_omove_i1"
156 "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
158 (define_reservation "cfv3_alu_i1"
159 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
161 (define_reservation "cfv3_omove_i1"
162 "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
164 ;; Load from a memory location and store to an indexed location.
166 (define_reservation "cfv12_alu_1i"
167 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
169 (define_reservation "cfv12_omove_1i"
170 "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
172 (define_reservation "cfv3_alu_1i"
173 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
175 (define_reservation "cfv3_omove_1i"
176 "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
178 ;; Lea operation for a memory location.
180 (define_reservation "cfv123_lea_10"
183 ;; Lea operation for an indexed location.
185 (define_reservation "cfv123_lea_i0"
186 "cf_dsoc,cf_agex,cf_agex")
188 ;; Pea operation for a memory location.
190 (define_reservation "cfv12_pea_11"
191 "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
193 (define_reservation "cfv3_pea_11"
194 "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
196 ;; Pea operation for an indexed location.
198 (define_reservation "cfv12_pea_i1"
199 "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
201 (define_reservation "cfv3_pea_i1"
202 "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
204 ;; Long multiplication with no mac.
205 ;; Takes 9-18 cycles.
206 (define_reservation "cfv123_mul_l_00"
207 "cf_dsoc,(cf_agex+cf_dsoc)*17,cf_agex")
209 ;; Word multiplication with no mac.
211 (define_reservation "cfv123_mul_w_00"
212 "cf_dsoc,(cf_agex+cf_dsoc)*8,cf_agex")
214 ;; Long multiplication with no mac.
215 ;; Takes 11-20 cycles.
216 (define_reservation "cfv12_mul_l_10"
217 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*17,cf_agex")
218 ;; Takes 12-21 cycles.
219 (define_reservation "cfv3_mul_l_10"
220 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*17,cf_agex")
222 ;; Word multiplication with no mac.
224 (define_reservation "cfv12_mul_w_10"
225 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
227 (define_reservation "cfv3_mul_w_10"
228 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
230 ;; Word multiplication with no mac.
232 (define_reservation "cfv12_mul_w_i0"
233 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
235 (define_reservation "cfv3_mul_w_i0"
236 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
238 (define_automaton "cf_mac")
240 (define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4"
243 ;; Long multiplication with mac.
245 (define_reservation "cfv123_mac_l_00"
246 "cf_dsoc,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
248 ;; Word multiplication with mac.
250 (define_reservation "cfv123_mac_w_00"
251 "cf_dsoc,cf_agex,cf_mac1,cf_mac2")
253 ;; Long multiplication with mac.
255 (define_reservation "cfv12_mac_l_10"
256 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
258 (define_reservation "cfv3_mac_l_10"
259 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
261 ;; Word multiplication with mac.
263 (define_reservation "cfv12_mac_w_10"
264 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
266 (define_reservation "cfv3_mac_w_10"
267 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
269 ;; Word multiplication with mac.
271 (define_reservation "cfv12_mac_w_i0"
272 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
274 (define_reservation "cfv3_mac_w_i0"
275 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
277 ;; Multiplication with emac.
279 (define_reservation "cfv123_emac_00"
280 "cf_dsoc,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
282 ;; Multiplication with emac.
284 (define_reservation "cfv12_emac_10"
285 "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
287 (define_reservation "cfv3_emac_10"
288 "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
290 ;; Word multiplication with emac.
292 (define_reservation "cfv12_emac_w_i0"
293 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
295 (define_reservation "cfv3_emac_w_i0"
296 "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
298 ;; Return instruction.
299 ;; ??? As return reads target address from stack, use a mem-read reservation
301 ;; ??? It's not clear what the core does during these 5 cycles.
302 ;; ??? Luckily, we don't care that much about an insn that won't be moved.
304 (define_reservation "cfv12_rts" "cfv12_alu_10")
306 (define_reservation "cfv3_rts" "cfv3_alu_10")
309 ;; ??? It's not clear what reservation is best to use for calls.
310 ;; ??? For now we use mem-write + return reservations to reflect the fact of
311 ;; ??? pushing and poping return address to and from the stack.
313 (define_reservation "cfv12_call" "cfv12_alu_01,cfv12_rts")
315 (define_reservation "cfv3_call" "cfv3_alu_01,cfv3_rts")
317 ;; Conditional branch instruction.
318 ;; ??? Branch reservations are unclear to me so far. Luckily, we don't care
319 ;; ??? that much about branches.
321 (define_reservation "cfv12_bcc" "cfv123_alu_00")
323 (define_reservation "cfv3_bcc" "cfv123_alu_00")
325 ;; Unconditional branch instruciton.
327 (define_reservation "cfv12_bra" "cfv12_alu_01")
329 (define_reservation "cfv3_bra" "cfv3_alu_01")
331 ;; Computed jump instruction.
333 (define_reservation "cfv12_jmp"
334 "(cf_dsoc+cf_agex)*3")
336 (define_reservation "cfv3_jmp"
337 "(cf_dsoc+cf_agex)*5")
339 ;; Instruction reservations.
341 ;; Below reservations are simple derivation from the above reservations.
342 ;; Each reservation from the above expands into 3 reservations below - one
343 ;; for each instruction size.
344 ;; A number in the end of reservation's name is the size of the instruction.
346 (define_insn_reservation "cfv123_alu_00_1" 1
347 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
348 (eq_attr "type2" "alu,alu_reg,omove"))
349 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
350 (eq_attr "op_mem" "00"))
351 "cf_ib1+cfv123_alu_00")
353 (define_insn_reservation "cfv123_alu_00_2" 1
354 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
355 (eq_attr "type2" "alu,alu_reg,omove"))
356 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
357 (eq_attr "op_mem" "00"))
358 "cf_ib2+cfv123_alu_00")
360 (define_insn_reservation "cfv123_alu_00_3" 1
361 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
362 (eq_attr "type2" "alu,alu_reg,omove"))
363 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
364 (eq_attr "op_mem" "00"))
365 "cf_ib3+cfv123_alu_00")
367 (define_insn_reservation "cfv12_alu_10_1" 3
368 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
369 (eq_attr "type2" "alu"))
370 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
371 (eq_attr "op_mem" "10"))
372 "cf_ib1+cfv12_alu_10")
374 (define_insn_reservation "cfv12_alu_10_2" 3
375 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
376 (eq_attr "type2" "alu"))
377 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
378 (eq_attr "op_mem" "10"))
379 "cf_ib2+cfv12_alu_10")
381 (define_insn_reservation "cfv12_alu_10_3" 3
382 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
383 (eq_attr "type2" "alu"))
384 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
385 (eq_attr "op_mem" "10"))
386 "cf_ib3+cfv12_alu_10")
388 (define_insn_reservation "cfv12_omove_10_1" 2
389 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
390 (eq_attr "type2" "omove"))
391 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
392 (eq_attr "op_mem" "10"))
393 "cf_ib1+cfv12_omove_10")
395 (define_insn_reservation "cfv12_omove_10_2" 2
396 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
397 (eq_attr "type2" "omove"))
398 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
399 (eq_attr "op_mem" "10"))
400 "cf_ib2+cfv12_omove_10")
402 (define_insn_reservation "cfv12_omove_10_3" 2
403 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
404 (eq_attr "type2" "omove"))
405 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
406 (eq_attr "op_mem" "10"))
407 "cf_ib3+cfv12_omove_10")
409 (define_insn_reservation "cfv3_alu_10_1" 4
410 (and (and (and (eq_attr "cpu" "cfv3")
411 (eq_attr "type2" "alu"))
412 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
413 (eq_attr "op_mem" "10"))
414 "cf_ib1+cfv3_alu_10")
416 (define_insn_reservation "cfv3_alu_10_2" 4
417 (and (and (and (eq_attr "cpu" "cfv3")
418 (eq_attr "type2" "alu"))
419 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
420 (eq_attr "op_mem" "10"))
421 "cf_ib2+cfv3_alu_10")
423 (define_insn_reservation "cfv3_alu_10_3" 4
424 (and (and (and (eq_attr "cpu" "cfv3")
425 (eq_attr "type2" "alu"))
426 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
427 (eq_attr "op_mem" "10"))
428 "cf_ib3+cfv3_alu_10")
430 (define_insn_reservation "cfv3_omove_10_1" 3
431 (and (and (and (eq_attr "cpu" "cfv3")
432 (eq_attr "type2" "omove"))
433 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
434 (eq_attr "op_mem" "10"))
435 "cf_ib1+cfv3_omove_10")
437 (define_insn_reservation "cfv3_omove_10_2" 3
438 (and (and (and (eq_attr "cpu" "cfv3")
439 (eq_attr "type2" "omove"))
440 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
441 (eq_attr "op_mem" "10"))
442 "cf_ib2+cfv3_omove_10")
444 (define_insn_reservation "cfv3_omove_10_3" 3
445 (and (and (and (eq_attr "cpu" "cfv3")
446 (eq_attr "type2" "omove"))
447 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
448 (eq_attr "op_mem" "10"))
449 "cf_ib3+cfv3_omove_10")
451 (define_insn_reservation "cfv12_alu_i0_2" 4
452 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
453 (eq_attr "type2" "alu"))
454 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
455 (eq_attr "op_mem" "i0"))
456 "cf_ib2+cfv12_alu_i0")
458 (define_insn_reservation "cfv12_alu_i0_3" 4
459 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
460 (eq_attr "type2" "alu"))
461 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
462 (eq_attr "op_mem" "i0"))
463 "cf_ib3+cfv12_alu_i0")
465 (define_insn_reservation "cfv12_omove_i0_2" 3
466 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
467 (eq_attr "type2" "omove"))
468 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
469 (eq_attr "op_mem" "i0"))
470 "cf_ib2+cfv12_omove_i0")
472 (define_insn_reservation "cfv12_omove_i0_3" 3
473 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
474 (eq_attr "type2" "omove"))
475 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
476 (eq_attr "op_mem" "i0"))
477 "cf_ib3+cfv12_omove_i0")
479 (define_insn_reservation "cfv3_alu_i0_2" 5
480 (and (and (and (eq_attr "cpu" "cfv3")
481 (eq_attr "type2" "alu"))
482 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
483 (eq_attr "op_mem" "i0"))
484 "cf_ib2+cfv3_alu_i0")
486 (define_insn_reservation "cfv3_alu_i0_3" 5
487 (and (and (and (eq_attr "cpu" "cfv3")
488 (eq_attr "type2" "alu"))
489 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
490 (eq_attr "op_mem" "i0"))
491 "cf_ib3+cfv3_alu_i0")
493 (define_insn_reservation "cfv3_omove_i0_2" 4
494 (and (and (and (eq_attr "cpu" "cfv3")
495 (eq_attr "type2" "omove"))
496 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
497 (eq_attr "op_mem" "i0"))
498 "cf_ib2+cfv3_omove_i0")
500 (define_insn_reservation "cfv3_omove_i0_3" 4
501 (and (and (and (eq_attr "cpu" "cfv3")
502 (eq_attr "type2" "omove"))
503 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
504 (eq_attr "op_mem" "i0"))
505 "cf_ib3+cfv3_omove_i0")
507 (define_insn_reservation "cfv12_alu_01_1" 0
508 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
509 (eq_attr "type2" "alu,omove"))
510 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
511 (eq_attr "op_mem" "01"))
512 "cf_ib1+cfv12_alu_01")
514 (define_insn_reservation "cfv12_alu_01_2" 0
515 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
516 (eq_attr "type2" "alu,omove"))
517 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
518 (eq_attr "op_mem" "01"))
519 "cf_ib2+cfv12_alu_01")
521 (define_insn_reservation "cfv12_alu_01_3" 0
522 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
523 (eq_attr "type2" "alu,omove"))
524 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
525 (eq_attr "op_mem" "01"))
526 "cf_ib3+cfv12_alu_01")
528 (define_insn_reservation "cfv3_alu_01_1" 0
529 (and (and (and (eq_attr "cpu" "cfv3")
530 (eq_attr "type2" "alu,omove"))
531 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
532 (eq_attr "op_mem" "01"))
533 "cf_ib1+cfv3_alu_01")
535 (define_insn_reservation "cfv3_alu_01_2" 0
536 (and (and (and (eq_attr "cpu" "cfv3")
537 (eq_attr "type2" "alu,omove"))
538 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
539 (eq_attr "op_mem" "01"))
540 "cf_ib2+cfv3_alu_01")
542 (define_insn_reservation "cfv3_alu_01_3" 0
543 (and (and (and (eq_attr "cpu" "cfv3")
544 (eq_attr "type2" "alu,omove"))
545 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
546 (eq_attr "op_mem" "01"))
547 "cf_ib3+cfv3_alu_01")
549 (define_insn_reservation "cfv12_alu_0i_2" 0
550 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
551 (eq_attr "type2" "alu,omove"))
552 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
553 (eq_attr "op_mem" "0i"))
554 "cf_ib2+cfv12_alu_0i")
556 (define_insn_reservation "cfv12_alu_0i_3" 0
557 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
558 (eq_attr "type2" "alu,omove"))
559 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
560 (eq_attr "op_mem" "0i"))
561 "cf_ib3+cfv12_alu_0i")
563 (define_insn_reservation "cfv3_alu_0i_2" 0
564 (and (and (and (eq_attr "cpu" "cfv3")
565 (eq_attr "type2" "alu,omove"))
566 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
567 (eq_attr "op_mem" "0i"))
568 "cf_ib2+cfv3_alu_0i")
570 (define_insn_reservation "cfv3_alu_0i_3" 0
571 (and (and (and (eq_attr "cpu" "cfv3")
572 (eq_attr "type2" "alu,omove"))
573 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
574 (eq_attr "op_mem" "0i"))
575 "cf_ib3+cfv3_alu_0i")
577 (define_insn_reservation "cfv12_alu_11_1" 0
578 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
579 (eq_attr "type2" "alu"))
580 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
581 (eq_attr "op_mem" "11"))
582 "cf_ib1+cfv12_alu_11")
584 (define_insn_reservation "cfv12_alu_11_2" 0
585 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
586 (eq_attr "type2" "alu"))
587 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
588 (eq_attr "op_mem" "11"))
589 "cf_ib2+cfv12_alu_11")
591 (define_insn_reservation "cfv12_alu_11_3" 0
592 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
593 (eq_attr "type2" "alu"))
594 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
595 (eq_attr "op_mem" "11"))
596 "cf_ib3+cfv12_alu_11")
598 (define_insn_reservation "cfv12_omove_11_1" 0
599 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
600 (eq_attr "type2" "omove"))
601 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
602 (eq_attr "op_mem" "11"))
603 "cf_ib1+cfv12_omove_11")
605 (define_insn_reservation "cfv12_omove_11_2" 0
606 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
607 (eq_attr "type2" "omove"))
608 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
609 (eq_attr "op_mem" "11"))
610 "cf_ib2+cfv12_omove_11")
612 (define_insn_reservation "cfv12_omove_11_3" 0
613 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
614 (eq_attr "type2" "omove"))
615 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
616 (eq_attr "op_mem" "11"))
617 "cf_ib3+cfv12_omove_11")
619 (define_insn_reservation "cfv3_alu_11_1" 0
620 (and (and (and (eq_attr "cpu" "cfv3")
621 (eq_attr "type2" "alu"))
622 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
623 (eq_attr "op_mem" "11"))
624 "cf_ib1+cfv3_alu_11")
626 (define_insn_reservation "cfv3_alu_11_2" 0
627 (and (and (and (eq_attr "cpu" "cfv3")
628 (eq_attr "type2" "alu"))
629 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
630 (eq_attr "op_mem" "11"))
631 "cf_ib2+cfv3_alu_11")
633 (define_insn_reservation "cfv3_alu_11_3" 0
634 (and (and (and (eq_attr "cpu" "cfv3")
635 (eq_attr "type2" "alu"))
636 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
637 (eq_attr "op_mem" "11"))
638 "cf_ib3+cfv3_alu_11")
640 (define_insn_reservation "cfv3_omove_11_1" 0
641 (and (and (and (eq_attr "cpu" "cfv3")
642 (eq_attr "type2" "omove"))
643 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
644 (eq_attr "op_mem" "11"))
645 "cf_ib1+cfv3_omove_11")
647 (define_insn_reservation "cfv3_omove_11_2" 0
648 (and (and (and (eq_attr "cpu" "cfv3")
649 (eq_attr "type2" "omove"))
650 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
651 (eq_attr "op_mem" "11"))
652 "cf_ib2+cfv3_omove_11")
654 (define_insn_reservation "cfv3_omove_11_3" 0
655 (and (and (and (eq_attr "cpu" "cfv3")
656 (eq_attr "type2" "omove"))
657 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
658 (eq_attr "op_mem" "11"))
659 "cf_ib3+cfv3_omove_11")
661 (define_insn_reservation "cfv12_alu_i1_2" 0
662 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
663 (eq_attr "type2" "alu"))
664 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
665 (eq_attr "op_mem" "i1"))
666 "cf_ib2+cfv12_alu_i1")
668 (define_insn_reservation "cfv12_alu_i1_3" 0
669 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
670 (eq_attr "type2" "alu"))
671 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
672 (eq_attr "op_mem" "i1"))
673 "cf_ib3+cfv12_alu_i1")
675 (define_insn_reservation "cfv12_omove_i1_2" 0
676 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
677 (eq_attr "type2" "omove"))
678 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
679 (eq_attr "op_mem" "i1"))
680 "cf_ib2+cfv12_omove_i1")
682 (define_insn_reservation "cfv12_omove_i1_3" 0
683 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
684 (eq_attr "type2" "omove"))
685 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
686 (eq_attr "op_mem" "i1"))
687 "cf_ib3+cfv12_omove_i1")
689 (define_insn_reservation "cfv3_alu_i1_2" 0
690 (and (and (and (eq_attr "cpu" "cfv3")
691 (eq_attr "type2" "alu"))
692 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
693 (eq_attr "op_mem" "i1"))
694 "cf_ib2+cfv3_alu_i1")
696 (define_insn_reservation "cfv3_alu_i1_3" 0
697 (and (and (and (eq_attr "cpu" "cfv3")
698 (eq_attr "type2" "alu"))
699 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
700 (eq_attr "op_mem" "i1"))
701 "cf_ib3+cfv3_alu_i1")
703 (define_insn_reservation "cfv3_omove_i1_2" 0
704 (and (and (and (eq_attr "cpu" "cfv3")
705 (eq_attr "type2" "omove"))
706 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
707 (eq_attr "op_mem" "i1"))
708 "cf_ib2+cfv3_omove_i1")
710 (define_insn_reservation "cfv3_omove_i1_3" 0
711 (and (and (and (eq_attr "cpu" "cfv3")
712 (eq_attr "type2" "omove"))
713 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
714 (eq_attr "op_mem" "i1"))
715 "cf_ib3+cfv3_omove_i1")
717 (define_insn_reservation "cfv12_alu_1i_2" 0
718 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
719 (eq_attr "type2" "alu"))
720 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
721 (eq_attr "op_mem" "1i"))
722 "cf_ib2+cfv12_alu_1i")
724 (define_insn_reservation "cfv12_alu_1i_3" 0
725 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
726 (eq_attr "type2" "alu"))
727 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
728 (eq_attr "op_mem" "1i"))
729 "cf_ib3+cfv12_alu_1i")
731 (define_insn_reservation "cfv12_omove_1i_2" 0
732 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
733 (eq_attr "type2" "omove"))
734 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
735 (eq_attr "op_mem" "1i"))
736 "cf_ib2+cfv12_omove_1i")
738 (define_insn_reservation "cfv12_omove_1i_3" 0
739 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
740 (eq_attr "type2" "omove"))
741 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
742 (eq_attr "op_mem" "1i"))
743 "cf_ib3+cfv12_omove_1i")
745 (define_insn_reservation "cfv3_alu_1i_2" 0
746 (and (and (and (eq_attr "cpu" "cfv3")
747 (eq_attr "type2" "alu"))
748 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
749 (eq_attr "op_mem" "1i"))
750 "cf_ib2+cfv3_alu_1i")
752 (define_insn_reservation "cfv3_alu_1i_3" 0
753 (and (and (and (eq_attr "cpu" "cfv3")
754 (eq_attr "type2" "alu"))
755 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
756 (eq_attr "op_mem" "1i"))
757 "cf_ib3+cfv3_alu_1i")
759 (define_insn_reservation "cfv3_omove_1i_2" 0
760 (and (and (and (eq_attr "cpu" "cfv3")
761 (eq_attr "type2" "omove"))
762 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
763 (eq_attr "op_mem" "1i"))
764 "cf_ib2+cfv3_omove_1i")
766 (define_insn_reservation "cfv3_omove_1i_3" 0
767 (and (and (and (eq_attr "cpu" "cfv3")
768 (eq_attr "type2" "omove"))
769 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
770 (eq_attr "op_mem" "1i"))
771 "cf_ib3+cfv3_omove_1i")
773 (define_insn_reservation "cfv123_lea_10_1" 1
774 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
775 (eq_attr "type2" "lea"))
776 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
777 (eq_attr "op_mem" "10"))
778 "cf_ib1+cfv123_lea_10")
780 (define_insn_reservation "cfv123_lea_10_2" 1
781 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
782 (eq_attr "type2" "lea"))
783 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
784 (eq_attr "op_mem" "10"))
785 "cf_ib2+cfv123_lea_10")
787 (define_insn_reservation "cfv123_lea_10_3" 1
788 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
789 (eq_attr "type2" "lea"))
790 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
791 (eq_attr "op_mem" "10"))
792 "cf_ib3+cfv123_lea_10")
794 (define_insn_reservation "cfv123_lea_i0_2" 2
795 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
796 (eq_attr "type2" "lea"))
797 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
798 (eq_attr "op_mem" "i0"))
799 "cf_ib2+cfv123_lea_i0")
801 (define_insn_reservation "cfv123_lea_i0_3" 2
802 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
803 (eq_attr "type2" "lea"))
804 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
805 (eq_attr "op_mem" "i0"))
806 "cf_ib3+cfv123_lea_i0")
808 (define_insn_reservation "cfv12_pea_11_1" 0
809 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
810 (eq_attr "type2" "pea"))
811 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
812 (eq_attr "op_mem" "11"))
813 "cf_ib1+cfv12_pea_11")
815 (define_insn_reservation "cfv12_pea_11_2" 0
816 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
817 (eq_attr "type2" "pea"))
818 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
819 (eq_attr "op_mem" "11"))
820 "cf_ib2+cfv12_pea_11")
822 (define_insn_reservation "cfv12_pea_11_3" 0
823 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
824 (eq_attr "type2" "pea"))
825 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
826 (eq_attr "op_mem" "11"))
827 "cf_ib3+cfv12_pea_11")
829 (define_insn_reservation "cfv3_pea_11_1" 0
830 (and (and (and (eq_attr "cpu" "cfv3")
831 (eq_attr "type2" "pea"))
832 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
833 (eq_attr "op_mem" "11"))
834 "cf_ib1+cfv3_pea_11")
836 (define_insn_reservation "cfv3_pea_11_2" 0
837 (and (and (and (eq_attr "cpu" "cfv3")
838 (eq_attr "type2" "pea"))
839 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
840 (eq_attr "op_mem" "11"))
841 "cf_ib2+cfv3_pea_11")
843 (define_insn_reservation "cfv3_pea_11_3" 0
844 (and (and (and (eq_attr "cpu" "cfv3")
845 (eq_attr "type2" "pea"))
846 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
847 (eq_attr "op_mem" "11"))
848 "cf_ib3+cfv3_pea_11")
850 (define_insn_reservation "cfv12_pea_i1_2" 0
851 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
852 (eq_attr "type2" "pea"))
853 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
854 (eq_attr "op_mem" "i1"))
855 "cf_ib2+cfv12_pea_i1")
857 (define_insn_reservation "cfv12_pea_i1_3" 0
858 (and (and (and (eq_attr "cpu" "cfv1,cfv2")
859 (eq_attr "type2" "pea"))
860 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
861 (eq_attr "op_mem" "i1"))
862 "cf_ib3+cfv12_pea_i1")
864 (define_insn_reservation "cfv3_pea_i1_2" 0
865 (and (and (and (eq_attr "cpu" "cfv3")
866 (eq_attr "type2" "pea"))
867 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
868 (eq_attr "op_mem" "i1"))
869 "cf_ib2+cfv3_pea_i1")
871 (define_insn_reservation "cfv3_pea_i1_3" 0
872 (and (and (and (eq_attr "cpu" "cfv3")
873 (eq_attr "type2" "pea"))
874 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
875 (eq_attr "op_mem" "i1"))
876 "cf_ib3+cfv3_pea_i1")
878 (define_insn_reservation "cfv123_mul_l_00_1" 18
879 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
880 (eq_attr "mac" "no"))
881 (eq_attr "type2" "mul_l"))
882 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
883 (eq_attr "op_mem" "00"))
884 "cf_ib1+cfv123_mul_l_00")
886 (define_insn_reservation "cfv123_mul_l_00_2" 18
887 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
888 (eq_attr "mac" "no"))
889 (eq_attr "type2" "mul_l"))
890 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
891 (eq_attr "op_mem" "00"))
892 "cf_ib2+cfv123_mul_l_00")
894 (define_insn_reservation "cfv123_mul_l_00_3" 18
895 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
896 (eq_attr "mac" "no"))
897 (eq_attr "type2" "mul_l"))
898 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
899 (eq_attr "op_mem" "00"))
900 "cf_ib3+cfv123_mul_l_00")
902 (define_insn_reservation "cfv123_mul_w_00_1" 9
903 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
904 (eq_attr "mac" "no"))
905 (eq_attr "type2" "mul_w"))
906 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
907 (eq_attr "op_mem" "00"))
908 "cf_ib1+cfv123_mul_w_00")
910 (define_insn_reservation "cfv123_mul_w_00_2" 9
911 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
912 (eq_attr "mac" "no"))
913 (eq_attr "type2" "mul_w"))
914 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
915 (eq_attr "op_mem" "00"))
916 "cf_ib2+cfv123_mul_w_00")
918 (define_insn_reservation "cfv123_mul_w_00_3" 9
919 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
920 (eq_attr "mac" "no"))
921 (eq_attr "type2" "mul_w"))
922 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
923 (eq_attr "op_mem" "00"))
924 "cf_ib3+cfv123_mul_w_00")
926 (define_insn_reservation "cfv12_mul_l_10_1" 20
927 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
928 (eq_attr "mac" "no"))
929 (eq_attr "type2" "mul_l"))
930 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
931 (eq_attr "op_mem" "10"))
932 "cf_ib1+cfv12_mul_l_10")
934 (define_insn_reservation "cfv12_mul_l_10_2" 20
935 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
936 (eq_attr "mac" "no"))
937 (eq_attr "type2" "mul_l"))
938 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
939 (eq_attr "op_mem" "10"))
940 "cf_ib2+cfv12_mul_l_10")
942 (define_insn_reservation "cfv12_mul_l_10_3" 20
943 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
944 (eq_attr "mac" "no"))
945 (eq_attr "type2" "mul_l"))
946 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
947 (eq_attr "op_mem" "10"))
948 "cf_ib3+cfv12_mul_l_10")
950 (define_insn_reservation "cfv3_mul_l_10_1" 21
951 (and (and (and (and (eq_attr "cpu" "cfv3")
952 (eq_attr "mac" "no"))
953 (eq_attr "type2" "mul_l"))
954 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
955 (eq_attr "op_mem" "10"))
956 "cf_ib1+cfv3_mul_l_10")
958 (define_insn_reservation "cfv3_mul_l_10_2" 21
959 (and (and (and (and (eq_attr "cpu" "cfv3")
960 (eq_attr "mac" "no"))
961 (eq_attr "type2" "mul_l"))
962 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
963 (eq_attr "op_mem" "10"))
964 "cf_ib2+cfv3_mul_l_10")
966 (define_insn_reservation "cfv3_mul_l_10_3" 21
967 (and (and (and (and (eq_attr "cpu" "cfv3")
968 (eq_attr "mac" "no"))
969 (eq_attr "type2" "mul_l"))
970 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
971 (eq_attr "op_mem" "10"))
972 "cf_ib3+cfv3_mul_l_10")
974 (define_insn_reservation "cfv12_mul_w_10_1" 11
975 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
976 (eq_attr "mac" "no"))
977 (eq_attr "type2" "mul_w"))
978 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
979 (eq_attr "op_mem" "10"))
980 "cf_ib1+cfv12_mul_w_10")
982 (define_insn_reservation "cfv12_mul_w_10_2" 11
983 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
984 (eq_attr "mac" "no"))
985 (eq_attr "type2" "mul_w"))
986 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
987 (eq_attr "op_mem" "10"))
988 "cf_ib2+cfv12_mul_w_10")
990 (define_insn_reservation "cfv12_mul_w_10_3" 11
991 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
992 (eq_attr "mac" "no"))
993 (eq_attr "type2" "mul_w"))
994 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
995 (eq_attr "op_mem" "10"))
996 "cf_ib3+cfv12_mul_w_10")
998 (define_insn_reservation "cfv3_mul_w_10_1" 12
999 (and (and (and (and (eq_attr "cpu" "cfv3")
1000 (eq_attr "mac" "no"))
1001 (eq_attr "type2" "mul_w"))
1002 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1003 (eq_attr "op_mem" "10"))
1004 "cf_ib1+cfv3_mul_w_10")
1006 (define_insn_reservation "cfv3_mul_w_10_2" 12
1007 (and (and (and (and (eq_attr "cpu" "cfv3")
1008 (eq_attr "mac" "no"))
1009 (eq_attr "type2" "mul_w"))
1010 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1011 (eq_attr "op_mem" "10"))
1012 "cf_ib2+cfv3_mul_w_10")
1014 (define_insn_reservation "cfv3_mul_w_10_3" 12
1015 (and (and (and (and (eq_attr "cpu" "cfv3")
1016 (eq_attr "mac" "no"))
1017 (eq_attr "type2" "mul_w"))
1018 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1019 (eq_attr "op_mem" "10"))
1020 "cf_ib3+cfv3_mul_w_10")
1022 (define_insn_reservation "cfv12_mul_w_i0_2" 12
1023 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1024 (eq_attr "mac" "no"))
1025 (eq_attr "type2" "mul_w"))
1026 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1027 (eq_attr "op_mem" "i0"))
1028 "cf_ib2+cfv12_mul_w_i0")
1030 (define_insn_reservation "cfv12_mul_w_i0_3" 12
1031 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1032 (eq_attr "mac" "no"))
1033 (eq_attr "type2" "mul_w"))
1034 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1035 (eq_attr "op_mem" "i0"))
1036 "cf_ib3+cfv12_mul_w_i0")
1039 (define_insn_reservation "cfv3_mul_w_i0_2" 13
1040 (and (and (and (and (eq_attr "cpu" "cfv3")
1041 (eq_attr "mac" "no"))
1042 (eq_attr "type2" "mul_w"))
1043 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1044 (eq_attr "op_mem" "i0"))
1045 "cf_ib2+cfv3_mul_w_i0")
1047 (define_insn_reservation "cfv3_mul_w_i0_3" 13
1048 (and (and (and (and (eq_attr "cpu" "cfv3")
1049 (eq_attr "mac" "no"))
1050 (eq_attr "type2" "mul_w"))
1051 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1052 (eq_attr "op_mem" "i0"))
1053 "cf_ib3+cfv3_mul_w_i0")
1055 (define_insn_reservation "cfv123_mac_l_00_1" 5
1056 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1057 (eq_attr "mac" "cf_mac"))
1058 (eq_attr "type2" "mul_l"))
1059 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1060 (eq_attr "op_mem" "00"))
1061 "cf_ib1+cfv123_mac_l_00")
1063 (define_insn_reservation "cfv123_mac_l_00_2" 5
1064 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1065 (eq_attr "mac" "cf_mac"))
1066 (eq_attr "type2" "mul_l"))
1067 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1068 (eq_attr "op_mem" "00"))
1069 "cf_ib2+cfv123_mac_l_00")
1071 (define_insn_reservation "cfv123_mac_l_00_3" 5
1072 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1073 (eq_attr "mac" "cf_mac"))
1074 (eq_attr "type2" "mul_l"))
1075 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1076 (eq_attr "op_mem" "00"))
1077 "cf_ib3+cfv123_mac_l_00")
1079 (define_insn_reservation "cfv123_mac_w_00_1" 3
1080 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1081 (eq_attr "mac" "cf_mac"))
1082 (eq_attr "type2" "mul_w"))
1083 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1084 (eq_attr "op_mem" "00"))
1085 "cf_ib1+cfv123_mac_w_00")
1087 (define_insn_reservation "cfv123_mac_w_00_2" 3
1088 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1089 (eq_attr "mac" "cf_mac"))
1090 (eq_attr "type2" "mul_w"))
1091 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1092 (eq_attr "op_mem" "00"))
1093 "cf_ib2+cfv123_mac_w_00")
1095 (define_insn_reservation "cfv123_mac_w_00_3" 3
1096 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1097 (eq_attr "mac" "cf_mac"))
1098 (eq_attr "type2" "mul_w"))
1099 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1100 (eq_attr "op_mem" "00"))
1101 "cf_ib3+cfv123_mac_w_00")
1103 (define_insn_reservation "cfv12_mac_l_10_1" 7
1104 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1105 (eq_attr "mac" "cf_mac"))
1106 (eq_attr "type2" "mul_l"))
1107 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1108 (eq_attr "op_mem" "10"))
1109 "cf_ib1+cfv12_mac_l_10")
1111 (define_insn_reservation "cfv12_mac_l_10_2" 7
1112 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1113 (eq_attr "mac" "cf_mac"))
1114 (eq_attr "type2" "mul_l"))
1115 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1116 (eq_attr "op_mem" "10"))
1117 "cf_ib2+cfv12_mac_l_10")
1119 (define_insn_reservation "cfv12_mac_l_10_3" 7
1120 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1121 (eq_attr "mac" "cf_mac"))
1122 (eq_attr "type2" "mul_l"))
1123 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1124 (eq_attr "op_mem" "10"))
1125 "cf_ib3+cfv12_mac_l_10")
1127 (define_insn_reservation "cfv3_mac_l_10_1" 8
1128 (and (and (and (and (eq_attr "cpu" "cfv3")
1129 (eq_attr "mac" "cf_mac"))
1130 (eq_attr "type2" "mul_l"))
1131 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1132 (eq_attr "op_mem" "10"))
1133 "cf_ib1+cfv3_mac_l_10")
1135 (define_insn_reservation "cfv3_mac_l_10_2" 8
1136 (and (and (and (and (eq_attr "cpu" "cfv3")
1137 (eq_attr "mac" "cf_mac"))
1138 (eq_attr "type2" "mul_l"))
1139 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1140 (eq_attr "op_mem" "10"))
1141 "cf_ib2+cfv3_mac_l_10")
1143 (define_insn_reservation "cfv3_mac_l_10_3" 8
1144 (and (and (and (and (eq_attr "cpu" "cfv3")
1145 (eq_attr "mac" "cf_mac"))
1146 (eq_attr "type2" "mul_l"))
1147 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1148 (eq_attr "op_mem" "10"))
1149 "cf_ib3+cfv3_mac_l_10")
1151 (define_insn_reservation "cfv12_mac_w_10_1" 5
1152 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1153 (eq_attr "mac" "cf_mac"))
1154 (eq_attr "type2" "mul_w"))
1155 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1156 (eq_attr "op_mem" "10"))
1157 "cf_ib1+cfv12_mac_w_10")
1159 (define_insn_reservation "cfv12_mac_w_10_2" 5
1160 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1161 (eq_attr "mac" "cf_mac"))
1162 (eq_attr "type2" "mul_w"))
1163 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1164 (eq_attr "op_mem" "10"))
1165 "cf_ib2+cfv12_mac_w_10")
1167 (define_insn_reservation "cfv12_mac_w_10_3" 5
1168 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1169 (eq_attr "mac" "cf_mac"))
1170 (eq_attr "type2" "mul_w"))
1171 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1172 (eq_attr "op_mem" "10"))
1173 "cf_ib3+cfv12_mac_w_10")
1175 (define_insn_reservation "cfv3_mac_w_10_1" 6
1176 (and (and (and (and (eq_attr "cpu" "cfv3")
1177 (eq_attr "mac" "cf_mac"))
1178 (eq_attr "type2" "mul_w"))
1179 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1180 (eq_attr "op_mem" "10"))
1181 "cf_ib1+cfv3_mac_w_10")
1183 (define_insn_reservation "cfv3_mac_w_10_2" 6
1184 (and (and (and (and (eq_attr "cpu" "cfv3")
1185 (eq_attr "mac" "cf_mac"))
1186 (eq_attr "type2" "mul_w"))
1187 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1188 (eq_attr "op_mem" "10"))
1189 "cf_ib2+cfv3_mac_w_10")
1191 (define_insn_reservation "cfv3_mac_w_10_3" 6
1192 (and (and (and (and (eq_attr "cpu" "cfv3")
1193 (eq_attr "mac" "cf_mac"))
1194 (eq_attr "type2" "mul_w"))
1195 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1196 (eq_attr "op_mem" "10"))
1197 "cf_ib3+cfv3_mac_w_10")
1199 (define_insn_reservation "cfv12_mac_w_i0_2" 6
1200 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1201 (eq_attr "mac" "cf_mac"))
1202 (eq_attr "type2" "mul_w"))
1203 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1204 (eq_attr "op_mem" "i0"))
1205 "cf_ib2+cfv12_mac_w_i0")
1207 (define_insn_reservation "cfv12_mac_w_i0_3" 6
1208 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1209 (eq_attr "mac" "cf_mac"))
1210 (eq_attr "type2" "mul_w"))
1211 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1212 (eq_attr "op_mem" "i0"))
1213 "cf_ib3+cfv12_mac_w_i0")
1215 (define_insn_reservation "cfv3_mac_w_i0_2" 7
1216 (and (and (and (and (eq_attr "cpu" "cfv3")
1217 (eq_attr "mac" "cf_mac"))
1218 (eq_attr "type2" "mul_w"))
1219 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1220 (eq_attr "op_mem" "i0"))
1221 "cf_ib2+cfv3_mac_w_i0")
1223 (define_insn_reservation "cfv3_mac_w_i0_3" 7
1224 (and (and (and (and (eq_attr "cpu" "cfv3")
1225 (eq_attr "mac" "cf_mac"))
1226 (eq_attr "type2" "mul_w"))
1227 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1228 (eq_attr "op_mem" "i0"))
1229 "cf_ib3+cfv3_mac_w_i0")
1231 (define_insn_reservation "cfv123_emac_00_1" 4
1232 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1233 (eq_attr "mac" "cf_emac"))
1234 (eq_attr "type2" "mul_l,mul_w"))
1235 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1236 (eq_attr "op_mem" "00"))
1237 "cf_ib1+cfv123_emac_00")
1239 (define_insn_reservation "cfv123_emac_00_2" 4
1240 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1241 (eq_attr "mac" "cf_emac"))
1242 (eq_attr "type2" "mul_l,mul_w"))
1243 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1244 (eq_attr "op_mem" "00"))
1245 "cf_ib2+cfv123_emac_00")
1247 (define_insn_reservation "cfv123_emac_00_3" 4
1248 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1249 (eq_attr "mac" "cf_emac"))
1250 (eq_attr "type2" "mul_l,mul_w"))
1251 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1252 (eq_attr "op_mem" "00"))
1253 "cf_ib3+cfv123_emac_00")
1255 (define_insn_reservation "cfv12_emac_10_1" 6
1256 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1257 (eq_attr "mac" "cf_emac"))
1258 (eq_attr "type2" "mul_l,mul_w"))
1259 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1260 (eq_attr "op_mem" "10"))
1261 "cf_ib1+cfv12_emac_10")
1263 (define_insn_reservation "cfv12_emac_10_2" 6
1264 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1265 (eq_attr "mac" "cf_emac"))
1266 (eq_attr "type2" "mul_l,mul_w"))
1267 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1268 (eq_attr "op_mem" "10"))
1269 "cf_ib2+cfv12_emac_10")
1271 (define_insn_reservation "cfv12_emac_10_3" 6
1272 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1273 (eq_attr "mac" "cf_emac"))
1274 (eq_attr "type2" "mul_l,mul_w"))
1275 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1276 (eq_attr "op_mem" "10"))
1277 "cf_ib3+cfv12_emac_10")
1279 (define_insn_reservation "cfv3_emac_10_1" 7
1280 (and (and (and (and (eq_attr "cpu" "cfv3")
1281 (eq_attr "mac" "cf_emac"))
1282 (eq_attr "type2" "mul_l,mul_w"))
1283 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1284 (eq_attr "op_mem" "10"))
1285 "cf_ib1+cfv3_emac_10")
1287 (define_insn_reservation "cfv3_emac_10_2" 7
1288 (and (and (and (and (eq_attr "cpu" "cfv3")
1289 (eq_attr "mac" "cf_emac"))
1290 (eq_attr "type2" "mul_l,mul_w"))
1291 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1292 (eq_attr "op_mem" "10"))
1293 "cf_ib2+cfv3_emac_10")
1295 (define_insn_reservation "cfv3_emac_10_3" 7
1296 (and (and (and (and (eq_attr "cpu" "cfv3")
1297 (eq_attr "mac" "cf_emac"))
1298 (eq_attr "type2" "mul_l,mul_w"))
1299 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1300 (eq_attr "op_mem" "10"))
1301 "cf_ib3+cfv3_emac_10")
1303 (define_insn_reservation "cfv12_emac_w_i0_2" 7
1304 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1305 (eq_attr "mac" "cf_emac"))
1306 (eq_attr "type2" "mul_w"))
1307 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1308 (eq_attr "op_mem" "i0"))
1309 "cf_ib2+cfv12_emac_w_i0")
1311 (define_insn_reservation "cfv12_emac_w_i0_3" 7
1312 (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
1313 (eq_attr "mac" "cf_emac"))
1314 (eq_attr "type2" "mul_w"))
1315 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1316 (eq_attr "op_mem" "i0"))
1317 "cf_ib3+cfv12_emac_w_i0")
1319 (define_insn_reservation "cfv3_emac_w_i0_2" 8
1320 (and (and (and (and (eq_attr "cpu" "cfv3")
1321 (eq_attr "mac" "cf_emac"))
1322 (eq_attr "type2" "mul_w"))
1323 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1324 (eq_attr "op_mem" "i0"))
1325 "cf_ib2+cfv3_emac_w_i0")
1327 (define_insn_reservation "cfv3_emac_w_i0_3" 8
1328 (and (and (and (and (eq_attr "cpu" "cfv3")
1329 (eq_attr "mac" "cf_emac"))
1330 (eq_attr "type2" "mul_w"))
1331 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1332 (eq_attr "op_mem" "i0"))
1333 "cf_ib3+cfv3_emac_w_i0")
1335 (define_insn_reservation "cfv12_rts_1" 5
1336 (and (and (eq_attr "cpu" "cfv1,cfv2")
1337 (eq_attr "type2" "rts"))
1338 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1341 (define_insn_reservation "cfv3_rts_1" 8
1342 (and (and (eq_attr "cpu" "cfv3")
1343 (eq_attr "type2" "rts"))
1344 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1347 (define_insn_reservation "cfv12_call_1" 3
1348 (and (and (eq_attr "cpu" "cfv1,cfv2")
1349 (eq_attr "type2" "call"))
1350 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1351 "cf_ib1+cfv12_call")
1353 (define_insn_reservation "cfv12_call_2" 3
1354 (and (and (eq_attr "cpu" "cfv1,cfv2")
1355 (eq_attr "type2" "call"))
1356 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1357 "cf_ib2+cfv12_call")
1359 (define_insn_reservation "cfv12_call_3" 3
1360 (and (and (eq_attr "cpu" "cfv1,cfv2")
1361 (eq_attr "type2" "call"))
1362 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1363 "cf_ib3+cfv12_call")
1365 (define_insn_reservation "cfv3_call_1" 1
1366 (and (and (eq_attr "cpu" "cfv3")
1367 (eq_attr "type2" "call"))
1368 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1371 (define_insn_reservation "cfv3_call_2" 1
1372 (and (and (eq_attr "cpu" "cfv3")
1373 (eq_attr "type2" "call"))
1374 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1377 (define_insn_reservation "cfv3_call_3" 1
1378 (and (and (eq_attr "cpu" "cfv3")
1379 (eq_attr "type2" "call"))
1380 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1383 (define_insn_reservation "cfv12_bcc_1" 2
1384 (and (and (eq_attr "cpu" "cfv1,cfv2")
1385 (eq_attr "type2" "bcc"))
1386 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1389 (define_insn_reservation "cfv12_bcc_2" 2
1390 (and (and (eq_attr "cpu" "cfv1,cfv2")
1391 (eq_attr "type2" "bcc"))
1392 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1395 (define_insn_reservation "cfv12_bcc_3" 2
1396 (and (and (eq_attr "cpu" "cfv1,cfv2")
1397 (eq_attr "type2" "bcc"))
1398 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1401 (define_insn_reservation "cfv3_bcc_1" 1
1402 (and (and (eq_attr "cpu" "cfv3")
1403 (eq_attr "type2" "bcc"))
1404 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1407 (define_insn_reservation "cfv3_bcc_2" 1
1408 (and (and (eq_attr "cpu" "cfv3")
1409 (eq_attr "type2" "bcc"))
1410 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1413 (define_insn_reservation "cfv3_bcc_3" 1
1414 (and (and (eq_attr "cpu" "cfv3")
1415 (eq_attr "type2" "bcc"))
1416 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1419 (define_insn_reservation "cfv12_bra_1" 2
1420 (and (and (eq_attr "cpu" "cfv1,cfv2")
1421 (eq_attr "type2" "bra"))
1422 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1425 (define_insn_reservation "cfv12_bra_2" 2
1426 (and (and (eq_attr "cpu" "cfv1,cfv2")
1427 (eq_attr "type2" "bra"))
1428 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1431 (define_insn_reservation "cfv12_bra_3" 2
1432 (and (and (eq_attr "cpu" "cfv1,cfv2")
1433 (eq_attr "type2" "bra"))
1434 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1437 (define_insn_reservation "cfv3_bra_1" 1
1438 (and (and (eq_attr "cpu" "cfv3")
1439 (eq_attr "type2" "bra"))
1440 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1443 (define_insn_reservation "cfv3_bra_2" 1
1444 (and (and (eq_attr "cpu" "cfv3")
1445 (eq_attr "type2" "bra"))
1446 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1449 (define_insn_reservation "cfv3_bra_3" 1
1450 (and (and (eq_attr "cpu" "cfv3")
1451 (eq_attr "type2" "bra"))
1452 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1455 (define_insn_reservation "cfv12_jmp_1" 3
1456 (and (and (eq_attr "cpu" "cfv1,cfv2")
1457 (eq_attr "type2" "jmp"))
1458 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1461 (define_insn_reservation "cfv12_jmp_2" 3
1462 (and (and (eq_attr "cpu" "cfv1,cfv2")
1463 (eq_attr "type2" "jmp"))
1464 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1467 (define_insn_reservation "cfv12_jmp_3" 3
1468 (and (and (eq_attr "cpu" "cfv1,cfv2")
1469 (eq_attr "type2" "jmp"))
1470 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1473 (define_insn_reservation "cfv3_jmp_1" 5
1474 (and (and (eq_attr "cpu" "cfv3")
1475 (eq_attr "type2" "jmp"))
1476 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1479 (define_insn_reservation "cfv3_jmp_2" 5
1480 (and (and (eq_attr "cpu" "cfv3")
1481 (eq_attr "type2" "jmp"))
1482 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1485 (define_insn_reservation "cfv3_jmp_3" 5
1486 (and (and (eq_attr "cpu" "cfv3")
1487 (eq_attr "type2" "jmp"))
1488 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1491 ;; Misc reservations.
1493 (define_insn_reservation "cfv12_unlk_1" 2
1494 (and (and (eq_attr "cpu" "cfv1,cfv2")
1495 (eq_attr "type2" "unlk"))
1496 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1497 "cf_ib1+cfv12_alu_10")
1499 (define_insn_reservation "cfv3_unlk_1" 3
1500 (and (and (eq_attr "cpu" "cfv3")
1501 (eq_attr "type2" "unlk"))
1502 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1503 "cf_ib1+cfv3_alu_10")
1505 ;; This automaton is used to gather statistics on insns that need reservations.
1506 (define_automaton "cf_guess")
1508 (define_query_cpu_unit "cf_guess" "cf_guess")
1510 ;; Dummy reservation for instructions that are not handled yet.
1512 (define_insn_reservation "cf_guess_1" 1
1513 (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1514 (eq_attr "guess" "yes"))
1515 (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
1516 "cf_ib1+cf_guess+cf_dsoc+cf_agex")
1518 (define_insn_reservation "cf_guess_2" 1
1519 (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1520 (eq_attr "guess" "yes"))
1521 (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
1522 "cf_ib2+cf_guess+cf_dsoc+cf_agex")
1524 (define_insn_reservation "cf_guess_3" 1
1525 (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
1526 (eq_attr "guess" "yes"))
1527 (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
1528 "cf_ib3+cf_guess+cf_dsoc+cf_agex")