1 /* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
32 #undef WCHAR_TYPE_SIZE
34 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
41 #undef SUBTARGET_SWITCHES
44 /* M32R/X overrides. */
45 /* Print subsidiary information on the compiler version in use. */
46 #define TARGET_VERSION fprintf (stderr, " (m32r/x)");
48 /* Additional flags for the preprocessor. */
49 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
51 /* Assembler switches. */
52 #define ASM_CPU_SPEC \
53 "%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
55 /* Use m32rx specific crt0/crtinit/crtfini files. */
56 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
57 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
59 /* Extra machine dependent switches. */
60 #define SUBTARGET_SWITCHES \
61 { "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
62 { "32r", -TARGET_M32RX_MASK, "" },
64 /* Define this macro as a C expression for the initializer of an array of
65 strings to tell the driver program which options are defaults for this
66 target and thus do not need to be handled specially when using
67 `MULTILIB_OPTIONS'. */
68 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
70 /* Number of additional registers the subtarget defines. */
71 #define SUBTARGET_NUM_REGISTERS 1
73 /* 1 for registers that cannot be allocated. */
74 #define SUBTARGET_FIXED_REGISTERS , 1
76 /* 1 for registers that are not available across function calls. */
77 #define SUBTARGET_CALL_USED_REGISTERS , 1
79 /* Order to allocate model specific registers. */
80 #define SUBTARGET_REG_ALLOC_ORDER , 19
82 /* Registers which are accumulators. */
83 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
85 /* All registers added. */
86 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
88 /* Additional accumulator registers. */
89 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
91 /* Define additional register names. */
92 #define SUBTARGET_REGISTER_NAMES , "a1"
93 /* end M32R/X overrides. */
95 /* Print subsidiary information on the compiler version in use. */
96 #ifndef TARGET_VERSION
97 #define TARGET_VERSION fprintf (stderr, " (m32r)")
100 /* Switch Recognition by gcc.c. Add -G xx support */
102 #undef SWITCH_TAKES_ARG
103 #define SWITCH_TAKES_ARG(CHAR) \
104 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
106 /* Names to predefine in the preprocessor for this target machine. */
107 /* __M32R__ is defined by the existing compiler so we use that. */
108 #define CPP_PREDEFINES "-Acpu=m32r -Amachine=m32r -D__M32R__"
110 /* This macro defines names of additional specifications to put in the specs
111 that can be used in various specifications like CC1_SPEC. Its definition
112 is an initializer with a subgrouping for each command option.
114 Each subgrouping contains a string constant, that defines the
115 specification name, and a string constant that used by the GNU CC driver
118 Do not define this macro if it does not need to do anything. */
120 #ifndef SUBTARGET_EXTRA_SPECS
121 #define SUBTARGET_EXTRA_SPECS
125 #define ASM_CPU_SPEC ""
129 #define CPP_CPU_SPEC ""
133 #define CC1_CPU_SPEC ""
136 #ifndef LINK_CPU_SPEC
137 #define LINK_CPU_SPEC ""
140 #ifndef STARTFILE_CPU_SPEC
141 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
144 #ifndef ENDFILE_CPU_SPEC
145 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
149 #if 0 /* not supported yet */
150 #define RELAX_SPEC "%{mrelax:-relax}"
152 #define RELAX_SPEC ""
156 #define EXTRA_SPECS \
157 { "asm_cpu", ASM_CPU_SPEC }, \
158 { "cpp_cpu", CPP_CPU_SPEC }, \
159 { "cc1_cpu", CC1_CPU_SPEC }, \
160 { "link_cpu", LINK_CPU_SPEC }, \
161 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
162 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
163 { "relax", RELAX_SPEC }, \
164 SUBTARGET_EXTRA_SPECS
166 #define CC1_SPEC "%{G*} %(cc1_cpu)"
168 /* Options to pass on to the assembler. */
170 #define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
172 #undef ASM_FINAL_SPEC
174 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
176 #undef STARTFILE_SPEC
177 #define STARTFILE_SPEC "%(startfile_cpu)"
180 #define ENDFILE_SPEC "%(endfile_cpu)"
184 /* Run-time compilation parameters selecting different hardware subsets. */
186 extern int target_flags;
188 /* If non-zero, tell the linker to do relaxing.
189 We don't do anything with the option, other than recognize it.
190 LINK_SPEC handles passing -relax to the linker.
191 This can cause incorrect debugging information as line numbers may
192 turn out wrong. This shouldn't be specified unless accompanied with -O2
193 [where the user expects debugging information to be less accurate]. */
194 #define TARGET_RELAX_MASK (1 << 0)
196 /* For miscellaneous debugging purposes. */
197 #define TARGET_DEBUG_MASK (1 << 1)
198 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
200 /* Align loops to 32 byte boundaries (cache line size). */
201 /* ??? This option is experimental and is not documented. */
202 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
203 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
205 /* Change issue rate. */
206 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
207 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
209 /* Change branch cost */
210 #define TARGET_BRANCH_COST_MASK (1 << 4)
211 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
213 /* Target machine to compile for. */
214 #define TARGET_M32R 1
216 /* Support extended instruction set. */
217 #define TARGET_M32RX_MASK (1 << 5)
218 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
220 #define TARGET_M32R (! TARGET_M32RX)
222 /* Macro to define tables used to set the flags.
223 This is a list in braces of pairs in braces,
224 each pair being { "NAME", VALUE }
225 where VALUE is the bits to set or minus the bits to clear.
226 An empty string NAME is used to identify the default VALUE. */
228 #ifndef SUBTARGET_SWITCHES
229 #define SUBTARGET_SWITCHES
232 #ifndef TARGET_DEFAULT
233 #define TARGET_DEFAULT 0
236 #define TARGET_SWITCHES \
238 /* { "relax", TARGET_RELAX_MASK, "" }, \
239 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \
240 { "debug", TARGET_DEBUG_MASK, \
241 N_("Display compile time statistics") }, \
242 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \
243 N_("Align all loops to 32 byte boundary") }, \
244 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
245 { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \
246 N_("Only issue one instruction per cycle") }, \
247 { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \
248 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \
249 N_("Prefer branches over conditional execution") }, \
250 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
252 { "", TARGET_DEFAULT, "" } \
255 extern const char * m32r_model_string;
256 extern const char * m32r_sdata_string;
258 #ifndef SUBTARGET_OPTIONS
259 #define SUBTARGET_OPTIONS
262 #define TARGET_OPTIONS \
264 { "model=", & m32r_model_string, \
265 N_("Code size: small, medium or large") }, \
266 { "sdata=", & m32r_sdata_string, \
267 N_("Small data area: none, sdata, use") } \
273 Code models are used to select between two choices of two separate
274 possibilities (address space size, call insn to use):
276 small: addresses use 24 bits, use bl to make calls
277 medium: addresses use 32 bits, use bl to make calls (*1)
278 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
280 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
281 using this one doesn't make much sense.
283 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
284 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
286 Internally these are recorded as TARGET_ADDR{24,32} and
289 The __model__ attribute can be used to select the code model to use when
290 accessing particular objects. */
292 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
294 extern enum m32r_model m32r_model;
295 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
296 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
297 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
298 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
299 #define TARGET_ADDR32 (! TARGET_ADDR24)
300 #define TARGET_CALL26 (! TARGET_CALL32)
301 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
303 /* The default is the small model. */
304 #ifndef M32R_MODEL_DEFAULT
305 #define M32R_MODEL_DEFAULT "small"
310 The SDA consists of sections .sdata, .sbss, and .scommon.
311 .scommon isn't a real section, symbols in it have their section index
312 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
314 Two switches control the SDA:
316 -G NNN - specifies the maximum size of variable to go in the SDA
318 -msdata=foo - specifies how such variables are handled
320 -msdata=none - small data area is disabled
322 -msdata=sdata - small data goes in the SDA, special code isn't
323 generated to use it, and special relocs aren't
326 -msdata=use - small data goes in the SDA, special code is generated
327 to use the SDA and special relocs are generated
329 The SDA is not multilib'd, it isn't necessary.
330 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
331 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
332 -msdata=use will successfully link with them (references in header files
333 will cause the compiler to emit code that refers to library objects in
334 .data). ??? There can be a problem if the user passes a -G value greater
335 than the default and a library object in a header file is that size.
336 The default is 8 so this should be rare - if it occurs the user
337 is required to rebuild the libraries or use a smaller value for -G.
340 /* Maximum size of variables that go in .sdata/.sbss.
341 The -msdata=foo switch also controls how small variables are handled. */
342 #ifndef SDATA_DEFAULT_SIZE
343 #define SDATA_DEFAULT_SIZE 8
346 extern int g_switch_value; /* value of the -G xx switch */
347 extern int g_switch_set; /* whether -G xx was passed. */
349 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
351 extern enum m32r_sdata m32r_sdata;
352 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
353 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
354 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
356 /* Default is to disable the SDA
357 [for upward compatibility with previous toolchains]. */
358 #ifndef M32R_SDATA_DEFAULT
359 #define M32R_SDATA_DEFAULT "none"
362 /* Define this macro as a C expression for the initializer of an array of
363 strings to tell the driver program which options are defaults for this
364 target and thus do not need to be handled specially when using
365 `MULTILIB_OPTIONS'. */
366 #ifndef SUBTARGET_MULTILIB_DEFAULTS
367 #define SUBTARGET_MULTILIB_DEFAULTS
370 #ifndef MULTILIB_DEFAULTS
371 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
374 /* Sometimes certain combinations of command options do not make
375 sense on a particular target machine. You can define a macro
376 `OVERRIDE_OPTIONS' to take account of this. This macro, if
377 defined, is executed once just after all the command options have
380 Don't use this macro to turn on various extra optimizations for
381 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
383 #ifndef SUBTARGET_OVERRIDE_OPTIONS
384 #define SUBTARGET_OVERRIDE_OPTIONS
387 #define OVERRIDE_OPTIONS \
390 /* These need to be done at start up. \
391 It's convenient to do them here. */ \
393 SUBTARGET_OVERRIDE_OPTIONS \
397 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
398 #define SUBTARGET_OPTIMIZATION_OPTIONS
401 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
405 flag_regmove = TRUE; \
409 flag_omit_frame_pointer = TRUE; \
410 flag_strength_reduce = FALSE; \
413 SUBTARGET_OPTIMIZATION_OPTIONS \
417 /* Define this macro if debugging can be performed even without a
418 frame pointer. If this macro is defined, GNU CC will turn on the
419 `-fomit-frame-pointer' option whenever `-O' is specified. */
420 #define CAN_DEBUG_WITHOUT_FP
422 /* Target machine storage layout. */
424 /* Define to use software floating point emulator for REAL_ARITHMETIC and
425 decimal <-> binary conversion. */
426 #define REAL_ARITHMETIC
428 /* Define this if most significant bit is lowest numbered
429 in instructions that operate on numbered bit-fields. */
430 #define BITS_BIG_ENDIAN 1
432 /* Define this if most significant byte of a word is the lowest numbered. */
433 #define BYTES_BIG_ENDIAN 1
435 /* Define this if most significant word of a multiword number is the lowest
437 #define WORDS_BIG_ENDIAN 1
439 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
440 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
441 which will be used only when compiling libgcc2.c. Typically the
442 value will be set based on preprocessor defines. */
443 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
445 /* Number of bits in an addressable storage unit. */
446 #define BITS_PER_UNIT 8
448 /* Width in bits of a "word", which is the contents of a machine register.
449 Note that this is not necessarily the width of data type `int';
450 if using 16-bit ints on a 68000, this would still be 32.
451 But on a machine with 16-bit registers, this would be 16. */
452 #define BITS_PER_WORD 32
454 /* Width of a word, in units (bytes). */
455 #define UNITS_PER_WORD 4
457 /* Define this macro if it is advisable to hold scalars in registers
458 in a wider mode than that declared by the program. In such cases,
459 the value is constrained to be within the bounds of the declared
460 type, but kept valid in the wider mode. The signedness of the
461 extension may differ from that of the type. */
462 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
463 if (GET_MODE_CLASS (MODE) == MODE_INT \
464 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
469 /* Define this macro if the promotion described by `PROMOTE_MODE'
470 should also be done for outgoing function arguments. */
471 /*#define PROMOTE_FUNCTION_ARGS*/
473 /* Likewise, if the function return value is promoted.
474 If defined, FUNCTION_VALUE must perform the same promotions done by
476 /*#define PROMOTE_FUNCTION_RETURN*/
478 /* Width in bits of a pointer.
479 See also the macro `Pmode' defined below. */
480 #define POINTER_SIZE 32
482 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
483 #define PARM_BOUNDARY 32
485 /* Boundary (in *bits*) on which stack pointer should be aligned. */
486 #define STACK_BOUNDARY 32
488 /* ALIGN FRAMES on word boundaries */
489 #define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
491 /* Allocation boundary (in *bits*) for the code of a function. */
492 #define FUNCTION_BOUNDARY 32
494 /* Alignment of field after `int : 0' in a structure. */
495 #define EMPTY_FIELD_BOUNDARY 32
497 /* Every structure's size must be a multiple of this. */
498 #define STRUCTURE_SIZE_BOUNDARY 8
500 /* A bitfield declared as `int' forces `int' alignment for the struct. */
501 #define PCC_BITFIELD_TYPE_MATTERS 1
503 /* No data type wants to be aligned rounder than this. */
504 #define BIGGEST_ALIGNMENT 32
506 /* The best alignment to use in cases where we have a choice. */
507 #define FASTEST_ALIGNMENT 32
509 /* Make strings word-aligned so strcpy from constants will be faster. */
510 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
511 ((TREE_CODE (EXP) == STRING_CST \
512 && (ALIGN) < FASTEST_ALIGNMENT) \
513 ? FASTEST_ALIGNMENT : (ALIGN))
515 /* Make arrays of chars word-aligned for the same reasons. */
516 #define DATA_ALIGNMENT(TYPE, ALIGN) \
517 (TREE_CODE (TYPE) == ARRAY_TYPE \
518 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
519 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
521 /* Set this nonzero if move instructions will actually fail to work
522 when given unaligned data. */
523 #define STRICT_ALIGNMENT 1
525 /* Layout of source language data types. */
527 #define SHORT_TYPE_SIZE 16
528 #define INT_TYPE_SIZE 32
529 #define LONG_TYPE_SIZE 32
530 #define LONG_LONG_TYPE_SIZE 64
531 #define FLOAT_TYPE_SIZE 32
532 #define DOUBLE_TYPE_SIZE 64
533 #define LONG_DOUBLE_TYPE_SIZE 64
535 /* Define this as 1 if `char' should by default be signed; else as 0. */
536 #define DEFAULT_SIGNED_CHAR 1
538 #define SIZE_TYPE "long unsigned int"
539 #define PTRDIFF_TYPE "long int"
540 #define WCHAR_TYPE "short unsigned int"
541 #define WCHAR_TYPE_SIZE 16
543 /* Standard register usage. */
545 /* Number of actual hardware registers.
546 The hardware registers are assigned numbers for the compiler
547 from 0 to just below FIRST_PSEUDO_REGISTER.
548 All registers that the compiler knows about must be given numbers,
549 even those that are not normally considered general registers. */
551 #define M32R_NUM_REGISTERS 19
553 #ifndef SUBTARGET_NUM_REGISTERS
554 #define SUBTARGET_NUM_REGISTERS 0
557 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
559 /* 1 for registers that have pervasive standard uses
560 and are not available for the register allocator.
562 0-3 - arguments/results
563 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
565 7 - call used, static chain pointer
567 12 - call saved [reserved for global pointer]
569 14 - subroutine link register
574 19 - accumulator 1 in the m32r/x
575 By default, the extension registers are not available. */
577 #ifndef SUBTARGET_FIXED_REGISTERS
578 #define SUBTARGET_FIXED_REGISTERS
581 #define FIXED_REGISTERS \
583 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 1, \
586 SUBTARGET_FIXED_REGISTERS \
589 /* 1 for registers not available across function calls.
590 These must include the FIXED_REGISTERS and also any
591 registers that can be used without being saved.
592 The latter must include the registers where values are returned
593 and the register where structure-value addresses are passed.
594 Aside from that, you can include as many other registers as you like. */
596 #ifndef SUBTARGET_CALL_USED_REGISTERS
597 #define SUBTARGET_CALL_USED_REGISTERS
600 #define CALL_USED_REGISTERS \
602 1, 1, 1, 1, 1, 1, 1, 1, \
603 0, 0, 0, 0, 0, 0, 1, 1, \
605 SUBTARGET_CALL_USED_REGISTERS \
608 /* Zero or more C statements that may conditionally modify two variables
609 `fixed_regs' and `call_used_regs' (both of type `char []') after they
610 have been initialized from the two preceding macros.
612 This is necessary in case the fixed or call-clobbered registers depend
615 You need not define this macro if it has no work to do. */
617 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
618 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
621 /* If defined, an initializer for a vector of integers, containing the
622 numbers of hard registers in the order in which GNU CC should
623 prefer to use them (from most preferred to least). */
625 #ifndef SUBTARGET_REG_ALLOC_ORDER
626 #define SUBTARGET_REG_ALLOC_ORDER
629 #if 1 /* better for int code */
630 #define REG_ALLOC_ORDER \
632 4, 5, 6, 7, 2, 3, 8, 9, 10, \
633 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
634 SUBTARGET_REG_ALLOC_ORDER \
637 #else /* better for fp code at expense of int code */
638 #define REG_ALLOC_ORDER \
640 0, 1, 2, 3, 4, 5, 6, 7, 8, \
641 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
642 SUBTARGET_REG_ALLOC_ORDER \
646 /* Return number of consecutive hard regs needed starting at reg REGNO
647 to hold something of mode MODE.
648 This is ordinarily the length in words of a value of mode MODE
649 but can be less for certain modes in special long registers. */
650 #define HARD_REGNO_NREGS(REGNO, MODE) \
651 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
653 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
654 extern unsigned int m32r_hard_regno_mode_ok[];
655 extern unsigned int m32r_mode_class[];
656 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
657 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
659 /* A C expression that is nonzero if it is desirable to choose
660 register allocation so as to avoid move instructions between a
661 value of mode MODE1 and a value of mode MODE2.
663 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
664 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
665 MODE2)' must be zero. */
667 /* Tie QI/HI/SI modes together. */
668 #define MODES_TIEABLE_P(MODE1, MODE2) \
669 (GET_MODE_CLASS (MODE1) == MODE_INT \
670 && GET_MODE_CLASS (MODE2) == MODE_INT \
671 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
672 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
674 /* Register classes and constants. */
676 /* Define the classes of registers for register constraints in the
677 machine description. Also define ranges of constants.
679 One of the classes must always be named ALL_REGS and include all hard regs.
680 If there is more than one class, another class must be named NO_REGS
681 and contain no registers.
683 The name GENERAL_REGS must be the name of a class (or an alias for
684 another name such as ALL_REGS). This is the class of registers
685 that is allowed by "g" or "r" in a register constraint.
686 Also, registers outside this class are allocated only when
687 instructions express preferences for them.
689 The classes must be numbered in nondecreasing order; that is,
690 a larger-numbered class must never be contained completely
691 in a smaller-numbered class.
693 For any two classes, it is very desirable that there be another
694 class that represents their union.
696 It is important that any condition codes have class NO_REGS.
697 See `register_operand'. */
701 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
704 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
706 /* Give names of register classes as strings for dump file. */
707 #define REG_CLASS_NAMES \
708 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
710 /* Define which registers fit in which classes.
711 This is an initializer for a vector of HARD_REG_SET
712 of length N_REG_CLASSES. */
714 #ifndef SUBTARGET_REG_CLASS_CARRY
715 #define SUBTARGET_REG_CLASS_CARRY 0
718 #ifndef SUBTARGET_REG_CLASS_ACCUM
719 #define SUBTARGET_REG_CLASS_ACCUM 0
722 #ifndef SUBTARGET_REG_CLASS_GENERAL
723 #define SUBTARGET_REG_CLASS_GENERAL 0
726 #ifndef SUBTARGET_REG_CLASS_ALL
727 #define SUBTARGET_REG_CLASS_ALL 0
730 #define REG_CLASS_CONTENTS \
733 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
734 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
735 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
736 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
739 /* The same information, inverted:
740 Return the class number of the smallest class containing
741 reg number REGNO. This could be a conditional expression
742 or could index an array. */
743 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
744 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
746 /* The class value for index registers, and the one for base regs. */
747 #define INDEX_REG_CLASS GENERAL_REGS
748 #define BASE_REG_CLASS GENERAL_REGS
750 #define REG_CLASS_FROM_LETTER(C) \
751 ((C) == 'c' ? CARRY_REG \
752 : (C) == 'a' ? ACCUM_REGS \
755 /* These assume that REGNO is a hard or pseudo reg number.
756 They give nonzero only if REGNO is a hard reg of the suitable class
757 or a pseudo reg currently allocated to a suitable hard reg.
758 Since they use reg_renumber, they are safe only once reg_renumber
759 has been allocated, which happens in local-alloc.c. */
760 #define REGNO_OK_FOR_BASE_P(REGNO) \
761 ((REGNO) < FIRST_PSEUDO_REGISTER \
762 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
763 : GPR_P (reg_renumber[REGNO]))
764 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
766 /* Given an rtx X being reloaded into a reg required to be
767 in class CLASS, return the class of reg to actually use.
768 In general this is just CLASS; but on some machines
769 in some cases it is preferable to use a more restrictive class. */
770 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
773 /* Return the maximum number of consecutive registers
774 needed to represent mode MODE in a register of class CLASS. */
775 #define CLASS_MAX_NREGS(CLASS, MODE) \
776 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
778 /* The letters I, J, K, L, M, N, O, P in a register constraint string
779 can be used to stand for particular ranges of immediate operands.
780 This macro defines what the ranges are.
781 C is the letter, and VALUE is a constant value.
782 Return 1 if VALUE is in the range specified by C. */
783 /* 'I' is used for 8 bit signed immediates.
784 'J' is used for 16 bit signed immediates.
785 'K' is used for 16 bit unsigned immediates.
786 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
787 'M' is used for 24 bit unsigned immediates.
788 'N' is used for any 32 bit non-symbolic value.
789 'O' is used for 5 bit unsigned immediates (shift count).
790 'P' is used for 16 bit signed immediates for compares
791 (values in the range -32767 to +32768). */
793 /* Return true if a value is inside a range. */
794 #define IN_RANGE_P(VALUE, LOW, HIGH) \
795 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
796 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
798 /* Local to this file. */
799 #define INT8_P(X) ((X) >= -0x80 && (X) <= 0x7f)
800 #define INT16_P(X) ((X) >= -0x8000 && (X) <= 0x7fff)
801 #define CMP_INT16_P(X) ((X) >= -0x7fff && (X) <= 0x8000)
802 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
803 && ((X) >> 16) >= -0x8000 \
804 && ((X) >> 16) <= 0x7fff)
805 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
806 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
807 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
808 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
809 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
811 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
812 ((C) == 'I' ? INT8_P (VALUE) \
813 : (C) == 'J' ? INT16_P (VALUE) \
814 : (C) == 'K' ? UINT16_P (VALUE) \
815 : (C) == 'L' ? UPPER16_P (VALUE) \
816 : (C) == 'M' ? UINT24_P (VALUE) \
817 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
818 : (C) == 'O' ? UINT5_P (VALUE) \
819 : (C) == 'P' ? CMP_INT16_P (VALUE) \
822 /* Similar, but for floating constants, and defining letters G and H.
823 Here VALUE is the CONST_DOUBLE rtx itself.
824 For the m32r, handle a few constants inline.
825 ??? We needn't treat DI and DF modes differently, but for now we do. */
826 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
827 ((C) == 'G' ? easy_di_const (VALUE) \
828 : (C) == 'H' ? easy_df_const (VALUE) \
831 /* A C expression that defines the optional machine-dependent constraint
832 letters that can be used to segregate specific types of operands,
833 usually memory references, for the target machine. It should return 1 if
834 VALUE corresponds to the operand type represented by the constraint letter
835 C. If C is not defined as an extra constraint, the value returned should
836 be 0 regardless of VALUE. */
837 /* Q is for symbolic addresses loadable with ld24.
838 R is for symbolic addresses when ld24 can't be used.
839 S is for stores with pre {inc,dec}rement
840 T is for indirect of a pointer.
841 U is for loads with post increment. */
843 #define EXTRA_CONSTRAINT(VALUE, C) \
844 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
845 || addr24_operand (VALUE, VOIDmode)) \
846 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
847 || addr32_operand (VALUE, VOIDmode)) \
848 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
849 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
851 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
852 && memreg_operand (VALUE, GET_MODE (VALUE))) \
853 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
854 && LOAD_POSTINC_P (GET_MODE (VALUE), \
858 /* Stack layout and stack pointer usage. */
860 /* Define this macro if pushing a word onto the stack moves the stack
861 pointer to a smaller address. */
862 #define STACK_GROWS_DOWNWARD
864 /* Define this if the nominal address of the stack frame
865 is at the high-address end of the local variables;
866 that is, each additional local variable allocated
867 goes at a more negative offset from the frame pointer. */
868 /*#define FRAME_GROWS_DOWNWARD*/
870 /* Offset from frame pointer to start allocating local variables at.
871 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
872 first local allocated. Otherwise, it is the offset to the BEGINNING
873 of the first local allocated. */
874 /* The frame pointer points at the same place as the stack pointer, except if
875 alloca has been called. */
876 #define STARTING_FRAME_OFFSET \
877 M32R_STACK_ALIGN (current_function_outgoing_args_size)
879 /* Offset from the stack pointer register to the first location at which
880 outgoing arguments are placed. */
881 #define STACK_POINTER_OFFSET 0
883 /* Offset of first parameter from the argument pointer register value. */
884 #define FIRST_PARM_OFFSET(FNDECL) 0
886 /* A C expression whose value is RTL representing the address in a
887 stack frame where the pointer to the caller's frame is stored.
888 Assume that FRAMEADDR is an RTL expression for the address of the
891 If you don't define this macro, the default is to return the value
892 of FRAMEADDR--that is, the stack frame address is also the address
893 of the stack word that points to the previous frame. */
894 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
896 /* A C expression whose value is RTL representing the value of the
897 return address for the frame COUNT steps up from the current frame.
898 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
899 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
901 /* The current return address is in r14. */
902 #if 0 /* The default value should work. */
903 #define RETURN_ADDR_RTX(COUNT, FRAME) \
905 ? gen_rtx_REG (Pmode, 14) \
906 : copy_to_reg (gen_rtx_MEM (Pmode, \
907 memory_address (Pmode, \
908 plus_constant ((FRAME), \
912 /* Register to use for pushing function arguments. */
913 #define STACK_POINTER_REGNUM 15
915 /* Base register for access to local variables of the function. */
916 #define FRAME_POINTER_REGNUM 13
918 /* Base register for access to arguments of the function. */
919 #define ARG_POINTER_REGNUM 16
921 /* The register number of the return address pointer register, which
922 is used to access the current function's return address from the
923 stack. On some machines, the return address is not at a fixed
924 offset from the frame pointer or stack pointer or argument
925 pointer. This register can be defined to point to the return
926 address on the stack, and then be converted by `ELIMINABLE_REGS'
927 into either the frame pointer or stack pointer.
929 Do not define this macro unless there is no other way to get the
930 return address from the stack. */
932 /* #define RETURN_ADDRESS_POINTER_REGNUM */
934 /* Register in which static-chain is passed to a function. This must
935 not be a register used by the prologue. */
936 #define STATIC_CHAIN_REGNUM 7
938 /* These aren't official macros. */
939 #define PROLOGUE_TMP_REGNUM 4
940 #define RETURN_ADDR_REGNUM 14
941 /* #define GP_REGNUM 12 */
942 #define CARRY_REGNUM 17
943 #define ACCUM_REGNUM 18
944 #define M32R_MAX_INT_REGS 16
946 #ifndef SUBTARGET_GPR_P
947 #define SUBTARGET_GPR_P(REGNO) 0
950 #ifndef SUBTARGET_ACCUM_P
951 #define SUBTARGET_ACCUM_P(REGNO) 0
954 #ifndef SUBTARGET_CARRY_P
955 #define SUBTARGET_CARRY_P(REGNO) 0
958 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
959 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
960 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
962 /* Eliminating the frame and arg pointers. */
964 /* A C expression which is nonzero if a function must have and use a
965 frame pointer. This expression is evaluated in the reload pass.
966 If its value is nonzero the function will have a frame pointer. */
967 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
970 /* C statement to store the difference between the frame pointer
971 and the stack pointer values immediately after the function prologue.
972 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
973 need not be defined. */
974 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
975 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
978 /* If defined, this macro specifies a table of register pairs used to
979 eliminate unneeded registers that point into the stack frame. If
980 it is not defined, the only elimination attempted by the compiler
981 is to replace references to the frame pointer with references to
984 Note that the elimination of the argument pointer with the stack
985 pointer is specified first since that is the preferred elimination. */
987 #define ELIMINABLE_REGS \
988 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
989 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
990 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
992 /* A C expression that returns non-zero if the compiler is allowed to
993 try to replace register number FROM-REG with register number
994 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
995 defined, and will usually be the constant 1, since most of the
996 cases preventing register elimination are things that the compiler
997 already knows about. */
999 #define CAN_ELIMINATE(FROM, TO) \
1000 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1001 ? ! frame_pointer_needed \
1004 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1005 specifies the initial difference between the specified pair of
1006 registers. This macro must be defined if `ELIMINABLE_REGS' is
1009 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1011 int size = m32r_compute_frame_size (get_frame_size ()); \
1013 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1015 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1016 (OFFSET) = size - current_function_pretend_args_size; \
1017 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1018 (OFFSET) = size - current_function_pretend_args_size; \
1023 /* Function argument passing. */
1025 /* When a prototype says `char' or `short', really pass an `int'. */
1026 #define PROMOTE_PROTOTYPES 1
1028 /* If defined, the maximum amount of space required for outgoing
1029 arguments will be computed and placed into the variable
1030 `current_function_outgoing_args_size'. No space will be pushed
1031 onto the stack for each call; instead, the function prologue should
1032 increase the stack frame size by this amount. */
1033 #define ACCUMULATE_OUTGOING_ARGS 1
1035 /* Define this macro if functions should assume that stack space has
1036 been allocated for arguments even when their values are passed in
1039 The value of this macro is the size, in bytes, of the area
1040 reserved for arguments passed in registers for the function
1041 represented by FNDECL.
1043 This space can be allocated by the caller, or be a part of the
1044 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1047 #define REG_PARM_STACK_SPACE(FNDECL) \
1048 (M32R_MAX_PARM_REGS * UNITS_PER_WORD)
1051 /* Value is the number of bytes of arguments automatically
1052 popped when returning from a subroutine call.
1053 FUNDECL is the declaration node of the function (as a tree),
1054 FUNTYPE is the data type of the function (as a tree),
1055 or for a library call it is an identifier node for the subroutine name.
1056 SIZE is the number of bytes of arguments passed on the stack. */
1057 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1059 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1060 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1062 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1063 || TREE_ADDRESSABLE (TYPE)))
1065 /* Define a data type for recording info about an argument list
1066 during the scan of that argument list. This data type should
1067 hold all necessary information about the function itself
1068 and about the args processed so far, enough to enable macros
1069 such as FUNCTION_ARG to determine where the next arg should go. */
1070 #define CUMULATIVE_ARGS int
1072 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1073 for a call to a function whose data type is FNTYPE.
1074 For a library call, FNTYPE is 0. */
1075 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1078 /* The number of registers used for parameter passing. Local to this file. */
1079 #define M32R_MAX_PARM_REGS 4
1081 /* 1 if N is a possible register number for function argument passing. */
1082 #define FUNCTION_ARG_REGNO_P(N) \
1083 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1085 /* The ROUND_ADVANCE* macros are local to this file. */
1086 /* Round SIZE up to a word boundary. */
1087 #define ROUND_ADVANCE(SIZE) \
1088 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1090 /* Round arg MODE/TYPE up to the next word boundary. */
1091 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1092 ((MODE) == BLKmode \
1093 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1094 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
1096 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1097 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1099 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1100 a reg. This includes arguments that have to be passed by reference as the
1101 pointer to them is passed in a reg if one is available (and that is what
1103 This macro is only used in this file. */
1104 #define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
1105 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1107 /* Determine where to put an argument to a function.
1108 Value is zero to push the argument on the stack,
1109 or a hard register in which to store the argument.
1111 MODE is the argument's machine mode.
1112 TYPE is the data type of the argument (as a tree).
1113 This is null for libcalls where that information may
1115 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1116 the preceding args and about the function being called.
1117 NAMED is nonzero if this argument is a named parameter
1118 (otherwise it is an extra parameter matching an ellipsis). */
1119 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1120 and the rest are pushed. */
1121 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1122 (PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)) \
1123 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1126 /* ??? Quick hack to try to get varargs working the normal way. */
1127 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1128 (((! current_function_varargs || (NAMED)) \
1129 && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))) \
1130 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1133 /* A C expression for the number of words, at the beginning of an
1134 argument, must be put in registers. The value must be zero for
1135 arguments that are passed entirely in registers or that are entirely
1136 pushed on the stack.
1138 On some machines, certain arguments must be passed partially in
1139 registers and partially in memory. On these machines, typically the
1140 first @var{n} words of arguments are passed in registers, and the rest
1141 on the stack. If a multi-word argument (a @code{double} or a
1142 structure) crosses that boundary, its first few words must be passed
1143 in registers and the rest must be pushed. This macro tells the
1144 compiler when this occurs, and how many of the words should go in
1146 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1147 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1149 /* A C expression that indicates when an argument must be passed by
1150 reference. If nonzero for an argument, a copy of that argument is
1151 made in memory and a pointer to the argument is passed instead of
1152 the argument itself. The pointer is passed in whatever way is
1153 appropriate for passing a pointer to that type. */
1154 /* All arguments greater than 8 bytes are passed this way. */
1155 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1156 ((TYPE) && int_size_in_bytes (TYPE) > 8)
1158 /* Update the data in CUM to advance over an argument
1159 of mode MODE and data type TYPE.
1160 (TYPE is null for libcalls where that information may not be available.) */
1161 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1162 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1163 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1165 /* If defined, a C expression that gives the alignment boundary, in bits,
1166 of an argument with the specified mode and type. If it is not defined,
1167 PARM_BOUNDARY is used for all arguments. */
1169 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1170 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1171 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1173 : 2 * PARM_BOUNDARY)
1176 /* This macro offers an alternative
1177 to using `__builtin_saveregs' and defining the macro
1178 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1179 arguments into the stack so that all the arguments appear to have
1180 been passed consecutively on the stack. Once this is done, you
1181 can use the standard implementation of varargs that works for
1182 machines that pass all their arguments on the stack.
1184 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
1185 containing the values that obtain after processing of the named
1186 arguments. The arguments MODE and TYPE describe the last named
1187 argument--its machine mode and its data type as a tree node.
1189 The macro implementation should do two things: first, push onto the
1190 stack all the argument registers *not* used for the named
1191 arguments, and second, store the size of the data thus pushed into
1192 the `int'-valued variable whose name is supplied as the argument
1193 PRETEND_SIZE. The value that you store here will serve as
1194 additional offset for setting up the stack frame.
1196 If the argument NO_RTL is nonzero, it means that the
1197 arguments of the function are being analyzed for the second time.
1198 This happens for an inline function, which is not actually
1199 compiled until the end of the source file. The macro
1200 `SETUP_INCOMING_VARARGS' should not generate any instructions in
1203 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1204 m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1206 /* Implement `va_arg'. */
1207 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1208 m32r_va_arg (valist, type)
1210 /* Function results. */
1212 /* Define how to find the value returned by a function.
1213 VALTYPE is the data type of the value (as a tree).
1214 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1215 otherwise, FUNC is 0. */
1216 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1218 /* Define how to find the value returned by a library function
1219 assuming the value has mode MODE. */
1220 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1222 /* 1 if N is a possible register number for a function value
1223 as seen by the caller. */
1224 /* ??? What about r1 in DI/DF values. */
1225 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1227 /* A C expression which can inhibit the returning of certain function
1228 values in registers, based on the type of value. A nonzero value says
1229 to return the function value in memory, just as large structures are
1230 always returned. Here TYPE will be a C expression of type `tree',
1231 representing the data type of the value. */
1232 #define RETURN_IN_MEMORY(TYPE) \
1233 (int_size_in_bytes (TYPE) > 8)
1235 /* Tell GCC to use RETURN_IN_MEMORY. */
1236 #define DEFAULT_PCC_STRUCT_RETURN 0
1238 /* Register in which address to store a structure value
1239 is passed to a function, or 0 to use `invisible' first argument. */
1240 #define STRUCT_VALUE 0
1242 /* Function entry and exit. */
1244 /* Initialize data used by insn expanders. This is called from
1245 init_emit, once for each function, before code is generated. */
1246 #define INIT_EXPANDERS m32r_init_expanders ()
1248 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1249 the stack pointer does not matter. The value is tested only in
1250 functions that have frame pointers.
1251 No definition is equivalent to always zero. */
1252 #define EXIT_IGNORE_STACK 1
1254 /* Output assembler code to FILE to increment profiler label # LABELNO
1255 for profiling a function entry. */
1256 #define FUNCTION_PROFILER(FILE, LABELNO) abort ()
1260 /* On the M32R, the trampoline is
1267 ??? Need addr32 support.
1270 /* Length in bytes of the trampoline for entering a nested function. */
1271 #define TRAMPOLINE_SIZE 12
1273 /* Emit RTL insns to initialize the variable parts of a trampoline.
1274 FNADDR is an RTX for the address of the function's pure code.
1275 CXT is an RTX for the static chain value for the function. */
1276 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1278 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1279 plus_constant ((CXT), 0xe7000000)); \
1280 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1281 plus_constant ((FNADDR), 0xe6000000)); \
1282 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1283 GEN_INT (0x1fc67000)); \
1284 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)))); \
1287 /* Library calls. */
1289 /* Generate calls to memcpy, memcmp and memset. */
1290 #define TARGET_MEM_FUNCTIONS
1292 /* Addressing modes, and classification of registers for them. */
1294 /* Maximum number of registers that can appear in a valid memory address. */
1295 #define MAX_REGS_PER_ADDRESS 1
1297 /* We have post-inc load and pre-dec,pre-inc store,
1298 but only for 4 byte vals. */
1299 #define HAVE_PRE_DECREMENT 1
1300 #define HAVE_PRE_INCREMENT 1
1301 #define HAVE_POST_INCREMENT 1
1303 /* Recognize any constant value that is a valid address. */
1304 #define CONSTANT_ADDRESS_P(X) \
1305 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1306 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
1308 /* Nonzero if the constant value X is a legitimate general operand.
1309 We don't allow (plus symbol large-constant) as the relocations can't
1310 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1311 We allow all CONST_DOUBLE's as the md file patterns will force the
1312 constant to memory if they can't handle them. */
1314 #define LEGITIMATE_CONSTANT_P(X) \
1315 (! (GET_CODE (X) == CONST \
1316 && GET_CODE (XEXP (X, 0)) == PLUS \
1317 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1318 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1319 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1321 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1322 and check its validity for a certain class.
1323 We have two alternate definitions for each of them.
1324 The usual definition accepts all pseudo regs; the other rejects
1325 them unless they have been allocated suitable hard regs.
1326 The symbol REG_OK_STRICT causes the latter definition to be used.
1328 Most source files want to accept pseudo regs in the hope that
1329 they will get allocated to the class that the insn wants them to be in.
1330 Source files for reload pass need to be strict.
1331 After reload, it makes no difference, since pseudo regs have
1332 been eliminated by then. */
1334 #ifdef REG_OK_STRICT
1336 /* Nonzero if X is a hard reg that can be used as a base reg. */
1337 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1338 /* Nonzero if X is a hard reg that can be used as an index. */
1339 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1343 /* Nonzero if X is a hard reg that can be used as a base reg
1344 or if it is a pseudo reg. */
1345 #define REG_OK_FOR_BASE_P(X) \
1346 (GPR_P (REGNO (X)) \
1347 || (REGNO (X)) == ARG_POINTER_REGNUM \
1348 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1349 /* Nonzero if X is a hard reg that can be used as an index
1350 or if it is a pseudo reg. */
1351 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1355 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1356 that is a valid memory address for an instruction.
1357 The MODE argument is the machine mode for the MEM expression
1358 that wants to use this address. */
1360 /* Local to this file. */
1361 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1363 /* Local to this file. */
1364 #define RTX_OK_FOR_OFFSET_P(X) \
1365 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1367 /* Local to this file. */
1368 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1369 (GET_CODE (X) == PLUS \
1370 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1371 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1373 /* Local to this file. */
1374 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1375 since more than one instruction will be required. */
1376 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1377 (GET_CODE (X) == LO_SUM \
1378 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
1379 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1380 && CONSTANT_P (XEXP (X, 1)))
1382 /* Local to this file. */
1383 /* Is this a load and increment operation. */
1384 #define LOAD_POSTINC_P(MODE, X) \
1385 (((MODE) == SImode || (MODE) == SFmode) \
1386 && GET_CODE (X) == POST_INC \
1387 && GET_CODE (XEXP (X, 0)) == REG \
1388 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1390 /* Local to this file. */
1391 /* Is this a increment/decrement and store operation. */
1392 #define STORE_PREINC_PREDEC_P(MODE, X) \
1393 (((MODE) == SImode || (MODE) == SFmode) \
1394 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1395 && GET_CODE (XEXP (X, 0)) == REG \
1396 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1398 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1399 { if (RTX_OK_FOR_BASE_P (X)) \
1401 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1403 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1405 if (LOAD_POSTINC_P ((MODE), (X))) \
1407 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1411 /* Try machine-dependent ways of modifying an illegitimate address
1412 to be legitimate. If we find one, return the new, valid address.
1413 This macro is used in only one place: `memory_address' in explow.c.
1415 OLDX is the address as it was before break_out_memory_refs was called.
1416 In some cases it is useful to look at this to decide what needs to be done.
1418 MODE and WIN are passed so that this macro can use
1419 GO_IF_LEGITIMATE_ADDRESS.
1421 It is always safe for this macro to do nothing. It exists to recognize
1422 opportunities to optimize the output.
1424 ??? Is there anything useful we can do here for the M32R? */
1426 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1428 /* Go to LABEL if ADDR (a legitimate address expression)
1429 has an effect that depends on the machine mode it is used for. */
1430 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1432 if (GET_CODE (ADDR) == PRE_DEC \
1433 || GET_CODE (ADDR) == PRE_INC \
1434 || GET_CODE (ADDR) == POST_INC \
1435 || GET_CODE (ADDR) == LO_SUM) \
1439 /* Condition code usage. */
1441 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1442 return the mode to be used for the comparison. */
1443 #define SELECT_CC_MODE(OP, X, Y) \
1444 ((enum machine_mode)m32r_select_cc_mode ((int)OP, X, Y))
1446 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1447 floating point inequality comparison. */
1448 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1452 /* ??? I'm quite sure I don't understand enough of the subtleties involved
1453 in choosing the right numbers to use here, but there doesn't seem to be
1454 enough documentation on this. What I've done is define an insn to cost
1455 4 "units" and work from there. COSTS_N_INSNS (N) is defined as (N) * 4 - 2
1456 so that seems reasonable. Some values are supposed to be defined relative
1457 to each other and thus aren't necessarily related to COSTS_N_INSNS. */
1459 /* Compute the cost of computing a constant rtl expression RTX
1460 whose rtx-code is CODE. The body of this macro is a portion
1461 of a switch statement. If the code is computed here,
1462 return it with a return statement. Otherwise, break from the switch. */
1463 /* Small integers are as cheap as registers. 4 byte values can be fetched
1464 as immediate constants - let's give that the cost of an extra insn. */
1465 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1467 if (INT16_P (INTVAL (X))) \
1469 /* fall through */ \
1474 case CONST_DOUBLE : \
1477 split_double (X, &high, &low); \
1478 return 4 * (!INT16_P (INTVAL (high)) \
1479 + !INT16_P (INTVAL (low))); \
1482 /* Compute the cost of an address. */
1483 #define ADDRESS_COST(ADDR) m32r_address_cost (ADDR)
1485 /* Compute extra cost of moving data between one register class
1487 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1489 /* Compute the cost of moving data between registers and memory. */
1490 /* Memory is 3 times as expensive as registers.
1491 ??? Is that the right way to look at it? */
1492 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1493 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1495 /* The cost of a branch insn. */
1496 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1497 while (a < N && a). Branches aren't that expensive on the M32R so
1498 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1499 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1501 /* Provide the costs of a rtl expression. This is in the body of a
1502 switch on CODE. The purpose for the cost of MULT is to encourage
1503 `synth_mult' to find a synthetic multiply when reasonable.
1505 If we need more than 12 insns to do a multiply, then go out-of-line,
1506 since the call overhead will be < 10% of the cost of the multiply. */
1507 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1509 return COSTS_N_INSNS (3); \
1514 return COSTS_N_INSNS (10);
1516 /* Nonzero if access to memory by bytes is slow and undesirable.
1517 For RISC chips, it means that access to memory by bytes is no
1518 better than access by words when possible, so grab a whole word
1519 and maybe make use of that. */
1520 #define SLOW_BYTE_ACCESS 1
1522 /* Define this macro if it is as good or better to call a constant
1523 function address than to call an address kept in a register. */
1524 #define NO_FUNCTION_CSE
1526 /* Define this macro if it is as good or better for a function to call
1527 itself with an explicit address than to call an address kept in a
1529 #define NO_RECURSIVE_FUNCTION_CSE
1531 /* When the `length' insn attribute is used, this macro specifies the
1532 value to be assigned to the address of the first insn in a
1533 function. If not specified, 0 is used. */
1534 #define FIRST_INSN_ADDRESS m32r_first_insn_address ()
1537 /* Section selection. */
1539 #define TEXT_SECTION_ASM_OP "\t.section .text"
1540 #define DATA_SECTION_ASM_OP "\t.section .data"
1541 #define RODATA_SECTION_ASM_OP "\t.section .rodata"
1542 #define BSS_SECTION_ASM_OP "\t.section .bss"
1543 #define SDATA_SECTION_ASM_OP "\t.section .sdata"
1544 #define SBSS_SECTION_ASM_OP "\t.section .sbss"
1545 /* This one is for svr4.h. */
1546 #undef CONST_SECTION_ASM_OP
1547 #define CONST_SECTION_ASM_OP "\t.section .rodata"
1549 /* A list of names for sections other than the standard two, which are
1550 `in_text' and `in_data'. You need not define this macro
1551 on a system with no other sections (that GCC needs to use). */
1552 #undef EXTRA_SECTIONS
1553 #define EXTRA_SECTIONS in_sdata, in_sbss, in_const
1555 /* One or more functions to be defined in "varasm.c". These
1556 functions should do jobs analogous to those of `text_section' and
1557 `data_section', for your additional sections. Do not define this
1558 macro if you do not define `EXTRA_SECTIONS'. */
1559 #undef EXTRA_SECTION_FUNCTIONS
1560 #define EXTRA_SECTION_FUNCTIONS \
1561 CONST_SECTION_FUNCTION \
1562 SDATA_SECTION_FUNCTION \
1563 SBSS_SECTION_FUNCTION
1565 #define SDATA_SECTION_FUNCTION \
1569 if (in_section != in_sdata) \
1571 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
1572 in_section = in_sdata; \
1576 #define SBSS_SECTION_FUNCTION \
1580 if (in_section != in_sbss) \
1582 fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP); \
1583 in_section = in_sbss; \
1587 /* A C statement or statements to switch to the appropriate section for
1588 output of EXP. You can assume that EXP is either a `VAR_DECL' node
1589 or a constant of some sort. RELOC indicates whether the initial value
1590 of EXP requires link-time relocations. */
1591 #undef SELECT_SECTION
1592 #define SELECT_SECTION(EXP, RELOC, ALIGN) \
1593 m32r_select_section ((EXP), (RELOC))
1595 /* A C statement or statements to switch to the appropriate section for
1596 output of RTX in mode MODE. You can assume that RTX
1597 is some kind of constant in RTL. The argument MODE is redundant
1598 except in the case of a `const_int' rtx. Select the section by
1599 calling `text_section' or one of the alternatives for other
1602 Do not define this macro if you put all constants in the read-only
1605 #undef SELECT_RTX_SECTION
1607 /* Define this macro if jump tables (for tablejump insns) should be
1608 output in the text section, along with the assembler instructions.
1609 Otherwise, the readonly data section is used.
1610 This macro is irrelevant if there is no separate readonly data section. */
1611 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
1613 /* Define this macro if references to a symbol must be treated
1614 differently depending on something about the variable or
1615 function named by the symbol (such as what section it is in).
1617 The macro definition, if any, is executed immediately after the
1618 rtl for DECL or other node is created.
1619 The value of the rtl will be a `mem' whose address is a
1622 The usual thing for this macro to do is to store a flag in the
1623 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1624 name string in the `symbol_ref' (if one bit is not enough
1627 #define SDATA_FLAG_CHAR '@'
1628 /* Small objects are recorded with no prefix for space efficiency since
1629 they'll be the most common. This isn't the case if the user passes
1630 -mmodel={medium|large} and one could choose to not mark symbols that
1631 are the default, but that complicates things. */
1632 /*#define SMALL_FLAG_CHAR '#'*/
1633 #define MEDIUM_FLAG_CHAR '%'
1634 #define LARGE_FLAG_CHAR '&'
1636 #define SDATA_NAME_P(NAME) (*(NAME) == SDATA_FLAG_CHAR)
1637 /*#define SMALL_NAME_P(NAME) (*(NAME) == SMALL_FLAG_CHAR)*/
1638 #define SMALL_NAME_P(NAME) (! ENCODED_NAME_P (NAME) && ! LIT_NAME_P (NAME))
1639 #define MEDIUM_NAME_P(NAME) (*(NAME) == MEDIUM_FLAG_CHAR)
1640 #define LARGE_NAME_P(NAME) (*(NAME) == LARGE_FLAG_CHAR)
1641 /* For string literals, etc. */
1642 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
1644 #define ENCODED_NAME_P(SYMBOL_NAME) \
1645 (SDATA_NAME_P (SYMBOL_NAME) \
1646 /*|| SMALL_NAME_P (SYMBOL_NAME)*/ \
1647 || MEDIUM_NAME_P (SYMBOL_NAME) \
1648 || LARGE_NAME_P (SYMBOL_NAME))
1650 #define ENCODE_SECTION_INFO(DECL) m32r_encode_section_info (DECL)
1652 /* Decode SYM_NAME and store the real name part in VAR, sans
1653 the characters that encode section info. Define this macro if
1654 ENCODE_SECTION_INFO alters the symbol's name string. */
1655 /* Note that we have to handle symbols like "%*start". */
1656 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1658 (VAR) = (SYMBOL_NAME) + ENCODED_NAME_P (SYMBOL_NAME); \
1659 (VAR) += *(VAR) == '*'; \
1664 /* The register number of the register used to address a table of static
1665 data addresses in memory. In some cases this register is defined by a
1666 processor's ``application binary interface'' (ABI). When this macro
1667 is defined, RTL is generated for this register once, as with the stack
1668 pointer and frame pointer registers. If this macro is not defined, it
1669 is up to the machine-dependent files to allocate such a register (if
1671 /*#define PIC_OFFSET_TABLE_REGNUM 12*/
1673 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1674 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1676 /* This register is call-saved on the M32R. */
1677 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1679 /* By generating position-independent code, when two different programs (A
1680 and B) share a common library (libC.a), the text of the library can be
1681 shared whether or not the library is linked at the same address for both
1682 programs. In some of these environments, position-independent code
1683 requires not only the use of different addressing modes, but also
1684 special code to enable the use of these addressing modes.
1686 The FINALIZE_PIC macro serves as a hook to emit these special
1687 codes once the function is being compiled into assembly code, but not
1688 before. (It is not done before, because in the case of compiling an
1689 inline function, it would lead to multiple PIC prologues being
1690 included in functions which used inline functions and were compiled to
1691 assembly language.) */
1693 /*#define FINALIZE_PIC m32r_finalize_pic ()*/
1695 /* A C expression that is nonzero if X is a legitimate immediate
1696 operand on the target machine when generating position independent code.
1697 You can assume that X satisfies CONSTANT_P, so you need not
1698 check this. You can also assume `flag_pic' is true, so you need not
1699 check it either. You need not define this macro if all constants
1700 (including SYMBOL_REF) can be immediate operands when generating
1701 position independent code. */
1702 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
1704 /* Control the assembler format that we output. */
1706 /* Output at beginning of assembler file. */
1707 #define ASM_FILE_START(FILE) m32r_asm_file_start (FILE)
1709 /* A C string constant describing how to begin a comment in the target
1710 assembler language. The compiler assumes that the comment will
1711 end at the end of the line. */
1712 #define ASM_COMMENT_START ";"
1714 /* Output to assembler file text saying following lines
1715 may contain character constants, extra white space, comments, etc. */
1716 #define ASM_APP_ON ""
1718 /* Output to assembler file text saying following lines
1719 no longer contain unusual constructs. */
1720 #define ASM_APP_OFF ""
1722 /* This is how to output the definition of a user-level label named NAME,
1723 such as the label on a static function or variable NAME. */
1724 /* On the M32R we need to ensure the next instruction starts on a 32 bit
1725 boundary [the previous insn must either be 2 16 bit insns or 1 32 bit]. */
1726 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1729 assemble_name (FILE, NAME); \
1730 fputs (":\n", FILE); \
1734 /* This is how to output a command to make the user-level label named NAME
1735 defined for reference from other files. */
1736 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
1739 fputs ("\t.global\t", FILE); \
1740 assemble_name (FILE, NAME); \
1741 fputs ("\n", FILE); \
1745 /* This is how to output a reference to a user-level label named NAME.
1746 `assemble_name' uses this. */
1747 #undef ASM_OUTPUT_LABELREF
1748 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1751 const char * real_name; \
1752 STRIP_NAME_ENCODING (real_name, (NAME)); \
1753 asm_fprintf (FILE, "%U%s", real_name); \
1757 /* If -Os, don't force line number labels to begin at the beginning of
1758 the word; we still want the assembler to try to put things in parallel,
1759 should that be possible.
1760 For m32r/d, instructions are never in parallel (other than with a nop)
1761 and the simulator and stub both handle a breakpoint in the middle of
1762 a word so don't ever force line number labels to begin at the beginning
1765 #undef ASM_OUTPUT_SOURCE_LINE
1766 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1769 static int sym_lineno = 1; \
1770 fprintf (file, ".stabn 68,0,%d,.LM%d-", \
1771 line, sym_lineno); \
1773 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1774 fprintf (file, (optimize_size || TARGET_M32R) \
1775 ? "\n\t.debugsym .LM%d\n" \
1782 /* Store in OUTPUT a string (made with alloca) containing
1783 an assembler-name for a local static variable named NAME.
1784 LABELNO is an integer which is different for each call. */
1785 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1788 (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);\
1789 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)); \
1793 /* How to refer to registers in assembler output.
1794 This sequence is indexed by compiler's hard-register-number (see above). */
1795 #ifndef SUBTARGET_REGISTER_NAMES
1796 #define SUBTARGET_REGISTER_NAMES
1799 #define REGISTER_NAMES \
1801 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1802 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1803 "ap", "cbit", "a0" \
1804 SUBTARGET_REGISTER_NAMES \
1807 /* If defined, a C initializer for an array of structures containing
1808 a name and a register number. This macro defines additional names
1809 for hard registers, thus allowing the `asm' option in declarations
1810 to refer to registers using alternate names. */
1811 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1812 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1815 #define ADDITIONAL_REGISTER_NAMES \
1817 /*{ "gp", GP_REGNUM },*/ \
1818 { "r13", FRAME_POINTER_REGNUM }, \
1819 { "r14", RETURN_ADDR_REGNUM }, \
1820 { "r15", STACK_POINTER_REGNUM }, \
1821 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1824 /* A C expression which evaluates to true if CODE is a valid
1825 punctuation character for use in the `PRINT_OPERAND' macro. */
1826 extern char m32r_punct_chars[];
1827 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1828 m32r_punct_chars[(unsigned char) (CHAR)]
1830 /* Print operand X (an rtx) in assembler syntax to file FILE.
1831 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1832 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1833 #define PRINT_OPERAND(FILE, X, CODE) \
1834 m32r_print_operand (FILE, X, CODE)
1836 /* A C compound statement to output to stdio stream STREAM the
1837 assembler syntax for an instruction operand that is a memory
1838 reference whose address is ADDR. ADDR is an RTL expression.
1840 On some machines, the syntax for a symbolic address depends on
1841 the section that the address refers to. On these machines,
1842 define the macro `ENCODE_SECTION_INFO' to store the information
1843 into the `symbol_ref', and then check for it here. */
1844 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1845 m32r_print_operand_address (FILE, ADDR)
1847 /* If defined, C string expressions to be used for the `%R', `%L',
1848 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1849 are useful when a single `md' file must support multiple assembler
1850 formats. In that case, the various `tm.h' files can define these
1851 macros differently. */
1852 #define REGISTER_PREFIX ""
1853 #define LOCAL_LABEL_PREFIX ".L"
1854 #define USER_LABEL_PREFIX ""
1855 #define IMMEDIATE_PREFIX "#"
1857 /* This is how to output an element of a case-vector that is absolute. */
1858 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1862 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1863 fprintf (FILE, "\t.word\t"); \
1864 assemble_name (FILE, label); \
1865 fprintf (FILE, "\n"); \
1869 /* This is how to output an element of a case-vector that is relative. */
1870 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1874 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1875 fprintf (FILE, "\t.word\t"); \
1876 assemble_name (FILE, label); \
1877 fprintf (FILE, "-"); \
1878 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1879 assemble_name (FILE, label); \
1880 fprintf (FILE, ")\n"); \
1884 /* The desired alignment for the location counter at the beginning
1886 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1887 if -malign-loops. */
1888 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1890 /* Define this to be the maximum number of insns to move around when moving
1891 a loop test from the top of a loop to the bottom
1892 and seeing whether to duplicate it. The default is thirty.
1894 Loop unrolling currently doesn't like this optimization, so
1895 disable doing if we are unrolling loops and saving space. */
1896 #define LOOP_TEST_THRESHOLD (optimize_size \
1897 && !flag_unroll_loops \
1898 && !flag_unroll_all_loops ? 2 : 30)
1900 /* This is how to output an assembler line
1901 that says to advance the location counter
1902 to a multiple of 2**LOG bytes. */
1903 /* .balign is used to avoid confusion. */
1904 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1908 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1912 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1913 separate, explicit argument. If you define this macro, it is used in
1914 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1915 handling the required alignment of the variable. The alignment is
1916 specified as the number of bits. */
1918 #define SCOMMON_ASM_OP "\t.scomm\t"
1920 #undef ASM_OUTPUT_ALIGNED_COMMON
1921 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1924 if (! TARGET_SDATA_NONE \
1925 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1926 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1928 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1929 assemble_name ((FILE), (NAME)); \
1930 fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1934 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1935 separate, explicit argument. If you define this macro, it is used in
1936 place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1937 handling the required alignment of the variable. The alignment is
1938 specified as the number of bits.
1940 For the M32R we need sbss support. */
1942 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1945 ASM_GLOBALIZE_LABEL (FILE, NAME); \
1946 ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \
1950 /* Debugging information. */
1952 /* Generate DBX and DWARF debugging information. */
1953 #undef DBX_DEBUGGING_INFO
1954 #undef DWARF_DEBUGGING_INFO
1955 #undef DWARF2_DEBUGGING_INFO
1957 #define DBX_DEBUGGING_INFO
1958 #define DWARF_DEBUGGING_INFO
1959 #define DWARF2_DEBUGGING_INFO
1961 /* Prefer STABS (for now). */
1962 #undef PREFERRED_DEBUGGING_TYPE
1963 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
1965 /* Turn off splitting of long stabs. */
1966 #define DBX_CONTIN_LENGTH 0
1968 /* Miscellaneous. */
1970 /* Specify the machine mode that this machine uses
1971 for the index in the tablejump instruction. */
1972 #define CASE_VECTOR_MODE Pmode
1974 /* Define as C expression which evaluates to nonzero if the tablejump
1975 instruction expects the table to contain offsets from the address of the
1977 Do not define this if the table should contain absolute addresses. */
1978 /* It's not clear what PIC will look like or whether we want to use -fpic
1979 for the embedded form currently being talked about. For now require -fpic
1980 to get pc relative switch tables. */
1981 /*#define CASE_VECTOR_PC_RELATIVE 1 */
1983 /* Define if operations between registers always perform the operation
1984 on the full register even if a narrower mode is specified. */
1985 #define WORD_REGISTER_OPERATIONS
1987 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1988 will either zero-extend or sign-extend. The value of this macro should
1989 be the code that says which one of the two operations is implicitly
1990 done, NIL if none. */
1991 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1993 /* Specify the tree operation to be used to convert reals to integers. */
1994 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1996 /* This is the kind of divide that is easiest to do in the general case. */
1997 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1999 /* Max number of bytes we can move from memory to memory
2000 in one reasonably fast instruction. */
2003 /* Define this to be nonzero if shift instructions ignore all but the low-order
2005 #define SHIFT_COUNT_TRUNCATED 1
2007 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2008 is done just by pretending it is already truncated. */
2009 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2011 /* We assume that the store-condition-codes instructions store 0 for false
2012 and some other value for true. This is the value stored for true. */
2013 #define STORE_FLAG_VALUE 1
2015 /* Specify the machine mode that pointers have.
2016 After generation of rtl, the compiler makes no further distinction
2017 between pointers and any other objects of this machine mode. */
2018 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
2019 it's own problems (you have to add extendpsisi2 and truncsipsi2).
2021 #define Pmode SImode
2023 /* A function address in a call instruction. */
2024 #define FUNCTION_MODE SImode
2026 /* Define the information needed to generate branch and scc insns. This is
2027 stored from the compare operation. Note that we can't use "rtx" here
2028 since it hasn't been defined! */
2029 extern struct rtx_def * m32r_compare_op0;
2030 extern struct rtx_def * m32r_compare_op1;
2032 /* M32R function types. */
2033 enum m32r_function_type
2035 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
2038 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
2040 /* Define this if you have defined special-purpose predicates in the
2041 file `MACHINE.c'. This macro is called within an initializer of an
2042 array of structures. The first field in the structure is the name
2043 of a predicate and the second field is an array of rtl codes. For
2044 each predicate, list all rtl codes that can be in expressions
2045 matched by the predicate. The list should have a trailing comma. */
2047 #define PREDICATE_CODES \
2048 { "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \
2049 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
2050 { "carry_compare_operand", { EQ, NE }}, \
2051 { "eqne_comparison_operator", { EQ, NE }}, \
2052 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \
2053 { "move_dest_operand", { REG, SUBREG, MEM }}, \
2054 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2055 CONST_DOUBLE, LABEL_REF, CONST, \
2057 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2059 { "two_insn_const_operand", { CONST_INT }}, \
2060 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2061 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2062 { "int8_operand", { CONST_INT }}, \
2063 { "uint16_operand", { CONST_INT }}, \
2064 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \
2065 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \
2066 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \
2067 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \
2068 { "cmp_int16_operand", { CONST_INT }}, \
2069 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2070 { "extend_operand", { REG, SUBREG, MEM }}, \
2071 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2072 { "m32r_block_immediate_operand",{ CONST_INT }}, \
2073 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2074 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }},
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