1 /* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
32 #undef WCHAR_TYPE_SIZE
33 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
40 #undef SUBTARGET_SWITCHES
43 /* M32R/X overrides. */
44 /* Print subsidiary information on the compiler version in use. */
45 #define TARGET_VERSION fprintf (stderr, " (m32r/x)");
47 /* Additional flags for the preprocessor. */
48 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
50 /* Assembler switches. */
51 #define ASM_CPU_SPEC \
52 "%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
54 /* Use m32rx specific crt0/crtinit/crtfini files. */
55 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
56 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
58 /* Extra machine dependent switches. */
59 #define SUBTARGET_SWITCHES \
60 { "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
61 { "32r", -TARGET_M32RX_MASK, "" },
63 /* Define this macro as a C expression for the initializer of an array of
64 strings to tell the driver program which options are defaults for this
65 target and thus do not need to be handled specially when using
66 `MULTILIB_OPTIONS'. */
67 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
69 /* Number of additional registers the subtarget defines. */
70 #define SUBTARGET_NUM_REGISTERS 1
72 /* 1 for registers that cannot be allocated. */
73 #define SUBTARGET_FIXED_REGISTERS , 1
75 /* 1 for registers that are not available across function calls. */
76 #define SUBTARGET_CALL_USED_REGISTERS , 1
78 /* Order to allocate model specific registers. */
79 #define SUBTARGET_REG_ALLOC_ORDER , 19
81 /* Registers which are accumulators. */
82 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
84 /* All registers added. */
85 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
87 /* Additional accumulator registers. */
88 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
90 /* Define additional register names. */
91 #define SUBTARGET_REGISTER_NAMES , "a1"
92 /* end M32R/X overrides. */
94 /* Print subsidiary information on the compiler version in use. */
95 #ifndef TARGET_VERSION
96 #define TARGET_VERSION fprintf (stderr, " (m32r)")
99 /* Switch Recognition by gcc.c. Add -G xx support */
101 #undef SWITCH_TAKES_ARG
102 #define SWITCH_TAKES_ARG(CHAR) \
103 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
105 /* Names to predefine in the preprocessor for this target machine. */
106 /* __M32R__ is defined by the existing compiler so we use that. */
107 #define TARGET_CPU_CPP_BUILTINS() \
110 builtin_define ("__M32R__"); \
111 builtin_assert ("cpu=m32r"); \
112 builtin_assert ("machine=m32r"); \
116 /* This macro defines names of additional specifications to put in the specs
117 that can be used in various specifications like CC1_SPEC. Its definition
118 is an initializer with a subgrouping for each command option.
120 Each subgrouping contains a string constant, that defines the
121 specification name, and a string constant that used by the GNU CC driver
124 Do not define this macro if it does not need to do anything. */
126 #ifndef SUBTARGET_EXTRA_SPECS
127 #define SUBTARGET_EXTRA_SPECS
131 #define ASM_CPU_SPEC ""
135 #define CPP_CPU_SPEC ""
139 #define CC1_CPU_SPEC ""
142 #ifndef LINK_CPU_SPEC
143 #define LINK_CPU_SPEC ""
146 #ifndef STARTFILE_CPU_SPEC
147 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
150 #ifndef ENDFILE_CPU_SPEC
151 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
155 #if 0 /* not supported yet */
156 #define RELAX_SPEC "%{mrelax:-relax}"
158 #define RELAX_SPEC ""
162 #define EXTRA_SPECS \
163 { "asm_cpu", ASM_CPU_SPEC }, \
164 { "cpp_cpu", CPP_CPU_SPEC }, \
165 { "cc1_cpu", CC1_CPU_SPEC }, \
166 { "link_cpu", LINK_CPU_SPEC }, \
167 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
168 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
169 { "relax", RELAX_SPEC }, \
170 SUBTARGET_EXTRA_SPECS
172 #define CC1_SPEC "%{G*} %(cc1_cpu)"
174 /* Options to pass on to the assembler. */
176 #define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
178 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
180 #undef STARTFILE_SPEC
181 #define STARTFILE_SPEC "%(startfile_cpu)"
184 #define ENDFILE_SPEC "%(endfile_cpu)"
188 /* Run-time compilation parameters selecting different hardware subsets. */
190 extern int target_flags;
192 /* If nonzero, tell the linker to do relaxing.
193 We don't do anything with the option, other than recognize it.
194 LINK_SPEC handles passing -relax to the linker.
195 This can cause incorrect debugging information as line numbers may
196 turn out wrong. This shouldn't be specified unless accompanied with -O2
197 [where the user expects debugging information to be less accurate]. */
198 #define TARGET_RELAX_MASK (1 << 0)
200 /* For miscellaneous debugging purposes. */
201 #define TARGET_DEBUG_MASK (1 << 1)
202 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
204 /* Align loops to 32 byte boundaries (cache line size). */
205 /* ??? This option is experimental and is not documented. */
206 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
207 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
209 /* Change issue rate. */
210 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
211 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
213 /* Change branch cost */
214 #define TARGET_BRANCH_COST_MASK (1 << 4)
215 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
217 /* Target machine to compile for. */
218 #define TARGET_M32R 1
220 /* Support extended instruction set. */
221 #define TARGET_M32RX_MASK (1 << 5)
222 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
224 #define TARGET_M32R (! TARGET_M32RX)
226 /* Macro to define tables used to set the flags.
227 This is a list in braces of pairs in braces,
228 each pair being { "NAME", VALUE }
229 where VALUE is the bits to set or minus the bits to clear.
230 An empty string NAME is used to identify the default VALUE. */
232 #ifndef SUBTARGET_SWITCHES
233 #define SUBTARGET_SWITCHES
236 #ifndef TARGET_DEFAULT
237 #define TARGET_DEFAULT 0
240 #define TARGET_SWITCHES \
242 /* { "relax", TARGET_RELAX_MASK, "" }, \
243 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \
244 { "debug", TARGET_DEBUG_MASK, \
245 N_("Display compile time statistics") }, \
246 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \
247 N_("Align all loops to 32 byte boundary") }, \
248 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
249 { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \
250 N_("Only issue one instruction per cycle") }, \
251 { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \
252 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \
253 N_("Prefer branches over conditional execution") }, \
254 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
256 { "", TARGET_DEFAULT, "" } \
259 extern const char * m32r_model_string;
260 extern const char * m32r_sdata_string;
262 #ifndef SUBTARGET_OPTIONS
263 #define SUBTARGET_OPTIONS
266 #define TARGET_OPTIONS \
268 { "model=", & m32r_model_string, \
269 N_("Code size: small, medium or large"), 0}, \
270 { "sdata=", & m32r_sdata_string, \
271 N_("Small data area: none, sdata, use"), 0} \
277 Code models are used to select between two choices of two separate
278 possibilities (address space size, call insn to use):
280 small: addresses use 24 bits, use bl to make calls
281 medium: addresses use 32 bits, use bl to make calls (*1)
282 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
284 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
285 using this one doesn't make much sense.
287 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
288 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
290 Internally these are recorded as TARGET_ADDR{24,32} and
293 The __model__ attribute can be used to select the code model to use when
294 accessing particular objects. */
296 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
298 extern enum m32r_model m32r_model;
299 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
300 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
301 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
302 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
303 #define TARGET_ADDR32 (! TARGET_ADDR24)
304 #define TARGET_CALL26 (! TARGET_CALL32)
305 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
307 /* The default is the small model. */
308 #ifndef M32R_MODEL_DEFAULT
309 #define M32R_MODEL_DEFAULT "small"
314 The SDA consists of sections .sdata, .sbss, and .scommon.
315 .scommon isn't a real section, symbols in it have their section index
316 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
318 Two switches control the SDA:
320 -G NNN - specifies the maximum size of variable to go in the SDA
322 -msdata=foo - specifies how such variables are handled
324 -msdata=none - small data area is disabled
326 -msdata=sdata - small data goes in the SDA, special code isn't
327 generated to use it, and special relocs aren't
330 -msdata=use - small data goes in the SDA, special code is generated
331 to use the SDA and special relocs are generated
333 The SDA is not multilib'd, it isn't necessary.
334 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
335 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
336 -msdata=use will successfully link with them (references in header files
337 will cause the compiler to emit code that refers to library objects in
338 .data). ??? There can be a problem if the user passes a -G value greater
339 than the default and a library object in a header file is that size.
340 The default is 8 so this should be rare - if it occurs the user
341 is required to rebuild the libraries or use a smaller value for -G.
344 /* Maximum size of variables that go in .sdata/.sbss.
345 The -msdata=foo switch also controls how small variables are handled. */
346 #ifndef SDATA_DEFAULT_SIZE
347 #define SDATA_DEFAULT_SIZE 8
350 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
352 extern enum m32r_sdata m32r_sdata;
353 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
354 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
355 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
357 /* Default is to disable the SDA
358 [for upward compatibility with previous toolchains]. */
359 #ifndef M32R_SDATA_DEFAULT
360 #define M32R_SDATA_DEFAULT "none"
363 /* Define this macro as a C expression for the initializer of an array of
364 strings to tell the driver program which options are defaults for this
365 target and thus do not need to be handled specially when using
366 `MULTILIB_OPTIONS'. */
367 #ifndef SUBTARGET_MULTILIB_DEFAULTS
368 #define SUBTARGET_MULTILIB_DEFAULTS
371 #ifndef MULTILIB_DEFAULTS
372 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
375 /* Sometimes certain combinations of command options do not make
376 sense on a particular target machine. You can define a macro
377 `OVERRIDE_OPTIONS' to take account of this. This macro, if
378 defined, is executed once just after all the command options have
381 Don't use this macro to turn on various extra optimizations for
382 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
384 #ifndef SUBTARGET_OVERRIDE_OPTIONS
385 #define SUBTARGET_OVERRIDE_OPTIONS
388 #define OVERRIDE_OPTIONS \
391 /* These need to be done at start up. \
392 It's convenient to do them here. */ \
394 SUBTARGET_OVERRIDE_OPTIONS \
398 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
399 #define SUBTARGET_OPTIMIZATION_OPTIONS
402 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
406 flag_regmove = TRUE; \
410 flag_omit_frame_pointer = TRUE; \
411 flag_strength_reduce = FALSE; \
414 SUBTARGET_OPTIMIZATION_OPTIONS \
418 /* Define this macro if debugging can be performed even without a
419 frame pointer. If this macro is defined, GNU CC will turn on the
420 `-fomit-frame-pointer' option whenever `-O' is specified. */
421 #define CAN_DEBUG_WITHOUT_FP
423 /* Target machine storage layout. */
425 /* Define this if most significant bit is lowest numbered
426 in instructions that operate on numbered bit-fields. */
427 #define BITS_BIG_ENDIAN 1
429 /* Define this if most significant byte of a word is the lowest numbered. */
430 #define BYTES_BIG_ENDIAN 1
432 /* Define this if most significant word of a multiword number is the lowest
434 #define WORDS_BIG_ENDIAN 1
436 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
437 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
438 which will be used only when compiling libgcc2.c. Typically the
439 value will be set based on preprocessor defines. */
440 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
442 /* Width of a word, in units (bytes). */
443 #define UNITS_PER_WORD 4
445 /* Define this macro if it is advisable to hold scalars in registers
446 in a wider mode than that declared by the program. In such cases,
447 the value is constrained to be within the bounds of the declared
448 type, but kept valid in the wider mode. The signedness of the
449 extension may differ from that of the type. */
450 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
451 if (GET_MODE_CLASS (MODE) == MODE_INT \
452 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
457 /* Define this macro if the promotion described by `PROMOTE_MODE'
458 should also be done for outgoing function arguments. */
459 /*#define PROMOTE_FUNCTION_ARGS*/
461 /* Likewise, if the function return value is promoted.
462 If defined, FUNCTION_VALUE must perform the same promotions done by
464 /*#define PROMOTE_FUNCTION_RETURN*/
466 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
467 #define PARM_BOUNDARY 32
469 /* Boundary (in *bits*) on which stack pointer should be aligned. */
470 #define STACK_BOUNDARY 32
472 /* ALIGN FRAMES on word boundaries */
473 #define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
475 /* Allocation boundary (in *bits*) for the code of a function. */
476 #define FUNCTION_BOUNDARY 32
478 /* Alignment of field after `int : 0' in a structure. */
479 #define EMPTY_FIELD_BOUNDARY 32
481 /* Every structure's size must be a multiple of this. */
482 #define STRUCTURE_SIZE_BOUNDARY 8
484 /* A bit-field declared as `int' forces `int' alignment for the struct. */
485 #define PCC_BITFIELD_TYPE_MATTERS 1
487 /* No data type wants to be aligned rounder than this. */
488 #define BIGGEST_ALIGNMENT 32
490 /* The best alignment to use in cases where we have a choice. */
491 #define FASTEST_ALIGNMENT 32
493 /* Make strings word-aligned so strcpy from constants will be faster. */
494 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
495 ((TREE_CODE (EXP) == STRING_CST \
496 && (ALIGN) < FASTEST_ALIGNMENT) \
497 ? FASTEST_ALIGNMENT : (ALIGN))
499 /* Make arrays of chars word-aligned for the same reasons. */
500 #define DATA_ALIGNMENT(TYPE, ALIGN) \
501 (TREE_CODE (TYPE) == ARRAY_TYPE \
502 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
503 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
505 /* Set this nonzero if move instructions will actually fail to work
506 when given unaligned data. */
507 #define STRICT_ALIGNMENT 1
509 /* Layout of source language data types. */
511 #define SHORT_TYPE_SIZE 16
512 #define INT_TYPE_SIZE 32
513 #define LONG_TYPE_SIZE 32
514 #define LONG_LONG_TYPE_SIZE 64
515 #define FLOAT_TYPE_SIZE 32
516 #define DOUBLE_TYPE_SIZE 64
517 #define LONG_DOUBLE_TYPE_SIZE 64
519 /* Define this as 1 if `char' should by default be signed; else as 0. */
520 #define DEFAULT_SIGNED_CHAR 1
522 #define SIZE_TYPE "long unsigned int"
523 #define PTRDIFF_TYPE "long int"
524 #define WCHAR_TYPE "short unsigned int"
525 #define WCHAR_TYPE_SIZE 16
527 /* Standard register usage. */
529 /* Number of actual hardware registers.
530 The hardware registers are assigned numbers for the compiler
531 from 0 to just below FIRST_PSEUDO_REGISTER.
532 All registers that the compiler knows about must be given numbers,
533 even those that are not normally considered general registers. */
535 #define M32R_NUM_REGISTERS 19
537 #ifndef SUBTARGET_NUM_REGISTERS
538 #define SUBTARGET_NUM_REGISTERS 0
541 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
543 /* 1 for registers that have pervasive standard uses
544 and are not available for the register allocator.
546 0-3 - arguments/results
547 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
549 7 - call used, static chain pointer
551 12 - call saved [reserved for global pointer]
553 14 - subroutine link register
558 19 - accumulator 1 in the m32r/x
559 By default, the extension registers are not available. */
561 #ifndef SUBTARGET_FIXED_REGISTERS
562 #define SUBTARGET_FIXED_REGISTERS
565 #define FIXED_REGISTERS \
567 0, 0, 0, 0, 0, 0, 0, 0, \
568 0, 0, 0, 0, 0, 0, 0, 1, \
570 SUBTARGET_FIXED_REGISTERS \
573 /* 1 for registers not available across function calls.
574 These must include the FIXED_REGISTERS and also any
575 registers that can be used without being saved.
576 The latter must include the registers where values are returned
577 and the register where structure-value addresses are passed.
578 Aside from that, you can include as many other registers as you like. */
580 #ifndef SUBTARGET_CALL_USED_REGISTERS
581 #define SUBTARGET_CALL_USED_REGISTERS
584 #define CALL_USED_REGISTERS \
586 1, 1, 1, 1, 1, 1, 1, 1, \
587 0, 0, 0, 0, 0, 0, 1, 1, \
589 SUBTARGET_CALL_USED_REGISTERS \
592 /* Zero or more C statements that may conditionally modify two variables
593 `fixed_regs' and `call_used_regs' (both of type `char []') after they
594 have been initialized from the two preceding macros.
596 This is necessary in case the fixed or call-clobbered registers depend
599 You need not define this macro if it has no work to do. */
601 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
602 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
605 /* If defined, an initializer for a vector of integers, containing the
606 numbers of hard registers in the order in which GNU CC should
607 prefer to use them (from most preferred to least). */
609 #ifndef SUBTARGET_REG_ALLOC_ORDER
610 #define SUBTARGET_REG_ALLOC_ORDER
613 #if 1 /* better for int code */
614 #define REG_ALLOC_ORDER \
616 4, 5, 6, 7, 2, 3, 8, 9, 10, \
617 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
618 SUBTARGET_REG_ALLOC_ORDER \
621 #else /* better for fp code at expense of int code */
622 #define REG_ALLOC_ORDER \
624 0, 1, 2, 3, 4, 5, 6, 7, 8, \
625 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
626 SUBTARGET_REG_ALLOC_ORDER \
630 /* Return number of consecutive hard regs needed starting at reg REGNO
631 to hold something of mode MODE.
632 This is ordinarily the length in words of a value of mode MODE
633 but can be less for certain modes in special long registers. */
634 #define HARD_REGNO_NREGS(REGNO, MODE) \
635 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
637 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
638 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
639 extern unsigned int m32r_mode_class[];
640 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
641 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
643 /* A C expression that is nonzero if it is desirable to choose
644 register allocation so as to avoid move instructions between a
645 value of mode MODE1 and a value of mode MODE2.
647 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
648 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
649 MODE2)' must be zero. */
651 /* Tie QI/HI/SI modes together. */
652 #define MODES_TIEABLE_P(MODE1, MODE2) \
653 (GET_MODE_CLASS (MODE1) == MODE_INT \
654 && GET_MODE_CLASS (MODE2) == MODE_INT \
655 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
656 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
658 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
659 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG)
661 /* Register classes and constants. */
663 /* Define the classes of registers for register constraints in the
664 machine description. Also define ranges of constants.
666 One of the classes must always be named ALL_REGS and include all hard regs.
667 If there is more than one class, another class must be named NO_REGS
668 and contain no registers.
670 The name GENERAL_REGS must be the name of a class (or an alias for
671 another name such as ALL_REGS). This is the class of registers
672 that is allowed by "g" or "r" in a register constraint.
673 Also, registers outside this class are allocated only when
674 instructions express preferences for them.
676 The classes must be numbered in nondecreasing order; that is,
677 a larger-numbered class must never be contained completely
678 in a smaller-numbered class.
680 For any two classes, it is very desirable that there be another
681 class that represents their union.
683 It is important that any condition codes have class NO_REGS.
684 See `register_operand'. */
688 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
691 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
693 /* Give names of register classes as strings for dump file. */
694 #define REG_CLASS_NAMES \
695 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
697 /* Define which registers fit in which classes.
698 This is an initializer for a vector of HARD_REG_SET
699 of length N_REG_CLASSES. */
701 #ifndef SUBTARGET_REG_CLASS_CARRY
702 #define SUBTARGET_REG_CLASS_CARRY 0
705 #ifndef SUBTARGET_REG_CLASS_ACCUM
706 #define SUBTARGET_REG_CLASS_ACCUM 0
709 #ifndef SUBTARGET_REG_CLASS_GENERAL
710 #define SUBTARGET_REG_CLASS_GENERAL 0
713 #ifndef SUBTARGET_REG_CLASS_ALL
714 #define SUBTARGET_REG_CLASS_ALL 0
717 #define REG_CLASS_CONTENTS \
720 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
721 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
722 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
723 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
726 /* The same information, inverted:
727 Return the class number of the smallest class containing
728 reg number REGNO. This could be a conditional expression
729 or could index an array. */
730 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
731 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
733 /* The class value for index registers, and the one for base regs. */
734 #define INDEX_REG_CLASS GENERAL_REGS
735 #define BASE_REG_CLASS GENERAL_REGS
737 #define REG_CLASS_FROM_LETTER(C) \
738 ((C) == 'c' ? CARRY_REG \
739 : (C) == 'a' ? ACCUM_REGS \
742 /* These assume that REGNO is a hard or pseudo reg number.
743 They give nonzero only if REGNO is a hard reg of the suitable class
744 or a pseudo reg currently allocated to a suitable hard reg.
745 Since they use reg_renumber, they are safe only once reg_renumber
746 has been allocated, which happens in local-alloc.c. */
747 #define REGNO_OK_FOR_BASE_P(REGNO) \
748 ((REGNO) < FIRST_PSEUDO_REGISTER \
749 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
750 : GPR_P (reg_renumber[REGNO]))
751 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
753 /* Given an rtx X being reloaded into a reg required to be
754 in class CLASS, return the class of reg to actually use.
755 In general this is just CLASS; but on some machines
756 in some cases it is preferable to use a more restrictive class. */
757 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
760 /* Return the maximum number of consecutive registers
761 needed to represent mode MODE in a register of class CLASS. */
762 #define CLASS_MAX_NREGS(CLASS, MODE) \
763 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
765 /* The letters I, J, K, L, M, N, O, P in a register constraint string
766 can be used to stand for particular ranges of immediate operands.
767 This macro defines what the ranges are.
768 C is the letter, and VALUE is a constant value.
769 Return 1 if VALUE is in the range specified by C. */
770 /* 'I' is used for 8 bit signed immediates.
771 'J' is used for 16 bit signed immediates.
772 'K' is used for 16 bit unsigned immediates.
773 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
774 'M' is used for 24 bit unsigned immediates.
775 'N' is used for any 32 bit non-symbolic value.
776 'O' is used for 5 bit unsigned immediates (shift count).
777 'P' is used for 16 bit signed immediates for compares
778 (values in the range -32767 to +32768). */
780 /* Return true if a value is inside a range. */
781 #define IN_RANGE_P(VALUE, LOW, HIGH) \
782 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
783 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
785 /* Local to this file. */
786 #define INT8_P(X) ((X) >= -0x80 && (X) <= 0x7f)
787 #define INT16_P(X) ((X) >= -0x8000 && (X) <= 0x7fff)
788 #define CMP_INT16_P(X) ((X) >= -0x7fff && (X) <= 0x8000)
789 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
790 && ((X) >> 16) >= -0x8000 \
791 && ((X) >> 16) <= 0x7fff)
792 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
793 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
794 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
795 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
796 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
798 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
799 ((C) == 'I' ? INT8_P (VALUE) \
800 : (C) == 'J' ? INT16_P (VALUE) \
801 : (C) == 'K' ? UINT16_P (VALUE) \
802 : (C) == 'L' ? UPPER16_P (VALUE) \
803 : (C) == 'M' ? UINT24_P (VALUE) \
804 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
805 : (C) == 'O' ? UINT5_P (VALUE) \
806 : (C) == 'P' ? CMP_INT16_P (VALUE) \
809 /* Similar, but for floating constants, and defining letters G and H.
810 Here VALUE is the CONST_DOUBLE rtx itself.
811 For the m32r, handle a few constants inline.
812 ??? We needn't treat DI and DF modes differently, but for now we do. */
813 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
814 ((C) == 'G' ? easy_di_const (VALUE) \
815 : (C) == 'H' ? easy_df_const (VALUE) \
818 /* A C expression that defines the optional machine-dependent constraint
819 letters that can be used to segregate specific types of operands,
820 usually memory references, for the target machine. It should return 1 if
821 VALUE corresponds to the operand type represented by the constraint letter
822 C. If C is not defined as an extra constraint, the value returned should
823 be 0 regardless of VALUE. */
824 /* Q is for symbolic addresses loadable with ld24.
825 R is for symbolic addresses when ld24 can't be used.
826 S is for stores with pre {inc,dec}rement
827 T is for indirect of a pointer.
828 U is for loads with post increment. */
830 #define EXTRA_CONSTRAINT(VALUE, C) \
831 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
832 || addr24_operand (VALUE, VOIDmode)) \
833 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
834 || addr32_operand (VALUE, VOIDmode)) \
835 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
836 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
838 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
839 && memreg_operand (VALUE, GET_MODE (VALUE))) \
840 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
841 && LOAD_POSTINC_P (GET_MODE (VALUE), \
845 /* Stack layout and stack pointer usage. */
847 /* Define this macro if pushing a word onto the stack moves the stack
848 pointer to a smaller address. */
849 #define STACK_GROWS_DOWNWARD
851 /* Define this if the nominal address of the stack frame
852 is at the high-address end of the local variables;
853 that is, each additional local variable allocated
854 goes at a more negative offset from the frame pointer. */
855 /*#define FRAME_GROWS_DOWNWARD*/
857 /* Offset from frame pointer to start allocating local variables at.
858 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
859 first local allocated. Otherwise, it is the offset to the BEGINNING
860 of the first local allocated. */
861 /* The frame pointer points at the same place as the stack pointer, except if
862 alloca has been called. */
863 #define STARTING_FRAME_OFFSET \
864 M32R_STACK_ALIGN (current_function_outgoing_args_size)
866 /* Offset from the stack pointer register to the first location at which
867 outgoing arguments are placed. */
868 #define STACK_POINTER_OFFSET 0
870 /* Offset of first parameter from the argument pointer register value. */
871 #define FIRST_PARM_OFFSET(FNDECL) 0
873 /* A C expression whose value is RTL representing the address in a
874 stack frame where the pointer to the caller's frame is stored.
875 Assume that FRAMEADDR is an RTL expression for the address of the
878 If you don't define this macro, the default is to return the value
879 of FRAMEADDR--that is, the stack frame address is also the address
880 of the stack word that points to the previous frame. */
881 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
883 /* A C expression whose value is RTL representing the value of the
884 return address for the frame COUNT steps up from the current frame.
885 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
886 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
888 /* The current return address is in r14. */
889 #if 0 /* The default value should work. */
890 #define RETURN_ADDR_RTX(COUNT, FRAME) \
892 ? gen_rtx_REG (Pmode, 14) \
893 : copy_to_reg (gen_rtx_MEM (Pmode, \
894 memory_address (Pmode, \
895 plus_constant ((FRAME), \
899 /* Register to use for pushing function arguments. */
900 #define STACK_POINTER_REGNUM 15
902 /* Base register for access to local variables of the function. */
903 #define FRAME_POINTER_REGNUM 13
905 /* Base register for access to arguments of the function. */
906 #define ARG_POINTER_REGNUM 16
908 /* The register number of the return address pointer register, which
909 is used to access the current function's return address from the
910 stack. On some machines, the return address is not at a fixed
911 offset from the frame pointer or stack pointer or argument
912 pointer. This register can be defined to point to the return
913 address on the stack, and then be converted by `ELIMINABLE_REGS'
914 into either the frame pointer or stack pointer.
916 Do not define this macro unless there is no other way to get the
917 return address from the stack. */
919 /* #define RETURN_ADDRESS_POINTER_REGNUM */
921 /* Register in which static-chain is passed to a function. This must
922 not be a register used by the prologue. */
923 #define STATIC_CHAIN_REGNUM 7
925 /* These aren't official macros. */
926 #define PROLOGUE_TMP_REGNUM 4
927 #define RETURN_ADDR_REGNUM 14
928 /* #define GP_REGNUM 12 */
929 #define CARRY_REGNUM 17
930 #define ACCUM_REGNUM 18
931 #define M32R_MAX_INT_REGS 16
933 #ifndef SUBTARGET_GPR_P
934 #define SUBTARGET_GPR_P(REGNO) 0
937 #ifndef SUBTARGET_ACCUM_P
938 #define SUBTARGET_ACCUM_P(REGNO) 0
941 #ifndef SUBTARGET_CARRY_P
942 #define SUBTARGET_CARRY_P(REGNO) 0
945 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
946 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
947 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
949 /* Eliminating the frame and arg pointers. */
951 /* A C expression which is nonzero if a function must have and use a
952 frame pointer. This expression is evaluated in the reload pass.
953 If its value is nonzero the function will have a frame pointer. */
954 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
957 /* C statement to store the difference between the frame pointer
958 and the stack pointer values immediately after the function prologue.
959 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
960 need not be defined. */
961 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
962 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
965 /* If defined, this macro specifies a table of register pairs used to
966 eliminate unneeded registers that point into the stack frame. If
967 it is not defined, the only elimination attempted by the compiler
968 is to replace references to the frame pointer with references to
971 Note that the elimination of the argument pointer with the stack
972 pointer is specified first since that is the preferred elimination. */
974 #define ELIMINABLE_REGS \
975 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
976 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
977 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
979 /* A C expression that returns nonzero if the compiler is allowed to
980 try to replace register number FROM-REG with register number
981 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
982 defined, and will usually be the constant 1, since most of the
983 cases preventing register elimination are things that the compiler
984 already knows about. */
986 #define CAN_ELIMINATE(FROM, TO) \
987 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
988 ? ! frame_pointer_needed \
991 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
992 specifies the initial difference between the specified pair of
993 registers. This macro must be defined if `ELIMINABLE_REGS' is
996 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
998 int size = m32r_compute_frame_size (get_frame_size ()); \
1000 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1002 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1003 (OFFSET) = size - current_function_pretend_args_size; \
1004 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1005 (OFFSET) = size - current_function_pretend_args_size; \
1010 /* Function argument passing. */
1012 /* When a prototype says `char' or `short', really pass an `int'. */
1013 #define PROMOTE_PROTOTYPES 1
1015 /* If defined, the maximum amount of space required for outgoing
1016 arguments will be computed and placed into the variable
1017 `current_function_outgoing_args_size'. No space will be pushed
1018 onto the stack for each call; instead, the function prologue should
1019 increase the stack frame size by this amount. */
1020 #define ACCUMULATE_OUTGOING_ARGS 1
1022 /* Define this macro if functions should assume that stack space has
1023 been allocated for arguments even when their values are passed in
1026 The value of this macro is the size, in bytes, of the area
1027 reserved for arguments passed in registers for the function
1028 represented by FNDECL.
1030 This space can be allocated by the caller, or be a part of the
1031 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1034 #define REG_PARM_STACK_SPACE(FNDECL) \
1035 (M32R_MAX_PARM_REGS * UNITS_PER_WORD)
1038 /* Value is the number of bytes of arguments automatically
1039 popped when returning from a subroutine call.
1040 FUNDECL is the declaration node of the function (as a tree),
1041 FUNTYPE is the data type of the function (as a tree),
1042 or for a library call it is an identifier node for the subroutine name.
1043 SIZE is the number of bytes of arguments passed on the stack. */
1044 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1046 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1047 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1049 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1050 || TREE_ADDRESSABLE (TYPE)))
1052 /* Define a data type for recording info about an argument list
1053 during the scan of that argument list. This data type should
1054 hold all necessary information about the function itself
1055 and about the args processed so far, enough to enable macros
1056 such as FUNCTION_ARG to determine where the next arg should go. */
1057 #define CUMULATIVE_ARGS int
1059 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1060 for a call to a function whose data type is FNTYPE.
1061 For a library call, FNTYPE is 0. */
1062 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1065 /* The number of registers used for parameter passing. Local to this file. */
1066 #define M32R_MAX_PARM_REGS 4
1068 /* 1 if N is a possible register number for function argument passing. */
1069 #define FUNCTION_ARG_REGNO_P(N) \
1070 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1072 /* The ROUND_ADVANCE* macros are local to this file. */
1073 /* Round SIZE up to a word boundary. */
1074 #define ROUND_ADVANCE(SIZE) \
1075 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1077 /* Round arg MODE/TYPE up to the next word boundary. */
1078 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1079 ((MODE) == BLKmode \
1080 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1081 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1083 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1084 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1086 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1087 a reg. This includes arguments that have to be passed by reference as the
1088 pointer to them is passed in a reg if one is available (and that is what
1090 This macro is only used in this file. */
1091 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1092 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1094 /* Determine where to put an argument to a function.
1095 Value is zero to push the argument on the stack,
1096 or a hard register in which to store the argument.
1098 MODE is the argument's machine mode.
1099 TYPE is the data type of the argument (as a tree).
1100 This is null for libcalls where that information may
1102 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1103 the preceding args and about the function being called.
1104 NAMED is nonzero if this argument is a named parameter
1105 (otherwise it is an extra parameter matching an ellipsis). */
1106 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1107 and the rest are pushed. */
1108 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1109 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1110 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1113 /* A C expression for the number of words, at the beginning of an
1114 argument, must be put in registers. The value must be zero for
1115 arguments that are passed entirely in registers or that are entirely
1116 pushed on the stack.
1118 On some machines, certain arguments must be passed partially in
1119 registers and partially in memory. On these machines, typically the
1120 first @var{n} words of arguments are passed in registers, and the rest
1121 on the stack. If a multi-word argument (a @code{double} or a
1122 structure) crosses that boundary, its first few words must be passed
1123 in registers and the rest must be pushed. This macro tells the
1124 compiler when this occurs, and how many of the words should go in
1126 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1127 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1129 /* A C expression that indicates when an argument must be passed by
1130 reference. If nonzero for an argument, a copy of that argument is
1131 made in memory and a pointer to the argument is passed instead of
1132 the argument itself. The pointer is passed in whatever way is
1133 appropriate for passing a pointer to that type. */
1134 /* All arguments greater than 8 bytes are passed this way. */
1135 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1136 ((TYPE) && m32r_pass_by_reference (TYPE))
1138 /* Update the data in CUM to advance over an argument
1139 of mode MODE and data type TYPE.
1140 (TYPE is null for libcalls where that information may not be available.) */
1141 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1142 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1143 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1145 /* If defined, a C expression that gives the alignment boundary, in bits,
1146 of an argument with the specified mode and type. If it is not defined,
1147 PARM_BOUNDARY is used for all arguments. */
1149 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1150 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1151 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1153 : 2 * PARM_BOUNDARY)
1156 /* This macro offers an alternative
1157 to using `__builtin_saveregs' and defining the macro
1158 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1159 arguments into the stack so that all the arguments appear to have
1160 been passed consecutively on the stack. Once this is done, you
1161 can use the standard implementation of varargs that works for
1162 machines that pass all their arguments on the stack.
1164 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
1165 containing the values that obtain after processing of the named
1166 arguments. The arguments MODE and TYPE describe the last named
1167 argument--its machine mode and its data type as a tree node.
1169 The macro implementation should do two things: first, push onto the
1170 stack all the argument registers *not* used for the named
1171 arguments, and second, store the size of the data thus pushed into
1172 the `int'-valued variable whose name is supplied as the argument
1173 PRETEND_SIZE. The value that you store here will serve as
1174 additional offset for setting up the stack frame.
1176 If the argument NO_RTL is nonzero, it means that the
1177 arguments of the function are being analyzed for the second time.
1178 This happens for an inline function, which is not actually
1179 compiled until the end of the source file. The macro
1180 `SETUP_INCOMING_VARARGS' should not generate any instructions in
1183 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1184 m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1186 /* Implement `va_arg'. */
1187 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1188 m32r_va_arg (valist, type)
1190 /* Function results. */
1192 /* Define how to find the value returned by a function.
1193 VALTYPE is the data type of the value (as a tree).
1194 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1195 otherwise, FUNC is 0. */
1196 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1198 /* Define how to find the value returned by a library function
1199 assuming the value has mode MODE. */
1200 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1202 /* 1 if N is a possible register number for a function value
1203 as seen by the caller. */
1204 /* ??? What about r1 in DI/DF values. */
1205 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1207 /* A C expression which can inhibit the returning of certain function
1208 values in registers, based on the type of value. A nonzero value says
1209 to return the function value in memory, just as large structures are
1210 always returned. Here TYPE will be a C expression of type `tree',
1211 representing the data type of the value. */
1212 #define RETURN_IN_MEMORY(TYPE) m32r_pass_by_reference (TYPE)
1214 /* Tell GCC to use RETURN_IN_MEMORY. */
1215 #define DEFAULT_PCC_STRUCT_RETURN 0
1217 /* Register in which address to store a structure value
1218 is passed to a function, or 0 to use `invisible' first argument. */
1219 #define STRUCT_VALUE 0
1221 /* Function entry and exit. */
1223 /* Initialize data used by insn expanders. This is called from
1224 init_emit, once for each function, before code is generated. */
1225 #define INIT_EXPANDERS m32r_init_expanders ()
1227 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1228 the stack pointer does not matter. The value is tested only in
1229 functions that have frame pointers.
1230 No definition is equivalent to always zero. */
1231 #define EXIT_IGNORE_STACK 1
1233 /* Output assembler code to FILE to increment profiler label # LABELNO
1234 for profiling a function entry. */
1235 #define FUNCTION_PROFILER(FILE, LABELNO) abort ()
1239 /* On the M32R, the trampoline is
1246 ??? Need addr32 support.
1249 /* Length in bytes of the trampoline for entering a nested function. */
1250 #define TRAMPOLINE_SIZE 12
1252 /* Emit RTL insns to initialize the variable parts of a trampoline.
1253 FNADDR is an RTX for the address of the function's pure code.
1254 CXT is an RTX for the static chain value for the function. */
1255 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1257 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1258 plus_constant ((CXT), 0xe7000000)); \
1259 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1260 plus_constant ((FNADDR), 0xe6000000)); \
1261 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1262 GEN_INT (0x1fc67000)); \
1263 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)))); \
1266 /* Library calls. */
1268 /* Generate calls to memcpy, memcmp and memset. */
1269 #define TARGET_MEM_FUNCTIONS
1271 /* Addressing modes, and classification of registers for them. */
1273 /* Maximum number of registers that can appear in a valid memory address. */
1274 #define MAX_REGS_PER_ADDRESS 1
1276 /* We have post-inc load and pre-dec,pre-inc store,
1277 but only for 4 byte vals. */
1278 #define HAVE_PRE_DECREMENT 1
1279 #define HAVE_PRE_INCREMENT 1
1280 #define HAVE_POST_INCREMENT 1
1282 /* Recognize any constant value that is a valid address. */
1283 #define CONSTANT_ADDRESS_P(X) \
1284 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1285 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
1287 /* Nonzero if the constant value X is a legitimate general operand.
1288 We don't allow (plus symbol large-constant) as the relocations can't
1289 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1290 We allow all CONST_DOUBLE's as the md file patterns will force the
1291 constant to memory if they can't handle them. */
1293 #define LEGITIMATE_CONSTANT_P(X) \
1294 (! (GET_CODE (X) == CONST \
1295 && GET_CODE (XEXP (X, 0)) == PLUS \
1296 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1297 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1298 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1300 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1301 and check its validity for a certain class.
1302 We have two alternate definitions for each of them.
1303 The usual definition accepts all pseudo regs; the other rejects
1304 them unless they have been allocated suitable hard regs.
1305 The symbol REG_OK_STRICT causes the latter definition to be used.
1307 Most source files want to accept pseudo regs in the hope that
1308 they will get allocated to the class that the insn wants them to be in.
1309 Source files for reload pass need to be strict.
1310 After reload, it makes no difference, since pseudo regs have
1311 been eliminated by then. */
1313 #ifdef REG_OK_STRICT
1315 /* Nonzero if X is a hard reg that can be used as a base reg. */
1316 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1317 /* Nonzero if X is a hard reg that can be used as an index. */
1318 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1322 /* Nonzero if X is a hard reg that can be used as a base reg
1323 or if it is a pseudo reg. */
1324 #define REG_OK_FOR_BASE_P(X) \
1325 (GPR_P (REGNO (X)) \
1326 || (REGNO (X)) == ARG_POINTER_REGNUM \
1327 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1328 /* Nonzero if X is a hard reg that can be used as an index
1329 or if it is a pseudo reg. */
1330 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1334 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1335 that is a valid memory address for an instruction.
1336 The MODE argument is the machine mode for the MEM expression
1337 that wants to use this address. */
1339 /* Local to this file. */
1340 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1342 /* Local to this file. */
1343 #define RTX_OK_FOR_OFFSET_P(X) \
1344 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1346 /* Local to this file. */
1347 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1348 (GET_CODE (X) == PLUS \
1349 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1350 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1352 /* Local to this file. */
1353 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1354 since more than one instruction will be required. */
1355 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1356 (GET_CODE (X) == LO_SUM \
1357 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
1358 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1359 && CONSTANT_P (XEXP (X, 1)))
1361 /* Local to this file. */
1362 /* Is this a load and increment operation. */
1363 #define LOAD_POSTINC_P(MODE, X) \
1364 (((MODE) == SImode || (MODE) == SFmode) \
1365 && GET_CODE (X) == POST_INC \
1366 && GET_CODE (XEXP (X, 0)) == REG \
1367 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1369 /* Local to this file. */
1370 /* Is this an increment/decrement and store operation. */
1371 #define STORE_PREINC_PREDEC_P(MODE, X) \
1372 (((MODE) == SImode || (MODE) == SFmode) \
1373 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1374 && GET_CODE (XEXP (X, 0)) == REG \
1375 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1377 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1378 { if (RTX_OK_FOR_BASE_P (X)) \
1380 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1382 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1384 if (LOAD_POSTINC_P ((MODE), (X))) \
1386 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1390 /* Try machine-dependent ways of modifying an illegitimate address
1391 to be legitimate. If we find one, return the new, valid address.
1392 This macro is used in only one place: `memory_address' in explow.c.
1394 OLDX is the address as it was before break_out_memory_refs was called.
1395 In some cases it is useful to look at this to decide what needs to be done.
1397 MODE and WIN are passed so that this macro can use
1398 GO_IF_LEGITIMATE_ADDRESS.
1400 It is always safe for this macro to do nothing. It exists to recognize
1401 opportunities to optimize the output.
1403 ??? Is there anything useful we can do here for the M32R? */
1405 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1407 /* Go to LABEL if ADDR (a legitimate address expression)
1408 has an effect that depends on the machine mode it is used for. */
1409 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1411 if (GET_CODE (ADDR) == PRE_DEC \
1412 || GET_CODE (ADDR) == PRE_INC \
1413 || GET_CODE (ADDR) == POST_INC \
1414 || GET_CODE (ADDR) == LO_SUM) \
1418 /* Condition code usage. */
1420 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
1421 floating point inequality comparison. */
1422 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1426 /* Compute extra cost of moving data between one register class
1428 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1430 /* Compute the cost of moving data between registers and memory. */
1431 /* Memory is 3 times as expensive as registers.
1432 ??? Is that the right way to look at it? */
1433 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1434 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1436 /* The cost of a branch insn. */
1437 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1438 while (a < N && a). Branches aren't that expensive on the M32R so
1439 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1440 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1442 /* Nonzero if access to memory by bytes is slow and undesirable.
1443 For RISC chips, it means that access to memory by bytes is no
1444 better than access by words when possible, so grab a whole word
1445 and maybe make use of that. */
1446 #define SLOW_BYTE_ACCESS 1
1448 /* Define this macro if it is as good or better to call a constant
1449 function address than to call an address kept in a register. */
1450 #define NO_FUNCTION_CSE
1452 /* Define this macro if it is as good or better for a function to call
1453 itself with an explicit address than to call an address kept in a
1455 #define NO_RECURSIVE_FUNCTION_CSE
1457 /* When the `length' insn attribute is used, this macro specifies the
1458 value to be assigned to the address of the first insn in a
1459 function. If not specified, 0 is used. */
1460 #define FIRST_INSN_ADDRESS m32r_first_insn_address ()
1463 /* Section selection. */
1465 #define TEXT_SECTION_ASM_OP "\t.section .text"
1466 #define DATA_SECTION_ASM_OP "\t.section .data"
1467 #define BSS_SECTION_ASM_OP "\t.section .bss"
1469 /* Define this macro if jump tables (for tablejump insns) should be
1470 output in the text section, along with the assembler instructions.
1471 Otherwise, the readonly data section is used.
1472 This macro is irrelevant if there is no separate readonly data section. */
1473 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
1477 /* The register number of the register used to address a table of static
1478 data addresses in memory. In some cases this register is defined by a
1479 processor's ``application binary interface'' (ABI). When this macro
1480 is defined, RTL is generated for this register once, as with the stack
1481 pointer and frame pointer registers. If this macro is not defined, it
1482 is up to the machine-dependent files to allocate such a register (if
1484 /*#define PIC_OFFSET_TABLE_REGNUM 12*/
1486 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1487 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1489 /* This register is call-saved on the M32R. */
1490 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1492 /* By generating position-independent code, when two different programs (A
1493 and B) share a common library (libC.a), the text of the library can be
1494 shared whether or not the library is linked at the same address for both
1495 programs. In some of these environments, position-independent code
1496 requires not only the use of different addressing modes, but also
1497 special code to enable the use of these addressing modes.
1499 The FINALIZE_PIC macro serves as a hook to emit these special
1500 codes once the function is being compiled into assembly code, but not
1501 before. (It is not done before, because in the case of compiling an
1502 inline function, it would lead to multiple PIC prologues being
1503 included in functions which used inline functions and were compiled to
1504 assembly language.) */
1506 /*#define FINALIZE_PIC m32r_finalize_pic ()*/
1508 /* A C expression that is nonzero if X is a legitimate immediate
1509 operand on the target machine when generating position independent code.
1510 You can assume that X satisfies CONSTANT_P, so you need not
1511 check this. You can also assume `flag_pic' is true, so you need not
1512 check it either. You need not define this macro if all constants
1513 (including SYMBOL_REF) can be immediate operands when generating
1514 position independent code. */
1515 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
1517 /* Control the assembler format that we output. */
1519 /* A C string constant describing how to begin a comment in the target
1520 assembler language. The compiler assumes that the comment will
1521 end at the end of the line. */
1522 #define ASM_COMMENT_START ";"
1524 /* Output to assembler file text saying following lines
1525 may contain character constants, extra white space, comments, etc. */
1526 #define ASM_APP_ON ""
1528 /* Output to assembler file text saying following lines
1529 no longer contain unusual constructs. */
1530 #define ASM_APP_OFF ""
1532 /* Globalizing directive for a label. */
1533 #define GLOBAL_ASM_OP "\t.global\t"
1535 /* If -Os, don't force line number labels to begin at the beginning of
1536 the word; we still want the assembler to try to put things in parallel,
1537 should that be possible.
1538 For m32r/d, instructions are never in parallel (other than with a nop)
1539 and the simulator and stub both handle a breakpoint in the middle of
1540 a word so don't ever force line number labels to begin at the beginning
1543 #undef ASM_OUTPUT_SOURCE_LINE
1544 #define ASM_OUTPUT_SOURCE_LINE(file, line, counter) \
1547 fprintf (file, ".stabn 68,0,%d,.LM%d-", \
1550 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1551 fprintf (file, (optimize_size || TARGET_M32R) \
1552 ? "\n\t.debugsym .LM%d\n" \
1558 /* How to refer to registers in assembler output.
1559 This sequence is indexed by compiler's hard-register-number (see above). */
1560 #ifndef SUBTARGET_REGISTER_NAMES
1561 #define SUBTARGET_REGISTER_NAMES
1564 #define REGISTER_NAMES \
1566 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1567 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1568 "ap", "cbit", "a0" \
1569 SUBTARGET_REGISTER_NAMES \
1572 /* If defined, a C initializer for an array of structures containing
1573 a name and a register number. This macro defines additional names
1574 for hard registers, thus allowing the `asm' option in declarations
1575 to refer to registers using alternate names. */
1576 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1577 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1580 #define ADDITIONAL_REGISTER_NAMES \
1582 /*{ "gp", GP_REGNUM },*/ \
1583 { "r13", FRAME_POINTER_REGNUM }, \
1584 { "r14", RETURN_ADDR_REGNUM }, \
1585 { "r15", STACK_POINTER_REGNUM }, \
1586 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1589 /* A C expression which evaluates to true if CODE is a valid
1590 punctuation character for use in the `PRINT_OPERAND' macro. */
1591 extern char m32r_punct_chars[256];
1592 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1593 m32r_punct_chars[(unsigned char) (CHAR)]
1595 /* Print operand X (an rtx) in assembler syntax to file FILE.
1596 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1597 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1598 #define PRINT_OPERAND(FILE, X, CODE) \
1599 m32r_print_operand (FILE, X, CODE)
1601 /* A C compound statement to output to stdio stream STREAM the
1602 assembler syntax for an instruction operand that is a memory
1603 reference whose address is ADDR. ADDR is an RTL expression. */
1604 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1605 m32r_print_operand_address (FILE, ADDR)
1607 /* If defined, C string expressions to be used for the `%R', `%L',
1608 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1609 are useful when a single `md' file must support multiple assembler
1610 formats. In that case, the various `tm.h' files can define these
1611 macros differently. */
1612 #define REGISTER_PREFIX ""
1613 #define LOCAL_LABEL_PREFIX ".L"
1614 #define USER_LABEL_PREFIX ""
1615 #define IMMEDIATE_PREFIX "#"
1617 /* This is how to output an element of a case-vector that is absolute. */
1618 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1622 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1623 fprintf (FILE, "\t.word\t"); \
1624 assemble_name (FILE, label); \
1625 fprintf (FILE, "\n"); \
1629 /* This is how to output an element of a case-vector that is relative. */
1630 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1634 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1635 fprintf (FILE, "\t.word\t"); \
1636 assemble_name (FILE, label); \
1637 fprintf (FILE, "-"); \
1638 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1639 assemble_name (FILE, label); \
1640 fprintf (FILE, ")\n"); \
1644 /* The desired alignment for the location counter at the beginning
1646 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1647 if -malign-loops. */
1648 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1650 /* Define this to be the maximum number of insns to move around when moving
1651 a loop test from the top of a loop to the bottom
1652 and seeing whether to duplicate it. The default is thirty.
1654 Loop unrolling currently doesn't like this optimization, so
1655 disable doing if we are unrolling loops and saving space. */
1656 #define LOOP_TEST_THRESHOLD (optimize_size \
1657 && !flag_unroll_loops \
1658 && !flag_unroll_all_loops ? 2 : 30)
1660 /* This is how to output an assembler line
1661 that says to advance the location counter
1662 to a multiple of 2**LOG bytes. */
1663 /* .balign is used to avoid confusion. */
1664 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1668 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1672 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1673 separate, explicit argument. If you define this macro, it is used in
1674 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1675 handling the required alignment of the variable. The alignment is
1676 specified as the number of bits. */
1678 #define SCOMMON_ASM_OP "\t.scomm\t"
1680 #undef ASM_OUTPUT_ALIGNED_COMMON
1681 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1684 if (! TARGET_SDATA_NONE \
1685 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1686 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1688 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1689 assemble_name ((FILE), (NAME)); \
1690 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
1694 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1695 separate, explicit argument. If you define this macro, it is used in
1696 place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1697 handling the required alignment of the variable. The alignment is
1698 specified as the number of bits.
1700 For the M32R we need sbss support. */
1702 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1705 ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \
1709 /* Debugging information. */
1711 /* Generate DBX and DWARF debugging information. */
1712 #define DBX_DEBUGGING_INFO 1
1713 #define DWARF_DEBUGGING_INFO 1
1714 #define DWARF2_DEBUGGING_INFO 1
1716 /* Prefer STABS (for now). */
1717 #undef PREFERRED_DEBUGGING_TYPE
1718 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
1720 /* Turn off splitting of long stabs. */
1721 #define DBX_CONTIN_LENGTH 0
1723 /* Miscellaneous. */
1725 /* Specify the machine mode that this machine uses
1726 for the index in the tablejump instruction. */
1727 #define CASE_VECTOR_MODE Pmode
1729 /* Define as C expression which evaluates to nonzero if the tablejump
1730 instruction expects the table to contain offsets from the address of the
1732 Do not define this if the table should contain absolute addresses. */
1733 /* It's not clear what PIC will look like or whether we want to use -fpic
1734 for the embedded form currently being talked about. For now require -fpic
1735 to get pc relative switch tables. */
1736 /*#define CASE_VECTOR_PC_RELATIVE 1 */
1738 /* Define if operations between registers always perform the operation
1739 on the full register even if a narrower mode is specified. */
1740 #define WORD_REGISTER_OPERATIONS
1742 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1743 will either zero-extend or sign-extend. The value of this macro should
1744 be the code that says which one of the two operations is implicitly
1745 done, NIL if none. */
1746 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1748 /* Max number of bytes we can move from memory to memory
1749 in one reasonably fast instruction. */
1752 /* Define this to be nonzero if shift instructions ignore all but the low-order
1754 #define SHIFT_COUNT_TRUNCATED 1
1756 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1757 is done just by pretending it is already truncated. */
1758 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1760 /* Specify the machine mode that pointers have.
1761 After generation of rtl, the compiler makes no further distinction
1762 between pointers and any other objects of this machine mode. */
1763 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
1764 it's own problems (you have to add extendpsisi2 and truncsipsi2).
1766 #define Pmode SImode
1768 /* A function address in a call instruction. */
1769 #define FUNCTION_MODE SImode
1771 /* Define the information needed to generate branch and scc insns. This is
1772 stored from the compare operation. Note that we can't use "rtx" here
1773 since it hasn't been defined! */
1774 extern struct rtx_def * m32r_compare_op0;
1775 extern struct rtx_def * m32r_compare_op1;
1777 /* M32R function types. */
1778 enum m32r_function_type
1780 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
1783 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
1785 /* Define this if you have defined special-purpose predicates in the
1786 file `MACHINE.c'. This macro is called within an initializer of an
1787 array of structures. The first field in the structure is the name
1788 of a predicate and the second field is an array of rtl codes. For
1789 each predicate, list all rtl codes that can be in expressions
1790 matched by the predicate. The list should have a trailing comma. */
1792 #define PREDICATE_CODES \
1793 { "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \
1794 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
1795 { "carry_compare_operand", { EQ, NE }}, \
1796 { "eqne_comparison_operator", { EQ, NE }}, \
1797 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \
1798 { "move_dest_operand", { REG, SUBREG, MEM }}, \
1799 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \
1800 CONST_DOUBLE, LABEL_REF, CONST, \
1802 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \
1804 { "two_insn_const_operand", { CONST_INT }}, \
1805 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
1806 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
1807 { "int8_operand", { CONST_INT }}, \
1808 { "uint16_operand", { CONST_INT }}, \
1809 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \
1810 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \
1811 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \
1812 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \
1813 { "cmp_int16_operand", { CONST_INT }}, \
1814 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
1815 { "extend_operand", { REG, SUBREG, MEM }}, \
1816 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
1817 { "m32r_block_immediate_operand",{ CONST_INT }}, \
1818 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
1819 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }},