1 /* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #undef SWITCH_TAKES_ARG
27 #undef WORD_SWITCH_TAKES_ARG
28 #undef HANDLE_SYSV_PRAGMA
32 #undef WCHAR_TYPE_SIZE
34 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
41 #undef SUBTARGET_SWITCHES
44 /* M32R/X overrides. */
45 /* Print subsidiary information on the compiler version in use. */
46 #define TARGET_VERSION fprintf (stderr, " (m32r/x)");
48 /* Additional flags for the preprocessor. */
49 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
51 /* Assembler switches. */
52 #define ASM_CPU_SPEC \
53 "%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
55 /* Use m32rx specific crt0/crtinit/crtfini files. */
56 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
57 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
59 /* Extra machine dependent switches. */
60 #define SUBTARGET_SWITCHES \
61 { "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
62 { "32r", -TARGET_M32RX_MASK, "" },
64 /* Define this macro as a C expression for the initializer of an array of
65 strings to tell the driver program which options are defaults for this
66 target and thus do not need to be handled specially when using
67 `MULTILIB_OPTIONS'. */
68 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
70 /* Number of additional registers the subtarget defines. */
71 #define SUBTARGET_NUM_REGISTERS 1
73 /* 1 for registers that cannot be allocated. */
74 #define SUBTARGET_FIXED_REGISTERS , 1
76 /* 1 for registers that are not available across function calls. */
77 #define SUBTARGET_CALL_USED_REGISTERS , 1
79 /* Order to allocate model specific registers. */
80 #define SUBTARGET_REG_ALLOC_ORDER , 19
82 /* Registers which are accumulators. */
83 #define SUBTARGET_REG_CLASS_ACCUM 0x80000
85 /* All registers added. */
86 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
88 /* Additional accumulator registers. */
89 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
91 /* Define additional register names. */
92 #define SUBTARGET_REGISTER_NAMES , "a1"
93 /* end M32R/X overrides. */
95 /* Print subsidiary information on the compiler version in use. */
96 #ifndef TARGET_VERSION
97 #define TARGET_VERSION fprintf (stderr, " (m32r)")
100 /* Switch Recognition by gcc.c. Add -G xx support */
102 #undef SWITCH_TAKES_ARG
103 #define SWITCH_TAKES_ARG(CHAR) \
104 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
106 /* Names to predefine in the preprocessor for this target machine. */
107 /* __M32R__ is defined by the existing compiler so we use that. */
108 #define CPP_PREDEFINES "-Acpu=m32r -Amachine=m32r -D__M32R__"
110 /* This macro defines names of additional specifications to put in the specs
111 that can be used in various specifications like CC1_SPEC. Its definition
112 is an initializer with a subgrouping for each command option.
114 Each subgrouping contains a string constant, that defines the
115 specification name, and a string constant that used by the GNU CC driver
118 Do not define this macro if it does not need to do anything. */
120 #ifndef SUBTARGET_EXTRA_SPECS
121 #define SUBTARGET_EXTRA_SPECS
125 #define ASM_CPU_SPEC ""
129 #define CPP_CPU_SPEC ""
133 #define CC1_CPU_SPEC ""
136 #ifndef LINK_CPU_SPEC
137 #define LINK_CPU_SPEC ""
140 #ifndef STARTFILE_CPU_SPEC
141 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
144 #ifndef ENDFILE_CPU_SPEC
145 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
149 #if 0 /* not supported yet */
150 #define RELAX_SPEC "%{mrelax:-relax}"
152 #define RELAX_SPEC ""
156 #define EXTRA_SPECS \
157 { "asm_cpu", ASM_CPU_SPEC }, \
158 { "cpp_cpu", CPP_CPU_SPEC }, \
159 { "cc1_cpu", CC1_CPU_SPEC }, \
160 { "link_cpu", LINK_CPU_SPEC }, \
161 { "startfile_cpu", STARTFILE_CPU_SPEC }, \
162 { "endfile_cpu", ENDFILE_CPU_SPEC }, \
163 { "relax", RELAX_SPEC }, \
164 SUBTARGET_EXTRA_SPECS
166 #define CC1_SPEC "%{G*} %(cc1_cpu)"
168 /* Options to pass on to the assembler. */
170 #define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
172 #undef ASM_FINAL_SPEC
174 #define LINK_SPEC "%{v} %(link_cpu) %(relax)"
176 #undef STARTFILE_SPEC
177 #define STARTFILE_SPEC "%(startfile_cpu)"
180 #define ENDFILE_SPEC "%(endfile_cpu)"
184 /* Run-time compilation parameters selecting different hardware subsets. */
186 extern int target_flags;
188 /* If non-zero, tell the linker to do relaxing.
189 We don't do anything with the option, other than recognize it.
190 LINK_SPEC handles passing -relax to the linker.
191 This can cause incorrect debugging information as line numbers may
192 turn out wrong. This shouldn't be specified unless accompanied with -O2
193 [where the user expects debugging information to be less accurate]. */
194 #define TARGET_RELAX_MASK (1 << 0)
196 /* For miscellaneous debugging purposes. */
197 #define TARGET_DEBUG_MASK (1 << 1)
198 #define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
200 /* Align loops to 32 byte boundaries (cache line size). */
201 /* ??? This option is experimental and is not documented. */
202 #define TARGET_ALIGN_LOOPS_MASK (1 << 2)
203 #define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
205 /* Change issue rate. */
206 #define TARGET_LOW_ISSUE_RATE_MASK (1 << 3)
207 #define TARGET_LOW_ISSUE_RATE (target_flags & TARGET_LOW_ISSUE_RATE_MASK)
209 /* Change branch cost */
210 #define TARGET_BRANCH_COST_MASK (1 << 4)
211 #define TARGET_BRANCH_COST (target_flags & TARGET_BRANCH_COST_MASK)
213 /* Target machine to compile for. */
214 #define TARGET_M32R 1
216 /* Support extended instruction set. */
217 #define TARGET_M32RX_MASK (1 << 5)
218 #define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
220 #define TARGET_M32R (! TARGET_M32RX)
222 /* Macro to define tables used to set the flags.
223 This is a list in braces of pairs in braces,
224 each pair being { "NAME", VALUE }
225 where VALUE is the bits to set or minus the bits to clear.
226 An empty string NAME is used to identify the default VALUE. */
228 #ifndef SUBTARGET_SWITCHES
229 #define SUBTARGET_SWITCHES
232 #ifndef TARGET_DEFAULT
233 #define TARGET_DEFAULT 0
236 #define TARGET_SWITCHES \
238 /* { "relax", TARGET_RELAX_MASK, "" }, \
239 { "no-relax", -TARGET_RELAX_MASK, "" },*/ \
240 { "debug", TARGET_DEBUG_MASK, \
241 N_("Display compile time statistics") }, \
242 { "align-loops", TARGET_ALIGN_LOOPS_MASK, \
243 N_("Align all loops to 32 byte boundary") }, \
244 { "no-align-loops", -TARGET_ALIGN_LOOPS_MASK, "" }, \
245 { "issue-rate=1", TARGET_LOW_ISSUE_RATE_MASK, \
246 N_("Only issue one instruction per cycle") }, \
247 { "issue-rate=2", -TARGET_LOW_ISSUE_RATE_MASK, "" }, \
248 { "branch-cost=1", TARGET_BRANCH_COST_MASK, \
249 N_("Prefer branches over conditional execution") }, \
250 { "branch-cost=2", -TARGET_BRANCH_COST_MASK, "" }, \
252 { "", TARGET_DEFAULT, "" } \
255 extern const char * m32r_model_string;
256 extern const char * m32r_sdata_string;
258 #ifndef SUBTARGET_OPTIONS
259 #define SUBTARGET_OPTIONS
262 #define TARGET_OPTIONS \
264 { "model=", & m32r_model_string, \
265 N_("Code size: small, medium or large") }, \
266 { "sdata=", & m32r_sdata_string, \
267 N_("Small data area: none, sdata, use") } \
273 Code models are used to select between two choices of two separate
274 possibilities (address space size, call insn to use):
276 small: addresses use 24 bits, use bl to make calls
277 medium: addresses use 32 bits, use bl to make calls (*1)
278 large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
280 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
281 using this one doesn't make much sense.
283 (*1) The linker may eventually be able to relax seth/add3 -> ld24.
284 (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
286 Internally these are recorded as TARGET_ADDR{24,32} and
289 The __model__ attribute can be used to select the code model to use when
290 accessing particular objects. */
292 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
294 extern enum m32r_model m32r_model;
295 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
296 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
297 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
298 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
299 #define TARGET_ADDR32 (! TARGET_ADDR24)
300 #define TARGET_CALL26 (! TARGET_CALL32)
301 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
303 /* The default is the small model. */
304 #ifndef M32R_MODEL_DEFAULT
305 #define M32R_MODEL_DEFAULT "small"
310 The SDA consists of sections .sdata, .sbss, and .scommon.
311 .scommon isn't a real section, symbols in it have their section index
312 set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
314 Two switches control the SDA:
316 -G NNN - specifies the maximum size of variable to go in the SDA
318 -msdata=foo - specifies how such variables are handled
320 -msdata=none - small data area is disabled
322 -msdata=sdata - small data goes in the SDA, special code isn't
323 generated to use it, and special relocs aren't
326 -msdata=use - small data goes in the SDA, special code is generated
327 to use the SDA and special relocs are generated
329 The SDA is not multilib'd, it isn't necessary.
330 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
331 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
332 -msdata=use will successfully link with them (references in header files
333 will cause the compiler to emit code that refers to library objects in
334 .data). ??? There can be a problem if the user passes a -G value greater
335 than the default and a library object in a header file is that size.
336 The default is 8 so this should be rare - if it occurs the user
337 is required to rebuild the libraries or use a smaller value for -G.
340 /* Maximum size of variables that go in .sdata/.sbss.
341 The -msdata=foo switch also controls how small variables are handled. */
342 #ifndef SDATA_DEFAULT_SIZE
343 #define SDATA_DEFAULT_SIZE 8
346 extern int g_switch_value; /* value of the -G xx switch */
347 extern int g_switch_set; /* whether -G xx was passed. */
349 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
351 extern enum m32r_sdata m32r_sdata;
352 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
353 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
354 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
356 /* Default is to disable the SDA
357 [for upward compatibility with previous toolchains]. */
358 #ifndef M32R_SDATA_DEFAULT
359 #define M32R_SDATA_DEFAULT "none"
362 /* Define this macro as a C expression for the initializer of an array of
363 strings to tell the driver program which options are defaults for this
364 target and thus do not need to be handled specially when using
365 `MULTILIB_OPTIONS'. */
366 #ifndef SUBTARGET_MULTILIB_DEFAULTS
367 #define SUBTARGET_MULTILIB_DEFAULTS
370 #ifndef MULTILIB_DEFAULTS
371 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
374 /* Sometimes certain combinations of command options do not make
375 sense on a particular target machine. You can define a macro
376 `OVERRIDE_OPTIONS' to take account of this. This macro, if
377 defined, is executed once just after all the command options have
380 Don't use this macro to turn on various extra optimizations for
381 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
383 #ifndef SUBTARGET_OVERRIDE_OPTIONS
384 #define SUBTARGET_OVERRIDE_OPTIONS
387 #define OVERRIDE_OPTIONS \
390 /* These need to be done at start up. \
391 It's convenient to do them here. */ \
393 SUBTARGET_OVERRIDE_OPTIONS \
397 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS
398 #define SUBTARGET_OPTIMIZATION_OPTIONS
401 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
405 flag_regmove = TRUE; \
409 flag_omit_frame_pointer = TRUE; \
410 flag_strength_reduce = FALSE; \
413 SUBTARGET_OPTIMIZATION_OPTIONS \
417 /* Define this macro if debugging can be performed even without a
418 frame pointer. If this macro is defined, GNU CC will turn on the
419 `-fomit-frame-pointer' option whenever `-O' is specified. */
420 #define CAN_DEBUG_WITHOUT_FP
422 /* Target machine storage layout. */
424 /* Define to use software floating point emulator for REAL_ARITHMETIC and
425 decimal <-> binary conversion. */
426 #define REAL_ARITHMETIC
428 /* Define this if most significant bit is lowest numbered
429 in instructions that operate on numbered bit-fields. */
430 #define BITS_BIG_ENDIAN 1
432 /* Define this if most significant byte of a word is the lowest numbered. */
433 #define BYTES_BIG_ENDIAN 1
435 /* Define this if most significant word of a multiword number is the lowest
437 #define WORDS_BIG_ENDIAN 1
439 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must
440 be a constant value with the same meaning as WORDS_BIG_ENDIAN,
441 which will be used only when compiling libgcc2.c. Typically the
442 value will be set based on preprocessor defines. */
443 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
445 /* Width in bits of a "word", which is the contents of a machine register.
446 Note that this is not necessarily the width of data type `int';
447 if using 16-bit ints on a 68000, this would still be 32.
448 But on a machine with 16-bit registers, this would be 16. */
449 #define BITS_PER_WORD 32
451 /* Width of a word, in units (bytes). */
452 #define UNITS_PER_WORD 4
454 /* Define this macro if it is advisable to hold scalars in registers
455 in a wider mode than that declared by the program. In such cases,
456 the value is constrained to be within the bounds of the declared
457 type, but kept valid in the wider mode. The signedness of the
458 extension may differ from that of the type. */
459 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
460 if (GET_MODE_CLASS (MODE) == MODE_INT \
461 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
466 /* Define this macro if the promotion described by `PROMOTE_MODE'
467 should also be done for outgoing function arguments. */
468 /*#define PROMOTE_FUNCTION_ARGS*/
470 /* Likewise, if the function return value is promoted.
471 If defined, FUNCTION_VALUE must perform the same promotions done by
473 /*#define PROMOTE_FUNCTION_RETURN*/
475 /* Width in bits of a pointer.
476 See also the macro `Pmode' defined below. */
477 #define POINTER_SIZE 32
479 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
480 #define PARM_BOUNDARY 32
482 /* Boundary (in *bits*) on which stack pointer should be aligned. */
483 #define STACK_BOUNDARY 32
485 /* ALIGN FRAMES on word boundaries */
486 #define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
488 /* Allocation boundary (in *bits*) for the code of a function. */
489 #define FUNCTION_BOUNDARY 32
491 /* Alignment of field after `int : 0' in a structure. */
492 #define EMPTY_FIELD_BOUNDARY 32
494 /* Every structure's size must be a multiple of this. */
495 #define STRUCTURE_SIZE_BOUNDARY 8
497 /* A bitfield declared as `int' forces `int' alignment for the struct. */
498 #define PCC_BITFIELD_TYPE_MATTERS 1
500 /* No data type wants to be aligned rounder than this. */
501 #define BIGGEST_ALIGNMENT 32
503 /* The best alignment to use in cases where we have a choice. */
504 #define FASTEST_ALIGNMENT 32
506 /* Make strings word-aligned so strcpy from constants will be faster. */
507 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
508 ((TREE_CODE (EXP) == STRING_CST \
509 && (ALIGN) < FASTEST_ALIGNMENT) \
510 ? FASTEST_ALIGNMENT : (ALIGN))
512 /* Make arrays of chars word-aligned for the same reasons. */
513 #define DATA_ALIGNMENT(TYPE, ALIGN) \
514 (TREE_CODE (TYPE) == ARRAY_TYPE \
515 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
516 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
518 /* Set this nonzero if move instructions will actually fail to work
519 when given unaligned data. */
520 #define STRICT_ALIGNMENT 1
522 /* Layout of source language data types. */
524 #define SHORT_TYPE_SIZE 16
525 #define INT_TYPE_SIZE 32
526 #define LONG_TYPE_SIZE 32
527 #define LONG_LONG_TYPE_SIZE 64
528 #define FLOAT_TYPE_SIZE 32
529 #define DOUBLE_TYPE_SIZE 64
530 #define LONG_DOUBLE_TYPE_SIZE 64
532 /* Define this as 1 if `char' should by default be signed; else as 0. */
533 #define DEFAULT_SIGNED_CHAR 1
535 #define SIZE_TYPE "long unsigned int"
536 #define PTRDIFF_TYPE "long int"
537 #define WCHAR_TYPE "short unsigned int"
538 #define WCHAR_TYPE_SIZE 16
540 /* Standard register usage. */
542 /* Number of actual hardware registers.
543 The hardware registers are assigned numbers for the compiler
544 from 0 to just below FIRST_PSEUDO_REGISTER.
545 All registers that the compiler knows about must be given numbers,
546 even those that are not normally considered general registers. */
548 #define M32R_NUM_REGISTERS 19
550 #ifndef SUBTARGET_NUM_REGISTERS
551 #define SUBTARGET_NUM_REGISTERS 0
554 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
556 /* 1 for registers that have pervasive standard uses
557 and are not available for the register allocator.
559 0-3 - arguments/results
560 4-5 - call used [4 is used as a tmp during prologue/epilogue generation]
562 7 - call used, static chain pointer
564 12 - call saved [reserved for global pointer]
566 14 - subroutine link register
571 19 - accumulator 1 in the m32r/x
572 By default, the extension registers are not available. */
574 #ifndef SUBTARGET_FIXED_REGISTERS
575 #define SUBTARGET_FIXED_REGISTERS
578 #define FIXED_REGISTERS \
580 0, 0, 0, 0, 0, 0, 0, 0, \
581 0, 0, 0, 0, 0, 0, 0, 1, \
583 SUBTARGET_FIXED_REGISTERS \
586 /* 1 for registers not available across function calls.
587 These must include the FIXED_REGISTERS and also any
588 registers that can be used without being saved.
589 The latter must include the registers where values are returned
590 and the register where structure-value addresses are passed.
591 Aside from that, you can include as many other registers as you like. */
593 #ifndef SUBTARGET_CALL_USED_REGISTERS
594 #define SUBTARGET_CALL_USED_REGISTERS
597 #define CALL_USED_REGISTERS \
599 1, 1, 1, 1, 1, 1, 1, 1, \
600 0, 0, 0, 0, 0, 0, 1, 1, \
602 SUBTARGET_CALL_USED_REGISTERS \
605 /* Zero or more C statements that may conditionally modify two variables
606 `fixed_regs' and `call_used_regs' (both of type `char []') after they
607 have been initialized from the two preceding macros.
609 This is necessary in case the fixed or call-clobbered registers depend
612 You need not define this macro if it has no work to do. */
614 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
615 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
618 /* If defined, an initializer for a vector of integers, containing the
619 numbers of hard registers in the order in which GNU CC should
620 prefer to use them (from most preferred to least). */
622 #ifndef SUBTARGET_REG_ALLOC_ORDER
623 #define SUBTARGET_REG_ALLOC_ORDER
626 #if 1 /* better for int code */
627 #define REG_ALLOC_ORDER \
629 4, 5, 6, 7, 2, 3, 8, 9, 10, \
630 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \
631 SUBTARGET_REG_ALLOC_ORDER \
634 #else /* better for fp code at expense of int code */
635 #define REG_ALLOC_ORDER \
637 0, 1, 2, 3, 4, 5, 6, 7, 8, \
638 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \
639 SUBTARGET_REG_ALLOC_ORDER \
643 /* Return number of consecutive hard regs needed starting at reg REGNO
644 to hold something of mode MODE.
645 This is ordinarily the length in words of a value of mode MODE
646 but can be less for certain modes in special long registers. */
647 #define HARD_REGNO_NREGS(REGNO, MODE) \
648 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
650 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
651 extern unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
652 extern unsigned int m32r_mode_class[];
653 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
654 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
656 /* A C expression that is nonzero if it is desirable to choose
657 register allocation so as to avoid move instructions between a
658 value of mode MODE1 and a value of mode MODE2.
660 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
661 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
662 MODE2)' must be zero. */
664 /* Tie QI/HI/SI modes together. */
665 #define MODES_TIEABLE_P(MODE1, MODE2) \
666 (GET_MODE_CLASS (MODE1) == MODE_INT \
667 && GET_MODE_CLASS (MODE2) == MODE_INT \
668 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
669 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
671 /* Register classes and constants. */
673 /* Define the classes of registers for register constraints in the
674 machine description. Also define ranges of constants.
676 One of the classes must always be named ALL_REGS and include all hard regs.
677 If there is more than one class, another class must be named NO_REGS
678 and contain no registers.
680 The name GENERAL_REGS must be the name of a class (or an alias for
681 another name such as ALL_REGS). This is the class of registers
682 that is allowed by "g" or "r" in a register constraint.
683 Also, registers outside this class are allocated only when
684 instructions express preferences for them.
686 The classes must be numbered in nondecreasing order; that is,
687 a larger-numbered class must never be contained completely
688 in a smaller-numbered class.
690 For any two classes, it is very desirable that there be another
691 class that represents their union.
693 It is important that any condition codes have class NO_REGS.
694 See `register_operand'. */
698 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
701 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
703 /* Give names of register classes as strings for dump file. */
704 #define REG_CLASS_NAMES \
705 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
707 /* Define which registers fit in which classes.
708 This is an initializer for a vector of HARD_REG_SET
709 of length N_REG_CLASSES. */
711 #ifndef SUBTARGET_REG_CLASS_CARRY
712 #define SUBTARGET_REG_CLASS_CARRY 0
715 #ifndef SUBTARGET_REG_CLASS_ACCUM
716 #define SUBTARGET_REG_CLASS_ACCUM 0
719 #ifndef SUBTARGET_REG_CLASS_GENERAL
720 #define SUBTARGET_REG_CLASS_GENERAL 0
723 #ifndef SUBTARGET_REG_CLASS_ALL
724 #define SUBTARGET_REG_CLASS_ALL 0
727 #define REG_CLASS_CONTENTS \
730 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \
731 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \
732 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \
733 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \
736 /* The same information, inverted:
737 Return the class number of the smallest class containing
738 reg number REGNO. This could be a conditional expression
739 or could index an array. */
740 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
741 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
743 /* The class value for index registers, and the one for base regs. */
744 #define INDEX_REG_CLASS GENERAL_REGS
745 #define BASE_REG_CLASS GENERAL_REGS
747 #define REG_CLASS_FROM_LETTER(C) \
748 ((C) == 'c' ? CARRY_REG \
749 : (C) == 'a' ? ACCUM_REGS \
752 /* These assume that REGNO is a hard or pseudo reg number.
753 They give nonzero only if REGNO is a hard reg of the suitable class
754 or a pseudo reg currently allocated to a suitable hard reg.
755 Since they use reg_renumber, they are safe only once reg_renumber
756 has been allocated, which happens in local-alloc.c. */
757 #define REGNO_OK_FOR_BASE_P(REGNO) \
758 ((REGNO) < FIRST_PSEUDO_REGISTER \
759 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \
760 : GPR_P (reg_renumber[REGNO]))
761 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
763 /* Given an rtx X being reloaded into a reg required to be
764 in class CLASS, return the class of reg to actually use.
765 In general this is just CLASS; but on some machines
766 in some cases it is preferable to use a more restrictive class. */
767 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
770 /* Return the maximum number of consecutive registers
771 needed to represent mode MODE in a register of class CLASS. */
772 #define CLASS_MAX_NREGS(CLASS, MODE) \
773 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
775 /* The letters I, J, K, L, M, N, O, P in a register constraint string
776 can be used to stand for particular ranges of immediate operands.
777 This macro defines what the ranges are.
778 C is the letter, and VALUE is a constant value.
779 Return 1 if VALUE is in the range specified by C. */
780 /* 'I' is used for 8 bit signed immediates.
781 'J' is used for 16 bit signed immediates.
782 'K' is used for 16 bit unsigned immediates.
783 'L' is used for 16 bit immediates left shifted by 16 (sign ???).
784 'M' is used for 24 bit unsigned immediates.
785 'N' is used for any 32 bit non-symbolic value.
786 'O' is used for 5 bit unsigned immediates (shift count).
787 'P' is used for 16 bit signed immediates for compares
788 (values in the range -32767 to +32768). */
790 /* Return true if a value is inside a range. */
791 #define IN_RANGE_P(VALUE, LOW, HIGH) \
792 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \
793 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
795 /* Local to this file. */
796 #define INT8_P(X) ((X) >= -0x80 && (X) <= 0x7f)
797 #define INT16_P(X) ((X) >= -0x8000 && (X) <= 0x7fff)
798 #define CMP_INT16_P(X) ((X) >= -0x7fff && (X) <= 0x8000)
799 #define UPPER16_P(X) (((X) & 0xffff) == 0 \
800 && ((X) >> 16) >= -0x8000 \
801 && ((X) >> 16) <= 0x7fff)
802 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff)
803 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff)
804 #define UINT32_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0xffffffff)
805 #define UINT5_P(X) ((X) >= 0 && (X) < 32)
806 #define INVERTED_SIGNED_8BIT(VAL) ((VAL) >= -127 && (VAL) <= 128)
808 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
809 ((C) == 'I' ? INT8_P (VALUE) \
810 : (C) == 'J' ? INT16_P (VALUE) \
811 : (C) == 'K' ? UINT16_P (VALUE) \
812 : (C) == 'L' ? UPPER16_P (VALUE) \
813 : (C) == 'M' ? UINT24_P (VALUE) \
814 : (C) == 'N' ? INVERTED_SIGNED_8BIT (VALUE) \
815 : (C) == 'O' ? UINT5_P (VALUE) \
816 : (C) == 'P' ? CMP_INT16_P (VALUE) \
819 /* Similar, but for floating constants, and defining letters G and H.
820 Here VALUE is the CONST_DOUBLE rtx itself.
821 For the m32r, handle a few constants inline.
822 ??? We needn't treat DI and DF modes differently, but for now we do. */
823 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
824 ((C) == 'G' ? easy_di_const (VALUE) \
825 : (C) == 'H' ? easy_df_const (VALUE) \
828 /* A C expression that defines the optional machine-dependent constraint
829 letters that can be used to segregate specific types of operands,
830 usually memory references, for the target machine. It should return 1 if
831 VALUE corresponds to the operand type represented by the constraint letter
832 C. If C is not defined as an extra constraint, the value returned should
833 be 0 regardless of VALUE. */
834 /* Q is for symbolic addresses loadable with ld24.
835 R is for symbolic addresses when ld24 can't be used.
836 S is for stores with pre {inc,dec}rement
837 T is for indirect of a pointer.
838 U is for loads with post increment. */
840 #define EXTRA_CONSTRAINT(VALUE, C) \
841 ( (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
842 || addr24_operand (VALUE, VOIDmode)) \
843 : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
844 || addr32_operand (VALUE, VOIDmode)) \
845 : (C) == 'S' ? (GET_CODE (VALUE) == MEM \
846 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE), \
848 : (C) == 'T' ? (GET_CODE (VALUE) == MEM \
849 && memreg_operand (VALUE, GET_MODE (VALUE))) \
850 : (C) == 'U' ? (GET_CODE (VALUE) == MEM \
851 && LOAD_POSTINC_P (GET_MODE (VALUE), \
855 /* Stack layout and stack pointer usage. */
857 /* Define this macro if pushing a word onto the stack moves the stack
858 pointer to a smaller address. */
859 #define STACK_GROWS_DOWNWARD
861 /* Define this if the nominal address of the stack frame
862 is at the high-address end of the local variables;
863 that is, each additional local variable allocated
864 goes at a more negative offset from the frame pointer. */
865 /*#define FRAME_GROWS_DOWNWARD*/
867 /* Offset from frame pointer to start allocating local variables at.
868 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
869 first local allocated. Otherwise, it is the offset to the BEGINNING
870 of the first local allocated. */
871 /* The frame pointer points at the same place as the stack pointer, except if
872 alloca has been called. */
873 #define STARTING_FRAME_OFFSET \
874 M32R_STACK_ALIGN (current_function_outgoing_args_size)
876 /* Offset from the stack pointer register to the first location at which
877 outgoing arguments are placed. */
878 #define STACK_POINTER_OFFSET 0
880 /* Offset of first parameter from the argument pointer register value. */
881 #define FIRST_PARM_OFFSET(FNDECL) 0
883 /* A C expression whose value is RTL representing the address in a
884 stack frame where the pointer to the caller's frame is stored.
885 Assume that FRAMEADDR is an RTL expression for the address of the
888 If you don't define this macro, the default is to return the value
889 of FRAMEADDR--that is, the stack frame address is also the address
890 of the stack word that points to the previous frame. */
891 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
893 /* A C expression whose value is RTL representing the value of the
894 return address for the frame COUNT steps up from the current frame.
895 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
896 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
898 /* The current return address is in r14. */
899 #if 0 /* The default value should work. */
900 #define RETURN_ADDR_RTX(COUNT, FRAME) \
902 ? gen_rtx_REG (Pmode, 14) \
903 : copy_to_reg (gen_rtx_MEM (Pmode, \
904 memory_address (Pmode, \
905 plus_constant ((FRAME), \
909 /* Register to use for pushing function arguments. */
910 #define STACK_POINTER_REGNUM 15
912 /* Base register for access to local variables of the function. */
913 #define FRAME_POINTER_REGNUM 13
915 /* Base register for access to arguments of the function. */
916 #define ARG_POINTER_REGNUM 16
918 /* The register number of the return address pointer register, which
919 is used to access the current function's return address from the
920 stack. On some machines, the return address is not at a fixed
921 offset from the frame pointer or stack pointer or argument
922 pointer. This register can be defined to point to the return
923 address on the stack, and then be converted by `ELIMINABLE_REGS'
924 into either the frame pointer or stack pointer.
926 Do not define this macro unless there is no other way to get the
927 return address from the stack. */
929 /* #define RETURN_ADDRESS_POINTER_REGNUM */
931 /* Register in which static-chain is passed to a function. This must
932 not be a register used by the prologue. */
933 #define STATIC_CHAIN_REGNUM 7
935 /* These aren't official macros. */
936 #define PROLOGUE_TMP_REGNUM 4
937 #define RETURN_ADDR_REGNUM 14
938 /* #define GP_REGNUM 12 */
939 #define CARRY_REGNUM 17
940 #define ACCUM_REGNUM 18
941 #define M32R_MAX_INT_REGS 16
943 #ifndef SUBTARGET_GPR_P
944 #define SUBTARGET_GPR_P(REGNO) 0
947 #ifndef SUBTARGET_ACCUM_P
948 #define SUBTARGET_ACCUM_P(REGNO) 0
951 #ifndef SUBTARGET_CARRY_P
952 #define SUBTARGET_CARRY_P(REGNO) 0
955 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
956 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
957 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
959 /* Eliminating the frame and arg pointers. */
961 /* A C expression which is nonzero if a function must have and use a
962 frame pointer. This expression is evaluated in the reload pass.
963 If its value is nonzero the function will have a frame pointer. */
964 #define FRAME_POINTER_REQUIRED current_function_calls_alloca
967 /* C statement to store the difference between the frame pointer
968 and the stack pointer values immediately after the function prologue.
969 If `ELIMINABLE_REGS' is defined, this macro will be not be used and
970 need not be defined. */
971 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
972 ((VAR) = m32r_compute_frame_size (get_frame_size ()))
975 /* If defined, this macro specifies a table of register pairs used to
976 eliminate unneeded registers that point into the stack frame. If
977 it is not defined, the only elimination attempted by the compiler
978 is to replace references to the frame pointer with references to
981 Note that the elimination of the argument pointer with the stack
982 pointer is specified first since that is the preferred elimination. */
984 #define ELIMINABLE_REGS \
985 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
986 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
987 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
989 /* A C expression that returns non-zero if the compiler is allowed to
990 try to replace register number FROM-REG with register number
991 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
992 defined, and will usually be the constant 1, since most of the
993 cases preventing register elimination are things that the compiler
994 already knows about. */
996 #define CAN_ELIMINATE(FROM, TO) \
997 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
998 ? ! frame_pointer_needed \
1001 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1002 specifies the initial difference between the specified pair of
1003 registers. This macro must be defined if `ELIMINABLE_REGS' is
1006 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1008 int size = m32r_compute_frame_size (get_frame_size ()); \
1010 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1012 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1013 (OFFSET) = size - current_function_pretend_args_size; \
1014 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1015 (OFFSET) = size - current_function_pretend_args_size; \
1020 /* Function argument passing. */
1022 /* When a prototype says `char' or `short', really pass an `int'. */
1023 #define PROMOTE_PROTOTYPES 1
1025 /* If defined, the maximum amount of space required for outgoing
1026 arguments will be computed and placed into the variable
1027 `current_function_outgoing_args_size'. No space will be pushed
1028 onto the stack for each call; instead, the function prologue should
1029 increase the stack frame size by this amount. */
1030 #define ACCUMULATE_OUTGOING_ARGS 1
1032 /* Define this macro if functions should assume that stack space has
1033 been allocated for arguments even when their values are passed in
1036 The value of this macro is the size, in bytes, of the area
1037 reserved for arguments passed in registers for the function
1038 represented by FNDECL.
1040 This space can be allocated by the caller, or be a part of the
1041 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1044 #define REG_PARM_STACK_SPACE(FNDECL) \
1045 (M32R_MAX_PARM_REGS * UNITS_PER_WORD)
1048 /* Value is the number of bytes of arguments automatically
1049 popped when returning from a subroutine call.
1050 FUNDECL is the declaration node of the function (as a tree),
1051 FUNTYPE is the data type of the function (as a tree),
1052 or for a library call it is an identifier node for the subroutine name.
1053 SIZE is the number of bytes of arguments passed on the stack. */
1054 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
1056 /* Nonzero if we do not know how to pass TYPE solely in registers. */
1057 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1059 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1060 || TREE_ADDRESSABLE (TYPE)))
1062 /* Define a data type for recording info about an argument list
1063 during the scan of that argument list. This data type should
1064 hold all necessary information about the function itself
1065 and about the args processed so far, enough to enable macros
1066 such as FUNCTION_ARG to determine where the next arg should go. */
1067 #define CUMULATIVE_ARGS int
1069 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1070 for a call to a function whose data type is FNTYPE.
1071 For a library call, FNTYPE is 0. */
1072 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1075 /* The number of registers used for parameter passing. Local to this file. */
1076 #define M32R_MAX_PARM_REGS 4
1078 /* 1 if N is a possible register number for function argument passing. */
1079 #define FUNCTION_ARG_REGNO_P(N) \
1080 ((unsigned) (N) < M32R_MAX_PARM_REGS)
1082 /* The ROUND_ADVANCE* macros are local to this file. */
1083 /* Round SIZE up to a word boundary. */
1084 #define ROUND_ADVANCE(SIZE) \
1085 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1087 /* Round arg MODE/TYPE up to the next word boundary. */
1088 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1089 ((MODE) == BLKmode \
1090 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1091 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
1093 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1094 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1096 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1097 a reg. This includes arguments that have to be passed by reference as the
1098 pointer to them is passed in a reg if one is available (and that is what
1100 This macro is only used in this file. */
1101 #define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
1102 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1104 /* Determine where to put an argument to a function.
1105 Value is zero to push the argument on the stack,
1106 or a hard register in which to store the argument.
1108 MODE is the argument's machine mode.
1109 TYPE is the data type of the argument (as a tree).
1110 This is null for libcalls where that information may
1112 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1113 the preceding args and about the function being called.
1114 NAMED is nonzero if this argument is a named parameter
1115 (otherwise it is an extra parameter matching an ellipsis). */
1116 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1117 and the rest are pushed. */
1118 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1119 (PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)) \
1120 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1123 /* ??? Quick hack to try to get varargs working the normal way. */
1124 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1125 (((! current_function_varargs || (NAMED)) \
1126 && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))) \
1127 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \
1130 /* A C expression for the number of words, at the beginning of an
1131 argument, must be put in registers. The value must be zero for
1132 arguments that are passed entirely in registers or that are entirely
1133 pushed on the stack.
1135 On some machines, certain arguments must be passed partially in
1136 registers and partially in memory. On these machines, typically the
1137 first @var{n} words of arguments are passed in registers, and the rest
1138 on the stack. If a multi-word argument (a @code{double} or a
1139 structure) crosses that boundary, its first few words must be passed
1140 in registers and the rest must be pushed. This macro tells the
1141 compiler when this occurs, and how many of the words should go in
1143 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1144 function_arg_partial_nregs (&CUM, (int)MODE, TYPE, NAMED)
1146 /* A C expression that indicates when an argument must be passed by
1147 reference. If nonzero for an argument, a copy of that argument is
1148 made in memory and a pointer to the argument is passed instead of
1149 the argument itself. The pointer is passed in whatever way is
1150 appropriate for passing a pointer to that type. */
1151 /* All arguments greater than 8 bytes are passed this way. */
1152 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1153 ((TYPE) && int_size_in_bytes (TYPE) > 8)
1155 /* Update the data in CUM to advance over an argument
1156 of mode MODE and data type TYPE.
1157 (TYPE is null for libcalls where that information may not be available.) */
1158 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1159 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
1160 + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
1162 /* If defined, a C expression that gives the alignment boundary, in bits,
1163 of an argument with the specified mode and type. If it is not defined,
1164 PARM_BOUNDARY is used for all arguments. */
1166 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */
1167 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1168 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
1170 : 2 * PARM_BOUNDARY)
1173 /* This macro offers an alternative
1174 to using `__builtin_saveregs' and defining the macro
1175 `EXPAND_BUILTIN_SAVEREGS'. Use it to store the anonymous register
1176 arguments into the stack so that all the arguments appear to have
1177 been passed consecutively on the stack. Once this is done, you
1178 can use the standard implementation of varargs that works for
1179 machines that pass all their arguments on the stack.
1181 The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
1182 containing the values that obtain after processing of the named
1183 arguments. The arguments MODE and TYPE describe the last named
1184 argument--its machine mode and its data type as a tree node.
1186 The macro implementation should do two things: first, push onto the
1187 stack all the argument registers *not* used for the named
1188 arguments, and second, store the size of the data thus pushed into
1189 the `int'-valued variable whose name is supplied as the argument
1190 PRETEND_SIZE. The value that you store here will serve as
1191 additional offset for setting up the stack frame.
1193 If the argument NO_RTL is nonzero, it means that the
1194 arguments of the function are being analyzed for the second time.
1195 This happens for an inline function, which is not actually
1196 compiled until the end of the source file. The macro
1197 `SETUP_INCOMING_VARARGS' should not generate any instructions in
1200 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1201 m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1203 /* Implement `va_arg'. */
1204 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1205 m32r_va_arg (valist, type)
1207 /* Function results. */
1209 /* Define how to find the value returned by a function.
1210 VALTYPE is the data type of the value (as a tree).
1211 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1212 otherwise, FUNC is 0. */
1213 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
1215 /* Define how to find the value returned by a library function
1216 assuming the value has mode MODE. */
1217 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
1219 /* 1 if N is a possible register number for a function value
1220 as seen by the caller. */
1221 /* ??? What about r1 in DI/DF values. */
1222 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
1224 /* A C expression which can inhibit the returning of certain function
1225 values in registers, based on the type of value. A nonzero value says
1226 to return the function value in memory, just as large structures are
1227 always returned. Here TYPE will be a C expression of type `tree',
1228 representing the data type of the value. */
1229 #define RETURN_IN_MEMORY(TYPE) \
1230 (int_size_in_bytes (TYPE) > 8)
1232 /* Tell GCC to use RETURN_IN_MEMORY. */
1233 #define DEFAULT_PCC_STRUCT_RETURN 0
1235 /* Register in which address to store a structure value
1236 is passed to a function, or 0 to use `invisible' first argument. */
1237 #define STRUCT_VALUE 0
1239 /* Function entry and exit. */
1241 /* Initialize data used by insn expanders. This is called from
1242 init_emit, once for each function, before code is generated. */
1243 #define INIT_EXPANDERS m32r_init_expanders ()
1245 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1246 the stack pointer does not matter. The value is tested only in
1247 functions that have frame pointers.
1248 No definition is equivalent to always zero. */
1249 #define EXIT_IGNORE_STACK 1
1251 /* Output assembler code to FILE to increment profiler label # LABELNO
1252 for profiling a function entry. */
1253 #define FUNCTION_PROFILER(FILE, LABELNO) abort ()
1257 /* On the M32R, the trampoline is
1264 ??? Need addr32 support.
1267 /* Length in bytes of the trampoline for entering a nested function. */
1268 #define TRAMPOLINE_SIZE 12
1270 /* Emit RTL insns to initialize the variable parts of a trampoline.
1271 FNADDR is an RTX for the address of the function's pure code.
1272 CXT is an RTX for the static chain value for the function. */
1273 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1275 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 0)), \
1276 plus_constant ((CXT), 0xe7000000)); \
1277 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), \
1278 plus_constant ((FNADDR), 0xe6000000)); \
1279 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), \
1280 GEN_INT (0x1fc67000)); \
1281 emit_insn (gen_flush_icache (validize_mem (gen_rtx_MEM (SImode, TRAMP)))); \
1284 /* Library calls. */
1286 /* Generate calls to memcpy, memcmp and memset. */
1287 #define TARGET_MEM_FUNCTIONS
1289 /* Addressing modes, and classification of registers for them. */
1291 /* Maximum number of registers that can appear in a valid memory address. */
1292 #define MAX_REGS_PER_ADDRESS 1
1294 /* We have post-inc load and pre-dec,pre-inc store,
1295 but only for 4 byte vals. */
1296 #define HAVE_PRE_DECREMENT 1
1297 #define HAVE_PRE_INCREMENT 1
1298 #define HAVE_POST_INCREMENT 1
1300 /* Recognize any constant value that is a valid address. */
1301 #define CONSTANT_ADDRESS_P(X) \
1302 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1303 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
1305 /* Nonzero if the constant value X is a legitimate general operand.
1306 We don't allow (plus symbol large-constant) as the relocations can't
1307 describe it. INTVAL > 32767 handles both 16 bit and 24 bit relocations.
1308 We allow all CONST_DOUBLE's as the md file patterns will force the
1309 constant to memory if they can't handle them. */
1311 #define LEGITIMATE_CONSTANT_P(X) \
1312 (! (GET_CODE (X) == CONST \
1313 && GET_CODE (XEXP (X, 0)) == PLUS \
1314 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1315 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1316 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
1318 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1319 and check its validity for a certain class.
1320 We have two alternate definitions for each of them.
1321 The usual definition accepts all pseudo regs; the other rejects
1322 them unless they have been allocated suitable hard regs.
1323 The symbol REG_OK_STRICT causes the latter definition to be used.
1325 Most source files want to accept pseudo regs in the hope that
1326 they will get allocated to the class that the insn wants them to be in.
1327 Source files for reload pass need to be strict.
1328 After reload, it makes no difference, since pseudo regs have
1329 been eliminated by then. */
1331 #ifdef REG_OK_STRICT
1333 /* Nonzero if X is a hard reg that can be used as a base reg. */
1334 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
1335 /* Nonzero if X is a hard reg that can be used as an index. */
1336 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1340 /* Nonzero if X is a hard reg that can be used as a base reg
1341 or if it is a pseudo reg. */
1342 #define REG_OK_FOR_BASE_P(X) \
1343 (GPR_P (REGNO (X)) \
1344 || (REGNO (X)) == ARG_POINTER_REGNUM \
1345 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1346 /* Nonzero if X is a hard reg that can be used as an index
1347 or if it is a pseudo reg. */
1348 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1352 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1353 that is a valid memory address for an instruction.
1354 The MODE argument is the machine mode for the MEM expression
1355 that wants to use this address. */
1357 /* Local to this file. */
1358 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
1360 /* Local to this file. */
1361 #define RTX_OK_FOR_OFFSET_P(X) \
1362 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
1364 /* Local to this file. */
1365 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
1366 (GET_CODE (X) == PLUS \
1367 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1368 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
1370 /* Local to this file. */
1371 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
1372 since more than one instruction will be required. */
1373 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
1374 (GET_CODE (X) == LO_SUM \
1375 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
1376 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
1377 && CONSTANT_P (XEXP (X, 1)))
1379 /* Local to this file. */
1380 /* Is this a load and increment operation. */
1381 #define LOAD_POSTINC_P(MODE, X) \
1382 (((MODE) == SImode || (MODE) == SFmode) \
1383 && GET_CODE (X) == POST_INC \
1384 && GET_CODE (XEXP (X, 0)) == REG \
1385 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1387 /* Local to this file. */
1388 /* Is this an increment/decrement and store operation. */
1389 #define STORE_PREINC_PREDEC_P(MODE, X) \
1390 (((MODE) == SImode || (MODE) == SFmode) \
1391 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
1392 && GET_CODE (XEXP (X, 0)) == REG \
1393 && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
1395 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1396 { if (RTX_OK_FOR_BASE_P (X)) \
1398 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
1400 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
1402 if (LOAD_POSTINC_P ((MODE), (X))) \
1404 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
1408 /* Try machine-dependent ways of modifying an illegitimate address
1409 to be legitimate. If we find one, return the new, valid address.
1410 This macro is used in only one place: `memory_address' in explow.c.
1412 OLDX is the address as it was before break_out_memory_refs was called.
1413 In some cases it is useful to look at this to decide what needs to be done.
1415 MODE and WIN are passed so that this macro can use
1416 GO_IF_LEGITIMATE_ADDRESS.
1418 It is always safe for this macro to do nothing. It exists to recognize
1419 opportunities to optimize the output.
1421 ??? Is there anything useful we can do here for the M32R? */
1423 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1425 /* Go to LABEL if ADDR (a legitimate address expression)
1426 has an effect that depends on the machine mode it is used for. */
1427 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1429 if (GET_CODE (ADDR) == PRE_DEC \
1430 || GET_CODE (ADDR) == PRE_INC \
1431 || GET_CODE (ADDR) == POST_INC \
1432 || GET_CODE (ADDR) == LO_SUM) \
1436 /* Condition code usage. */
1438 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1439 return the mode to be used for the comparison. */
1440 #define SELECT_CC_MODE(OP, X, Y) \
1441 ((enum machine_mode)m32r_select_cc_mode ((int)OP, X, Y))
1443 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1444 floating point inequality comparison. */
1445 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
1449 /* ??? I'm quite sure I don't understand enough of the subtleties involved
1450 in choosing the right numbers to use here, but there doesn't seem to be
1451 enough documentation on this. What I've done is define an insn to cost
1452 4 "units" and work from there. COSTS_N_INSNS (N) is defined as (N) * 4 - 2
1453 so that seems reasonable. Some values are supposed to be defined relative
1454 to each other and thus aren't necessarily related to COSTS_N_INSNS. */
1456 /* Compute the cost of computing a constant rtl expression RTX
1457 whose rtx-code is CODE. The body of this macro is a portion
1458 of a switch statement. If the code is computed here,
1459 return it with a return statement. Otherwise, break from the switch. */
1460 /* Small integers are as cheap as registers. 4 byte values can be fetched
1461 as immediate constants - let's give that the cost of an extra insn. */
1462 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1464 if (INT16_P (INTVAL (X))) \
1466 /* fall through */ \
1471 case CONST_DOUBLE : \
1474 split_double (X, &high, &low); \
1475 return 4 * (!INT16_P (INTVAL (high)) \
1476 + !INT16_P (INTVAL (low))); \
1479 /* Compute the cost of an address. */
1480 #define ADDRESS_COST(ADDR) m32r_address_cost (ADDR)
1482 /* Compute extra cost of moving data between one register class
1484 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
1486 /* Compute the cost of moving data between registers and memory. */
1487 /* Memory is 3 times as expensive as registers.
1488 ??? Is that the right way to look at it? */
1489 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \
1490 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
1492 /* The cost of a branch insn. */
1493 /* A value of 2 here causes GCC to avoid using branches in comparisons like
1494 while (a < N && a). Branches aren't that expensive on the M32R so
1495 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */
1496 #define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
1498 /* Provide the costs of a rtl expression. This is in the body of a
1499 switch on CODE. The purpose for the cost of MULT is to encourage
1500 `synth_mult' to find a synthetic multiply when reasonable.
1502 If we need more than 12 insns to do a multiply, then go out-of-line,
1503 since the call overhead will be < 10% of the cost of the multiply. */
1504 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1506 return COSTS_N_INSNS (3); \
1511 return COSTS_N_INSNS (10);
1513 /* Nonzero if access to memory by bytes is slow and undesirable.
1514 For RISC chips, it means that access to memory by bytes is no
1515 better than access by words when possible, so grab a whole word
1516 and maybe make use of that. */
1517 #define SLOW_BYTE_ACCESS 1
1519 /* Define this macro if it is as good or better to call a constant
1520 function address than to call an address kept in a register. */
1521 #define NO_FUNCTION_CSE
1523 /* Define this macro if it is as good or better for a function to call
1524 itself with an explicit address than to call an address kept in a
1526 #define NO_RECURSIVE_FUNCTION_CSE
1528 /* When the `length' insn attribute is used, this macro specifies the
1529 value to be assigned to the address of the first insn in a
1530 function. If not specified, 0 is used. */
1531 #define FIRST_INSN_ADDRESS m32r_first_insn_address ()
1534 /* Section selection. */
1536 #define TEXT_SECTION_ASM_OP "\t.section .text"
1537 #define DATA_SECTION_ASM_OP "\t.section .data"
1538 #define RODATA_SECTION_ASM_OP "\t.section .rodata"
1539 #define BSS_SECTION_ASM_OP "\t.section .bss"
1540 #define SDATA_SECTION_ASM_OP "\t.section .sdata"
1541 #define SBSS_SECTION_ASM_OP "\t.section .sbss"
1542 /* This one is for svr4.h. */
1543 #undef CONST_SECTION_ASM_OP
1544 #define CONST_SECTION_ASM_OP "\t.section .rodata"
1546 /* A list of names for sections other than the standard two, which are
1547 `in_text' and `in_data'. You need not define this macro
1548 on a system with no other sections (that GCC needs to use). */
1549 #undef EXTRA_SECTIONS
1550 #define EXTRA_SECTIONS in_sdata, in_sbss, in_const
1552 /* One or more functions to be defined in "varasm.c". These
1553 functions should do jobs analogous to those of `text_section' and
1554 `data_section', for your additional sections. Do not define this
1555 macro if you do not define `EXTRA_SECTIONS'. */
1556 #undef EXTRA_SECTION_FUNCTIONS
1557 #define EXTRA_SECTION_FUNCTIONS \
1558 CONST_SECTION_FUNCTION \
1559 SDATA_SECTION_FUNCTION \
1560 SBSS_SECTION_FUNCTION
1562 #define SDATA_SECTION_FUNCTION \
1566 if (in_section != in_sdata) \
1568 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
1569 in_section = in_sdata; \
1573 #define SBSS_SECTION_FUNCTION \
1577 if (in_section != in_sbss) \
1579 fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP); \
1580 in_section = in_sbss; \
1584 /* A C statement or statements to switch to the appropriate section for
1585 output of EXP. You can assume that EXP is either a `VAR_DECL' node
1586 or a constant of some sort. RELOC indicates whether the initial value
1587 of EXP requires link-time relocations. */
1588 #undef SELECT_SECTION
1589 #define SELECT_SECTION(EXP, RELOC, ALIGN) \
1590 m32r_select_section ((EXP), (RELOC))
1592 /* A C statement or statements to switch to the appropriate section for
1593 output of RTX in mode MODE. You can assume that RTX
1594 is some kind of constant in RTL. The argument MODE is redundant
1595 except in the case of a `const_int' rtx. Select the section by
1596 calling `text_section' or one of the alternatives for other
1599 Do not define this macro if you put all constants in the read-only
1602 #undef SELECT_RTX_SECTION
1604 /* Define this macro if jump tables (for tablejump insns) should be
1605 output in the text section, along with the assembler instructions.
1606 Otherwise, the readonly data section is used.
1607 This macro is irrelevant if there is no separate readonly data section. */
1608 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
1610 /* Define this macro if references to a symbol must be treated
1611 differently depending on something about the variable or
1612 function named by the symbol (such as what section it is in).
1614 The macro definition, if any, is executed immediately after the
1615 rtl for DECL or other node is created.
1616 The value of the rtl will be a `mem' whose address is a
1619 The usual thing for this macro to do is to store a flag in the
1620 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1621 name string in the `symbol_ref' (if one bit is not enough
1624 #define SDATA_FLAG_CHAR '@'
1625 /* Small objects are recorded with no prefix for space efficiency since
1626 they'll be the most common. This isn't the case if the user passes
1627 -mmodel={medium|large} and one could choose to not mark symbols that
1628 are the default, but that complicates things. */
1629 /*#define SMALL_FLAG_CHAR '#'*/
1630 #define MEDIUM_FLAG_CHAR '%'
1631 #define LARGE_FLAG_CHAR '&'
1633 #define SDATA_NAME_P(NAME) (*(NAME) == SDATA_FLAG_CHAR)
1634 /*#define SMALL_NAME_P(NAME) (*(NAME) == SMALL_FLAG_CHAR)*/
1635 #define SMALL_NAME_P(NAME) (! ENCODED_NAME_P (NAME) && ! LIT_NAME_P (NAME))
1636 #define MEDIUM_NAME_P(NAME) (*(NAME) == MEDIUM_FLAG_CHAR)
1637 #define LARGE_NAME_P(NAME) (*(NAME) == LARGE_FLAG_CHAR)
1638 /* For string literals, etc. */
1639 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
1641 #define ENCODED_NAME_P(SYMBOL_NAME) \
1642 (SDATA_NAME_P (SYMBOL_NAME) \
1643 /*|| SMALL_NAME_P (SYMBOL_NAME)*/ \
1644 || MEDIUM_NAME_P (SYMBOL_NAME) \
1645 || LARGE_NAME_P (SYMBOL_NAME))
1647 #define ENCODE_SECTION_INFO(DECL, FIRST) m32r_encode_section_info (DECL, FIRST)
1649 /* Decode SYM_NAME and store the real name part in VAR, sans
1650 the characters that encode section info. Define this macro if
1651 ENCODE_SECTION_INFO alters the symbol's name string. */
1652 /* Note that we have to handle symbols like "%*start". */
1653 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1655 (VAR) = (SYMBOL_NAME) + ENCODED_NAME_P (SYMBOL_NAME); \
1656 (VAR) += *(VAR) == '*'; \
1661 /* The register number of the register used to address a table of static
1662 data addresses in memory. In some cases this register is defined by a
1663 processor's ``application binary interface'' (ABI). When this macro
1664 is defined, RTL is generated for this register once, as with the stack
1665 pointer and frame pointer registers. If this macro is not defined, it
1666 is up to the machine-dependent files to allocate such a register (if
1668 /*#define PIC_OFFSET_TABLE_REGNUM 12*/
1670 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
1671 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
1673 /* This register is call-saved on the M32R. */
1674 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
1676 /* By generating position-independent code, when two different programs (A
1677 and B) share a common library (libC.a), the text of the library can be
1678 shared whether or not the library is linked at the same address for both
1679 programs. In some of these environments, position-independent code
1680 requires not only the use of different addressing modes, but also
1681 special code to enable the use of these addressing modes.
1683 The FINALIZE_PIC macro serves as a hook to emit these special
1684 codes once the function is being compiled into assembly code, but not
1685 before. (It is not done before, because in the case of compiling an
1686 inline function, it would lead to multiple PIC prologues being
1687 included in functions which used inline functions and were compiled to
1688 assembly language.) */
1690 /*#define FINALIZE_PIC m32r_finalize_pic ()*/
1692 /* A C expression that is nonzero if X is a legitimate immediate
1693 operand on the target machine when generating position independent code.
1694 You can assume that X satisfies CONSTANT_P, so you need not
1695 check this. You can also assume `flag_pic' is true, so you need not
1696 check it either. You need not define this macro if all constants
1697 (including SYMBOL_REF) can be immediate operands when generating
1698 position independent code. */
1699 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
1701 /* Control the assembler format that we output. */
1703 /* Output at beginning of assembler file. */
1704 #define ASM_FILE_START(FILE) m32r_asm_file_start (FILE)
1706 /* A C string constant describing how to begin a comment in the target
1707 assembler language. The compiler assumes that the comment will
1708 end at the end of the line. */
1709 #define ASM_COMMENT_START ";"
1711 /* Output to assembler file text saying following lines
1712 may contain character constants, extra white space, comments, etc. */
1713 #define ASM_APP_ON ""
1715 /* Output to assembler file text saying following lines
1716 no longer contain unusual constructs. */
1717 #define ASM_APP_OFF ""
1719 /* This is how to output the definition of a user-level label named NAME,
1720 such as the label on a static function or variable NAME. */
1721 /* On the M32R we need to ensure the next instruction starts on a 32 bit
1722 boundary [the previous insn must either be 2 16 bit insns or 1 32 bit]. */
1723 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1726 assemble_name (FILE, NAME); \
1727 fputs (":\n", FILE); \
1731 /* This is how to output a command to make the user-level label named NAME
1732 defined for reference from other files. */
1733 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
1736 fputs ("\t.global\t", FILE); \
1737 assemble_name (FILE, NAME); \
1738 fputs ("\n", FILE); \
1742 /* This is how to output a reference to a user-level label named NAME.
1743 `assemble_name' uses this. */
1744 #undef ASM_OUTPUT_LABELREF
1745 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1748 const char * real_name; \
1749 STRIP_NAME_ENCODING (real_name, (NAME)); \
1750 asm_fprintf (FILE, "%U%s", real_name); \
1754 /* If -Os, don't force line number labels to begin at the beginning of
1755 the word; we still want the assembler to try to put things in parallel,
1756 should that be possible.
1757 For m32r/d, instructions are never in parallel (other than with a nop)
1758 and the simulator and stub both handle a breakpoint in the middle of
1759 a word so don't ever force line number labels to begin at the beginning
1762 #undef ASM_OUTPUT_SOURCE_LINE
1763 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1766 static int sym_lineno = 1; \
1767 fprintf (file, ".stabn 68,0,%d,.LM%d-", \
1768 line, sym_lineno); \
1770 (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
1771 fprintf (file, (optimize_size || TARGET_M32R) \
1772 ? "\n\t.debugsym .LM%d\n" \
1779 /* Store in OUTPUT a string (made with alloca) containing
1780 an assembler-name for a local static variable named NAME.
1781 LABELNO is an integer which is different for each call. */
1782 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1785 (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);\
1786 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)); \
1790 /* How to refer to registers in assembler output.
1791 This sequence is indexed by compiler's hard-register-number (see above). */
1792 #ifndef SUBTARGET_REGISTER_NAMES
1793 #define SUBTARGET_REGISTER_NAMES
1796 #define REGISTER_NAMES \
1798 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1799 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \
1800 "ap", "cbit", "a0" \
1801 SUBTARGET_REGISTER_NAMES \
1804 /* If defined, a C initializer for an array of structures containing
1805 a name and a register number. This macro defines additional names
1806 for hard registers, thus allowing the `asm' option in declarations
1807 to refer to registers using alternate names. */
1808 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
1809 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES
1812 #define ADDITIONAL_REGISTER_NAMES \
1814 /*{ "gp", GP_REGNUM },*/ \
1815 { "r13", FRAME_POINTER_REGNUM }, \
1816 { "r14", RETURN_ADDR_REGNUM }, \
1817 { "r15", STACK_POINTER_REGNUM }, \
1818 SUBTARGET_ADDITIONAL_REGISTER_NAMES \
1821 /* A C expression which evaluates to true if CODE is a valid
1822 punctuation character for use in the `PRINT_OPERAND' macro. */
1823 extern char m32r_punct_chars[256];
1824 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1825 m32r_punct_chars[(unsigned char) (CHAR)]
1827 /* Print operand X (an rtx) in assembler syntax to file FILE.
1828 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1829 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1830 #define PRINT_OPERAND(FILE, X, CODE) \
1831 m32r_print_operand (FILE, X, CODE)
1833 /* A C compound statement to output to stdio stream STREAM the
1834 assembler syntax for an instruction operand that is a memory
1835 reference whose address is ADDR. ADDR is an RTL expression.
1837 On some machines, the syntax for a symbolic address depends on
1838 the section that the address refers to. On these machines,
1839 define the macro `ENCODE_SECTION_INFO' to store the information
1840 into the `symbol_ref', and then check for it here. */
1841 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1842 m32r_print_operand_address (FILE, ADDR)
1844 /* If defined, C string expressions to be used for the `%R', `%L',
1845 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These
1846 are useful when a single `md' file must support multiple assembler
1847 formats. In that case, the various `tm.h' files can define these
1848 macros differently. */
1849 #define REGISTER_PREFIX ""
1850 #define LOCAL_LABEL_PREFIX ".L"
1851 #define USER_LABEL_PREFIX ""
1852 #define IMMEDIATE_PREFIX "#"
1854 /* This is how to output an element of a case-vector that is absolute. */
1855 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1859 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1860 fprintf (FILE, "\t.word\t"); \
1861 assemble_name (FILE, label); \
1862 fprintf (FILE, "\n"); \
1866 /* This is how to output an element of a case-vector that is relative. */
1867 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
1871 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1872 fprintf (FILE, "\t.word\t"); \
1873 assemble_name (FILE, label); \
1874 fprintf (FILE, "-"); \
1875 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1876 assemble_name (FILE, label); \
1877 fprintf (FILE, ")\n"); \
1881 /* The desired alignment for the location counter at the beginning
1883 /* On the M32R, align loops to 32 byte boundaries (cache line size)
1884 if -malign-loops. */
1885 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
1887 /* Define this to be the maximum number of insns to move around when moving
1888 a loop test from the top of a loop to the bottom
1889 and seeing whether to duplicate it. The default is thirty.
1891 Loop unrolling currently doesn't like this optimization, so
1892 disable doing if we are unrolling loops and saving space. */
1893 #define LOOP_TEST_THRESHOLD (optimize_size \
1894 && !flag_unroll_loops \
1895 && !flag_unroll_all_loops ? 2 : 30)
1897 /* This is how to output an assembler line
1898 that says to advance the location counter
1899 to a multiple of 2**LOG bytes. */
1900 /* .balign is used to avoid confusion. */
1901 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1905 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \
1909 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
1910 separate, explicit argument. If you define this macro, it is used in
1911 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
1912 handling the required alignment of the variable. The alignment is
1913 specified as the number of bits. */
1915 #define SCOMMON_ASM_OP "\t.scomm\t"
1917 #undef ASM_OUTPUT_ALIGNED_COMMON
1918 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1921 if (! TARGET_SDATA_NONE \
1922 && (SIZE) > 0 && (SIZE) <= g_switch_value) \
1923 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
1925 fprintf ((FILE), "%s", COMMON_ASM_OP); \
1926 assemble_name ((FILE), (NAME)); \
1927 fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
1931 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1932 separate, explicit argument. If you define this macro, it is used in
1933 place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1934 handling the required alignment of the variable. The alignment is
1935 specified as the number of bits.
1937 For the M32R we need sbss support. */
1939 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1942 ASM_GLOBALIZE_LABEL (FILE, NAME); \
1943 ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN); \
1947 /* Debugging information. */
1949 /* Generate DBX and DWARF debugging information. */
1950 #undef DBX_DEBUGGING_INFO
1951 #undef DWARF_DEBUGGING_INFO
1952 #undef DWARF2_DEBUGGING_INFO
1954 #define DBX_DEBUGGING_INFO
1955 #define DWARF_DEBUGGING_INFO
1956 #define DWARF2_DEBUGGING_INFO
1958 /* Prefer STABS (for now). */
1959 #undef PREFERRED_DEBUGGING_TYPE
1960 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
1962 /* Turn off splitting of long stabs. */
1963 #define DBX_CONTIN_LENGTH 0
1965 /* Miscellaneous. */
1967 /* Specify the machine mode that this machine uses
1968 for the index in the tablejump instruction. */
1969 #define CASE_VECTOR_MODE Pmode
1971 /* Define as C expression which evaluates to nonzero if the tablejump
1972 instruction expects the table to contain offsets from the address of the
1974 Do not define this if the table should contain absolute addresses. */
1975 /* It's not clear what PIC will look like or whether we want to use -fpic
1976 for the embedded form currently being talked about. For now require -fpic
1977 to get pc relative switch tables. */
1978 /*#define CASE_VECTOR_PC_RELATIVE 1 */
1980 /* Define if operations between registers always perform the operation
1981 on the full register even if a narrower mode is specified. */
1982 #define WORD_REGISTER_OPERATIONS
1984 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1985 will either zero-extend or sign-extend. The value of this macro should
1986 be the code that says which one of the two operations is implicitly
1987 done, NIL if none. */
1988 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1990 /* Max number of bytes we can move from memory to memory
1991 in one reasonably fast instruction. */
1994 /* Define this to be nonzero if shift instructions ignore all but the low-order
1996 #define SHIFT_COUNT_TRUNCATED 1
1998 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1999 is done just by pretending it is already truncated. */
2000 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2002 /* We assume that the store-condition-codes instructions store 0 for false
2003 and some other value for true. This is the value stored for true. */
2004 #define STORE_FLAG_VALUE 1
2006 /* Specify the machine mode that pointers have.
2007 After generation of rtl, the compiler makes no further distinction
2008 between pointers and any other objects of this machine mode. */
2009 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
2010 it's own problems (you have to add extendpsisi2 and truncsipsi2).
2012 #define Pmode SImode
2014 /* A function address in a call instruction. */
2015 #define FUNCTION_MODE SImode
2017 /* Define the information needed to generate branch and scc insns. This is
2018 stored from the compare operation. Note that we can't use "rtx" here
2019 since it hasn't been defined! */
2020 extern struct rtx_def * m32r_compare_op0;
2021 extern struct rtx_def * m32r_compare_op1;
2023 /* M32R function types. */
2024 enum m32r_function_type
2026 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
2029 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
2031 /* Define this if you have defined special-purpose predicates in the
2032 file `MACHINE.c'. This macro is called within an initializer of an
2033 array of structures. The first field in the structure is the name
2034 of a predicate and the second field is an array of rtl codes. For
2035 each predicate, list all rtl codes that can be in expressions
2036 matched by the predicate. The list should have a trailing comma. */
2038 #define PREDICATE_CODES \
2039 { "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \
2040 { "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
2041 { "carry_compare_operand", { EQ, NE }}, \
2042 { "eqne_comparison_operator", { EQ, NE }}, \
2043 { "signed_comparison_operator", { EQ, NE, LT, LE, GT, GE }}, \
2044 { "move_dest_operand", { REG, SUBREG, MEM }}, \
2045 { "move_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2046 CONST_DOUBLE, LABEL_REF, CONST, \
2048 { "move_double_src_operand", { REG, SUBREG, MEM, CONST_INT, \
2050 { "two_insn_const_operand", { CONST_INT }}, \
2051 { "symbolic_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2052 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2053 { "int8_operand", { CONST_INT }}, \
2054 { "uint16_operand", { CONST_INT }}, \
2055 { "reg_or_int16_operand", { REG, SUBREG, CONST_INT }}, \
2056 { "reg_or_uint16_operand", { REG, SUBREG, CONST_INT }}, \
2057 { "reg_or_cmp_int16_operand", { REG, SUBREG, CONST_INT }}, \
2058 { "reg_or_eq_int16_operand", { REG, SUBREG, CONST_INT }}, \
2059 { "cmp_int16_operand", { CONST_INT }}, \
2060 { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \
2061 { "extend_operand", { REG, SUBREG, MEM }}, \
2062 { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2063 { "m32r_block_immediate_operand",{ CONST_INT }}, \
2064 { "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \
2065 { "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }},
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