1 /* Subroutines used for code generation on the M32R/D cpu.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
37 /* Save the operands last given to a compare for use when we
38 generate a scc or bcc insn. */
39 rtx m32r_compare_op0, m32r_compare_op1;
41 /* Array of valid operand punctuation characters. */
42 char m32r_punct_chars[256];
44 static void init_reg_tables ();
46 /* Selected code model. */
47 char *m32r_model_string = M32R_MODEL_DEFAULT;
48 enum m32r_model m32r_model;
50 /* Selected SDA support. */
51 char *m32r_sdata_string = M32R_SDATA_DEFAULT;
52 enum m32r_sdata m32r_sdata;
54 /* Called by OVERRIDE_OPTIONS to initialize various things. */
61 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
62 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
63 m32r_punct_chars['#'] = 1;
64 m32r_punct_chars['@'] = 1; /* ??? no longer used */
66 /* Provide default value if not specified. */
68 g_switch_value = SDATA_DEFAULT_SIZE;
70 if (strcmp (m32r_model_string, "small") == 0)
71 m32r_model = M32R_MODEL_SMALL;
72 else if (strcmp (m32r_model_string, "medium") == 0)
73 m32r_model = M32R_MODEL_MEDIUM;
74 else if (strcmp (m32r_model_string, "large") == 0)
75 m32r_model = M32R_MODEL_LARGE;
77 error ("bad value (%s) for -mmodel switch", m32r_model_string);
79 if (strcmp (m32r_sdata_string, "none") == 0)
80 m32r_sdata = M32R_SDATA_NONE;
81 else if (strcmp (m32r_sdata_string, "sdata") == 0)
82 m32r_sdata = M32R_SDATA_SDATA;
83 else if (strcmp (m32r_sdata_string, "use") == 0)
84 m32r_sdata = M32R_SDATA_USE;
86 error ("bad value (%s) for -msdata switch", m32r_sdata_string);
89 /* Vectors to keep interesting information about registers where it can easily
90 be got. We use to use the actual mode value as the bit number, but there
91 is (or may be) more than 32 modes now. Instead we use two tables: one
92 indexed by hard register number, and one indexed by mode. */
94 /* The purpose of m32r_mode_class is to shrink the range of modes so that
95 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
96 mapped into one m32r_mode_class mode. */
98 enum m32r_mode_class {
100 S_MODE, D_MODE, T_MODE, O_MODE,
101 SF_MODE, DF_MODE, TF_MODE, OF_MODE
104 /* Modes for condition codes. */
105 #define C_MODES (1 << (int) C_MODE)
107 /* Modes for single-word and smaller quantities. */
108 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
110 /* Modes for double-word and smaller quantities. */
111 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
113 /* Modes for quad-word and smaller quantities. */
114 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
116 /* Value is 1 if register/mode pair is acceptable on arc. */
118 unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
119 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
120 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
124 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
126 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
133 for (i = 0; i < NUM_MACHINE_MODES; i++)
135 switch (GET_MODE_CLASS (i))
138 case MODE_PARTIAL_INT:
139 case MODE_COMPLEX_INT:
140 if (GET_MODE_SIZE (i) <= 4)
141 m32r_mode_class[i] = 1 << (int) S_MODE;
142 else if (GET_MODE_SIZE (i) == 8)
143 m32r_mode_class[i] = 1 << (int) D_MODE;
144 else if (GET_MODE_SIZE (i) == 16)
145 m32r_mode_class[i] = 1 << (int) T_MODE;
146 else if (GET_MODE_SIZE (i) == 32)
147 m32r_mode_class[i] = 1 << (int) O_MODE;
149 m32r_mode_class[i] = 0;
152 case MODE_COMPLEX_FLOAT:
153 if (GET_MODE_SIZE (i) <= 4)
154 m32r_mode_class[i] = 1 << (int) SF_MODE;
155 else if (GET_MODE_SIZE (i) == 8)
156 m32r_mode_class[i] = 1 << (int) DF_MODE;
157 else if (GET_MODE_SIZE (i) == 16)
158 m32r_mode_class[i] = 1 << (int) TF_MODE;
159 else if (GET_MODE_SIZE (i) == 32)
160 m32r_mode_class[i] = 1 << (int) OF_MODE;
162 m32r_mode_class[i] = 0;
166 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
167 we must explicitly check for them here. */
168 if (i == (int) CCmode)
169 m32r_mode_class[i] = 1 << (int) C_MODE;
171 m32r_mode_class[i] = 0;
176 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
179 m32r_regno_reg_class[i] = GENERAL_REGS;
180 else if (i == ARG_POINTER_REGNUM)
181 m32r_regno_reg_class[i] = GENERAL_REGS;
183 m32r_regno_reg_class[i] = NO_REGS;
187 /* M32R specific attribute support.
189 interrupt - for interrupt functions
191 model - select code model used to access object
193 small: addresses use 24 bits, use bl to make calls
194 medium: addresses use 32 bits, use bl to make calls
195 large: addresses use 32 bits, use seth/add3/jl to make calls
197 Grep for MODEL in m32r.h for more info.
200 /* Return nonzero if IDENTIFIER is a valid decl attribute. */
203 m32r_valid_machine_decl_attribute (type, attributes, identifier, args)
209 static tree interrupt_ident, model_ident;
210 static tree small_ident, medium_ident, large_ident;
212 if (interrupt_ident == 0)
214 interrupt_ident = get_identifier ("__interrupt__");
215 model_ident = get_identifier ("__model__");
216 small_ident = get_identifier ("__small__");
217 medium_ident = get_identifier ("__medium__");
218 large_ident = get_identifier ("__large__");
221 if (identifier == interrupt_ident
222 && list_length (args) == 0)
225 if (identifier == model_ident
226 && list_length (args) == 1
227 && (TREE_VALUE (args) == small_ident
228 || TREE_VALUE (args) == medium_ident
229 || TREE_VALUE (args) == large_ident))
235 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
236 and two if they are nearly compatible (which causes a warning to be
240 m32r_comp_type_attributes (type1, type2)
246 /* Set the default attributes for TYPE. */
249 m32r_set_default_type_attributes (type)
254 /* A C statement or statements to switch to the appropriate
255 section for output of DECL. DECL is either a `VAR_DECL' node
256 or a constant of some sort. RELOC indicates whether forming
257 the initial value of DECL requires link-time relocations. */
260 m32r_select_section (decl, reloc)
264 if (TREE_CODE (decl) == STRING_CST)
266 if (! flag_writable_strings)
271 else if (TREE_CODE (decl) == VAR_DECL)
273 if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
275 else if ((flag_pic && reloc)
276 || !TREE_READONLY (decl)
277 || TREE_SIDE_EFFECTS (decl)
278 || !DECL_INITIAL (decl)
279 || (DECL_INITIAL (decl) != error_mark_node
280 && !TREE_CONSTANT (DECL_INITIAL (decl))))
289 /* Encode section information of DECL, which is either a VAR_DECL,
290 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
292 For the M32R we want to record:
294 - whether the object lives in .sdata/.sbss.
295 objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
297 - what code model should be used to access the object
298 small: recorded with no flag - for space efficiency since they'll
300 medium: prefixed with MEDIUM_FLAG_CHAR
301 large: prefixed with LARGE_FLAG_CHAR
305 m32r_encode_section_info (decl)
311 switch (TREE_CODE (decl))
315 model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
319 /* ??? document all others that can appear here */
324 /* Only mark the object as being small data area addressable if
325 it hasn't been explicitly marked with a code model.
327 The user can explicitly put an object in the small data area with the
328 section attribute. If the object is in sdata/sbss and marked with a
329 code model do both [put the object in .sdata and mark it as being
330 addressed with a specific code model - don't mark it as being addressed
331 with an SDA reloc though]. This is ok and might be useful at times. If
332 the object doesn't fit the linker will give an error. */
336 if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
337 && DECL_SECTION_NAME (decl) != NULL_TREE)
339 char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
340 if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
342 #if 0 /* ??? There's no reason to disallow this, is there? */
343 if (TREE_READONLY (decl))
344 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
346 prefix = SDATA_FLAG_CHAR;
351 if (TREE_CODE (decl) == VAR_DECL
352 && ! TREE_READONLY (decl)
353 && ! TARGET_SDATA_NONE)
355 int size = int_size_in_bytes (TREE_TYPE (decl));
357 if (size > 0 && size <= g_switch_value)
358 prefix = SDATA_FLAG_CHAR;
363 /* If data area not decided yet, check for a code model. */
368 if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__small__"))
369 ; /* don't mark the symbol specially */
370 else if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__medium__"))
371 prefix = MEDIUM_FLAG_CHAR;
372 else if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__large__"))
373 prefix = LARGE_FLAG_CHAR;
375 abort (); /* shouldn't happen */
379 if (TARGET_MODEL_SMALL)
380 ; /* don't mark the symbol specially */
381 else if (TARGET_MODEL_MEDIUM)
382 prefix = MEDIUM_FLAG_CHAR;
383 else if (TARGET_MODEL_LARGE)
384 prefix = LARGE_FLAG_CHAR;
386 abort (); /* shouldn't happen */
392 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
393 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
394 char *str = XSTR (XEXP (rtl, 0), 0);
395 int len = strlen (str);
396 char *newstr = savealloc (len + 2);
397 strcpy (newstr + 1, str);
399 XSTR (XEXP (rtl, 0), 0) = newstr;
403 /* Do anything needed before RTL is emitted for each function. */
406 m32r_init_expanders ()
408 /* ??? At one point there was code here. The function is left in
409 to make it easy to experiment. */
412 /* Acceptable arguments to the call insn. */
415 call_address_operand (op, mode)
417 enum machine_mode mode;
419 return (symbolic_operand (op, mode)
420 || (GET_CODE (op) == CONST_INT && LEGITIMATE_CONSTANT_P (op))
421 || (GET_CODE (op) == REG));
425 call_operand (op, mode)
427 enum machine_mode mode;
429 if (GET_CODE (op) != MEM)
432 return call_address_operand (op, mode);
435 /* Returns 1 if OP is a symbol reference. */
438 symbolic_operand (op, mode)
440 enum machine_mode mode;
442 switch (GET_CODE (op))
453 /* Return truth value of statement that OP is a symbolic memory
454 operand of mode MODE. */
457 symbolic_memory_operand (op, mode)
459 enum machine_mode mode;
461 if (GET_CODE (op) == SUBREG)
462 op = SUBREG_REG (op);
463 if (GET_CODE (op) != MEM)
466 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
467 || GET_CODE (op) == LABEL_REF);
470 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
473 small_data_operand (op, mode)
475 enum machine_mode mode;
477 if (! TARGET_SDATA_USE)
480 if (GET_CODE (op) == SYMBOL_REF)
481 return SDATA_NAME_P (XSTR (op, 0));
483 if (GET_CODE (op) == CONST
484 && GET_CODE (XEXP (op, 0)) == PLUS
485 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
486 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
487 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
488 return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
493 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
496 addr24_operand (op, mode)
498 enum machine_mode mode;
500 if (GET_CODE (op) == LABEL_REF)
501 return TARGET_ADDR24;
503 if (GET_CODE (op) == SYMBOL_REF)
504 return (SMALL_NAME_P (XSTR (op, 0))
506 && CONSTANT_POOL_ADDRESS_P (op)));
508 if (GET_CODE (op) == CONST
509 && GET_CODE (XEXP (op, 0)) == PLUS
510 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
511 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
512 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
514 rtx sym = XEXP (XEXP (op, 0), 0);
515 return (SMALL_NAME_P (XSTR (sym, 0))
517 && CONSTANT_POOL_ADDRESS_P (op)));
523 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
526 addr32_operand (op, mode)
528 enum machine_mode mode;
530 if (GET_CODE (op) == LABEL_REF)
531 return TARGET_ADDR32;
533 if (GET_CODE (op) == SYMBOL_REF)
534 return (! addr24_operand (op)
535 && ! small_data_operand (op));
537 if (GET_CODE (op) == CONST
538 && GET_CODE (XEXP (op, 0)) == PLUS
539 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
540 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
542 return (! addr24_operand (op)
543 && ! small_data_operand (op));
549 /* Return 1 if OP is a function that can be called with the `bl' insn. */
552 call26_operand (op, mode)
554 enum machine_mode mode;
556 if (GET_CODE (op) == SYMBOL_REF)
557 return ! LARGE_NAME_P (XSTR (op, 0));
559 return TARGET_CALL26;
562 /* Return 1 if OP is a function that must be called with 32 bit addressing. */
565 call32_operand (op, mode)
567 enum machine_mode mode;
569 return ! call26_operand (op, mode);
572 /* Returns 1 if OP is an acceptable operand for seth/add3. */
575 seth_add3_operand (op, mode)
577 enum machine_mode mode;
579 if (GET_CODE (op) == SYMBOL_REF
580 || GET_CODE (op) == LABEL_REF)
583 if (GET_CODE (op) == CONST
584 && GET_CODE (XEXP (op, 0)) == PLUS
585 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
586 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
587 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
593 /* Return true if OP is a signed 8 bit immediate value. */
596 int8_operand (op, mode)
598 enum machine_mode mode;
600 if (GET_CODE (op) != CONST_INT)
602 return INT8_P (INTVAL (op));
605 /* Return true if OP is a signed 16 bit immediate value. */
608 int16_operand (op, mode)
610 enum machine_mode mode;
612 if (GET_CODE (op) != CONST_INT)
614 return INT16_P (INTVAL (op));
617 /* Return true if OP is a signed 16 bit immediate value
618 useful in comparisons. */
621 cmp_int16_operand (op, mode)
623 enum machine_mode mode;
625 if (GET_CODE (op) != CONST_INT)
627 return CMP_INT16_P (INTVAL (op));
630 /* Return true if OP is an unsigned 16 bit immediate value. */
633 uint16_operand (op, mode)
635 enum machine_mode mode;
637 if (GET_CODE (op) != CONST_INT)
639 return UINT16_P (INTVAL (op));
642 /* Return true if OP is an unsigned 24 bit immediate value. */
645 uint24_operand (op, mode)
647 enum machine_mode mode;
649 if (GET_CODE (op) != CONST_INT)
651 return UINT24_P (INTVAL (op));
654 /* Return true if OP is a register or signed 8 bit value. */
657 reg_or_int8_operand (op, mode)
659 enum machine_mode mode;
661 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
662 return register_operand (op, mode);
663 if (GET_CODE (op) != CONST_INT)
665 return INT8_P (INTVAL (op));
668 /* Return true if OP is a register or signed 8 bit value. */
671 reg_or_int16_operand (op, mode)
673 enum machine_mode mode;
675 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
676 return register_operand (op, mode);
677 if (GET_CODE (op) != CONST_INT)
679 return INT16_P (INTVAL (op));
682 /* Return true if OP is a register or signed 8 bit value. */
685 reg_or_uint16_operand (op, mode)
687 enum machine_mode mode;
689 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
690 return register_operand (op, mode);
691 if (GET_CODE (op) != CONST_INT)
693 return UINT16_P (INTVAL (op));
696 /* Return true if OP is a register or signed 16 bit value for compares. */
699 reg_or_cmp_int16_operand (op, mode)
701 enum machine_mode mode;
703 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
704 return register_operand (op, mode);
705 if (GET_CODE (op) != CONST_INT)
707 return CMP_INT16_P (INTVAL (op));
710 /* Return true if OP is a const_int requiring two instructions to load. */
713 two_insn_const_operand (op, mode)
715 enum machine_mode mode;
717 if (GET_CODE (op) != CONST_INT)
719 if (INT16_P (INTVAL (op))
720 || UINT24_P (INTVAL (op))
721 || UPPER16_P (INTVAL (op)))
726 /* Return true if OP is an acceptable argument for a single word
730 move_src_operand (op, mode)
732 enum machine_mode mode;
734 switch (GET_CODE (op))
738 return addr24_operand (op, mode);
740 /* ??? We allow more cse opportunities if we only allow constants
741 loadable with one insn, and split the rest into two. The instances
742 where this would help should be rare and the current way is
744 return INT32_P (INTVAL (op));
746 return TARGET_ADDR24;
750 else if (mode == SImode)
752 /* Large unsigned constants are represented as const_double's. */
753 unsigned HOST_WIDE_INT low, high;
755 low = CONST_DOUBLE_LOW (op);
756 high = CONST_DOUBLE_HIGH (op);
757 return high == 0 && low <= 0xffffffff;
762 return register_operand (op, mode);
764 /* (subreg (mem ...) ...) can occur here if the inner part was once a
765 pseudo-reg and is now a stack slot. */
766 if (GET_CODE (SUBREG_REG (op)) == MEM)
767 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
769 return register_operand (op, mode);
771 return address_operand (XEXP (op, 0), mode);
777 /* Return true if OP is an acceptable argument for a double word
781 move_double_src_operand (op, mode)
783 enum machine_mode mode;
785 switch (GET_CODE (op))
790 return easy_df_const (op);
792 return easy_di_const (op);
794 return register_operand (op, mode);
796 /* (subreg (mem ...) ...) can occur here if the inner part was once a
797 pseudo-reg and is now a stack slot. */
798 if (GET_CODE (SUBREG_REG (op)) == MEM)
799 return move_double_src_operand (SUBREG_REG (op), mode);
801 return register_operand (op, mode);
803 /* Disallow auto inc/dec for now. */
804 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
805 || GET_CODE (XEXP (op, 0)) == PRE_INC)
807 return address_operand (XEXP (op, 0), mode);
813 /* Return true if OP is an acceptable argument for a move destination. */
816 move_dest_operand (op, mode)
818 enum machine_mode mode;
820 switch (GET_CODE (op))
823 return register_operand (op, mode);
825 /* (subreg (mem ...) ...) can occur here if the inner part was once a
826 pseudo-reg and is now a stack slot. */
827 if (GET_CODE (SUBREG_REG (op)) == MEM)
828 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
830 return register_operand (op, mode);
832 return address_operand (XEXP (op, 0), mode);
838 /* Return 1 if OP is a DImode const we want to handle inline.
839 This must match the code in the movdi pattern.
840 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
846 rtx high_rtx, low_rtx;
847 HOST_WIDE_INT high, low;
849 split_double (op, &high_rtx, &low_rtx);
850 high = INTVAL (high_rtx);
851 low = INTVAL (low_rtx);
852 /* Pick constants loadable with 2 16 bit `ldi' insns. */
853 if (high >= -128 && high <= 127
854 && low >= -128 && low <= 127)
859 /* Return 1 if OP is a DFmode const we want to handle inline.
860 This must match the code in the movdf pattern.
861 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
870 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
871 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
872 if (l[0] == 0 && l[1] == 0)
874 if ((l[0] & 0xffff) == 0 && l[1] == 0)
879 /* Return 1 if OP is an EQ or NE comparison operator. */
882 eqne_comparison_operator (op, mode)
884 enum machine_mode mode;
886 enum rtx_code code = GET_CODE (op);
888 if (GET_RTX_CLASS (code) != '<')
890 return (code == EQ || code == NE);
893 /* Return 1 if OP is a signed comparison operator. */
896 signed_comparison_operator (op, mode)
898 enum machine_mode mode;
900 enum rtx_code code = GET_CODE (op);
902 if (GET_RTX_CLASS (code) != '<')
904 return (code == EQ || code == NE
905 || code == LT || code == LE || code == GT || code == GE);
908 /* Return 1 if OP is (mem (reg ...)).
909 This is used in insn length calcs. */
912 memreg_operand (op, mode)
914 enum machine_mode mode;
916 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
921 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
922 return the mode to be used for the comparison. */
925 m32r_select_cc_mode (op, x, y)
932 /* X and Y are two things to compare using CODE. Emit the compare insn and
933 return the rtx for compare [arg0 of the if_then_else]. */
936 gen_compare (code, x, y)
940 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
941 enum rtx_code compare_code, branch_code;
942 rtx cc_reg = gen_rtx (REG, mode, CARRY_REGNUM);
947 case EQ: compare_code = EQ; branch_code = NE; break;
948 case NE: compare_code = EQ; branch_code = EQ; break;
949 case LT: compare_code = LT; branch_code = NE; break;
950 case LE: compare_code = LT; branch_code = EQ; swap_p = 1; break;
951 case GT: compare_code = LT; branch_code = NE; swap_p = 1; break;
952 case GE: compare_code = LT; branch_code = EQ; break;
953 case LTU: compare_code = LTU; branch_code = NE; break;
954 case LEU: compare_code = LTU; branch_code = EQ; swap_p = 1; break;
955 case GTU: compare_code = LTU; branch_code = NE; swap_p = 1; break;
956 case GEU: compare_code = LTU; branch_code = EQ; break;
959 if (! TARGET_OLD_COMPARE)
961 /* reg/reg equal comparison */
962 if (compare_code == EQ
963 && register_operand (y, SImode))
964 return gen_rtx (code, mode, x, y);
965 /* reg/zero signed comparison */
966 if ((compare_code == EQ || compare_code == LT)
968 return gen_rtx (code, mode, x, y);
969 /* reg/smallconst equal comparison */
970 if (compare_code == EQ
971 && GET_CODE (y) == CONST_INT
972 && CMP_INT16_P (INTVAL (y)))
974 rtx tmp = gen_reg_rtx (SImode);
975 emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
976 return gen_rtx (code, mode, tmp, const0_rtx);
978 /* reg/const equal comparison */
979 if (compare_code == EQ
982 rtx tmp = force_reg (GET_MODE (x), y);
983 return gen_rtx (code, mode, x, tmp);
987 if (swap_p && CONSTANT_P (y))
988 y = force_reg (GET_MODE (x), y);
989 else if (CONSTANT_P (y))
992 (code == LTU || code == LEU || code == GTU || code == GEU)
993 ? uint16_operand (y, GET_MODE (y))
994 : reg_or_cmp_int16_operand (y, GET_MODE (y));
996 y = force_reg (GET_MODE (x), y);
999 switch (compare_code)
1002 emit_insn (gen_cmp_eqsi_insn (swap_p ? y : x, swap_p ? x : y));
1005 emit_insn (gen_cmp_ltsi_insn (swap_p ? y : x, swap_p ? x : y));
1008 emit_insn (gen_cmp_ltusi_insn (swap_p ? y : x, swap_p ? x : y));
1012 return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1015 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro. */
1018 function_arg_partial_nregs (cum, mode, type, named)
1019 CUMULATIVE_ARGS *cum;
1020 enum machine_mode mode;
1025 int size = (((mode == BLKmode && type)
1026 ? int_size_in_bytes (type)
1027 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1029 if (*cum >= M32R_MAX_PARM_REGS)
1031 else if (*cum + size > M32R_MAX_PARM_REGS)
1032 ret = (*cum + size) - M32R_MAX_PARM_REGS;
1039 /* Do any needed setup for a variadic function. For the M32R, we must
1040 create a register parameter block, and then copy any anonymous arguments
1041 in registers to memory.
1043 CUM has not been updated for the last named argument which has type TYPE
1044 and mode MODE, and we rely on this fact. */
1047 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1048 CUMULATIVE_ARGS *cum;
1049 enum machine_mode mode;
1059 /* All BLKmode values are passed by reference. */
1060 if (mode == BLKmode)
1063 /* We must treat `__builtin_va_alist' as an anonymous arg. */
1064 if (current_function_varargs)
1065 first_anon_arg = *cum;
1067 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1068 + ROUND_ADVANCE_ARG (mode, type));
1070 if (first_anon_arg < M32R_MAX_PARM_REGS)
1072 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1073 int first_reg_offset = first_anon_arg;
1074 /* Size in words to "pretend" allocate. */
1075 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1078 regblock = gen_rtx (MEM, BLKmode,
1079 plus_constant (arg_pointer_rtx,
1080 FIRST_PARM_OFFSET (0)));
1081 move_block_from_reg (first_reg_offset, regblock,
1082 size, size * UNITS_PER_WORD);
1084 *pretend_size = (size * UNITS_PER_WORD);
1088 /* Cost functions. */
1090 /* Provide the costs of an addressing mode that contains ADDR.
1091 If ADDR is not a valid address, its cost is irrelevant.
1093 This function is trivial at the moment. This code doesn't live
1094 in m32r.h so it's easy to experiment. */
1097 m32r_address_cost (addr)
1103 /* Type of function DECL.
1105 The result is cached. To reset the cache at the end of a function,
1106 call with DECL = NULL_TREE. */
1108 enum m32r_function_type
1109 m32r_compute_function_type (decl)
1113 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1114 /* Last function we were called for. */
1115 static tree last_fn = NULL_TREE;
1117 /* Resetting the cached value? */
1118 if (decl == NULL_TREE)
1120 fn_type = M32R_FUNCTION_UNKNOWN;
1121 last_fn = NULL_TREE;
1125 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1128 /* Compute function type. */
1129 fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
1130 ? M32R_FUNCTION_INTERRUPT
1131 : M32R_FUNCTION_NORMAL);
1136 \f/* Function prologue/epilogue handlers. */
1138 /* M32R stack frames look like:
1140 Before call After call
1141 +-----------------------+ +-----------------------+
1143 high | local variables, | | local variables, |
1144 mem | reg save area, etc. | | reg save area, etc. |
1146 +-----------------------+ +-----------------------+
1148 | arguments on stack. | | arguments on stack. |
1150 SP+0->+-----------------------+ +-----------------------+
1151 | reg parm save area, |
1152 | only created for |
1153 | variable argument |
1155 +-----------------------+
1156 | previous frame ptr |
1157 +-----------------------+
1159 | register save area |
1161 +-----------------------+
1163 +-----------------------+
1167 +-----------------------+
1169 | alloca allocations |
1171 +-----------------------+
1173 low | arguments on stack |
1175 SP+0->+-----------------------+
1178 1) The "reg parm save area" does not exist for non variable argument fns.
1179 2) The "reg parm save area" can be eliminated completely if we saved regs
1180 containing anonymous args separately but that complicates things too
1181 much (so it's not done).
1182 3) The return address is saved after the register save area so as to have as
1183 many insns as possible between the restoration of `lr' and the `jmp lr'.
1186 /* Structure to be filled in by m32r_compute_frame_size with register
1187 save masks, and offsets for the current function. */
1188 struct m32r_frame_info
1190 unsigned int total_size; /* # bytes that the entire frame takes up */
1191 unsigned int extra_size; /* # bytes of extra stuff */
1192 unsigned int pretend_size; /* # bytes we push and pretend caller did */
1193 unsigned int args_size; /* # bytes that outgoing arguments take up */
1194 unsigned int reg_size; /* # bytes needed to store regs */
1195 unsigned int var_size; /* # bytes that variables take up */
1196 unsigned int gmask; /* mask of saved gp registers */
1197 unsigned int save_fp; /* nonzero if fp must be saved */
1198 unsigned int save_lr; /* nonzero if lr (return addr) must be saved */
1199 int initialized; /* nonzero if frame size already calculated */
1202 /* Current frame information calculated by m32r_compute_frame_size. */
1203 static struct m32r_frame_info current_frame_info;
1205 /* Zero structure to initialize current_frame_info. */
1206 static struct m32r_frame_info zero_frame_info;
1208 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1209 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1211 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1212 The return address and frame pointer are treated separately.
1213 Don't consider them here. */
1214 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1215 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1216 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1218 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1219 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
1221 /* Return the bytes needed to compute the frame pointer from the current
1224 SIZE is the size needed for local variables. */
1227 m32r_compute_frame_size (size)
1228 int size; /* # of var. bytes allocated. */
1231 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1232 unsigned int reg_size;
1234 enum m32r_function_type fn_type;
1237 var_size = M32R_STACK_ALIGN (size);
1238 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1239 pretend_size = current_function_pretend_args_size;
1240 extra_size = FIRST_PARM_OFFSET (0);
1241 total_size = extra_size + pretend_size + args_size + var_size;
1245 /* See if this is an interrupt handler. Call used registers must be saved
1247 fn_type = m32r_compute_function_type (current_function_decl);
1248 interrupt_p = M32R_INTERRUPT_P (fn_type);
1250 /* Calculate space needed for registers. */
1252 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1254 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1256 reg_size += UNITS_PER_WORD;
1257 gmask |= 1 << regno;
1261 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1262 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1264 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1266 total_size += reg_size;
1268 /* ??? Not sure this is necessary, and I don't think the epilogue
1269 handler will do the right thing if this changes total_size. */
1270 total_size = M32R_STACK_ALIGN (total_size);
1272 /* Save computed information. */
1273 current_frame_info.total_size = total_size;
1274 current_frame_info.extra_size = extra_size;
1275 current_frame_info.pretend_size = pretend_size;
1276 current_frame_info.var_size = var_size;
1277 current_frame_info.args_size = args_size;
1278 current_frame_info.reg_size = reg_size;
1279 current_frame_info.gmask = gmask;
1280 current_frame_info.initialized = reload_completed;
1282 /* Ok, we're done. */
1286 /* Set up the stack and frame pointer (if desired) for the function. */
1289 m32r_output_function_prologue (file, size)
1294 int total_size, frame_size;
1295 char *sp_str = reg_names[STACK_POINTER_REGNUM];
1296 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
1297 unsigned int gmask = current_frame_info.gmask;
1298 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1300 /* If this is an interrupt handler, mark it as such. */
1301 if (M32R_INTERRUPT_P (fn_type))
1303 fprintf (file, "\t%s interrupt handler\n",
1307 /* This is only for the human reader. */
1308 fprintf (file, "\t%s BEGIN PROLOGUE %s vars= %d, regs= %d, args= %d, extra= %d\n",
1309 ASM_COMMENT_START, ASM_COMMENT_START,
1310 current_frame_info.var_size,
1311 current_frame_info.reg_size / 4,
1312 current_frame_info.args_size,
1313 current_frame_info.extra_size);
1315 total_size = (! current_frame_info.initialized
1316 ? m32r_compute_frame_size (size)
1317 : current_frame_info.total_size);
1319 /* These cases shouldn't happen. Catch them now. */
1320 if (total_size == 0 && gmask)
1324 /* Allocate space for register arguments if this is a variadic function. */
1325 if (current_frame_info.pretend_size != 0)
1326 fprintf (file, "\taddi %s,%d\n",
1327 sp_str, -current_frame_info.pretend_size);
1329 /* If there are unnamed args in registers, save them. */
1330 if (current_function_stdarg || current_function_varargs)
1333 fprintf (file, "\taddi %s,%d\n",
1334 sp_str, - M32R_MAX_PARM_REGS * UNITS_PER_WORD);
1335 for (i = 0; i < M32R_MAX_PARM_REGS; ++i)
1336 fprintf (file, "\tst %s,@(sp,%d)\n",
1337 reg_names[i], i * UNITS_PER_WORD);
1341 /* Save any registers we need to and set up fp. */
1343 if (current_frame_info.save_fp)
1344 fprintf (file, "\tpush %s\n", fp_str);
1346 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1348 /* Save any needed call-saved regs (and call-used if this is an
1349 interrupt handler). */
1350 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1352 if ((gmask & (1 << regno)) != 0)
1353 fprintf (file, "\tpush %s\n", reg_names[regno]);
1356 if (current_frame_info.save_lr)
1357 fprintf (file, "\tpush %s\n", reg_names[RETURN_ADDR_REGNUM]);
1359 /* Allocate the stack frame. */
1360 frame_size = total_size - (current_frame_info.pretend_size
1361 + current_frame_info.reg_size);
1362 if (frame_size == 0)
1363 ; /* nothing to do */
1364 else if (frame_size <= 128)
1365 fprintf (file, "\taddi %s,%d\n",
1366 sp_str, -frame_size);
1367 else if (frame_size <= 32768)
1368 fprintf (file, "\tadd3 %s,%s,%d\n",
1369 sp_str, sp_str, -frame_size);
1371 fprintf (file, "\tld24 %s,%d\n\tsub %s,%s\n",
1372 reg_names[PROLOGUE_TMP_REGNUM], frame_size,
1373 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1375 if (frame_pointer_needed)
1376 fprintf (file, "\tmv %s,%s\n", fp_str, sp_str);
1378 fprintf (file, "\t%s END PROLOGUE\n", ASM_COMMENT_START);
1381 /* Do any necessary cleanup after a function to restore stack, frame,
1385 m32r_output_function_epilogue (file, size)
1390 int noepilogue = FALSE;
1392 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1394 /* This is only for the human reader. */
1395 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1397 if (!current_frame_info.initialized)
1399 total_size = current_frame_info.total_size;
1401 if (total_size == 0)
1403 rtx insn = get_last_insn ();
1405 /* If the last insn was a BARRIER, we don't have to write any code
1406 because a jump (aka return) was put there. */
1407 if (GET_CODE (insn) == NOTE)
1408 insn = prev_nonnote_insn (insn);
1409 if (insn && GET_CODE (insn) == BARRIER)
1415 unsigned int pretend_size = current_frame_info.pretend_size;
1416 unsigned int frame_size = total_size - pretend_size;
1417 unsigned int var_size = current_frame_info.var_size;
1418 unsigned int args_size = current_frame_info.args_size;
1419 unsigned int gmask = current_frame_info.gmask;
1420 int can_trust_sp_p = !current_function_calls_alloca;
1421 char *sp_str = reg_names[STACK_POINTER_REGNUM];
1422 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
1424 /* The first thing to do is point the sp at the bottom of the register
1428 unsigned int reg_offset = var_size + args_size;
1429 if (reg_offset == 0)
1430 ; /* nothing to do */
1431 else if (reg_offset < 32768)
1432 fprintf (file, "\tadd3 %s,%s,%d\n",
1433 sp_str, sp_str, reg_offset);
1435 fprintf (file, "\tld24 %s,%d\n\tadd %s,%s\n",
1436 reg_names[PROLOGUE_TMP_REGNUM], reg_offset,
1437 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1439 else if (frame_pointer_needed)
1441 unsigned int reg_offset = var_size + args_size;
1442 if (reg_offset == 0)
1443 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1444 else if (reg_offset < 32768)
1445 fprintf (file, "\tadd3 %s,%s,%d\n",
1446 sp_str, fp_str, reg_offset);
1448 fprintf (file, "\tld24 %s,%d\n\tadd %s,%s\n",
1449 reg_names[PROLOGUE_TMP_REGNUM], reg_offset,
1450 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1455 if (current_frame_info.save_lr)
1456 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1458 /* Restore any saved registers, in reverse order of course. */
1459 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1460 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1462 if ((gmask & (1L << regno)) != 0)
1463 fprintf (file, "\tpop %s\n", reg_names[regno]);
1466 if (current_frame_info.save_fp)
1467 fprintf (file, "\tpop %s\n", fp_str);
1469 /* Remove varargs area if present. */
1470 if (current_frame_info.pretend_size != 0)
1471 fprintf (file, "\taddi %s,%d\n",
1472 sp_str, current_frame_info.pretend_size);
1474 /* Emit the return instruction. */
1475 if (M32R_INTERRUPT_P (fn_type))
1476 fprintf (file, "\trte\n");
1478 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1481 #if 0 /* no longer needed */
1482 /* Ensure the function cleanly ends on a 32 bit boundary. */
1483 fprintf (file, "\t.fillinsn\n");
1486 /* Reset state info for each function. */
1487 current_frame_info = zero_frame_info;
1488 m32r_compute_function_type (NULL_TREE);
1493 /* Emit special PIC prologues and epilogues. */
1496 m32r_finalize_pic ()
1501 /* Nested function support. */
1503 /* Emit RTL insns to initialize the variable parts of a trampoline.
1504 FNADDR is an RTX for the address of the function's pure code.
1505 CXT is an RTX for the static chain value for the function. */
1508 m32r_initialize_trampoline (tramp, fnaddr, cxt)
1509 rtx tramp, fnaddr, cxt;
1513 /* Set the cpu type and print out other fancy things,
1514 at the top of the file. */
1517 m32r_asm_file_start (file)
1520 if (flag_verbose_asm)
1521 fprintf (file, "%s M32R/D special options: -G %d\n",
1522 ASM_COMMENT_START, g_switch_value);
1525 /* Print operand X (an rtx) in assembler syntax to file FILE.
1526 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1527 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1530 m32r_print_operand (file, x, code)
1538 /* Write second word of DImode or DFmode reference,
1539 register or memory. */
1540 if (GET_CODE (x) == REG)
1541 fputs (reg_names[REGNO (x)+1], file);
1542 else if (GET_CODE (x) == MEM)
1544 fprintf (file, "@(");
1545 /* Handle possible auto-increment. Since it is pre-increment and
1546 we have already done it, we can just use an offset of four. */
1547 /* ??? This is taken from rs6000.c I think. I don't think it is
1548 currently necessary, but keep it around. */
1549 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1550 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1551 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1553 output_address (plus_constant (XEXP (x, 0), 4));
1557 output_operand_lossage ("invalid operand to %R code");
1560 case 'H' : /* High word */
1561 case 'L' : /* Low word */
1562 if (GET_CODE (x) == REG)
1564 /* L = least significant word, H = most significant word */
1565 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1566 fputs (reg_names[REGNO (x)], file);
1568 fputs (reg_names[REGNO (x)+1], file);
1570 else if (GET_CODE (x) == CONST_INT
1571 || GET_CODE (x) == CONST_DOUBLE)
1575 split_double (x, &first, &second);
1576 fprintf (file, "0x%08lx",
1577 code == 'L' ? INTVAL (first) : INTVAL (second));
1580 output_operand_lossage ("invalid operand to %H/%L code");
1588 if (GET_CODE (x) != CONST_DOUBLE
1589 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1591 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1592 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
1593 fprintf (file, "%s", str);
1597 case 'B' : /* Bottom half */
1598 case 'T' : /* Top half */
1599 /* Output the argument to a `seth' insn (sets the Top half-word).
1600 For constants output arguments to a seth/or3 pair to set Top and
1601 Bottom halves. For symbols output arguments to a seth/add3 pair to
1602 set Top and Bottom halves. The difference exists because for
1603 constants seth/or3 is more readable but for symbols we need to use
1604 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1605 switch (GET_CODE (x))
1612 split_double (x, &first, &second);
1613 x = WORDS_BIG_ENDIAN ? second : first;
1615 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
1621 ? INTVAL (x) & 0xffff
1622 : (INTVAL (x) >> 16) & 0xffff));
1628 && small_data_operand (x, VOIDmode))
1630 fputs ("sda(", file);
1631 output_addr_const (file, x);
1637 fputs (code == 'T' ? "shigh(" : "low(", file);
1638 output_addr_const (file, x);
1642 output_operand_lossage ("invalid operand to %T/%B code");
1649 /* Output a load/store with update indicator if appropriate. */
1650 if (GET_CODE (x) == MEM)
1652 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1653 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1657 output_operand_lossage ("invalid operand to %U code");
1661 /* Print a constant value negated. */
1662 if (GET_CODE (x) == CONST_INT)
1663 output_addr_const (file, GEN_INT (- INTVAL (x)));
1665 output_operand_lossage ("invalid operand to %N code");
1669 /* Print a const_int in hex. Used in comments. */
1670 if (GET_CODE (x) == CONST_INT)
1672 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
1681 fputs (IMMEDIATE_PREFIX, file);
1684 #if 0 /* ??? no longer used */
1686 fputs (reg_names[SDA_REGNUM], file);
1691 /* Do nothing special. */
1696 output_operand_lossage ("invalid operand output code");
1699 switch (GET_CODE (x))
1702 fputs (reg_names[REGNO (x)], file);
1706 fprintf (file, "@(");
1707 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1708 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
1709 GET_MODE_SIZE (GET_MODE (x))));
1710 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1711 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
1712 - GET_MODE_SIZE (GET_MODE (x))));
1714 output_address (XEXP (x, 0));
1719 /* We handle SFmode constants here as output_addr_const doesn't. */
1720 if (GET_MODE (x) == SFmode)
1725 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1726 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1727 fprintf (file, "0x%08lx", l);
1731 /* Fall through. Let output_addr_const deal with it. */
1734 output_addr_const (file, x);
1739 /* Print a memory address as an operand to reference that memory location. */
1742 m32r_print_operand_address (file, addr)
1746 register rtx base, index = 0;
1749 switch (GET_CODE (addr))
1752 fputs (reg_names[REGNO (addr)], file);
1756 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
1757 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
1758 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
1759 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
1761 base = XEXP (addr, 0), index = XEXP (addr, 1);
1762 if (GET_CODE (base) == REG)
1764 /* Print the offset first (if present) to conform to the manual. */
1768 fprintf (file, "%d,", offset);
1769 fputs (reg_names[REGNO (base)], file);
1771 /* The chip doesn't support this, but left in for generality. */
1772 else if (GET_CODE (index) == REG)
1773 fprintf (file, "%s,%s",
1774 reg_names[REGNO (base)], reg_names[REGNO (index)]);
1775 /* Not sure this can happen, but leave in for now. */
1776 else if (GET_CODE (index) == SYMBOL_REF)
1778 output_addr_const (file, index);
1780 fputs (reg_names[REGNO (base)], file);
1785 else if (GET_CODE (base) == LO_SUM)
1788 || GET_CODE (XEXP (base, 0)) != REG)
1790 if (small_data_operand (XEXP (base, 1), VOIDmode))
1791 fputs ("sda(", file);
1793 fputs ("low(", file);
1794 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
1796 fputs (reg_names[REGNO (XEXP (base, 0))], file);
1803 if (GET_CODE (XEXP (addr, 0)) != REG)
1805 if (small_data_operand (XEXP (addr, 1), VOIDmode))
1806 fputs ("sda(", file);
1808 fputs ("low(", file);
1809 output_addr_const (file, XEXP (addr, 1));
1811 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
1816 /* We shouldn't get here as we've lost the mode of the memory object
1817 (which says how much to inc/dec by). */
1822 output_addr_const (file, addr);