1 /* Target Code for R8C/M16C/M32C
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
48 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
64 static int interrupt_p (tree node);
65 static bool m32c_asm_integer (rtx, unsigned int, int);
66 static int m32c_comp_type_attributes (tree, tree);
67 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
68 static struct machine_function *m32c_init_machine_status (void);
69 static void m32c_insert_attributes (tree, tree *);
70 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
72 static bool m32c_promote_prototypes (tree);
73 static int m32c_pushm_popm (Push_Pop_Type);
74 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
75 static rtx m32c_struct_value_rtx (tree, int);
76 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
77 static int need_to_save (int);
79 #define streq(a,b) (strcmp ((a), (b)) == 0)
81 /* Internal support routines */
83 /* Debugging statements are tagged with DEBUG0 only so that they can
84 be easily enabled individually, by replacing the '0' with '1' as
90 /* This is needed by some of the commented-out debug statements
92 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
94 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
96 /* These are all to support encode_pattern(). */
97 static char pattern[30], *patternp;
98 static GTY(()) rtx patternr[30];
99 #define RTX_IS(x) (streq (pattern, x))
101 /* Some macros to simplify the logic throughout this file. */
102 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
103 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
105 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
106 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
108 /* We do most RTX matching by converting the RTX into a string, and
109 using string compares. This vastly simplifies the logic in many of
110 the functions in this file.
112 On exit, pattern[] has the encoded string (use RTX_IS("...") to
113 compare it) and patternr[] has pointers to the nodes in the RTX
114 corresponding to each character in the encoded string. The latter
115 is mostly used by print_operand().
117 Unrecognized patterns have '?' in them; this shows up when the
118 assembler complains about syntax errors.
122 encode_pattern_1 (rtx x)
126 if (patternp == pattern + sizeof (pattern) - 2)
132 patternr[patternp - pattern] = x;
134 switch (GET_CODE (x))
140 if (GET_MODE_SIZE (GET_MODE (x)) !=
141 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
143 encode_pattern_1 (XEXP (x, 0));
148 encode_pattern_1 (XEXP (x, 0));
152 encode_pattern_1 (XEXP (x, 0));
153 encode_pattern_1 (XEXP (x, 1));
157 encode_pattern_1 (XEXP (x, 0));
161 encode_pattern_1 (XEXP (x, 0));
165 encode_pattern_1 (XEXP (x, 0));
166 encode_pattern_1 (XEXP (x, 1));
170 encode_pattern_1 (XEXP (x, 0));
187 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
188 for (i = 0; i < XVECLEN (x, 0); i++)
189 encode_pattern_1 (XVECEXP (x, 0, i));
196 for (i = 0; i < XVECLEN (x, 0); i++)
197 encode_pattern_1 (XVECEXP (x, 0, i));
201 encode_pattern_1 (XEXP (x, 0));
203 encode_pattern_1 (XEXP (x, 1));
208 fprintf (stderr, "can't encode pattern %s\n",
209 GET_RTX_NAME (GET_CODE (x)));
218 encode_pattern (rtx x)
221 encode_pattern_1 (x);
225 /* Since register names indicate the mode they're used in, we need a
226 way to determine which name to refer to the register with. Called
227 by print_operand(). */
230 reg_name_with_mode (int regno, enum machine_mode mode)
232 int mlen = GET_MODE_SIZE (mode);
233 if (regno == R0_REGNO && mlen == 1)
235 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
237 if (regno == R0_REGNO && mlen == 6)
239 if (regno == R0_REGNO && mlen == 8)
241 if (regno == R1_REGNO && mlen == 1)
243 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
245 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
247 return reg_names[regno];
250 /* How many bytes a register uses on stack when it's pushed. We need
251 to know this because the push opcode needs to explicitly indicate
252 the size of the register, even though the name of the register
253 already tells it that. Used by m32c_output_reg_{push,pop}, which
254 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
257 reg_push_size (int regno)
282 static int *class_sizes = 0;
284 /* Given two register classes, find the largest intersection between
285 them. If there is no intersection, return RETURNED_IF_EMPTY
288 reduce_class (int original_class, int limiting_class, int returned_if_empty)
290 int cc = class_contents[original_class][0];
291 int i, best = NO_REGS;
294 if (original_class == limiting_class)
295 return original_class;
300 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
301 for (i = 0; i < LIM_REG_CLASSES; i++)
304 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
305 if (class_contents[i][0] & (1 << r))
310 cc &= class_contents[limiting_class][0];
311 for (i = 0; i < LIM_REG_CLASSES; i++)
313 int ic = class_contents[i][0];
316 if (best_size < class_sizes[i])
319 best_size = class_sizes[i];
324 return returned_if_empty;
328 /* Returns TRUE If there are any registers that exist in both register
331 classes_intersect (int class1, int class2)
333 return class_contents[class1][0] & class_contents[class2][0];
336 /* Used by m32c_register_move_cost to determine if a move is
337 impossibly expensive. */
339 class_can_hold_mode (int class, enum machine_mode mode)
341 /* Cache the results: 0=untested 1=no 2=yes */
342 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
343 if (results[class][mode] == 0)
346 results[class][mode] = 1;
347 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
348 if (class_contents[class][0] & (1 << r)
349 && HARD_REGNO_MODE_OK (r, mode))
352 n = HARD_REGNO_NREGS (r, mode);
353 for (i = 1; i < n; i++)
354 if (!(class_contents[class][0] & (1 << (r + i))))
358 results[class][mode] = 2;
364 fprintf (stderr, "class %s can hold %s? %s\n",
365 class_names[class], mode_name[mode],
366 (results[class][mode] == 2) ? "yes" : "no");
368 return results[class][mode] == 2;
371 /* Run-time Target Specification. */
373 /* Memregs are memory locations that gcc treats like general
374 registers, as there are a limited number of true registers and the
375 m32c families can use memory in most places that registers can be
378 However, since memory accesses are more expensive than registers,
379 we allow the user to limit the number of memregs available, in
380 order to try to persuade gcc to try harder to use real registers.
382 Memregs are provided by m32c-lib1.S.
385 int target_memregs = 16;
386 static bool target_memregs_set = FALSE;
387 int ok_to_change_target_memregs = TRUE;
389 #undef TARGET_HANDLE_OPTION
390 #define TARGET_HANDLE_OPTION m32c_handle_option
392 m32c_handle_option (size_t code,
393 const char *arg ATTRIBUTE_UNUSED,
394 int value ATTRIBUTE_UNUSED)
396 if (code == OPT_memregs_)
398 target_memregs_set = TRUE;
399 target_memregs = atoi (arg);
404 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
405 provide a default. */
407 m32c_override_options (void)
409 if (target_memregs_set)
411 if (target_memregs < 0 || target_memregs > 16)
412 error ("invalid target memregs value '%d'", target_memregs);
415 target_memregs = "16";
418 /* Defining data structures for per-function information */
420 /* The usual; we set up our machine_function data. */
421 static struct machine_function *
422 m32c_init_machine_status (void)
424 struct machine_function *machine;
426 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
431 /* Implements INIT_EXPANDERS. We just set up to call the above
434 m32c_init_expanders (void)
436 init_machine_status = m32c_init_machine_status;
441 #undef TARGET_PROMOTE_FUNCTION_RETURN
442 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
444 m32c_promote_function_return (tree fntype ATTRIBUTE_UNUSED)
449 /* Register Basics */
451 /* Basic Characteristics of Registers */
453 /* Whether a mode fits in a register is complex enough to warrant a
462 } nregs_table[FIRST_PSEUDO_REGISTER] =
464 { 1, 1, 2, 2, 4 }, /* r0 */
465 { 0, 1, 0, 0, 0 }, /* r2 */
466 { 1, 1, 2, 2, 0 }, /* r1 */
467 { 0, 1, 0, 0, 0 }, /* r3 */
468 { 0, 1, 1, 0, 0 }, /* a0 */
469 { 0, 1, 1, 0, 0 }, /* a1 */
470 { 0, 1, 1, 0, 0 }, /* sb */
471 { 0, 1, 1, 0, 0 }, /* fb */
472 { 0, 1, 1, 0, 0 }, /* sp */
473 { 1, 1, 1, 0, 0 }, /* pc */
474 { 0, 0, 0, 0, 0 }, /* fl */
475 { 1, 1, 1, 0, 0 }, /* ap */
476 { 1, 1, 2, 2, 4 }, /* mem0 */
477 { 1, 1, 2, 2, 4 }, /* mem1 */
478 { 1, 1, 2, 2, 4 }, /* mem2 */
479 { 1, 1, 2, 2, 4 }, /* mem3 */
480 { 1, 1, 2, 2, 4 }, /* mem4 */
481 { 1, 1, 2, 2, 0 }, /* mem5 */
482 { 1, 1, 2, 2, 0 }, /* mem6 */
483 { 1, 1, 0, 0, 0 }, /* mem7 */
486 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
487 available memregs, and select which registers need to be preserved
488 across calls based on the chip family. */
491 m32c_conditional_register_usage (void)
496 if (0 <= target_memregs && target_memregs <= 16)
498 /* The command line option is bytes, but our "registers" are
500 for (i = target_memregs/2; i < 8; i++)
502 fixed_regs[MEM0_REGNO + i] = 1;
503 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
507 /* M32CM and M32C preserve more registers across function calls. */
510 call_used_regs[R1_REGNO] = 0;
511 call_used_regs[R2_REGNO] = 0;
512 call_used_regs[R3_REGNO] = 0;
513 call_used_regs[A0_REGNO] = 0;
514 call_used_regs[A1_REGNO] = 0;
518 /* How Values Fit in Registers */
520 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
521 different registers are different sizes from each other, *and* may
522 be different sizes in different chip families. */
524 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
526 if (regno == FLG_REGNO && mode == CCmode)
528 if (regno >= FIRST_PSEUDO_REGISTER)
529 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
531 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
532 return (GET_MODE_SIZE (mode) + 1) / 2;
534 if (GET_MODE_SIZE (mode) <= 1)
535 return nregs_table[regno].qi_regs;
536 if (GET_MODE_SIZE (mode) <= 2)
537 return nregs_table[regno].hi_regs;
538 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
540 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
541 return nregs_table[regno].pi_regs;
542 if (GET_MODE_SIZE (mode) <= 4)
543 return nregs_table[regno].si_regs;
544 if (GET_MODE_SIZE (mode) <= 8)
545 return nregs_table[regno].di_regs;
549 /* Implements HARD_REGNO_MODE_OK. The above function does the work
550 already; just test its return value. */
552 m32c_hard_regno_ok (int regno, enum machine_mode mode)
554 return m32c_hard_regno_nregs (regno, mode) != 0;
557 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
558 registers are all different sizes. However, since most modes are
559 bigger than our registers anyway, it's easier to implement this
560 function that way, leaving QImode as the only unique case. */
562 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
564 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
567 if (m1 == QImode || m2 == QImode)
573 /* Register Classes */
575 /* Implements REGNO_REG_CLASS. */
577 m32c_regno_reg_class (int regno)
601 if (IS_MEM_REGNO (regno))
607 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
608 for certain chip families. */
610 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
612 if (memcmp (s, "Rsp", 3) == 0)
614 if (memcmp (s, "Rfb", 3) == 0)
616 if (memcmp (s, "Rsb", 3) == 0)
618 if (memcmp (s, "Rcr", 3) == 0 && TARGET_A16)
620 if (memcmp (s, "Rcl", 3) == 0 && TARGET_A24)
622 if (memcmp (s, "R0w", 3) == 0)
624 if (memcmp (s, "R1w", 3) == 0)
626 if (memcmp (s, "R2w", 3) == 0)
628 if (memcmp (s, "R3w", 3) == 0)
630 if (memcmp (s, "R02", 3) == 0)
632 if (memcmp (s, "R03", 3) == 0)
634 if (memcmp (s, "Rdi", 3) == 0)
636 if (memcmp (s, "Rhl", 3) == 0)
638 if (memcmp (s, "R23", 3) == 0)
640 if (memcmp (s, "Raa", 3) == 0)
642 if (memcmp (s, "Raw", 3) == 0 && TARGET_A16)
644 if (memcmp (s, "Ral", 3) == 0 && TARGET_A24)
646 if (memcmp (s, "Rqi", 3) == 0)
648 if (memcmp (s, "Rad", 3) == 0)
650 if (memcmp (s, "Rsi", 3) == 0)
652 if (memcmp (s, "Rhi", 3) == 0)
654 if (memcmp (s, "Rhc", 3) == 0)
656 if (memcmp (s, "Rra", 3) == 0)
658 if (memcmp (s, "Rfl", 3) == 0)
660 if (memcmp (s, "Rmm", 3) == 0)
662 if (fixed_regs[MEM0_REGNO])
667 /* PSImode registers - i.e. whatever can hold a pointer. */
668 if (memcmp (s, "Rpi", 3) == 0)
673 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
676 /* We handle this one as an EXTRA_CONSTRAINT. */
677 if (memcmp (s, "Rpa", 3) == 0)
683 /* Implements REGNO_OK_FOR_BASE_P. */
685 m32c_regno_ok_for_base_p (int regno)
687 if (regno == A0_REGNO
688 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
693 #define DEBUG_RELOAD 0
695 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
696 registers of the appropriate size. */
698 m32c_preferred_reload_class (rtx x, int rclass)
700 int newclass = rclass;
703 fprintf (stderr, "\npreferred_reload_class for %s is ",
704 class_names[rclass]);
706 if (rclass == NO_REGS)
707 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
709 if (classes_intersect (rclass, CR_REGS))
711 switch (GET_MODE (x))
717 /* newclass = HI_REGS; */
722 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
724 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
725 && ~class_contents[rclass][0] & 0x000f)
728 rclass = reduce_class (rclass, newclass, rclass);
730 if (GET_MODE (x) == QImode)
731 rclass = reduce_class (rclass, HL_REGS, rclass);
734 fprintf (stderr, "%s\n", class_names[rclass]);
737 if (GET_CODE (x) == MEM
738 && GET_CODE (XEXP (x, 0)) == PLUS
739 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
740 fprintf (stderr, "Glorm!\n");
745 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
747 m32c_preferred_output_reload_class (rtx x, int rclass)
749 return m32c_preferred_reload_class (x, rclass);
752 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
753 address registers for reloads since they're needed for address
756 m32c_limit_reload_class (enum machine_mode mode, int rclass)
759 fprintf (stderr, "limit_reload_class for %s: %s ->",
760 mode_name[mode], class_names[rclass]);
764 rclass = reduce_class (rclass, HL_REGS, rclass);
765 else if (mode == HImode)
766 rclass = reduce_class (rclass, HI_REGS, rclass);
767 else if (mode == SImode)
768 rclass = reduce_class (rclass, SI_REGS, rclass);
770 if (rclass != A_REGS)
771 rclass = reduce_class (rclass, DI_REGS, rclass);
774 fprintf (stderr, " %s\n", class_names[rclass]);
779 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
780 r0 or r1, as those are the only real QImode registers. CR regs get
781 reloaded through appropriately sized general or address
784 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
786 int cc = class_contents[rclass][0];
788 fprintf (stderr, "\nsecondary reload class %s %s\n",
789 class_names[rclass], mode_name[mode]);
793 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
795 if (classes_intersect (rclass, CR_REGS)
796 && GET_CODE (x) == REG
797 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
798 return TARGET_A16 ? HI_REGS : A_REGS;
802 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
805 m32c_class_likely_spilled_p (int regclass)
807 if (regclass == A_REGS)
809 return reg_class_size[regclass] == 1;
812 /* Implements CLASS_MAX_NREGS. We calculate this according to its
813 documented meaning, to avoid potential inconsistencies with actual
814 class definitions. */
816 m32c_class_max_nregs (int regclass, enum machine_mode mode)
820 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
821 if (class_contents[regclass][0] & (1 << rn))
823 int n = m32c_hard_regno_nregs (rn, mode);
830 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
831 QI (r0l, r1l) because the chip doesn't support QI ops on other
832 registers (well, it does on a0/a1 but if we let gcc do that, reload
833 suffers). Otherwise, we allow changes to larger modes. */
835 m32c_cannot_change_mode_class (enum machine_mode from,
836 enum machine_mode to, int rclass)
839 fprintf (stderr, "cannot change from %s to %s in %s\n",
840 mode_name[from], mode_name[to], class_names[rclass]);
844 return (class_contents[rclass][0] & 0x1ffa);
846 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
847 && GET_MODE_SIZE (from) > 1)
849 if (GET_MODE_SIZE (from) > 2) /* all other regs */
855 /* Helpers for the rest of the file. */
856 /* TRUE if the rtx is a REG rtx for the given register. */
857 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
858 && REGNO (rtx) == regno)
859 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
860 base register in address calculations (hence the "strict"
862 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
863 && (REGNO (rtx) == AP_REGNO \
864 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
866 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
867 constraints start with 'I', with the next two characters indicating
868 the type and size of the range allowed. */
870 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
871 char c ATTRIBUTE_UNUSED, const char *str)
873 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
874 [sun] bits [SUN] bytes, p=pointer size
875 I[-0-9][0-9] matches that number */
876 if (memcmp (str, "Is3", 3) == 0)
878 return (-8 <= value && value <= 7);
880 if (memcmp (str, "IS1", 3) == 0)
882 return (-128 <= value && value <= 127);
884 if (memcmp (str, "IS2", 3) == 0)
886 return (-32768 <= value && value <= 32767);
888 if (memcmp (str, "IU2", 3) == 0)
890 return (0 <= value && value <= 65535);
892 if (memcmp (str, "IU3", 3) == 0)
894 return (0 <= value && value <= 0x00ffffff);
896 if (memcmp (str, "In4", 3) == 0)
898 return (-8 <= value && value && value <= 8);
900 if (memcmp (str, "In5", 3) == 0)
902 return (-16 <= value && value && value <= 16);
904 if (memcmp (str, "IM2", 3) == 0)
906 return (-65536 <= value && value && value <= -1);
908 if (memcmp (str, "Ilb", 3) == 0)
910 int b = exact_log2 (value);
911 return (b >= 1 && b <= 8);
913 if (memcmp (str, "Ilw", 3) == 0)
915 int b = exact_log2 (value);
916 return (b >= 1 && b <= 16);
921 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
922 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
923 call return values. */
925 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
927 encode_pattern (value);
928 if (memcmp (str, "Sd", 2) == 0)
930 /* This is the common "src/dest" address */
932 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
934 if (RTX_IS ("ms") || RTX_IS ("m+si"))
938 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
942 if (REGNO (r) == SP_REGNO)
944 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
946 else if (memcmp (str, "Sa", 2) == 0)
951 else if (RTX_IS ("m+ri"))
955 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
957 else if (memcmp (str, "Si", 2) == 0)
959 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
961 else if (memcmp (str, "Ss", 2) == 0)
963 return ((RTX_IS ("mr")
964 && (IS_REG (patternr[1], SP_REGNO)))
965 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
967 else if (memcmp (str, "Sf", 2) == 0)
969 return ((RTX_IS ("mr")
970 && (IS_REG (patternr[1], FB_REGNO)))
971 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
973 else if (memcmp (str, "Sb", 2) == 0)
975 return ((RTX_IS ("mr")
976 && (IS_REG (patternr[1], SB_REGNO)))
977 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
979 else if (memcmp (str, "S1", 2) == 0)
981 return r1h_operand (value, QImode);
984 gcc_assert (str[0] != 'S');
986 if (memcmp (str, "Rpa", 2) == 0)
987 return GET_CODE (value) == PARALLEL;
992 /* This is for when we're debugging the above. */
994 m32c_extra_constraint_p (rtx value, char c, const char *str)
996 int rv = m32c_extra_constraint_p2 (value, c, str);
998 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1005 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1006 starting with 'S'. */
1008 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1013 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1014 but don't currently define any. */
1016 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1021 /* STACK AND CALLING */
1025 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1026 (yes, THREE bytes) onto the stack for the return address, but we
1027 don't support pointers bigger than 16 bits on those chips. This
1028 will likely wreak havoc with exception unwinding. FIXME. */
1030 m32c_return_addr_rtx (int count)
1032 enum machine_mode mode;
1038 /* we want 2[$fb] */
1047 /* FIXME: it's really 3 bytes */
1053 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1054 return copy_to_mode_reg (mode, ra_mem);
1057 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1059 m32c_incoming_return_addr_rtx (void)
1062 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1065 /* Exception Handling Support */
1067 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1070 m32c_eh_return_data_regno (int n)
1079 return INVALID_REGNUM;
1083 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1084 m32c_emit_eh_epilogue. */
1086 m32c_eh_return_stackadj_rtx (void)
1088 if (!cfun->machine->eh_stack_adjust)
1092 sa = gen_reg_rtx (Pmode);
1093 cfun->machine->eh_stack_adjust = sa;
1095 return cfun->machine->eh_stack_adjust;
1098 /* Registers That Address the Stack Frame */
1100 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1101 the original spec called for dwarf numbers to vary with register
1102 width as well, for example, r0l, r0, and r2r0 would each have
1103 different dwarf numbers. GCC doesn't support this, and we don't do
1104 it, and gdb seems to like it this way anyway. */
1106 m32c_dwarf_frame_regnum (int n)
1132 return DWARF_FRAME_REGISTERS + 1;
1136 /* The frame looks like this:
1138 ap -> +------------------------------
1139 | Return address (3 or 4 bytes)
1140 | Saved FB (2 or 4 bytes)
1141 fb -> +------------------------------
1144 | through r0 as needed
1145 sp -> +------------------------------
1148 /* We use this to wrap all emitted insns in the prologue. */
1152 RTX_FRAME_RELATED_P (x) = 1;
1156 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1157 how much the stack pointer moves for each, for each cpu family. */
1166 /* These are in push order. */
1167 { FB_REGNO, 0x01, 2, 4 },
1168 { SB_REGNO, 0x02, 2, 4 },
1169 { A1_REGNO, 0x04, 2, 4 },
1170 { A0_REGNO, 0x08, 2, 4 },
1171 { R3_REGNO, 0x10, 2, 2 },
1172 { R2_REGNO, 0x20, 2, 2 },
1173 { R1_REGNO, 0x40, 2, 2 },
1174 { R0_REGNO, 0x80, 2, 2 }
1177 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1179 /* Returns TRUE if we need to save/restore the given register. We
1180 save everything for exception handlers, so that any register can be
1181 unwound. For interrupt handlers, we save everything if the handler
1182 calls something else (because we don't know what *that* function
1183 might do), but try to be a bit smarter if the handler is a leaf
1184 function. We always save $a0, though, because we use that in the
1185 epilog to copy $fb to $sp. */
1187 need_to_save (int regno)
1189 if (fixed_regs[regno])
1191 if (cfun->calls_eh_return)
1193 if (regno == FP_REGNO)
1195 if (cfun->machine->is_interrupt
1196 && (!cfun->machine->is_leaf || regno == A0_REGNO))
1198 if (regs_ever_live[regno]
1199 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1204 /* This function contains all the intelligence about saving and
1205 restoring registers. It always figures out the register save set.
1206 When called with PP_justcount, it merely returns the size of the
1207 save set (for eliminating the frame pointer, for example). When
1208 called with PP_pushm or PP_popm, it emits the appropriate
1209 instructions for saving (pushm) or restoring (popm) the
1212 m32c_pushm_popm (Push_Pop_Type ppt)
1215 int byte_count = 0, bytes;
1217 rtx dwarf_set[PUSHM_N];
1219 int nosave_mask = 0;
1221 if (cfun->return_rtx
1222 && GET_CODE (cfun->return_rtx) == PARALLEL
1223 && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
1225 rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
1226 rtx rv = XEXP (exp, 0);
1227 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1230 nosave_mask |= 0x20; /* PSI, SI */
1232 nosave_mask |= 0xf0; /* DF */
1234 nosave_mask |= 0x50; /* DI */
1237 for (i = 0; i < (int) PUSHM_N; i++)
1239 /* Skip if neither register needs saving. */
1240 if (!need_to_save (pushm_info[i].reg1))
1243 if (pushm_info[i].bit & nosave_mask)
1246 reg_mask |= pushm_info[i].bit;
1247 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1249 if (ppt == PP_pushm)
1251 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1254 /* Always use stack_pointer_rtx instead of calling
1255 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1256 that there is a single rtx representing the stack pointer,
1257 namely stack_pointer_rtx, and uses == to recognize it. */
1258 addr = stack_pointer_rtx;
1260 if (byte_count != 0)
1261 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1263 dwarf_set[n_dwarfs++] =
1264 gen_rtx_SET (VOIDmode,
1265 gen_rtx_MEM (mode, addr),
1266 gen_rtx_REG (mode, pushm_info[i].reg1));
1267 F (dwarf_set[n_dwarfs - 1]);
1270 byte_count += bytes;
1273 if (cfun->machine->is_interrupt)
1275 cfun->machine->intr_pushm = reg_mask & 0xfe;
1280 if (cfun->machine->is_interrupt)
1281 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1282 if (need_to_save (i))
1285 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1288 if (ppt == PP_pushm && byte_count)
1290 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1295 XVECEXP (note, 0, 0)
1296 = gen_rtx_SET (VOIDmode,
1298 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1300 GEN_INT (-byte_count)));
1301 F (XVECEXP (note, 0, 0));
1303 for (i = 0; i < n_dwarfs; i++)
1304 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1306 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1308 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1312 if (cfun->machine->is_interrupt)
1313 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1314 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1317 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1319 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1323 if (ppt == PP_popm && byte_count)
1327 if (cfun->machine->is_interrupt)
1328 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1329 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1332 insn = emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1334 insn = emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1338 emit_insn (gen_popm (GEN_INT (reg_mask)));
1344 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1345 diagrams our call frame. */
1347 m32c_initial_elimination_offset (int from, int to)
1351 if (from == AP_REGNO)
1361 ofs += m32c_pushm_popm (PP_justcount);
1362 ofs += get_frame_size ();
1365 /* Account for push rounding. */
1367 ofs = (ofs + 1) & ~1;
1369 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1375 /* Passing Function Arguments on the Stack */
1377 #undef TARGET_PROMOTE_PROTOTYPES
1378 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1380 m32c_promote_prototypes (tree fntype ATTRIBUTE_UNUSED)
1385 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1386 M32C has word stacks. */
1388 m32c_push_rounding (int n)
1390 if (TARGET_R8C || TARGET_M16C)
1392 return (n + 1) & ~1;
1395 /* Passing Arguments in Registers */
1397 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1398 partly on stack. If our function returns a struct, a pointer to a
1399 buffer for it is at the top of the stack (last thing pushed). The
1400 first few real arguments may be in registers as follows:
1402 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1403 arg2 in r2 if it's HI (else pushed on stack)
1405 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1408 Structs are not passed in registers, even if they fit. Only
1409 integer and pointer types are passed in registers.
1411 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1414 m32c_function_arg (CUMULATIVE_ARGS * ca,
1415 enum machine_mode mode, tree type, int named)
1417 /* Can return a reg, parallel, or 0 for stack */
1420 fprintf (stderr, "func_arg %d (%s, %d)\n",
1421 ca->parm_num, mode_name[mode], named);
1425 if (mode == VOIDmode)
1428 if (ca->force_mem || !named)
1431 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1437 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1440 switch (ca->parm_num)
1443 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1444 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1448 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1449 rv = gen_rtx_REG (mode, R2_REGNO);
1459 #undef TARGET_PASS_BY_REFERENCE
1460 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1462 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1463 enum machine_mode mode ATTRIBUTE_UNUSED,
1464 tree type ATTRIBUTE_UNUSED,
1465 bool named ATTRIBUTE_UNUSED)
1470 /* Implements INIT_CUMULATIVE_ARGS. */
1472 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1473 tree fntype ATTRIBUTE_UNUSED,
1474 rtx libname ATTRIBUTE_UNUSED,
1475 tree fndecl ATTRIBUTE_UNUSED,
1476 int n_named_args ATTRIBUTE_UNUSED)
1482 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1483 returning structures, so we always reset that. Otherwise, we only
1484 need to know the sequence number of the argument to know what to do
1487 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1488 enum machine_mode mode ATTRIBUTE_UNUSED,
1489 tree type ATTRIBUTE_UNUSED,
1490 int named ATTRIBUTE_UNUSED)
1497 /* Implements FUNCTION_ARG_REGNO_P. */
1499 m32c_function_arg_regno_p (int r)
1502 return (r == R0_REGNO);
1503 return (r == R1_REGNO || r == R2_REGNO);
1506 /* How Scalar Function Values Are Returned */
1508 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1509 combination of registers starting there (r2r0 for longs, r3r1r2r0
1510 for long long, r3r2r1r0 for doubles), except that that ABI
1511 currently doesn't work because it ends up using all available
1512 general registers and gcc often can't compile it. So, instead, we
1513 return anything bigger than 16 bits in "mem0" (effectively, a
1514 memory location). */
1516 m32c_libcall_value (enum machine_mode mode)
1518 /* return reg or parallel */
1520 /* FIXME: GCC has difficulty returning large values in registers,
1521 because that ties up most of the general registers and gives the
1522 register allocator little to work with. Until we can resolve
1523 this, large values are returned in memory. */
1528 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1529 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1530 gen_rtx_REG (HImode,
1533 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1534 gen_rtx_REG (HImode,
1537 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1538 gen_rtx_REG (HImode,
1541 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1542 gen_rtx_REG (HImode,
1548 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1552 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1553 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1561 if (GET_MODE_SIZE (mode) > 2)
1562 return gen_rtx_REG (mode, MEM0_REGNO);
1563 return gen_rtx_REG (mode, R0_REGNO);
1566 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1569 m32c_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
1571 /* return reg or parallel */
1572 enum machine_mode mode = TYPE_MODE (valtype);
1573 return m32c_libcall_value (mode);
1576 /* How Large Values Are Returned */
1578 /* We return structures by pushing the address on the stack, even if
1579 we use registers for the first few "real" arguments. */
1580 #undef TARGET_STRUCT_VALUE_RTX
1581 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1583 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1584 int incoming ATTRIBUTE_UNUSED)
1589 /* Function Entry and Exit */
1591 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1593 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1595 if (cfun->machine->is_interrupt)
1600 /* Implementing the Varargs Macros */
1602 #undef TARGET_STRICT_ARGUMENT_NAMING
1603 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1605 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1610 /* Trampolines for Nested Functions */
1614 1 0000 75C43412 mov.w #0x1234,a0
1615 2 0004 FC000000 jmp.a label
1618 1 0000 BC563412 mov.l:s #0x123456,a0
1619 2 0004 CC000000 jmp.a label
1622 /* Implements TRAMPOLINE_SIZE. */
1624 m32c_trampoline_size (void)
1626 /* Allocate extra space so we can avoid the messy shifts when we
1627 initialize the trampoline; we just write past the end of the
1629 return TARGET_A16 ? 8 : 10;
1632 /* Implements TRAMPOLINE_ALIGNMENT. */
1634 m32c_trampoline_alignment (void)
1639 /* Implements INITIALIZE_TRAMPOLINE. */
1641 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1643 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1646 /* Note: we subtract a "word" because the moves want signed
1647 constants, not unsigned constants. */
1648 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1649 emit_move_insn (A0 (HImode, 2), chainval);
1650 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1651 /* We use 16 bit addresses here, but store the zero to turn it
1652 into a 24 bit offset. */
1653 emit_move_insn (A0 (HImode, 5), function);
1654 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1658 /* Note that the PSI moves actually write 4 bytes. Make sure we
1659 write stuff out in the right order, and leave room for the
1660 extra byte at the end. */
1661 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1662 emit_move_insn (A0 (PSImode, 1), chainval);
1663 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1664 emit_move_insn (A0 (PSImode, 5), function);
1669 /* Addressing Modes */
1671 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1672 wide range of non-orthogonal addressing modes, including the
1673 ability to double-indirect on *some* of them. Not all insns
1674 support all modes, either, but we rely on predicates and
1675 constraints to deal with that. */
1677 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1683 /* Wide references to memory will be split after reload, so we must
1684 ensure that all parts of such splits remain legitimate
1686 mode_adjust = GET_MODE_SIZE (mode) - 1;
1688 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1689 if (GET_CODE (x) == PRE_DEC
1690 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1692 return (GET_CODE (XEXP (x, 0)) == REG
1693 && REGNO (XEXP (x, 0)) == SP_REGNO);
1697 /* This is the double indirection detection, but it currently
1698 doesn't work as cleanly as this code implies, so until we've had
1699 a chance to debug it, leave it disabled. */
1700 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1703 fprintf (stderr, "double indirect\n");
1712 /* Most indexable registers can be used without displacements,
1713 although some of them will be emitted with an explicit zero
1714 to please the assembler. */
1715 switch (REGNO (patternr[0]))
1725 if (IS_PSEUDO (patternr[0], strict))
1732 /* This is more interesting, because different base registers
1733 allow for different displacements - both range and signedness
1734 - and it differs from chip series to chip series too. */
1735 int rn = REGNO (patternr[1]);
1736 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1742 /* The syntax only allows positive offsets, but when the
1743 offsets span the entire memory range, we can simulate
1744 negative offsets by wrapping. */
1746 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1748 return (offs >= 0 && offs <= 65535 - mode_adjust);
1750 return (offs >= -16777216 && offs <= 16777215);
1754 return (offs >= -128 && offs <= 127 - mode_adjust);
1755 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1758 return (offs >= -128 && offs <= 127 - mode_adjust);
1761 if (IS_PSEUDO (patternr[1], strict))
1766 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1768 rtx reg = patternr[1];
1770 /* We don't know where the symbol is, so only allow base
1771 registers which support displacements spanning the whole
1773 switch (REGNO (reg))
1777 /* $sb needs a secondary reload, but since it's involved in
1778 memory address reloads too, we don't deal with it very
1780 /* case SB_REGNO: */
1783 if (IS_PSEUDO (reg, strict))
1791 /* Implements REG_OK_FOR_BASE_P. */
1793 m32c_reg_ok_for_base_p (rtx x, int strict)
1795 if (GET_CODE (x) != REG)
1806 if (IS_PSEUDO (x, strict))
1812 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1813 worry about is frame base offsets, as $fb has a limited
1814 displacement range. We deal with this by attempting to reload $fb
1815 itself into an address register; that seems to result in the best
1818 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1819 rtx oldx ATTRIBUTE_UNUSED,
1820 enum machine_mode mode ATTRIBUTE_UNUSED)
1823 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1825 fprintf (stderr, "\n");
1828 if (GET_CODE (*x) == PLUS
1829 && GET_CODE (XEXP (*x, 0)) == REG
1830 && REGNO (XEXP (*x, 0)) == FB_REGNO
1831 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1832 && (INTVAL (XEXP (*x, 1)) < -128
1833 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1835 /* reload FB to A_REGS */
1837 rtx temp = gen_reg_rtx (Pmode);
1839 foo = emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1840 XEXP (*x, 0) = temp;
1847 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1849 m32c_legitimize_reload_address (rtx * x,
1850 enum machine_mode mode,
1852 int type, int ind_levels ATTRIBUTE_UNUSED)
1855 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1860 /* At one point, this function tried to get $fb copied to an address
1861 register, which in theory would maximize sharing, but gcc was
1862 *also* still trying to reload the whole address, and we'd run out
1863 of address registers. So we let gcc do the naive (but safe)
1864 reload instead, when the above function doesn't handle it for
1870 /* Used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1872 m32c_mode_dependent_address (rtx addr)
1874 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == PRE_DEC)
1879 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
1880 so we can allow anything. */
1882 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
1888 /* Condition Code Status */
1890 #undef TARGET_FIXED_CONDITION_CODE_REGS
1891 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
1893 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
1896 *p2 = INVALID_REGNUM;
1900 /* Describing Relative Costs of Operations */
1902 /* Implements REGISTER_MOVE_COST. We make impossible moves
1903 prohibitively expensive, like trying to put QIs in r2/r3 (there are
1904 no opcodes to do that). We also discourage use of mem* registers
1905 since they're really memory. */
1907 m32c_register_move_cost (enum machine_mode mode, int from, int to)
1909 int cost = COSTS_N_INSNS (3);
1910 int cc = class_contents[from][0] | class_contents[to][0];
1911 /* FIXME: pick real values, but not 2 for now. */
1912 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
1914 if (!(cc & ~class_contents[R23_REGS][0]))
1915 cost = COSTS_N_INSNS (1000);
1917 cost = COSTS_N_INSNS (80);
1920 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
1921 cost = COSTS_N_INSNS (1000);
1923 if (classes_intersect (from, CR_REGS))
1924 cost += COSTS_N_INSNS (5);
1926 if (classes_intersect (to, CR_REGS))
1927 cost += COSTS_N_INSNS (5);
1929 if (from == MEM_REGS || to == MEM_REGS)
1930 cost += COSTS_N_INSNS (50);
1931 else if (classes_intersect (from, MEM_REGS)
1932 || classes_intersect (to, MEM_REGS))
1933 cost += COSTS_N_INSNS (10);
1936 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
1937 mode_name[mode], class_names[from], class_names[to], cost);
1942 /* Implements MEMORY_MOVE_COST. */
1944 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1945 int reg_class ATTRIBUTE_UNUSED,
1946 int in ATTRIBUTE_UNUSED)
1948 /* FIXME: pick real values. */
1949 return COSTS_N_INSNS (10);
1952 /* Defining the Output Assembler Language */
1954 /* The Overall Framework of an Assembler File */
1956 #undef TARGET_HAVE_NAMED_SECTIONS
1957 #define TARGET_HAVE_NAMED_SECTIONS true
1959 /* Output of Data */
1961 /* We may have 24 bit sizes, which is the native address size.
1962 Currently unused, but provided for completeness. */
1963 #undef TARGET_ASM_INTEGER
1964 #define TARGET_ASM_INTEGER m32c_asm_integer
1966 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
1971 fprintf (asm_out_file, "\t.3byte\t");
1972 output_addr_const (asm_out_file, x);
1973 fputc ('\n', asm_out_file);
1976 return default_assemble_integer (x, size, aligned_p);
1979 /* Output of Assembler Instructions */
1981 /* We use a lookup table because the addressing modes are non-orthogonal. */
1986 char const *pattern;
1989 const conversions[] = {
1992 { 0, "mr", "z[1]" },
1993 { 0, "m+ri", "3[2]" },
1994 { 0, "m+rs", "3[2]" },
1995 { 0, "m+r+si", "4+5[2]" },
1998 { 0, "m+si", "2+3" },
2000 { 0, "mmr", "[z[2]]" },
2001 { 0, "mm+ri", "[4[3]]" },
2002 { 0, "mm+rs", "[4[3]]" },
2003 { 0, "mm+r+si", "[5+6[3]]" },
2004 { 0, "mms", "[[2]]" },
2005 { 0, "mmi", "[[2]]" },
2006 { 0, "mm+si", "[4[3]]" },
2010 { 0, "+si", "#1+2" },
2016 { 'd', "+si", "1+2" },
2019 { 'D', "+si", "1+2" },
2029 /* This is in order according to the bitfield that pushm/popm use. */
2030 static char const *pushm_regs[] = {
2031 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2034 /* Implements PRINT_OPERAND. */
2036 m32c_print_operand (FILE * file, rtx x, int code)
2041 int unsigned_const = 0;
2043 /* Multiplies; constants are converted to sign-extended format but
2044 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2056 /* This one is only for debugging; you can put it in a pattern to
2057 force this error. */
2060 fprintf (stderr, "dj: unreviewed pattern:");
2061 if (current_output_insn)
2062 debug_rtx (current_output_insn);
2065 /* PSImode operations are either .w or .l depending on the target. */
2069 fprintf (file, "w");
2071 fprintf (file, "l");
2074 /* Inverted conditionals. */
2077 switch (GET_CODE (x))
2083 fputs ("gtu", file);
2089 fputs ("geu", file);
2095 fputs ("leu", file);
2101 fputs ("ltu", file);
2114 /* Regular conditionals. */
2117 switch (GET_CODE (x))
2123 fputs ("leu", file);
2129 fputs ("ltu", file);
2135 fputs ("gtu", file);
2141 fputs ("geu", file);
2154 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2156 if (code == 'h' && GET_MODE (x) == SImode)
2158 x = m32c_subreg (HImode, x, SImode, 0);
2161 if (code == 'H' && GET_MODE (x) == SImode)
2163 x = m32c_subreg (HImode, x, SImode, 2);
2166 /* 'x' and 'X' need to be ignored for non-immediates. */
2167 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2171 for (i = 0; conversions[i].pattern; i++)
2172 if (conversions[i].code == code
2173 && streq (conversions[i].pattern, pattern))
2175 for (j = 0; conversions[i].format[j]; j++)
2176 /* backslash quotes the next character in the output pattern. */
2177 if (conversions[i].format[j] == '\\')
2179 fputc (conversions[i].format[j + 1], file);
2182 /* Digits in the output pattern indicate that the
2183 corresponding RTX is to be output at that point. */
2184 else if (ISDIGIT (conversions[i].format[j]))
2186 rtx r = patternr[conversions[i].format[j] - '0'];
2187 switch (GET_CODE (r))
2190 fprintf (file, "%s",
2191 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2198 fprintf (file, "%d", (int) exact_log2 (INTVAL (r)));
2201 /* Unsigned byte. */
2202 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2206 /* Unsigned word. */
2207 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2208 INTVAL (r) & 0xffff);
2211 /* pushm and popm encode a register set into a single byte. */
2213 for (b = 7; b >= 0; b--)
2214 if (INTVAL (r) & (1 << b))
2216 fprintf (file, "%s%s", comma, pushm_regs[b]);
2221 /* "Minus". Output -X */
2222 ival = (-INTVAL (r) & 0xffff);
2224 ival = ival - 0x10000;
2225 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2229 if (conversions[i].format[j + 1] == '[' && ival < 0)
2231 /* We can simulate negative displacements by
2232 taking advantage of address space
2233 wrapping when the offset can span the
2234 entire address range. */
2236 patternr[conversions[i].format[j + 2] - '0'];
2237 if (GET_CODE (base) == REG)
2238 switch (REGNO (base))
2243 ival = 0x1000000 + ival;
2245 ival = 0x10000 + ival;
2249 ival = 0x10000 + ival;
2253 else if (code == 'd' && ival < 0 && j == 0)
2254 /* The "mova" opcode is used to do addition by
2255 computing displacements, but again, we need
2256 displacements to be unsigned *if* they're
2257 the only component of the displacement
2258 (i.e. no "symbol-4" type displacement). */
2259 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2261 if (conversions[i].format[j] == '0')
2263 /* More conversions to unsigned. */
2264 if (unsigned_const == 2)
2266 if (unsigned_const == 1)
2269 if (streq (conversions[i].pattern, "mi")
2270 || streq (conversions[i].pattern, "mmi"))
2272 /* Integers used as addresses are unsigned. */
2273 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2275 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2280 /* We don't have const_double constants. If it
2281 happens, make it obvious. */
2282 fprintf (file, "[const_double 0x%lx]",
2283 (unsigned long) CONST_DOUBLE_HIGH (r));
2286 assemble_name (file, XSTR (r, 0));
2289 output_asm_label (r);
2292 fprintf (stderr, "don't know how to print this operand:");
2299 if (conversions[i].format[j] == 'z')
2301 /* Some addressing modes *must* have a displacement,
2302 so insert a zero here if needed. */
2304 for (k = j + 1; conversions[i].format[k]; k++)
2305 if (ISDIGIT (conversions[i].format[k]))
2307 rtx reg = patternr[conversions[i].format[k] - '0'];
2308 if (GET_CODE (reg) == REG
2309 && (REGNO (reg) == SB_REGNO
2310 || REGNO (reg) == FB_REGNO
2311 || REGNO (reg) == SP_REGNO))
2316 /* Signed displacements off symbols need to have signs
2318 if (conversions[i].format[j] == '+'
2319 && (!code || code == 'I')
2320 && ISDIGIT (conversions[i].format[j + 1])
2321 && GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2323 && INTVAL (patternr[conversions[i].format[j + 1] - '0']) <
2326 fputc (conversions[i].format[j], file);
2330 if (!conversions[i].pattern)
2332 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2335 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2341 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2342 above for descriptions of what these do. */
2344 m32c_print_operand_punct_valid_p (int c)
2346 if (c == '&' || c == '!')
2351 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2353 m32c_print_operand_address (FILE * stream, rtx address)
2355 gcc_assert (GET_CODE (address) == MEM);
2356 m32c_print_operand (stream, XEXP (address, 0), 0);
2359 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2360 differently than general registers. */
2362 m32c_output_reg_push (FILE * s, int regno)
2364 if (regno == FLG_REGNO)
2365 fprintf (s, "\tpushc\tflg\n");
2367 fprintf (s, "\tpush.%c\t%s",
2368 " bwll"[reg_push_size (regno)], reg_names[regno]);
2371 /* Likewise for ASM_OUTPUT_REG_POP. */
2373 m32c_output_reg_pop (FILE * s, int regno)
2375 if (regno == FLG_REGNO)
2376 fprintf (s, "\tpopc\tflg\n");
2378 fprintf (s, "\tpop.%c\t%s",
2379 " bwll"[reg_push_size (regno)], reg_names[regno]);
2382 /* Defining target-specific uses of `__attribute__' */
2384 /* Used to simplify the logic below. Find the attributes wherever
2386 #define M32C_ATTRIBUTES(decl) \
2387 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2388 : DECL_ATTRIBUTES (decl) \
2389 ? (DECL_ATTRIBUTES (decl)) \
2390 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2392 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2394 interrupt_p (tree node ATTRIBUTE_UNUSED)
2396 tree list = M32C_ATTRIBUTES (node);
2399 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2401 list = TREE_CHAIN (list);
2407 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2408 tree name ATTRIBUTE_UNUSED,
2409 tree args ATTRIBUTE_UNUSED,
2410 int flags ATTRIBUTE_UNUSED,
2411 bool * no_add_attrs ATTRIBUTE_UNUSED)
2416 #undef TARGET_ATTRIBUTE_TABLE
2417 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2418 static const struct attribute_spec m32c_attribute_table[] = {
2419 {"interrupt", 0, 0, false, false, false, interrupt_handler},
2420 {0, 0, 0, 0, 0, 0, 0}
2423 #undef TARGET_COMP_TYPE_ATTRIBUTES
2424 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2426 m32c_comp_type_attributes (tree type1 ATTRIBUTE_UNUSED,
2427 tree type2 ATTRIBUTE_UNUSED)
2429 /* 0=incompatible 1=compatible 2=warning */
2433 #undef TARGET_INSERT_ATTRIBUTES
2434 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2436 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2437 tree * attr_ptr ATTRIBUTE_UNUSED)
2439 /* Nothing to do here. */
2444 /* Returns TRUE if we support a move between the first two operands.
2445 At the moment, we just want to discourage mem to mem moves until
2446 after reload, because reload has a hard time with our limited
2447 number of address registers, and we can get into a situation where
2448 we need three of them when we only have two. */
2450 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2452 rtx op0 = operands[0];
2453 rtx op1 = operands[1];
2458 #define DEBUG_MOV_OK 0
2460 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2465 if (GET_CODE (op0) == SUBREG)
2466 op0 = XEXP (op0, 0);
2467 if (GET_CODE (op1) == SUBREG)
2468 op1 = XEXP (op1, 0);
2470 if (GET_CODE (op0) == MEM
2471 && GET_CODE (op1) == MEM
2472 && ! reload_completed)
2475 fprintf (stderr, " - no, mem to mem\n");
2481 fprintf (stderr, " - ok\n");
2488 /* Subregs are non-orthogonal for us, because our registers are all
2491 m32c_subreg (enum machine_mode outer,
2492 rtx x, enum machine_mode inner, int byte)
2496 /* Converting MEMs to different types that are the same size, we
2497 just rewrite them. */
2498 if (GET_CODE (x) == SUBREG
2499 && SUBREG_BYTE (x) == 0
2500 && GET_CODE (SUBREG_REG (x)) == MEM
2501 && (GET_MODE_SIZE (GET_MODE (x))
2502 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2505 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
2506 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
2509 /* Push/pop get done as smaller push/pops. */
2510 if (GET_CODE (x) == MEM
2511 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
2512 || GET_CODE (XEXP (x, 0)) == POST_INC))
2513 return gen_rtx_MEM (outer, XEXP (x, 0));
2514 if (GET_CODE (x) == SUBREG
2515 && GET_CODE (XEXP (x, 0)) == MEM
2516 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
2517 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
2518 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
2520 if (GET_CODE (x) != REG)
2521 return simplify_gen_subreg (outer, x, inner, byte);
2524 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
2525 return simplify_gen_subreg (outer, x, inner, byte);
2527 if (IS_MEM_REGNO (r))
2528 return simplify_gen_subreg (outer, x, inner, byte);
2530 /* This is where the complexities of our register layout are
2534 else if (outer == HImode)
2536 if (r == R0_REGNO && byte == 2)
2538 else if (r == R0_REGNO && byte == 4)
2540 else if (r == R0_REGNO && byte == 6)
2542 else if (r == R1_REGNO && byte == 2)
2544 else if (r == A0_REGNO && byte == 2)
2547 else if (outer == SImode)
2549 if (r == R0_REGNO && byte == 0)
2551 else if (r == R0_REGNO && byte == 4)
2556 fprintf (stderr, "m32c_subreg %s %s %d\n",
2557 mode_name[outer], mode_name[inner], byte);
2561 return gen_rtx_REG (outer, nr);
2564 /* Used to emit move instructions. We split some moves,
2565 and avoid mem-mem moves. */
2567 m32c_prepare_move (rtx * operands, enum machine_mode mode)
2569 if (TARGET_A16 && mode == PSImode)
2570 return m32c_split_move (operands, mode, 1);
2571 if ((GET_CODE (operands[0]) == MEM)
2572 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
2574 rtx pmv = XEXP (operands[0], 0);
2575 rtx dest_reg = XEXP (pmv, 0);
2576 rtx dest_mod = XEXP (pmv, 1);
2578 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
2579 operands[0] = gen_rtx_MEM (mode, dest_reg);
2581 if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
2582 operands[1] = copy_to_mode_reg (mode, operands[1]);
2586 #define DEBUG_SPLIT 0
2588 /* Returns TRUE if the given PSImode move should be split. We split
2589 for all r8c/m16c moves, since it doesn't support them, and for
2590 POP.L as we can only *push* SImode. */
2592 m32c_split_psi_p (rtx * operands)
2595 fprintf (stderr, "\nm32c_split_psi_p\n");
2596 debug_rtx (operands[0]);
2597 debug_rtx (operands[1]);
2602 fprintf (stderr, "yes, A16\n");
2606 if (GET_CODE (operands[1]) == MEM
2607 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
2610 fprintf (stderr, "yes, pop.l\n");
2615 fprintf (stderr, "no, default\n");
2620 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
2621 (define_expand), 1 if it is not optional (define_insn_and_split),
2622 and 3 for define_split (alternate api). */
2624 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
2627 int parts, si, di, rev = 0;
2628 int rv = 0, opi = 2;
2629 enum machine_mode submode = HImode;
2630 rtx *ops, local_ops[10];
2632 /* define_split modifies the existing operands, but the other two
2633 emit new insns. OPS is where we store the operand pairs, which
2644 /* Before splitting mem-mem moves, force one operand into a
2646 if (!no_new_pseudos && MEM_P (operands[0]) && MEM_P (operands[1]))
2649 fprintf (stderr, "force_reg...\n");
2650 debug_rtx (operands[1]);
2652 operands[1] = force_reg (mode, operands[1]);
2654 debug_rtx (operands[1]);
2661 fprintf (stderr, "\nsplit_move %d all=%d\n", no_new_pseudos, split_all);
2662 debug_rtx (operands[0]);
2663 debug_rtx (operands[1]);
2666 /* We don't need to split these. */
2669 && (mode == SImode || mode == PSImode)
2670 && !(GET_CODE (operands[1]) == MEM
2671 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2674 /* First, enumerate the subregs we'll be dealing with. */
2675 for (si = 0; si < parts; si++)
2678 m32c_subreg (submode, operands[0], mode,
2679 si * GET_MODE_SIZE (submode));
2681 m32c_subreg (submode, operands[1], mode,
2682 si * GET_MODE_SIZE (submode));
2685 /* Split pushes by emitting a sequence of smaller pushes. */
2686 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
2688 for (si = parts - 1; si >= 0; si--)
2690 ops[opi++] = gen_rtx_MEM (submode,
2691 gen_rtx_PRE_DEC (Pmode,
2699 /* Likewise for pops. */
2700 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
2702 for (di = 0; di < parts; di++)
2705 ops[opi++] = gen_rtx_MEM (submode,
2706 gen_rtx_POST_INC (Pmode,
2714 /* if d[di] == s[si] for any di < si, we'll early clobber. */
2715 for (di = 0; di < parts - 1; di++)
2716 for (si = di + 1; si < parts; si++)
2717 if (reg_mentioned_p (d[di], s[si]))
2721 for (si = 0; si < parts; si++)
2727 for (si = parts - 1; si >= 0; si--)
2734 /* Now emit any moves we may have accumulated. */
2735 if (rv && split_all != 3)
2738 for (i = 2; i < opi; i += 2)
2739 emit_move_insn (ops[i], ops[i + 1]);
2744 /* The m32c only has one shift, but it takes a signed count. GCC
2745 doesn't want this, so we fake it by negating any shift count when
2746 we're pretending to shift the other way. */
2748 m32c_prepare_shift (rtx * operands, int scale, int bits)
2751 if (GET_CODE (operands[2]) == CONST_INT
2752 && INTVAL (operands[2]) <= (1 << (bits - 1))
2753 && INTVAL (operands[2]) >= -(1 << (bits - 1)))
2755 operands[2] = GEN_INT (scale * INTVAL (operands[2]));
2760 temp = gen_reg_rtx (QImode);
2761 if (GET_CODE (operands[2]) == CONST_INT)
2762 temp = GEN_INT (-INTVAL (operands[2]));
2764 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
2772 /* Pattern Output Functions */
2774 /* Returns TRUE if the current function is a leaf, and thus we can
2775 determine which registers an interrupt function really needs to
2776 save. The logic below is mostly about finding the insn sequence
2777 that's the function, versus any sequence that might be open for the
2780 m32c_leaf_function_p (void)
2782 rtx saved_first, saved_last;
2783 struct sequence_stack *seq;
2786 saved_first = cfun->emit->x_first_insn;
2787 saved_last = cfun->emit->x_last_insn;
2788 for (seq = cfun->emit->sequence_stack; seq && seq->next; seq = seq->next)
2792 cfun->emit->x_first_insn = seq->first;
2793 cfun->emit->x_last_insn = seq->last;
2796 rv = leaf_function_p ();
2798 cfun->emit->x_first_insn = saved_first;
2799 cfun->emit->x_last_insn = saved_last;
2803 /* Returns TRUE if the current function needs to use the ENTER/EXIT
2804 opcodes. If the function doesn't need the frame base or stack
2805 pointer, it can use the simpler RTS opcode. */
2807 m32c_function_needs_enter (void)
2810 struct sequence_stack *seq;
2811 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
2812 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
2814 insn = get_insns ();
2815 for (seq = cfun->emit->sequence_stack;
2817 insn = seq->first, seq = seq->next);
2821 if (reg_mentioned_p (sp, insn))
2823 if (reg_mentioned_p (fb, insn))
2825 insn = NEXT_INSN (insn);
2830 /* Mark all the subexpressions of the PARALLEL rtx PAR as
2831 frame-related. Return PAR.
2833 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
2834 PARALLEL rtx other than the first if they do not have the
2835 FRAME_RELATED flag set on them. So this function is handy for
2836 marking up 'enter' instructions. */
2838 m32c_all_frame_related (rtx par)
2840 int len = XVECLEN (par, 0);
2843 for (i = 0; i < len; i++)
2844 F (XVECEXP (par, 0, i));
2849 /* Emits the prologue. See the frame layout comment earlier in this
2850 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
2851 that we manually update sp. */
2853 m32c_emit_prologue (void)
2855 int frame_size, extra_frame_size = 0, reg_save_size;
2856 int complex_prologue = 0;
2858 cfun->machine->is_leaf = m32c_leaf_function_p ();
2859 if (interrupt_p (cfun->decl))
2861 cfun->machine->is_interrupt = 1;
2862 complex_prologue = 1;
2865 reg_save_size = m32c_pushm_popm (PP_justcount);
2867 if (interrupt_p (cfun->decl))
2868 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
2871 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
2873 && !cfun->machine->is_interrupt
2874 && !m32c_function_needs_enter ())
2875 cfun->machine->use_rts = 1;
2877 if (frame_size > 254)
2879 extra_frame_size = frame_size - 254;
2882 if (cfun->machine->use_rts == 0)
2883 F (emit_insn (m32c_all_frame_related
2885 ? gen_prologue_enter_16 (GEN_INT (frame_size))
2886 : gen_prologue_enter_24 (GEN_INT (frame_size)))));
2888 if (extra_frame_size)
2890 complex_prologue = 1;
2892 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
2893 gen_rtx_REG (HImode, SP_REGNO),
2894 GEN_INT (-extra_frame_size))));
2896 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
2897 gen_rtx_REG (PSImode, SP_REGNO),
2898 GEN_INT (-extra_frame_size))));
2901 complex_prologue += m32c_pushm_popm (PP_pushm);
2903 /* This just emits a comment into the .s file for debugging. */
2904 if (complex_prologue)
2905 emit_insn (gen_prologue_end ());
2908 /* Likewise, for the epilogue. The only exception is that, for
2909 interrupts, we must manually unwind the frame as the REIT opcode
2912 m32c_emit_epilogue (void)
2914 /* This just emits a comment into the .s file for debugging. */
2915 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
2916 emit_insn (gen_epilogue_start ());
2918 m32c_pushm_popm (PP_popm);
2920 if (cfun->machine->is_interrupt)
2922 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
2924 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
2925 gen_rtx_REG (spmode, FP_REGNO));
2926 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
2927 gen_rtx_REG (spmode, A0_REGNO));
2929 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
2931 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
2932 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
2933 emit_jump_insn (gen_epilogue_reit (GEN_INT (TARGET_A16 ? 4 : 6)));
2935 else if (cfun->machine->use_rts)
2936 emit_jump_insn (gen_epilogue_rts ());
2938 emit_jump_insn (gen_epilogue_exitd (GEN_INT (TARGET_A16 ? 2 : 4)));
2943 m32c_emit_eh_epilogue (rtx ret_addr)
2945 /* R0[R2] has the stack adjustment. R1[R3] has the address to
2946 return to. We have to fudge the stack, pop everything, pop SP
2947 (fudged), and return (fudged). This is actually easier to do in
2948 assembler, so punt to libgcc. */
2949 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
2950 /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
2954 /* The Global `targetm' Variable. */
2956 struct gcc_target targetm = TARGET_INITIALIZER;
2958 #include "gt-m32c.h"