1 /* Target Code for R8C/M16C/M32C
2 Copyright (C) 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Red Hat.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
47 #include "target-def.h"
49 #include "langhooks.h"
50 #include "tree-gimple.h"
55 /* Used by m32c_pushm_popm. */
63 static tree interrupt_handler (tree *, tree, tree, int, bool *);
64 static tree function_vector_handler (tree *, tree, tree, int, bool *);
65 static int interrupt_p (tree node);
66 static bool m32c_asm_integer (rtx, unsigned int, int);
67 static int m32c_comp_type_attributes (const_tree, const_tree);
68 static bool m32c_fixed_condition_code_regs (unsigned int *, unsigned int *);
69 static struct machine_function *m32c_init_machine_status (void);
70 static void m32c_insert_attributes (tree, tree *);
71 static bool m32c_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
73 static bool m32c_promote_prototypes (const_tree);
74 static int m32c_pushm_popm (Push_Pop_Type);
75 static bool m32c_strict_argument_naming (CUMULATIVE_ARGS *);
76 static rtx m32c_struct_value_rtx (tree, int);
77 static rtx m32c_subreg (enum machine_mode, rtx, enum machine_mode, int);
78 static int need_to_save (int);
79 int current_function_special_page_vector (rtx);
81 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
83 #define streq(a,b) (strcmp ((a), (b)) == 0)
85 /* Internal support routines */
87 /* Debugging statements are tagged with DEBUG0 only so that they can
88 be easily enabled individually, by replacing the '0' with '1' as
94 /* This is needed by some of the commented-out debug statements
96 static char const *class_names[LIM_REG_CLASSES] = REG_CLASS_NAMES;
98 static int class_contents[LIM_REG_CLASSES][1] = REG_CLASS_CONTENTS;
100 /* These are all to support encode_pattern(). */
101 static char pattern[30], *patternp;
102 static GTY(()) rtx patternr[30];
103 #define RTX_IS(x) (streq (pattern, x))
105 /* Some macros to simplify the logic throughout this file. */
106 #define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
107 #define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
109 #define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
110 #define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
112 /* We do most RTX matching by converting the RTX into a string, and
113 using string compares. This vastly simplifies the logic in many of
114 the functions in this file.
116 On exit, pattern[] has the encoded string (use RTX_IS("...") to
117 compare it) and patternr[] has pointers to the nodes in the RTX
118 corresponding to each character in the encoded string. The latter
119 is mostly used by print_operand().
121 Unrecognized patterns have '?' in them; this shows up when the
122 assembler complains about syntax errors.
126 encode_pattern_1 (rtx x)
130 if (patternp == pattern + sizeof (pattern) - 2)
136 patternr[patternp - pattern] = x;
138 switch (GET_CODE (x))
144 if (GET_MODE_SIZE (GET_MODE (x)) !=
145 GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
147 encode_pattern_1 (XEXP (x, 0));
152 encode_pattern_1 (XEXP (x, 0));
156 encode_pattern_1 (XEXP (x, 0));
157 encode_pattern_1 (XEXP (x, 1));
161 encode_pattern_1 (XEXP (x, 0));
165 encode_pattern_1 (XEXP (x, 0));
169 encode_pattern_1 (XEXP (x, 0));
170 encode_pattern_1 (XEXP (x, 1));
174 encode_pattern_1 (XEXP (x, 0));
191 *patternp++ = '0' + XCINT (x, 1, UNSPEC);
192 for (i = 0; i < XVECLEN (x, 0); i++)
193 encode_pattern_1 (XVECEXP (x, 0, i));
200 for (i = 0; i < XVECLEN (x, 0); i++)
201 encode_pattern_1 (XVECEXP (x, 0, i));
205 encode_pattern_1 (XEXP (x, 0));
207 encode_pattern_1 (XEXP (x, 1));
212 fprintf (stderr, "can't encode pattern %s\n",
213 GET_RTX_NAME (GET_CODE (x)));
222 encode_pattern (rtx x)
225 encode_pattern_1 (x);
229 /* Since register names indicate the mode they're used in, we need a
230 way to determine which name to refer to the register with. Called
231 by print_operand(). */
234 reg_name_with_mode (int regno, enum machine_mode mode)
236 int mlen = GET_MODE_SIZE (mode);
237 if (regno == R0_REGNO && mlen == 1)
239 if (regno == R0_REGNO && (mlen == 3 || mlen == 4))
241 if (regno == R0_REGNO && mlen == 6)
243 if (regno == R0_REGNO && mlen == 8)
245 if (regno == R1_REGNO && mlen == 1)
247 if (regno == R1_REGNO && (mlen == 3 || mlen == 4))
249 if (regno == A0_REGNO && TARGET_A16 && (mlen == 3 || mlen == 4))
251 return reg_names[regno];
254 /* How many bytes a register uses on stack when it's pushed. We need
255 to know this because the push opcode needs to explicitly indicate
256 the size of the register, even though the name of the register
257 already tells it that. Used by m32c_output_reg_{push,pop}, which
258 is only used through calls to ASM_OUTPUT_REG_{PUSH,POP}. */
261 reg_push_size (int regno)
286 static int *class_sizes = 0;
288 /* Given two register classes, find the largest intersection between
289 them. If there is no intersection, return RETURNED_IF_EMPTY
292 reduce_class (int original_class, int limiting_class, int returned_if_empty)
294 int cc = class_contents[original_class][0];
295 int i, best = NO_REGS;
298 if (original_class == limiting_class)
299 return original_class;
304 class_sizes = (int *) xmalloc (LIM_REG_CLASSES * sizeof (int));
305 for (i = 0; i < LIM_REG_CLASSES; i++)
308 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
309 if (class_contents[i][0] & (1 << r))
314 cc &= class_contents[limiting_class][0];
315 for (i = 0; i < LIM_REG_CLASSES; i++)
317 int ic = class_contents[i][0];
320 if (best_size < class_sizes[i])
323 best_size = class_sizes[i];
328 return returned_if_empty;
332 /* Returns TRUE If there are any registers that exist in both register
335 classes_intersect (int class1, int class2)
337 return class_contents[class1][0] & class_contents[class2][0];
340 /* Used by m32c_register_move_cost to determine if a move is
341 impossibly expensive. */
343 class_can_hold_mode (int class, enum machine_mode mode)
345 /* Cache the results: 0=untested 1=no 2=yes */
346 static char results[LIM_REG_CLASSES][MAX_MACHINE_MODE];
347 if (results[class][mode] == 0)
350 results[class][mode] = 1;
351 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
352 if (class_contents[class][0] & (1 << r)
353 && HARD_REGNO_MODE_OK (r, mode))
356 n = HARD_REGNO_NREGS (r, mode);
357 for (i = 1; i < n; i++)
358 if (!(class_contents[class][0] & (1 << (r + i))))
362 results[class][mode] = 2;
368 fprintf (stderr, "class %s can hold %s? %s\n",
369 class_names[class], mode_name[mode],
370 (results[class][mode] == 2) ? "yes" : "no");
372 return results[class][mode] == 2;
375 /* Run-time Target Specification. */
377 /* Memregs are memory locations that gcc treats like general
378 registers, as there are a limited number of true registers and the
379 m32c families can use memory in most places that registers can be
382 However, since memory accesses are more expensive than registers,
383 we allow the user to limit the number of memregs available, in
384 order to try to persuade gcc to try harder to use real registers.
386 Memregs are provided by m32c-lib1.S.
389 int target_memregs = 16;
390 static bool target_memregs_set = FALSE;
391 int ok_to_change_target_memregs = TRUE;
393 #undef TARGET_HANDLE_OPTION
394 #define TARGET_HANDLE_OPTION m32c_handle_option
396 m32c_handle_option (size_t code,
397 const char *arg ATTRIBUTE_UNUSED,
398 int value ATTRIBUTE_UNUSED)
400 if (code == OPT_memregs_)
402 target_memregs_set = TRUE;
403 target_memregs = atoi (arg);
408 /* Implements OVERRIDE_OPTIONS. We limit memregs to 0..16, and
409 provide a default. */
411 m32c_override_options (void)
413 if (target_memregs_set)
415 if (target_memregs < 0 || target_memregs > 16)
416 error ("invalid target memregs value '%d'", target_memregs);
422 /* Defining data structures for per-function information */
424 /* The usual; we set up our machine_function data. */
425 static struct machine_function *
426 m32c_init_machine_status (void)
428 struct machine_function *machine;
430 (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
435 /* Implements INIT_EXPANDERS. We just set up to call the above
438 m32c_init_expanders (void)
440 init_machine_status = m32c_init_machine_status;
445 #undef TARGET_PROMOTE_FUNCTION_RETURN
446 #define TARGET_PROMOTE_FUNCTION_RETURN m32c_promote_function_return
448 m32c_promote_function_return (const_tree fntype ATTRIBUTE_UNUSED)
453 /* Register Basics */
455 /* Basic Characteristics of Registers */
457 /* Whether a mode fits in a register is complex enough to warrant a
466 } nregs_table[FIRST_PSEUDO_REGISTER] =
468 { 1, 1, 2, 2, 4 }, /* r0 */
469 { 0, 1, 0, 0, 0 }, /* r2 */
470 { 1, 1, 2, 2, 0 }, /* r1 */
471 { 0, 1, 0, 0, 0 }, /* r3 */
472 { 0, 1, 1, 0, 0 }, /* a0 */
473 { 0, 1, 1, 0, 0 }, /* a1 */
474 { 0, 1, 1, 0, 0 }, /* sb */
475 { 0, 1, 1, 0, 0 }, /* fb */
476 { 0, 1, 1, 0, 0 }, /* sp */
477 { 1, 1, 1, 0, 0 }, /* pc */
478 { 0, 0, 0, 0, 0 }, /* fl */
479 { 1, 1, 1, 0, 0 }, /* ap */
480 { 1, 1, 2, 2, 4 }, /* mem0 */
481 { 1, 1, 2, 2, 4 }, /* mem1 */
482 { 1, 1, 2, 2, 4 }, /* mem2 */
483 { 1, 1, 2, 2, 4 }, /* mem3 */
484 { 1, 1, 2, 2, 4 }, /* mem4 */
485 { 1, 1, 2, 2, 0 }, /* mem5 */
486 { 1, 1, 2, 2, 0 }, /* mem6 */
487 { 1, 1, 0, 0, 0 }, /* mem7 */
490 /* Implements CONDITIONAL_REGISTER_USAGE. We adjust the number of
491 available memregs, and select which registers need to be preserved
492 across calls based on the chip family. */
495 m32c_conditional_register_usage (void)
499 if (0 <= target_memregs && target_memregs <= 16)
501 /* The command line option is bytes, but our "registers" are
503 for (i = target_memregs/2; i < 8; i++)
505 fixed_regs[MEM0_REGNO + i] = 1;
506 CLEAR_HARD_REG_BIT (reg_class_contents[MEM_REGS], MEM0_REGNO + i);
510 /* M32CM and M32C preserve more registers across function calls. */
513 call_used_regs[R1_REGNO] = 0;
514 call_used_regs[R2_REGNO] = 0;
515 call_used_regs[R3_REGNO] = 0;
516 call_used_regs[A0_REGNO] = 0;
517 call_used_regs[A1_REGNO] = 0;
521 /* How Values Fit in Registers */
523 /* Implements HARD_REGNO_NREGS. This is complicated by the fact that
524 different registers are different sizes from each other, *and* may
525 be different sizes in different chip families. */
527 m32c_hard_regno_nregs (int regno, enum machine_mode mode)
529 if (regno == FLG_REGNO && mode == CCmode)
531 if (regno >= FIRST_PSEUDO_REGISTER)
532 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
534 if (regno >= MEM0_REGNO && regno <= MEM7_REGNO)
535 return (GET_MODE_SIZE (mode) + 1) / 2;
537 if (GET_MODE_SIZE (mode) <= 1)
538 return nregs_table[regno].qi_regs;
539 if (GET_MODE_SIZE (mode) <= 2)
540 return nregs_table[regno].hi_regs;
541 if (regno == A0_REGNO && mode == PSImode && TARGET_A16)
543 if ((GET_MODE_SIZE (mode) <= 3 || mode == PSImode) && TARGET_A24)
544 return nregs_table[regno].pi_regs;
545 if (GET_MODE_SIZE (mode) <= 4)
546 return nregs_table[regno].si_regs;
547 if (GET_MODE_SIZE (mode) <= 8)
548 return nregs_table[regno].di_regs;
552 /* Implements HARD_REGNO_MODE_OK. The above function does the work
553 already; just test its return value. */
555 m32c_hard_regno_ok (int regno, enum machine_mode mode)
557 return m32c_hard_regno_nregs (regno, mode) != 0;
560 /* Implements MODES_TIEABLE_P. In general, modes aren't tieable since
561 registers are all different sizes. However, since most modes are
562 bigger than our registers anyway, it's easier to implement this
563 function that way, leaving QImode as the only unique case. */
565 m32c_modes_tieable_p (enum machine_mode m1, enum machine_mode m2)
567 if (GET_MODE_SIZE (m1) == GET_MODE_SIZE (m2))
571 if (m1 == QImode || m2 == QImode)
578 /* Register Classes */
580 /* Implements REGNO_REG_CLASS. */
582 m32c_regno_reg_class (int regno)
606 if (IS_MEM_REGNO (regno))
612 /* Implements REG_CLASS_FROM_CONSTRAINT. Note that some constraints only match
613 for certain chip families. */
615 m32c_reg_class_from_constraint (char c ATTRIBUTE_UNUSED, const char *s)
617 if (memcmp (s, "Rsp", 3) == 0)
619 if (memcmp (s, "Rfb", 3) == 0)
621 if (memcmp (s, "Rsb", 3) == 0)
623 if (memcmp (s, "Rcr", 3) == 0)
624 return TARGET_A16 ? CR_REGS : NO_REGS;
625 if (memcmp (s, "Rcl", 3) == 0)
626 return TARGET_A24 ? CR_REGS : NO_REGS;
627 if (memcmp (s, "R0w", 3) == 0)
629 if (memcmp (s, "R1w", 3) == 0)
631 if (memcmp (s, "R2w", 3) == 0)
633 if (memcmp (s, "R3w", 3) == 0)
635 if (memcmp (s, "R02", 3) == 0)
637 if (memcmp (s, "R03", 3) == 0)
639 if (memcmp (s, "Rdi", 3) == 0)
641 if (memcmp (s, "Rhl", 3) == 0)
643 if (memcmp (s, "R23", 3) == 0)
645 if (memcmp (s, "Ra0", 3) == 0)
647 if (memcmp (s, "Ra1", 3) == 0)
649 if (memcmp (s, "Raa", 3) == 0)
651 if (memcmp (s, "Raw", 3) == 0)
652 return TARGET_A16 ? A_REGS : NO_REGS;
653 if (memcmp (s, "Ral", 3) == 0)
654 return TARGET_A24 ? A_REGS : NO_REGS;
655 if (memcmp (s, "Rqi", 3) == 0)
657 if (memcmp (s, "Rad", 3) == 0)
659 if (memcmp (s, "Rsi", 3) == 0)
661 if (memcmp (s, "Rhi", 3) == 0)
663 if (memcmp (s, "Rhc", 3) == 0)
665 if (memcmp (s, "Rra", 3) == 0)
667 if (memcmp (s, "Rfl", 3) == 0)
669 if (memcmp (s, "Rmm", 3) == 0)
671 if (fixed_regs[MEM0_REGNO])
676 /* PSImode registers - i.e. whatever can hold a pointer. */
677 if (memcmp (s, "Rpi", 3) == 0)
682 return RA_REGS; /* r2r0 and r3r1 can hold pointers. */
685 /* We handle this one as an EXTRA_CONSTRAINT. */
686 if (memcmp (s, "Rpa", 3) == 0)
691 fprintf(stderr, "unrecognized R constraint: %.3s\n", s);
698 /* Implements REGNO_OK_FOR_BASE_P. */
700 m32c_regno_ok_for_base_p (int regno)
702 if (regno == A0_REGNO
703 || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER)
708 #define DEBUG_RELOAD 0
710 /* Implements PREFERRED_RELOAD_CLASS. In general, prefer general
711 registers of the appropriate size. */
713 m32c_preferred_reload_class (rtx x, int rclass)
715 int newclass = rclass;
718 fprintf (stderr, "\npreferred_reload_class for %s is ",
719 class_names[rclass]);
721 if (rclass == NO_REGS)
722 rclass = GET_MODE (x) == QImode ? HL_REGS : R03_REGS;
724 if (classes_intersect (rclass, CR_REGS))
726 switch (GET_MODE (x))
732 /* newclass = HI_REGS; */
737 else if (newclass == QI_REGS && GET_MODE_SIZE (GET_MODE (x)) > 2)
739 else if (GET_MODE_SIZE (GET_MODE (x)) > 4
740 && ~class_contents[rclass][0] & 0x000f)
743 rclass = reduce_class (rclass, newclass, rclass);
745 if (GET_MODE (x) == QImode)
746 rclass = reduce_class (rclass, HL_REGS, rclass);
749 fprintf (stderr, "%s\n", class_names[rclass]);
752 if (GET_CODE (x) == MEM
753 && GET_CODE (XEXP (x, 0)) == PLUS
754 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
755 fprintf (stderr, "Glorm!\n");
760 /* Implements PREFERRED_OUTPUT_RELOAD_CLASS. */
762 m32c_preferred_output_reload_class (rtx x, int rclass)
764 return m32c_preferred_reload_class (x, rclass);
767 /* Implements LIMIT_RELOAD_CLASS. We basically want to avoid using
768 address registers for reloads since they're needed for address
771 m32c_limit_reload_class (enum machine_mode mode, int rclass)
774 fprintf (stderr, "limit_reload_class for %s: %s ->",
775 mode_name[mode], class_names[rclass]);
779 rclass = reduce_class (rclass, HL_REGS, rclass);
780 else if (mode == HImode)
781 rclass = reduce_class (rclass, HI_REGS, rclass);
782 else if (mode == SImode)
783 rclass = reduce_class (rclass, SI_REGS, rclass);
785 if (rclass != A_REGS)
786 rclass = reduce_class (rclass, DI_REGS, rclass);
789 fprintf (stderr, " %s\n", class_names[rclass]);
794 /* Implements SECONDARY_RELOAD_CLASS. QImode have to be reloaded in
795 r0 or r1, as those are the only real QImode registers. CR regs get
796 reloaded through appropriately sized general or address
799 m32c_secondary_reload_class (int rclass, enum machine_mode mode, rtx x)
801 int cc = class_contents[rclass][0];
803 fprintf (stderr, "\nsecondary reload class %s %s\n",
804 class_names[rclass], mode_name[mode]);
808 && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
810 if (classes_intersect (rclass, CR_REGS)
811 && GET_CODE (x) == REG
812 && REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
813 return TARGET_A16 ? HI_REGS : A_REGS;
817 /* Implements CLASS_LIKELY_SPILLED_P. A_REGS is needed for address
820 m32c_class_likely_spilled_p (int regclass)
822 if (regclass == A_REGS)
824 return reg_class_size[regclass] == 1;
827 /* Implements CLASS_MAX_NREGS. We calculate this according to its
828 documented meaning, to avoid potential inconsistencies with actual
829 class definitions. */
831 m32c_class_max_nregs (int regclass, enum machine_mode mode)
835 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
836 if (class_contents[regclass][0] & (1 << rn))
838 int n = m32c_hard_regno_nregs (rn, mode);
845 /* Implements CANNOT_CHANGE_MODE_CLASS. Only r0 and r1 can change to
846 QI (r0l, r1l) because the chip doesn't support QI ops on other
847 registers (well, it does on a0/a1 but if we let gcc do that, reload
848 suffers). Otherwise, we allow changes to larger modes. */
850 m32c_cannot_change_mode_class (enum machine_mode from,
851 enum machine_mode to, int rclass)
855 fprintf (stderr, "cannot change from %s to %s in %s\n",
856 mode_name[from], mode_name[to], class_names[rclass]);
859 /* If the larger mode isn't allowed in any of these registers, we
860 can't allow the change. */
861 for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)
862 if (class_contents[rclass][0] & (1 << rn))
863 if (! m32c_hard_regno_ok (rn, to))
867 return (class_contents[rclass][0] & 0x1ffa);
869 if (class_contents[rclass][0] & 0x0005 /* r0, r1 */
870 && GET_MODE_SIZE (from) > 1)
872 if (GET_MODE_SIZE (from) > 2) /* all other regs */
878 /* Helpers for the rest of the file. */
879 /* TRUE if the rtx is a REG rtx for the given register. */
880 #define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
881 && REGNO (rtx) == regno)
882 /* TRUE if the rtx is a pseudo - specifically, one we can use as a
883 base register in address calculations (hence the "strict"
885 #define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
886 && (REGNO (rtx) == AP_REGNO \
887 || REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
889 /* Implements CONST_OK_FOR_CONSTRAINT_P. Currently, all constant
890 constraints start with 'I', with the next two characters indicating
891 the type and size of the range allowed. */
893 m32c_const_ok_for_constraint_p (HOST_WIDE_INT value,
894 char c ATTRIBUTE_UNUSED, const char *str)
896 /* s=signed u=unsigned n=nonzero m=minus l=log2able,
897 [sun] bits [SUN] bytes, p=pointer size
898 I[-0-9][0-9] matches that number */
899 if (memcmp (str, "Is3", 3) == 0)
901 return (-8 <= value && value <= 7);
903 if (memcmp (str, "IS1", 3) == 0)
905 return (-128 <= value && value <= 127);
907 if (memcmp (str, "IS2", 3) == 0)
909 return (-32768 <= value && value <= 32767);
911 if (memcmp (str, "IU2", 3) == 0)
913 return (0 <= value && value <= 65535);
915 if (memcmp (str, "IU3", 3) == 0)
917 return (0 <= value && value <= 0x00ffffff);
919 if (memcmp (str, "In4", 3) == 0)
921 return (-8 <= value && value && value <= 8);
923 if (memcmp (str, "In5", 3) == 0)
925 return (-16 <= value && value && value <= 16);
927 if (memcmp (str, "In6", 3) == 0)
929 return (-32 <= value && value && value <= 32);
931 if (memcmp (str, "IM2", 3) == 0)
933 return (-65536 <= value && value && value <= -1);
935 if (memcmp (str, "Ilb", 3) == 0)
937 int b = exact_log2 (value);
938 return (b >= 0 && b <= 7);
940 if (memcmp (str, "Imb", 3) == 0)
942 int b = exact_log2 ((value ^ 0xff) & 0xff);
943 return (b >= 0 && b <= 7);
945 if (memcmp (str, "Ilw", 3) == 0)
947 int b = exact_log2 (value);
948 return (b >= 0 && b <= 15);
950 if (memcmp (str, "Imw", 3) == 0)
952 int b = exact_log2 ((value ^ 0xffff) & 0xffff);
953 return (b >= 0 && b <= 15);
955 if (memcmp (str, "I00", 3) == 0)
962 /* Implements EXTRA_CONSTRAINT_STR (see next function too). 'S' is
963 for memory constraints, plus "Rpa" for PARALLEL rtx's we use for
964 call return values. */
966 m32c_extra_constraint_p2 (rtx value, char c ATTRIBUTE_UNUSED, const char *str)
968 encode_pattern (value);
969 if (memcmp (str, "Sd", 2) == 0)
971 /* This is the common "src/dest" address */
973 if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
975 if (RTX_IS ("ms") || RTX_IS ("m+si"))
977 if (RTX_IS ("m++rii"))
979 if (REGNO (patternr[3]) == FB_REGNO
980 && INTVAL (patternr[4]) == 0)
985 else if (RTX_IS ("m+ri") || RTX_IS ("m+rs") || RTX_IS ("m+r+si"))
989 if (REGNO (r) == SP_REGNO)
991 return m32c_legitimate_address_p (GET_MODE (value), XEXP (value, 0), 1);
993 else if (memcmp (str, "Sa", 2) == 0)
998 else if (RTX_IS ("m+ri"))
1002 return (IS_REG (r, A0_REGNO) || IS_REG (r, A1_REGNO));
1004 else if (memcmp (str, "Si", 2) == 0)
1006 return (RTX_IS ("mi") || RTX_IS ("ms") || RTX_IS ("m+si"));
1008 else if (memcmp (str, "Ss", 2) == 0)
1010 return ((RTX_IS ("mr")
1011 && (IS_REG (patternr[1], SP_REGNO)))
1012 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SP_REGNO))));
1014 else if (memcmp (str, "Sf", 2) == 0)
1016 return ((RTX_IS ("mr")
1017 && (IS_REG (patternr[1], FB_REGNO)))
1018 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], FB_REGNO))));
1020 else if (memcmp (str, "Sb", 2) == 0)
1022 return ((RTX_IS ("mr")
1023 && (IS_REG (patternr[1], SB_REGNO)))
1024 || (RTX_IS ("m+ri") && (IS_REG (patternr[2], SB_REGNO))));
1026 else if (memcmp (str, "Sp", 2) == 0)
1028 /* Absolute addresses 0..0x1fff used for bit addressing (I/O ports) */
1029 return (RTX_IS ("mi")
1030 && !(INTVAL (patternr[1]) & ~0x1fff));
1032 else if (memcmp (str, "S1", 2) == 0)
1034 return r1h_operand (value, QImode);
1037 gcc_assert (str[0] != 'S');
1039 if (memcmp (str, "Rpa", 2) == 0)
1040 return GET_CODE (value) == PARALLEL;
1045 /* This is for when we're debugging the above. */
1047 m32c_extra_constraint_p (rtx value, char c, const char *str)
1049 int rv = m32c_extra_constraint_p2 (value, c, str);
1051 fprintf (stderr, "\nconstraint %.*s: %d\n", CONSTRAINT_LEN (c, str), str,
1058 /* Implements EXTRA_MEMORY_CONSTRAINT. Currently, we only use strings
1059 starting with 'S'. */
1061 m32c_extra_memory_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1066 /* Implements EXTRA_ADDRESS_CONSTRAINT. We reserve 'A' strings for these,
1067 but don't currently define any. */
1069 m32c_extra_address_constraint (char c, const char *str ATTRIBUTE_UNUSED)
1074 /* STACK AND CALLING */
1078 /* Implements RETURN_ADDR_RTX. Note that R8C and M16C push 24 bits
1079 (yes, THREE bytes) onto the stack for the return address, but we
1080 don't support pointers bigger than 16 bits on those chips. This
1081 will likely wreak havoc with exception unwinding. FIXME. */
1083 m32c_return_addr_rtx (int count)
1085 enum machine_mode mode;
1091 /* we want 2[$fb] */
1100 /* FIXME: it's really 3 bytes */
1106 gen_rtx_MEM (mode, plus_constant (gen_rtx_REG (Pmode, FP_REGNO), offset));
1107 return copy_to_mode_reg (mode, ra_mem);
1110 /* Implements INCOMING_RETURN_ADDR_RTX. See comment above. */
1112 m32c_incoming_return_addr_rtx (void)
1115 return gen_rtx_MEM (PSImode, gen_rtx_REG (PSImode, SP_REGNO));
1118 /* Exception Handling Support */
1120 /* Implements EH_RETURN_DATA_REGNO. Choose registers able to hold
1123 m32c_eh_return_data_regno (int n)
1135 return INVALID_REGNUM;
1139 /* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
1140 m32c_emit_eh_epilogue. */
1142 m32c_eh_return_stackadj_rtx (void)
1144 if (!cfun->machine->eh_stack_adjust)
1148 sa = gen_rtx_REG (Pmode, R0_REGNO);
1149 cfun->machine->eh_stack_adjust = sa;
1151 return cfun->machine->eh_stack_adjust;
1154 /* Registers That Address the Stack Frame */
1156 /* Implements DWARF_FRAME_REGNUM and DBX_REGISTER_NUMBER. Note that
1157 the original spec called for dwarf numbers to vary with register
1158 width as well, for example, r0l, r0, and r2r0 would each have
1159 different dwarf numbers. GCC doesn't support this, and we don't do
1160 it, and gdb seems to like it this way anyway. */
1162 m32c_dwarf_frame_regnum (int n)
1188 return DWARF_FRAME_REGISTERS + 1;
1192 /* The frame looks like this:
1194 ap -> +------------------------------
1195 | Return address (3 or 4 bytes)
1196 | Saved FB (2 or 4 bytes)
1197 fb -> +------------------------------
1200 | through r0 as needed
1201 sp -> +------------------------------
1204 /* We use this to wrap all emitted insns in the prologue. */
1208 RTX_FRAME_RELATED_P (x) = 1;
1212 /* This maps register numbers to the PUSHM/POPM bitfield, and tells us
1213 how much the stack pointer moves for each, for each cpu family. */
1222 /* These are in reverse push (nearest-to-sp) order. */
1223 { R0_REGNO, 0x80, 2, 2 },
1224 { R1_REGNO, 0x40, 2, 2 },
1225 { R2_REGNO, 0x20, 2, 2 },
1226 { R3_REGNO, 0x10, 2, 2 },
1227 { A0_REGNO, 0x08, 2, 4 },
1228 { A1_REGNO, 0x04, 2, 4 },
1229 { SB_REGNO, 0x02, 2, 4 },
1230 { FB_REGNO, 0x01, 2, 4 }
1233 #define PUSHM_N (sizeof(pushm_info)/sizeof(pushm_info[0]))
1235 /* Returns TRUE if we need to save/restore the given register. We
1236 save everything for exception handlers, so that any register can be
1237 unwound. For interrupt handlers, we save everything if the handler
1238 calls something else (because we don't know what *that* function
1239 might do), but try to be a bit smarter if the handler is a leaf
1240 function. We always save $a0, though, because we use that in the
1241 epilogue to copy $fb to $sp. */
1243 need_to_save (int regno)
1245 if (fixed_regs[regno])
1247 if (cfun->calls_eh_return)
1249 if (regno == FP_REGNO)
1251 if (cfun->machine->is_interrupt
1252 && (!cfun->machine->is_leaf || regno == A0_REGNO))
1254 if (df_regs_ever_live_p (regno)
1255 && (!call_used_regs[regno] || cfun->machine->is_interrupt))
1260 /* This function contains all the intelligence about saving and
1261 restoring registers. It always figures out the register save set.
1262 When called with PP_justcount, it merely returns the size of the
1263 save set (for eliminating the frame pointer, for example). When
1264 called with PP_pushm or PP_popm, it emits the appropriate
1265 instructions for saving (pushm) or restoring (popm) the
1268 m32c_pushm_popm (Push_Pop_Type ppt)
1271 int byte_count = 0, bytes;
1273 rtx dwarf_set[PUSHM_N];
1275 int nosave_mask = 0;
1277 if (cfun->return_rtx
1278 && GET_CODE (cfun->return_rtx) == PARALLEL
1279 && !(cfun->calls_eh_return || cfun->machine->is_interrupt))
1281 rtx exp = XVECEXP (cfun->return_rtx, 0, 0);
1282 rtx rv = XEXP (exp, 0);
1283 int rv_bytes = GET_MODE_SIZE (GET_MODE (rv));
1286 nosave_mask |= 0x20; /* PSI, SI */
1288 nosave_mask |= 0xf0; /* DF */
1290 nosave_mask |= 0x50; /* DI */
1293 for (i = 0; i < (int) PUSHM_N; i++)
1295 /* Skip if neither register needs saving. */
1296 if (!need_to_save (pushm_info[i].reg1))
1299 if (pushm_info[i].bit & nosave_mask)
1302 reg_mask |= pushm_info[i].bit;
1303 bytes = TARGET_A16 ? pushm_info[i].a16_bytes : pushm_info[i].a24_bytes;
1305 if (ppt == PP_pushm)
1307 enum machine_mode mode = (bytes == 2) ? HImode : SImode;
1310 /* Always use stack_pointer_rtx instead of calling
1311 rtx_gen_REG ourselves. Code elsewhere in GCC assumes
1312 that there is a single rtx representing the stack pointer,
1313 namely stack_pointer_rtx, and uses == to recognize it. */
1314 addr = stack_pointer_rtx;
1316 if (byte_count != 0)
1317 addr = gen_rtx_PLUS (GET_MODE (addr), addr, GEN_INT (byte_count));
1319 dwarf_set[n_dwarfs++] =
1320 gen_rtx_SET (VOIDmode,
1321 gen_rtx_MEM (mode, addr),
1322 gen_rtx_REG (mode, pushm_info[i].reg1));
1323 F (dwarf_set[n_dwarfs - 1]);
1326 byte_count += bytes;
1329 if (cfun->machine->is_interrupt)
1331 cfun->machine->intr_pushm = reg_mask & 0xfe;
1336 if (cfun->machine->is_interrupt)
1337 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1338 if (need_to_save (i))
1341 cfun->machine->intr_pushmem[i - MEM0_REGNO] = 1;
1344 if (ppt == PP_pushm && byte_count)
1346 rtx note = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (n_dwarfs + 1));
1351 XVECEXP (note, 0, 0)
1352 = gen_rtx_SET (VOIDmode,
1354 gen_rtx_PLUS (GET_MODE (stack_pointer_rtx),
1356 GEN_INT (-byte_count)));
1357 F (XVECEXP (note, 0, 0));
1359 for (i = 0; i < n_dwarfs; i++)
1360 XVECEXP (note, 0, i + 1) = dwarf_set[i];
1362 pushm = F (emit_insn (gen_pushm (GEN_INT (reg_mask))));
1364 REG_NOTES (pushm) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, note,
1368 if (cfun->machine->is_interrupt)
1369 for (i = MEM0_REGNO; i <= MEM7_REGNO; i++)
1370 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1373 pushm = emit_insn (gen_pushhi_16 (gen_rtx_REG (HImode, i)));
1375 pushm = emit_insn (gen_pushhi_24 (gen_rtx_REG (HImode, i)));
1379 if (ppt == PP_popm && byte_count)
1381 if (cfun->machine->is_interrupt)
1382 for (i = MEM7_REGNO; i >= MEM0_REGNO; i--)
1383 if (cfun->machine->intr_pushmem[i - MEM0_REGNO])
1386 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, i)));
1388 emit_insn (gen_pophi_24 (gen_rtx_REG (HImode, i)));
1391 emit_insn (gen_popm (GEN_INT (reg_mask)));
1397 /* Implements INITIAL_ELIMINATION_OFFSET. See the comment above that
1398 diagrams our call frame. */
1400 m32c_initial_elimination_offset (int from, int to)
1404 if (from == AP_REGNO)
1414 ofs += m32c_pushm_popm (PP_justcount);
1415 ofs += get_frame_size ();
1418 /* Account for push rounding. */
1420 ofs = (ofs + 1) & ~1;
1422 fprintf (stderr, "initial_elimination_offset from=%d to=%d, ofs=%d\n", from,
1428 /* Passing Function Arguments on the Stack */
1430 #undef TARGET_PROMOTE_PROTOTYPES
1431 #define TARGET_PROMOTE_PROTOTYPES m32c_promote_prototypes
1433 m32c_promote_prototypes (const_tree fntype ATTRIBUTE_UNUSED)
1438 /* Implements PUSH_ROUNDING. The R8C and M16C have byte stacks, the
1439 M32C has word stacks. */
1441 m32c_push_rounding (int n)
1443 if (TARGET_R8C || TARGET_M16C)
1445 return (n + 1) & ~1;
1448 /* Passing Arguments in Registers */
1450 /* Implements FUNCTION_ARG. Arguments are passed partly in registers,
1451 partly on stack. If our function returns a struct, a pointer to a
1452 buffer for it is at the top of the stack (last thing pushed). The
1453 first few real arguments may be in registers as follows:
1455 R8C/M16C: arg1 in r1 if it's QI or HI (else it's pushed on stack)
1456 arg2 in r2 if it's HI (else pushed on stack)
1458 M32C: arg1 in r0 if it's QI or HI (else it's pushed on stack)
1461 Structs are not passed in registers, even if they fit. Only
1462 integer and pointer types are passed in registers.
1464 Note that when arg1 doesn't fit in r1, arg2 may still be passed in
1467 m32c_function_arg (CUMULATIVE_ARGS * ca,
1468 enum machine_mode mode, tree type, int named)
1470 /* Can return a reg, parallel, or 0 for stack */
1473 fprintf (stderr, "func_arg %d (%s, %d)\n",
1474 ca->parm_num, mode_name[mode], named);
1478 if (mode == VOIDmode)
1481 if (ca->force_mem || !named)
1484 fprintf (stderr, "func arg: force %d named %d, mem\n", ca->force_mem,
1490 if (type && INTEGRAL_TYPE_P (type) && POINTER_TYPE_P (type))
1493 if (type && AGGREGATE_TYPE_P (type))
1496 switch (ca->parm_num)
1499 if (GET_MODE_SIZE (mode) == 1 || GET_MODE_SIZE (mode) == 2)
1500 rv = gen_rtx_REG (mode, TARGET_A16 ? R1_REGNO : R0_REGNO);
1504 if (TARGET_A16 && GET_MODE_SIZE (mode) == 2)
1505 rv = gen_rtx_REG (mode, R2_REGNO);
1515 #undef TARGET_PASS_BY_REFERENCE
1516 #define TARGET_PASS_BY_REFERENCE m32c_pass_by_reference
1518 m32c_pass_by_reference (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,
1519 enum machine_mode mode ATTRIBUTE_UNUSED,
1520 const_tree type ATTRIBUTE_UNUSED,
1521 bool named ATTRIBUTE_UNUSED)
1526 /* Implements INIT_CUMULATIVE_ARGS. */
1528 m32c_init_cumulative_args (CUMULATIVE_ARGS * ca,
1530 rtx libname ATTRIBUTE_UNUSED,
1532 int n_named_args ATTRIBUTE_UNUSED)
1534 if (fntype && aggregate_value_p (TREE_TYPE (fntype), fndecl))
1541 /* Implements FUNCTION_ARG_ADVANCE. force_mem is set for functions
1542 returning structures, so we always reset that. Otherwise, we only
1543 need to know the sequence number of the argument to know what to do
1546 m32c_function_arg_advance (CUMULATIVE_ARGS * ca,
1547 enum machine_mode mode ATTRIBUTE_UNUSED,
1548 tree type ATTRIBUTE_UNUSED,
1549 int named ATTRIBUTE_UNUSED)
1557 /* Implements FUNCTION_ARG_REGNO_P. */
1559 m32c_function_arg_regno_p (int r)
1562 return (r == R0_REGNO);
1563 return (r == R1_REGNO || r == R2_REGNO);
1566 /* HImode and PSImode are the two "native" modes as far as GCC is
1567 concerned, but the chips also support a 32-bit mode which is used
1568 for some opcodes in R8C/M16C and for reset vectors and such. */
1569 #undef TARGET_VALID_POINTER_MODE
1570 #define TARGET_VALID_POINTER_MODE m32c_valid_pointer_mode
1572 m32c_valid_pointer_mode (enum machine_mode mode)
1582 /* How Scalar Function Values Are Returned */
1584 /* Implements LIBCALL_VALUE. Most values are returned in $r0, or some
1585 combination of registers starting there (r2r0 for longs, r3r1r2r0
1586 for long long, r3r2r1r0 for doubles), except that that ABI
1587 currently doesn't work because it ends up using all available
1588 general registers and gcc often can't compile it. So, instead, we
1589 return anything bigger than 16 bits in "mem0" (effectively, a
1590 memory location). */
1592 m32c_libcall_value (enum machine_mode mode)
1594 /* return reg or parallel */
1596 /* FIXME: GCC has difficulty returning large values in registers,
1597 because that ties up most of the general registers and gives the
1598 register allocator little to work with. Until we can resolve
1599 this, large values are returned in memory. */
1604 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (4));
1605 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1606 gen_rtx_REG (HImode,
1609 XVECEXP (rv, 0, 1) = gen_rtx_EXPR_LIST (VOIDmode,
1610 gen_rtx_REG (HImode,
1613 XVECEXP (rv, 0, 2) = gen_rtx_EXPR_LIST (VOIDmode,
1614 gen_rtx_REG (HImode,
1617 XVECEXP (rv, 0, 3) = gen_rtx_EXPR_LIST (VOIDmode,
1618 gen_rtx_REG (HImode,
1624 if (TARGET_A24 && GET_MODE_SIZE (mode) > 2)
1628 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (1));
1629 XVECEXP (rv, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode,
1637 if (GET_MODE_SIZE (mode) > 2)
1638 return gen_rtx_REG (mode, MEM0_REGNO);
1639 return gen_rtx_REG (mode, R0_REGNO);
1642 /* Implements FUNCTION_VALUE. Functions and libcalls have the same
1645 m32c_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
1647 /* return reg or parallel */
1648 const enum machine_mode mode = TYPE_MODE (valtype);
1649 return m32c_libcall_value (mode);
1652 /* How Large Values Are Returned */
1654 /* We return structures by pushing the address on the stack, even if
1655 we use registers for the first few "real" arguments. */
1656 #undef TARGET_STRUCT_VALUE_RTX
1657 #define TARGET_STRUCT_VALUE_RTX m32c_struct_value_rtx
1659 m32c_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1660 int incoming ATTRIBUTE_UNUSED)
1665 /* Function Entry and Exit */
1667 /* Implements EPILOGUE_USES. Interrupts restore all registers. */
1669 m32c_epilogue_uses (int regno ATTRIBUTE_UNUSED)
1671 if (cfun->machine->is_interrupt)
1676 /* Implementing the Varargs Macros */
1678 #undef TARGET_STRICT_ARGUMENT_NAMING
1679 #define TARGET_STRICT_ARGUMENT_NAMING m32c_strict_argument_naming
1681 m32c_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
1686 /* Trampolines for Nested Functions */
1690 1 0000 75C43412 mov.w #0x1234,a0
1691 2 0004 FC000000 jmp.a label
1694 1 0000 BC563412 mov.l:s #0x123456,a0
1695 2 0004 CC000000 jmp.a label
1698 /* Implements TRAMPOLINE_SIZE. */
1700 m32c_trampoline_size (void)
1702 /* Allocate extra space so we can avoid the messy shifts when we
1703 initialize the trampoline; we just write past the end of the
1705 return TARGET_A16 ? 8 : 10;
1708 /* Implements TRAMPOLINE_ALIGNMENT. */
1710 m32c_trampoline_alignment (void)
1715 /* Implements INITIALIZE_TRAMPOLINE. */
1717 m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
1719 #define A0(m,i) gen_rtx_MEM (m, plus_constant (tramp, i))
1722 /* Note: we subtract a "word" because the moves want signed
1723 constants, not unsigned constants. */
1724 emit_move_insn (A0 (HImode, 0), GEN_INT (0xc475 - 0x10000));
1725 emit_move_insn (A0 (HImode, 2), chainval);
1726 emit_move_insn (A0 (QImode, 4), GEN_INT (0xfc - 0x100));
1727 /* We use 16-bit addresses here, but store the zero to turn it
1728 into a 24-bit offset. */
1729 emit_move_insn (A0 (HImode, 5), function);
1730 emit_move_insn (A0 (QImode, 7), GEN_INT (0x00));
1734 /* Note that the PSI moves actually write 4 bytes. Make sure we
1735 write stuff out in the right order, and leave room for the
1736 extra byte at the end. */
1737 emit_move_insn (A0 (QImode, 0), GEN_INT (0xbc - 0x100));
1738 emit_move_insn (A0 (PSImode, 1), chainval);
1739 emit_move_insn (A0 (QImode, 4), GEN_INT (0xcc - 0x100));
1740 emit_move_insn (A0 (PSImode, 5), function);
1745 /* Implicit Calls to Library Routines */
1747 #undef TARGET_INIT_LIBFUNCS
1748 #define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
1750 m32c_init_libfuncs (void)
1754 /* We do this because the M32C has an HImode operand, but the
1755 M16C has an 8-bit operand. Since gcc looks at the match data
1756 and not the expanded rtl, we have to reset the array so that
1757 the right modes are found. */
1758 setcc_gen_code[EQ] = CODE_FOR_seq_24;
1759 setcc_gen_code[NE] = CODE_FOR_sne_24;
1760 setcc_gen_code[GT] = CODE_FOR_sgt_24;
1761 setcc_gen_code[GE] = CODE_FOR_sge_24;
1762 setcc_gen_code[LT] = CODE_FOR_slt_24;
1763 setcc_gen_code[LE] = CODE_FOR_sle_24;
1764 setcc_gen_code[GTU] = CODE_FOR_sgtu_24;
1765 setcc_gen_code[GEU] = CODE_FOR_sgeu_24;
1766 setcc_gen_code[LTU] = CODE_FOR_sltu_24;
1767 setcc_gen_code[LEU] = CODE_FOR_sleu_24;
1771 /* Addressing Modes */
1773 /* Used by GO_IF_LEGITIMATE_ADDRESS. The r8c/m32c family supports a
1774 wide range of non-orthogonal addressing modes, including the
1775 ability to double-indirect on *some* of them. Not all insns
1776 support all modes, either, but we rely on predicates and
1777 constraints to deal with that. */
1779 m32c_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1785 /* Wide references to memory will be split after reload, so we must
1786 ensure that all parts of such splits remain legitimate
1788 mode_adjust = GET_MODE_SIZE (mode) - 1;
1790 /* allowing PLUS yields mem:HI(plus:SI(mem:SI(plus:SI in m32c_split_move */
1791 if (GET_CODE (x) == PRE_DEC
1792 || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
1794 return (GET_CODE (XEXP (x, 0)) == REG
1795 && REGNO (XEXP (x, 0)) == SP_REGNO);
1799 /* This is the double indirection detection, but it currently
1800 doesn't work as cleanly as this code implies, so until we've had
1801 a chance to debug it, leave it disabled. */
1802 if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
1805 fprintf (stderr, "double indirect\n");
1814 /* Most indexable registers can be used without displacements,
1815 although some of them will be emitted with an explicit zero
1816 to please the assembler. */
1817 switch (REGNO (patternr[0]))
1827 if (IS_PSEUDO (patternr[0], strict))
1834 /* This is more interesting, because different base registers
1835 allow for different displacements - both range and signedness
1836 - and it differs from chip series to chip series too. */
1837 int rn = REGNO (patternr[1]);
1838 HOST_WIDE_INT offs = INTVAL (patternr[2]);
1844 /* The syntax only allows positive offsets, but when the
1845 offsets span the entire memory range, we can simulate
1846 negative offsets by wrapping. */
1848 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1850 return (offs >= 0 && offs <= 65535 - mode_adjust);
1852 return (offs >= -16777216 && offs <= 16777215);
1856 return (offs >= -128 && offs <= 127 - mode_adjust);
1857 return (offs >= -65536 && offs <= 65535 - mode_adjust);
1860 return (offs >= -128 && offs <= 127 - mode_adjust);
1863 if (IS_PSEUDO (patternr[1], strict))
1868 if (RTX_IS ("+rs") || RTX_IS ("+r+si"))
1870 rtx reg = patternr[1];
1872 /* We don't know where the symbol is, so only allow base
1873 registers which support displacements spanning the whole
1875 switch (REGNO (reg))
1879 /* $sb needs a secondary reload, but since it's involved in
1880 memory address reloads too, we don't deal with it very
1882 /* case SB_REGNO: */
1885 if (IS_PSEUDO (reg, strict))
1893 /* Implements REG_OK_FOR_BASE_P. */
1895 m32c_reg_ok_for_base_p (rtx x, int strict)
1897 if (GET_CODE (x) != REG)
1908 if (IS_PSEUDO (x, strict))
1914 /* We have three choices for choosing fb->aN offsets. If we choose -128,
1915 we need one MOVA -128[fb],aN opcode and 16-bit aN displacements,
1917 EB 4B FF mova -128[$fb],$a0
1918 D8 0C FF FF mov.w:Q #0,-1[$a0]
1920 Alternately, we subtract the frame size, and hopefully use 8-bit aN
1923 77 54 00 01 sub #256,$a0
1924 D8 08 01 mov.w:Q #0,1[$a0]
1926 If we don't offset (i.e. offset by zero), we end up with:
1928 D8 0C 00 FF mov.w:Q #0,-256[$a0]
1930 We have to subtract *something* so that we have a PLUS rtx to mark
1931 that we've done this reload. The -128 offset will never result in
1932 an 8-bit aN offset, and the payoff for the second case is five
1933 loads *if* those loads are within 256 bytes of the other end of the
1934 frame, so the third case seems best. Note that we subtract the
1935 zero, but detect that in the addhi3 pattern. */
1937 #define BIG_FB_ADJ 0
1939 /* Implements LEGITIMIZE_ADDRESS. The only address we really have to
1940 worry about is frame base offsets, as $fb has a limited
1941 displacement range. We deal with this by attempting to reload $fb
1942 itself into an address register; that seems to result in the best
1945 m32c_legitimize_address (rtx * x ATTRIBUTE_UNUSED,
1946 rtx oldx ATTRIBUTE_UNUSED,
1947 enum machine_mode mode ATTRIBUTE_UNUSED)
1950 fprintf (stderr, "m32c_legitimize_address for mode %s\n", mode_name[mode]);
1952 fprintf (stderr, "\n");
1955 if (GET_CODE (*x) == PLUS
1956 && GET_CODE (XEXP (*x, 0)) == REG
1957 && REGNO (XEXP (*x, 0)) == FB_REGNO
1958 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1959 && (INTVAL (XEXP (*x, 1)) < -128
1960 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
1962 /* reload FB to A_REGS */
1963 rtx temp = gen_reg_rtx (Pmode);
1965 emit_insn (gen_rtx_SET (VOIDmode, temp, XEXP (*x, 0)));
1966 XEXP (*x, 0) = temp;
1973 /* Implements LEGITIMIZE_RELOAD_ADDRESS. See comment above. */
1975 m32c_legitimize_reload_address (rtx * x,
1976 enum machine_mode mode,
1978 int type, int ind_levels ATTRIBUTE_UNUSED)
1981 fprintf (stderr, "\nm32c_legitimize_reload_address for mode %s\n",
1986 /* At one point, this function tried to get $fb copied to an address
1987 register, which in theory would maximize sharing, but gcc was
1988 *also* still trying to reload the whole address, and we'd run out
1989 of address registers. So we let gcc do the naive (but safe)
1990 reload instead, when the above function doesn't handle it for
1993 The code below is a second attempt at the above. */
1995 if (GET_CODE (*x) == PLUS
1996 && GET_CODE (XEXP (*x, 0)) == REG
1997 && REGNO (XEXP (*x, 0)) == FB_REGNO
1998 && GET_CODE (XEXP (*x, 1)) == CONST_INT
1999 && (INTVAL (XEXP (*x, 1)) < -128
2000 || INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
2003 int offset = INTVAL (XEXP (*x, 1));
2004 int adjustment = -BIG_FB_ADJ;
2006 sum = gen_rtx_PLUS (Pmode, XEXP (*x, 0),
2007 GEN_INT (adjustment));
2008 *x = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - adjustment));
2009 if (type == RELOAD_OTHER)
2010 type = RELOAD_FOR_OTHER_ADDRESS;
2011 push_reload (sum, NULL_RTX, &XEXP (*x, 0), NULL,
2012 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2017 if (GET_CODE (*x) == PLUS
2018 && GET_CODE (XEXP (*x, 0)) == PLUS
2019 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
2020 && REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
2021 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
2022 && GET_CODE (XEXP (*x, 1)) == CONST_INT
2025 if (type == RELOAD_OTHER)
2026 type = RELOAD_FOR_OTHER_ADDRESS;
2027 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
2028 A_REGS, Pmode, VOIDmode, 0, 0, opnum,
2036 /* Implements LEGITIMATE_CONSTANT_P. We split large constants anyway,
2037 so we can allow anything. */
2039 m32c_legitimate_constant_p (rtx x ATTRIBUTE_UNUSED)
2045 /* Condition Code Status */
2047 #undef TARGET_FIXED_CONDITION_CODE_REGS
2048 #define TARGET_FIXED_CONDITION_CODE_REGS m32c_fixed_condition_code_regs
2050 m32c_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
2053 *p2 = INVALID_REGNUM;
2057 /* Describing Relative Costs of Operations */
2059 /* Implements REGISTER_MOVE_COST. We make impossible moves
2060 prohibitively expensive, like trying to put QIs in r2/r3 (there are
2061 no opcodes to do that). We also discourage use of mem* registers
2062 since they're really memory. */
2064 m32c_register_move_cost (enum machine_mode mode, int from, int to)
2066 int cost = COSTS_N_INSNS (3);
2067 int cc = class_contents[from][0] | class_contents[to][0];
2068 /* FIXME: pick real values, but not 2 for now. */
2069 if (mode == QImode && (cc & class_contents[R23_REGS][0]))
2071 if (!(cc & ~class_contents[R23_REGS][0]))
2072 cost = COSTS_N_INSNS (1000);
2074 cost = COSTS_N_INSNS (80);
2077 if (!class_can_hold_mode (from, mode) || !class_can_hold_mode (to, mode))
2078 cost = COSTS_N_INSNS (1000);
2080 if (classes_intersect (from, CR_REGS))
2081 cost += COSTS_N_INSNS (5);
2083 if (classes_intersect (to, CR_REGS))
2084 cost += COSTS_N_INSNS (5);
2086 if (from == MEM_REGS || to == MEM_REGS)
2087 cost += COSTS_N_INSNS (50);
2088 else if (classes_intersect (from, MEM_REGS)
2089 || classes_intersect (to, MEM_REGS))
2090 cost += COSTS_N_INSNS (10);
2093 fprintf (stderr, "register_move_cost %s from %s to %s = %d\n",
2094 mode_name[mode], class_names[from], class_names[to], cost);
2099 /* Implements MEMORY_MOVE_COST. */
2101 m32c_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2102 int reg_class ATTRIBUTE_UNUSED,
2103 int in ATTRIBUTE_UNUSED)
2105 /* FIXME: pick real values. */
2106 return COSTS_N_INSNS (10);
2109 /* Here we try to describe when we use multiple opcodes for one RTX so
2110 that gcc knows when to use them. */
2111 #undef TARGET_RTX_COSTS
2112 #define TARGET_RTX_COSTS m32c_rtx_costs
2114 m32c_rtx_costs (rtx x, int code, int outer_code, int *total)
2119 if (REGNO (x) >= MEM0_REGNO && REGNO (x) <= MEM7_REGNO)
2120 *total += COSTS_N_INSNS (500);
2122 *total += COSTS_N_INSNS (1);
2128 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2130 /* mov.b r1l, r1h */
2131 *total += COSTS_N_INSNS (1);
2134 if (INTVAL (XEXP (x, 1)) > 8
2135 || INTVAL (XEXP (x, 1)) < -8)
2138 /* mov.b r1l, r1h */
2139 *total += COSTS_N_INSNS (2);
2154 if (outer_code == SET)
2156 *total += COSTS_N_INSNS (2);
2163 rtx dest = XEXP (x, 0);
2164 rtx addr = XEXP (dest, 0);
2165 switch (GET_CODE (addr))
2168 *total += COSTS_N_INSNS (1);
2171 *total += COSTS_N_INSNS (3);
2174 *total += COSTS_N_INSNS (2);
2182 /* Reasonable default. */
2183 if (TARGET_A16 && GET_MODE(x) == SImode)
2184 *total += COSTS_N_INSNS (2);
2190 #undef TARGET_ADDRESS_COST
2191 #define TARGET_ADDRESS_COST m32c_address_cost
2193 m32c_address_cost (rtx addr)
2195 /* fprintf(stderr, "\naddress_cost\n");
2197 switch (GET_CODE (addr))
2200 return COSTS_N_INSNS(1);
2202 return COSTS_N_INSNS(3);
2204 return COSTS_N_INSNS(2);
2210 /* Defining the Output Assembler Language */
2212 /* The Overall Framework of an Assembler File */
2214 #undef TARGET_HAVE_NAMED_SECTIONS
2215 #define TARGET_HAVE_NAMED_SECTIONS true
2217 /* Output of Data */
2219 /* We may have 24 bit sizes, which is the native address size.
2220 Currently unused, but provided for completeness. */
2221 #undef TARGET_ASM_INTEGER
2222 #define TARGET_ASM_INTEGER m32c_asm_integer
2224 m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
2229 fprintf (asm_out_file, "\t.3byte\t");
2230 output_addr_const (asm_out_file, x);
2231 fputc ('\n', asm_out_file);
2234 if (GET_CODE (x) == SYMBOL_REF)
2236 fprintf (asm_out_file, "\t.long\t");
2237 output_addr_const (asm_out_file, x);
2238 fputc ('\n', asm_out_file);
2243 return default_assemble_integer (x, size, aligned_p);
2246 /* Output of Assembler Instructions */
2248 /* We use a lookup table because the addressing modes are non-orthogonal. */
2253 char const *pattern;
2256 const conversions[] = {
2259 { 0, "mr", "z[1]" },
2260 { 0, "m+ri", "3[2]" },
2261 { 0, "m+rs", "3[2]" },
2262 { 0, "m+r+si", "4+5[2]" },
2265 { 0, "m+si", "2+3" },
2267 { 0, "mmr", "[z[2]]" },
2268 { 0, "mm+ri", "[4[3]]" },
2269 { 0, "mm+rs", "[4[3]]" },
2270 { 0, "mm+r+si", "[5+6[3]]" },
2271 { 0, "mms", "[[2]]" },
2272 { 0, "mmi", "[[2]]" },
2273 { 0, "mm+si", "[4[3]]" },
2277 { 0, "+si", "#1+2" },
2283 { 'd', "+si", "1+2" },
2286 { 'D', "+si", "1+2" },
2297 /* This is in order according to the bitfield that pushm/popm use. */
2298 static char const *pushm_regs[] = {
2299 "fb", "sb", "a1", "a0", "r3", "r2", "r1", "r0"
2302 /* Implements PRINT_OPERAND. */
2304 m32c_print_operand (FILE * file, rtx x, int code)
2309 int unsigned_const = 0;
2312 /* Multiplies; constants are converted to sign-extended format but
2313 we need unsigned, so 'u' and 'U' tell us what size unsigned we
2325 /* This one is only for debugging; you can put it in a pattern to
2326 force this error. */
2329 fprintf (stderr, "dj: unreviewed pattern:");
2330 if (current_output_insn)
2331 debug_rtx (current_output_insn);
2334 /* PSImode operations are either .w or .l depending on the target. */
2338 fprintf (file, "w");
2340 fprintf (file, "l");
2343 /* Inverted conditionals. */
2346 switch (GET_CODE (x))
2352 fputs ("gtu", file);
2358 fputs ("geu", file);
2364 fputs ("leu", file);
2370 fputs ("ltu", file);
2383 /* Regular conditionals. */
2386 switch (GET_CODE (x))
2392 fputs ("leu", file);
2398 fputs ("ltu", file);
2404 fputs ("gtu", file);
2410 fputs ("geu", file);
2423 /* Used in negsi2 to do HImode ops on the two parts of an SImode
2425 if (code == 'h' && GET_MODE (x) == SImode)
2427 x = m32c_subreg (HImode, x, SImode, 0);
2430 if (code == 'H' && GET_MODE (x) == SImode)
2432 x = m32c_subreg (HImode, x, SImode, 2);
2435 if (code == 'h' && GET_MODE (x) == HImode)
2437 x = m32c_subreg (QImode, x, HImode, 0);
2440 if (code == 'H' && GET_MODE (x) == HImode)
2442 /* We can't actually represent this as an rtx. Do it here. */
2443 if (GET_CODE (x) == REG)
2448 fputs ("r0h", file);
2451 fputs ("r1h", file);
2457 /* This should be a MEM. */
2458 x = m32c_subreg (QImode, x, HImode, 1);
2461 /* This is for BMcond, which always wants word register names. */
2462 if (code == 'h' && GET_MODE (x) == QImode)
2464 if (GET_CODE (x) == REG)
2465 x = gen_rtx_REG (HImode, REGNO (x));
2468 /* 'x' and 'X' need to be ignored for non-immediates. */
2469 if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
2474 for (i = 0; conversions[i].pattern; i++)
2475 if (conversions[i].code == code
2476 && streq (conversions[i].pattern, pattern))
2478 for (j = 0; conversions[i].format[j]; j++)
2479 /* backslash quotes the next character in the output pattern. */
2480 if (conversions[i].format[j] == '\\')
2482 fputc (conversions[i].format[j + 1], file);
2485 /* Digits in the output pattern indicate that the
2486 corresponding RTX is to be output at that point. */
2487 else if (ISDIGIT (conversions[i].format[j]))
2489 rtx r = patternr[conversions[i].format[j] - '0'];
2490 switch (GET_CODE (r))
2493 fprintf (file, "%s",
2494 reg_name_with_mode (REGNO (r), GET_MODE (r)));
2503 int i = (int) exact_log2 (v);
2505 i = (int) exact_log2 ((v ^ 0xffff) & 0xffff);
2507 i = (int) exact_log2 ((v ^ 0xff) & 0xff);
2509 fprintf (file, "%d", i);
2513 /* Unsigned byte. */
2514 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2518 /* Unsigned word. */
2519 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2520 INTVAL (r) & 0xffff);
2523 /* pushm and popm encode a register set into a single byte. */
2525 for (b = 7; b >= 0; b--)
2526 if (INTVAL (r) & (1 << b))
2528 fprintf (file, "%s%s", comma, pushm_regs[b]);
2533 /* "Minus". Output -X */
2534 ival = (-INTVAL (r) & 0xffff);
2536 ival = ival - 0x10000;
2537 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2541 if (conversions[i].format[j + 1] == '[' && ival < 0)
2543 /* We can simulate negative displacements by
2544 taking advantage of address space
2545 wrapping when the offset can span the
2546 entire address range. */
2548 patternr[conversions[i].format[j + 2] - '0'];
2549 if (GET_CODE (base) == REG)
2550 switch (REGNO (base))
2555 ival = 0x1000000 + ival;
2557 ival = 0x10000 + ival;
2561 ival = 0x10000 + ival;
2565 else if (code == 'd' && ival < 0 && j == 0)
2566 /* The "mova" opcode is used to do addition by
2567 computing displacements, but again, we need
2568 displacements to be unsigned *if* they're
2569 the only component of the displacement
2570 (i.e. no "symbol-4" type displacement). */
2571 ival = (TARGET_A24 ? 0x1000000 : 0x10000) + ival;
2573 if (conversions[i].format[j] == '0')
2575 /* More conversions to unsigned. */
2576 if (unsigned_const == 2)
2578 if (unsigned_const == 1)
2581 if (streq (conversions[i].pattern, "mi")
2582 || streq (conversions[i].pattern, "mmi"))
2584 /* Integers used as addresses are unsigned. */
2585 ival &= (TARGET_A24 ? 0xffffff : 0xffff);
2587 if (force_sign && ival >= 0)
2589 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
2594 /* We don't have const_double constants. If it
2595 happens, make it obvious. */
2596 fprintf (file, "[const_double 0x%lx]",
2597 (unsigned long) CONST_DOUBLE_HIGH (r));
2600 assemble_name (file, XSTR (r, 0));
2603 output_asm_label (r);
2606 fprintf (stderr, "don't know how to print this operand:");
2613 if (conversions[i].format[j] == 'z')
2615 /* Some addressing modes *must* have a displacement,
2616 so insert a zero here if needed. */
2618 for (k = j + 1; conversions[i].format[k]; k++)
2619 if (ISDIGIT (conversions[i].format[k]))
2621 rtx reg = patternr[conversions[i].format[k] - '0'];
2622 if (GET_CODE (reg) == REG
2623 && (REGNO (reg) == SB_REGNO
2624 || REGNO (reg) == FB_REGNO
2625 || REGNO (reg) == SP_REGNO))
2630 /* Signed displacements off symbols need to have signs
2632 if (conversions[i].format[j] == '+'
2633 && (!code || code == 'D' || code == 'd')
2634 && ISDIGIT (conversions[i].format[j + 1])
2635 && (GET_CODE (patternr[conversions[i].format[j + 1] - '0'])
2641 fputc (conversions[i].format[j], file);
2645 if (!conversions[i].pattern)
2647 fprintf (stderr, "unconvertible operand %c `%s'", code ? code : '-',
2650 fprintf (file, "[%c.%s]", code ? code : '-', pattern);
2656 /* Implements PRINT_OPERAND_PUNCT_VALID_P. See m32c_print_operand
2657 above for descriptions of what these do. */
2659 m32c_print_operand_punct_valid_p (int c)
2661 if (c == '&' || c == '!')
2666 /* Implements PRINT_OPERAND_ADDRESS. Nothing unusual here. */
2668 m32c_print_operand_address (FILE * stream, rtx address)
2670 gcc_assert (GET_CODE (address) == MEM);
2671 m32c_print_operand (stream, XEXP (address, 0), 0);
2674 /* Implements ASM_OUTPUT_REG_PUSH. Control registers are pushed
2675 differently than general registers. */
2677 m32c_output_reg_push (FILE * s, int regno)
2679 if (regno == FLG_REGNO)
2680 fprintf (s, "\tpushc\tflg\n");
2682 fprintf (s, "\tpush.%c\t%s\n",
2683 " bwll"[reg_push_size (regno)], reg_names[regno]);
2686 /* Likewise for ASM_OUTPUT_REG_POP. */
2688 m32c_output_reg_pop (FILE * s, int regno)
2690 if (regno == FLG_REGNO)
2691 fprintf (s, "\tpopc\tflg\n");
2693 fprintf (s, "\tpop.%c\t%s\n",
2694 " bwll"[reg_push_size (regno)], reg_names[regno]);
2697 /* Defining target-specific uses of `__attribute__' */
2699 /* Used to simplify the logic below. Find the attributes wherever
2701 #define M32C_ATTRIBUTES(decl) \
2702 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
2703 : DECL_ATTRIBUTES (decl) \
2704 ? (DECL_ATTRIBUTES (decl)) \
2705 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
2707 /* Returns TRUE if the given tree has the "interrupt" attribute. */
2709 interrupt_p (tree node ATTRIBUTE_UNUSED)
2711 tree list = M32C_ATTRIBUTES (node);
2714 if (is_attribute_p ("interrupt", TREE_PURPOSE (list)))
2716 list = TREE_CHAIN (list);
2722 interrupt_handler (tree * node ATTRIBUTE_UNUSED,
2723 tree name ATTRIBUTE_UNUSED,
2724 tree args ATTRIBUTE_UNUSED,
2725 int flags ATTRIBUTE_UNUSED,
2726 bool * no_add_attrs ATTRIBUTE_UNUSED)
2731 /* Returns TRUE if given tree has the "function_vector" attribute. */
2733 m32c_special_page_vector_p (tree func)
2735 if (TREE_CODE (func) != FUNCTION_DECL)
2738 tree list = M32C_ATTRIBUTES (func);
2741 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2743 list = TREE_CHAIN (list);
2749 function_vector_handler (tree * node ATTRIBUTE_UNUSED,
2750 tree name ATTRIBUTE_UNUSED,
2751 tree args ATTRIBUTE_UNUSED,
2752 int flags ATTRIBUTE_UNUSED,
2753 bool * no_add_attrs ATTRIBUTE_UNUSED)
2757 /* The attribute is not supported for R8C target. */
2758 warning (OPT_Wattributes,
2759 "`%s' attribute is not supported for R8C target",
2760 IDENTIFIER_POINTER (name));
2761 *no_add_attrs = true;
2763 else if (TREE_CODE (*node) != FUNCTION_DECL)
2765 /* The attribute must be applied to functions only. */
2766 warning (OPT_Wattributes,
2767 "`%s' attribute applies only to functions",
2768 IDENTIFIER_POINTER (name));
2769 *no_add_attrs = true;
2771 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
2773 /* The argument must be a constant integer. */
2774 warning (OPT_Wattributes,
2775 "`%s' attribute argument not an integer constant",
2776 IDENTIFIER_POINTER (name));
2777 *no_add_attrs = true;
2779 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) < 18
2780 || TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
2782 /* The argument value must be between 18 to 255. */
2783 warning (OPT_Wattributes,
2784 "`%s' attribute argument should be between 18 to 255",
2785 IDENTIFIER_POINTER (name));
2786 *no_add_attrs = true;
2791 /* If the function is assigned the attribute 'function_vector', it
2792 returns the function vector number, otherwise returns zero. */
2794 current_function_special_page_vector (rtx x)
2798 if ((GET_CODE(x) == SYMBOL_REF)
2799 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
2801 tree t = SYMBOL_REF_DECL (x);
2803 if (TREE_CODE (t) != FUNCTION_DECL)
2806 tree list = M32C_ATTRIBUTES (t);
2809 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
2811 num = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
2815 list = TREE_CHAIN (list);
2824 #undef TARGET_ATTRIBUTE_TABLE
2825 #define TARGET_ATTRIBUTE_TABLE m32c_attribute_table
2826 static const struct attribute_spec m32c_attribute_table[] = {
2827 {"interrupt", 0, 0, false, false, false, interrupt_handler},
2828 {"function_vector", 1, 1, true, false, false, function_vector_handler},
2829 {0, 0, 0, 0, 0, 0, 0}
2832 #undef TARGET_COMP_TYPE_ATTRIBUTES
2833 #define TARGET_COMP_TYPE_ATTRIBUTES m32c_comp_type_attributes
2835 m32c_comp_type_attributes (const_tree type1 ATTRIBUTE_UNUSED,
2836 const_tree type2 ATTRIBUTE_UNUSED)
2838 /* 0=incompatible 1=compatible 2=warning */
2842 #undef TARGET_INSERT_ATTRIBUTES
2843 #define TARGET_INSERT_ATTRIBUTES m32c_insert_attributes
2845 m32c_insert_attributes (tree node ATTRIBUTE_UNUSED,
2846 tree * attr_ptr ATTRIBUTE_UNUSED)
2848 /* Nothing to do here. */
2853 /* This is a list of legal subregs of hard regs. */
2854 static const struct {
2855 unsigned char outer_mode_size;
2856 unsigned char inner_mode_size;
2857 unsigned char byte_mask;
2858 unsigned char legal_when;
2860 } legal_subregs[] = {
2861 {1, 2, 0x03, 1, R0_REGNO}, /* r0h r0l */
2862 {1, 2, 0x03, 1, R1_REGNO}, /* r1h r1l */
2863 {1, 2, 0x01, 1, A0_REGNO},
2864 {1, 2, 0x01, 1, A1_REGNO},
2866 {1, 4, 0x01, 1, A0_REGNO},
2867 {1, 4, 0x01, 1, A1_REGNO},
2869 {2, 4, 0x05, 1, R0_REGNO}, /* r2 r0 */
2870 {2, 4, 0x05, 1, R1_REGNO}, /* r3 r1 */
2871 {2, 4, 0x05, 16, A0_REGNO}, /* a1 a0 */
2872 {2, 4, 0x01, 24, A0_REGNO}, /* a1 a0 */
2873 {2, 4, 0x01, 24, A1_REGNO}, /* a1 a0 */
2875 {4, 8, 0x55, 1, R0_REGNO}, /* r3 r1 r2 r0 */
2878 /* Returns TRUE if OP is a subreg of a hard reg which we don't
2881 m32c_illegal_subreg_p (rtx op)
2885 int src_mode, dest_mode;
2887 if (GET_CODE (op) != SUBREG)
2890 dest_mode = GET_MODE (op);
2891 offset = SUBREG_BYTE (op);
2892 op = SUBREG_REG (op);
2893 src_mode = GET_MODE (op);
2895 if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
2897 if (GET_CODE (op) != REG)
2899 if (REGNO (op) >= MEM0_REGNO)
2902 offset = (1 << offset);
2904 for (i = 0; i < ARRAY_SIZE (legal_subregs); i ++)
2905 if (legal_subregs[i].outer_mode_size == GET_MODE_SIZE (dest_mode)
2906 && legal_subregs[i].regno == REGNO (op)
2907 && legal_subregs[i].inner_mode_size == GET_MODE_SIZE (src_mode)
2908 && legal_subregs[i].byte_mask & offset)
2910 switch (legal_subregs[i].legal_when)
2927 /* Returns TRUE if we support a move between the first two operands.
2928 At the moment, we just want to discourage mem to mem moves until
2929 after reload, because reload has a hard time with our limited
2930 number of address registers, and we can get into a situation where
2931 we need three of them when we only have two. */
2933 m32c_mov_ok (rtx * operands, enum machine_mode mode ATTRIBUTE_UNUSED)
2935 rtx op0 = operands[0];
2936 rtx op1 = operands[1];
2941 #define DEBUG_MOV_OK 0
2943 fprintf (stderr, "m32c_mov_ok %s\n", mode_name[mode]);
2948 if (GET_CODE (op0) == SUBREG)
2949 op0 = XEXP (op0, 0);
2950 if (GET_CODE (op1) == SUBREG)
2951 op1 = XEXP (op1, 0);
2953 if (GET_CODE (op0) == MEM
2954 && GET_CODE (op1) == MEM
2955 && ! reload_completed)
2958 fprintf (stderr, " - no, mem to mem\n");
2964 fprintf (stderr, " - ok\n");
2969 /* Returns TRUE if two consecutive HImode mov instructions, generated
2970 for moving an immediate double data to a double data type variable
2971 location, can be combined into single SImode mov instruction. */
2973 m32c_immd_dbl_mov (rtx * operands,
2974 enum machine_mode mode ATTRIBUTE_UNUSED)
2976 int flag = 0, okflag = 0, offset1 = 0, offset2 = 0, offsetsign = 0;
2980 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
2981 && MEM_SCALAR_P (operands[0])
2982 && !MEM_IN_STRUCT_P (operands[0])
2983 && GET_CODE (XEXP (operands[2], 0)) == CONST
2984 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
2985 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
2986 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 1)) == CONST_INT
2987 && MEM_SCALAR_P (operands[2])
2988 && !MEM_IN_STRUCT_P (operands[2]))
2991 else if (GET_CODE (XEXP (operands[0], 0)) == CONST
2992 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == PLUS
2993 && GET_CODE (XEXP (XEXP (XEXP (operands[0], 0), 0), 0)) == SYMBOL_REF
2994 && MEM_SCALAR_P (operands[0])
2995 && !MEM_IN_STRUCT_P (operands[0])
2996 && !(XINT (XEXP (XEXP (XEXP (operands[0], 0), 0), 1), 0) %4)
2997 && GET_CODE (XEXP (operands[2], 0)) == CONST
2998 && GET_CODE (XEXP (XEXP (operands[2], 0), 0)) == PLUS
2999 && GET_CODE (XEXP (XEXP (XEXP (operands[2], 0), 0), 0)) == SYMBOL_REF
3000 && MEM_SCALAR_P (operands[2])
3001 && !MEM_IN_STRUCT_P (operands[2]))
3004 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
3005 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
3006 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == FB_REGNO
3007 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT
3008 && MEM_SCALAR_P (operands[0])
3009 && !MEM_IN_STRUCT_P (operands[0])
3010 && !(XINT (XEXP (XEXP (operands[0], 0), 1), 0) %4)
3011 && REGNO (XEXP (XEXP (operands[2], 0), 0)) == FB_REGNO
3012 && GET_CODE (XEXP (XEXP (operands[2], 0), 1)) == CONST_INT
3013 && MEM_SCALAR_P (operands[2])
3014 && !MEM_IN_STRUCT_P (operands[2]))
3023 str1 = XSTR (XEXP (operands[0], 0), 0);
3024 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3025 if (strcmp (str1, str2) == 0)
3031 str1 = XSTR (XEXP (XEXP (XEXP (operands[0], 0), 0), 0), 0);
3032 str2 = XSTR (XEXP (XEXP (XEXP (operands[2], 0), 0), 0), 0);
3033 if (strcmp(str1,str2) == 0)
3039 offset1 = XINT (XEXP (XEXP (operands[0], 0), 1), 0);
3040 offset2 = XINT (XEXP (XEXP (operands[2], 0), 1), 0);
3041 offsetsign = offset1 >> ((sizeof (offset1) * 8) -1);
3042 if (((offset2-offset1) == 2) && offsetsign != 0)
3054 operands[4] = gen_rtx_MEM (SImode, XEXP (operands[0], 0));
3056 val = (XINT (operands[3], 0) << 16) + (XINT (operands[1], 0) & 0xFFFF);
3057 operands[5] = gen_rtx_CONST_INT (VOIDmode, val);
3067 /* Subregs are non-orthogonal for us, because our registers are all
3070 m32c_subreg (enum machine_mode outer,
3071 rtx x, enum machine_mode inner, int byte)
3075 /* Converting MEMs to different types that are the same size, we
3076 just rewrite them. */
3077 if (GET_CODE (x) == SUBREG
3078 && SUBREG_BYTE (x) == 0
3079 && GET_CODE (SUBREG_REG (x)) == MEM
3080 && (GET_MODE_SIZE (GET_MODE (x))
3081 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3084 x = gen_rtx_MEM (GET_MODE (x), XEXP (SUBREG_REG (x), 0));
3085 MEM_COPY_ATTRIBUTES (x, SUBREG_REG (oldx));
3088 /* Push/pop get done as smaller push/pops. */
3089 if (GET_CODE (x) == MEM
3090 && (GET_CODE (XEXP (x, 0)) == PRE_DEC
3091 || GET_CODE (XEXP (x, 0)) == POST_INC))
3092 return gen_rtx_MEM (outer, XEXP (x, 0));
3093 if (GET_CODE (x) == SUBREG
3094 && GET_CODE (XEXP (x, 0)) == MEM
3095 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
3096 || GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
3097 return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
3099 if (GET_CODE (x) != REG)
3100 return simplify_gen_subreg (outer, x, inner, byte);
3103 if (r >= FIRST_PSEUDO_REGISTER || r == AP_REGNO)
3104 return simplify_gen_subreg (outer, x, inner, byte);
3106 if (IS_MEM_REGNO (r))
3107 return simplify_gen_subreg (outer, x, inner, byte);
3109 /* This is where the complexities of our register layout are
3113 else if (outer == HImode)
3115 if (r == R0_REGNO && byte == 2)
3117 else if (r == R0_REGNO && byte == 4)
3119 else if (r == R0_REGNO && byte == 6)
3121 else if (r == R1_REGNO && byte == 2)
3123 else if (r == A0_REGNO && byte == 2)
3126 else if (outer == SImode)
3128 if (r == R0_REGNO && byte == 0)
3130 else if (r == R0_REGNO && byte == 4)
3135 fprintf (stderr, "m32c_subreg %s %s %d\n",
3136 mode_name[outer], mode_name[inner], byte);
3140 return gen_rtx_REG (outer, nr);
3143 /* Used to emit move instructions. We split some moves,
3144 and avoid mem-mem moves. */
3146 m32c_prepare_move (rtx * operands, enum machine_mode mode)
3148 if (TARGET_A16 && mode == PSImode)
3149 return m32c_split_move (operands, mode, 1);
3150 if ((GET_CODE (operands[0]) == MEM)
3151 && (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
3153 rtx pmv = XEXP (operands[0], 0);
3154 rtx dest_reg = XEXP (pmv, 0);
3155 rtx dest_mod = XEXP (pmv, 1);
3157 emit_insn (gen_rtx_SET (Pmode, dest_reg, dest_mod));
3158 operands[0] = gen_rtx_MEM (mode, dest_reg);
3160 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3161 operands[1] = copy_to_mode_reg (mode, operands[1]);
3165 #define DEBUG_SPLIT 0
3167 /* Returns TRUE if the given PSImode move should be split. We split
3168 for all r8c/m16c moves, since it doesn't support them, and for
3169 POP.L as we can only *push* SImode. */
3171 m32c_split_psi_p (rtx * operands)
3174 fprintf (stderr, "\nm32c_split_psi_p\n");
3175 debug_rtx (operands[0]);
3176 debug_rtx (operands[1]);
3181 fprintf (stderr, "yes, A16\n");
3185 if (GET_CODE (operands[1]) == MEM
3186 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3189 fprintf (stderr, "yes, pop.l\n");
3194 fprintf (stderr, "no, default\n");
3199 /* Split the given move. SPLIT_ALL is 0 if splitting is optional
3200 (define_expand), 1 if it is not optional (define_insn_and_split),
3201 and 3 for define_split (alternate api). */
3203 m32c_split_move (rtx * operands, enum machine_mode mode, int split_all)
3206 int parts, si, di, rev = 0;
3207 int rv = 0, opi = 2;
3208 enum machine_mode submode = HImode;
3209 rtx *ops, local_ops[10];
3211 /* define_split modifies the existing operands, but the other two
3212 emit new insns. OPS is where we store the operand pairs, which
3223 /* Before splitting mem-mem moves, force one operand into a
3225 if (can_create_pseudo_p () && MEM_P (operands[0]) && MEM_P (operands[1]))
3228 fprintf (stderr, "force_reg...\n");
3229 debug_rtx (operands[1]);
3231 operands[1] = force_reg (mode, operands[1]);
3233 debug_rtx (operands[1]);
3240 fprintf (stderr, "\nsplit_move %d all=%d\n", !can_create_pseudo_p (),
3242 debug_rtx (operands[0]);
3243 debug_rtx (operands[1]);
3246 /* Note that split_all is not used to select the api after this
3247 point, so it's safe to set it to 3 even with define_insn. */
3248 /* None of the chips can move SI operands to sp-relative addresses,
3249 so we always split those. */
3250 if (m32c_extra_constraint_p (operands[0], 'S', "Ss"))
3253 /* We don't need to split these. */
3256 && (mode == SImode || mode == PSImode)
3257 && !(GET_CODE (operands[1]) == MEM
3258 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
3261 /* First, enumerate the subregs we'll be dealing with. */
3262 for (si = 0; si < parts; si++)
3265 m32c_subreg (submode, operands[0], mode,
3266 si * GET_MODE_SIZE (submode));
3268 m32c_subreg (submode, operands[1], mode,
3269 si * GET_MODE_SIZE (submode));
3272 /* Split pushes by emitting a sequence of smaller pushes. */
3273 if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
3275 for (si = parts - 1; si >= 0; si--)
3277 ops[opi++] = gen_rtx_MEM (submode,
3278 gen_rtx_PRE_DEC (Pmode,
3286 /* Likewise for pops. */
3287 else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
3289 for (di = 0; di < parts; di++)
3292 ops[opi++] = gen_rtx_MEM (submode,
3293 gen_rtx_POST_INC (Pmode,
3301 /* if d[di] == s[si] for any di < si, we'll early clobber. */
3302 for (di = 0; di < parts - 1; di++)
3303 for (si = di + 1; si < parts; si++)
3304 if (reg_mentioned_p (d[di], s[si]))
3308 for (si = 0; si < parts; si++)
3314 for (si = parts - 1; si >= 0; si--)
3321 /* Now emit any moves we may have accumulated. */
3322 if (rv && split_all != 3)
3325 for (i = 2; i < opi; i += 2)
3326 emit_move_insn (ops[i], ops[i + 1]);
3331 /* The m32c has a number of opcodes that act like memcpy, strcmp, and
3332 the like. For the R8C they expect one of the addresses to be in
3333 R1L:An so we need to arrange for that. Otherwise, it's just a
3334 matter of picking out the operands we want and emitting the right
3335 pattern for them. All these expanders, which correspond to
3336 patterns in blkmov.md, must return nonzero if they expand the insn,
3337 or zero if they should FAIL. */
3339 /* This is a memset() opcode. All operands are implied, so we need to
3340 arrange for them to be in the right registers. The opcode wants
3341 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3342 the count (HI), and $2 the value (QI). */
3344 m32c_expand_setmemhi(rtx *operands)
3346 rtx desta, count, val;
3349 desta = XEXP (operands[0], 0);
3350 count = operands[1];
3353 desto = gen_reg_rtx (Pmode);
3354 counto = gen_reg_rtx (HImode);
3356 if (GET_CODE (desta) != REG
3357 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3358 desta = copy_to_mode_reg (Pmode, desta);
3360 /* This looks like an arbitrary restriction, but this is by far the
3361 most common case. For counts 8..14 this actually results in
3362 smaller code with no speed penalty because the half-sized
3363 constant can be loaded with a shorter opcode. */
3364 if (GET_CODE (count) == CONST_INT
3365 && GET_CODE (val) == CONST_INT
3366 && ! (INTVAL (count) & 1)
3367 && (INTVAL (count) > 1)
3368 && (INTVAL (val) <= 7 && INTVAL (val) >= -8))
3370 unsigned v = INTVAL (val) & 0xff;
3372 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3373 val = copy_to_mode_reg (HImode, GEN_INT (v));
3375 emit_insn (gen_setmemhi_whi_op (desto, counto, val, desta, count));
3377 emit_insn (gen_setmemhi_wpsi_op (desto, counto, val, desta, count));
3381 /* This is the generalized memset() case. */
3382 if (GET_CODE (val) != REG
3383 || REGNO (val) < FIRST_PSEUDO_REGISTER)
3384 val = copy_to_mode_reg (QImode, val);
3386 if (GET_CODE (count) != REG
3387 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3388 count = copy_to_mode_reg (HImode, count);
3391 emit_insn (gen_setmemhi_bhi_op (desto, counto, val, desta, count));
3393 emit_insn (gen_setmemhi_bpsi_op (desto, counto, val, desta, count));
3398 /* This is a memcpy() opcode. All operands are implied, so we need to
3399 arrange for them to be in the right registers. The opcode wants
3400 addresses, not [mem] syntax. $0 is the destination (MEM:BLK), $1
3401 is the source (MEM:BLK), and $2 the count (HI). */
3403 m32c_expand_movmemhi(rtx *operands)
3405 rtx desta, srca, count;
3406 rtx desto, srco, counto;
3408 desta = XEXP (operands[0], 0);
3409 srca = XEXP (operands[1], 0);
3410 count = operands[2];
3412 desto = gen_reg_rtx (Pmode);
3413 srco = gen_reg_rtx (Pmode);
3414 counto = gen_reg_rtx (HImode);
3416 if (GET_CODE (desta) != REG
3417 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3418 desta = copy_to_mode_reg (Pmode, desta);
3420 if (GET_CODE (srca) != REG
3421 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3422 srca = copy_to_mode_reg (Pmode, srca);
3424 /* Similar to setmem, but we don't need to check the value. */
3425 if (GET_CODE (count) == CONST_INT
3426 && ! (INTVAL (count) & 1)
3427 && (INTVAL (count) > 1))
3429 count = copy_to_mode_reg (HImode, GEN_INT (INTVAL (count) / 2));
3431 emit_insn (gen_movmemhi_whi_op (desto, srco, counto, desta, srca, count));
3433 emit_insn (gen_movmemhi_wpsi_op (desto, srco, counto, desta, srca, count));
3437 /* This is the generalized memset() case. */
3438 if (GET_CODE (count) != REG
3439 || REGNO (count) < FIRST_PSEUDO_REGISTER)
3440 count = copy_to_mode_reg (HImode, count);
3443 emit_insn (gen_movmemhi_bhi_op (desto, srco, counto, desta, srca, count));
3445 emit_insn (gen_movmemhi_bpsi_op (desto, srco, counto, desta, srca, count));
3450 /* This is a stpcpy() opcode. $0 is the destination (MEM:BLK) after
3451 the copy, which should point to the NUL at the end of the string,
3452 $1 is the destination (MEM:BLK), and $2 is the source (MEM:BLK).
3453 Since our opcode leaves the destination pointing *after* the NUL,
3454 we must emit an adjustment. */
3456 m32c_expand_movstr(rtx *operands)
3461 desta = XEXP (operands[1], 0);
3462 srca = XEXP (operands[2], 0);
3464 desto = gen_reg_rtx (Pmode);
3465 srco = gen_reg_rtx (Pmode);
3467 if (GET_CODE (desta) != REG
3468 || REGNO (desta) < FIRST_PSEUDO_REGISTER)
3469 desta = copy_to_mode_reg (Pmode, desta);
3471 if (GET_CODE (srca) != REG
3472 || REGNO (srca) < FIRST_PSEUDO_REGISTER)
3473 srca = copy_to_mode_reg (Pmode, srca);
3475 emit_insn (gen_movstr_op (desto, srco, desta, srca));
3476 /* desto ends up being a1, which allows this type of add through MOVA. */
3477 emit_insn (gen_addpsi3 (operands[0], desto, GEN_INT (-1)));
3482 /* This is a strcmp() opcode. $0 is the destination (HI) which holds
3483 <=>0 depending on the comparison, $1 is one string (MEM:BLK), and
3484 $2 is the other (MEM:BLK). We must do the comparison, and then
3485 convert the flags to a signed integer result. */
3487 m32c_expand_cmpstr(rtx *operands)
3491 src1a = XEXP (operands[1], 0);
3492 src2a = XEXP (operands[2], 0);
3494 if (GET_CODE (src1a) != REG
3495 || REGNO (src1a) < FIRST_PSEUDO_REGISTER)
3496 src1a = copy_to_mode_reg (Pmode, src1a);
3498 if (GET_CODE (src2a) != REG
3499 || REGNO (src2a) < FIRST_PSEUDO_REGISTER)
3500 src2a = copy_to_mode_reg (Pmode, src2a);
3502 emit_insn (gen_cmpstrhi_op (src1a, src2a, src1a, src2a));
3503 emit_insn (gen_cond_to_int (operands[0]));
3509 typedef rtx (*shift_gen_func)(rtx, rtx, rtx);
3511 static shift_gen_func
3512 shift_gen_func_for (int mode, int code)
3514 #define GFF(m,c,f) if (mode == m && code == c) return f
3515 GFF(QImode, ASHIFT, gen_ashlqi3_i);
3516 GFF(QImode, ASHIFTRT, gen_ashrqi3_i);
3517 GFF(QImode, LSHIFTRT, gen_lshrqi3_i);
3518 GFF(HImode, ASHIFT, gen_ashlhi3_i);
3519 GFF(HImode, ASHIFTRT, gen_ashrhi3_i);
3520 GFF(HImode, LSHIFTRT, gen_lshrhi3_i);
3521 GFF(PSImode, ASHIFT, gen_ashlpsi3_i);
3522 GFF(PSImode, ASHIFTRT, gen_ashrpsi3_i);
3523 GFF(PSImode, LSHIFTRT, gen_lshrpsi3_i);
3524 GFF(SImode, ASHIFT, TARGET_A16 ? gen_ashlsi3_16 : gen_ashlsi3_24);
3525 GFF(SImode, ASHIFTRT, TARGET_A16 ? gen_ashrsi3_16 : gen_ashrsi3_24);
3526 GFF(SImode, LSHIFTRT, TARGET_A16 ? gen_lshrsi3_16 : gen_lshrsi3_24);
3531 /* The m32c only has one shift, but it takes a signed count. GCC
3532 doesn't want this, so we fake it by negating any shift count when
3533 we're pretending to shift the other way. Also, the shift count is
3534 limited to -8..8. It's slightly better to use two shifts for 9..15
3535 than to load the count into r1h, so we do that too. */
3537 m32c_prepare_shift (rtx * operands, int scale, int shift_code)
3539 enum machine_mode mode = GET_MODE (operands[0]);
3540 shift_gen_func func = shift_gen_func_for (mode, shift_code);
3543 if (GET_CODE (operands[2]) == CONST_INT)
3545 int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
3546 int count = INTVAL (operands[2]) * scale;
3548 while (count > maxc)
3550 temp = gen_reg_rtx (mode);
3551 emit_insn (func (temp, operands[1], GEN_INT (maxc)));
3555 while (count < -maxc)
3557 temp = gen_reg_rtx (mode);
3558 emit_insn (func (temp, operands[1], GEN_INT (-maxc)));
3562 emit_insn (func (operands[0], operands[1], GEN_INT (count)));
3566 temp = gen_reg_rtx (QImode);
3568 /* The pattern has a NEG that corresponds to this. */
3569 emit_move_insn (temp, gen_rtx_NEG (QImode, operands[2]));
3570 else if (TARGET_A16 && mode == SImode)
3571 /* We do this because the code below may modify this, we don't
3572 want to modify the origin of this value. */
3573 emit_move_insn (temp, operands[2]);
3575 /* We'll only use it for the shift, no point emitting a move. */
3578 if (TARGET_A16 && GET_MODE_SIZE (mode) == 4)
3580 /* The m16c has a limit of -16..16 for SI shifts, even when the
3581 shift count is in a register. Since there are so many targets
3582 of these shifts, it's better to expand the RTL here than to
3583 call a helper function.
3585 The resulting code looks something like this:
3597 We take advantage of the fact that "negative" shifts are
3598 undefined to skip one of the comparisons. */
3601 rtx label, lref, insn, tempvar;
3603 emit_move_insn (operands[0], operands[1]);
3606 label = gen_label_rtx ();
3607 lref = gen_rtx_LABEL_REF (VOIDmode, label);
3608 LABEL_NUSES (label) ++;
3610 tempvar = gen_reg_rtx (mode);
3612 if (shift_code == ASHIFT)
3614 /* This is a left shift. We only need check positive counts. */
3615 emit_jump_insn (gen_cbranchqi4 (gen_rtx_LE (VOIDmode, 0, 0),
3616 count, GEN_INT (16), label));
3617 emit_insn (func (tempvar, operands[0], GEN_INT (8)));
3618 emit_insn (func (operands[0], tempvar, GEN_INT (8)));
3619 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (-16)));
3620 emit_label_after (label, insn);
3624 /* This is a right shift. We only need check negative counts. */
3625 emit_jump_insn (gen_cbranchqi4 (gen_rtx_GE (VOIDmode, 0, 0),
3626 count, GEN_INT (-16), label));
3627 emit_insn (func (tempvar, operands[0], GEN_INT (-8)));
3628 emit_insn (func (operands[0], tempvar, GEN_INT (-8)));
3629 insn = emit_insn (gen_addqi3 (count, count, GEN_INT (16)));
3630 emit_label_after (label, insn);
3632 operands[1] = operands[0];
3633 emit_insn (func (operands[0], operands[0], count));
3641 /* The m32c has a limited range of operations that work on PSImode
3642 values; we have to expand to SI, do the math, and truncate back to
3643 PSI. Yes, this is expensive, but hopefully gcc will learn to avoid
3646 m32c_expand_neg_mulpsi3 (rtx * operands)
3648 /* operands: a = b * i */
3649 rtx temp1; /* b as SI */
3650 rtx scale /* i as SI */;
3651 rtx temp2; /* a*b as SI */
3653 temp1 = gen_reg_rtx (SImode);
3654 temp2 = gen_reg_rtx (SImode);
3655 if (GET_CODE (operands[2]) != CONST_INT)
3657 scale = gen_reg_rtx (SImode);
3658 emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
3661 scale = copy_to_mode_reg (SImode, operands[2]);
3663 emit_insn (gen_zero_extendpsisi2 (temp1, operands[1]));
3664 temp2 = expand_simple_binop (SImode, MULT, temp1, scale, temp2, 1, OPTAB_LIB);
3665 emit_insn (gen_truncsipsi2 (operands[0], temp2));
3668 static rtx compare_op0, compare_op1;
3671 m32c_pend_compare (rtx *operands)
3673 compare_op0 = operands[0];
3674 compare_op1 = operands[1];
3678 m32c_unpend_compare (void)
3680 switch (GET_MODE (compare_op0))
3683 emit_insn (gen_cmpqi_op (compare_op0, compare_op1));
3685 emit_insn (gen_cmphi_op (compare_op0, compare_op1));
3687 emit_insn (gen_cmppsi_op (compare_op0, compare_op1));
3689 /* Just to silence the "missing case" warnings. */ ;
3694 m32c_expand_scc (int code, rtx *operands)
3696 enum machine_mode mode = TARGET_A16 ? QImode : HImode;
3698 emit_insn (gen_rtx_SET (mode,
3700 gen_rtx_fmt_ee (code,
3706 /* Pattern Output Functions */
3708 /* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
3709 match_operand rtx's OP. */
3711 m32c_cmp_flg_0 (rtx cmp)
3713 return gen_rtx_fmt_ee (GET_CODE (cmp),
3715 gen_rtx_REG (CCmode, FLG_REGNO),
3720 m32c_expand_movcc (rtx *operands)
3722 rtx rel = operands[1];
3725 if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
3727 if (GET_CODE (operands[2]) != CONST_INT
3728 || GET_CODE (operands[3]) != CONST_INT)
3730 emit_insn (gen_cmpqi(XEXP (rel, 0), XEXP (rel, 1)));
3731 if (GET_CODE (rel) == NE)
3733 rtx tmp = operands[2];
3734 operands[2] = operands[3];
3738 cmp = gen_rtx_fmt_ee (GET_CODE (rel),
3743 emit_move_insn (operands[0],
3744 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3751 /* Used for the "insv" pattern. Return nonzero to fail, else done. */
3753 m32c_expand_insv (rtx *operands)
3758 if (INTVAL (operands[1]) != 1)
3761 /* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
3762 if (GET_CODE (operands[3]) != CONST_INT)
3764 if (INTVAL (operands[3]) != 0
3765 && INTVAL (operands[3]) != 1
3766 && INTVAL (operands[3]) != -1)
3769 mask = 1 << INTVAL (operands[2]);
3772 if (GET_CODE (op0) == SUBREG
3773 && SUBREG_BYTE (op0) == 0)
3775 rtx sub = SUBREG_REG (op0);
3776 if (GET_MODE (sub) == HImode || GET_MODE (sub) == QImode)
3780 if (!can_create_pseudo_p ()
3781 || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
3785 src0 = gen_reg_rtx (GET_MODE (op0));
3786 emit_move_insn (src0, op0);
3789 if (GET_MODE (op0) == HImode
3790 && INTVAL (operands[2]) >= 8
3791 && GET_MODE (op0) == MEM)
3793 /* We are little endian. */
3794 rtx new_mem = gen_rtx_MEM (QImode, plus_constant (XEXP (op0, 0), 1));
3795 MEM_COPY_ATTRIBUTES (new_mem, op0);
3799 /* First, we generate a mask with the correct polarity. If we are
3800 storing a zero, we want an AND mask, so invert it. */
3801 if (INTVAL (operands[3]) == 0)
3803 /* Storing a zero, use an AND mask */
3804 if (GET_MODE (op0) == HImode)
3809 /* Now we need to properly sign-extend the mask in case we need to
3810 fall back to an AND or OR opcode. */
3811 if (GET_MODE (op0) == HImode)
3822 switch ( (INTVAL (operands[3]) ? 4 : 0)
3823 + ((GET_MODE (op0) == HImode) ? 2 : 0)
3824 + (TARGET_A24 ? 1 : 0))
3826 case 0: p = gen_andqi3_16 (op0, src0, GEN_INT (mask)); break;
3827 case 1: p = gen_andqi3_24 (op0, src0, GEN_INT (mask)); break;
3828 case 2: p = gen_andhi3_16 (op0, src0, GEN_INT (mask)); break;
3829 case 3: p = gen_andhi3_24 (op0, src0, GEN_INT (mask)); break;
3830 case 4: p = gen_iorqi3_16 (op0, src0, GEN_INT (mask)); break;
3831 case 5: p = gen_iorqi3_24 (op0, src0, GEN_INT (mask)); break;
3832 case 6: p = gen_iorhi3_16 (op0, src0, GEN_INT (mask)); break;
3833 case 7: p = gen_iorhi3_24 (op0, src0, GEN_INT (mask)); break;
3841 m32c_scc_pattern(rtx *operands, RTX_CODE code)
3843 static char buf[30];
3844 if (GET_CODE (operands[0]) == REG
3845 && REGNO (operands[0]) == R0_REGNO)
3848 return "stzx\t#1,#0,r0l";
3850 return "stzx\t#0,#1,r0l";
3852 sprintf(buf, "bm%s\t0,%%h0\n\tand.b\t#1,%%0", GET_RTX_NAME (code));
3856 /* Encode symbol attributes of a SYMBOL_REF into its
3857 SYMBOL_REF_FLAGS. */
3859 m32c_encode_section_info (tree decl, rtx rtl, int first)
3861 int extra_flags = 0;
3863 default_encode_section_info (decl, rtl, first);
3864 if (TREE_CODE (decl) == FUNCTION_DECL
3865 && m32c_special_page_vector_p (decl))
3867 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION;
3870 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
3873 /* Returns TRUE if the current function is a leaf, and thus we can
3874 determine which registers an interrupt function really needs to
3875 save. The logic below is mostly about finding the insn sequence
3876 that's the function, versus any sequence that might be open for the
3879 m32c_leaf_function_p (void)
3881 rtx saved_first, saved_last;
3882 struct sequence_stack *seq;
3885 saved_first = cfun->emit->x_first_insn;
3886 saved_last = cfun->emit->x_last_insn;
3887 for (seq = cfun->emit->sequence_stack; seq && seq->next; seq = seq->next)
3891 cfun->emit->x_first_insn = seq->first;
3892 cfun->emit->x_last_insn = seq->last;
3895 rv = leaf_function_p ();
3897 cfun->emit->x_first_insn = saved_first;
3898 cfun->emit->x_last_insn = saved_last;
3902 /* Returns TRUE if the current function needs to use the ENTER/EXIT
3903 opcodes. If the function doesn't need the frame base or stack
3904 pointer, it can use the simpler RTS opcode. */
3906 m32c_function_needs_enter (void)
3909 struct sequence_stack *seq;
3910 rtx sp = gen_rtx_REG (Pmode, SP_REGNO);
3911 rtx fb = gen_rtx_REG (Pmode, FB_REGNO);
3913 insn = get_insns ();
3914 for (seq = cfun->emit->sequence_stack;
3916 insn = seq->first, seq = seq->next);
3920 if (reg_mentioned_p (sp, insn))
3922 if (reg_mentioned_p (fb, insn))
3924 insn = NEXT_INSN (insn);
3929 /* Mark all the subexpressions of the PARALLEL rtx PAR as
3930 frame-related. Return PAR.
3932 dwarf2out.c:dwarf2out_frame_debug_expr ignores sub-expressions of a
3933 PARALLEL rtx other than the first if they do not have the
3934 FRAME_RELATED flag set on them. So this function is handy for
3935 marking up 'enter' instructions. */
3937 m32c_all_frame_related (rtx par)
3939 int len = XVECLEN (par, 0);
3942 for (i = 0; i < len; i++)
3943 F (XVECEXP (par, 0, i));
3948 /* Emits the prologue. See the frame layout comment earlier in this
3949 file. We can reserve up to 256 bytes with the ENTER opcode, beyond
3950 that we manually update sp. */
3952 m32c_emit_prologue (void)
3954 int frame_size, extra_frame_size = 0, reg_save_size;
3955 int complex_prologue = 0;
3957 cfun->machine->is_leaf = m32c_leaf_function_p ();
3958 if (interrupt_p (cfun->decl))
3960 cfun->machine->is_interrupt = 1;
3961 complex_prologue = 1;
3964 reg_save_size = m32c_pushm_popm (PP_justcount);
3966 if (interrupt_p (cfun->decl))
3967 emit_insn (gen_pushm (GEN_INT (cfun->machine->intr_pushm)));
3970 m32c_initial_elimination_offset (FB_REGNO, SP_REGNO) - reg_save_size;
3972 && !cfun->machine->is_interrupt
3973 && !m32c_function_needs_enter ())
3974 cfun->machine->use_rts = 1;
3976 if (frame_size > 254)
3978 extra_frame_size = frame_size - 254;
3981 if (cfun->machine->use_rts == 0)
3982 F (emit_insn (m32c_all_frame_related
3984 ? gen_prologue_enter_16 (GEN_INT (frame_size + 2))
3985 : gen_prologue_enter_24 (GEN_INT (frame_size + 4)))));
3987 if (extra_frame_size)
3989 complex_prologue = 1;
3991 F (emit_insn (gen_addhi3 (gen_rtx_REG (HImode, SP_REGNO),
3992 gen_rtx_REG (HImode, SP_REGNO),
3993 GEN_INT (-extra_frame_size))));
3995 F (emit_insn (gen_addpsi3 (gen_rtx_REG (PSImode, SP_REGNO),
3996 gen_rtx_REG (PSImode, SP_REGNO),
3997 GEN_INT (-extra_frame_size))));
4000 complex_prologue += m32c_pushm_popm (PP_pushm);
4002 /* This just emits a comment into the .s file for debugging. */
4003 if (complex_prologue)
4004 emit_insn (gen_prologue_end ());
4007 /* Likewise, for the epilogue. The only exception is that, for
4008 interrupts, we must manually unwind the frame as the REIT opcode
4011 m32c_emit_epilogue (void)
4013 /* This just emits a comment into the .s file for debugging. */
4014 if (m32c_pushm_popm (PP_justcount) > 0 || cfun->machine->is_interrupt)
4015 emit_insn (gen_epilogue_start ());
4017 m32c_pushm_popm (PP_popm);
4019 if (cfun->machine->is_interrupt)
4021 enum machine_mode spmode = TARGET_A16 ? HImode : PSImode;
4023 emit_move_insn (gen_rtx_REG (spmode, A0_REGNO),
4024 gen_rtx_REG (spmode, FP_REGNO));
4025 emit_move_insn (gen_rtx_REG (spmode, SP_REGNO),
4026 gen_rtx_REG (spmode, A0_REGNO));
4028 emit_insn (gen_pophi_16 (gen_rtx_REG (HImode, FP_REGNO)));
4030 emit_insn (gen_poppsi (gen_rtx_REG (PSImode, FP_REGNO)));
4031 emit_insn (gen_popm (GEN_INT (cfun->machine->intr_pushm)));
4033 emit_jump_insn (gen_epilogue_reit_16 ());
4035 emit_jump_insn (gen_epilogue_reit_24 ());
4037 else if (cfun->machine->use_rts)
4038 emit_jump_insn (gen_epilogue_rts ());
4039 else if (TARGET_A16)
4040 emit_jump_insn (gen_epilogue_exitd_16 ());
4042 emit_jump_insn (gen_epilogue_exitd_24 ());
4047 m32c_emit_eh_epilogue (rtx ret_addr)
4049 /* R0[R2] has the stack adjustment. R1[R3] has the address to
4050 return to. We have to fudge the stack, pop everything, pop SP
4051 (fudged), and return (fudged). This is actually easier to do in
4052 assembler, so punt to libgcc. */
4053 emit_jump_insn (gen_eh_epilogue (ret_addr, cfun->machine->eh_stack_adjust));
4054 /* emit_insn (gen_rtx_CLOBBER (HImode, gen_rtx_REG (HImode, R0L_REGNO))); */
4058 /* Indicate which flags must be properly set for a given conditional. */
4060 flags_needed_for_conditional (rtx cond)
4062 switch (GET_CODE (cond))
4086 /* Returns true if a compare insn is redundant because it would only
4087 set flags that are already set correctly. */
4089 m32c_compare_redundant (rtx cmp, rtx *operands)
4104 fprintf(stderr, "\n\033[32mm32c_compare_redundant\033[0m\n");
4108 fprintf(stderr, "operands[%d] = ", i);
4109 debug_rtx(operands[i]);
4113 next = next_nonnote_insn (cmp);
4114 if (!next || !INSN_P (next))
4117 fprintf(stderr, "compare not followed by insn\n");
4122 if (GET_CODE (PATTERN (next)) == SET
4123 && GET_CODE (XEXP ( PATTERN (next), 1)) == IF_THEN_ELSE)
4125 next = XEXP (XEXP (PATTERN (next), 1), 0);
4127 else if (GET_CODE (PATTERN (next)) == SET)
4129 /* If this is a conditional, flags_needed will be something
4130 other than FLAGS_N, which we test below. */
4131 next = XEXP (PATTERN (next), 1);
4136 fprintf(stderr, "compare not followed by conditional\n");
4142 fprintf(stderr, "conditional is: ");
4146 flags_needed = flags_needed_for_conditional (next);
4147 if (flags_needed == FLAGS_N)
4150 fprintf(stderr, "compare not followed by conditional\n");
4156 /* Compare doesn't set overflow and carry the same way that
4157 arithmetic instructions do, so we can't replace those. */
4158 if (flags_needed & FLAGS_OC)
4163 prev = prev_nonnote_insn (prev);
4167 fprintf(stderr, "No previous insn.\n");
4174 fprintf(stderr, "Previous insn is a non-insn.\n");
4178 pp = PATTERN (prev);
4179 if (GET_CODE (pp) != SET)
4182 fprintf(stderr, "Previous insn is not a SET.\n");
4186 pflags = get_attr_flags (prev);
4188 /* Looking up attributes of previous insns corrupted the recog
4190 INSN_UID (cmp) = -1;
4191 recog (PATTERN (cmp), cmp, 0);
4193 if (pflags == FLAGS_N
4194 && reg_mentioned_p (op0, pp))
4197 fprintf(stderr, "intermediate non-flags insn uses op:\n");
4202 } while (pflags == FLAGS_N);
4204 fprintf(stderr, "previous flag-setting insn:\n");
4209 if (GET_CODE (pp) == SET
4210 && GET_CODE (XEXP (pp, 0)) == REG
4211 && REGNO (XEXP (pp, 0)) == FLG_REGNO
4212 && GET_CODE (XEXP (pp, 1)) == COMPARE)
4214 /* Adjacent cbranches must have the same operands to be
4216 rtx pop0 = XEXP (XEXP (pp, 1), 0);
4217 rtx pop1 = XEXP (XEXP (pp, 1), 1);
4219 fprintf(stderr, "adjacent cbranches\n");
4223 if (rtx_equal_p (op0, pop0)
4224 && rtx_equal_p (op1, pop1))
4227 fprintf(stderr, "prev cmp not same\n");
4232 /* Else the previous insn must be a SET, with either the source or
4233 dest equal to operands[0], and operands[1] must be zero. */
4235 if (!rtx_equal_p (op1, const0_rtx))
4238 fprintf(stderr, "operands[1] not const0_rtx\n");
4242 if (GET_CODE (pp) != SET)
4245 fprintf (stderr, "pp not set\n");
4249 if (!rtx_equal_p (op0, SET_SRC (pp))
4250 && !rtx_equal_p (op0, SET_DEST (pp)))
4253 fprintf(stderr, "operands[0] not found in set\n");
4259 fprintf(stderr, "cmp flags %x prev flags %x\n", flags_needed, pflags);
4261 if ((pflags & flags_needed) == flags_needed)
4267 /* Return the pattern for a compare. This will be commented out if
4268 the compare is redundant, else a normal pattern is returned. Thus,
4269 the assembler output says where the compare would have been. */
4271 m32c_output_compare (rtx insn, rtx *operands)
4273 static char template[] = ";cmp.b\t%1,%0";
4276 template[5] = " bwll"[GET_MODE_SIZE(GET_MODE(operands[0]))];
4277 if (m32c_compare_redundant (insn, operands))
4280 fprintf(stderr, "cbranch: cmp not needed\n");
4286 fprintf(stderr, "cbranch: cmp needed: `%s'\n", template);
4288 return template + 1;
4291 #undef TARGET_ENCODE_SECTION_INFO
4292 #define TARGET_ENCODE_SECTION_INFO m32c_encode_section_info
4294 /* The Global `targetm' Variable. */
4296 struct gcc_target targetm = TARGET_INITIALIZER;
4298 #include "gt-m32c.h"