1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors
2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
69 ;; UNSPEC values used in iq2000.md
72 ;; 1 movsi_us, get_fnaddr
74 ;; 20 builtin_setjmp_setup
76 ;; UNSPEC_VOLATILE values
80 ;; 4 exception_receiver
92 ;; ....................
96 ;; ....................
98 ;; Classification of each insn.
99 ;; branch conditional branch
100 ;; jump unconditional jump
101 ;; call unconditional call
102 ;; load load instruction(s)
103 ;; store store instruction(s)
104 ;; move data movement within same register set
105 ;; xfer transfer to/from coprocessor
106 ;; arith integer arithmetic instruction
107 ;; darith double precision integer arithmetic instructions
108 ;; imul integer multiply
109 ;; idiv integer divide
110 ;; icmp integer compare
111 ;; fadd floating point add/subtract
112 ;; fmul floating point multiply
113 ;; fmadd floating point multiply-add
114 ;; fdiv floating point divide
115 ;; fabs floating point absolute value
116 ;; fneg floating point negation
117 ;; fcmp floating point compare
118 ;; fcvt floating point convert
119 ;; fsqrt floating point square root
120 ;; multi multiword sequence (or user asm statements)
124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
125 (const_string "unknown"))
127 ;; Main data type used by the insn
128 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
130 ;; Length (in # of bytes). A conditional branch is allowed only to a
131 ;; location within a signed 18-bit offset of the delay slot. If that
132 ;; provides too small a range, we use the `j' instruction. This
133 ;; instruction takes a 28-bit value, but that value is not an offset.
134 ;; Instead, it's bitwise-ored with the high-order four bits of the
135 ;; instruction in the delay slot, which means it cannot be used to
136 ;; cross a 256MB boundary. We could fall back back on the jr,
137 ;; instruction which allows full access to the entire address space,
138 ;; but we do not do so at present.
140 (define_attr "length" ""
141 (cond [(eq_attr "type" "branch")
142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
150 (const (symbol_ref "iq2000_cpu_attr")))
152 ;; Does the instruction have a mandatory delay slot? has_dslot
153 ;; Can the instruction be in a delay slot? ok_in_dslot
154 ;; Can the instruction not be in a delay slot? not_in_dslot
155 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
157 (const_string "has_dslot")
158 (const_string "ok_in_dslot")))
160 ;; Attribute defining whether or not we can use the branch-likely instructions
162 (define_attr "branch_likely" "no,yes"
164 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
166 (const_string "no"))))
169 ;; Describe a user's asm statement.
170 (define_asm_attributes
171 [(set_attr "type" "multi")])
175 ;; .........................
177 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
179 ;; .........................
181 (define_delay (eq_attr "type" "jump")
182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
186 (define_delay (eq_attr "type" "branch")
187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])
191 (define_delay (eq_attr "type" "call")
192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
196 (include "predicates.md")
199 ;; .........................
203 ;; .........................
205 (define_automaton "iq2000")
206 (define_cpu_unit "core,memory" "iq2000")
208 (define_insn_reservation "nonmemory" 1
209 (eq_attr "type" "!load,move,store,xfer")
212 (define_insn_reservation "iq2000_load_move" 3
213 (and (eq_attr "type" "load,move")
214 (eq_attr "cpu" "iq2000"))
217 (define_insn_reservation "other_load_move" 1
218 (and (eq_attr "type" "load,move")
219 (eq_attr "cpu" "!iq2000"))
222 (define_insn_reservation "store" 1
223 (eq_attr "type" "store")
226 (define_insn_reservation "xfer" 2
227 (eq_attr "type" "xfer")
231 ;; ....................
235 ;; ....................
239 [(trap_if (const_int 1) (const_int 0))]
247 ;; ....................
251 ;; ....................
254 (define_expand "addsi3"
255 [(set (match_operand:SI 0 "register_operand" "=d")
256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
257 (match_operand:SI 2 "arith_operand" "dI")))]
261 (define_insn "addsi3_internal"
262 [(set (match_operand:SI 0 "register_operand" "=d,=d")
263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
264 (match_operand:SI 2 "arith_operand" "d,I")))]
269 [(set_attr "type" "arith")
270 (set_attr "mode" "SI")])
273 ;; ....................
277 ;; ....................
280 (define_expand "subsi3"
281 [(set (match_operand:SI 0 "register_operand" "=d")
282 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
283 (match_operand:SI 2 "arith_operand" "dI")))]
287 (define_insn "subsi3_internal"
288 [(set (match_operand:SI 0 "register_operand" "=d,=d")
289 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
290 (match_operand:SI 2 "arith_operand" "d,I")))]
295 [(set_attr "type" "arith")
296 (set_attr "mode" "SI")])
299 ;; ....................
301 ;; NEGATION and ONE'S COMPLEMENT
303 ;; ....................
305 (define_insn "negsi2"
306 [(set (match_operand:SI 0 "register_operand" "=d")
307 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
311 operands[2] = const0_rtx;
312 return \"subu\\t%0,%z2,%1\";
314 [(set_attr "type" "arith")
315 (set_attr "mode" "SI")])
317 (define_insn "one_cmplsi2"
318 [(set (match_operand:SI 0 "register_operand" "=d")
319 (not:SI (match_operand:SI 1 "register_operand" "d")))]
323 operands[2] = const0_rtx;
324 return \"nor\\t%0,%z2,%1\";
326 [(set_attr "type" "arith")
327 (set_attr "mode" "SI")])
330 ;; ....................
334 ;; ....................
337 (define_expand "andsi3"
338 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
339 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
340 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
345 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
346 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
347 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
351 if (which_alternative == 0)
352 return \"and\\t%0,%1,%2\";
353 else if (which_alternative == 1)
354 return \"andi\\t%0,%1,%x2\";
355 else if (which_alternative == 2)
357 if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
359 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
360 return \"andoui\\t%0,%1,%x2\";
364 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
365 return \"andoi\\t%0,%1,%x2\";
369 [(set_attr "type" "arith")
370 (set_attr "mode" "SI")])
372 (define_expand "iorsi3"
373 [(set (match_operand:SI 0 "register_operand" "=d,d")
374 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
375 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
380 [(set (match_operand:SI 0 "register_operand" "=d,d")
381 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
382 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
387 [(set_attr "type" "arith")
388 (set_attr "mode" "SI")])
390 (define_expand "xorsi3"
391 [(set (match_operand:SI 0 "register_operand" "=d,d")
392 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
393 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
398 [(set (match_operand:SI 0 "register_operand" "=d,d")
399 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
400 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
405 [(set_attr "type" "arith")
406 (set_attr "mode" "SI")])
408 (define_insn "*norsi3"
409 [(set (match_operand:SI 0 "register_operand" "=d")
410 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
411 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
414 [(set_attr "type" "arith")
415 (set_attr "mode" "SI")])
418 ;; ....................
422 ;; ....................
425 ;; Those for integer source operand are ordered widest source type first.
427 (define_expand "zero_extendhisi2"
428 [(set (match_operand:SI 0 "register_operand" "")
429 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
434 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
435 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
439 if (which_alternative == 0)
440 return \"andi\\t%0,%1,0xffff\";
442 return iq2000_move_1word (operands, insn, TRUE);
444 [(set_attr "type" "arith,load,load")
445 (set_attr "mode" "SI")
446 (set_attr "length" "4,4,8")])
448 (define_expand "zero_extendqihi2"
449 [(set (match_operand:HI 0 "register_operand" "")
450 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
455 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
456 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
460 if (which_alternative == 0)
461 return \"andi\\t%0,%1,0x00ff\";
463 return iq2000_move_1word (operands, insn, TRUE);
465 [(set_attr "type" "arith,load,load")
466 (set_attr "mode" "HI")
467 (set_attr "length" "4,4,8")])
469 (define_expand "zero_extendqisi2"
470 [(set (match_operand:SI 0 "register_operand" "")
471 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
476 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
477 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
481 if (which_alternative == 0)
482 return \"andi\\t%0,%1,0x00ff\";
484 return iq2000_move_1word (operands, insn, TRUE);
486 [(set_attr "type" "arith,load,load")
487 (set_attr "mode" "SI")
488 (set_attr "length" "4,4,8")])
491 ;; ....................
495 ;; ....................
498 ;; Those for integer source operand are ordered widest source type first.
500 ;; These patterns originally accepted general_operands, however, slightly
501 ;; better code is generated by only accepting register_operands, and then
502 ;; letting combine generate the lh and lb insns.
504 (define_expand "extendhisi2"
505 [(set (match_operand:SI 0 "register_operand" "")
506 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
510 if (optimize && GET_CODE (operands[1]) == MEM)
511 operands[1] = force_not_mem (operands[1]);
513 if (GET_CODE (operands[1]) != MEM)
515 rtx op1 = gen_lowpart (SImode, operands[1]);
516 rtx temp = gen_reg_rtx (SImode);
517 rtx shift = GEN_INT (16);
519 emit_insn (gen_ashlsi3 (temp, op1, shift));
520 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
525 (define_insn "extendhisi2_internal"
526 [(set (match_operand:SI 0 "register_operand" "=d,d")
527 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
529 "* return iq2000_move_1word (operands, insn, FALSE);"
530 [(set_attr "type" "load")
531 (set_attr "mode" "SI")
532 (set_attr "length" "4,8")])
534 (define_expand "extendqihi2"
535 [(set (match_operand:HI 0 "register_operand" "")
536 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
540 if (optimize && GET_CODE (operands[1]) == MEM)
541 operands[1] = force_not_mem (operands[1]);
543 if (GET_CODE (operands[1]) != MEM)
545 rtx op0 = gen_lowpart (SImode, operands[0]);
546 rtx op1 = gen_lowpart (SImode, operands[1]);
547 rtx temp = gen_reg_rtx (SImode);
548 rtx shift = GEN_INT (24);
550 emit_insn (gen_ashlsi3 (temp, op1, shift));
551 emit_insn (gen_ashrsi3 (op0, temp, shift));
556 (define_insn "extendqihi2_internal"
557 [(set (match_operand:HI 0 "register_operand" "=d,d")
558 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
560 "* return iq2000_move_1word (operands, insn, FALSE);"
561 [(set_attr "type" "load")
562 (set_attr "mode" "SI")
563 (set_attr "length" "4,8")])
566 (define_expand "extendqisi2"
567 [(set (match_operand:SI 0 "register_operand" "")
568 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
572 if (optimize && GET_CODE (operands[1]) == MEM)
573 operands[1] = force_not_mem (operands[1]);
575 if (GET_CODE (operands[1]) != MEM)
577 rtx op1 = gen_lowpart (SImode, operands[1]);
578 rtx temp = gen_reg_rtx (SImode);
579 rtx shift = GEN_INT (24);
581 emit_insn (gen_ashlsi3 (temp, op1, shift));
582 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
587 (define_insn "extendqisi2_insn"
588 [(set (match_operand:SI 0 "register_operand" "=d,d")
589 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
591 "* return iq2000_move_1word (operands, insn, FALSE);"
592 [(set_attr "type" "load")
593 (set_attr "mode" "SI")
594 (set_attr "length" "4,8")])
597 ;; ........................
599 ;; BIT FIELD EXTRACTION
601 ;; ........................
604 [(set (match_operand:SI 0 "register_operand" "=r")
605 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
606 (match_operand:SI 2 "const_int_operand" "O")
607 (match_operand:SI 3 "const_int_operand" "O")))]
612 value[2] = INTVAL (operands[2]);
613 value[3] = INTVAL (operands[3]);
614 operands[2] = GEN_INT ((value[3]));
615 operands[3] = GEN_INT ((32 - value[2]));
616 return \"ram\\t%0,%1,%2,%3,0x0\";
618 [(set_attr "type" "arith")])
621 ;; ....................
625 ;; ....................
627 /* Take care of constants that don't fit in single instruction */
629 [(set (match_operand:SI 0 "register_operand" "")
630 (match_operand:SI 1 "general_operand" ""))]
631 "(reload_in_progress || reload_completed)
632 && large_int (operands[1], SImode)"
635 (high:SI (match_dup 1)))
637 (lo_sum:SI (match_dup 0)
641 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be
645 [(set (match_operand:SI 0 "register_operand" "=r")
646 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
648 "lui\\t%0,%%hi(%1) # high"
649 [(set_attr "type" "move")])
652 [(set (match_operand:SI 0 "register_operand" "=r")
653 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
654 (match_operand:SI 2 "immediate_operand" "")))]
656 "addiu\\t%0,%1,%%lo(%2) # low"
657 [(set_attr "type" "arith")
658 (set_attr "mode" "SI")])
660 ;; 32-bit Integer moves
663 [(set (match_operand:SI 0 "register_operand" "")
664 (match_operand:SI 1 "large_int" ""))]
665 "reload_in_progress | reload_completed"
669 (ior:SI (match_dup 0)
673 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
676 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
679 ;; Unlike most other insns, the move insns can't be split with
680 ;; different predicates, because register spilling and other parts of
681 ;; the compiler, have memoized the insn number already.
683 (define_expand "movsi"
684 [(set (match_operand:SI 0 "nonimmediate_operand" "")
685 (match_operand:SI 1 "general_operand" ""))]
689 if (iq2000_check_split (operands[1], SImode))
691 enum machine_mode mode = GET_MODE (operands[0]);
692 rtx tem = ((reload_in_progress | reload_completed)
693 ? operands[0] : gen_reg_rtx (mode));
695 emit_insn (gen_rtx_SET (VOIDmode, tem,
696 gen_rtx_HIGH (mode, operands[1])));
698 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
701 if ((reload_in_progress | reload_completed) == 0
702 && !register_operand (operands[0], SImode)
703 && !register_operand (operands[1], SImode)
704 && (GET_CODE (operands[1]) != CONST_INT
705 || INTVAL (operands[1]) != 0))
707 rtx temp = force_reg (SImode, operands[1]);
708 emit_move_insn (operands[0], temp);
712 /* Take care of constants that don't fit in single instruction */
713 if ((reload_in_progress || reload_completed)
714 && CONSTANT_P (operands[1])
715 && GET_CODE (operands[1]) != HIGH
716 && GET_CODE (operands[1]) != LO_SUM
717 && ! SMALL_INT_UNSIGNED (operands[1]))
719 rtx tem = ((reload_in_progress | reload_completed)
720 ? operands[0] : gen_reg_rtx (SImode));
722 emit_insn (gen_rtx_SET (VOIDmode, tem,
723 gen_rtx_HIGH (SImode, operands[1])));
724 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]);
728 ;; The difference between these two is whether or not ints are allowed
729 ;; in FP registers (off by default, use -mdebugh to enable).
731 (define_insn "movsi_internal2"
732 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
733 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
734 "(register_operand (operands[0], SImode)
735 || register_operand (operands[1], SImode)
736 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
737 "* return iq2000_move_1word (operands, insn, FALSE);"
738 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,move,move,move")
739 (set_attr "mode" "SI")
740 (set_attr "length" "4,8,4,8,4,8,4,8,4,4,4,4,4,4")])
742 ;; 16-bit Integer moves
744 ;; Unlike most other insns, the move insns can't be split with
745 ;; different predicates, because register spilling and other parts of
746 ;; the compiler, have memoized the insn number already.
747 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
749 (define_expand "movhi"
750 [(set (match_operand:HI 0 "nonimmediate_operand" "")
751 (match_operand:HI 1 "general_operand" ""))]
755 if ((reload_in_progress | reload_completed) == 0
756 && !register_operand (operands[0], HImode)
757 && !register_operand (operands[1], HImode)
758 && ((GET_CODE (operands[1]) != CONST_INT
759 || INTVAL (operands[1]) != 0)))
761 rtx temp = force_reg (HImode, operands[1]);
762 emit_move_insn (operands[0], temp);
767 ;; The difference between these two is whether or not ints are allowed
768 ;; in FP registers (off by default, use -mdebugh to enable).
770 (define_insn "movhi_internal2"
771 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
772 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
773 "(register_operand (operands[0], HImode)
774 || register_operand (operands[1], HImode)
775 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
776 "* return iq2000_move_1word (operands, insn, TRUE);"
777 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move")
778 (set_attr "mode" "HI")
779 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
781 ;; 8-bit Integer moves
783 ;; Unlike most other insns, the move insns can't be split with
784 ;; different predicates, because register spilling and other parts of
785 ;; the compiler, have memoized the insn number already.
786 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
788 (define_expand "movqi"
789 [(set (match_operand:QI 0 "nonimmediate_operand" "")
790 (match_operand:QI 1 "general_operand" ""))]
794 if ((reload_in_progress | reload_completed) == 0
795 && !register_operand (operands[0], QImode)
796 && !register_operand (operands[1], QImode)
797 && (GET_CODE (operands[1]) != CONST_INT
798 || INTVAL (operands[1]) != 0))
800 rtx temp = force_reg (QImode, operands[1]);
801 emit_move_insn (operands[0], temp);
806 ;; The difference between these two is whether or not ints are allowed
807 ;; in FP registers (off by default, use -mdebugh to enable).
809 (define_insn "movqi_internal2"
810 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
811 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
812 "(register_operand (operands[0], QImode)
813 || register_operand (operands[1], QImode)
814 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
815 "* return iq2000_move_1word (operands, insn, TRUE);"
816 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move")
817 (set_attr "mode" "QI")
818 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
820 ;; 32-bit floating point moves
822 (define_expand "movsf"
823 [(set (match_operand:SF 0 "general_operand" "")
824 (match_operand:SF 1 "general_operand" ""))]
828 if (!reload_in_progress
830 && GET_CODE (operands[0]) == MEM
831 && (GET_CODE (operands[1]) == MEM
832 || GET_CODE (operands[1]) == CONST_DOUBLE))
833 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
835 /* Take care of reg <- SF constant */
836 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) )
838 emit_insn (gen_movsf_high (operands[0], operands[1]));
839 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1]));
844 (define_insn "movsf_lo_sum"
845 [(set (match_operand:SF 0 "register_operand" "=r")
846 (lo_sum:SF (match_operand:SF 1 "register_operand" "r")
847 (match_operand:SF 2 "const_double_operand" "")))]
854 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]);
855 REAL_VALUE_TO_TARGET_SINGLE (r, i);
856 operands[2] = GEN_INT (i);
857 return \"addiu\\t%0,%1,%%lo(%2) # low\";
859 [(set_attr "length" "4")
860 (set_attr "type" "arith")])
862 (define_insn "movsf_high"
863 [(set (match_operand:SF 0 "register_operand" "=r")
864 (high:SF (match_operand:SF 1 "const_double_operand" "")))]
871 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
872 REAL_VALUE_TO_TARGET_SINGLE (r, i);
873 operands[1] = GEN_INT (i);
874 return \"lui\\t%0,%%hi(%1) # high\";
876 [(set_attr "length" "4")
877 (set_attr "type" "arith")])
879 (define_insn "*movsf_internal"
880 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
881 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
882 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)"
885 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn);
886 if (which_alternative == 0)
887 return \"or\\t%0,%1,%1\";
888 else if (which_alternative == 1)
889 return \"lw\\t%0,%1\";
890 else if (which_alternative == 2)
891 return \"sw\\t%1,%0\";
893 [(set_attr "length" "4,4,4")
894 (set_attr "type" "arith,load,store")]
898 ;; ....................
902 ;; ....................
904 (define_expand "ashlsi3"
905 [(set (match_operand:SI 0 "register_operand" "=d")
906 (ashift:SI (match_operand:SI 1 "register_operand" "d")
907 (match_operand:SI 2 "arith_operand" "dI")))]
911 (define_insn "ashlsi3_internal1"
912 [(set (match_operand:SI 0 "register_operand" "=d")
913 (ashift:SI (match_operand:SI 1 "register_operand" "d")
914 (match_operand:SI 2 "arith_operand" "dI")))]
918 if (GET_CODE (operands[2]) == CONST_INT)
920 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
921 return \"sll\\t%0,%1,%2\";
924 return \"sllv\\t%0,%1,%2\";
926 [(set_attr "type" "arith")
927 (set_attr "mode" "SI")])
929 (define_expand "ashrsi3"
930 [(set (match_operand:SI 0 "register_operand" "=d")
931 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
932 (match_operand:SI 2 "arith_operand" "dI")))]
936 (define_insn "ashrsi3_internal1"
937 [(set (match_operand:SI 0 "register_operand" "=d")
938 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
939 (match_operand:SI 2 "arith_operand" "dI")))]
943 if (GET_CODE (operands[2]) == CONST_INT)
945 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
946 return \"sra\\t%0,%1,%2\";
949 return \"srav\\t%0,%1,%2\";
951 [(set_attr "type" "arith")
952 (set_attr "mode" "SI")])
954 (define_expand "lshrsi3"
955 [(set (match_operand:SI 0 "register_operand" "=d")
956 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
957 (match_operand:SI 2 "arith_operand" "dI")))]
961 (define_insn "lshrsi3_internal1"
962 [(set (match_operand:SI 0 "register_operand" "=d")
963 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
964 (match_operand:SI 2 "arith_operand" "dI")))]
968 if (GET_CODE (operands[2]) == CONST_INT)
970 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
971 return \"srl\\t%0,%1,%2\";
974 return \"srlv\\t%0,%1,%2\";
976 [(set_attr "type" "arith")
977 (set_attr "mode" "SI")])
980 (define_insn "rotrsi3"
981 [(set (match_operand:SI 0 "register_operand" "=r")
982 (rotatert:SI (match_operand:SI 1 "register_operand" "r")
983 (match_operand:SI 2 "uns_arith_operand" "O")))]
985 "ram %0,%1,%2,0x0,0x0"
986 [(set_attr "type" "arith")])
990 ;; ....................
994 ;; ....................
996 ;; Flow here is rather complex:
998 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
999 ;; arguments into the branch_cmp array, and the type into
1000 ;; branch_type. No RTL is generated.
1002 ;; 2) The appropriate branch define_expand is called, which then
1003 ;; creates the appropriate RTL for the comparison and branch.
1004 ;; Different CC modes are used, based on what type of branch is
1005 ;; done, so that we can constrain things appropriately. There
1006 ;; are assumptions in the rest of GCC that break if we fold the
1007 ;; operands into the branches for integer operations, and use cc0
1008 ;; for floating point, so we use the fp status register instead.
1009 ;; If needed, an appropriate temporary is created to hold the
1010 ;; of the integer compare.
1012 (define_expand "cmpsi"
1014 (compare:CC (match_operand:SI 0 "register_operand" "")
1015 (match_operand:SI 1 "arith_operand" "")))]
1019 if (operands[0]) /* avoid unused code message */
1021 branch_cmp[0] = operands[0];
1022 branch_cmp[1] = operands[1];
1023 branch_type = CMP_SI;
1028 (define_expand "tstsi"
1030 (match_operand:SI 0 "register_operand" ""))]
1034 if (operands[0]) /* avoid unused code message */
1036 branch_cmp[0] = operands[0];
1037 branch_cmp[1] = const0_rtx;
1038 branch_type = CMP_SI;
1044 ;; ....................
1046 ;; CONDITIONAL BRANCHES
1048 ;; ....................
1050 ;; Conditional branches on comparisons with zero.
1052 (define_insn "branch_zero"
1055 (match_operator:SI 0 "cmp_op"
1056 [(match_operand:SI 2 "register_operand" "d")
1058 (label_ref (match_operand 1 "" ""))
1063 return iq2000_output_conditional_branch (insn,
1065 /*two_operands_p=*/0,
1068 get_attr_length (insn));
1070 [(set_attr "type" "branch")
1071 (set_attr "mode" "none")])
1073 (define_insn "branch_zero_inverted"
1076 (match_operator:SI 0 "cmp_op"
1077 [(match_operand:SI 2 "register_operand" "d")
1080 (label_ref (match_operand 1 "" ""))))]
1084 return iq2000_output_conditional_branch (insn,
1086 /*two_operands_p=*/0,
1089 get_attr_length (insn));
1091 [(set_attr "type" "branch")
1092 (set_attr "mode" "none")])
1094 ;; Conditional branch on equality comparison.
1096 (define_insn "branch_equality"
1099 (match_operator:SI 0 "equality_op"
1100 [(match_operand:SI 2 "register_operand" "d")
1101 (match_operand:SI 3 "register_operand" "d")])
1102 (label_ref (match_operand 1 "" ""))
1107 return iq2000_output_conditional_branch (insn,
1109 /*two_operands_p=*/1,
1112 get_attr_length (insn));
1114 [(set_attr "type" "branch")
1115 (set_attr "mode" "none")])
1117 (define_insn "branch_equality_inverted"
1120 (match_operator:SI 0 "equality_op"
1121 [(match_operand:SI 2 "register_operand" "d")
1122 (match_operand:SI 3 "register_operand" "d")])
1124 (label_ref (match_operand 1 "" ""))))]
1128 return iq2000_output_conditional_branch (insn,
1130 /*two_operands_p=*/1,
1133 get_attr_length (insn));
1135 [(set_attr "type" "branch")
1136 (set_attr "mode" "none")])
1138 (define_expand "beq"
1140 (if_then_else (eq:CC (cc0)
1142 (label_ref (match_operand 0 "" ""))
1147 if (operands[0]) /* avoid unused code warning */
1149 gen_conditional_branch (operands, EQ);
1154 (define_expand "bne"
1156 (if_then_else (ne:CC (cc0)
1158 (label_ref (match_operand 0 "" ""))
1163 if (operands[0]) /* avoid unused code warning */
1165 gen_conditional_branch (operands, NE);
1170 (define_expand "bgt"
1172 (if_then_else (gt:CC (cc0)
1174 (label_ref (match_operand 0 "" ""))
1179 if (operands[0]) /* avoid unused code warning */
1181 gen_conditional_branch (operands, GT);
1186 (define_expand "bge"
1188 (if_then_else (ge:CC (cc0)
1190 (label_ref (match_operand 0 "" ""))
1195 if (operands[0]) /* avoid unused code warning */
1197 gen_conditional_branch (operands, GE);
1202 (define_expand "blt"
1204 (if_then_else (lt:CC (cc0)
1206 (label_ref (match_operand 0 "" ""))
1211 if (operands[0]) /* avoid unused code warning */
1213 gen_conditional_branch (operands, LT);
1218 (define_expand "ble"
1220 (if_then_else (le:CC (cc0)
1222 (label_ref (match_operand 0 "" ""))
1227 if (operands[0]) /* avoid unused code warning */
1229 gen_conditional_branch (operands, LE);
1234 (define_expand "bgtu"
1236 (if_then_else (gtu:CC (cc0)
1238 (label_ref (match_operand 0 "" ""))
1243 if (operands[0]) /* avoid unused code warning */
1245 gen_conditional_branch (operands, GTU);
1250 (define_expand "bgeu"
1252 (if_then_else (geu:CC (cc0)
1254 (label_ref (match_operand 0 "" ""))
1259 if (operands[0]) /* avoid unused code warning */
1261 gen_conditional_branch (operands, GEU);
1267 (define_expand "bltu"
1269 (if_then_else (ltu:CC (cc0)
1271 (label_ref (match_operand 0 "" ""))
1276 if (operands[0]) /* avoid unused code warning */
1278 gen_conditional_branch (operands, LTU);
1283 (define_expand "bleu"
1285 (if_then_else (leu:CC (cc0)
1287 (label_ref (match_operand 0 "" ""))
1292 if (operands[0]) /* avoid unused code warning */
1294 gen_conditional_branch (operands, LEU);
1299 ;; Recognize bbi and bbin instructions. These use two unusual template
1300 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF
1301 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC
1302 ;; and outputs the operand if `x' is a LABEL_REF.
1307 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1309 (match_operand:SI 1 "arith_operand" "I"))
1311 (match_operand 2 "pc_or_label_operand" "")
1312 (match_operand 3 "pc_or_label_operand" "")))]
1314 "bb%A2\\t%0(31-%1),%P2%P3"
1315 [(set_attr "length" "4")
1316 (set_attr "type" "branch")])
1321 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1323 (match_operand:SI 1 "arith_operand" "I"))
1325 (match_operand 2 "pc_or_label_operand" "")
1326 (match_operand 3 "pc_or_label_operand" "")))]
1328 "bb%A3\\t%0(31-%1),%P2%P3"
1329 [(set_attr "length" "4")
1330 (set_attr "type" "branch")])
1335 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1337 (match_operand:SI 1 "arith_operand" "I"))
1339 (match_operand 2 "pc_or_label_operand" "")
1340 (match_operand 3 "pc_or_label_operand" "")))]
1342 "bb%A2\\t%0(31-%1),%P2%P3"
1343 [(set_attr "length" "4")
1344 (set_attr "type" "branch")])
1349 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1351 (match_operand:SI 1 "arith_operand" "I"))
1353 (match_operand 2 "pc_or_label_operand" "")
1354 (match_operand 3 "pc_or_label_operand" "")))]
1356 "bb%A3\\t%0(31-%1),%P2%P3"
1357 [(set_attr "length" "4")
1358 (set_attr "type" "branch")])
1363 (eq (and:SI (match_operand:SI 0 "register_operand" "r")
1364 (match_operand:SI 1 "power_of_2_operand" "I"))
1366 (match_operand 2 "pc_or_label_operand" "")
1367 (match_operand 3 "pc_or_label_operand" "")))]
1369 "bb%A3\\t%0(%p1),%P2%P3"
1370 [(set_attr "length" "4")
1371 (set_attr "type" "branch")])
1376 (ne (and:SI (match_operand:SI 0 "register_operand" "r")
1377 (match_operand:SI 1 "power_of_2_operand" "I"))
1379 (match_operand 2 "pc_or_label_operand" "")
1380 (match_operand 3 "pc_or_label_operand" "")))]
1382 "bb%A2\\t%0(%p1),%P2%P3"
1383 [(set_attr "length" "4")
1384 (set_attr "type" "branch")])
1387 ;; ....................
1389 ;; SETTING A REGISTER FROM A COMPARISON
1391 ;; ....................
1393 (define_expand "seq"
1394 [(set (match_operand:SI 0 "register_operand" "=d")
1395 (eq:SI (match_dup 1)
1400 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1403 /* Set up operands from compare. */
1404 operands[1] = branch_cmp[0];
1405 operands[2] = branch_cmp[1];
1407 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
1412 (define_insn "seq_si_zero"
1413 [(set (match_operand:SI 0 "register_operand" "=d")
1414 (eq:SI (match_operand:SI 1 "register_operand" "d")
1418 [(set_attr "type" "arith")
1419 (set_attr "mode" "SI")])
1421 (define_expand "sne"
1422 [(set (match_operand:SI 0 "register_operand" "=d")
1423 (ne:SI (match_dup 1)
1428 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1431 /* Set up operands from compare. */
1432 operands[1] = branch_cmp[0];
1433 operands[2] = branch_cmp[1];
1435 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
1439 (define_insn "sne_si_zero"
1440 [(set (match_operand:SI 0 "register_operand" "=d")
1441 (ne:SI (match_operand:SI 1 "register_operand" "d")
1445 [(set_attr "type" "arith")
1446 (set_attr "mode" "SI")])
1448 (define_expand "sgt"
1449 [(set (match_operand:SI 0 "register_operand" "=d")
1450 (gt:SI (match_dup 1)
1455 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1458 /* Set up operands from compare. */
1459 operands[1] = branch_cmp[0];
1460 operands[2] = branch_cmp[1];
1462 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
1466 (define_insn "sgt_si"
1467 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1468 (gt:SI (match_operand:SI 1 "register_operand" "d,d")
1469 (match_operand:SI 2 "reg_or_0_operand" "d,J")))]
1474 [(set_attr "type" "arith,arith")
1475 (set_attr "mode" "SI,SI")])
1477 (define_expand "sge"
1478 [(set (match_operand:SI 0 "register_operand" "=d")
1479 (ge:SI (match_dup 1)
1484 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1487 /* Set up operands from compare. */
1488 operands[1] = branch_cmp[0];
1489 operands[2] = branch_cmp[1];
1491 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
1495 (define_expand "slt"
1496 [(set (match_operand:SI 0 "register_operand" "=d")
1497 (lt:SI (match_dup 1)
1502 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1505 /* Set up operands from compare. */
1506 operands[1] = branch_cmp[0];
1507 operands[2] = branch_cmp[1];
1509 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
1513 (define_insn "slt_si"
1514 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1515 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
1516 (match_operand:SI 2 "arith_operand" "d,I")))]
1521 [(set_attr "type" "arith,arith")
1522 (set_attr "mode" "SI,SI")])
1524 (define_expand "sle"
1525 [(set (match_operand:SI 0 "register_operand" "=d")
1526 (le:SI (match_dup 1)
1531 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1534 /* Set up operands from compare. */
1535 operands[1] = branch_cmp[0];
1536 operands[2] = branch_cmp[1];
1538 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
1542 (define_insn "sle_si_const"
1543 [(set (match_operand:SI 0 "register_operand" "=d")
1544 (le:SI (match_operand:SI 1 "register_operand" "d")
1545 (match_operand:SI 2 "small_int" "I")))]
1546 "INTVAL (operands[2]) < 32767"
1549 operands[2] = GEN_INT (INTVAL (operands[2])+1);
1550 return \"slti\\t%0,%1,%2\";
1552 [(set_attr "type" "arith")
1553 (set_attr "mode" "SI")])
1555 (define_expand "sgtu"
1556 [(set (match_operand:SI 0 "register_operand" "=d")
1557 (gtu:SI (match_dup 1)
1562 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1565 /* Set up operands from compare. */
1566 operands[1] = branch_cmp[0];
1567 operands[2] = branch_cmp[1];
1569 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
1573 (define_insn "sgtu_si"
1574 [(set (match_operand:SI 0 "register_operand" "=d")
1575 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1576 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
1579 [(set_attr "type" "arith")
1580 (set_attr "mode" "SI")])
1583 [(set (match_operand:SI 0 "register_operand" "=t")
1584 (gtu:SI (match_operand:SI 1 "register_operand" "d")
1585 (match_operand:SI 2 "register_operand" "d")))]
1588 [(set_attr "type" "arith")
1589 (set_attr "mode" "SI")])
1591 (define_expand "sgeu"
1592 [(set (match_operand:SI 0 "register_operand" "=d")
1593 (geu:SI (match_dup 1)
1598 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1601 /* Set up operands from compare. */
1602 operands[1] = branch_cmp[0];
1603 operands[2] = branch_cmp[1];
1605 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
1609 (define_expand "sltu"
1610 [(set (match_operand:SI 0 "register_operand" "=d")
1611 (ltu:SI (match_dup 1)
1616 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1619 /* Set up operands from compare. */
1620 operands[1] = branch_cmp[0];
1621 operands[2] = branch_cmp[1];
1623 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
1627 (define_insn "sltu_si"
1628 [(set (match_operand:SI 0 "register_operand" "=d,=d")
1629 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
1630 (match_operand:SI 2 "arith_operand" "d,I")))]
1635 [(set_attr "type" "arith,arith")
1636 (set_attr "mode" "SI,SI")])
1638 (define_expand "sleu"
1639 [(set (match_operand:SI 0 "register_operand" "=d")
1640 (leu:SI (match_dup 1)
1645 if (branch_type != CMP_SI && (branch_type != CMP_DI))
1648 /* Set up operands from compare. */
1649 operands[1] = branch_cmp[0];
1650 operands[2] = branch_cmp[1];
1652 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
1656 (define_insn "sleu_si_const"
1657 [(set (match_operand:SI 0 "register_operand" "=d")
1658 (leu:SI (match_operand:SI 1 "register_operand" "d")
1659 (match_operand:SI 2 "small_int" "I")))]
1660 "INTVAL (operands[2]) < 32767"
1663 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
1664 return \"sltiu\\t%0,%1,%2\";
1666 [(set_attr "type" "arith")
1667 (set_attr "mode" "SI")])
1671 ;; ....................
1673 ;; UNCONDITIONAL BRANCHES
1675 ;; ....................
1677 ;; Unconditional branches.
1681 (label_ref (match_operand 0 "" "")))]
1685 if (GET_CODE (operands[0]) == REG)
1688 /* return \"b\\t%l0\";*/
1690 [(set_attr "type" "jump")
1691 (set_attr "mode" "none")])
1693 (define_expand "indirect_jump"
1694 [(set (pc) (match_operand 0 "register_operand" "d"))]
1700 if (operands[0]) /* eliminate unused code warnings */
1703 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1704 operands[0] = copy_to_mode_reg (Pmode, dest);
1706 if (!(Pmode == DImode))
1707 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
1709 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
1715 (define_insn "indirect_jump_internal1"
1716 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
1717 "!(Pmode == DImode)"
1719 [(set_attr "type" "jump")
1720 (set_attr "mode" "none")])
1722 (define_expand "tablejump"
1724 (match_operand 0 "register_operand" "d"))
1725 (use (label_ref (match_operand 1 "" "")))]
1729 if (operands[0]) /* eliminate unused code warnings */
1731 gcc_assert (GET_MODE (operands[0]) == Pmode);
1733 if (!(Pmode == DImode))
1734 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
1736 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
1742 (define_insn "tablejump_internal1"
1744 (match_operand:SI 0 "register_operand" "d"))
1745 (use (label_ref (match_operand 1 "" "")))]
1746 "!(Pmode == DImode)"
1748 [(set_attr "type" "jump")
1749 (set_attr "mode" "none")])
1751 (define_expand "tablejump_internal3"
1752 [(parallel [(set (pc)
1753 (plus:SI (match_operand:SI 0 "register_operand" "d")
1754 (label_ref:SI (match_operand 1 "" ""))))
1755 (use (label_ref:SI (match_dup 1)))])]
1759 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
1760 ;;; it is not valid. ??? With the USE, the condition tests may not be required
1763 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
1764 ;;; We just use the conservative number here.
1768 (plus:SI (match_operand:SI 0 "register_operand" "d")
1769 (label_ref:SI (match_operand 1 "" ""))))
1770 (use (label_ref:SI (match_dup 1)))]
1771 "!(Pmode == DImode) && next_active_insn (insn) != 0
1772 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
1773 && PREV_INSN (next_active_insn (insn)) == operands[1]"
1778 [(set_attr "type" "jump")
1779 (set_attr "mode" "none")
1780 (set_attr "length" "8")])
1783 ;; ....................
1785 ;; Function prologue/epilogue
1787 ;; ....................
1790 (define_expand "prologue"
1795 if (iq2000_isa >= 0) /* avoid unused code warnings */
1797 iq2000_expand_prologue ();
1802 ;; Block any insns from being moved before this point, since the
1803 ;; profiling call to mcount can use various registers that aren't
1804 ;; saved or used to pass arguments.
1806 (define_insn "blockage"
1807 [(unspec_volatile [(const_int 0)] 0)]
1810 [(set_attr "type" "unknown")
1811 (set_attr "mode" "none")
1812 (set_attr "length" "0")])
1814 (define_expand "epilogue"
1819 if (iq2000_isa >= 0) /* avoid unused code warnings */
1821 iq2000_expand_epilogue ();
1826 ;; Trivial return. Make it look like a normal return insn as that
1827 ;; allows jump optimizations to work better .
1828 (define_insn "return"
1830 "iq2000_can_use_return_insn ()"
1832 [(set_attr "type" "jump")
1833 (set_attr "mode" "none")])
1837 (define_insn "return_internal"
1838 [(use (match_operand 0 "pmode_register_operand" ""))
1845 [(set_attr "type" "jump")
1846 (set_attr "mode" "none")])
1848 (define_insn "eh_return_internal"
1855 [(set_attr "type" "jump")
1856 (set_attr "mode" "none")])
1858 (define_expand "eh_return"
1859 [(use (match_operand:SI 0 "register_operand" "r"))]
1863 iq2000_expand_eh_return (operands[0]);
1869 ;; ....................
1873 ;; ....................
1875 ;; calls.c now passes a third argument, make saber happy
1877 (define_expand "call"
1878 [(parallel [(call (match_operand 0 "memory_operand" "m")
1879 (match_operand 1 "" "i"))
1880 (clobber (reg:SI 31))
1881 (use (match_operand 2 "" "")) ;; next_arg_reg
1882 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
1888 if (operands[0]) /* eliminate unused code warnings */
1890 addr = XEXP (operands[0], 0);
1891 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1892 || ! call_insn_operand (addr, VOIDmode))
1893 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1895 /* In order to pass small structures by value in registers
1896 compatibly with the IQ2000 compiler, we need to shift the value
1897 into the high part of the register. Function_arg has encoded
1898 a PARALLEL rtx, holding a vector of adjustments to be made
1899 as the next_arg_reg variable, so we split up the insns,
1900 and emit them separately. */
1902 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
1904 rtvec adjust = XVEC (operands[2], 0);
1905 int num = GET_NUM_ELEM (adjust);
1908 for (i = 0; i < num; i++)
1909 emit_insn (RTVEC_ELT (adjust, i));
1912 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
1913 gen_rtx_REG (SImode,
1914 GP_REG_FIRST + 31)));
1919 (define_expand "call_internal0"
1920 [(parallel [(call (match_operand 0 "" "")
1921 (match_operand 1 "" ""))
1922 (clobber (match_operand:SI 2 "" ""))])]
1926 (define_insn "call_internal1"
1927 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
1928 (match_operand 1 "" "i"))
1929 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1933 register rtx target = operands[0];
1935 if (GET_CODE (target) == CONST_INT)
1936 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
1937 else if (CONSTANT_ADDRESS_P (target))
1938 return \"jal\\t%0\";
1940 return \"jalr\\t%2,%0\";
1942 [(set_attr "type" "call")
1943 (set_attr "mode" "none")])
1945 ;; calls.c now passes a fourth argument, make saber happy
1947 (define_expand "call_value"
1948 [(parallel [(set (match_operand 0 "register_operand" "=df")
1949 (call (match_operand 1 "memory_operand" "m")
1950 (match_operand 2 "" "i")))
1951 (clobber (reg:SI 31))
1952 (use (match_operand 3 "" ""))])] ;; next_arg_reg
1958 if (operands[0]) /* eliminate unused code warning */
1960 addr = XEXP (operands[1], 0);
1961 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
1962 || ! call_insn_operand (addr, VOIDmode))
1963 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1965 /* In order to pass small structures by value in registers
1966 compatibly with the IQ2000 compiler, we need to shift the value
1967 into the high part of the register. Function_arg has encoded
1968 a PARALLEL rtx, holding a vector of adjustments to be made
1969 as the next_arg_reg variable, so we split up the insns,
1970 and emit them separately. */
1972 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
1974 rtvec adjust = XVEC (operands[3], 0);
1975 int num = GET_NUM_ELEM (adjust);
1978 for (i = 0; i < num; i++)
1979 emit_insn (RTVEC_ELT (adjust, i));
1982 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
1984 emit_call_insn (gen_call_value_multiple_internal0
1985 (XEXP (XVECEXP (operands[0], 0, 0), 0),
1986 operands[1], operands[2],
1987 XEXP (XVECEXP (operands[0], 0, 1), 0),
1988 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
1992 /* We have a call returning a DImode structure in an FP reg.
1993 Strip off the now unnecessary PARALLEL. */
1994 if (GET_CODE (operands[0]) == PARALLEL)
1995 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
1997 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
1998 gen_rtx_REG (SImode,
1999 GP_REG_FIRST + 31)));
2005 (define_expand "call_value_internal0"
2006 [(parallel [(set (match_operand 0 "" "")
2007 (call (match_operand 1 "" "")
2008 (match_operand 2 "" "")))
2009 (clobber (match_operand:SI 3 "" ""))])]
2013 (define_insn "call_value_internal1"
2014 [(set (match_operand 0 "register_operand" "=df")
2015 (call (mem (match_operand 1 "call_insn_operand" "ri"))
2016 (match_operand 2 "" "i")))
2017 (clobber (match_operand:SI 3 "register_operand" "=d"))]
2021 register rtx target = operands[1];
2023 if (GET_CODE (target) == CONST_INT)
2024 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
2025 else if (CONSTANT_ADDRESS_P (target))
2026 return \"jal\\t%1\";
2028 return \"jalr\\t%3,%1\";
2030 [(set_attr "type" "call")
2031 (set_attr "mode" "none")])
2033 (define_expand "call_value_multiple_internal0"
2034 [(parallel [(set (match_operand 0 "" "")
2035 (call (match_operand 1 "" "")
2036 (match_operand 2 "" "")))
2037 (set (match_operand 3 "" "")
2040 (clobber (match_operand:SI 4 "" ""))])]
2044 ;; ??? May eventually need all 6 versions of the call patterns with multiple
2047 (define_insn "call_value_multiple_internal1"
2048 [(set (match_operand 0 "register_operand" "=df")
2049 (call (mem (match_operand 1 "call_insn_operand" "ri"))
2050 (match_operand 2 "" "i")))
2051 (set (match_operand 3 "register_operand" "=df")
2052 (call (mem (match_dup 1))
2054 (clobber (match_operand:SI 4 "register_operand" "=d"))]
2058 register rtx target = operands[1];
2060 if (GET_CODE (target) == CONST_INT)
2061 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
2062 else if (CONSTANT_ADDRESS_P (target))
2063 return \"jal\\t%1\";
2065 return \"jalr\\t%4,%1\";
2067 [(set_attr "type" "call")
2068 (set_attr "mode" "none")])
2070 ;; Call subroutine returning any type.
2072 (define_expand "untyped_call"
2073 [(parallel [(call (match_operand 0 "" "")
2075 (match_operand 1 "" "")
2076 (match_operand 2 "" "")])]
2080 if (operands[0]) /* silence statement not reached warnings */
2084 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
2086 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2088 rtx set = XVECEXP (operands[2], 0, i);
2089 emit_move_insn (SET_DEST (set), SET_SRC (set));
2092 emit_insn (gen_blockage ());
2098 ;; ....................
2102 ;; ....................
2109 [(set_attr "type" "nop")
2110 (set_attr "mode" "none")])
2113 ;; For the rare case where we need to load an address into a register
2114 ;; that cannot be recognized by the normal movsi/addsi instructions.
2115 ;; I have no idea how many insns this can actually generate. It should
2116 ;; be rare, so over-estimating as 10 instructions should not have any
2117 ;; real performance impact.
2118 (define_insn "leasi"
2119 [(set (match_operand:SI 0 "register_operand" "=d")
2120 (match_operand:SI 1 "address_operand" "p"))]
2126 xoperands[0] = operands[0];
2127 xoperands[1] = XEXP (operands[1], 0);
2128 xoperands[2] = XEXP (operands[1], 1);
2129 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
2132 [(set_attr "type" "arith")
2133 (set_attr "mode" "SI")
2134 (set_attr "length" "40")])
2136 (define_insn "ado16"
2137 [(set (match_operand:SI 0 "register_operand" "=r")
2138 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2139 (match_operand:SI 2 "register_operand" "r")]
2142 "ado16\\t%0, %1, %2"
2146 [(set (match_operand:SI 0 "register_operand" "=r")
2147 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2148 (match_operand:SI 2 "const_int_operand" "I")
2149 (match_operand:SI 3 "const_int_operand" "I")
2150 (match_operand:SI 4 "const_int_operand" "I")]
2153 "ram\\t%0, %1, %2, %3, %4"
2156 (define_insn "chkhdr"
2157 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
2158 (match_operand:SI 1 "register_operand" "r")]
2161 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
2162 [(set_attr "dslot" "not_in_dslot")]
2166 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2167 (match_operand:SI 1 "register_operand" "r")]
2170 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
2171 [(set_attr "dslot" "not_in_dslot")]
2175 [(set (match_operand:SI 0 "register_operand" "=r")
2176 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2179 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2180 [(set_attr "dslot" "ok_in_dslot")]
2184 [(set (match_operand:SI 0 "register_operand" "=r")
2185 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2188 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2189 [(set_attr "dslot" "ok_in_dslot")]
2193 [(set (match_operand:SI 0 "register_operand" "=r")
2194 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2197 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2198 [(set_attr "dslot" "not_in_dslot")]
2202 [(set (match_operand:SI 0 "register_operand" "=r")
2203 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2206 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2207 [(set_attr "dslot" "not_in_dslot")]
2211 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2212 (match_operand:SI 1 "const_int_operand" "I")]
2215 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2216 [(set_attr "dslot" "ok_in_dslot")]
2220 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2221 (match_operand:SI 1 "const_int_operand" "I")]
2224 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2225 [(set_attr "dslot" "ok_in_dslot")]
2229 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2230 (match_operand:SI 1 "const_int_operand" "I")]
2233 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2234 [(set_attr "dslot" "ok_in_dslot")]
2238 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
2239 (match_operand:SI 1 "const_int_operand" "I")]
2242 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
2243 [(set_attr "dslot" "ok_in_dslot")]
2247 [(set (match_operand:SI 0 "register_operand" "=r")
2248 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2251 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2252 [(set_attr "dslot" "ok_in_dslot")]
2256 [(set (match_operand:SI 0 "register_operand" "=r")
2257 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2260 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2261 [(set_attr "dslot" "ok_in_dslot")]
2265 [(set (match_operand:SI 0 "register_operand" "=r")
2266 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2269 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2270 [(set_attr "dslot" "not_in_dslot")]
2274 [(set (match_operand:SI 0 "register_operand" "=r")
2275 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
2278 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
2279 [(set_attr "dslot" "not_in_dslot")]
2283 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2284 (match_operand:SI 1 "const_int_operand" "I")]
2287 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2288 [(set_attr "dslot" "ok_in_dslot")]
2292 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2293 (match_operand:SI 1 "const_int_operand" "I")]
2296 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2297 [(set_attr "dslot" "ok_in_dslot")]
2301 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2302 (match_operand:SI 1 "const_int_operand" "I")]
2305 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2306 [(set_attr "dslot" "ok_in_dslot")]
2310 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2311 (match_operand:SI 1 "const_int_operand" "I")]
2314 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
2315 [(set_attr "dslot" "ok_in_dslot")]
2319 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2320 (match_operand:SI 1 "register_operand" "r")]
2323 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
2324 [(set_attr "dslot" "not_in_dslot")]
2328 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2329 (match_operand:SI 1 "register_operand" "r")]
2332 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
2333 [(set_attr "dslot" "not_in_dslot")]
2337 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2338 (match_operand:SI 1 "register_operand" "r")]
2341 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
2342 [(set_attr "dslot" "not_in_dslot")]
2346 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2349 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
2350 [(set_attr "dslot" "not_in_dslot")]
2354 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2355 (match_operand:SI 1 "register_operand" "r")]
2358 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
2359 [(set_attr "dslot" "not_in_dslot")]
2363 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2364 (match_operand:SI 1 "register_operand" "r")]
2367 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
2368 [(set_attr "dslot" "not_in_dslot")]
2372 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2373 (match_operand:SI 1 "register_operand" "r")]
2376 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
2377 [(set_attr "dslot" "not_in_dslot")]
2380 (define_insn "luc32"
2381 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2382 (match_operand:SI 1 "register_operand" "r")]
2385 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
2386 [(set_attr "dslot" "not_in_dslot")]
2389 (define_insn "luc32l"
2390 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2391 (match_operand:SI 1 "register_operand" "r")]
2394 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2395 [(set_attr "dslot" "not_in_dslot")]
2398 (define_insn "luc64"
2399 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2400 (match_operand:SI 1 "register_operand" "r")]
2403 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
2404 [(set_attr "dslot" "not_in_dslot")]
2407 (define_insn "luc64l"
2408 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2409 (match_operand:SI 1 "register_operand" "r")]
2412 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2413 [(set_attr "dslot" "not_in_dslot")]
2417 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2418 (match_operand:SI 1 "register_operand" "r")]
2421 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
2422 [(set_attr "dslot" "ok_in_dslot")]
2425 (define_insn "lulck"
2426 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2429 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
2430 [(set_attr "dslot" "not_in_dslot")]
2433 (define_insn "lum32"
2434 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2435 (match_operand:SI 1 "register_operand" "r")]
2438 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
2439 [(set_attr "dslot" "not_in_dslot")]
2442 (define_insn "lum32l"
2443 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2444 (match_operand:SI 1 "register_operand" "r")]
2447 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);"
2448 [(set_attr "dslot" "not_in_dslot")]
2451 (define_insn "lum64"
2452 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2453 (match_operand:SI 1 "register_operand" "r")]
2456 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
2457 [(set_attr "dslot" "not_in_dslot")]
2460 (define_insn "lum64l"
2461 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2462 (match_operand:SI 1 "register_operand" "r")]
2465 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
2466 [(set_attr "dslot" "not_in_dslot")]
2470 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2471 (match_operand:SI 1 "register_operand" "r")]
2474 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
2475 [(set_attr "dslot" "not_in_dslot")]
2479 [(set (match_operand:SI 0 "register_operand" "=r")
2480 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
2481 (match_operand:SI 2 "register_operand" "r")
2482 (match_operand:SI 3 "const_int_operand" "I")]
2485 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);"
2486 [(set_attr "dslot" "ok_in_dslot")]
2489 (define_insn "srrdl"
2490 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2493 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);"
2494 [(set_attr "dslot" "not_in_dslot")]
2497 (define_insn "srulck"
2498 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2501 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);"
2502 [(set_attr "dslot" "not_in_dslot")]
2505 (define_insn "srwru"
2506 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2507 (match_operand:SI 1 "register_operand" "r")]
2510 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);"
2511 [(set_attr "dslot" "not_in_dslot")]
2514 (define_insn "trapqfl"
2515 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)]
2517 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);"
2518 [(set_attr "dslot" "not_in_dslot")]
2521 (define_insn "trapqne"
2522 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)]
2524 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);"
2525 [(set_attr "dslot" "not_in_dslot")]
2528 (define_insn "traprel"
2529 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2532 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);"
2533 [(set_attr "dslot" "not_in_dslot")]
2537 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
2538 (match_operand:SI 1 "register_operand" "r")]
2541 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);"
2542 [(set_attr "dslot" "not_in_dslot")]
2545 (define_insn "syscall"
2546 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)]
2549 [(set_attr "dslot" "not_in_dslot")]