1 ;; IA-64 machine description for vector operations.
2 ;; Copyright (C) 2004, 2005
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
22 ;; Integer vector operations
24 (define_mode_macro VECINT [V8QI V4HI V2SI])
25 (define_mode_macro VECINT12 [V8QI V4HI])
26 (define_mode_macro VECINT24 [V4HI V2SI])
27 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
29 (define_expand "mov<mode>"
30 [(set (match_operand:VECINT 0 "general_operand" "")
31 (match_operand:VECINT 1 "general_operand" ""))]
34 rtx op1 = ia64_expand_move (operands[0], operands[1]);
40 (define_insn "*mov<mode>_internal"
41 [(set (match_operand:VECINT 0 "destination_operand"
42 "=r,r,r,r,m ,*f ,*f,Q ,r ,*f")
43 (match_operand:VECINT 1 "move_operand"
44 "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))]
45 "ia64_move_ok (operands[0], operands[1])"
57 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")])
59 (define_insn "one_cmpl<mode>2"
60 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
61 (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
64 [(set_attr "itanium_class" "ilog")])
66 (define_insn "and<mode>3"
67 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
69 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
70 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
75 [(set_attr "itanium_class" "ilog,fmisc")])
77 (define_insn "*andnot<mode>"
78 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
80 (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f"))
81 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
86 [(set_attr "itanium_class" "ilog,fmisc")])
88 (define_insn "ior<mode>3"
89 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
91 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
92 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
97 [(set_attr "itanium_class" "ilog,fmisc")])
99 (define_insn "xor<mode>3"
100 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f")
102 (match_operand:VECINT 1 "grfr_register_operand" "r,*f")
103 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))]
108 [(set_attr "itanium_class" "ilog,fmisc")])
110 (define_insn "neg<mode>2"
111 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
112 (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))]
114 "psub<vecsize> %0 = r0, %1"
115 [(set_attr "itanium_class" "mmalua")])
117 (define_insn "add<mode>3"
118 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
119 (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
120 (match_operand:VECINT 2 "gr_register_operand" "r")))]
122 "padd<vecsize> %0 = %1, %2"
123 [(set_attr "itanium_class" "mmalua")])
125 (define_insn "*ssadd<mode>3"
126 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
128 (match_operand:VECINT12 1 "gr_register_operand" "r")
129 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
131 "padd<vecsize>.sss %0 = %1, %2"
132 [(set_attr "itanium_class" "mmalua")])
134 (define_insn "*usadd<mode>3"
135 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
137 (match_operand:VECINT12 1 "gr_register_operand" "r")
138 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
140 "padd<vecsize>.uuu %0 = %1, %2"
141 [(set_attr "itanium_class" "mmalua")])
143 (define_insn "sub<mode>3"
144 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
145 (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")
146 (match_operand:VECINT 2 "gr_register_operand" "r")))]
148 "psub<vecsize> %0 = %1, %2"
149 [(set_attr "itanium_class" "mmalua")])
151 (define_insn "*sssub<mode>3"
152 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
154 (match_operand:VECINT12 1 "gr_register_operand" "r")
155 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
157 "psub<vecsize>.sss %0 = %1, %2"
158 [(set_attr "itanium_class" "mmalua")])
160 (define_insn "*ussub<mode>3"
161 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r")
163 (match_operand:VECINT12 1 "gr_register_operand" "r")
164 (match_operand:VECINT12 2 "gr_register_operand" "r")))]
166 "psub<vecsize>.uuu %0 = %1, %2"
167 [(set_attr "itanium_class" "mmalua")])
169 (define_expand "mulv8qi3"
170 [(set (match_operand:V8QI 0 "gr_register_operand" "")
171 (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
172 (match_operand:V8QI 2 "gr_register_operand" "r")))]
175 rtx r1, l1, r2, l2, rm, lm;
177 r1 = gen_reg_rtx (V4HImode);
178 l1 = gen_reg_rtx (V4HImode);
179 r2 = gen_reg_rtx (V4HImode);
180 l2 = gen_reg_rtx (V4HImode);
182 /* Zero-extend the QImode elements into two words of HImode elements
183 by interleaving them with zero bytes. */
184 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r1),
185 operands[1], CONST0_RTX (V8QImode)));
186 emit_insn (gen_mix1_r (gen_lowpart (V8QImode, r2),
187 operands[2], CONST0_RTX (V8QImode)));
188 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l1),
189 operands[1], CONST0_RTX (V8QImode)));
190 emit_insn (gen_mix1_l (gen_lowpart (V8QImode, l2),
191 operands[2], CONST0_RTX (V8QImode)));
194 rm = gen_reg_rtx (V4HImode);
195 lm = gen_reg_rtx (V4HImode);
196 emit_insn (gen_mulv4hi3 (rm, r1, r2));
197 emit_insn (gen_mulv4hi3 (lm, l1, l2));
199 /* Zap the high order bytes of the HImode elements by overwriting those
200 in one part with the low order bytes of the other. */
201 emit_insn (gen_mix1_r (operands[0],
202 gen_lowpart (V8QImode, rm),
203 gen_lowpart (V8QImode, lm)));
207 (define_insn "mulv4hi3"
208 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
209 (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r")
210 (match_operand:V4HI 2 "gr_register_operand" "r")))]
212 "pmpyshr2 %0 = %1, %2, 0"
213 [(set_attr "itanium_class" "mmmul")])
215 (define_expand "umax<mode>3"
216 [(set (match_operand:VECINT 0 "gr_register_operand" "")
217 (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
218 (match_operand:VECINT 2 "gr_register_operand" "")))]
221 if (ia64_expand_vecint_minmax (UMAX, <MODE>mode, operands))
225 (define_expand "smax<mode>3"
226 [(set (match_operand:VECINT 0 "gr_register_operand" "")
227 (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
228 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
231 if (ia64_expand_vecint_minmax (SMAX, <MODE>mode, operands))
235 (define_expand "umin<mode>3"
236 [(set (match_operand:VECINT 0 "gr_register_operand" "")
237 (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
238 (match_operand:VECINT 2 "gr_register_operand" "")))]
241 if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands))
245 (define_expand "smin<mode>3"
246 [(set (match_operand:VECINT 0 "gr_register_operand" "")
247 (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
248 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
251 if (ia64_expand_vecint_minmax (SMIN, <MODE>mode, operands))
255 (define_insn "*umaxv8qi3"
256 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
257 (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
258 (match_operand:V8QI 2 "gr_register_operand" "r")))]
260 "pmax1.u %0 = %1, %2"
261 [(set_attr "itanium_class" "mmshf")])
263 (define_insn "*smaxv4hi3"
264 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
265 (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
266 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
268 "pmax2 %0 = %r1, %r2"
269 [(set_attr "itanium_class" "mmshf")])
271 (define_insn "*uminv8qi3"
272 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
273 (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r")
274 (match_operand:V8QI 2 "gr_register_operand" "r")))]
276 "pmin1.u %0 = %1, %2"
277 [(set_attr "itanium_class" "mmshf")])
279 (define_insn "*sminv4hi3"
280 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
281 (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
282 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))]
284 "pmin2 %0 = %r1, %r2"
285 [(set_attr "itanium_class" "mmshf")])
287 (define_insn "ashl<mode>3"
288 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
290 (match_operand:VECINT24 1 "gr_register_operand" "r")
291 (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
293 "pshl<vecsize> %0 = %1, %2"
294 [(set_attr "itanium_class" "mmshf")])
296 (define_insn "ashr<mode>3"
297 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
299 (match_operand:VECINT24 1 "gr_register_operand" "r")
300 (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
302 "pshr<vecsize> %0 = %1, %2"
303 [(set_attr "itanium_class" "mmshf")])
305 (define_insn "lshr<mode>3"
306 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
308 (match_operand:VECINT24 1 "gr_register_operand" "r")
309 (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
311 "pshr<vecsize>.u %0 = %1, %2"
312 [(set_attr "itanium_class" "mmshf")])
314 (define_expand "vec_shl_<mode>"
315 [(set (match_operand:VECINT 0 "gr_register_operand" "")
316 (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "")
317 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
320 operands[0] = gen_lowpart (DImode, operands[0]);
321 operands[1] = gen_lowpart (DImode, operands[1]);
324 (define_expand "vec_shr_<mode>"
325 [(set (match_operand:VECINT 0 "gr_register_operand" "")
326 (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "")
327 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
330 operands[0] = gen_lowpart (DImode, operands[0]);
331 operands[1] = gen_lowpart (DImode, operands[1]);
334 (define_expand "vcond<mode>"
335 [(set (match_operand:VECINT 0 "gr_register_operand" "")
338 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
339 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
340 (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
341 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
344 ia64_expand_vecint_cmov (operands);
348 (define_expand "vcondu<mode>"
349 [(set (match_operand:VECINT 0 "gr_register_operand" "")
352 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "")
353 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")])
354 (match_operand:VECINT 1 "gr_reg_or_0_operand" "")
355 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))]
358 ia64_expand_vecint_cmov (operands);
362 (define_insn "*cmpeq_<mode>"
363 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
364 (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
365 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
367 "pcmp<vecsize>.eq %0 = %r1, %r2"
368 [(set_attr "itanium_class" "mmalua")])
370 (define_insn "*cmpgt_<mode>"
371 [(set (match_operand:VECINT 0 "gr_register_operand" "=r")
372 (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU")
373 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))]
375 "pcmp<vecsize>.gt %0 = %r1, %r2"
376 [(set_attr "itanium_class" "mmalua")])
378 (define_insn "pack2_sss"
379 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
382 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
384 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
386 "pack2.sss %0 = %r1, %r2"
387 [(set_attr "itanium_class" "mmshf")])
389 (define_insn "*pack2_uss"
390 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
393 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU"))
395 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))]
397 "pack2.uss %0 = %r1, %r2"
398 [(set_attr "itanium_class" "mmshf")])
400 (define_insn "pack4_sss"
401 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
404 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU"))
406 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))]
408 "pack4.sss %0 = %r1, %r2"
409 [(set_attr "itanium_class" "mmshf")])
411 (define_insn "unpack1_l"
412 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
415 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
416 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
417 (parallel [(const_int 0)
426 "unpack1.l %0 = %r2, %r1"
427 [(set_attr "itanium_class" "mmshf")])
429 (define_insn "unpack1_h"
430 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
433 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
434 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
435 (parallel [(const_int 4)
444 "unpack1.h %0 = %r2, %r1"
445 [(set_attr "itanium_class" "mmshf")])
447 (define_insn "mix1_r"
448 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
451 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
452 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
453 (parallel [(const_int 0)
462 "mix1.r %0 = %r2, %r1"
463 [(set_attr "itanium_class" "mmshf")])
465 (define_insn "mix1_l"
466 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
469 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU")
470 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU"))
471 (parallel [(const_int 1)
480 "mix1.l %0 = %r2, %r1"
481 [(set_attr "itanium_class" "mmshf")])
483 (define_insn "*mux1_rev"
484 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
486 (match_operand:V8QI 1 "gr_register_operand" "r")
487 (parallel [(const_int 7)
497 [(set_attr "itanium_class" "mmshf")])
499 (define_insn "*mux1_mix"
500 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
502 (match_operand:V8QI 1 "gr_register_operand" "r")
503 (parallel [(const_int 0)
513 [(set_attr "itanium_class" "mmshf")])
515 (define_insn "*mux1_shuf"
516 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
518 (match_operand:V8QI 1 "gr_register_operand" "r")
519 (parallel [(const_int 0)
528 "mux1 %0 = %1, @shuf"
529 [(set_attr "itanium_class" "mmshf")])
531 (define_insn "*mux1_alt"
532 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
534 (match_operand:V8QI 1 "gr_register_operand" "r")
535 (parallel [(const_int 0)
545 [(set_attr "itanium_class" "mmshf")])
547 (define_insn "*mux1_brcst_v8qi"
548 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
550 (match_operand:V8QI 1 "gr_register_operand" "r")
551 (parallel [(const_int 0)
560 "mux1 %0 = %1, @brcst"
561 [(set_attr "itanium_class" "mmshf")])
563 (define_insn "*mux1_brcst_qi"
564 [(set (match_operand:V8QI 0 "gr_register_operand" "=r")
566 (match_operand:QI 1 "gr_register_operand" "r")))]
568 "mux1 %0 = %1, @brcst"
569 [(set_attr "itanium_class" "mmshf")])
571 (define_insn "unpack2_l"
572 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
575 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
576 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
577 (parallel [(const_int 0)
582 "unpack2.l %0 = %r2, %r1"
583 [(set_attr "itanium_class" "mmshf")])
585 (define_insn "unpack2_h"
586 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
589 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
590 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
591 (parallel [(const_int 2)
596 "unpack2.h %0 = %r2, %r1"
597 [(set_attr "itanium_class" "mmshf")])
599 (define_insn "*mix2_r"
600 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
603 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
604 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
605 (parallel [(const_int 0)
610 "mix2.r %0 = %r2, %r1"
611 [(set_attr "itanium_class" "mmshf")])
613 (define_insn "*mix2_l"
614 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
617 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")
618 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))
619 (parallel [(const_int 1)
624 "mix2.l %0 = %r2, %r1"
625 [(set_attr "itanium_class" "mmshf")])
628 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
630 (match_operand:V4HI 1 "gr_register_operand" "r")
631 (parallel [(match_operand 2 "const_int_2bit_operand" "")
632 (match_operand 3 "const_int_2bit_operand" "")
633 (match_operand 4 "const_int_2bit_operand" "")
634 (match_operand 5 "const_int_2bit_operand" "")])))]
638 mask = INTVAL (operands[2]);
639 mask |= INTVAL (operands[3]) << 2;
640 mask |= INTVAL (operands[4]) << 4;
641 mask |= INTVAL (operands[5]) << 6;
642 operands[2] = GEN_INT (mask);
643 return "%,mux2 %0 = %1, %2";
645 [(set_attr "itanium_class" "mmshf")])
647 (define_insn "*mux2_brcst_hi"
648 [(set (match_operand:V4HI 0 "gr_register_operand" "=r")
650 (match_operand:HI 1 "gr_register_operand" "r")))]
653 [(set_attr "itanium_class" "mmshf")])
655 ;; Note that mix4.r performs the exact same operation.
656 (define_insn "*unpack4_l"
657 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
660 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
661 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
662 (parallel [(const_int 0)
665 "unpack4.l %0 = %r2, %r1"
666 [(set_attr "itanium_class" "mmshf")])
668 ;; Note that mix4.l performs the exact same operation.
669 (define_insn "*unpack4_h"
670 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
673 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")
674 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))
675 (parallel [(const_int 1)
678 "unpack4.h %0 = %r2, %r1"
679 [(set_attr "itanium_class" "mmshf")])
681 (define_expand "vec_initv2si"
682 [(match_operand:V2SF 0 "gr_register_operand" "")
683 (match_operand 1 "" "")]
686 rtx op1 = XVECEXP (operands[1], 0, 0);
687 rtx op2 = XVECEXP (operands[1], 0, 1);
690 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
692 x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0));
693 emit_move_insn (operands[0], x);
697 if (!gr_reg_or_0_operand (op1, SImode))
698 op1 = force_reg (SImode, op1);
699 if (!gr_reg_or_0_operand (op2, SImode))
700 op2 = force_reg (SImode, op2);
702 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2);
703 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
707 (define_insn "*vecinit_v2si"
708 [(set (match_operand:V2SI 0 "gr_register_operand" "=r")
710 (match_operand:SI 1 "gr_reg_or_0_operand" "rO")
711 (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))]
713 "unpack4.l %0 = %r2, %r1"
714 [(set_attr "itanium_class" "mmshf")])
716 ;; Missing operations
721 ;; pmpyshr, general form
730 ;; Floating point vector operations
732 (define_expand "movv2sf"
733 [(set (match_operand:V2SF 0 "general_operand" "")
734 (match_operand:V2SF 1 "general_operand" ""))]
737 rtx op1 = ia64_expand_move (operands[0], operands[1]);
743 (define_insn "*movv2sf_internal"
744 [(set (match_operand:V2SF 0 "destination_operand"
745 "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r")
746 (match_operand:V2SF 1 "move_operand"
747 "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))]
748 "ia64_move_ok (operands[0], operands[1])"
750 static const char * const alt[] = {
752 "%,fpack %0 = %F2, %F1",
756 "%,addl %0 = %v1, r0",
758 "%,ld8%O1 %0 = %1%P1",
759 "%,st8%Q0 %0 = %r1%P0",
760 "%,setf.sig %0 = %1",
764 if (which_alternative == 1)
766 operands[2] = XVECEXP (operands[1], 0, 1);
767 operands[1] = XVECEXP (operands[1], 0, 0);
770 return alt[which_alternative];
772 [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")])
774 (define_insn "absv2sf2"
775 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
776 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
779 [(set_attr "itanium_class" "fmisc")])
781 (define_insn "negv2sf2"
782 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
783 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))]
786 [(set_attr "itanium_class" "fmisc")])
788 (define_insn "*negabsv2sf2"
789 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
791 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))]
794 [(set_attr "itanium_class" "fmisc")])
796 ;; In order to convince combine to merge plus and mult to a useful fpma,
797 ;; we need a couple of extra patterns.
798 (define_expand "addv2sf3"
800 [(set (match_operand:V2SF 0 "fr_register_operand" "")
801 (plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
802 (match_operand:V2SF 2 "fr_register_operand" "")))
803 (use (match_dup 3))])]
806 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
807 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
810 ;; The split condition here could be combine_completed, if we had such.
811 (define_insn_and_split "*addv2sf3_1"
812 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
813 (plus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
814 (match_operand:V2SF 2 "fr_register_operand" "f")))
815 (use (match_operand:V2SF 3 "fr_register_operand" "f"))]
821 (mult:V2SF (match_dup 1) (match_dup 3))
825 (define_insn_and_split "*addv2sf3_2"
826 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
828 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
829 (match_operand:V2SF 2 "fr_register_operand" "f"))
830 (match_operand:V2SF 3 "fr_register_operand" "f")))
831 (use (match_operand:V2SF 4 "" "X"))]
837 (mult:V2SF (match_dup 1) (match_dup 2))
841 ;; In order to convince combine to merge minus and mult to a useful fpms,
842 ;; we need a couple of extra patterns.
843 (define_expand "subv2sf3"
845 [(set (match_operand:V2SF 0 "fr_register_operand" "")
846 (minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "")
847 (match_operand:V2SF 2 "fr_register_operand" "")))
848 (use (match_dup 3))])]
851 rtvec v = gen_rtvec (2, CONST1_RTX (SFmode), CONST1_RTX (SFmode));
852 operands[3] = force_reg (V2SFmode, gen_rtx_CONST_VECTOR (V2SFmode, v));
855 ;; The split condition here could be combine_completed, if we had such.
856 (define_insn_and_split "*subv2sf3_1"
857 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
858 (minus:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
859 (match_operand:V2SF 2 "fr_register_operand" "f")))
860 (use (match_operand:V2SF 3 "fr_register_operand" "f"))]
866 (mult:V2SF (match_dup 1) (match_dup 3))
870 (define_insn_and_split "*subv2sf3_2"
871 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
873 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
874 (match_operand:V2SF 2 "fr_register_operand" "f"))
875 (match_operand:V2SF 3 "fr_register_operand" "f")))
876 (use (match_operand:V2SF 4 "" "X"))]
882 (mult:V2SF (match_dup 1) (match_dup 2))
886 (define_insn "mulv2sf3"
887 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
888 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
889 (match_operand:V2SF 2 "fr_register_operand" "f")))]
892 [(set_attr "itanium_class" "fmac")])
895 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
897 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
898 (match_operand:V2SF 2 "fr_register_operand" "f"))
899 (match_operand:V2SF 3 "fr_register_operand" "f")))]
901 "fpma %0 = %1, %2, %3"
902 [(set_attr "itanium_class" "fmac")])
905 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
907 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
908 (match_operand:V2SF 2 "fr_register_operand" "f"))
909 (match_operand:V2SF 3 "fr_register_operand" "f")))]
911 "fpms %0 = %1, %2, %3"
912 [(set_attr "itanium_class" "fmac")])
914 (define_insn "*fpnmpy"
915 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
917 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
918 (match_operand:V2SF 2 "fr_register_operand" "f"))))]
921 [(set_attr "itanium_class" "fmac")])
923 (define_insn "*fpnma"
924 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
927 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
928 (match_operand:V2SF 2 "fr_register_operand" "f")))
929 (match_operand:V2SF 3 "fr_register_operand" "f")))]
931 "fpnma %0 = %1, %2, %3"
932 [(set_attr "itanium_class" "fmac")])
934 (define_insn "smaxv2sf3"
935 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
936 (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
937 (match_operand:V2SF 2 "fr_register_operand" "f")))]
940 [(set_attr "itanium_class" "fmisc")])
942 (define_insn "sminv2sf3"
943 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
944 (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")
945 (match_operand:V2SF 2 "fr_register_operand" "f")))]
948 [(set_attr "itanium_class" "fmisc")])
950 (define_expand "reduc_plus_v2sf"
951 [(match_operand:V2SF 0 "fr_register_operand" "")
952 (match_operand:V2SF 1 "fr_register_operand" "")]
955 rtx tmp = gen_reg_rtx (V2SFmode);
956 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
957 emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp));
961 (define_expand "reduc_smax_v2sf"
962 [(match_operand:V2SF 0 "fr_register_operand" "")
963 (match_operand:V2SF 1 "fr_register_operand" "")]
966 rtx tmp = gen_reg_rtx (V2SFmode);
967 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
968 emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp));
972 (define_expand "reduc_smin_v2sf"
973 [(match_operand:V2SF 0 "fr_register_operand" "")
974 (match_operand:V2SF 1 "fr_register_operand" "")]
977 rtx tmp = gen_reg_rtx (V2SFmode);
978 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode)));
979 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp));
983 (define_expand "vcondv2sf"
984 [(set (match_operand:V2SF 0 "fr_register_operand" "")
987 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "")
988 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")])
989 (match_operand:V2SF 1 "fr_reg_or_0_operand" "")
990 (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))]
995 cmp = gen_reg_rtx (V2SFmode);
996 PUT_MODE (operands[3], V2SFmode);
997 emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3]));
999 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
1000 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1004 (define_insn "*fpcmp"
1005 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1006 (match_operator:V2SF 3 "comparison_operator"
1007 [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1008 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))]
1010 "fpcmp.%D3 %0 = %F1, %F2"
1011 [(set_attr "itanium_class" "fmisc")])
1013 (define_insn "*fselect"
1014 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1016 (match_operand:V2SF 1 "fr_register_operand" "f")
1017 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")
1018 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))]
1020 "fselect %0 = %F2, %F3, %1"
1021 [(set_attr "itanium_class" "fmisc")])
1023 (define_expand "vec_initv2sf"
1024 [(match_operand:V2SF 0 "fr_register_operand" "")
1025 (match_operand 1 "" "")]
1028 rtx op1 = XVECEXP (operands[1], 0, 0);
1029 rtx op2 = XVECEXP (operands[1], 0, 1);
1032 if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE)
1034 x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0));
1035 emit_move_insn (operands[0], x);
1039 if (!fr_reg_or_fp01_operand (op1, SFmode))
1040 op1 = force_reg (SFmode, op1);
1041 if (!fr_reg_or_fp01_operand (op2, SFmode))
1042 op2 = force_reg (SFmode, op2);
1044 emit_insn (gen_fpack (operands[0], op1, op2));
1048 (define_insn "fpack"
1049 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1051 (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
1052 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
1054 "fpack %0 = %F2, %F1"
1055 [(set_attr "itanium_class" "fmisc")])
1057 (define_insn "fswap"
1058 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1061 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1062 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1063 (parallel [(const_int 1) (const_int 2)])))]
1065 "fswap %0 = %F1, %F2"
1066 [(set_attr "itanium_class" "fmisc")])
1068 (define_insn "*fmix_l"
1069 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1072 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1073 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1074 (parallel [(const_int 1) (const_int 3)])))]
1076 "fmix.l %0 = %F2, %F1"
1077 [(set_attr "itanium_class" "fmisc")])
1079 (define_insn "fmix_r"
1080 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1083 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1084 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1085 (parallel [(const_int 0) (const_int 2)])))]
1087 "fmix.r %0 = %F2, %F1"
1088 [(set_attr "itanium_class" "fmisc")])
1090 (define_insn "fmix_lr"
1091 [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
1094 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
1095 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU"))
1096 (parallel [(const_int 0) (const_int 3)])))]
1098 "fmix.lr %0 = %F2, %F1"
1099 [(set_attr "itanium_class" "fmisc")])
1101 (define_expand "vec_setv2sf"
1102 [(match_operand:V2SF 0 "fr_register_operand" "")
1103 (match_operand:SF 1 "fr_register_operand" "")
1104 (match_operand 2 "const_int_operand" "")]
1107 rtx tmp = gen_reg_rtx (V2SFmode);
1108 emit_insn (gen_fpack (tmp, operands[1], CONST0_RTX (SFmode)));
1110 switch (INTVAL (operands[2]))
1113 emit_insn (gen_fmix_lr (operands[0], tmp, operands[0]));
1116 emit_insn (gen_fmix_r (operands[0], operands[0], tmp));
1124 (define_insn_and_split "*vec_extractv2sf_0_le"
1125 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m")
1126 (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r")
1129 "!TARGET_BIG_ENDIAN"
1132 [(set (match_dup 0) (match_dup 1))]
1134 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1])))
1135 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1136 else if (MEM_P (operands[1]))
1137 operands[1] = adjust_address (operands[1], SFmode, 0);
1139 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1142 (define_insn_and_split "*vec_extractv2sf_0_be"
1143 [(set (match_operand:SF 0 "register_operand" "=r,f")
1144 (unspec:SF [(match_operand:V2SF 1 "register_operand" "rf,r")
1150 [(set (match_dup 0) (match_dup 1))]
1152 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1])))
1153 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0]));
1155 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1]));
1158 (define_insn_and_split "*vec_extractv2sf_1"
1159 [(set (match_operand:SF 0 "register_operand" "=r")
1160 (unspec:SF [(match_operand:V2SF 1 "register_operand" "r")
1168 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
1169 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
1170 emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32)));
1174 (define_expand "vec_extractv2sf"
1175 [(set (match_operand:SF 0 "register_operand" "")
1176 (unspec:SF [(match_operand:V2SF 1 "register_operand" "")
1177 (match_operand:DI 2 "const_int_operand" "")]
1182 ;; Missing operations