1 ;; GCC machine description for IA-64 synchronization instructions.
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 (define_mode_macro I48MODE [SI DI])
23 (define_mode_attr modesuffix [(SI "4") (DI "8")])
26 (define_expand "memory_barrier"
27 [(set (mem:BLK (match_dup 0))
28 (unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
31 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
32 MEM_VOLATILE_P (operands[0]) = 1;
35 (define_insn "*mf_internal"
36 [(set (match_operand:BLK 0 "" "")
37 (unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
40 [(set_attr "itanium_class" "syst_m")])
42 (define_expand "sync_add<mode>"
43 [(match_operand:I48MODE 0 "gr_register_operand" "")
44 (match_operand:I48MODE 1 "memory_operand" "")
45 (match_operand:I48MODE 2 "general_operand" "")]
48 if (!fetchadd_operand (operands[2], <MODE>mode))
50 emit_insn (gen_memory_barrier ());
51 emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
55 (define_expand "sync_old_add<mode>"
56 [(match_operand:I48MODE 0 "gr_register_operand" "")
57 (match_operand:I48MODE 1 "memory_operand" "")
58 (match_operand:I48MODE 2 "general_operand" "")]
61 if (!fetchadd_operand (operands[2], <MODE>mode))
63 emit_insn (gen_memory_barrier ());
64 emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
68 (define_insn "fetchadd_acq_<mode>"
69 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
70 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
72 (unspec:I48MODE [(match_dup 1)
73 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
74 UNSPEC_FETCHADD_ACQ))]
76 "fetchadd<modesuffix>.acq %0 = %1, %2"
77 [(set_attr "itanium_class" "sem")])
79 (define_expand "sync_compare_and_swap<mode>"
80 [(match_operand:I48MODE 0 "gr_register_operand" "")
81 (match_operand:I48MODE 1 "memory_operand" "")
82 (match_operand:I48MODE 2 "gr_register_operand" "")
83 (match_operand:I48MODE 3 "gr_register_operand" "")]
86 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
87 convert_move (ccv, operands[2], 1);
88 emit_insn (gen_memory_barrier ());
89 emit_insn (gen_cmpxchg_acq_<mode> (operands[0], operands[1],
94 (define_insn "cmpxchg_acq_<mode>"
95 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
96 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
98 (unspec:I48MODE [(match_dup 1)
99 (match_operand:DI 2 "ar_ccv_reg_operand" "")
100 (match_operand:I48MODE 3 "gr_register_operand" "r")]
101 UNSPEC_CMPXCHG_ACQ))]
103 "cmpxchg<modesuffix>.acq %0 = %1, %3, %2"
104 [(set_attr "itanium_class" "sem")])
106 (define_insn "sync_lock_test_and_set<mode>"
107 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
108 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
110 (match_operand:I48MODE 2 "gr_register_operand" "r"))]
112 "xchg<modesuffix> %0 = %1, %2"
113 [(set_attr "itanium_class" "sem")])
115 (define_expand "sync_lock_release<mode>"
116 [(set (match_operand:I48MODE 0 "memory_operand" "")
117 (match_operand:I48MODE 1 "gr_reg_or_0_operand" ""))]
120 gcc_assert (MEM_VOLATILE_P (operands[0]));