1 ;; GCC machine description for IA-64 synchronization instructions.
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 (define_mode_macro IMODE [QI HI SI DI])
23 (define_mode_macro I48MODE [SI DI])
24 (define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
27 (define_insn "memory_barrier"
28 [(set (mem:BLK (match_scratch:DI 0 "X"))
29 (unspec:BLK [(mem:BLK (match_scratch:DI 1 "X"))] UNSPEC_MF))]
32 [(set_attr "itanium_class" "syst_m")])
34 (define_expand "sync_add<mode>"
35 [(match_operand:I48MODE 0 "gr_register_operand" "")
36 (match_operand:I48MODE 1 "memory_operand" "")
37 (match_operand:I48MODE 2 "general_operand" "")]
40 if (!fetchadd_operand (operands[2], <MODE>mode))
42 emit_insn (gen_memory_barrier ());
43 emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
47 (define_expand "sync_old_add<mode>"
48 [(match_operand:I48MODE 0 "gr_register_operand" "")
49 (match_operand:I48MODE 1 "memory_operand" "")
50 (match_operand:I48MODE 2 "general_operand" "")]
53 if (!fetchadd_operand (operands[2], <MODE>mode))
55 emit_insn (gen_memory_barrier ());
56 emit_insn (gen_fetchadd_acq_<mode> (operands[0], operands[1], operands[2]));
60 (define_insn "fetchadd_acq_<mode>"
61 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
62 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
64 (unspec:I48MODE [(match_dup 1)
65 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
66 UNSPEC_FETCHADD_ACQ))]
68 "fetchadd<modesuffix>.acq %0 = %1, %2"
69 [(set_attr "itanium_class" "sem")])
71 (define_expand "sync_compare_and_swap<mode>"
72 [(match_operand:IMODE 0 "gr_register_operand" "")
73 (match_operand:IMODE 1 "memory_operand" "")
74 (match_operand:IMODE 2 "gr_register_operand" "")
75 (match_operand:IMODE 3 "gr_register_operand" "")]
78 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
79 convert_move (ccv, operands[2], 1);
80 emit_insn (gen_memory_barrier ());
81 emit_insn (gen_cmpxchg_acq_<mode> (operands[0], operands[1],
86 (define_insn "cmpxchg_acq_<mode>"
87 [(set (match_operand:IMODE 0 "gr_register_operand" "=r")
88 (match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
90 (unspec:IMODE [(match_dup 1)
91 (match_operand:DI 2 "ar_ccv_reg_operand" "")
92 (match_operand:IMODE 3 "gr_register_operand" "r")]
95 "cmpxchg<modesuffix>.acq %0 = %1, %3, %2"
96 [(set_attr "itanium_class" "sem")])
98 (define_insn "sync_lock_test_and_set<mode>"
99 [(set (match_operand:IMODE 0 "gr_register_operand" "=r")
100 (match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
102 (match_operand:IMODE 2 "gr_register_operand" "r"))]
104 "xchg<modesuffix> %0 = %1, %2"
105 [(set_attr "itanium_class" "sem")])
107 (define_expand "sync_lock_release<mode>"
108 [(set (match_operand:IMODE 0 "memory_operand" "")
109 (match_operand:IMODE 1 "gr_reg_or_0_operand" ""))]
112 gcc_assert (MEM_VOLATILE_P (operands[0]));