1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_assert("cpu=ia64"); \
38 builtin_assert("machine=ia64"); \
39 builtin_define("__ia64"); \
40 builtin_define("__ia64__"); \
41 builtin_define("__itanium__"); \
42 builtin_define("__ELF__"); \
45 builtin_define("_LP64"); \
46 builtin_define("__LP64__"); \
48 if (TARGET_BIG_ENDIAN) \
49 builtin_define("__BIG_ENDIAN__"); \
53 { "asm_extra", ASM_EXTRA_SPEC },
55 #define CC1_SPEC "%(cc1_cpu) "
57 #define ASM_EXTRA_SPEC ""
60 /* This declaration should be present. */
61 extern int target_flags;
63 /* This series of macros is to allow compiler command arguments to enable or
64 disable the use of optional features of the target machine. */
66 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
68 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
70 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
72 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
74 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
76 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
78 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
80 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
82 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
84 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
86 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
88 #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
90 #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
92 #define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
94 #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
96 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
98 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
100 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
102 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
104 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
106 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
108 #define TARGET_ILP32 (target_flags & MASK_ILP32)
110 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
112 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
114 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
116 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
118 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
120 #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
122 #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
124 #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
126 #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
128 #define TARGET_INLINE_FLOAT_DIV \
129 (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
131 #define TARGET_INLINE_INT_DIV \
132 (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
134 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
136 extern int ia64_tls_size;
137 #define TARGET_TLS14 (ia64_tls_size == 14)
138 #define TARGET_TLS22 (ia64_tls_size == 22)
139 #define TARGET_TLS64 (ia64_tls_size == 64)
141 #define TARGET_HPUX_LD 0
143 /* This macro defines names of command options to set and clear bits in
144 `target_flags'. Its definition is an initializer with a subgrouping for
145 each command option. */
147 #define TARGET_SWITCHES \
149 { "big-endian", MASK_BIG_ENDIAN, \
150 N_("Generate big endian code") }, \
151 { "little-endian", -MASK_BIG_ENDIAN, \
152 N_("Generate little endian code") }, \
153 { "gnu-as", MASK_GNU_AS, \
154 N_("Generate code for GNU as") }, \
155 { "no-gnu-as", -MASK_GNU_AS, \
156 N_("Generate code for Intel as") }, \
157 { "gnu-ld", MASK_GNU_LD, \
158 N_("Generate code for GNU ld") }, \
159 { "no-gnu-ld", -MASK_GNU_LD, \
160 N_("Generate code for Intel ld") }, \
161 { "no-pic", MASK_NO_PIC, \
162 N_("Generate code without GP reg") }, \
163 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
164 N_("Emit stop bits before and after volatile extended asms") }, \
165 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
166 N_("Don't emit stop bits before and after volatile extended asms") }, \
167 { "b-step", MASK_B_STEP, \
168 N_("Emit code for Itanium (TM) processor B step")}, \
169 { "register-names", MASK_REG_NAMES, \
170 N_("Use in/loc/out register names")}, \
171 { "no-sdata", MASK_NO_SDATA, \
172 N_("Disable use of sdata/scommon/sbss")}, \
173 { "sdata", -MASK_NO_SDATA, \
174 N_("Enable use of sdata/scommon/sbss")}, \
175 { "constant-gp", MASK_CONST_GP, \
176 N_("gp is constant (but save/restore gp on indirect calls)") }, \
177 { "auto-pic", MASK_AUTO_PIC, \
178 N_("Generate self-relocatable code") }, \
179 { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
180 N_("Generate inline floating point division, optimize for latency") },\
181 { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
182 N_("Generate inline floating point division, optimize for throughput") },\
183 { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
184 N_("Generate inline integer division, optimize for latency") }, \
185 { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
186 N_("Generate inline integer division, optimize for throughput") },\
187 { "dwarf2-asm", MASK_DWARF2_ASM, \
188 N_("Enable Dwarf 2 line debug info via GNU as")}, \
189 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
190 N_("Disable Dwarf 2 line debug info via GNU as")}, \
192 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
196 /* Default target_flags if no switches are specified */
198 #ifndef TARGET_DEFAULT
199 #define TARGET_DEFAULT MASK_DWARF2_ASM
202 #ifndef TARGET_CPU_DEFAULT
203 #define TARGET_CPU_DEFAULT 0
206 #ifndef SUBTARGET_SWITCHES
207 #define SUBTARGET_SWITCHES
210 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
211 options that have values. Its definition is an initializer with a
212 subgrouping for each command option. */
214 extern const char *ia64_fixed_range_string;
215 extern const char *ia64_tls_size_string;
216 #define TARGET_OPTIONS \
218 { "fixed-range=", &ia64_fixed_range_string, \
219 N_("Specify range of registers to make fixed")}, \
220 { "tls-size=", &ia64_tls_size_string, \
221 N_("Specify bit size of immediate TLS offsets")}, \
224 /* Sometimes certain combinations of command options do not make sense on a
225 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
226 take account of this. This macro, if defined, is executed once just after
227 all the command options have been parsed. */
229 #define OVERRIDE_OPTIONS ia64_override_options ()
231 /* Some machines may desire to change what optimizations are performed for
232 various optimization levels. This macro, if defined, is executed once just
233 after the optimization level is determined and before the remainder of the
234 command options have been parsed. Values set in this macro are used as the
235 default values for the other command line options. */
237 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
239 /* Driver configuration */
241 /* A C string constant that tells the GNU CC driver program options to pass to
242 `cc1'. It can also specify how to translate options you give to GNU CC into
243 options for GNU CC to pass to the `cc1'. */
246 #define CC1_SPEC "%{G*}"
248 /* A C string constant that tells the GNU CC driver program options to pass to
249 `cc1plus'. It can also specify how to translate options you give to GNU CC
250 into options for GNU CC to pass to the `cc1plus'. */
252 /* #define CC1PLUS_SPEC "" */
256 /* Define this macro to have the value 1 if the most significant bit in a byte
257 has the lowest number; otherwise define it to have the value zero. */
259 #define BITS_BIG_ENDIAN 0
261 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
263 /* Define this macro to have the value 1 if, in a multiword object, the most
264 significant word has the lowest number. */
266 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
268 #if defined(__BIG_ENDIAN__)
269 #define LIBGCC2_WORDS_BIG_ENDIAN 1
271 #define LIBGCC2_WORDS_BIG_ENDIAN 0
274 #define UNITS_PER_WORD 8
276 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
278 /* A C expression whose value is zero if pointers that need to be extended
279 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
280 they are zero-extended and negative one if there is a ptr_extend operation.
282 You need not define this macro if the `POINTER_SIZE' is equal to the width
284 /* Need this for 32 bit pointers, see hpux.h for setting it. */
285 /* #define POINTERS_EXTEND_UNSIGNED */
287 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
288 which has the specified mode and signedness is to be stored in a register.
289 This macro is only called when TYPE is a scalar type. */
290 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
293 if (GET_MODE_CLASS (MODE) == MODE_INT \
294 && GET_MODE_SIZE (MODE) < 4) \
299 /* ??? ABI doesn't allow us to define this. */
300 /* #define PROMOTE_FUNCTION_ARGS */
302 /* ??? ABI doesn't allow us to define this. */
303 /* #define PROMOTE_FUNCTION_RETURN */
305 #define PARM_BOUNDARY 64
307 /* Define this macro if you wish to preserve a certain alignment for the stack
308 pointer. The definition is a C expression for the desired alignment
309 (measured in bits). */
311 #define STACK_BOUNDARY 128
313 /* Align frames on double word boundaries */
314 #ifndef IA64_STACK_ALIGN
315 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
318 #define FUNCTION_BOUNDARY 128
320 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
321 128 bit integers all require 128 bit alignment. */
322 #define BIGGEST_ALIGNMENT 128
324 /* If defined, a C expression to compute the alignment for a static variable.
325 TYPE is the data type, and ALIGN is the alignment that the object
326 would ordinarily have. The value of this macro is used instead of that
327 alignment to align the object. */
329 #define DATA_ALIGNMENT(TYPE, ALIGN) \
330 (TREE_CODE (TYPE) == ARRAY_TYPE \
331 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
332 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
334 /* If defined, a C expression to compute the alignment given to a constant that
335 is being placed in memory. CONSTANT is the constant and ALIGN is the
336 alignment that the object would ordinarily have. The value of this macro is
337 used instead of that alignment to align the object. */
339 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
340 (TREE_CODE (EXP) == STRING_CST \
341 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
343 #define STRICT_ALIGNMENT 1
345 /* Define this if you wish to imitate the way many other C compilers handle
346 alignment of bitfields and the structures that contain them.
347 The behavior is that the type written for a bit-field (`int', `short', or
348 other integer type) imposes an alignment for the entire structure, as if the
349 structure really did contain an ordinary field of that type. In addition,
350 the bit-field is placed within the structure so that it would fit within such
351 a field, not crossing a boundary for it. */
352 #define PCC_BITFIELD_TYPE_MATTERS 1
354 /* An integer expression for the size in bits of the largest integer machine
355 mode that should actually be used. */
357 /* Allow pairs of registers to be used, which is the intent of the default. */
358 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
360 /* By default, the C++ compiler will use function addresses in the
361 vtable entries. Setting this nonzero tells the compiler to use
362 function descriptors instead. The value of this macro says how
363 many words wide the descriptor is (normally 2). It is assumed
364 that the address of a function descriptor may be treated as a
365 pointer to a function.
367 For reasons known only to HP, the vtable entries (as opposed to
368 normal function descriptors) are 16 bytes wide in 32-bit mode as
369 well, even though the 3rd and 4th words are unused. */
370 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
372 /* Due to silliness in the HPUX linker, vtable entries must be
373 8-byte aligned even in 32-bit mode. Rather than create multiple
374 ABIs, force this restriction on everyone else too. */
375 #define TARGET_VTABLE_ENTRY_ALIGN 64
377 /* Due to the above, we need extra padding for the data entries below 0
378 to retain the alignment of the descriptors. */
379 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
381 /* Layout of Source Language Data Types */
383 #define INT_TYPE_SIZE 32
385 #define SHORT_TYPE_SIZE 16
387 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
389 #define MAX_LONG_TYPE_SIZE 64
391 #define LONG_LONG_TYPE_SIZE 64
393 #define FLOAT_TYPE_SIZE 32
395 #define DOUBLE_TYPE_SIZE 64
397 #define LONG_DOUBLE_TYPE_SIZE 128
399 /* By default we use the 80-bit Intel extended float format packaged
400 in a 128-bit entity. */
401 #define INTEL_EXTENDED_IEEE_FORMAT 1
403 #define DEFAULT_SIGNED_CHAR 1
405 /* A C expression for a string describing the name of the data type to use for
406 size values. The typedef name `size_t' is defined using the contents of the
408 /* ??? Needs to be defined for P64 code. */
409 /* #define SIZE_TYPE */
411 /* A C expression for a string describing the name of the data type to use for
412 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
413 defined using the contents of the string. See `SIZE_TYPE' above for more
415 /* ??? Needs to be defined for P64 code. */
416 /* #define PTRDIFF_TYPE */
418 /* A C expression for a string describing the name of the data type to use for
419 wide characters. The typedef name `wchar_t' is defined using the contents
420 of the string. See `SIZE_TYPE' above for more information. */
421 /* #define WCHAR_TYPE */
423 /* A C expression for the size in bits of the data type for wide characters.
424 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
425 /* #define WCHAR_TYPE_SIZE */
428 /* Register Basics */
430 /* Number of hardware registers known to the compiler.
431 We have 128 general registers, 128 floating point registers,
432 64 predicate registers, 8 branch registers, one frame pointer,
433 and several "application" registers. */
435 #define FIRST_PSEUDO_REGISTER 335
437 /* Ranges for the various kinds of registers. */
438 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
439 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
440 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
441 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
442 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
443 #define GENERAL_REGNO_P(REGNO) \
444 (GR_REGNO_P (REGNO) \
445 || (REGNO) == FRAME_POINTER_REGNUM \
446 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
448 #define GR_REG(REGNO) ((REGNO) + 0)
449 #define FR_REG(REGNO) ((REGNO) + 128)
450 #define PR_REG(REGNO) ((REGNO) + 256)
451 #define BR_REG(REGNO) ((REGNO) + 320)
452 #define OUT_REG(REGNO) ((REGNO) + 120)
453 #define IN_REG(REGNO) ((REGNO) + 112)
454 #define LOC_REG(REGNO) ((REGNO) + 32)
456 #define AR_CCV_REGNUM 330
457 #define AR_UNAT_REGNUM 331
458 #define AR_PFS_REGNUM 332
459 #define AR_LC_REGNUM 333
460 #define AR_EC_REGNUM 334
462 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
463 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
464 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
466 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
467 || (REGNO) == AR_UNAT_REGNUM)
468 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
469 && (REGNO) < FIRST_PSEUDO_REGISTER)
470 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
471 && (REGNO) < FIRST_PSEUDO_REGISTER)
474 /* ??? Don't really need two sets of macros. I like this one better because
475 it is less typing. */
476 #define R_GR(REGNO) GR_REG (REGNO)
477 #define R_FR(REGNO) FR_REG (REGNO)
478 #define R_PR(REGNO) PR_REG (REGNO)
479 #define R_BR(REGNO) BR_REG (REGNO)
481 /* An initializer that says which registers are used for fixed purposes all
482 throughout the compiled code and are therefore not available for general
486 r1: global pointer (gp)
487 r12: stack pointer (sp)
488 r13: thread pointer (tp)
492 fp: eliminable frame pointer */
494 /* The last 16 stacked regs are reserved for the 8 input and 8 output
497 #define FIXED_REGISTERS \
498 { /* General registers. */ \
499 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
500 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
503 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
505 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
506 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
507 /* Floating-point registers. */ \
508 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
516 /* Predicate registers. */ \
517 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
521 /* Branch registers. */ \
522 0, 0, 0, 0, 0, 0, 0, 0, \
523 /*FP RA CCV UNAT PFS LC EC */ \
524 1, 1, 1, 1, 1, 0, 1 \
527 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
528 (in general) by function calls as well as for fixed registers. This
529 macro therefore identifies the registers that are not available for
530 general allocation of values that must live across function calls. */
532 #define CALL_USED_REGISTERS \
533 { /* General registers. */ \
534 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
536 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
537 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
541 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
542 /* Floating-point registers. */ \
543 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
547 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
551 /* Predicate registers. */ \
552 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 /* Branch registers. */ \
557 1, 0, 0, 0, 0, 0, 1, 1, \
558 /*FP RA CCV UNAT PFS LC EC */ \
559 1, 1, 1, 1, 1, 0, 1 \
562 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
563 problem which makes CALL_USED_REGISTERS *always* include
564 all the FIXED_REGISTERS. Until this problem has been
565 resolved this macro can be used to overcome this situation.
566 In particular, block_propagate() requires this list
567 be acurate, or we can remove registers which should be live.
568 This macro is used in regs_invalidated_by_call. */
570 #define CALL_REALLY_USED_REGISTERS \
571 { /* General registers. */ \
572 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
579 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
580 /* Floating-point registers. */ \
581 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
586 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
589 /* Predicate registers. */ \
590 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
594 /* Branch registers. */ \
595 1, 0, 0, 0, 0, 0, 1, 1, \
596 /*FP RA CCV UNAT PFS LC EC */ \
597 0, 0, 1, 0, 1, 0, 0 \
601 /* Define this macro if the target machine has register windows. This C
602 expression returns the register number as seen by the called function
603 corresponding to the register number OUT as seen by the calling function.
604 Return OUT if register number OUT is not an outbound register. */
606 #define INCOMING_REGNO(OUT) \
607 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
609 /* Define this macro if the target machine has register windows. This C
610 expression returns the register number as seen by the calling function
611 corresponding to the register number IN as seen by the called function.
612 Return IN if register number IN is not an inbound register. */
614 #define OUTGOING_REGNO(IN) \
615 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
617 /* Define this macro if the target machine has register windows. This
618 C expression returns true if the register is call-saved but is in the
621 #define LOCAL_REGNO(REGNO) \
622 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
624 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
625 return the mode to be used for the comparison. Must be defined if
626 EXTRA_CC_MODES is defined. */
628 #define SELECT_CC_MODE(OP,X,Y) CCmode
630 /* Order of allocation of registers */
632 /* If defined, an initializer for a vector of integers, containing the numbers
633 of hard registers in the order in which GNU CC should prefer to use them
634 (from most preferred to least).
636 If this macro is not defined, registers are used lowest numbered first (all
639 One use of this macro is on machines where the highest numbered registers
640 must always be saved and the save-multiple-registers instruction supports
641 only sequences of consecutive registers. On such machines, define
642 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
643 allocatable register first. */
645 /* ??? Should the GR return value registers come before or after the rest
646 of the caller-save GRs? */
648 #define REG_ALLOC_ORDER \
650 /* Caller-saved general registers. */ \
651 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
652 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
653 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
654 R_GR (30), R_GR (31), \
655 /* Output registers. */ \
656 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
657 R_GR (126), R_GR (127), \
658 /* Caller-saved general registers, also used for return values. */ \
659 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
660 /* addl caller-saved general registers. */ \
661 R_GR (2), R_GR (3), \
662 /* Caller-saved FP registers. */ \
663 R_FR (6), R_FR (7), \
664 /* Caller-saved FP registers, used for parameters and return values. */ \
665 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
666 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
667 /* Rotating caller-saved FP registers. */ \
668 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
669 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
670 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
671 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
672 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
673 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
674 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
675 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
676 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
677 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
678 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
679 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
680 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
681 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
682 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
683 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
684 R_FR (126), R_FR (127), \
685 /* Caller-saved predicate registers. */ \
686 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
687 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
688 /* Rotating caller-saved predicate registers. */ \
689 R_PR (16), R_PR (17), \
690 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
691 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
692 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
693 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
694 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
695 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
696 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
697 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
698 /* Caller-saved branch registers. */ \
699 R_BR (6), R_BR (7), \
701 /* Stacked callee-saved general registers. */ \
702 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
703 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
704 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
705 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
706 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
707 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
708 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
709 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
710 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
711 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
712 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
713 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
714 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
716 /* Input registers. */ \
717 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
718 R_GR (118), R_GR (119), \
719 /* Callee-saved general registers. */ \
720 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
721 /* Callee-saved FP registers. */ \
722 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
723 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
724 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
725 R_FR (30), R_FR (31), \
726 /* Callee-saved predicate registers. */ \
727 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
728 /* Callee-saved branch registers. */ \
729 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
731 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
732 R_GR (109), R_GR (110), R_GR (111), \
734 /* Special general registers. */ \
735 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
736 /* Special FP registers. */ \
737 R_FR (0), R_FR (1), \
738 /* Special predicate registers. */ \
740 /* Special branch registers. */ \
742 /* Other fixed registers. */ \
743 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
744 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
748 /* How Values Fit in Registers */
750 /* A C expression for the number of consecutive hard registers, starting at
751 register number REGNO, required to hold a value of mode MODE. */
753 /* ??? We say that BImode PR values require two registers. This allows us to
754 easily store the normal and inverted values. We use CCImode to indicate
755 a single predicate register. */
757 #define HARD_REGNO_NREGS(REGNO, MODE) \
758 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
759 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
760 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
761 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
762 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
764 /* A C expression that is nonzero if it is permissible to store a value of mode
765 MODE in hard register number REGNO (or in several registers starting with
768 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
769 (FR_REGNO_P (REGNO) ? \
770 GET_MODE_CLASS (MODE) != MODE_CC && \
771 (MODE) != TImode && \
772 (MODE) != BImode && \
773 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
774 : PR_REGNO_P (REGNO) ? \
775 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
776 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
777 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
778 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
781 /* A C expression that is nonzero if it is desirable to choose register
782 allocation so as to avoid move instructions between a value of mode MODE1
783 and a value of mode MODE2.
785 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
786 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
788 /* Don't tie integer and FP modes, as that causes us to get integer registers
789 allocated for FP instructions. TFmode only supported in FP registers so
790 we can't tie it with any other modes. */
791 #define MODES_TIEABLE_P(MODE1, MODE2) \
792 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
793 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
794 && (((MODE1) == BImode) == ((MODE2) == BImode)))
796 /* Handling Leaf Functions */
798 /* A C initializer for a vector, indexed by hard register number, which
799 contains 1 for a register that is allowable in a candidate for leaf function
801 /* ??? This might be useful. */
802 /* #define LEAF_REGISTERS */
804 /* A C expression whose value is the register number to which REGNO should be
805 renumbered, when a function is treated as a leaf function. */
806 /* ??? This might be useful. */
807 /* #define LEAF_REG_REMAP(REGNO) */
810 /* Register Classes */
812 /* An enumeral type that must be defined with all the register class names as
813 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
814 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
815 which is not a register class but rather tells how many classes there
817 /* ??? When compiling without optimization, it is possible for the only use of
818 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
819 Regclass handles this case specially and does not assign any costs to the
820 pseudo. The pseudo then ends up using the last class before ALL_REGS.
821 Thus we must not let either PR_REGS or BR_REGS be the last class. The
822 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
839 #define GENERAL_REGS GR_REGS
841 /* The number of distinct register classes. */
842 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
844 /* An initializer containing the names of the register classes as C string
845 constants. These names are used in writing some of the debugging dumps. */
846 #define REG_CLASS_NAMES \
847 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
848 "ADDL_REGS", "GR_REGS", "FR_REGS", \
849 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
851 /* An initializer containing the contents of the register classes, as integers
852 which are bit masks. The Nth integer specifies the contents of class N.
853 The way the integer MASK is interpreted is that register R is in the class
854 if `MASK & (1 << R)' is 1. */
855 #define REG_CLASS_CONTENTS \
858 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
859 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
860 0x00000000, 0x00000000, 0x0000 }, \
862 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
863 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
864 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
866 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
867 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
868 0x00000000, 0x00000000, 0x00FF }, \
870 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
871 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
872 0x00000000, 0x00000000, 0x0C00 }, \
874 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
875 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
876 0x00000000, 0x00000000, 0x7000 }, \
878 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
879 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
880 0x00000000, 0x00000000, 0x0000 }, \
882 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
883 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
884 0x00000000, 0x00000000, 0x0300 }, \
886 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
887 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
888 0x00000000, 0x00000000, 0x0000 }, \
889 /* GR_AND_BR_REGS. */ \
890 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
891 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
892 0x00000000, 0x00000000, 0x03FF }, \
893 /* GR_AND_FR_REGS. */ \
894 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
895 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
896 0x00000000, 0x00000000, 0x0300 }, \
898 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
899 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
900 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
903 /* A C expression whose value is a register class containing hard register
904 REGNO. In general there is more than one such class; choose a class which
905 is "minimal", meaning that no smaller class also contains the register. */
906 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
907 may call here with private (invalid) register numbers, such as
909 #define REGNO_REG_CLASS(REGNO) \
910 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
911 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
912 : FR_REGNO_P (REGNO) ? FR_REGS \
913 : PR_REGNO_P (REGNO) ? PR_REGS \
914 : BR_REGNO_P (REGNO) ? BR_REGS \
915 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
916 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
919 /* A macro whose definition is the name of the class to which a valid base
920 register must belong. A base register is one used in an address which is
921 the register value plus a displacement. */
922 #define BASE_REG_CLASS GENERAL_REGS
924 /* A macro whose definition is the name of the class to which a valid index
925 register must belong. An index register is one used in an address where its
926 value is either multiplied by a scale factor or added to another register
927 (as well as added to a displacement). This is needed for POST_MODIFY. */
928 #define INDEX_REG_CLASS GENERAL_REGS
930 /* A C expression which defines the machine-dependent operand constraint
931 letters for register classes. If CHAR is such a letter, the value should be
932 the register class corresponding to it. Otherwise, the value should be
933 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
934 will not be passed to this macro; you do not need to handle it. */
936 #define REG_CLASS_FROM_LETTER(CHAR) \
937 ((CHAR) == 'f' ? FR_REGS \
938 : (CHAR) == 'a' ? ADDL_REGS \
939 : (CHAR) == 'b' ? BR_REGS \
940 : (CHAR) == 'c' ? PR_REGS \
941 : (CHAR) == 'd' ? AR_M_REGS \
942 : (CHAR) == 'e' ? AR_I_REGS \
945 /* A C expression which is nonzero if register number NUM is suitable for use
946 as a base register in operand addresses. It may be either a suitable hard
947 register or a pseudo register that has been allocated such a hard reg. */
948 #define REGNO_OK_FOR_BASE_P(REGNO) \
949 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
951 /* A C expression which is nonzero if register number NUM is suitable for use
952 as an index register in operand addresses. It may be either a suitable hard
953 register or a pseudo register that has been allocated such a hard reg.
954 This is needed for POST_MODIFY. */
955 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
957 /* A C expression that places additional restrictions on the register class to
958 use when it is necessary to copy value X into a register in class CLASS.
959 The value is a register class; perhaps CLASS, or perhaps another, smaller
962 /* Don't allow volatile mem reloads into floating point registers. This
963 is defined to force reload to choose the r/m case instead of the f/f case
964 when reloading (set (reg fX) (mem/v)).
966 Do not reload expressions into AR regs. */
968 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
969 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
970 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
971 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
972 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
975 /* You should define this macro to indicate to the reload phase that it may
976 need to allocate at least one register for a reload in addition to the
977 register to contain the data. Specifically, if copying X to a register
978 CLASS in MODE requires an intermediate register, you should define this
979 to return the largest register class all of whose registers can be used
980 as intermediate registers or scratch registers. */
982 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
983 ia64_secondary_reload_class (CLASS, MODE, X)
985 /* Certain machines have the property that some registers cannot be copied to
986 some other registers without using memory. Define this macro on those
987 machines to be a C expression that is nonzero if objects of mode M in
988 registers of CLASS1 can only be copied to registers of class CLASS2 by
989 storing a register of CLASS1 into memory and loading that memory location
990 into a register of CLASS2. */
993 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
994 I'm not quite sure how it could be invoked. The normal problems
995 with unions should be solved with the addressof fiddling done by
996 movtf and friends. */
997 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
998 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
999 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1002 /* A C expression for the maximum number of consecutive registers of
1003 class CLASS needed to hold a value of mode MODE.
1004 This is closely related to the macro `HARD_REGNO_NREGS'. */
1006 #define CLASS_MAX_NREGS(CLASS, MODE) \
1007 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1008 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
1009 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1011 /* In FP regs, we can't change FP values to integer values and vice
1012 versa, but we can change e.g. DImode to SImode. */
1014 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
1015 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) ? FR_REGS : NO_REGS)
1017 /* A C expression that defines the machine-dependent operand constraint
1018 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1021 /* 14 bit signed immediate for arithmetic instructions. */
1022 #define CONST_OK_FOR_I(VALUE) \
1023 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1024 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1025 #define CONST_OK_FOR_J(VALUE) \
1026 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1027 /* 8 bit signed immediate for logical instructions. */
1028 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1029 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1030 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1031 /* 6 bit unsigned immediate for shift counts. */
1032 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1033 /* 9 bit signed immediate for load/store post-increments. */
1034 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1035 /* 0 for r0. Used by Linux kernel, do not change. */
1036 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1037 /* 0 or -1 for dep instruction. */
1038 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1040 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1041 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1042 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1043 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1044 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1045 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1046 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1047 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1048 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1051 /* A C expression that defines the machine-dependent operand constraint letters
1052 (`G', `H') that specify particular ranges of `const_double' values. */
1054 /* 0.0 and 1.0 for fr0 and fr1. */
1055 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1056 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1057 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1059 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1060 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1062 /* A C expression that defines the optional machine-dependent constraint
1063 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1064 types of operands, usually memory references, for the target machine. */
1066 /* Non-volatile memory for FP_REG loads/stores. */
1067 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1068 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1069 /* 1..4 for shladd arguments. */
1070 #define CONSTRAINT_OK_FOR_R(VALUE) \
1071 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1072 /* Non-post-inc memory for asms and other unsavory creatures. */
1073 #define CONSTRAINT_OK_FOR_S(VALUE) \
1074 (GET_CODE (VALUE) == MEM \
1075 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1076 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1078 #define EXTRA_CONSTRAINT(VALUE, C) \
1079 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1080 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1081 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1084 /* Basic Stack Layout */
1086 /* Define this macro if pushing a word onto the stack moves the stack pointer
1087 to a smaller address. */
1088 #define STACK_GROWS_DOWNWARD 1
1090 /* Define this macro if the addresses of local variable slots are at negative
1091 offsets from the frame pointer. */
1092 /* #define FRAME_GROWS_DOWNWARD */
1094 /* Offset from the frame pointer to the first local variable slot to
1096 #define STARTING_FRAME_OFFSET 0
1098 /* Offset from the stack pointer register to the first location at which
1099 outgoing arguments are placed. If not specified, the default value of zero
1100 is used. This is the proper value for most machines. */
1101 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1102 #define STACK_POINTER_OFFSET 16
1104 /* Offset from the argument pointer register to the first argument's address.
1105 On some machines it may depend on the data type of the function. */
1106 #define FIRST_PARM_OFFSET(FUNDECL) 0
1108 /* A C expression whose value is RTL representing the value of the return
1109 address for the frame COUNT steps up from the current frame, after the
1112 /* ??? Frames other than zero would likely require interpreting the frame
1113 unwind info, so we don't try to support them. We would also need to define
1114 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1116 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1117 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1119 /* A C expression whose value is RTL representing the location of the incoming
1120 return address at the beginning of any function, before the prologue. This
1121 RTL is either a `REG', indicating that the return value is saved in `REG',
1122 or a `MEM' representing a location in the stack. This enables DWARF2
1123 unwind info for C++ EH. */
1124 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1126 /* ??? This is not defined because of three problems.
1127 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1128 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1129 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1130 unused register number.
1131 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1132 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1133 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1134 to zero, despite what the documentation implies, because it is tested in
1135 a few places with #ifdef instead of #if. */
1136 #undef INCOMING_RETURN_ADDR_RTX
1138 /* A C expression whose value is an integer giving the offset, in bytes, from
1139 the value of the stack pointer register to the top of the stack frame at the
1140 beginning of any function, before the prologue. The top of the frame is
1141 defined to be the value of the stack pointer in the previous frame, just
1142 before the call instruction. */
1143 #define INCOMING_FRAME_SP_OFFSET 0
1146 /* Register That Address the Stack Frame. */
1148 /* The register number of the stack pointer register, which must also be a
1149 fixed register according to `FIXED_REGISTERS'. On most machines, the
1150 hardware determines which register this is. */
1152 #define STACK_POINTER_REGNUM 12
1154 /* The register number of the frame pointer register, which is used to access
1155 automatic variables in the stack frame. On some machines, the hardware
1156 determines which register this is. On other machines, you can choose any
1157 register you wish for this purpose. */
1159 #define FRAME_POINTER_REGNUM 328
1161 /* Base register for access to local variables of the function. */
1162 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1164 /* The register number of the arg pointer register, which is used to access the
1165 function's argument list. */
1166 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1168 #define ARG_POINTER_REGNUM R_GR(0)
1170 /* Due to the way varargs and argument spilling happens, the argument
1171 pointer is not 16-byte aligned like the stack pointer. */
1172 #define INIT_EXPANDERS \
1174 if (cfun && cfun->emit->regno_pointer_align) \
1175 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1178 /* The register number for the return address register. For IA-64, this
1179 is not actually a pointer as the name suggests, but that's a name that
1180 gen_rtx_REG already takes care to keep unique. We modify
1181 return_address_pointer_rtx in ia64_expand_prologue to reference the
1182 final output regnum. */
1183 #define RETURN_ADDRESS_POINTER_REGNUM 329
1185 /* Register numbers used for passing a function's static chain pointer. */
1186 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1187 #define STATIC_CHAIN_REGNUM 15
1189 /* Eliminating the Frame Pointer and the Arg Pointer */
1191 /* A C expression which is nonzero if a function must have and use a frame
1192 pointer. This expression is evaluated in the reload pass. If its value is
1193 nonzero the function will have a frame pointer. */
1194 #define FRAME_POINTER_REQUIRED 0
1196 /* Show we can debug even without a frame pointer. */
1197 #define CAN_DEBUG_WITHOUT_FP
1199 /* If defined, this macro specifies a table of register pairs used to eliminate
1200 unneeded registers that point into the stack frame. */
1202 #define ELIMINABLE_REGS \
1204 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1205 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1206 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1207 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1208 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1211 /* A C expression that returns nonzero if the compiler is allowed to try to
1212 replace register number FROM with register number TO. The frame pointer
1213 is automatically handled. */
1215 #define CAN_ELIMINATE(FROM, TO) \
1216 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1218 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1219 specifies the initial difference between the specified pair of
1220 registers. This macro must be defined if `ELIMINABLE_REGS' is
1222 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1223 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1225 /* Passing Function Arguments on the Stack */
1227 /* Define this macro if an argument declared in a prototype as an integral type
1228 smaller than `int' should actually be passed as an `int'. In addition to
1229 avoiding errors in certain cases of mismatch, it also makes for better code
1230 on certain machines. */
1231 /* ??? Investigate. */
1232 /* #define PROMOTE_PROTOTYPES */
1234 /* If defined, the maximum amount of space required for outgoing arguments will
1235 be computed and placed into the variable
1236 `current_function_outgoing_args_size'. */
1238 #define ACCUMULATE_OUTGOING_ARGS 1
1240 /* A C expression that should indicate the number of bytes of its own arguments
1241 that a function pops on returning, or 0 if the function pops no arguments
1242 and the caller must therefore pop them all after the function returns. */
1244 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1247 /* Function Arguments in Registers */
1249 #define MAX_ARGUMENT_SLOTS 8
1250 #define MAX_INT_RETURN_SLOTS 4
1251 #define GR_ARG_FIRST IN_REG (0)
1252 #define GR_RET_FIRST GR_REG (8)
1253 #define GR_RET_LAST GR_REG (11)
1254 #define FR_ARG_FIRST FR_REG (8)
1255 #define FR_RET_FIRST FR_REG (8)
1256 #define FR_RET_LAST FR_REG (15)
1257 #define AR_ARG_FIRST OUT_REG (0)
1259 /* A C expression that controls whether a function argument is passed in a
1260 register, and which register. */
1262 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1263 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1265 /* Define this macro if the target machine has "register windows", so that the
1266 register in which a function sees an arguments is not necessarily the same
1267 as the one in which the caller passed the argument. */
1269 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1270 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1272 /* A C expression for the number of words, at the beginning of an argument,
1273 must be put in registers. The value must be zero for arguments that are
1274 passed entirely in registers or that are entirely pushed on the stack. */
1276 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1277 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1279 /* A C expression that indicates when an argument must be passed by reference.
1280 If nonzero for an argument, a copy of that argument is made in memory and a
1281 pointer to the argument is passed instead of the argument itself. The
1282 pointer is passed in whatever way is appropriate for passing a pointer to
1285 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1286 ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1288 /* A C type for declaring a variable that is used as the first argument of
1289 `FUNCTION_ARG' and other related values. For some target machines, the type
1290 `int' suffices and can hold the number of bytes of argument so far. */
1292 typedef struct ia64_args
1294 int words; /* # words of arguments so far */
1295 int int_regs; /* # GR registers used so far */
1296 int fp_regs; /* # FR registers used so far */
1297 int prototype; /* whether function prototyped */
1300 /* A C statement (sans semicolon) for initializing the variable CUM for the
1301 state at the beginning of the argument list. */
1303 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1306 (CUM).int_regs = 0; \
1307 (CUM).fp_regs = 0; \
1308 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1311 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1312 arguments for the function being compiled. If this macro is undefined,
1313 `INIT_CUMULATIVE_ARGS' is used instead. */
1315 /* We set prototype to true so that we never try to return a PARALLEL from
1317 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1320 (CUM).int_regs = 0; \
1321 (CUM).fp_regs = 0; \
1322 (CUM).prototype = 1; \
1325 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1326 advance past an argument in the argument list. The values MODE, TYPE and
1327 NAMED describe that argument. Once this is done, the variable CUM is
1328 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1330 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1331 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1333 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1334 argument with the specified mode and type. */
1336 /* Arguments with alignment larger than 8 bytes start at the next even
1337 boundary. See ia64_function_arg. */
1339 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1340 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1341 : (((((MODE) == BLKmode \
1342 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1343 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1344 ? 128 : PARM_BOUNDARY)
1346 /* A C expression that is nonzero if REGNO is the number of a hard register in
1347 which function arguments are sometimes passed. This does *not* include
1348 implicit arguments such as the static chain and the structure-value address.
1349 On many machines, no registers can be used for this purpose since all
1350 function arguments are pushed on the stack. */
1351 #define FUNCTION_ARG_REGNO_P(REGNO) \
1352 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1353 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1355 /* Implement `va_arg'. */
1356 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1357 ia64_va_arg (valist, type)
1359 /* How Scalar Function Values are Returned */
1361 /* A C expression to create an RTX representing the place where a function
1362 returns a value of data type VALTYPE. */
1364 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1365 ia64_function_value (VALTYPE, FUNC)
1367 /* A C expression to create an RTX representing the place where a library
1368 function returns a value of mode MODE. */
1370 #define LIBCALL_VALUE(MODE) \
1371 gen_rtx_REG (MODE, \
1372 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1373 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1374 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1375 ? FR_RET_FIRST : GR_RET_FIRST))
1377 /* A C expression that is nonzero if REGNO is the number of a hard register in
1378 which the values of called function may come back. */
1380 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1381 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1382 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1385 /* How Large Values are Returned */
1387 /* A nonzero value says to return the function value in memory, just as large
1388 structures are always returned. */
1390 #define RETURN_IN_MEMORY(TYPE) \
1391 ia64_return_in_memory (TYPE)
1393 /* If you define this macro to be 0, then the conventions used for structure
1394 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1396 #define DEFAULT_PCC_STRUCT_RETURN 0
1398 /* If the structure value address is passed in a register, then
1399 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1401 #define STRUCT_VALUE_REGNUM GR_REG (8)
1404 /* Caller-Saves Register Allocation */
1406 /* A C expression to determine whether it is worthwhile to consider placing a
1407 pseudo-register in a call-clobbered hard register and saving and restoring
1408 it around each function call. The expression should be 1 when this is worth
1409 doing, and 0 otherwise.
1411 If you don't define this macro, a default is used which is good on most
1412 machines: `4 * CALLS < REFS'. */
1413 /* ??? Investigate. */
1414 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1417 /* Function Entry and Exit */
1419 /* Define this macro as a C expression that is nonzero if the return
1420 instruction or the function epilogue ignores the value of the stack pointer;
1421 in other words, if it is safe to delete an instruction to adjust the stack
1422 pointer before a return from the function. */
1424 #define EXIT_IGNORE_STACK 1
1426 /* Define this macro as a C expression that is nonzero for registers
1427 used by the epilogue or the `return' pattern. */
1429 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1431 /* Nonzero for registers used by the exception handling mechanism. */
1433 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1435 /* Output at beginning of assembler file. */
1437 #define ASM_FILE_START(FILE) \
1438 emit_safe_across_calls (FILE)
1440 /* Output part N of a function descriptor for DECL. For ia64, both
1441 words are emitted with a single relocation, so ignore N > 0. */
1442 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1447 fputs ("\tdata8.ua @iplt(", FILE); \
1449 fputs ("\tdata16.ua @iplt(", FILE); \
1450 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1451 fputs (")\n", FILE); \
1453 fputs ("\tdata8.ua 0\n", FILE); \
1457 /* Generating Code for Profiling. */
1459 /* A C statement or compound statement to output to FILE some assembler code to
1460 call the profiling subroutine `mcount'. */
1462 #undef FUNCTION_PROFILER
1463 #define FUNCTION_PROFILER(FILE, LABELNO) \
1466 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1467 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1468 if (TARGET_AUTO_PIC) \
1469 fputs ("\tmovl out3 = @gprel(", FILE); \
1471 fputs ("\taddl out3 = @ltoff(", FILE); \
1472 assemble_name (FILE, buf); \
1473 if (TARGET_AUTO_PIC) \
1474 fputs (");;\n", FILE); \
1476 fputs ("), r1;;\n", FILE); \
1477 fputs ("\tmov out1 = r1\n", FILE); \
1478 fputs ("\tmov out2 = b0\n", FILE); \
1479 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1482 /* Implementing the Varargs Macros. */
1484 /* Define this macro to store the anonymous register arguments into the stack
1485 so that all the arguments appear to have been passed consecutively on the
1488 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1489 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1491 /* Define this macro if the location where a function argument is passed
1492 depends on whether or not it is a named argument. */
1494 #define STRICT_ARGUMENT_NAMING 1
1497 /* Trampolines for Nested Functions. */
1499 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1500 the function containing a non-local goto target. */
1502 #define STACK_SAVEAREA_MODE(LEVEL) \
1503 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1505 /* Output assembler code for a block containing the constant parts of
1506 a trampoline, leaving space for the variable parts.
1508 The trampoline should set the static chain pointer to value placed
1509 into the trampoline and should branch to the specified routine.
1510 To make the normal indirect-subroutine calling convention work,
1511 the trampoline must look like a function descriptor; the first
1512 word being the target address and the second being the target's
1515 We abuse the concept of a global pointer by arranging for it
1516 to point to the data we need to load. The complete trampoline
1517 has the following form:
1519 +-------------------+ \
1520 TRAMP: | __ia64_trampoline | |
1521 +-------------------+ > fake function descriptor
1523 +-------------------+ /
1524 | target descriptor |
1525 +-------------------+
1527 +-------------------+
1530 /* A C expression for the size in bytes of the trampoline, as an integer. */
1532 #define TRAMPOLINE_SIZE 32
1534 /* Alignment required for trampolines, in bits. */
1536 #define TRAMPOLINE_ALIGNMENT 64
1538 /* A C statement to initialize the variable parts of a trampoline. */
1540 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1541 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1543 /* Implicit Calls to Library Routines */
1545 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1546 C) library functions `memcpy' and `memset' rather than the BSD functions
1547 `bcopy' and `bzero'. */
1549 #define TARGET_MEM_FUNCTIONS
1552 /* Addressing Modes */
1554 /* Define this macro if the machine supports post-increment addressing. */
1556 #define HAVE_POST_INCREMENT 1
1557 #define HAVE_POST_DECREMENT 1
1558 #define HAVE_POST_MODIFY_DISP 1
1559 #define HAVE_POST_MODIFY_REG 1
1561 /* A C expression that is 1 if the RTX X is a constant which is a valid
1564 #define CONSTANT_ADDRESS_P(X) 0
1566 /* The max number of registers that can appear in a valid memory address. */
1568 #define MAX_REGS_PER_ADDRESS 2
1570 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1571 RTX) is a legitimate memory address on the target machine for a memory
1572 operand of mode MODE. */
1574 #define LEGITIMATE_ADDRESS_REG(X) \
1575 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1576 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1577 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1579 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1580 (GET_CODE (X) == PLUS \
1581 && rtx_equal_p (R, XEXP (X, 0)) \
1582 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1583 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1584 && INTVAL (XEXP (X, 1)) >= -256 \
1585 && INTVAL (XEXP (X, 1)) < 256)))
1587 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1589 if (LEGITIMATE_ADDRESS_REG (X)) \
1591 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1592 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1593 && XEXP (X, 0) != arg_pointer_rtx) \
1595 else if (GET_CODE (X) == POST_MODIFY \
1596 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1597 && XEXP (X, 0) != arg_pointer_rtx \
1598 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1602 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1603 use as a base register. */
1605 #ifdef REG_OK_STRICT
1606 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1608 #define REG_OK_FOR_BASE_P(X) \
1609 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1612 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1613 use as an index register. This is needed for POST_MODIFY. */
1615 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1617 /* A C compound statement that attempts to replace X with a valid memory
1618 address for an operand of mode MODE.
1620 This must be present, but there is nothing useful to be done here. */
1622 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1624 /* A C statement or compound statement with a conditional `goto LABEL;'
1625 executed if memory address X (an RTX) can have different meanings depending
1626 on the machine mode of the memory reference it is used for or if the address
1627 is valid for some modes but not others. */
1629 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1630 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1633 /* A C expression that is nonzero if X is a legitimate constant for an
1634 immediate operand on the target machine. */
1636 #define LEGITIMATE_CONSTANT_P(X) \
1637 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1638 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1641 /* Condition Code Status */
1643 /* One some machines not all possible comparisons are defined, but you can
1644 convert an invalid comparison into a valid one. */
1645 /* ??? Investigate. See the alpha definition. */
1646 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1649 /* Describing Relative Costs of Operations */
1651 /* A part of a C `switch' statement that describes the relative costs of
1652 constant RTL expressions. */
1654 /* ??? This is incomplete. */
1656 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1658 if ((X) == const0_rtx) \
1660 switch (OUTER_CODE) \
1663 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
1665 if (CONST_OK_FOR_I (INTVAL (X))) \
1667 if (CONST_OK_FOR_J (INTVAL (X))) \
1669 return COSTS_N_INSNS (1); \
1671 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
1673 return COSTS_N_INSNS (1); \
1675 case CONST_DOUBLE: \
1676 return COSTS_N_INSNS (1); \
1680 return COSTS_N_INSNS (3);
1682 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
1684 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1686 /* For multiplies wider than HImode, we have to go to the FPU, \
1687 which normally involves copies. Plus there's the latency \
1688 of the multiply itself, and the latency of the instructions to \
1689 transfer integer regs to FP regs. */ \
1690 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
1691 return COSTS_N_INSNS (10); \
1692 return COSTS_N_INSNS (2); \
1698 return COSTS_N_INSNS (1); \
1703 /* We make divide expensive, so that divide-by-constant will be \
1704 optimized to a multiply. */ \
1705 return COSTS_N_INSNS (60);
1707 /* An expression giving the cost of an addressing mode that contains ADDRESS.
1708 If not defined, the cost is computed from the ADDRESS expression and the
1709 `CONST_COSTS' values. */
1711 #define ADDRESS_COST(ADDRESS) 0
1713 /* A C expression for the cost of moving data from a register in class FROM to
1714 one in class TO, using MODE. */
1716 #define REGISTER_MOVE_COST ia64_register_move_cost
1718 /* A C expression for the cost of moving data of mode M between a
1719 register and memory. */
1720 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1721 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1722 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1724 /* A C expression for the cost of a branch instruction. A value of 1 is the
1725 default; other values are interpreted relative to that. Used by the
1726 if-conversion code as max instruction count. */
1727 /* ??? This requires investigation. The primary effect might be how
1728 many additional insn groups we run into, vs how good the dynamic
1729 branch predictor is. */
1731 #define BRANCH_COST 6
1733 /* Define this macro as a C expression which is nonzero if accessing less than
1734 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1737 #define SLOW_BYTE_ACCESS 1
1739 /* Define this macro if it is as good or better to call a constant function
1740 address than to call an address kept in a register.
1742 Indirect function calls are more expensive that direct function calls, so
1743 don't cse function addresses. */
1745 #define NO_FUNCTION_CSE
1748 /* Dividing the output into sections. */
1750 /* A C expression whose value is a string containing the assembler operation
1751 that should precede instructions and read-only data. */
1753 #define TEXT_SECTION_ASM_OP "\t.text"
1755 /* A C expression whose value is a string containing the assembler operation to
1756 identify the following data as writable initialized data. */
1758 #define DATA_SECTION_ASM_OP "\t.data"
1760 /* If defined, a C expression whose value is a string containing the assembler
1761 operation to identify the following data as uninitialized global data. */
1763 #define BSS_SECTION_ASM_OP "\t.bss"
1765 #define ENCODE_SECTION_INFO_CHAR '@'
1767 #define IA64_DEFAULT_GVALUE 8
1769 /* Position Independent Code. */
1771 /* The register number of the register used to address a table of static data
1772 addresses in memory. */
1774 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1775 gen_rtx_REG (DImode, 1). */
1777 /* ??? Should we set flag_pic? Probably need to define
1778 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1780 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1782 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1783 clobbered by calls. */
1785 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1788 /* The Overall Framework of an Assembler File. */
1790 /* A C string constant describing how to begin a comment in the target
1791 assembler language. The compiler assumes that the comment will end at the
1794 #define ASM_COMMENT_START "//"
1796 /* A C string constant for text to be output before each `asm' statement or
1797 group of consecutive ones. */
1799 /* ??? This won't work with the Intel assembler, because it does not accept
1800 # as a comment start character. However, //APP does not work in gas, so we
1801 can't use that either. Same problem for ASM_APP_OFF below. */
1803 #define ASM_APP_ON "#APP\n"
1805 /* A C string constant for text to be output after each `asm' statement or
1806 group of consecutive ones. */
1808 #define ASM_APP_OFF "#NO_APP\n"
1811 /* Output of Data. */
1813 /* This is how to output an assembler line defining a `char' constant
1814 to an xdata segment. */
1816 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
1818 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
1819 output_addr_const (FILE, (VALUE)); \
1820 fprintf (FILE, "\n"); \
1823 /* This is how to output an assembler line defining a `short' constant
1824 to an xdata segment. */
1826 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
1828 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
1829 output_addr_const (FILE, (VALUE)); \
1830 fprintf (FILE, "\n"); \
1833 /* This is how to output an assembler line defining an `int' constant
1834 to an xdata segment. We also handle symbol output here. */
1836 /* ??? For ILP32, also need to handle function addresses here. */
1838 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
1840 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
1841 output_addr_const (FILE, (VALUE)); \
1842 fprintf (FILE, "\n"); \
1845 /* This is how to output an assembler line defining a `long' constant
1846 to an xdata segment. We also handle symbol output here. */
1848 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
1850 int need_closing_paren = 0; \
1851 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
1852 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
1853 && GET_CODE (VALUE) == SYMBOL_REF) \
1855 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
1856 need_closing_paren = 1; \
1858 output_addr_const (FILE, VALUE); \
1859 if (need_closing_paren) \
1860 fprintf (FILE, ")"); \
1861 fprintf (FILE, "\n"); \
1866 /* Output of Uninitialized Variables. */
1868 /* This is all handled by svr4.h. */
1871 /* Output and Generation of Labels. */
1873 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1874 assembler definition of a label named NAME. */
1876 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1877 why ia64_asm_output_label exists. */
1879 extern int ia64_asm_output_label;
1880 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1882 ia64_asm_output_label = 1; \
1883 assemble_name (STREAM, NAME); \
1884 fputs (":\n", STREAM); \
1885 ia64_asm_output_label = 0; \
1888 /* Globalizing directive for a label. */
1889 #define GLOBAL_ASM_OP "\t.global "
1891 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1892 necessary for declaring the name of an external symbol named NAME which is
1893 referenced in this compilation but not defined. */
1895 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1896 ia64_asm_output_external (FILE, DECL, NAME)
1898 /* A C statement to store into the string STRING a label whose name is made
1899 from the string PREFIX and the number NUM. */
1901 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1903 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1906 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1908 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1910 /* A C statement to output to the stdio stream STREAM assembler code which
1911 defines (equates) the symbol NAME to have the value VALUE. */
1913 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1915 assemble_name (STREAM, NAME); \
1916 fputs (" = ", STREAM); \
1917 assemble_name (STREAM, VALUE); \
1918 fputc ('\n', STREAM); \
1922 /* Macros Controlling Initialization Routines. */
1924 /* This is handled by svr4.h and sysv4.h. */
1927 /* Output of Assembler Instructions. */
1929 /* A C initializer containing the assembler's names for the machine registers,
1930 each one as a C string constant. */
1932 #define REGISTER_NAMES \
1934 /* General registers. */ \
1935 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1936 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1937 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1939 /* Local registers. */ \
1940 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1941 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1942 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1943 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1944 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1945 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1946 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1947 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1948 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1949 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1950 /* Input registers. */ \
1951 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1952 /* Output registers. */ \
1953 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1954 /* Floating-point registers. */ \
1955 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1956 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1957 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1958 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1959 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1960 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1961 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1962 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1963 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1964 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1965 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1966 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1967 "f120","f121","f122","f123","f124","f125","f126","f127", \
1968 /* Predicate registers. */ \
1969 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1970 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1971 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1972 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1973 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1974 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1975 "p60", "p61", "p62", "p63", \
1976 /* Branch registers. */ \
1977 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1978 /* Frame pointer. Return address. */ \
1979 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1982 /* If defined, a C initializer for an array of structures containing a name and
1983 a register number. This macro defines additional names for hard registers,
1984 thus allowing the `asm' option in declarations to refer to registers using
1987 #define ADDITIONAL_REGISTER_NAMES \
1989 { "gp", R_GR (1) }, \
1990 { "sp", R_GR (12) }, \
1991 { "in0", IN_REG (0) }, \
1992 { "in1", IN_REG (1) }, \
1993 { "in2", IN_REG (2) }, \
1994 { "in3", IN_REG (3) }, \
1995 { "in4", IN_REG (4) }, \
1996 { "in5", IN_REG (5) }, \
1997 { "in6", IN_REG (6) }, \
1998 { "in7", IN_REG (7) }, \
1999 { "out0", OUT_REG (0) }, \
2000 { "out1", OUT_REG (1) }, \
2001 { "out2", OUT_REG (2) }, \
2002 { "out3", OUT_REG (3) }, \
2003 { "out4", OUT_REG (4) }, \
2004 { "out5", OUT_REG (5) }, \
2005 { "out6", OUT_REG (6) }, \
2006 { "out7", OUT_REG (7) }, \
2007 { "loc0", LOC_REG (0) }, \
2008 { "loc1", LOC_REG (1) }, \
2009 { "loc2", LOC_REG (2) }, \
2010 { "loc3", LOC_REG (3) }, \
2011 { "loc4", LOC_REG (4) }, \
2012 { "loc5", LOC_REG (5) }, \
2013 { "loc6", LOC_REG (6) }, \
2014 { "loc7", LOC_REG (7) }, \
2015 { "loc8", LOC_REG (8) }, \
2016 { "loc9", LOC_REG (9) }, \
2017 { "loc10", LOC_REG (10) }, \
2018 { "loc11", LOC_REG (11) }, \
2019 { "loc12", LOC_REG (12) }, \
2020 { "loc13", LOC_REG (13) }, \
2021 { "loc14", LOC_REG (14) }, \
2022 { "loc15", LOC_REG (15) }, \
2023 { "loc16", LOC_REG (16) }, \
2024 { "loc17", LOC_REG (17) }, \
2025 { "loc18", LOC_REG (18) }, \
2026 { "loc19", LOC_REG (19) }, \
2027 { "loc20", LOC_REG (20) }, \
2028 { "loc21", LOC_REG (21) }, \
2029 { "loc22", LOC_REG (22) }, \
2030 { "loc23", LOC_REG (23) }, \
2031 { "loc24", LOC_REG (24) }, \
2032 { "loc25", LOC_REG (25) }, \
2033 { "loc26", LOC_REG (26) }, \
2034 { "loc27", LOC_REG (27) }, \
2035 { "loc28", LOC_REG (28) }, \
2036 { "loc29", LOC_REG (29) }, \
2037 { "loc30", LOC_REG (30) }, \
2038 { "loc31", LOC_REG (31) }, \
2039 { "loc32", LOC_REG (32) }, \
2040 { "loc33", LOC_REG (33) }, \
2041 { "loc34", LOC_REG (34) }, \
2042 { "loc35", LOC_REG (35) }, \
2043 { "loc36", LOC_REG (36) }, \
2044 { "loc37", LOC_REG (37) }, \
2045 { "loc38", LOC_REG (38) }, \
2046 { "loc39", LOC_REG (39) }, \
2047 { "loc40", LOC_REG (40) }, \
2048 { "loc41", LOC_REG (41) }, \
2049 { "loc42", LOC_REG (42) }, \
2050 { "loc43", LOC_REG (43) }, \
2051 { "loc44", LOC_REG (44) }, \
2052 { "loc45", LOC_REG (45) }, \
2053 { "loc46", LOC_REG (46) }, \
2054 { "loc47", LOC_REG (47) }, \
2055 { "loc48", LOC_REG (48) }, \
2056 { "loc49", LOC_REG (49) }, \
2057 { "loc50", LOC_REG (50) }, \
2058 { "loc51", LOC_REG (51) }, \
2059 { "loc52", LOC_REG (52) }, \
2060 { "loc53", LOC_REG (53) }, \
2061 { "loc54", LOC_REG (54) }, \
2062 { "loc55", LOC_REG (55) }, \
2063 { "loc56", LOC_REG (56) }, \
2064 { "loc57", LOC_REG (57) }, \
2065 { "loc58", LOC_REG (58) }, \
2066 { "loc59", LOC_REG (59) }, \
2067 { "loc60", LOC_REG (60) }, \
2068 { "loc61", LOC_REG (61) }, \
2069 { "loc62", LOC_REG (62) }, \
2070 { "loc63", LOC_REG (63) }, \
2071 { "loc64", LOC_REG (64) }, \
2072 { "loc65", LOC_REG (65) }, \
2073 { "loc66", LOC_REG (66) }, \
2074 { "loc67", LOC_REG (67) }, \
2075 { "loc68", LOC_REG (68) }, \
2076 { "loc69", LOC_REG (69) }, \
2077 { "loc70", LOC_REG (70) }, \
2078 { "loc71", LOC_REG (71) }, \
2079 { "loc72", LOC_REG (72) }, \
2080 { "loc73", LOC_REG (73) }, \
2081 { "loc74", LOC_REG (74) }, \
2082 { "loc75", LOC_REG (75) }, \
2083 { "loc76", LOC_REG (76) }, \
2084 { "loc77", LOC_REG (77) }, \
2085 { "loc78", LOC_REG (78) }, \
2086 { "loc79", LOC_REG (79) }, \
2089 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2090 for an instruction operand X. X is an RTL expression. */
2092 #define PRINT_OPERAND(STREAM, X, CODE) \
2093 ia64_print_operand (STREAM, X, CODE)
2095 /* A C expression which evaluates to true if CODE is a valid punctuation
2096 character for use in the `PRINT_OPERAND' macro. */
2098 /* ??? Keep this around for now, as we might need it later. */
2100 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2101 ((CODE) == '+' || (CODE) == ',')
2103 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2104 for an instruction operand that is a memory reference whose address is X. X
2105 is an RTL expression. */
2107 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2108 ia64_print_operand_address (STREAM, X)
2110 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2111 `%I' options of `asm_fprintf' (see `final.c'). */
2113 #define REGISTER_PREFIX ""
2114 #define LOCAL_LABEL_PREFIX "."
2115 #define USER_LABEL_PREFIX ""
2116 #define IMMEDIATE_PREFIX ""
2119 /* Output of dispatch tables. */
2121 /* This macro should be provided on machines where the addresses in a dispatch
2122 table are relative to the table's own address. */
2124 /* ??? Depends on the pointer size. */
2126 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2127 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
2129 /* This is how to output an element of a case-vector that is absolute.
2130 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2132 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2134 /* Jump tables only need 8 byte alignment. */
2136 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2139 /* Assembler Commands for Exception Regions. */
2141 /* Select a format to encode pointers in exception handling data. CODE
2142 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2143 true if the symbol may be affected by dynamic relocations. */
2144 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2145 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2146 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2148 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2149 indirect are handled automatically. */
2150 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2152 const char *reltag = NULL; \
2153 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2154 reltag = "@segrel("; \
2155 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2156 reltag = "@gprel("; \
2159 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2160 fputs (reltag, FILE); \
2161 assemble_name (FILE, XSTR (ADDR, 0)); \
2162 fputc (')', FILE); \
2168 /* Assembler Commands for Alignment. */
2170 /* ??? Investigate. */
2172 /* The alignment (log base 2) to put in front of LABEL, which follows
2175 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2177 /* The desired alignment for the location counter at the beginning
2180 /* #define LOOP_ALIGN(LABEL) */
2182 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2183 section because it fails put zeros in the bytes that are skipped. */
2185 #define ASM_NO_SKIP_IN_TEXT 1
2187 /* A C statement to output to the stdio stream STREAM an assembler command to
2188 advance the location counter to a multiple of 2 to the POWER bytes. */
2190 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2191 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2194 /* Macros Affecting all Debug Formats. */
2196 /* This is handled in svr4.h and sysv4.h. */
2199 /* Specific Options for DBX Output. */
2201 /* This is handled by dbxelf.h which is included by svr4.h. */
2204 /* Open ended Hooks for DBX Output. */
2209 /* File names in DBX format. */
2214 /* Macros for SDB and Dwarf Output. */
2216 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2217 output in response to the `-g' option. */
2219 #define DWARF2_DEBUGGING_INFO 1
2221 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2223 /* Use tags for debug info labels, so that they don't break instruction
2224 bundles. This also avoids getting spurious DV warnings from the
2225 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
2226 add brackets around the label. */
2228 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2229 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2231 /* Use section-relative relocations for debugging offsets. Unlike other
2232 targets that fake this by putting the section VMA at 0, IA-64 has
2233 proper relocations for them. */
2234 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2236 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2237 fputs ("@secrel(", FILE); \
2238 assemble_name (FILE, LABEL); \
2239 fputc (')', FILE); \
2242 /* Emit a PC-relative relocation. */
2243 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2245 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2246 fputs ("@pcrel(", FILE); \
2247 assemble_name (FILE, LABEL); \
2248 fputc (')', FILE); \
2251 /* Register Renaming Parameters. */
2253 /* A C expression that is nonzero if hard register number REGNO2 can be
2254 considered for use as a rename register for REGNO1 */
2256 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2257 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2260 /* Miscellaneous Parameters. */
2262 /* Define this if you have defined special-purpose predicates in the file
2263 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2264 expressions matched by the predicate. */
2266 #define PREDICATE_CODES \
2267 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2268 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2269 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2270 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2271 { "function_operand", {SYMBOL_REF}}, \
2272 { "setjmp_operand", {SYMBOL_REF}}, \
2273 { "destination_operand", {SUBREG, REG, MEM}}, \
2274 { "not_postinc_memory_operand", {MEM}}, \
2275 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2276 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2277 { "gr_register_operand", {SUBREG, REG}}, \
2278 { "fr_register_operand", {SUBREG, REG}}, \
2279 { "grfr_register_operand", {SUBREG, REG}}, \
2280 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2281 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2282 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2283 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2284 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2285 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2286 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2287 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2288 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2290 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2292 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2293 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2294 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2295 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2297 { "shladd_operand", {CONST_INT}}, \
2298 { "fetchadd_operand", {CONST_INT}}, \
2299 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2300 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2301 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2302 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2303 { "predicate_operator", {NE, EQ}}, \
2304 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2305 { "ar_lc_reg_operand", {REG}}, \
2306 { "ar_ccv_reg_operand", {REG}}, \
2307 { "ar_pfs_reg_operand", {REG}}, \
2308 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2309 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2310 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
2311 { "basereg_operand", {SUBREG, REG}},
2313 /* An alias for a machine mode name. This is the machine mode that elements of
2314 a jump-table should have. */
2316 #define CASE_VECTOR_MODE Pmode
2318 /* Define as C expression which evaluates to nonzero if the tablejump
2319 instruction expects the table to contain offsets from the address of the
2322 #define CASE_VECTOR_PC_RELATIVE 1
2324 /* Define this macro if operations between registers with integral mode smaller
2325 than a word are always performed on the entire register. */
2327 #define WORD_REGISTER_OPERATIONS
2329 /* Define this macro to be a C expression indicating when insns that read
2330 memory in MODE, an integral mode narrower than a word, set the bits outside
2331 of MODE to be either the sign-extension or the zero-extension of the data
2334 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2336 /* The maximum number of bytes that a single instruction can move quickly from
2337 memory to memory. */
2340 /* A C expression which is nonzero if on this machine it is safe to "convert"
2341 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2342 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2344 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2346 /* A C expression describing the value returned by a comparison operator with
2347 an integral mode and stored by a store-flag instruction (`sCOND') when the
2348 condition is true. */
2350 /* ??? Investigate using -1 instead of 1. */
2352 #define STORE_FLAG_VALUE 1
2354 /* An alias for the machine mode for pointers. */
2356 /* ??? This would change if we had ILP32 support. */
2358 #define Pmode DImode
2360 /* An alias for the machine mode used for memory references to functions being
2361 called, in `call' RTL expressions. */
2363 #define FUNCTION_MODE Pmode
2365 /* Define this macro to handle System V style pragmas: #pragma pack and
2366 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2369 /* If this architecture supports prefetch, define this to be the number of
2370 prefetch commands that can be executed in parallel.
2372 ??? This number is bogus and needs to be replaced before the value is
2373 actually used in optimizations. */
2375 #define SIMULTANEOUS_PREFETCHES 6
2377 /* If this architecture supports prefetch, define this to be the size of
2378 the cache line that is prefetched. */
2380 #define PREFETCH_BLOCK 32
2382 #define HANDLE_SYSV_PRAGMA 1
2384 /* In rare cases, correct code generation requires extra machine dependent
2385 processing between the second jump optimization pass and delayed branch
2386 scheduling. On those machines, define this macro as a C statement to act on
2387 the code starting at INSN. */
2389 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2391 /* A C expression for the maximum number of instructions to execute via
2392 conditional execution instructions instead of a branch. A value of
2393 BRANCH_COST+1 is the default if the machine does not use
2394 cc0, and 1 if it does use cc0. */
2395 /* ??? Investigate. */
2396 #define MAX_CONDITIONAL_EXECUTE 12
2398 extern int ia64_final_schedule;
2400 #define IA64_UNWIND_INFO 1
2401 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2403 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2405 /* This function contains machine specific function data. */
2406 struct machine_function GTY(())
2408 /* The new stack pointer when unwinding from EH. */
2409 rtx ia64_eh_epilogue_sp;
2411 /* The new bsp value when unwinding from EH. */
2412 rtx ia64_eh_epilogue_bsp;
2414 /* The GP value save register. */
2417 /* The number of varargs registers to save. */
2424 IA64_BUILTIN_SYNCHRONIZE,
2426 IA64_BUILTIN_FETCH_AND_ADD_SI,
2427 IA64_BUILTIN_FETCH_AND_SUB_SI,
2428 IA64_BUILTIN_FETCH_AND_OR_SI,
2429 IA64_BUILTIN_FETCH_AND_AND_SI,
2430 IA64_BUILTIN_FETCH_AND_XOR_SI,
2431 IA64_BUILTIN_FETCH_AND_NAND_SI,
2433 IA64_BUILTIN_ADD_AND_FETCH_SI,
2434 IA64_BUILTIN_SUB_AND_FETCH_SI,
2435 IA64_BUILTIN_OR_AND_FETCH_SI,
2436 IA64_BUILTIN_AND_AND_FETCH_SI,
2437 IA64_BUILTIN_XOR_AND_FETCH_SI,
2438 IA64_BUILTIN_NAND_AND_FETCH_SI,
2440 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2441 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2443 IA64_BUILTIN_SYNCHRONIZE_SI,
2445 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2447 IA64_BUILTIN_LOCK_RELEASE_SI,
2449 IA64_BUILTIN_FETCH_AND_ADD_DI,
2450 IA64_BUILTIN_FETCH_AND_SUB_DI,
2451 IA64_BUILTIN_FETCH_AND_OR_DI,
2452 IA64_BUILTIN_FETCH_AND_AND_DI,
2453 IA64_BUILTIN_FETCH_AND_XOR_DI,
2454 IA64_BUILTIN_FETCH_AND_NAND_DI,
2456 IA64_BUILTIN_ADD_AND_FETCH_DI,
2457 IA64_BUILTIN_SUB_AND_FETCH_DI,
2458 IA64_BUILTIN_OR_AND_FETCH_DI,
2459 IA64_BUILTIN_AND_AND_FETCH_DI,
2460 IA64_BUILTIN_XOR_AND_FETCH_DI,
2461 IA64_BUILTIN_NAND_AND_FETCH_DI,
2463 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2464 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2466 IA64_BUILTIN_SYNCHRONIZE_DI,
2468 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2470 IA64_BUILTIN_LOCK_RELEASE_DI,
2473 IA64_BUILTIN_FLUSHRS
2476 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2478 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
2481 #define DONT_USE_BUILTIN_SETJMP
2483 /* Output any profiling code before the prologue. */
2485 #undef PROFILE_BEFORE_PROLOGUE
2486 #define PROFILE_BEFORE_PROLOGUE 1
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