1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
34 /* Define this to be a string constant containing `-D' options to define the
35 predefined macros that identify this machine and system. These macros will
36 be predefined unless the `-ansi' option is specified. */
37 /* ??? This is undefed in svr4.h. */
38 #define CPP_PREDEFINES "-Dia64 -Amachine=ia64"
40 /* This declaration should be present. */
41 extern int target_flags;
43 /* This series of macros is to allow compiler command arguments to enable or
44 disable the use of optional features of the target machine. */
46 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
48 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
50 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
52 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
54 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
56 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
58 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
60 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
62 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
64 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
66 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
68 #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
70 #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
72 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
74 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
76 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
78 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
80 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
82 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
84 #define TARGET_ILP32 (target_flags & MASK_ILP32)
86 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
88 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
90 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
92 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
94 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
96 #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
98 #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
100 #define TARGET_INLINE_DIV \
101 (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
103 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
105 /* This macro defines names of command options to set and clear bits in
106 `target_flags'. Its definition is an initializer with a subgrouping for
107 each command option. */
109 #define TARGET_SWITCHES \
111 { "big-endian", MASK_BIG_ENDIAN, \
112 N_("Generate big endian code") }, \
113 { "little-endian", -MASK_BIG_ENDIAN, \
114 N_("Generate little endian code") }, \
115 { "gnu-as", MASK_GNU_AS, \
116 N_("Generate code for GNU as") }, \
117 { "no-gnu-as", -MASK_GNU_AS, \
118 N_("Generate code for Intel as") }, \
119 { "gnu-ld", MASK_GNU_LD, \
120 N_("Generate code for GNU ld") }, \
121 { "no-gnu-ld", -MASK_GNU_LD, \
122 N_("Generate code for Intel ld") }, \
123 { "no-pic", MASK_NO_PIC, \
124 N_("Generate code without GP reg") }, \
125 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
126 N_("Emit stop bits before and after volatile extended asms") }, \
127 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
128 N_("Don't emit stop bits before and after volatile extended asms") }, \
129 { "b-step", MASK_B_STEP, \
130 N_("Emit code for Itanium (TM) processor B step")}, \
131 { "register-names", MASK_REG_NAMES, \
132 N_("Use in/loc/out register names")}, \
133 { "no-sdata", MASK_NO_SDATA, \
134 N_("Disable use of sdata/scommon/sbss")}, \
135 { "sdata", -MASK_NO_SDATA, \
136 N_("Enable use of sdata/scommon/sbss")}, \
137 { "constant-gp", MASK_CONST_GP, \
138 N_("gp is constant (but save/restore gp on indirect calls)") }, \
139 { "auto-pic", MASK_AUTO_PIC, \
140 N_("Generate self-relocatable code") }, \
141 { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
142 N_("Generate inline division, optimize for latency") }, \
143 { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
144 N_("Generate inline division, optimize for throughput") }, \
145 { "dwarf2-asm", MASK_DWARF2_ASM, \
146 N_("Enable Dwarf 2 line debug info via GNU as")}, \
147 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
148 N_("Disable Dwarf 2 line debug info via GNU as")}, \
150 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
154 /* Default target_flags if no switches are specified */
156 #ifndef TARGET_DEFAULT
157 #define TARGET_DEFAULT MASK_DWARF2_ASM
160 #ifndef TARGET_CPU_DEFAULT
161 #define TARGET_CPU_DEFAULT 0
164 #ifndef SUBTARGET_SWITCHES
165 #define SUBTARGET_SWITCHES
168 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
169 options that have values. Its definition is an initializer with a
170 subgrouping for each command option. */
172 extern const char *ia64_fixed_range_string;
173 #define TARGET_OPTIONS \
175 { "fixed-range=", &ia64_fixed_range_string, \
176 N_("Specify range of registers to make fixed.")}, \
179 /* This macro is a C statement to print on `stderr' a string describing the
180 particular machine description choice. */
182 #define TARGET_VERSION fprintf (stderr, " (IA-64)");
184 /* Sometimes certain combinations of command options do not make sense on a
185 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
186 take account of this. This macro, if defined, is executed once just after
187 all the command options have been parsed. */
189 #define OVERRIDE_OPTIONS ia64_override_options ()
191 /* Some machines may desire to change what optimizations are performed for
192 various optimization levels. This macro, if defined, is executed once just
193 after the optimization level is determined and before the remainder of the
194 command options have been parsed. Values set in this macro are used as the
195 default values for the other command line options. */
197 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
199 /* Driver configuration */
201 /* A C string constant that tells the GNU CC driver program options to pass to
202 CPP. It can also specify how to translate options you give to GNU CC into
203 options for GNU CC to pass to the CPP. */
205 /* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */
206 /* ??? An alternative is to modify glimits.h to check for __LP64__ instead
207 of checked for CPU specific defines. We could also get rid of all LONG_MAX
208 defines in other tm.h files. */
210 "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
211 -D__LONG_MAX__=9223372036854775807L"
213 /* If this macro is defined, the preprocessor will not define the builtin macro
214 `__SIZE_TYPE__'. The macro `__SIZE_TYPE__' must then be defined by
217 This should be defined if `SIZE_TYPE' depends on target dependent flags
218 which are not accessible to the preprocessor. Otherwise, it should not be
220 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
221 /* #define NO_BUILTIN_SIZE_TYPE */
223 /* If this macro is defined, the preprocessor will not define the builtin macro
224 `__PTRDIFF_TYPE__'. The macro `__PTRDIFF_TYPE__' must then be defined by
227 This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
228 which are not accessible to the preprocessor. Otherwise, it should not be
230 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
231 /* #define NO_BUILTIN_PTRDIFF_TYPE */
233 /* A C string constant that tells the GNU CC driver program options to pass to
234 `cc1'. It can also specify how to translate options you give to GNU CC into
235 options for GNU CC to pass to the `cc1'. */
238 #define CC1_SPEC "%{G*}"
240 /* A C string constant that tells the GNU CC driver program options to pass to
241 `cc1plus'. It can also specify how to translate options you give to GNU CC
242 into options for GNU CC to pass to the `cc1plus'. */
244 /* #define CC1PLUS_SPEC "" */
246 /* A C string constant that tells the GNU CC driver program options to pass to
247 the assembler. It can also specify how to translate options you give to GNU
248 CC into options for GNU CC to pass to the assembler. */
250 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GNU_AS) != 0
253 "%{mno-gnu-as:-N so} %{!mno-gnu-as:-x} %{mconstant-gp} %{mauto-pic}"
257 "%{!mgnu-as:-N so} %{mgnu-as:-x} %{mconstant-gp:-M const_gp}\
258 %{mauto-pic:-M no_plabel}"
261 /* A C string constant that tells the GNU CC driver program options to pass to
262 the linker. It can also specify how to translate options you give to GNU CC
263 into options for GNU CC to pass to the linker. */
265 /* The Intel linker does not support dynamic linking, so we need -dn.
266 The Intel linker gives annoying messages unless -N so is used. */
267 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GNU_LD) != 0
269 #define LINK_SPEC "%{mno-gnu-ld:-dn -N so}"
272 #define LINK_SPEC "%{!mgnu-ld:-dn -N so}"
278 /* Define this macro to have the value 1 if the most significant bit in a byte
279 has the lowest number; otherwise define it to have the value zero. */
281 #define BITS_BIG_ENDIAN 0
283 /* Define this macro to have the value 1 if the most significant byte in a word
284 has the lowest number. This macro need not be a constant. */
286 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
288 /* Define this macro to have the value 1 if, in a multiword object, the most
289 significant word has the lowest number. */
291 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
293 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a
294 constant value with the same meaning as WORDS_BIG_ENDIAN, which will be used
295 only when compiling libgcc2.c. Typically the value will be set based on
296 preprocessor defines. */
297 #if defined(__BIG_ENDIAN__)
298 #define LIBGCC2_WORDS_BIG_ENDIAN 1
300 #define LIBGCC2_WORDS_BIG_ENDIAN 0
303 /* Define this macro to be the number of bits in an addressable storage unit
304 (byte); normally 8. */
305 #define BITS_PER_UNIT 8
307 /* Number of bits in a word; normally 32. */
308 #define BITS_PER_WORD 64
310 /* Number of storage units in a word; normally 4. */
311 #define UNITS_PER_WORD 8
313 /* Width of a pointer, in bits. You must specify a value no wider than the
314 width of `Pmode'. If it is not equal to the width of `Pmode', you must
315 define `POINTERS_EXTEND_UNSIGNED'. */
316 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
318 /* A C expression whose value is zero if pointers that need to be extended
319 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
320 they are zero-extended and negative one if there is an ptr_extend operation.
322 You need not define this macro if the `POINTER_SIZE' is equal to the width
324 /* Need this for 32 bit pointers, see hpux.h for setting it. */
325 /* #define POINTERS_EXTEND_UNSIGNED */
327 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
328 which has the specified mode and signedness is to be stored in a register.
329 This macro is only called when TYPE is a scalar type. */
330 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
333 if (GET_MODE_CLASS (MODE) == MODE_INT \
334 && GET_MODE_SIZE (MODE) < 4) \
339 /* Define this macro if the promotion described by `PROMOTE_MODE' should also
340 be done for outgoing function arguments. */
341 /* ??? ABI doesn't allow us to define this. */
342 /* #define PROMOTE_FUNCTION_ARGS */
344 /* Define this macro if the promotion described by `PROMOTE_MODE' should also
345 be done for the return value of functions.
347 If this macro is defined, `FUNCTION_VALUE' must perform the same promotions
348 done by `PROMOTE_MODE'. */
349 /* ??? ABI doesn't allow us to define this. */
350 /* #define PROMOTE_FUNCTION_RETURN */
352 /* Normal alignment required for function parameters on the stack, in bits.
353 All stack parameters receive at least this much alignment regardless of data
354 type. On most machines, this is the same as the size of an integer. */
355 #define PARM_BOUNDARY 64
357 /* Define this macro if you wish to preserve a certain alignment for the stack
358 pointer. The definition is a C expression for the desired alignment
359 (measured in bits). */
361 #define STACK_BOUNDARY 128
363 /* Align frames on double word boundaries */
364 #ifndef IA64_STACK_ALIGN
365 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
368 /* Alignment required for a function entry point, in bits. */
369 #define FUNCTION_BOUNDARY 128
371 /* Biggest alignment that any data type can require on this machine,
373 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
374 128 bit integers all require 128 bit alignment. */
375 #define BIGGEST_ALIGNMENT 128
377 /* If defined, a C expression to compute the alignment for a static variable.
378 TYPE is the data type, and ALIGN is the alignment that the object
379 would ordinarily have. The value of this macro is used instead of that
380 alignment to align the object. */
382 #define DATA_ALIGNMENT(TYPE, ALIGN) \
383 (TREE_CODE (TYPE) == ARRAY_TYPE \
384 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
385 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
387 /* If defined, a C expression to compute the alignment given to a constant that
388 is being placed in memory. CONSTANT is the constant and ALIGN is the
389 alignment that the object would ordinarily have. The value of this macro is
390 used instead of that alignment to align the object. */
392 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
393 (TREE_CODE (EXP) == STRING_CST \
394 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
396 /* Define this macro to be the value 1 if instructions will fail to work if
397 given data not on the nominal alignment. If instructions will merely go
398 slower in that case, define this macro as 0. */
399 #define STRICT_ALIGNMENT 1
401 /* Define this if you wish to imitate the way many other C compilers handle
402 alignment of bitfields and the structures that contain them.
403 The behavior is that the type written for a bitfield (`int', `short', or
404 other integer type) imposes an alignment for the entire structure, as if the
405 structure really did contain an ordinary field of that type. In addition,
406 the bitfield is placed within the structure so that it would fit within such
407 a field, not crossing a boundary for it. */
408 #define PCC_BITFIELD_TYPE_MATTERS 1
410 /* An integer expression for the size in bits of the largest integer machine
411 mode that should actually be used. */
413 /* Allow pairs of registers to be used, which is the intent of the default. */
414 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
416 /* A code distinguishing the floating point format of the target machine. */
417 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
420 /* Layout of Source Language Data Types */
422 /* A C expression for the size in bits of the type `int' on the target machine.
423 If you don't define this, the default is one word. */
424 #define INT_TYPE_SIZE 32
426 /* A C expression for the size in bits of the type `short' on the target
427 machine. If you don't define this, the default is half a word. (If this
428 would be less than one storage unit, it is rounded up to one unit.) */
429 #define SHORT_TYPE_SIZE 16
431 /* A C expression for the size in bits of the type `long' on the target
432 machine. If you don't define this, the default is one word. */
433 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
435 /* Maximum number for the size in bits of the type `long' on the target
436 machine. If this is undefined, the default is `LONG_TYPE_SIZE'. Otherwise,
437 it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
438 have at run-time. This is used in `cpp'. */
439 #define MAX_LONG_TYPE_SIZE 64
441 /* A C expression for the size in bits of the type `long long' on the target
442 machine. If you don't define this, the default is two words. If you want
443 to support GNU Ada on your machine, the value of macro must be at least 64. */
444 #define LONG_LONG_TYPE_SIZE 64
446 /* A C expression for the size in bits of the type `char' on the target
447 machine. If you don't define this, the default is one quarter of a word.
448 (If this would be less than one storage unit, it is rounded up to one unit.) */
449 #define CHAR_TYPE_SIZE 8
451 /* A C expression for the size in bits of the type `float' on the target
452 machine. If you don't define this, the default is one word. */
453 #define FLOAT_TYPE_SIZE 32
455 /* A C expression for the size in bits of the type `double' on the target
456 machine. If you don't define this, the default is two words. */
457 #define DOUBLE_TYPE_SIZE 64
459 /* A C expression for the size in bits of the type `long double' on the target
460 machine. If you don't define this, the default is two words. */
461 #define LONG_DOUBLE_TYPE_SIZE 128
463 /* Tell real.c that this is the 80-bit Intel extended float format
464 packaged in a 128-bit entity. */
466 #define INTEL_EXTENDED_IEEE_FORMAT 1
468 /* An expression whose value is 1 or 0, according to whether the type `char'
469 should be signed or unsigned by default. The user can always override this
470 default with the options `-fsigned-char' and `-funsigned-char'. */
471 #define DEFAULT_SIGNED_CHAR 1
473 /* A C expression for a string describing the name of the data type to use for
474 size values. The typedef name `size_t' is defined using the contents of the
476 /* ??? Needs to be defined for P64 code. */
477 /* #define SIZE_TYPE */
479 /* A C expression for a string describing the name of the data type to use for
480 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
481 defined using the contents of the string. See `SIZE_TYPE' above for more
483 /* ??? Needs to be defined for P64 code. */
484 /* #define PTRDIFF_TYPE */
486 /* A C expression for a string describing the name of the data type to use for
487 wide characters. The typedef name `wchar_t' is defined using the contents
488 of the string. See `SIZE_TYPE' above for more information. */
489 /* #define WCHAR_TYPE */
491 /* A C expression for the size in bits of the data type for wide characters.
492 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
493 /* #define WCHAR_TYPE_SIZE */
495 /* Maximum number for the size in bits of the data type for wide characters.
496 If this is undefined, the default is `WCHAR_TYPE_SIZE'. Otherwise, it is
497 the constant value that is the largest value that `WCHAR_TYPE_SIZE' can have
498 at run-time. This is used in `cpp'. */
499 /* #define MAX_WCHAR_TYPE_SIZE */
502 /* Register Basics */
504 /* Number of hardware registers known to the compiler.
505 We have 128 general registers, 128 floating point registers,
506 64 predicate registers, 8 branch registers, one frame pointer,
507 and several "application" registers. */
509 #define FIRST_PSEUDO_REGISTER 335
511 /* Ranges for the various kinds of registers. */
512 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
513 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
514 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
515 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
516 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
517 #define GENERAL_REGNO_P(REGNO) \
518 (GR_REGNO_P (REGNO) \
519 || (REGNO) == FRAME_POINTER_REGNUM \
520 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
522 #define GR_REG(REGNO) ((REGNO) + 0)
523 #define FR_REG(REGNO) ((REGNO) + 128)
524 #define PR_REG(REGNO) ((REGNO) + 256)
525 #define BR_REG(REGNO) ((REGNO) + 320)
526 #define OUT_REG(REGNO) ((REGNO) + 120)
527 #define IN_REG(REGNO) ((REGNO) + 112)
528 #define LOC_REG(REGNO) ((REGNO) + 32)
530 #define AR_CCV_REGNUM 330
531 #define AR_UNAT_REGNUM 331
532 #define AR_PFS_REGNUM 332
533 #define AR_LC_REGNUM 333
534 #define AR_EC_REGNUM 334
536 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
537 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
538 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
540 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
541 || (REGNO) == AR_UNAT_REGNUM)
542 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
543 && (REGNO) < FIRST_PSEUDO_REGISTER)
544 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
545 && (REGNO) < FIRST_PSEUDO_REGISTER)
548 /* ??? Don't really need two sets of macros. I like this one better because
549 it is less typing. */
550 #define R_GR(REGNO) GR_REG (REGNO)
551 #define R_FR(REGNO) FR_REG (REGNO)
552 #define R_PR(REGNO) PR_REG (REGNO)
553 #define R_BR(REGNO) BR_REG (REGNO)
555 /* An initializer that says which registers are used for fixed purposes all
556 throughout the compiled code and are therefore not available for general
560 r1: global pointer (gp)
561 r12: stack pointer (sp)
562 r13: thread pointer (tp)
566 fp: eliminable frame pointer */
568 /* The last 16 stacked regs are reserved for the 8 input and 8 output
571 #define FIXED_REGISTERS \
572 { /* General registers. */ \
573 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
574 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
575 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
576 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
577 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
578 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
579 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
580 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
581 /* Floating-point registers. */ \
582 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
590 /* Predicate registers. */ \
591 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
595 /* Branch registers. */ \
596 0, 0, 0, 0, 0, 0, 0, 0, \
597 /*FP RA CCV UNAT PFS LC EC */ \
598 1, 1, 1, 1, 1, 0, 1 \
601 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
602 (in general) by function calls as well as for fixed registers. This
603 macro therefore identifies the registers that are not available for
604 general allocation of values that must live across function calls. */
606 #define CALL_USED_REGISTERS \
607 { /* General registers. */ \
608 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
609 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
614 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
615 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
616 /* Floating-point registers. */ \
617 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
620 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
621 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
622 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
624 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
625 /* Predicate registers. */ \
626 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
627 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
630 /* Branch registers. */ \
631 1, 0, 0, 0, 0, 0, 1, 1, \
632 /*FP RA CCV UNAT PFS LC EC */ \
633 1, 1, 1, 1, 1, 0, 1 \
636 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
637 problem which makes CALL_USED_REGISTERS *always* include
638 all the FIXED_REGISTERS. Until this problem has been
639 resolved this macro can be used to overcome this situation.
640 In particular, block_propagate() requires this list
641 be acurate, or we can remove registers which should be live.
642 This macro is used in regs_invalidated_by_call ()*/
644 #define CALL_REALLY_USED_REGISTERS \
645 { /* General registers. */ \
646 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
647 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
648 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
649 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
651 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
652 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
653 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
654 /* Floating-point registers. */ \
655 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
656 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
657 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
658 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
659 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
660 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
661 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
663 /* Predicate registers. */ \
664 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
665 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
668 /* Branch registers. */ \
669 1, 0, 0, 0, 0, 0, 1, 1, \
670 /*FP RA CCV UNAT PFS LC EC */ \
671 0, 0, 1, 1, 1, 0, 0 \
675 /* Define this macro if the target machine has register windows. This C
676 expression returns the register number as seen by the called function
677 corresponding to the register number OUT as seen by the calling function.
678 Return OUT if register number OUT is not an outbound register. */
680 #define INCOMING_REGNO(OUT) \
681 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
683 /* Define this macro if the target machine has register windows. This C
684 expression returns the register number as seen by the calling function
685 corresponding to the register number IN as seen by the called function.
686 Return IN if register number IN is not an inbound register. */
688 #define OUTGOING_REGNO(IN) \
689 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
691 /* Define this macro if the target machine has register windows. This
692 C expression returns true if the register is call-saved but is in the
695 #define LOCAL_REGNO(REGNO) \
696 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
698 /* Add any extra modes needed to represent the condition code.
700 CCImode is used to mark a single predicate register instead
701 of a register pair. This is currently only used in reg_raw_mode
702 so that flow doesn't do something stupid. */
704 #define EXTRA_CC_MODES CC(CCImode, "CCI")
706 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
707 return the mode to be used for the comparison. Must be defined if
708 EXTRA_CC_MODES is defined. */
710 #define SELECT_CC_MODE(OP,X,Y) CCmode
712 /* Order of allocation of registers */
714 /* If defined, an initializer for a vector of integers, containing the numbers
715 of hard registers in the order in which GNU CC should prefer to use them
716 (from most preferred to least).
718 If this macro is not defined, registers are used lowest numbered first (all
721 One use of this macro is on machines where the highest numbered registers
722 must always be saved and the save-multiple-registers instruction supports
723 only sequences of consecutive registers. On such machines, define
724 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
725 allocatable register first. */
727 /* ??? Should the GR return value registers come before or after the rest
728 of the caller-save GRs? */
730 #define REG_ALLOC_ORDER \
732 /* Caller-saved general registers. */ \
733 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
734 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
735 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
736 R_GR (30), R_GR (31), \
737 /* Output registers. */ \
738 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
739 R_GR (126), R_GR (127), \
740 /* Caller-saved general registers, also used for return values. */ \
741 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
742 /* addl caller-saved general registers. */ \
743 R_GR (2), R_GR (3), \
744 /* Caller-saved FP registers. */ \
745 R_FR (6), R_FR (7), \
746 /* Caller-saved FP registers, used for parameters and return values. */ \
747 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
748 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
749 /* Rotating caller-saved FP registers. */ \
750 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
751 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
752 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
753 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
754 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
755 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
756 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
757 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
758 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
759 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
760 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
761 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
762 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
763 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
764 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
765 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
766 R_FR (126), R_FR (127), \
767 /* Caller-saved predicate registers. */ \
768 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
769 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
770 /* Rotating caller-saved predicate registers. */ \
771 R_PR (16), R_PR (17), \
772 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
773 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
774 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
775 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
776 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
777 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
778 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
779 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
780 /* Caller-saved branch registers. */ \
781 R_BR (6), R_BR (7), \
783 /* Stacked callee-saved general registers. */ \
784 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
785 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
786 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
787 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
788 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
789 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
790 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
791 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
792 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
793 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
794 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
795 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
796 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
798 /* Input registers. */ \
799 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
800 R_GR (118), R_GR (119), \
801 /* Callee-saved general registers. */ \
802 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
803 /* Callee-saved FP registers. */ \
804 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
805 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
806 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
807 R_FR (30), R_FR (31), \
808 /* Callee-saved predicate registers. */ \
809 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
810 /* Callee-saved branch registers. */ \
811 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
813 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
814 R_GR (109), R_GR (110), R_GR (111), \
816 /* Special general registers. */ \
817 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
818 /* Special FP registers. */ \
819 R_FR (0), R_FR (1), \
820 /* Special predicate registers. */ \
822 /* Special branch registers. */ \
824 /* Other fixed registers. */ \
825 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
826 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
830 /* How Values Fit in Registers */
832 /* A C expression for the number of consecutive hard registers, starting at
833 register number REGNO, required to hold a value of mode MODE. */
835 /* ??? We say that BImode PR values require two registers. This allows us to
836 easily store the normal and inverted values. We use CCImode to indicate
837 a single predicate register. */
839 #define HARD_REGNO_NREGS(REGNO, MODE) \
840 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
841 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
842 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
843 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
844 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
846 /* A C expression that is nonzero if it is permissible to store a value of mode
847 MODE in hard register number REGNO (or in several registers starting with
850 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
851 (FR_REGNO_P (REGNO) ? \
852 GET_MODE_CLASS (MODE) != MODE_CC && \
853 (MODE) != TImode && \
854 (MODE) != BImode && \
855 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
856 : PR_REGNO_P (REGNO) ? \
857 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
858 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
859 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
860 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
863 /* A C expression that is nonzero if it is desirable to choose register
864 allocation so as to avoid move instructions between a value of mode MODE1
865 and a value of mode MODE2.
867 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
868 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
870 /* Don't tie integer and FP modes, as that causes us to get integer registers
871 allocated for FP instructions. TFmode only supported in FP registers so
872 we can't tie it with any other modes. */
873 #define MODES_TIEABLE_P(MODE1, MODE2) \
874 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
875 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
876 && (((MODE1) == BImode) == ((MODE2) == BImode)))
878 /* Handling Leaf Functions */
880 /* A C initializer for a vector, indexed by hard register number, which
881 contains 1 for a register that is allowable in a candidate for leaf function
883 /* ??? This might be useful. */
884 /* #define LEAF_REGISTERS */
886 /* A C expression whose value is the register number to which REGNO should be
887 renumbered, when a function is treated as a leaf function. */
888 /* ??? This might be useful. */
889 /* #define LEAF_REG_REMAP(REGNO) */
892 /* Register Classes */
894 /* An enumeral type that must be defined with all the register class names as
895 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
896 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
897 which is not a register class but rather tells how many classes there
899 /* ??? When compiling without optimization, it is possible for the only use of
900 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
901 Regclass handles this case specially and does not assign any costs to the
902 pseudo. The pseudo then ends up using the last class before ALL_REGS.
903 Thus we must not let either PR_REGS or BR_REGS be the last class. The
904 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
920 #define GENERAL_REGS GR_REGS
922 /* The number of distinct register classes. */
923 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
925 /* An initializer containing the names of the register classes as C string
926 constants. These names are used in writing some of the debugging dumps. */
927 #define REG_CLASS_NAMES \
928 { "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_REGS", \
929 "GR_AND_FR_REGS", "AR_M_REGS", "AR_I_REGS", "ALL_REGS" }
931 /* An initializer containing the contents of the register classes, as integers
932 which are bit masks. The Nth integer specifies the contents of class N.
933 The way the integer MASK is interpreted is that register R is in the class
934 if `MASK & (1 << R)' is 1. */
935 #define REG_CLASS_CONTENTS \
938 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
939 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
940 0x00000000, 0x00000000, 0x0000 }, \
942 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
943 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
944 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
946 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
947 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
948 0x00000000, 0x00000000, 0x00FF }, \
950 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
951 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
952 0x00000000, 0x00000000, 0x0000 }, \
954 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
955 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
956 0x00000000, 0x00000000, 0x0300 }, \
958 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
959 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
960 0x00000000, 0x00000000, 0x0000 }, \
961 /* GR_AND_FR_REGS. */ \
962 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
963 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
964 0x00000000, 0x00000000, 0x0300 }, \
966 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
967 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
968 0x00000000, 0x00000000, 0x0C00 }, \
970 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
971 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
972 0x00000000, 0x00000000, 0x7000 }, \
974 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
975 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
976 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
979 /* A C expression whose value is a register class containing hard register
980 REGNO. In general there is more than one such class; choose a class which
981 is "minimal", meaning that no smaller class also contains the register. */
982 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
983 may call here with private (invalid) register numbers, such as
985 #define REGNO_REG_CLASS(REGNO) \
986 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
987 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
988 : FR_REGNO_P (REGNO) ? FR_REGS \
989 : PR_REGNO_P (REGNO) ? PR_REGS \
990 : BR_REGNO_P (REGNO) ? BR_REGS \
991 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
992 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
995 /* A macro whose definition is the name of the class to which a valid base
996 register must belong. A base register is one used in an address which is
997 the register value plus a displacement. */
998 #define BASE_REG_CLASS GENERAL_REGS
1000 /* A macro whose definition is the name of the class to which a valid index
1001 register must belong. An index register is one used in an address where its
1002 value is either multiplied by a scale factor or added to another register
1003 (as well as added to a displacement). This is needed for POST_MODIFY. */
1004 #define INDEX_REG_CLASS GENERAL_REGS
1006 /* A C expression which defines the machine-dependent operand constraint
1007 letters for register classes. If CHAR is such a letter, the value should be
1008 the register class corresponding to it. Otherwise, the value should be
1009 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
1010 will not be passed to this macro; you do not need to handle it. */
1012 #define REG_CLASS_FROM_LETTER(CHAR) \
1013 ((CHAR) == 'f' ? FR_REGS \
1014 : (CHAR) == 'a' ? ADDL_REGS \
1015 : (CHAR) == 'b' ? BR_REGS \
1016 : (CHAR) == 'c' ? PR_REGS \
1017 : (CHAR) == 'd' ? AR_M_REGS \
1018 : (CHAR) == 'e' ? AR_I_REGS \
1021 /* A C expression which is nonzero if register number NUM is suitable for use
1022 as a base register in operand addresses. It may be either a suitable hard
1023 register or a pseudo register that has been allocated such a hard reg. */
1024 #define REGNO_OK_FOR_BASE_P(REGNO) \
1025 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
1027 /* A C expression which is nonzero if register number NUM is suitable for use
1028 as an index register in operand addresses. It may be either a suitable hard
1029 register or a pseudo register that has been allocated such a hard reg.
1030 This is needed for POST_MODIFY. */
1031 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
1033 /* A C expression that places additional restrictions on the register class to
1034 use when it is necessary to copy value X into a register in class CLASS.
1035 The value is a register class; perhaps CLASS, or perhaps another, smaller
1038 /* Don't allow volatile mem reloads into floating point registers. This
1039 is defined to force reload to choose the r/m case instead of the f/f case
1040 when reloading (set (reg fX) (mem/v)).
1042 Do not reload expressions into AR regs. */
1044 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1045 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
1046 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
1047 : GET_RTX_CLASS (GET_CODE (X)) != 'o' && CLASS > GR_AND_FR_REGS ? NO_REGS \
1050 /* You should define this macro to indicate to the reload phase that it may
1051 need to allocate at least one register for a reload in addition to the
1052 register to contain the data. Specifically, if copying X to a register
1053 CLASS in MODE requires an intermediate register, you should define this
1054 to return the largest register class all of whose registers can be used
1055 as intermediate registers or scratch registers. */
1057 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
1058 ia64_secondary_reload_class (CLASS, MODE, X)
1060 /* Certain machines have the property that some registers cannot be copied to
1061 some other registers without using memory. Define this macro on those
1062 machines to be a C expression that is non-zero if objects of mode M in
1063 registers of CLASS1 can only be copied to registers of class CLASS2 by
1064 storing a register of CLASS1 into memory and loading that memory location
1065 into a register of CLASS2. */
1068 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
1069 I'm not quite sure how it could be invoked. The normal problems
1070 with unions should be solved with the addressof fiddling done by
1071 movtf and friends. */
1072 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1073 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
1074 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1077 /* A C expression for the maximum number of consecutive registers of
1078 class CLASS needed to hold a value of mode MODE.
1079 This is closely related to the macro `HARD_REGNO_NREGS'. */
1081 #define CLASS_MAX_NREGS(CLASS, MODE) \
1082 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1083 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
1084 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1086 /* If defined, gives a class of registers that cannot be used as the
1087 operand of a SUBREG that changes the mode of the object illegally. */
1089 #define CLASS_CANNOT_CHANGE_MODE FR_REGS
1091 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
1092 In FP regs, we can't change FP values to integer values and vice
1093 versa, but we can change e.g. DImode to SImode. */
1095 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1096 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO))
1098 /* A C expression that defines the machine-dependent operand constraint
1099 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1102 /* 14 bit signed immediate for arithmetic instructions. */
1103 #define CONST_OK_FOR_I(VALUE) \
1104 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1105 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1106 #define CONST_OK_FOR_J(VALUE) \
1107 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1108 /* 8 bit signed immediate for logical instructions. */
1109 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1110 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1111 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1112 /* 6 bit unsigned immediate for shift counts. */
1113 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1114 /* 9 bit signed immediate for load/store post-increments. */
1115 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1116 /* 0 for r0. Used by Linux kernel, do not change. */
1117 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1118 /* 0 or -1 for dep instruction. */
1119 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1121 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1122 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1123 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1124 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1125 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1126 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1127 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1128 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1129 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1132 /* A C expression that defines the machine-dependent operand constraint letters
1133 (`G', `H') that specify particular ranges of `const_double' values. */
1135 /* 0.0 and 1.0 for fr0 and fr1. */
1136 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1137 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1138 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1140 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1141 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1143 /* A C expression that defines the optional machine-dependent constraint
1144 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1145 types of operands, usually memory references, for the target machine. */
1147 /* Non-volatile memory for FP_REG loads/stores. */
1148 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1149 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1150 /* 1..4 for shladd arguments. */
1151 #define CONSTRAINT_OK_FOR_R(VALUE) \
1152 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1153 /* Non-post-inc memory for asms and other unsavory creatures. */
1154 #define CONSTRAINT_OK_FOR_S(VALUE) \
1155 (GET_CODE (VALUE) == MEM \
1156 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1157 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1159 #define EXTRA_CONSTRAINT(VALUE, C) \
1160 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1161 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1162 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1165 /* Basic Stack Layout */
1167 /* Define this macro if pushing a word onto the stack moves the stack pointer
1168 to a smaller address. */
1169 #define STACK_GROWS_DOWNWARD 1
1171 /* Define this macro if the addresses of local variable slots are at negative
1172 offsets from the frame pointer. */
1173 /* #define FRAME_GROWS_DOWNWARD */
1175 /* Offset from the frame pointer to the first local variable slot to
1177 #define STARTING_FRAME_OFFSET 0
1179 /* Offset from the stack pointer register to the first location at which
1180 outgoing arguments are placed. If not specified, the default value of zero
1181 is used. This is the proper value for most machines. */
1182 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1183 #define STACK_POINTER_OFFSET 16
1185 /* Offset from the argument pointer register to the first argument's address.
1186 On some machines it may depend on the data type of the function. */
1187 #define FIRST_PARM_OFFSET(FUNDECL) 0
1189 /* A C expression whose value is RTL representing the value of the return
1190 address for the frame COUNT steps up from the current frame, after the
1193 /* ??? Frames other than zero would likely require interpreting the frame
1194 unwind info, so we don't try to support them. We would also need to define
1195 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1197 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1198 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1200 /* A C expression whose value is RTL representing the location of the incoming
1201 return address at the beginning of any function, before the prologue. This
1202 RTL is either a `REG', indicating that the return value is saved in `REG',
1203 or a `MEM' representing a location in the stack. This enables DWARF2
1204 unwind info for C++ EH. */
1205 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1207 /* ??? This is not defined because of three problems.
1208 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1209 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1210 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1211 unused register number.
1212 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1213 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1214 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1215 to zero, despite what the documentation implies, because it is tested in
1216 a few places with #ifdef instead of #if. */
1217 #undef INCOMING_RETURN_ADDR_RTX
1219 /* A C expression whose value is an integer giving the offset, in bytes, from
1220 the value of the stack pointer register to the top of the stack frame at the
1221 beginning of any function, before the prologue. The top of the frame is
1222 defined to be the value of the stack pointer in the previous frame, just
1223 before the call instruction. */
1224 #define INCOMING_FRAME_SP_OFFSET 0
1227 /* Register That Address the Stack Frame. */
1229 /* The register number of the stack pointer register, which must also be a
1230 fixed register according to `FIXED_REGISTERS'. On most machines, the
1231 hardware determines which register this is. */
1233 #define STACK_POINTER_REGNUM 12
1235 /* The register number of the frame pointer register, which is used to access
1236 automatic variables in the stack frame. On some machines, the hardware
1237 determines which register this is. On other machines, you can choose any
1238 register you wish for this purpose. */
1240 #define FRAME_POINTER_REGNUM 328
1242 /* Base register for access to local variables of the function. */
1243 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1245 /* The register number of the arg pointer register, which is used to access the
1246 function's argument list. */
1247 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1249 #define ARG_POINTER_REGNUM R_GR(0)
1251 /* The register number for the return address register. For IA-64, this
1252 is not actually a pointer as the name suggests, but that's a name that
1253 gen_rtx_REG already takes care to keep unique. We modify
1254 return_address_pointer_rtx in ia64_expand_prologue to reference the
1255 final output regnum. */
1256 #define RETURN_ADDRESS_POINTER_REGNUM 329
1258 /* Register numbers used for passing a function's static chain pointer. */
1259 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1260 #define STATIC_CHAIN_REGNUM 15
1262 /* Eliminating the Frame Pointer and the Arg Pointer */
1264 /* A C expression which is nonzero if a function must have and use a frame
1265 pointer. This expression is evaluated in the reload pass. If its value is
1266 nonzero the function will have a frame pointer. */
1267 #define FRAME_POINTER_REQUIRED 0
1269 /* Show we can debug even without a frame pointer. */
1270 #define CAN_DEBUG_WITHOUT_FP
1272 /* If defined, this macro specifies a table of register pairs used to eliminate
1273 unneeded registers that point into the stack frame. */
1275 #define ELIMINABLE_REGS \
1277 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1278 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1279 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1280 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1281 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1284 /* A C expression that returns non-zero if the compiler is allowed to try to
1285 replace register number FROM with register number TO. The frame pointer
1286 is automatically handled. */
1288 #define CAN_ELIMINATE(FROM, TO) \
1289 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1291 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1292 specifies the initial difference between the specified pair of
1293 registers. This macro must be defined if `ELIMINABLE_REGS' is
1295 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1296 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1298 /* Passing Function Arguments on the Stack */
1300 /* Define this macro if an argument declared in a prototype as an integral type
1301 smaller than `int' should actually be passed as an `int'. In addition to
1302 avoiding errors in certain cases of mismatch, it also makes for better code
1303 on certain machines. */
1304 /* ??? Investigate. */
1305 /* #define PROMOTE_PROTOTYPES */
1307 /* If defined, the maximum amount of space required for outgoing arguments will
1308 be computed and placed into the variable
1309 `current_function_outgoing_args_size'. */
1311 #define ACCUMULATE_OUTGOING_ARGS 1
1313 /* A C expression that should indicate the number of bytes of its own arguments
1314 that a function pops on returning, or 0 if the function pops no arguments
1315 and the caller must therefore pop them all after the function returns. */
1317 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1320 /* Function Arguments in Registers */
1322 #define MAX_ARGUMENT_SLOTS 8
1323 #define MAX_INT_RETURN_SLOTS 4
1324 #define GR_ARG_FIRST IN_REG (0)
1325 #define GR_RET_FIRST GR_REG (8)
1326 #define GR_RET_LAST GR_REG (11)
1327 #define FR_ARG_FIRST FR_REG (8)
1328 #define FR_RET_FIRST FR_REG (8)
1329 #define FR_RET_LAST FR_REG (15)
1330 #define AR_ARG_FIRST OUT_REG (0)
1332 /* A C expression that controls whether a function argument is passed in a
1333 register, and which register. */
1335 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1336 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1338 /* Define this macro if the target machine has "register windows", so that the
1339 register in which a function sees an arguments is not necessarily the same
1340 as the one in which the caller passed the argument. */
1342 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1343 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1345 /* A C expression for the number of words, at the beginning of an argument,
1346 must be put in registers. The value must be zero for arguments that are
1347 passed entirely in registers or that are entirely pushed on the stack. */
1349 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1350 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1352 /* A C expression that indicates when an argument must be passed by reference.
1353 If nonzero for an argument, a copy of that argument is made in memory and a
1354 pointer to the argument is passed instead of the argument itself. The
1355 pointer is passed in whatever way is appropriate for passing a pointer to
1358 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1360 /* A C type for declaring a variable that is used as the first argument of
1361 `FUNCTION_ARG' and other related values. For some target machines, the type
1362 `int' suffices and can hold the number of bytes of argument so far. */
1364 typedef struct ia64_args
1366 int words; /* # words of arguments so far */
1367 int fp_regs; /* # FR registers used so far */
1368 int prototype; /* whether function prototyped */
1371 /* A C statement (sans semicolon) for initializing the variable CUM for the
1372 state at the beginning of the argument list. */
1374 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1377 (CUM).fp_regs = 0; \
1378 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1381 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1382 arguments for the function being compiled. If this macro is undefined,
1383 `INIT_CUMULATIVE_ARGS' is used instead. */
1385 /* We set prototype to true so that we never try to return a PARALLEL from
1387 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1390 (CUM).fp_regs = 0; \
1391 (CUM).prototype = 1; \
1394 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1395 advance past an argument in the argument list. The values MODE, TYPE and
1396 NAMED describe that argument. Once this is done, the variable CUM is
1397 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1399 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1400 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1402 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1403 argument with the specified mode and type. */
1405 /* Arguments with alignment larger than 8 bytes start at the next even
1406 boundary. See ia64_function_arg. */
1408 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1409 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1410 : (((((MODE) == BLKmode \
1411 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1412 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1413 ? 128 : PARM_BOUNDARY)
1415 /* A C expression that is nonzero if REGNO is the number of a hard register in
1416 which function arguments are sometimes passed. This does *not* include
1417 implicit arguments such as the static chain and the structure-value address.
1418 On many machines, no registers can be used for this purpose since all
1419 function arguments are pushed on the stack. */
1420 #define FUNCTION_ARG_REGNO_P(REGNO) \
1421 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1422 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1424 /* Implement `va_start' for varargs and stdarg. */
1425 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1426 ia64_va_start (stdarg, valist, nextarg)
1428 /* Implement `va_arg'. */
1429 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1430 ia64_va_arg (valist, type)
1432 /* How Scalar Function Values are Returned */
1434 /* A C expression to create an RTX representing the place where a function
1435 returns a value of data type VALTYPE. */
1437 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1438 ia64_function_value (VALTYPE, FUNC)
1440 /* A C expression to create an RTX representing the place where a library
1441 function returns a value of mode MODE. */
1443 #define LIBCALL_VALUE(MODE) \
1444 gen_rtx_REG (MODE, \
1445 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1446 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1447 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1448 ? FR_RET_FIRST : GR_RET_FIRST))
1450 /* A C expression that is nonzero if REGNO is the number of a hard register in
1451 which the values of called function may come back. */
1453 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1454 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1455 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1458 /* How Large Values are Returned */
1460 /* A nonzero value says to return the function value in memory, just as large
1461 structures are always returned. */
1463 #define RETURN_IN_MEMORY(TYPE) \
1464 ia64_return_in_memory (TYPE)
1466 /* If you define this macro to be 0, then the conventions used for structure
1467 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1469 #define DEFAULT_PCC_STRUCT_RETURN 0
1471 /* If the structure value address is passed in a register, then
1472 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1474 #define STRUCT_VALUE_REGNUM GR_REG (8)
1477 /* Caller-Saves Register Allocation */
1479 /* A C expression to determine whether it is worthwhile to consider placing a
1480 pseudo-register in a call-clobbered hard register and saving and restoring
1481 it around each function call. The expression should be 1 when this is worth
1482 doing, and 0 otherwise.
1484 If you don't define this macro, a default is used which is good on most
1485 machines: `4 * CALLS < REFS'. */
1486 /* ??? Investigate. */
1487 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1490 /* Function Entry and Exit */
1492 /* Define this macro as a C expression that is nonzero if the return
1493 instruction or the function epilogue ignores the value of the stack pointer;
1494 in other words, if it is safe to delete an instruction to adjust the stack
1495 pointer before a return from the function. */
1497 #define EXIT_IGNORE_STACK 1
1499 /* Define this macro as a C expression that is nonzero for registers
1500 used by the epilogue or the `return' pattern. */
1502 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1504 /* Output at beginning of assembler file. */
1506 #define ASM_FILE_START(FILE) \
1507 emit_safe_across_calls (FILE)
1509 /* A C compound statement that outputs the assembler code for a thunk function,
1510 used to implement C++ virtual function calls with multiple inheritance. */
1512 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1514 if (CONST_OK_FOR_I (DELTA)) \
1515 fprintf (FILE, "\tadds r32 = %d, r32\n", (DELTA)); \
1518 if (CONST_OK_FOR_J (DELTA)) \
1519 fprintf (FILE, "\taddl r2 = %d, r0\n", (DELTA)); \
1521 fprintf (FILE, "\tmovl r2 = %d\n", (DELTA)); \
1522 fprintf (FILE, "\t;;\n"); \
1523 fprintf (FILE, "\tadd r32 = r2, r32\n"); \
1525 fprintf (FILE, "\tbr "); \
1526 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1527 fprintf (FILE, "\n"); \
1531 /* Generating Code for Profiling. */
1533 /* A C statement or compound statement to output to FILE some assembler code to
1534 call the profiling subroutine `mcount'. */
1536 /* ??? Unclear if this will actually work. No way to test this currently. */
1538 #define FUNCTION_PROFILER(FILE, LABELNO) \
1541 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1542 fputs ("\taddl r16 = @ltoff(", FILE); \
1543 assemble_name (FILE, buf); \
1544 fputs ("), gp\n", FILE); \
1545 fputs ("\tmov r17 = r1;;\n", FILE); \
1546 fputs ("\tld8 out0 = [r16]\n", FILE); \
1547 fputs ("\tmov r18 = b0\n", FILE); \
1548 fputs ("\tbr.call.sptk.many rp = mcount;;\n", FILE); \
1549 fputs ("\tmov b0 = r18\n", FILE); \
1550 fputs ("\tmov r1 = r17;;\n", FILE); \
1553 /* A C statement or compound statement to output to FILE some assembler code to
1554 initialize basic-block profiling for the current object module. */
1556 /* ??? Unclear if this will actually work. No way to test this currently. */
1558 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1560 int labelno = LABELNO; \
1561 switch (profile_block_flag) \
1564 fputs ("\taddl r16 = @ltoff(LPBX0), gp\n", FILE); \
1565 fprintf (FILE, "\tmov out1 = %d;;\n", labelno); \
1566 fputs ("\tld8 out0 = [r16]\n", FILE); \
1567 fputs ("\tmov r17 = r1\n", FILE); \
1568 fputs ("\tmov r18 = b0\n", FILE); \
1569 fputs ("\tbr.call.sptk.many rp = __bb_init_trace_func;;\n", FILE);\
1570 fputs ("\tmov r1 = r17\n", FILE); \
1571 fputs ("\tmov b0 = r18;;\n", FILE); \
1574 fputs ("\taddl r16 = @ltoff(LPBX0), gp;;\n", FILE); \
1575 fputs ("\tld8 out0 = [r16];;\n", FILE); \
1576 fputs ("\tld8 r17 = [out0];;\n", FILE); \
1577 fputs ("\tcmp.eq p6, p0 = r0, r17;;\n", FILE); \
1578 fputs ("(p6)\tmov r16 = r1\n", FILE); \
1579 fputs ("(p6)\tmov r17 = b0\n", FILE); \
1580 fputs ("(p6)\tbr.call.sptk.many rp = __bb_init_func;;\n", FILE); \
1581 fputs ("(p6)\tmov r1 = r16\n", FILE); \
1582 fputs ("(p6)\tmov b0 = r17;;\n", FILE); \
1587 /* A C statement or compound statement to output to FILE some assembler code to
1588 increment the count associated with the basic block number BLOCKNO. */
1590 /* ??? This can't work unless we mark some registers as fixed, so that we
1591 can use them as temporaries in this macro. We need two registers for -a
1592 profiling and 4 registers for -ax profiling. */
1594 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1596 int blockn = BLOCKNO; \
1597 switch (profile_block_flag) \
1600 fputs ("\taddl r2 = @ltoff(__bb), gp\n", FILE); \
1601 fputs ("\taddl r3 = @ltoff(LPBX0), gp;;\n", FILE); \
1602 fprintf (FILE, "\tmov r9 = %d\n", blockn); \
1603 fputs ("\tld8 r2 = [r2]\n", FILE); \
1604 fputs ("\tld8 r3 = [r3];;\n", FILE); \
1605 fputs ("\tadd r8 = 8, r2\n", FILE); \
1606 fputs ("\tst8 [r2] = r9;;\n", FILE); \
1607 fputs ("\tst8 [r8] = r3\n", FILE); \
1608 fputs ("\tbr.call.sptk.many rp = __bb_trace_func\n", FILE); \
1612 fputs ("\taddl r2 = @ltoff(LPBX2), gp;;\n", FILE); \
1613 fputs ("\tld8 r2 = [r2];;\n", FILE); \
1614 fprintf (FILE, "\taddl r2 = %d, r2;;\n", 8 * blockn); \
1615 fputs ("\tld8 r3 = [r2];;\n", FILE); \
1616 fputs ("\tadd r3 = 1, r3;;\n", FILE); \
1617 fputs ("\tst8 [r2] = r3;;\n", FILE); \
1622 /* A C statement or compound statement to output to FILE assembler
1623 code to call function `__bb_trace_ret'. */
1625 /* ??? Unclear if this will actually work. No way to test this currently. */
1627 /* ??? This needs to be emitted into the epilogue. Perhaps rewrite to emit
1628 rtl and call from ia64_expand_epilogue? */
1630 #define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
1631 fputs ("\tbr.call.sptk.many rp = __bb_trace_ret\n", FILE);
1632 #undef FUNCTION_BLOCK_PROFILER_EXIT
1634 /* A C statement or compound statement to save all registers, which may be
1635 clobbered by a function call, including condition codes. */
1637 /* ??? We would have to save 20 GRs, 106 FRs, 10 PRs, 2 BRs, and possibly
1638 other things. This is not practical. Perhaps leave this feature (-ax)
1639 unsupported by undefining above macros? */
1641 /* #define MACHINE_STATE_SAVE(ID) */
1643 /* A C statement or compound statement to restore all registers, including
1644 condition codes, saved by `MACHINE_STATE_SAVE'. */
1646 /* ??? We would have to restore 20 GRs, 106 FRs, 10 PRs, 2 BRs, and possibly
1647 other things. This is not practical. Perhaps leave this feature (-ax)
1648 unsupported by undefining above macros? */
1650 /* #define MACHINE_STATE_RESTORE(ID) */
1653 /* Implementing the Varargs Macros. */
1655 /* Define this macro to store the anonymous register arguments into the stack
1656 so that all the arguments appear to have been passed consecutively on the
1659 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1660 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1662 /* Define this macro if the location where a function argument is passed
1663 depends on whether or not it is a named argument. */
1665 #define STRICT_ARGUMENT_NAMING 1
1668 /* Trampolines for Nested Functions. */
1670 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1671 the function containing a non-local goto target. */
1673 #define STACK_SAVEAREA_MODE(LEVEL) \
1674 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1676 /* Output assembler code for a block containing the constant parts of
1677 a trampoline, leaving space for the variable parts.
1679 The trampoline should set the static chain pointer to value placed
1680 into the trampoline and should branch to the specified routine.
1681 To make the normal indirect-subroutine calling convention work,
1682 the trampoline must look like a function descriptor; the first
1683 word being the target address and the second being the target's
1686 We abuse the concept of a global pointer by arranging for it
1687 to point to the data we need to load. The complete trampoline
1688 has the following form:
1690 +-------------------+ \
1691 TRAMP: | __ia64_trampoline | |
1692 +-------------------+ > fake function descriptor
1694 +-------------------+ /
1695 | target descriptor |
1696 +-------------------+
1698 +-------------------+
1701 /* A C expression for the size in bytes of the trampoline, as an integer. */
1703 #define TRAMPOLINE_SIZE 32
1705 /* Alignment required for trampolines, in bits. */
1707 #define TRAMPOLINE_ALIGNMENT 64
1709 /* A C statement to initialize the variable parts of a trampoline. */
1711 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1712 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1714 /* Implicit Calls to Library Routines */
1716 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1717 C) library functions `memcpy' and `memset' rather than the BSD functions
1718 `bcopy' and `bzero'. */
1720 #define TARGET_MEM_FUNCTIONS
1723 /* Addressing Modes */
1725 /* Define this macro if the machine supports post-increment addressing. */
1727 #define HAVE_POST_INCREMENT 1
1728 #define HAVE_POST_DECREMENT 1
1729 #define HAVE_POST_MODIFY_DISP 1
1730 #define HAVE_POST_MODIFY_REG 1
1732 /* A C expression that is 1 if the RTX X is a constant which is a valid
1735 #define CONSTANT_ADDRESS_P(X) 0
1737 /* The max number of registers that can appear in a valid memory address. */
1739 #define MAX_REGS_PER_ADDRESS 2
1741 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1742 RTX) is a legitimate memory address on the target machine for a memory
1743 operand of mode MODE. */
1745 #define LEGITIMATE_ADDRESS_REG(X) \
1746 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1747 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1748 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1750 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1751 (GET_CODE (X) == PLUS \
1752 && rtx_equal_p (R, XEXP (X, 0)) \
1753 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1754 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1755 && INTVAL (XEXP (X, 1)) >= -256 \
1756 && INTVAL (XEXP (X, 1)) < 256)))
1758 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1760 if (LEGITIMATE_ADDRESS_REG (X)) \
1762 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1763 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1764 && XEXP (X, 0) != arg_pointer_rtx) \
1766 else if (GET_CODE (X) == POST_MODIFY \
1767 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1768 && XEXP (X, 0) != arg_pointer_rtx \
1769 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1773 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1774 use as a base register. */
1776 #ifdef REG_OK_STRICT
1777 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1779 #define REG_OK_FOR_BASE_P(X) \
1780 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1783 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1784 use as an index register. This is needed for POST_MODIFY. */
1786 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1788 /* A C compound statement that attempts to replace X with a valid memory
1789 address for an operand of mode MODE.
1791 This must be present, but there is nothing useful to be done here. */
1793 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1795 /* A C statement or compound statement with a conditional `goto LABEL;'
1796 executed if memory address X (an RTX) can have different meanings depending
1797 on the machine mode of the memory reference it is used for or if the address
1798 is valid for some modes but not others. */
1800 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1801 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1804 /* A C expression that is nonzero if X is a legitimate constant for an
1805 immediate operand on the target machine. */
1807 #define LEGITIMATE_CONSTANT_P(X) \
1808 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1809 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1812 /* Condition Code Status */
1814 /* One some machines not all possible comparisons are defined, but you can
1815 convert an invalid comparison into a valid one. */
1816 /* ??? Investigate. See the alpha definition. */
1817 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1820 /* Describing Relative Costs of Operations */
1822 /* A part of a C `switch' statement that describes the relative costs of
1823 constant RTL expressions. */
1825 /* ??? This is incomplete. */
1827 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1829 if ((X) == const0_rtx) \
1831 switch (OUTER_CODE) \
1834 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
1836 if (CONST_OK_FOR_I (INTVAL (X))) \
1838 if (CONST_OK_FOR_J (INTVAL (X))) \
1840 return COSTS_N_INSNS (1); \
1842 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
1844 return COSTS_N_INSNS (1); \
1846 case CONST_DOUBLE: \
1847 return COSTS_N_INSNS (1); \
1851 return COSTS_N_INSNS (3);
1853 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
1855 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1857 /* For multiplies wider than HImode, we have to go to the FPU, \
1858 which normally involves copies. Plus there's the latency \
1859 of the multiply itself, and the latency of the instructions to \
1860 transfer integer regs to FP regs. */ \
1861 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
1862 return COSTS_N_INSNS (10); \
1863 return COSTS_N_INSNS (2); \
1869 return COSTS_N_INSNS (1); \
1874 /* We make divide expensive, so that divide-by-constant will be \
1875 optimized to a multiply. */ \
1876 return COSTS_N_INSNS (60);
1878 /* An expression giving the cost of an addressing mode that contains ADDRESS.
1879 If not defined, the cost is computed from the ADDRESS expression and the
1880 `CONST_COSTS' values. */
1882 #define ADDRESS_COST(ADDRESS) 0
1884 /* A C expression for the cost of moving data from a register in class FROM to
1887 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1888 ia64_register_move_cost((FROM), (TO))
1890 /* A C expression for the cost of moving data of mode M between a
1891 register and memory. */
1892 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1893 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS ? 4 : 10)
1895 /* A C expression for the cost of a branch instruction. A value of 1 is the
1896 default; other values are interpreted relative to that. Used by the
1897 if-conversion code as max instruction count. */
1898 /* ??? This requires investigation. The primary effect might be how
1899 many additional insn groups we run into, vs how good the dynamic
1900 branch predictor is. */
1902 #define BRANCH_COST 6
1904 /* Define this macro as a C expression which is nonzero if accessing less than
1905 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1908 #define SLOW_BYTE_ACCESS 1
1910 /* Define this macro if it is as good or better to call a constant function
1911 address than to call an address kept in a register.
1913 Indirect function calls are more expensive that direct function calls, so
1914 don't cse function addresses. */
1916 #define NO_FUNCTION_CSE
1919 /* Dividing the output into sections. */
1921 /* A C expression whose value is a string containing the assembler operation
1922 that should precede instructions and read-only data. */
1924 #define TEXT_SECTION_ASM_OP "\t.text"
1926 /* A C expression whose value is a string containing the assembler operation to
1927 identify the following data as writable initialized data. */
1929 #define DATA_SECTION_ASM_OP "\t.data"
1931 /* If defined, a C expression whose value is a string containing the assembler
1932 operation to identify the following data as uninitialized global data. */
1934 #define BSS_SECTION_ASM_OP "\t.bss"
1936 /* Define this macro if jump tables (for `tablejump' insns) should be output in
1937 the text section, along with the assembler instructions. */
1939 /* ??? It is probably better for the jump tables to be in the rodata section,
1940 which is where they go by default. Unfortunately, that currently does not
1941 work, because of some problem with pcrelative relocations not getting
1942 resolved correctly. */
1943 /* ??? FIXME ??? rth says that we should use @gprel to solve this problem. */
1944 /* ??? If jump tables are in the text section, then we can use 4 byte
1945 entries instead of 8 byte entries. */
1947 #define JUMP_TABLES_IN_TEXT_SECTION 1
1949 /* Define this macro if references to a symbol must be treated differently
1950 depending on something about the variable or function named by the symbol
1951 (such as what section it is in). */
1953 #define ENCODE_SECTION_INFO(DECL) ia64_encode_section_info (DECL)
1955 /* If a variable is weakened, made one only or moved into a different
1956 section, it may be necessary to redo the section info to move the
1957 variable out of sdata. */
1959 #define REDO_SECTION_INFO_P(DECL) \
1960 ((TREE_CODE (DECL) == VAR_DECL) \
1961 && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \
1962 || DECL_SECTION_NAME (DECL) != 0))
1964 #define SDATA_NAME_FLAG_CHAR '@'
1966 #define IA64_DEFAULT_GVALUE 8
1968 /* Decode SYM_NAME and store the real name part in VAR, sans the characters
1969 that encode section info. */
1971 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1972 (VAR) = ((SYMBOL_NAME) \
1973 + (*(SYMBOL_NAME) == '*' || *(SYMBOL_NAME) == SDATA_NAME_FLAG_CHAR))
1977 /* Position Independent Code. */
1979 /* The register number of the register used to address a table of static data
1980 addresses in memory. */
1982 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1983 gen_rtx_REG (DImode, 1). */
1985 /* ??? Should we set flag_pic? Probably need to define
1986 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1988 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1990 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1991 clobbered by calls. */
1993 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1996 /* The Overall Framework of an Assembler File. */
1998 /* A C string constant describing how to begin a comment in the target
1999 assembler language. The compiler assumes that the comment will end at the
2002 #define ASM_COMMENT_START "//"
2004 /* A C string constant for text to be output before each `asm' statement or
2005 group of consecutive ones. */
2007 /* ??? This won't work with the Intel assembler, because it does not accept
2008 # as a comment start character. However, //APP does not work in gas, so we
2009 can't use that either. Same problem for ASM_APP_OFF below. */
2011 #define ASM_APP_ON "#APP\n"
2013 /* A C string constant for text to be output after each `asm' statement or
2014 group of consecutive ones. */
2016 #define ASM_APP_OFF "#NO_APP\n"
2019 /* Output of Data. */
2021 /* A C statement to output to the stdio stream STREAM an assembler instruction
2022 to assemble a floating-point constant of `TFmode', `DFmode', `SFmode',
2023 respectively, whose value is VALUE. */
2025 /* ??? Must reverse the word order for big-endian code? */
2027 #define ASM_OUTPUT_LONG_DOUBLE(FILE, VALUE) \
2030 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, t); \
2031 fprintf (FILE, "\tdata4 0x%08lx, 0x%08lx, 0x%08lx, 0x%08lx\n", \
2032 t[0] & 0xffffffff, t[1] & 0xffffffff, t[2] & 0xffffffff, 0L);\
2035 /* ??? Must reverse the word order for big-endian code? */
2037 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2040 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, t); \
2041 fprintf (FILE, "\tdata8 0x%08lx%08lx\n", \
2042 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2045 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2048 REAL_VALUE_TO_TARGET_SINGLE (VALUE, t); \
2049 fprintf (FILE, "\tdata4 0x%lx\n", t & 0xffffffff); \
2052 /* A C statement to output to the stdio stream STREAM an assembler instruction
2053 to assemble an integer of 1, 2, 4, or 8 bytes, respectively, whose value
2056 /* This is how to output an assembler line defining a `char' constant. */
2058 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
2060 fprintf (FILE, "%s", ASM_BYTE_OP); \
2061 output_addr_const (FILE, (VALUE)); \
2062 fprintf (FILE, "\n"); \
2065 /* This is how to output an assembler line defining a `short' constant. */
2067 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
2069 fprintf (FILE, "\tdata2\t"); \
2070 output_addr_const (FILE, (VALUE)); \
2071 fprintf (FILE, "\n"); \
2074 /* This is how to output an assembler line defining an `int' constant.
2075 We also handle symbol output here. */
2077 /* ??? For ILP32, also need to handle function addresses here. */
2079 #define ASM_OUTPUT_INT(FILE, VALUE) \
2081 fprintf (FILE, "\tdata4\t"); \
2082 output_addr_const (FILE, (VALUE)); \
2083 fprintf (FILE, "\n"); \
2086 /* This is how to output an assembler line defining a `long' constant.
2087 We also handle symbol output here. */
2089 #define ASM_OUTPUT_DOUBLE_INT(FILE, VALUE) \
2091 fprintf (FILE, "\tdata8\t"); \
2092 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
2093 fprintf (FILE, "@fptr("); \
2094 output_addr_const (FILE, (VALUE)); \
2095 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
2096 fprintf (FILE, ")"); \
2097 fprintf (FILE, "\n"); \
2100 /* This is how to output an assembler line defining a `char' constant
2101 to an xdata segment. */
2103 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
2105 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
2106 output_addr_const (FILE, (VALUE)); \
2107 fprintf (FILE, "\n"); \
2110 /* This is how to output an assembler line defining a `short' constant
2111 to an xdata segment. */
2113 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
2115 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
2116 output_addr_const (FILE, (VALUE)); \
2117 fprintf (FILE, "\n"); \
2120 /* This is how to output an assembler line defining an `int' constant
2121 to an xdata segment. We also handle symbol output here. */
2123 /* ??? For ILP32, also need to handle function addresses here. */
2125 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
2127 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
2128 output_addr_const (FILE, (VALUE)); \
2129 fprintf (FILE, "\n"); \
2132 /* This is how to output an assembler line defining a `long' constant
2133 to an xdata segment. We also handle symbol output here. */
2135 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
2137 int need_closing_paren = 0; \
2138 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
2139 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
2140 && GET_CODE (VALUE) == SYMBOL_REF) \
2142 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
2143 need_closing_paren = 1; \
2145 output_addr_const (FILE, VALUE); \
2146 if (need_closing_paren) \
2147 fprintf (FILE, ")"); \
2148 fprintf (FILE, "\n"); \
2152 /* A C statement to output to the stdio stream STREAM an assembler instruction
2153 to assemble a single byte containing the number VALUE. */
2155 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
2156 fprintf (STREAM, "%s0x%x\n", ASM_BYTE_OP, (int)(VALUE) & 0xff)
2159 /* Output of Uninitialized Variables. */
2161 /* This is all handled by svr4.h. */
2164 /* Output and Generation of Labels. */
2166 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
2167 assembler definition of a label named NAME. */
2169 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
2170 why ia64_asm_output_label exists. */
2172 extern int ia64_asm_output_label;
2173 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
2175 ia64_asm_output_label = 1; \
2176 assemble_name (STREAM, NAME); \
2177 fputs (":\n", STREAM); \
2178 ia64_asm_output_label = 0; \
2181 /* A C statement (sans semicolon) to output to the stdio stream STREAM some
2182 commands that will make the label NAME global; that is, available for
2183 reference from other files. */
2185 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2187 fputs ("\t.global ", STREAM); \
2188 assemble_name (STREAM, NAME); \
2189 fputs ("\n", STREAM); \
2192 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
2193 necessary for declaring the name of an external symbol named NAME which is
2194 referenced in this compilation but not defined. */
2196 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2197 ia64_asm_output_external (FILE, DECL, NAME)
2199 /* A C statement to store into the string STRING a label whose name is made
2200 from the string PREFIX and the number NUM. */
2202 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
2204 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
2207 /* A C expression to assign to OUTVAR (which is a variable of type `char *') a
2208 newly allocated string made from the string NAME and the number NUMBER, with
2209 some suitable punctuation added. */
2211 /* ??? Not sure if using a ? in the name for Intel as is safe. */
2213 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
2215 (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \
2216 sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \
2220 /* A C statement to output to the stdio stream STREAM assembler code which
2221 defines (equates) the symbol NAME to have the value VALUE. */
2223 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
2225 assemble_name (STREAM, NAME); \
2226 fputs (" = ", STREAM); \
2227 assemble_name (STREAM, VALUE); \
2228 fputc ('\n', STREAM); \
2232 /* Macros Controlling Initialization Routines. */
2234 /* This is handled by svr4.h and sysv4.h. */
2237 /* Output of Assembler Instructions. */
2239 /* A C initializer containing the assembler's names for the machine registers,
2240 each one as a C string constant. */
2242 #define REGISTER_NAMES \
2244 /* General registers. */ \
2245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
2246 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
2247 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
2249 /* Local registers. */ \
2250 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
2251 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
2252 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
2253 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
2254 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
2255 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
2256 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
2257 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
2258 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
2259 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
2260 /* Input registers. */ \
2261 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
2262 /* Output registers. */ \
2263 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
2264 /* Floating-point registers. */ \
2265 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
2266 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
2267 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
2268 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
2269 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
2270 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
2271 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
2272 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
2273 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
2274 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
2275 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
2276 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
2277 "f120","f121","f122","f123","f124","f125","f126","f127", \
2278 /* Predicate registers. */ \
2279 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
2280 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
2281 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
2282 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
2283 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
2284 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
2285 "p60", "p61", "p62", "p63", \
2286 /* Branch registers. */ \
2287 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
2288 /* Frame pointer. Return address. */ \
2289 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
2292 /* If defined, a C initializer for an array of structures containing a name and
2293 a register number. This macro defines additional names for hard registers,
2294 thus allowing the `asm' option in declarations to refer to registers using
2297 #define ADDITIONAL_REGISTER_NAMES \
2299 { "gp", R_GR (1) }, \
2300 { "sp", R_GR (12) }, \
2301 { "in0", IN_REG (0) }, \
2302 { "in1", IN_REG (1) }, \
2303 { "in2", IN_REG (2) }, \
2304 { "in3", IN_REG (3) }, \
2305 { "in4", IN_REG (4) }, \
2306 { "in5", IN_REG (5) }, \
2307 { "in6", IN_REG (6) }, \
2308 { "in7", IN_REG (7) }, \
2309 { "out0", OUT_REG (0) }, \
2310 { "out1", OUT_REG (1) }, \
2311 { "out2", OUT_REG (2) }, \
2312 { "out3", OUT_REG (3) }, \
2313 { "out4", OUT_REG (4) }, \
2314 { "out5", OUT_REG (5) }, \
2315 { "out6", OUT_REG (6) }, \
2316 { "out7", OUT_REG (7) }, \
2317 { "loc0", LOC_REG (0) }, \
2318 { "loc1", LOC_REG (1) }, \
2319 { "loc2", LOC_REG (2) }, \
2320 { "loc3", LOC_REG (3) }, \
2321 { "loc4", LOC_REG (4) }, \
2322 { "loc5", LOC_REG (5) }, \
2323 { "loc6", LOC_REG (6) }, \
2324 { "loc7", LOC_REG (7) }, \
2325 { "loc8", LOC_REG (8) }, \
2326 { "loc9", LOC_REG (9) }, \
2327 { "loc10", LOC_REG (10) }, \
2328 { "loc11", LOC_REG (11) }, \
2329 { "loc12", LOC_REG (12) }, \
2330 { "loc13", LOC_REG (13) }, \
2331 { "loc14", LOC_REG (14) }, \
2332 { "loc15", LOC_REG (15) }, \
2333 { "loc16", LOC_REG (16) }, \
2334 { "loc17", LOC_REG (17) }, \
2335 { "loc18", LOC_REG (18) }, \
2336 { "loc19", LOC_REG (19) }, \
2337 { "loc20", LOC_REG (20) }, \
2338 { "loc21", LOC_REG (21) }, \
2339 { "loc22", LOC_REG (22) }, \
2340 { "loc23", LOC_REG (23) }, \
2341 { "loc24", LOC_REG (24) }, \
2342 { "loc25", LOC_REG (25) }, \
2343 { "loc26", LOC_REG (26) }, \
2344 { "loc27", LOC_REG (27) }, \
2345 { "loc28", LOC_REG (28) }, \
2346 { "loc29", LOC_REG (29) }, \
2347 { "loc30", LOC_REG (30) }, \
2348 { "loc31", LOC_REG (31) }, \
2349 { "loc32", LOC_REG (32) }, \
2350 { "loc33", LOC_REG (33) }, \
2351 { "loc34", LOC_REG (34) }, \
2352 { "loc35", LOC_REG (35) }, \
2353 { "loc36", LOC_REG (36) }, \
2354 { "loc37", LOC_REG (37) }, \
2355 { "loc38", LOC_REG (38) }, \
2356 { "loc39", LOC_REG (39) }, \
2357 { "loc40", LOC_REG (40) }, \
2358 { "loc41", LOC_REG (41) }, \
2359 { "loc42", LOC_REG (42) }, \
2360 { "loc43", LOC_REG (43) }, \
2361 { "loc44", LOC_REG (44) }, \
2362 { "loc45", LOC_REG (45) }, \
2363 { "loc46", LOC_REG (46) }, \
2364 { "loc47", LOC_REG (47) }, \
2365 { "loc48", LOC_REG (48) }, \
2366 { "loc49", LOC_REG (49) }, \
2367 { "loc50", LOC_REG (50) }, \
2368 { "loc51", LOC_REG (51) }, \
2369 { "loc52", LOC_REG (52) }, \
2370 { "loc53", LOC_REG (53) }, \
2371 { "loc54", LOC_REG (54) }, \
2372 { "loc55", LOC_REG (55) }, \
2373 { "loc56", LOC_REG (56) }, \
2374 { "loc57", LOC_REG (57) }, \
2375 { "loc58", LOC_REG (58) }, \
2376 { "loc59", LOC_REG (59) }, \
2377 { "loc60", LOC_REG (60) }, \
2378 { "loc61", LOC_REG (61) }, \
2379 { "loc62", LOC_REG (62) }, \
2380 { "loc63", LOC_REG (63) }, \
2381 { "loc64", LOC_REG (64) }, \
2382 { "loc65", LOC_REG (65) }, \
2383 { "loc66", LOC_REG (66) }, \
2384 { "loc67", LOC_REG (67) }, \
2385 { "loc68", LOC_REG (68) }, \
2386 { "loc69", LOC_REG (69) }, \
2387 { "loc70", LOC_REG (70) }, \
2388 { "loc71", LOC_REG (71) }, \
2389 { "loc72", LOC_REG (72) }, \
2390 { "loc73", LOC_REG (73) }, \
2391 { "loc74", LOC_REG (74) }, \
2392 { "loc75", LOC_REG (75) }, \
2393 { "loc76", LOC_REG (76) }, \
2394 { "loc77", LOC_REG (77) }, \
2395 { "loc78", LOC_REG (78) }, \
2396 { "loc79", LOC_REG (79) }, \
2399 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2400 for an instruction operand X. X is an RTL expression. */
2402 #define PRINT_OPERAND(STREAM, X, CODE) \
2403 ia64_print_operand (STREAM, X, CODE)
2405 /* A C expression which evaluates to true if CODE is a valid punctuation
2406 character for use in the `PRINT_OPERAND' macro. */
2408 /* ??? Keep this around for now, as we might need it later. */
2410 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2411 ((CODE) == '+' || (CODE) == ',')
2413 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2414 for an instruction operand that is a memory reference whose address is X. X
2415 is an RTL expression. */
2417 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2418 ia64_print_operand_address (STREAM, X)
2420 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2421 `%I' options of `asm_fprintf' (see `final.c'). */
2423 #define REGISTER_PREFIX ""
2424 #define LOCAL_LABEL_PREFIX "."
2425 #define USER_LABEL_PREFIX ""
2426 #define IMMEDIATE_PREFIX ""
2429 /* Output of dispatch tables. */
2431 /* This macro should be provided on machines where the addresses in a dispatch
2432 table are relative to the table's own address. */
2434 /* ??? Depends on the pointer size. */
2436 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2437 fprintf (STREAM, "\tdata8 .L%d-.L%d\n", VALUE, REL)
2439 /* This is how to output an element of a case-vector that is absolute.
2440 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2442 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2444 /* Define this if something special must be output at the end of a jump-table.
2445 We need to align back to a 16 byte boundary because offsets are smaller than
2448 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) ASM_OUTPUT_ALIGN (STREAM, 4)
2450 /* Jump tables only need 8 byte alignment. */
2452 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2455 /* Assembler Commands for Exception Regions. */
2457 /* Select a format to encode pointers in exception handling data. CODE
2458 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2459 true if the symbol may be affected by dynamic relocations. */
2460 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2461 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2462 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2464 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2465 indirect are handled automatically. */
2466 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2468 const char *reltag = NULL; \
2469 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2470 reltag = "@segrel("; \
2471 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2472 reltag = "@gprel("; \
2475 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2476 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2477 : (abort (), "")), FILE); \
2478 fputs (reltag, FILE); \
2479 assemble_name (FILE, XSTR (ADDR, 0)); \
2480 fputc (')', FILE); \
2486 /* Assembler Commands for Alignment. */
2488 /* The alignment (log base 2) to put in front of LABEL, which follows
2491 /* ??? Investigate. */
2493 /* ??? Emitting align directives increases the size of the line number debug
2494 info, because each .align forces use of an extended opcode. Perhaps try
2495 to fix this in the assembler? */
2497 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2499 /* The desired alignment for the location counter at the beginning
2502 /* ??? Investigate. */
2503 /* #define LOOP_ALIGN(LABEL) */
2505 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2506 section because it fails put zeros in the bytes that are skipped. */
2508 #define ASM_NO_SKIP_IN_TEXT 1
2510 /* A C statement to output to the stdio stream STREAM an assembler command to
2511 advance the location counter to a multiple of 2 to the POWER bytes. */
2513 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2514 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2517 /* Macros Affecting all Debug Formats. */
2519 /* This is handled in svr4.h and sysv4.h. */
2522 /* Specific Options for DBX Output. */
2524 /* This is handled by dbxelf.h which is included by svr4.h. */
2527 /* Open ended Hooks for DBX Output. */
2532 /* File names in DBX format. */
2537 /* Macros for SDB and Dwarf Output. */
2539 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2540 output in response to the `-g' option. */
2542 #define DWARF2_DEBUGGING_INFO
2544 /* C string constants giving the pseudo-op to use for a sequence of
2545 2, 4, and 8 byte unaligned constants. dwarf2out.c needs these. */
2547 #define UNALIGNED_SHORT_ASM_OP "\tdata2.ua\t"
2548 #define UNALIGNED_INT_ASM_OP "\tdata4.ua\t"
2549 #define UNALIGNED_DOUBLE_INT_ASM_OP "\tdata8.ua\t"
2551 /* We need to override the default definition for this in dwarf2out.c so that
2552 we can emit the necessary # postfix. */
2553 #define ASM_NAME_TO_STRING(STR, NAME) \
2555 if ((NAME)[0] == '*') \
2556 dyn_string_append (STR, NAME + 1); \
2560 STRIP_NAME_ENCODING (newstr, NAME); \
2561 dyn_string_append (STR, user_label_prefix); \
2562 dyn_string_append (STR, newstr); \
2563 dyn_string_append (STR, "#"); \
2568 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2570 /* Use tags for debug info labels, so that they don't break instruction
2571 bundles. This also avoids getting spurious DV warnings from the
2572 assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we
2573 add brackets around the label. */
2575 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2576 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2578 /* Use section-relative relocations for debugging offsets. Unlike other
2579 targets that fake this by putting the section VMA at 0, IA-64 has
2580 proper relocations for them. */
2581 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2583 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2584 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2585 : (abort (), "")), FILE); \
2586 fputs ("@secrel(", FILE); \
2587 assemble_name (FILE, LABEL); \
2588 fputc (')', FILE); \
2591 /* Emit a PC-relative relocation. */
2592 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2594 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2595 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2596 : (abort (), "")), FILE); \
2597 fputs ("@pcrel(", FILE); \
2598 assemble_name (FILE, LABEL); \
2599 fputc (')', FILE); \
2602 /* Cross Compilation and Floating Point. */
2604 /* Define to enable software floating point emulation. */
2605 #define REAL_ARITHMETIC
2608 /* Register Renaming Parameters. */
2610 /* A C expression that is nonzero if hard register number REGNO2 can be
2611 considered for use as a rename register for REGNO1 */
2613 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2614 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2616 /* Define this macro if the compiler should use extended basic blocks
2617 when renaming registers. Define this macro if the target has predicate
2620 #define RENAME_EXTENDED_BLOCKS
2623 /* Miscellaneous Parameters. */
2625 /* Define this if you have defined special-purpose predicates in the file
2626 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2627 expressions matched by the predicate. */
2629 #define PREDICATE_CODES \
2630 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2631 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2632 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2633 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2634 { "function_operand", {SYMBOL_REF}}, \
2635 { "setjmp_operand", {SYMBOL_REF}}, \
2636 { "destination_operand", {SUBREG, REG, MEM}}, \
2637 { "not_postinc_memory_operand", {MEM}}, \
2638 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2639 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2640 { "gr_register_operand", {SUBREG, REG}}, \
2641 { "fr_register_operand", {SUBREG, REG}}, \
2642 { "grfr_register_operand", {SUBREG, REG}}, \
2643 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2644 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2645 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2646 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2647 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2648 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2649 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2650 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2651 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2653 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2655 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2656 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2657 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2658 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2660 { "shladd_operand", {CONST_INT}}, \
2661 { "fetchadd_operand", {CONST_INT}}, \
2662 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2663 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2664 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2665 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2666 { "predicate_operator", {NE, EQ}}, \
2667 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2668 { "ar_lc_reg_operand", {REG}}, \
2669 { "ar_ccv_reg_operand", {REG}}, \
2670 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2671 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2672 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
2674 /* An alias for a machine mode name. This is the machine mode that elements of
2675 a jump-table should have. */
2677 #define CASE_VECTOR_MODE Pmode
2679 /* Define as C expression which evaluates to nonzero if the tablejump
2680 instruction expects the table to contain offsets from the address of the
2683 #define CASE_VECTOR_PC_RELATIVE 1
2685 /* Define this macro if operations between registers with integral mode smaller
2686 than a word are always performed on the entire register. */
2688 #define WORD_REGISTER_OPERATIONS
2690 /* Define this macro to be a C expression indicating when insns that read
2691 memory in MODE, an integral mode narrower than a word, set the bits outside
2692 of MODE to be either the sign-extension or the zero-extension of the data
2695 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2697 /* An alias for a tree code that should be used by default for conversion of
2698 floating point values to fixed point. */
2700 /* ??? Looks like this macro is obsolete and should be deleted everywhere. */
2702 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2704 /* An alias for a tree code that is the easiest kind of division to compile
2705 code for in the general case. */
2707 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2709 /* The maximum number of bytes that a single instruction can move quickly from
2710 memory to memory. */
2713 /* A C expression which is nonzero if on this machine it is safe to "convert"
2714 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2715 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2717 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2719 /* A C expression describing the value returned by a comparison operator with
2720 an integral mode and stored by a store-flag instruction (`sCOND') when the
2721 condition is true. */
2723 /* ??? Investigate using -1 instead of 1. */
2725 #define STORE_FLAG_VALUE 1
2727 /* An alias for the machine mode for pointers. */
2729 /* ??? This would change if we had ILP32 support. */
2731 #define Pmode DImode
2733 /* An alias for the machine mode used for memory references to functions being
2734 called, in `call' RTL expressions. */
2736 #define FUNCTION_MODE Pmode
2738 /* Define this macro to handle System V style pragmas: #pragma pack and
2739 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2742 #define HANDLE_SYSV_PRAGMA
2744 /* In rare cases, correct code generation requires extra machine dependent
2745 processing between the second jump optimization pass and delayed branch
2746 scheduling. On those machines, define this macro as a C statement to act on
2747 the code starting at INSN. */
2749 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2751 /* A C expression for the maximum number of instructions to execute via
2752 conditional execution instructions instead of a branch. A value of
2753 BRANCH_COST+1 is the default if the machine does not use
2754 cc0, and 1 if it does use cc0. */
2755 /* ??? Investigate. */
2756 #define MAX_CONDITIONAL_EXECUTE 12
2758 extern int ia64_final_schedule;
2760 #define IA64_UNWIND_INFO 1
2761 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2763 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2765 /* This function contains machine specific function data. */
2766 struct machine_function
2768 /* The new stack pointer when unwinding from EH. */
2769 struct rtx_def* ia64_eh_epilogue_sp;
2771 /* The new bsp value when unwinding from EH. */
2772 struct rtx_def* ia64_eh_epilogue_bsp;
2774 /* The GP value save register. */
2775 struct rtx_def* ia64_gp_save;
2777 /* The number of varargs registers to save. */
2784 IA64_BUILTIN_SYNCHRONIZE,
2786 IA64_BUILTIN_FETCH_AND_ADD_SI,
2787 IA64_BUILTIN_FETCH_AND_SUB_SI,
2788 IA64_BUILTIN_FETCH_AND_OR_SI,
2789 IA64_BUILTIN_FETCH_AND_AND_SI,
2790 IA64_BUILTIN_FETCH_AND_XOR_SI,
2791 IA64_BUILTIN_FETCH_AND_NAND_SI,
2793 IA64_BUILTIN_ADD_AND_FETCH_SI,
2794 IA64_BUILTIN_SUB_AND_FETCH_SI,
2795 IA64_BUILTIN_OR_AND_FETCH_SI,
2796 IA64_BUILTIN_AND_AND_FETCH_SI,
2797 IA64_BUILTIN_XOR_AND_FETCH_SI,
2798 IA64_BUILTIN_NAND_AND_FETCH_SI,
2800 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2801 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2803 IA64_BUILTIN_SYNCHRONIZE_SI,
2805 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2807 IA64_BUILTIN_LOCK_RELEASE_SI,
2809 IA64_BUILTIN_FETCH_AND_ADD_DI,
2810 IA64_BUILTIN_FETCH_AND_SUB_DI,
2811 IA64_BUILTIN_FETCH_AND_OR_DI,
2812 IA64_BUILTIN_FETCH_AND_AND_DI,
2813 IA64_BUILTIN_FETCH_AND_XOR_DI,
2814 IA64_BUILTIN_FETCH_AND_NAND_DI,
2816 IA64_BUILTIN_ADD_AND_FETCH_DI,
2817 IA64_BUILTIN_SUB_AND_FETCH_DI,
2818 IA64_BUILTIN_OR_AND_FETCH_DI,
2819 IA64_BUILTIN_AND_AND_FETCH_DI,
2820 IA64_BUILTIN_XOR_AND_FETCH_DI,
2821 IA64_BUILTIN_NAND_AND_FETCH_DI,
2823 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2824 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2826 IA64_BUILTIN_SYNCHRONIZE_DI,
2828 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2830 IA64_BUILTIN_LOCK_RELEASE_DI,
2833 IA64_BUILTIN_FLUSHRS
2836 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2838 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
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