1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
34 #define CPP_CPU_SPEC "\
35 -Acpu=ia64 -Amachine=ia64 \
36 %{!ansi:%{!std=c*:%{!std=i*:-Dia64}}} -D__ia64 -D__ia64__"
38 #define CC1_SPEC "%(cc1_cpu) "
40 /* This declaration should be present. */
41 extern int target_flags;
43 /* This series of macros is to allow compiler command arguments to enable or
44 disable the use of optional features of the target machine. */
46 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
48 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
50 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
52 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
54 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
56 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
58 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
60 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
62 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
64 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
66 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
68 #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
70 #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
72 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
74 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
76 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
78 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
80 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
82 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
84 #define TARGET_ILP32 (target_flags & MASK_ILP32)
86 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
88 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
90 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
92 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
94 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
96 #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
98 #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
100 #define TARGET_INLINE_DIV \
101 (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
103 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
105 /* This macro defines names of command options to set and clear bits in
106 `target_flags'. Its definition is an initializer with a subgrouping for
107 each command option. */
109 #define TARGET_SWITCHES \
111 { "big-endian", MASK_BIG_ENDIAN, \
112 N_("Generate big endian code") }, \
113 { "little-endian", -MASK_BIG_ENDIAN, \
114 N_("Generate little endian code") }, \
115 { "gnu-as", MASK_GNU_AS, \
116 N_("Generate code for GNU as") }, \
117 { "no-gnu-as", -MASK_GNU_AS, \
118 N_("Generate code for Intel as") }, \
119 { "gnu-ld", MASK_GNU_LD, \
120 N_("Generate code for GNU ld") }, \
121 { "no-gnu-ld", -MASK_GNU_LD, \
122 N_("Generate code for Intel ld") }, \
123 { "no-pic", MASK_NO_PIC, \
124 N_("Generate code without GP reg") }, \
125 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
126 N_("Emit stop bits before and after volatile extended asms") }, \
127 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
128 N_("Don't emit stop bits before and after volatile extended asms") }, \
129 { "b-step", MASK_B_STEP, \
130 N_("Emit code for Itanium (TM) processor B step")}, \
131 { "register-names", MASK_REG_NAMES, \
132 N_("Use in/loc/out register names")}, \
133 { "no-sdata", MASK_NO_SDATA, \
134 N_("Disable use of sdata/scommon/sbss")}, \
135 { "sdata", -MASK_NO_SDATA, \
136 N_("Enable use of sdata/scommon/sbss")}, \
137 { "constant-gp", MASK_CONST_GP, \
138 N_("gp is constant (but save/restore gp on indirect calls)") }, \
139 { "auto-pic", MASK_AUTO_PIC, \
140 N_("Generate self-relocatable code") }, \
141 { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
142 N_("Generate inline division, optimize for latency") }, \
143 { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
144 N_("Generate inline division, optimize for throughput") }, \
145 { "dwarf2-asm", MASK_DWARF2_ASM, \
146 N_("Enable Dwarf 2 line debug info via GNU as")}, \
147 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
148 N_("Disable Dwarf 2 line debug info via GNU as")}, \
150 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
154 /* Default target_flags if no switches are specified */
156 #ifndef TARGET_DEFAULT
157 #define TARGET_DEFAULT MASK_DWARF2_ASM
160 #ifndef TARGET_CPU_DEFAULT
161 #define TARGET_CPU_DEFAULT 0
164 #ifndef SUBTARGET_SWITCHES
165 #define SUBTARGET_SWITCHES
168 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
169 options that have values. Its definition is an initializer with a
170 subgrouping for each command option. */
172 extern const char *ia64_fixed_range_string;
173 #define TARGET_OPTIONS \
175 { "fixed-range=", &ia64_fixed_range_string, \
176 N_("Specify range of registers to make fixed")}, \
179 /* Sometimes certain combinations of command options do not make sense on a
180 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
181 take account of this. This macro, if defined, is executed once just after
182 all the command options have been parsed. */
184 #define OVERRIDE_OPTIONS ia64_override_options ()
186 /* Some machines may desire to change what optimizations are performed for
187 various optimization levels. This macro, if defined, is executed once just
188 after the optimization level is determined and before the remainder of the
189 command options have been parsed. Values set in this macro are used as the
190 default values for the other command line options. */
192 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
194 /* Driver configuration */
196 /* A C string constant that tells the GNU CC driver program options to pass to
197 CPP. It can also specify how to translate options you give to GNU CC into
198 options for GNU CC to pass to the CPP. */
200 /* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */
201 /* ??? An alternative is to modify glimits.h to check for __LP64__ instead
202 of checked for CPU specific defines. We could also get rid of all LONG_MAX
203 defines in other tm.h files. */
205 "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
206 -D__LONG_MAX__=9223372036854775807L"
208 /* If this macro is defined, the preprocessor will not define the builtin macro
209 `__SIZE_TYPE__'. The macro `__SIZE_TYPE__' must then be defined by
212 This should be defined if `SIZE_TYPE' depends on target dependent flags
213 which are not accessible to the preprocessor. Otherwise, it should not be
215 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
216 /* #define NO_BUILTIN_SIZE_TYPE */
218 /* If this macro is defined, the preprocessor will not define the builtin macro
219 `__PTRDIFF_TYPE__'. The macro `__PTRDIFF_TYPE__' must then be defined by
222 This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
223 which are not accessible to the preprocessor. Otherwise, it should not be
225 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
226 /* #define NO_BUILTIN_PTRDIFF_TYPE */
228 /* A C string constant that tells the GNU CC driver program options to pass to
229 `cc1'. It can also specify how to translate options you give to GNU CC into
230 options for GNU CC to pass to the `cc1'. */
233 #define CC1_SPEC "%{G*}"
235 /* A C string constant that tells the GNU CC driver program options to pass to
236 `cc1plus'. It can also specify how to translate options you give to GNU CC
237 into options for GNU CC to pass to the `cc1plus'. */
239 /* #define CC1PLUS_SPEC "" */
243 /* Define this macro to have the value 1 if the most significant bit in a byte
244 has the lowest number; otherwise define it to have the value zero. */
246 #define BITS_BIG_ENDIAN 0
248 /* Define this macro to have the value 1 if the most significant byte in a word
249 has the lowest number. This macro need not be a constant. */
251 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
253 /* Define this macro to have the value 1 if, in a multiword object, the most
254 significant word has the lowest number. */
256 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
258 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a
259 constant value with the same meaning as WORDS_BIG_ENDIAN, which will be used
260 only when compiling libgcc2.c. Typically the value will be set based on
261 preprocessor defines. */
262 #if defined(__BIG_ENDIAN__)
263 #define LIBGCC2_WORDS_BIG_ENDIAN 1
265 #define LIBGCC2_WORDS_BIG_ENDIAN 0
268 /* Define this macro to be the number of bits in an addressable storage unit
269 (byte); normally 8. */
270 #define BITS_PER_UNIT 8
272 /* Number of bits in a word; normally 32. */
273 #define BITS_PER_WORD 64
275 /* Number of storage units in a word; normally 4. */
276 #define UNITS_PER_WORD 8
278 /* Width of a pointer, in bits. You must specify a value no wider than the
279 width of `Pmode'. If it is not equal to the width of `Pmode', you must
280 define `POINTERS_EXTEND_UNSIGNED'. */
281 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
283 /* A C expression whose value is zero if pointers that need to be extended
284 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
285 they are zero-extended and negative one if there is an ptr_extend operation.
287 You need not define this macro if the `POINTER_SIZE' is equal to the width
289 /* Need this for 32 bit pointers, see hpux.h for setting it. */
290 /* #define POINTERS_EXTEND_UNSIGNED */
292 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
293 which has the specified mode and signedness is to be stored in a register.
294 This macro is only called when TYPE is a scalar type. */
295 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
298 if (GET_MODE_CLASS (MODE) == MODE_INT \
299 && GET_MODE_SIZE (MODE) < 4) \
304 /* Define this macro if the promotion described by `PROMOTE_MODE' should also
305 be done for outgoing function arguments. */
306 /* ??? ABI doesn't allow us to define this. */
307 /* #define PROMOTE_FUNCTION_ARGS */
309 /* Define this macro if the promotion described by `PROMOTE_MODE' should also
310 be done for the return value of functions.
312 If this macro is defined, `FUNCTION_VALUE' must perform the same promotions
313 done by `PROMOTE_MODE'. */
314 /* ??? ABI doesn't allow us to define this. */
315 /* #define PROMOTE_FUNCTION_RETURN */
317 /* Normal alignment required for function parameters on the stack, in bits.
318 All stack parameters receive at least this much alignment regardless of data
319 type. On most machines, this is the same as the size of an integer. */
320 #define PARM_BOUNDARY 64
322 /* Define this macro if you wish to preserve a certain alignment for the stack
323 pointer. The definition is a C expression for the desired alignment
324 (measured in bits). */
326 #define STACK_BOUNDARY 128
328 /* Align frames on double word boundaries */
329 #ifndef IA64_STACK_ALIGN
330 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
333 /* Alignment required for a function entry point, in bits. */
334 #define FUNCTION_BOUNDARY 128
336 /* Biggest alignment that any data type can require on this machine,
338 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
339 128 bit integers all require 128 bit alignment. */
340 #define BIGGEST_ALIGNMENT 128
342 /* If defined, a C expression to compute the alignment for a static variable.
343 TYPE is the data type, and ALIGN is the alignment that the object
344 would ordinarily have. The value of this macro is used instead of that
345 alignment to align the object. */
347 #define DATA_ALIGNMENT(TYPE, ALIGN) \
348 (TREE_CODE (TYPE) == ARRAY_TYPE \
349 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
350 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
352 /* If defined, a C expression to compute the alignment given to a constant that
353 is being placed in memory. CONSTANT is the constant and ALIGN is the
354 alignment that the object would ordinarily have. The value of this macro is
355 used instead of that alignment to align the object. */
357 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
358 (TREE_CODE (EXP) == STRING_CST \
359 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
361 /* Define this macro to be the value 1 if instructions will fail to work if
362 given data not on the nominal alignment. If instructions will merely go
363 slower in that case, define this macro as 0. */
364 #define STRICT_ALIGNMENT 1
366 /* Define this if you wish to imitate the way many other C compilers handle
367 alignment of bitfields and the structures that contain them.
368 The behavior is that the type written for a bitfield (`int', `short', or
369 other integer type) imposes an alignment for the entire structure, as if the
370 structure really did contain an ordinary field of that type. In addition,
371 the bitfield is placed within the structure so that it would fit within such
372 a field, not crossing a boundary for it. */
373 #define PCC_BITFIELD_TYPE_MATTERS 1
375 /* An integer expression for the size in bits of the largest integer machine
376 mode that should actually be used. */
378 /* Allow pairs of registers to be used, which is the intent of the default. */
379 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
381 /* A code distinguishing the floating point format of the target machine. */
382 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
384 /* By default, the C++ compiler will use function addresses in the
385 vtable entries. Setting this non-zero tells the compiler to use
386 function descriptors instead. The value of this macro says how
387 many words wide the descriptor is (normally 2). It is assumed
388 that the address of a function descriptor may be treated as a
389 pointer to a function. */
390 #define TARGET_VTABLE_USES_DESCRIPTORS 2
392 /* Layout of Source Language Data Types */
394 /* A C expression for the size in bits of the type `int' on the target machine.
395 If you don't define this, the default is one word. */
396 #define INT_TYPE_SIZE 32
398 /* A C expression for the size in bits of the type `short' on the target
399 machine. If you don't define this, the default is half a word. (If this
400 would be less than one storage unit, it is rounded up to one unit.) */
401 #define SHORT_TYPE_SIZE 16
403 /* A C expression for the size in bits of the type `long' on the target
404 machine. If you don't define this, the default is one word. */
405 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
407 /* Maximum number for the size in bits of the type `long' on the target
408 machine. If this is undefined, the default is `LONG_TYPE_SIZE'. Otherwise,
409 it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
410 have at run-time. This is used in `cpp'. */
411 #define MAX_LONG_TYPE_SIZE 64
413 /* A C expression for the size in bits of the type `long long' on the target
414 machine. If you don't define this, the default is two words. If you want
415 to support GNU Ada on your machine, the value of macro must be at least 64. */
416 #define LONG_LONG_TYPE_SIZE 64
418 /* A C expression for the size in bits of the type `char' on the target
419 machine. If you don't define this, the default is one quarter of a word.
420 (If this would be less than one storage unit, it is rounded up to one unit.) */
421 #define CHAR_TYPE_SIZE 8
423 /* A C expression for the size in bits of the type `float' on the target
424 machine. If you don't define this, the default is one word. */
425 #define FLOAT_TYPE_SIZE 32
427 /* A C expression for the size in bits of the type `double' on the target
428 machine. If you don't define this, the default is two words. */
429 #define DOUBLE_TYPE_SIZE 64
431 /* A C expression for the size in bits of the type `long double' on the target
432 machine. If you don't define this, the default is two words. */
433 #define LONG_DOUBLE_TYPE_SIZE 128
435 /* Tell real.c that this is the 80-bit Intel extended float format
436 packaged in a 128-bit entity. */
438 #define INTEL_EXTENDED_IEEE_FORMAT 1
440 /* An expression whose value is 1 or 0, according to whether the type `char'
441 should be signed or unsigned by default. The user can always override this
442 default with the options `-fsigned-char' and `-funsigned-char'. */
443 #define DEFAULT_SIGNED_CHAR 1
445 /* A C expression for a string describing the name of the data type to use for
446 size values. The typedef name `size_t' is defined using the contents of the
448 /* ??? Needs to be defined for P64 code. */
449 /* #define SIZE_TYPE */
451 /* A C expression for a string describing the name of the data type to use for
452 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
453 defined using the contents of the string. See `SIZE_TYPE' above for more
455 /* ??? Needs to be defined for P64 code. */
456 /* #define PTRDIFF_TYPE */
458 /* A C expression for a string describing the name of the data type to use for
459 wide characters. The typedef name `wchar_t' is defined using the contents
460 of the string. See `SIZE_TYPE' above for more information. */
461 /* #define WCHAR_TYPE */
463 /* A C expression for the size in bits of the data type for wide characters.
464 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
465 /* #define WCHAR_TYPE_SIZE */
467 /* Maximum number for the size in bits of the data type for wide characters.
468 If this is undefined, the default is `WCHAR_TYPE_SIZE'. Otherwise, it is
469 the constant value that is the largest value that `WCHAR_TYPE_SIZE' can have
470 at run-time. This is used in `cpp'. */
471 /* #define MAX_WCHAR_TYPE_SIZE */
474 /* Register Basics */
476 /* Number of hardware registers known to the compiler.
477 We have 128 general registers, 128 floating point registers,
478 64 predicate registers, 8 branch registers, one frame pointer,
479 and several "application" registers. */
481 #define FIRST_PSEUDO_REGISTER 335
483 /* Ranges for the various kinds of registers. */
484 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
485 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
486 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
487 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
488 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
489 #define GENERAL_REGNO_P(REGNO) \
490 (GR_REGNO_P (REGNO) \
491 || (REGNO) == FRAME_POINTER_REGNUM \
492 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
494 #define GR_REG(REGNO) ((REGNO) + 0)
495 #define FR_REG(REGNO) ((REGNO) + 128)
496 #define PR_REG(REGNO) ((REGNO) + 256)
497 #define BR_REG(REGNO) ((REGNO) + 320)
498 #define OUT_REG(REGNO) ((REGNO) + 120)
499 #define IN_REG(REGNO) ((REGNO) + 112)
500 #define LOC_REG(REGNO) ((REGNO) + 32)
502 #define AR_CCV_REGNUM 330
503 #define AR_UNAT_REGNUM 331
504 #define AR_PFS_REGNUM 332
505 #define AR_LC_REGNUM 333
506 #define AR_EC_REGNUM 334
508 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
509 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
510 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
512 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
513 || (REGNO) == AR_UNAT_REGNUM)
514 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
515 && (REGNO) < FIRST_PSEUDO_REGISTER)
516 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
517 && (REGNO) < FIRST_PSEUDO_REGISTER)
520 /* ??? Don't really need two sets of macros. I like this one better because
521 it is less typing. */
522 #define R_GR(REGNO) GR_REG (REGNO)
523 #define R_FR(REGNO) FR_REG (REGNO)
524 #define R_PR(REGNO) PR_REG (REGNO)
525 #define R_BR(REGNO) BR_REG (REGNO)
527 /* An initializer that says which registers are used for fixed purposes all
528 throughout the compiled code and are therefore not available for general
532 r1: global pointer (gp)
533 r12: stack pointer (sp)
534 r13: thread pointer (tp)
538 fp: eliminable frame pointer */
540 /* The last 16 stacked regs are reserved for the 8 input and 8 output
543 #define FIXED_REGISTERS \
544 { /* General registers. */ \
545 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
553 /* Floating-point registers. */ \
554 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
562 /* Predicate registers. */ \
563 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
567 /* Branch registers. */ \
568 0, 0, 0, 0, 0, 0, 0, 0, \
569 /*FP RA CCV UNAT PFS LC EC */ \
570 1, 1, 1, 1, 1, 0, 1 \
573 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
574 (in general) by function calls as well as for fixed registers. This
575 macro therefore identifies the registers that are not available for
576 general allocation of values that must live across function calls. */
578 #define CALL_USED_REGISTERS \
579 { /* General registers. */ \
580 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
587 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
588 /* Floating-point registers. */ \
589 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
592 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
597 /* Predicate registers. */ \
598 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
602 /* Branch registers. */ \
603 1, 0, 0, 0, 0, 0, 1, 1, \
604 /*FP RA CCV UNAT PFS LC EC */ \
605 1, 1, 1, 1, 1, 0, 1 \
608 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
609 problem which makes CALL_USED_REGISTERS *always* include
610 all the FIXED_REGISTERS. Until this problem has been
611 resolved this macro can be used to overcome this situation.
612 In particular, block_propagate() requires this list
613 be acurate, or we can remove registers which should be live.
614 This macro is used in regs_invalidated_by_call. */
616 #define CALL_REALLY_USED_REGISTERS \
617 { /* General registers. */ \
618 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
620 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
623 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
624 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
625 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
626 /* Floating-point registers. */ \
627 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
629 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
630 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
631 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
632 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
633 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
634 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
635 /* Predicate registers. */ \
636 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
637 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
638 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
639 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
640 /* Branch registers. */ \
641 1, 0, 0, 0, 0, 0, 1, 1, \
642 /*FP RA CCV UNAT PFS LC EC */ \
643 0, 0, 1, 0, 1, 0, 0 \
647 /* Define this macro if the target machine has register windows. This C
648 expression returns the register number as seen by the called function
649 corresponding to the register number OUT as seen by the calling function.
650 Return OUT if register number OUT is not an outbound register. */
652 #define INCOMING_REGNO(OUT) \
653 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
655 /* Define this macro if the target machine has register windows. This C
656 expression returns the register number as seen by the calling function
657 corresponding to the register number IN as seen by the called function.
658 Return IN if register number IN is not an inbound register. */
660 #define OUTGOING_REGNO(IN) \
661 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
663 /* Define this macro if the target machine has register windows. This
664 C expression returns true if the register is call-saved but is in the
667 #define LOCAL_REGNO(REGNO) \
668 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
670 /* Add any extra modes needed to represent the condition code.
672 CCImode is used to mark a single predicate register instead
673 of a register pair. This is currently only used in reg_raw_mode
674 so that flow doesn't do something stupid. */
676 #define EXTRA_CC_MODES CC(CCImode, "CCI")
678 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
679 return the mode to be used for the comparison. Must be defined if
680 EXTRA_CC_MODES is defined. */
682 #define SELECT_CC_MODE(OP,X,Y) CCmode
684 /* Order of allocation of registers */
686 /* If defined, an initializer for a vector of integers, containing the numbers
687 of hard registers in the order in which GNU CC should prefer to use them
688 (from most preferred to least).
690 If this macro is not defined, registers are used lowest numbered first (all
693 One use of this macro is on machines where the highest numbered registers
694 must always be saved and the save-multiple-registers instruction supports
695 only sequences of consecutive registers. On such machines, define
696 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
697 allocatable register first. */
699 /* ??? Should the GR return value registers come before or after the rest
700 of the caller-save GRs? */
702 #define REG_ALLOC_ORDER \
704 /* Caller-saved general registers. */ \
705 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
706 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
707 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
708 R_GR (30), R_GR (31), \
709 /* Output registers. */ \
710 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
711 R_GR (126), R_GR (127), \
712 /* Caller-saved general registers, also used for return values. */ \
713 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
714 /* addl caller-saved general registers. */ \
715 R_GR (2), R_GR (3), \
716 /* Caller-saved FP registers. */ \
717 R_FR (6), R_FR (7), \
718 /* Caller-saved FP registers, used for parameters and return values. */ \
719 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
720 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
721 /* Rotating caller-saved FP registers. */ \
722 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
723 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
724 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
725 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
726 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
727 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
728 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
729 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
730 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
731 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
732 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
733 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
734 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
735 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
736 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
737 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
738 R_FR (126), R_FR (127), \
739 /* Caller-saved predicate registers. */ \
740 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
741 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
742 /* Rotating caller-saved predicate registers. */ \
743 R_PR (16), R_PR (17), \
744 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
745 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
746 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
747 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
748 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
749 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
750 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
751 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
752 /* Caller-saved branch registers. */ \
753 R_BR (6), R_BR (7), \
755 /* Stacked callee-saved general registers. */ \
756 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
757 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
758 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
759 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
760 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
761 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
762 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
763 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
764 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
765 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
766 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
767 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
768 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
770 /* Input registers. */ \
771 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
772 R_GR (118), R_GR (119), \
773 /* Callee-saved general registers. */ \
774 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
775 /* Callee-saved FP registers. */ \
776 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
777 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
778 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
779 R_FR (30), R_FR (31), \
780 /* Callee-saved predicate registers. */ \
781 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
782 /* Callee-saved branch registers. */ \
783 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
785 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
786 R_GR (109), R_GR (110), R_GR (111), \
788 /* Special general registers. */ \
789 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
790 /* Special FP registers. */ \
791 R_FR (0), R_FR (1), \
792 /* Special predicate registers. */ \
794 /* Special branch registers. */ \
796 /* Other fixed registers. */ \
797 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
798 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
802 /* How Values Fit in Registers */
804 /* A C expression for the number of consecutive hard registers, starting at
805 register number REGNO, required to hold a value of mode MODE. */
807 /* ??? We say that BImode PR values require two registers. This allows us to
808 easily store the normal and inverted values. We use CCImode to indicate
809 a single predicate register. */
811 #define HARD_REGNO_NREGS(REGNO, MODE) \
812 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
813 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
814 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
815 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
816 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
818 /* A C expression that is nonzero if it is permissible to store a value of mode
819 MODE in hard register number REGNO (or in several registers starting with
822 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
823 (FR_REGNO_P (REGNO) ? \
824 GET_MODE_CLASS (MODE) != MODE_CC && \
825 (MODE) != TImode && \
826 (MODE) != BImode && \
827 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
828 : PR_REGNO_P (REGNO) ? \
829 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
830 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
831 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
832 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
835 /* A C expression that is nonzero if it is desirable to choose register
836 allocation so as to avoid move instructions between a value of mode MODE1
837 and a value of mode MODE2.
839 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
840 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
842 /* Don't tie integer and FP modes, as that causes us to get integer registers
843 allocated for FP instructions. TFmode only supported in FP registers so
844 we can't tie it with any other modes. */
845 #define MODES_TIEABLE_P(MODE1, MODE2) \
846 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
847 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
848 && (((MODE1) == BImode) == ((MODE2) == BImode)))
850 /* Handling Leaf Functions */
852 /* A C initializer for a vector, indexed by hard register number, which
853 contains 1 for a register that is allowable in a candidate for leaf function
855 /* ??? This might be useful. */
856 /* #define LEAF_REGISTERS */
858 /* A C expression whose value is the register number to which REGNO should be
859 renumbered, when a function is treated as a leaf function. */
860 /* ??? This might be useful. */
861 /* #define LEAF_REG_REMAP(REGNO) */
864 /* Register Classes */
866 /* An enumeral type that must be defined with all the register class names as
867 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
868 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
869 which is not a register class but rather tells how many classes there
871 /* ??? When compiling without optimization, it is possible for the only use of
872 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
873 Regclass handles this case specially and does not assign any costs to the
874 pseudo. The pseudo then ends up using the last class before ALL_REGS.
875 Thus we must not let either PR_REGS or BR_REGS be the last class. The
876 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
893 #define GENERAL_REGS GR_REGS
895 /* The number of distinct register classes. */
896 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
898 /* An initializer containing the names of the register classes as C string
899 constants. These names are used in writing some of the debugging dumps. */
900 #define REG_CLASS_NAMES \
901 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
902 "ADDL_REGS", "GR_REGS", "FR_REGS", \
903 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
905 /* An initializer containing the contents of the register classes, as integers
906 which are bit masks. The Nth integer specifies the contents of class N.
907 The way the integer MASK is interpreted is that register R is in the class
908 if `MASK & (1 << R)' is 1. */
909 #define REG_CLASS_CONTENTS \
912 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
913 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
914 0x00000000, 0x00000000, 0x0000 }, \
916 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
917 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
918 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
920 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
921 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
922 0x00000000, 0x00000000, 0x00FF }, \
924 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
925 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
926 0x00000000, 0x00000000, 0x0C00 }, \
928 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
929 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
930 0x00000000, 0x00000000, 0x7000 }, \
932 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
933 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
934 0x00000000, 0x00000000, 0x0000 }, \
936 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
937 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
938 0x00000000, 0x00000000, 0x0300 }, \
940 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
941 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
942 0x00000000, 0x00000000, 0x0000 }, \
943 /* GR_AND_BR_REGS. */ \
944 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
945 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
946 0x00000000, 0x00000000, 0x03FF }, \
947 /* GR_AND_FR_REGS. */ \
948 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
949 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
950 0x00000000, 0x00000000, 0x0300 }, \
952 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
953 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
954 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
957 /* A C expression whose value is a register class containing hard register
958 REGNO. In general there is more than one such class; choose a class which
959 is "minimal", meaning that no smaller class also contains the register. */
960 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
961 may call here with private (invalid) register numbers, such as
963 #define REGNO_REG_CLASS(REGNO) \
964 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
965 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
966 : FR_REGNO_P (REGNO) ? FR_REGS \
967 : PR_REGNO_P (REGNO) ? PR_REGS \
968 : BR_REGNO_P (REGNO) ? BR_REGS \
969 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
970 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
973 /* A macro whose definition is the name of the class to which a valid base
974 register must belong. A base register is one used in an address which is
975 the register value plus a displacement. */
976 #define BASE_REG_CLASS GENERAL_REGS
978 /* A macro whose definition is the name of the class to which a valid index
979 register must belong. An index register is one used in an address where its
980 value is either multiplied by a scale factor or added to another register
981 (as well as added to a displacement). This is needed for POST_MODIFY. */
982 #define INDEX_REG_CLASS GENERAL_REGS
984 /* A C expression which defines the machine-dependent operand constraint
985 letters for register classes. If CHAR is such a letter, the value should be
986 the register class corresponding to it. Otherwise, the value should be
987 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
988 will not be passed to this macro; you do not need to handle it. */
990 #define REG_CLASS_FROM_LETTER(CHAR) \
991 ((CHAR) == 'f' ? FR_REGS \
992 : (CHAR) == 'a' ? ADDL_REGS \
993 : (CHAR) == 'b' ? BR_REGS \
994 : (CHAR) == 'c' ? PR_REGS \
995 : (CHAR) == 'd' ? AR_M_REGS \
996 : (CHAR) == 'e' ? AR_I_REGS \
999 /* A C expression which is nonzero if register number NUM is suitable for use
1000 as a base register in operand addresses. It may be either a suitable hard
1001 register or a pseudo register that has been allocated such a hard reg. */
1002 #define REGNO_OK_FOR_BASE_P(REGNO) \
1003 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
1005 /* A C expression which is nonzero if register number NUM is suitable for use
1006 as an index register in operand addresses. It may be either a suitable hard
1007 register or a pseudo register that has been allocated such a hard reg.
1008 This is needed for POST_MODIFY. */
1009 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
1011 /* A C expression that places additional restrictions on the register class to
1012 use when it is necessary to copy value X into a register in class CLASS.
1013 The value is a register class; perhaps CLASS, or perhaps another, smaller
1016 /* Don't allow volatile mem reloads into floating point registers. This
1017 is defined to force reload to choose the r/m case instead of the f/f case
1018 when reloading (set (reg fX) (mem/v)).
1020 Do not reload expressions into AR regs. */
1022 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1023 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
1024 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
1025 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
1026 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
1029 /* You should define this macro to indicate to the reload phase that it may
1030 need to allocate at least one register for a reload in addition to the
1031 register to contain the data. Specifically, if copying X to a register
1032 CLASS in MODE requires an intermediate register, you should define this
1033 to return the largest register class all of whose registers can be used
1034 as intermediate registers or scratch registers. */
1036 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
1037 ia64_secondary_reload_class (CLASS, MODE, X)
1039 /* Certain machines have the property that some registers cannot be copied to
1040 some other registers without using memory. Define this macro on those
1041 machines to be a C expression that is non-zero if objects of mode M in
1042 registers of CLASS1 can only be copied to registers of class CLASS2 by
1043 storing a register of CLASS1 into memory and loading that memory location
1044 into a register of CLASS2. */
1047 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
1048 I'm not quite sure how it could be invoked. The normal problems
1049 with unions should be solved with the addressof fiddling done by
1050 movtf and friends. */
1051 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1052 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
1053 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1056 /* A C expression for the maximum number of consecutive registers of
1057 class CLASS needed to hold a value of mode MODE.
1058 This is closely related to the macro `HARD_REGNO_NREGS'. */
1060 #define CLASS_MAX_NREGS(CLASS, MODE) \
1061 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1062 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
1063 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1065 /* If defined, gives a class of registers that cannot be used as the
1066 operand of a SUBREG that changes the mode of the object illegally. */
1068 #define CLASS_CANNOT_CHANGE_MODE FR_REGS
1070 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
1071 In FP regs, we can't change FP values to integer values and vice
1072 versa, but we can change e.g. DImode to SImode. */
1074 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1075 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO))
1077 /* A C expression that defines the machine-dependent operand constraint
1078 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1081 /* 14 bit signed immediate for arithmetic instructions. */
1082 #define CONST_OK_FOR_I(VALUE) \
1083 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1084 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1085 #define CONST_OK_FOR_J(VALUE) \
1086 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1087 /* 8 bit signed immediate for logical instructions. */
1088 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1089 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1090 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1091 /* 6 bit unsigned immediate for shift counts. */
1092 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1093 /* 9 bit signed immediate for load/store post-increments. */
1094 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1095 /* 0 for r0. Used by Linux kernel, do not change. */
1096 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1097 /* 0 or -1 for dep instruction. */
1098 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1100 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1101 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1102 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1103 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1104 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1105 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1106 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1107 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1108 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1111 /* A C expression that defines the machine-dependent operand constraint letters
1112 (`G', `H') that specify particular ranges of `const_double' values. */
1114 /* 0.0 and 1.0 for fr0 and fr1. */
1115 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1116 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1117 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1119 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1120 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1122 /* A C expression that defines the optional machine-dependent constraint
1123 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1124 types of operands, usually memory references, for the target machine. */
1126 /* Non-volatile memory for FP_REG loads/stores. */
1127 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1128 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1129 /* 1..4 for shladd arguments. */
1130 #define CONSTRAINT_OK_FOR_R(VALUE) \
1131 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1132 /* Non-post-inc memory for asms and other unsavory creatures. */
1133 #define CONSTRAINT_OK_FOR_S(VALUE) \
1134 (GET_CODE (VALUE) == MEM \
1135 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1136 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1138 #define EXTRA_CONSTRAINT(VALUE, C) \
1139 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1140 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1141 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1144 /* Basic Stack Layout */
1146 /* Define this macro if pushing a word onto the stack moves the stack pointer
1147 to a smaller address. */
1148 #define STACK_GROWS_DOWNWARD 1
1150 /* Define this macro if the addresses of local variable slots are at negative
1151 offsets from the frame pointer. */
1152 /* #define FRAME_GROWS_DOWNWARD */
1154 /* Offset from the frame pointer to the first local variable slot to
1156 #define STARTING_FRAME_OFFSET 0
1158 /* Offset from the stack pointer register to the first location at which
1159 outgoing arguments are placed. If not specified, the default value of zero
1160 is used. This is the proper value for most machines. */
1161 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1162 #define STACK_POINTER_OFFSET 16
1164 /* Offset from the argument pointer register to the first argument's address.
1165 On some machines it may depend on the data type of the function. */
1166 #define FIRST_PARM_OFFSET(FUNDECL) 0
1168 /* A C expression whose value is RTL representing the value of the return
1169 address for the frame COUNT steps up from the current frame, after the
1172 /* ??? Frames other than zero would likely require interpreting the frame
1173 unwind info, so we don't try to support them. We would also need to define
1174 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1176 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1177 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1179 /* A C expression whose value is RTL representing the location of the incoming
1180 return address at the beginning of any function, before the prologue. This
1181 RTL is either a `REG', indicating that the return value is saved in `REG',
1182 or a `MEM' representing a location in the stack. This enables DWARF2
1183 unwind info for C++ EH. */
1184 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1186 /* ??? This is not defined because of three problems.
1187 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1188 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1189 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1190 unused register number.
1191 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1192 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1193 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1194 to zero, despite what the documentation implies, because it is tested in
1195 a few places with #ifdef instead of #if. */
1196 #undef INCOMING_RETURN_ADDR_RTX
1198 /* A C expression whose value is an integer giving the offset, in bytes, from
1199 the value of the stack pointer register to the top of the stack frame at the
1200 beginning of any function, before the prologue. The top of the frame is
1201 defined to be the value of the stack pointer in the previous frame, just
1202 before the call instruction. */
1203 #define INCOMING_FRAME_SP_OFFSET 0
1206 /* Register That Address the Stack Frame. */
1208 /* The register number of the stack pointer register, which must also be a
1209 fixed register according to `FIXED_REGISTERS'. On most machines, the
1210 hardware determines which register this is. */
1212 #define STACK_POINTER_REGNUM 12
1214 /* The register number of the frame pointer register, which is used to access
1215 automatic variables in the stack frame. On some machines, the hardware
1216 determines which register this is. On other machines, you can choose any
1217 register you wish for this purpose. */
1219 #define FRAME_POINTER_REGNUM 328
1221 /* Base register for access to local variables of the function. */
1222 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1224 /* The register number of the arg pointer register, which is used to access the
1225 function's argument list. */
1226 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1228 #define ARG_POINTER_REGNUM R_GR(0)
1230 /* The register number for the return address register. For IA-64, this
1231 is not actually a pointer as the name suggests, but that's a name that
1232 gen_rtx_REG already takes care to keep unique. We modify
1233 return_address_pointer_rtx in ia64_expand_prologue to reference the
1234 final output regnum. */
1235 #define RETURN_ADDRESS_POINTER_REGNUM 329
1237 /* Register numbers used for passing a function's static chain pointer. */
1238 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1239 #define STATIC_CHAIN_REGNUM 15
1241 /* Eliminating the Frame Pointer and the Arg Pointer */
1243 /* A C expression which is nonzero if a function must have and use a frame
1244 pointer. This expression is evaluated in the reload pass. If its value is
1245 nonzero the function will have a frame pointer. */
1246 #define FRAME_POINTER_REQUIRED 0
1248 /* Show we can debug even without a frame pointer. */
1249 #define CAN_DEBUG_WITHOUT_FP
1251 /* If defined, this macro specifies a table of register pairs used to eliminate
1252 unneeded registers that point into the stack frame. */
1254 #define ELIMINABLE_REGS \
1256 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1257 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1258 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1259 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1260 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1263 /* A C expression that returns non-zero if the compiler is allowed to try to
1264 replace register number FROM with register number TO. The frame pointer
1265 is automatically handled. */
1267 #define CAN_ELIMINATE(FROM, TO) \
1268 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1270 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1271 specifies the initial difference between the specified pair of
1272 registers. This macro must be defined if `ELIMINABLE_REGS' is
1274 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1275 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1277 /* Passing Function Arguments on the Stack */
1279 /* Define this macro if an argument declared in a prototype as an integral type
1280 smaller than `int' should actually be passed as an `int'. In addition to
1281 avoiding errors in certain cases of mismatch, it also makes for better code
1282 on certain machines. */
1283 /* ??? Investigate. */
1284 /* #define PROMOTE_PROTOTYPES */
1286 /* If defined, the maximum amount of space required for outgoing arguments will
1287 be computed and placed into the variable
1288 `current_function_outgoing_args_size'. */
1290 #define ACCUMULATE_OUTGOING_ARGS 1
1292 /* A C expression that should indicate the number of bytes of its own arguments
1293 that a function pops on returning, or 0 if the function pops no arguments
1294 and the caller must therefore pop them all after the function returns. */
1296 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1299 /* Function Arguments in Registers */
1301 #define MAX_ARGUMENT_SLOTS 8
1302 #define MAX_INT_RETURN_SLOTS 4
1303 #define GR_ARG_FIRST IN_REG (0)
1304 #define GR_RET_FIRST GR_REG (8)
1305 #define GR_RET_LAST GR_REG (11)
1306 #define FR_ARG_FIRST FR_REG (8)
1307 #define FR_RET_FIRST FR_REG (8)
1308 #define FR_RET_LAST FR_REG (15)
1309 #define AR_ARG_FIRST OUT_REG (0)
1311 /* A C expression that controls whether a function argument is passed in a
1312 register, and which register. */
1314 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1315 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1317 /* Define this macro if the target machine has "register windows", so that the
1318 register in which a function sees an arguments is not necessarily the same
1319 as the one in which the caller passed the argument. */
1321 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1322 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1324 /* A C expression for the number of words, at the beginning of an argument,
1325 must be put in registers. The value must be zero for arguments that are
1326 passed entirely in registers or that are entirely pushed on the stack. */
1328 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1329 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1331 /* A C expression that indicates when an argument must be passed by reference.
1332 If nonzero for an argument, a copy of that argument is made in memory and a
1333 pointer to the argument is passed instead of the argument itself. The
1334 pointer is passed in whatever way is appropriate for passing a pointer to
1337 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1339 /* A C type for declaring a variable that is used as the first argument of
1340 `FUNCTION_ARG' and other related values. For some target machines, the type
1341 `int' suffices and can hold the number of bytes of argument so far. */
1343 typedef struct ia64_args
1345 int words; /* # words of arguments so far */
1346 int fp_regs; /* # FR registers used so far */
1347 int prototype; /* whether function prototyped */
1350 /* A C statement (sans semicolon) for initializing the variable CUM for the
1351 state at the beginning of the argument list. */
1353 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1356 (CUM).fp_regs = 0; \
1357 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1360 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1361 arguments for the function being compiled. If this macro is undefined,
1362 `INIT_CUMULATIVE_ARGS' is used instead. */
1364 /* We set prototype to true so that we never try to return a PARALLEL from
1366 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1369 (CUM).fp_regs = 0; \
1370 (CUM).prototype = 1; \
1373 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1374 advance past an argument in the argument list. The values MODE, TYPE and
1375 NAMED describe that argument. Once this is done, the variable CUM is
1376 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1378 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1379 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1381 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1382 argument with the specified mode and type. */
1384 /* Arguments with alignment larger than 8 bytes start at the next even
1385 boundary. See ia64_function_arg. */
1387 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1388 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1389 : (((((MODE) == BLKmode \
1390 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1391 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1392 ? 128 : PARM_BOUNDARY)
1394 /* A C expression that is nonzero if REGNO is the number of a hard register in
1395 which function arguments are sometimes passed. This does *not* include
1396 implicit arguments such as the static chain and the structure-value address.
1397 On many machines, no registers can be used for this purpose since all
1398 function arguments are pushed on the stack. */
1399 #define FUNCTION_ARG_REGNO_P(REGNO) \
1400 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1401 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1403 /* Implement `va_start' for varargs and stdarg. */
1404 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1405 ia64_va_start (stdarg, valist, nextarg)
1407 /* Implement `va_arg'. */
1408 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1409 ia64_va_arg (valist, type)
1411 /* How Scalar Function Values are Returned */
1413 /* A C expression to create an RTX representing the place where a function
1414 returns a value of data type VALTYPE. */
1416 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1417 ia64_function_value (VALTYPE, FUNC)
1419 /* A C expression to create an RTX representing the place where a library
1420 function returns a value of mode MODE. */
1422 #define LIBCALL_VALUE(MODE) \
1423 gen_rtx_REG (MODE, \
1424 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1425 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1426 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1427 ? FR_RET_FIRST : GR_RET_FIRST))
1429 /* A C expression that is nonzero if REGNO is the number of a hard register in
1430 which the values of called function may come back. */
1432 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1433 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1434 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1437 /* How Large Values are Returned */
1439 /* A nonzero value says to return the function value in memory, just as large
1440 structures are always returned. */
1442 #define RETURN_IN_MEMORY(TYPE) \
1443 ia64_return_in_memory (TYPE)
1445 /* If you define this macro to be 0, then the conventions used for structure
1446 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1448 #define DEFAULT_PCC_STRUCT_RETURN 0
1450 /* If the structure value address is passed in a register, then
1451 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1453 #define STRUCT_VALUE_REGNUM GR_REG (8)
1456 /* Caller-Saves Register Allocation */
1458 /* A C expression to determine whether it is worthwhile to consider placing a
1459 pseudo-register in a call-clobbered hard register and saving and restoring
1460 it around each function call. The expression should be 1 when this is worth
1461 doing, and 0 otherwise.
1463 If you don't define this macro, a default is used which is good on most
1464 machines: `4 * CALLS < REFS'. */
1465 /* ??? Investigate. */
1466 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1469 /* Function Entry and Exit */
1471 /* Define this macro as a C expression that is nonzero if the return
1472 instruction or the function epilogue ignores the value of the stack pointer;
1473 in other words, if it is safe to delete an instruction to adjust the stack
1474 pointer before a return from the function. */
1476 #define EXIT_IGNORE_STACK 1
1478 /* Define this macro as a C expression that is nonzero for registers
1479 used by the epilogue or the `return' pattern. */
1481 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1483 /* Output at beginning of assembler file. */
1485 #define ASM_FILE_START(FILE) \
1486 emit_safe_across_calls (FILE)
1488 /* A C compound statement that outputs the assembler code for a thunk function,
1489 used to implement C++ virtual function calls with multiple inheritance. */
1491 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1493 if (CONST_OK_FOR_I (DELTA)) \
1495 fprintf (FILE, "\tadds r32 = "); \
1496 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1497 fprintf (FILE, ", r32\n"); \
1501 if (CONST_OK_FOR_J (DELTA)) \
1503 fprintf (FILE, "\taddl r2 = "); \
1504 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1505 fprintf (FILE, ", r0\n"); \
1509 fprintf (FILE, "\tmovl r2 = "); \
1510 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1511 fprintf (FILE, "\n"); \
1513 fprintf (FILE, "\t;;\n"); \
1514 fprintf (FILE, "\tadd r32 = r2, r32\n"); \
1516 fprintf (FILE, "\tbr "); \
1517 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1518 fprintf (FILE, "\n"); \
1521 /* Output part N of a function descriptor for DECL. For ia64, both
1522 words are emitted with a single relocation, so ignore N > 0. */
1523 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1527 fputs ("\tdata16.ua @iplt(", FILE); \
1528 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1529 fputs (")\n", FILE); \
1533 /* Generating Code for Profiling. */
1535 /* A C statement or compound statement to output to FILE some assembler code to
1536 call the profiling subroutine `mcount'. */
1538 #undef FUNCTION_PROFILER
1539 #define FUNCTION_PROFILER(FILE, LABELNO) \
1542 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1543 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1544 if (TARGET_AUTO_PIC) \
1545 fputs ("\tmovl out3 = @gprel(", FILE); \
1547 fputs ("\taddl out3 = @ltoff(", FILE); \
1548 assemble_name (FILE, buf); \
1549 if (TARGET_AUTO_PIC) \
1550 fputs (");;\n", FILE); \
1552 fputs ("), r1;;\n", FILE); \
1553 fputs ("\tmov out1 = r1\n", FILE); \
1554 fputs ("\tmov out2 = b0\n", FILE); \
1555 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1558 /* Implementing the Varargs Macros. */
1560 /* Define this macro to store the anonymous register arguments into the stack
1561 so that all the arguments appear to have been passed consecutively on the
1564 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1565 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1567 /* Define this macro if the location where a function argument is passed
1568 depends on whether or not it is a named argument. */
1570 #define STRICT_ARGUMENT_NAMING 1
1573 /* Trampolines for Nested Functions. */
1575 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1576 the function containing a non-local goto target. */
1578 #define STACK_SAVEAREA_MODE(LEVEL) \
1579 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1581 /* Output assembler code for a block containing the constant parts of
1582 a trampoline, leaving space for the variable parts.
1584 The trampoline should set the static chain pointer to value placed
1585 into the trampoline and should branch to the specified routine.
1586 To make the normal indirect-subroutine calling convention work,
1587 the trampoline must look like a function descriptor; the first
1588 word being the target address and the second being the target's
1591 We abuse the concept of a global pointer by arranging for it
1592 to point to the data we need to load. The complete trampoline
1593 has the following form:
1595 +-------------------+ \
1596 TRAMP: | __ia64_trampoline | |
1597 +-------------------+ > fake function descriptor
1599 +-------------------+ /
1600 | target descriptor |
1601 +-------------------+
1603 +-------------------+
1606 /* A C expression for the size in bytes of the trampoline, as an integer. */
1608 #define TRAMPOLINE_SIZE 32
1610 /* Alignment required for trampolines, in bits. */
1612 #define TRAMPOLINE_ALIGNMENT 64
1614 /* A C statement to initialize the variable parts of a trampoline. */
1616 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1617 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1619 /* Implicit Calls to Library Routines */
1621 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1622 C) library functions `memcpy' and `memset' rather than the BSD functions
1623 `bcopy' and `bzero'. */
1625 #define TARGET_MEM_FUNCTIONS
1628 /* Addressing Modes */
1630 /* Define this macro if the machine supports post-increment addressing. */
1632 #define HAVE_POST_INCREMENT 1
1633 #define HAVE_POST_DECREMENT 1
1634 #define HAVE_POST_MODIFY_DISP 1
1635 #define HAVE_POST_MODIFY_REG 1
1637 /* A C expression that is 1 if the RTX X is a constant which is a valid
1640 #define CONSTANT_ADDRESS_P(X) 0
1642 /* The max number of registers that can appear in a valid memory address. */
1644 #define MAX_REGS_PER_ADDRESS 2
1646 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1647 RTX) is a legitimate memory address on the target machine for a memory
1648 operand of mode MODE. */
1650 #define LEGITIMATE_ADDRESS_REG(X) \
1651 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1652 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1653 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1655 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1656 (GET_CODE (X) == PLUS \
1657 && rtx_equal_p (R, XEXP (X, 0)) \
1658 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1659 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1660 && INTVAL (XEXP (X, 1)) >= -256 \
1661 && INTVAL (XEXP (X, 1)) < 256)))
1663 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1665 if (LEGITIMATE_ADDRESS_REG (X)) \
1667 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1668 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1669 && XEXP (X, 0) != arg_pointer_rtx) \
1671 else if (GET_CODE (X) == POST_MODIFY \
1672 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1673 && XEXP (X, 0) != arg_pointer_rtx \
1674 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1678 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1679 use as a base register. */
1681 #ifdef REG_OK_STRICT
1682 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1684 #define REG_OK_FOR_BASE_P(X) \
1685 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1688 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1689 use as an index register. This is needed for POST_MODIFY. */
1691 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1693 /* A C compound statement that attempts to replace X with a valid memory
1694 address for an operand of mode MODE.
1696 This must be present, but there is nothing useful to be done here. */
1698 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1700 /* A C statement or compound statement with a conditional `goto LABEL;'
1701 executed if memory address X (an RTX) can have different meanings depending
1702 on the machine mode of the memory reference it is used for or if the address
1703 is valid for some modes but not others. */
1705 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1706 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1709 /* A C expression that is nonzero if X is a legitimate constant for an
1710 immediate operand on the target machine. */
1712 #define LEGITIMATE_CONSTANT_P(X) \
1713 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1714 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1717 /* Condition Code Status */
1719 /* One some machines not all possible comparisons are defined, but you can
1720 convert an invalid comparison into a valid one. */
1721 /* ??? Investigate. See the alpha definition. */
1722 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1725 /* Describing Relative Costs of Operations */
1727 /* A part of a C `switch' statement that describes the relative costs of
1728 constant RTL expressions. */
1730 /* ??? This is incomplete. */
1732 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1734 if ((X) == const0_rtx) \
1736 switch (OUTER_CODE) \
1739 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
1741 if (CONST_OK_FOR_I (INTVAL (X))) \
1743 if (CONST_OK_FOR_J (INTVAL (X))) \
1745 return COSTS_N_INSNS (1); \
1747 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
1749 return COSTS_N_INSNS (1); \
1751 case CONST_DOUBLE: \
1752 return COSTS_N_INSNS (1); \
1756 return COSTS_N_INSNS (3);
1758 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
1760 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1762 /* For multiplies wider than HImode, we have to go to the FPU, \
1763 which normally involves copies. Plus there's the latency \
1764 of the multiply itself, and the latency of the instructions to \
1765 transfer integer regs to FP regs. */ \
1766 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
1767 return COSTS_N_INSNS (10); \
1768 return COSTS_N_INSNS (2); \
1774 return COSTS_N_INSNS (1); \
1779 /* We make divide expensive, so that divide-by-constant will be \
1780 optimized to a multiply. */ \
1781 return COSTS_N_INSNS (60);
1783 /* An expression giving the cost of an addressing mode that contains ADDRESS.
1784 If not defined, the cost is computed from the ADDRESS expression and the
1785 `CONST_COSTS' values. */
1787 #define ADDRESS_COST(ADDRESS) 0
1789 /* A C expression for the cost of moving data from a register in class FROM to
1790 one in class TO, using MODE. */
1792 #define REGISTER_MOVE_COST ia64_register_move_cost
1794 /* A C expression for the cost of moving data of mode M between a
1795 register and memory. */
1796 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1797 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1798 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1800 /* A C expression for the cost of a branch instruction. A value of 1 is the
1801 default; other values are interpreted relative to that. Used by the
1802 if-conversion code as max instruction count. */
1803 /* ??? This requires investigation. The primary effect might be how
1804 many additional insn groups we run into, vs how good the dynamic
1805 branch predictor is. */
1807 #define BRANCH_COST 6
1809 /* Define this macro as a C expression which is nonzero if accessing less than
1810 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1813 #define SLOW_BYTE_ACCESS 1
1815 /* Define this macro if it is as good or better to call a constant function
1816 address than to call an address kept in a register.
1818 Indirect function calls are more expensive that direct function calls, so
1819 don't cse function addresses. */
1821 #define NO_FUNCTION_CSE
1824 /* Dividing the output into sections. */
1826 /* A C expression whose value is a string containing the assembler operation
1827 that should precede instructions and read-only data. */
1829 #define TEXT_SECTION_ASM_OP "\t.text"
1831 /* A C expression whose value is a string containing the assembler operation to
1832 identify the following data as writable initialized data. */
1834 #define DATA_SECTION_ASM_OP "\t.data"
1836 /* If defined, a C expression whose value is a string containing the assembler
1837 operation to identify the following data as uninitialized global data. */
1839 #define BSS_SECTION_ASM_OP "\t.bss"
1841 /* Define this macro if references to a symbol must be treated differently
1842 depending on something about the variable or function named by the symbol
1843 (such as what section it is in). */
1845 #define ENCODE_SECTION_INFO(DECL) ia64_encode_section_info (DECL)
1847 /* If a variable is weakened, made one only or moved into a different
1848 section, it may be necessary to redo the section info to move the
1849 variable out of sdata. */
1851 #define REDO_SECTION_INFO_P(DECL) \
1852 ((TREE_CODE (DECL) == VAR_DECL) \
1853 && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \
1854 || DECL_SECTION_NAME (DECL) != 0))
1856 #define SDATA_NAME_FLAG_CHAR '@'
1858 #define IA64_DEFAULT_GVALUE 8
1860 /* Decode SYM_NAME and store the real name part in VAR, sans the characters
1861 that encode section info. */
1863 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1865 (VAR) = (SYMBOL_NAME); \
1866 if ((VAR)[0] == SDATA_NAME_FLAG_CHAR) \
1868 if ((VAR)[0] == '*') \
1872 /* Position Independent Code. */
1874 /* The register number of the register used to address a table of static data
1875 addresses in memory. */
1877 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1878 gen_rtx_REG (DImode, 1). */
1880 /* ??? Should we set flag_pic? Probably need to define
1881 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1883 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1885 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1886 clobbered by calls. */
1888 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1891 /* The Overall Framework of an Assembler File. */
1893 /* A C string constant describing how to begin a comment in the target
1894 assembler language. The compiler assumes that the comment will end at the
1897 #define ASM_COMMENT_START "//"
1899 /* A C string constant for text to be output before each `asm' statement or
1900 group of consecutive ones. */
1902 /* ??? This won't work with the Intel assembler, because it does not accept
1903 # as a comment start character. However, //APP does not work in gas, so we
1904 can't use that either. Same problem for ASM_APP_OFF below. */
1906 #define ASM_APP_ON "#APP\n"
1908 /* A C string constant for text to be output after each `asm' statement or
1909 group of consecutive ones. */
1911 #define ASM_APP_OFF "#NO_APP\n"
1914 /* Output of Data. */
1916 /* A C statement to output to the stdio stream STREAM an assembler instruction
1917 to assemble a floating-point constant of `TFmode', `DFmode', `SFmode',
1918 respectively, whose value is VALUE. */
1920 /* ??? Must reverse the word order for big-endian code? */
1922 #define ASM_OUTPUT_LONG_DOUBLE(FILE, VALUE) \
1925 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, t); \
1926 fprintf (FILE, "\tdata4 0x%08lx, 0x%08lx, 0x%08lx, 0x%08lx\n", \
1927 t[0] & 0xffffffff, t[1] & 0xffffffff, t[2] & 0xffffffff, 0L);\
1930 /* ??? Must reverse the word order for big-endian code? */
1932 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1935 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, t); \
1936 fprintf (FILE, "\tdata8 0x%08lx%08lx\n", \
1937 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1940 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1943 REAL_VALUE_TO_TARGET_SINGLE (VALUE, t); \
1944 fprintf (FILE, "\tdata4 0x%lx\n", t & 0xffffffff); \
1947 /* A C statement to output to the stdio stream STREAM an assembler instruction
1948 to assemble an integer of 1, 2, 4, or 8 bytes, respectively, whose value
1951 /* This is how to output an assembler line defining a `char' constant. */
1953 #define ASM_OUTPUT_CHAR(FILE, VALUE) \
1955 fprintf (FILE, "%s", ASM_BYTE_OP); \
1956 output_addr_const (FILE, (VALUE)); \
1957 fprintf (FILE, "\n"); \
1960 /* This is how to output an assembler line defining a `short' constant. */
1962 #define ASM_OUTPUT_SHORT(FILE, VALUE) \
1964 fprintf (FILE, "\tdata2\t"); \
1965 output_addr_const (FILE, (VALUE)); \
1966 fprintf (FILE, "\n"); \
1969 /* This is how to output an assembler line defining an `int' constant.
1970 We also handle symbol output here. */
1972 /* ??? For ILP32, also need to handle function addresses here. */
1974 #define ASM_OUTPUT_INT(FILE, VALUE) \
1976 fprintf (FILE, "\tdata4\t"); \
1977 output_addr_const (FILE, (VALUE)); \
1978 fprintf (FILE, "\n"); \
1981 /* This is how to output an assembler line defining a `long' constant.
1982 We also handle symbol output here. */
1984 #define ASM_OUTPUT_DOUBLE_INT(FILE, VALUE) \
1986 fprintf (FILE, "\tdata8\t"); \
1987 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
1988 fprintf (FILE, "@fptr("); \
1989 output_addr_const (FILE, (VALUE)); \
1990 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
1991 fprintf (FILE, ")"); \
1992 fprintf (FILE, "\n"); \
1995 /* This is how to output an assembler line defining a `char' constant
1996 to an xdata segment. */
1998 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
2000 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
2001 output_addr_const (FILE, (VALUE)); \
2002 fprintf (FILE, "\n"); \
2005 /* This is how to output an assembler line defining a `short' constant
2006 to an xdata segment. */
2008 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
2010 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
2011 output_addr_const (FILE, (VALUE)); \
2012 fprintf (FILE, "\n"); \
2015 /* This is how to output an assembler line defining an `int' constant
2016 to an xdata segment. We also handle symbol output here. */
2018 /* ??? For ILP32, also need to handle function addresses here. */
2020 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
2022 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
2023 output_addr_const (FILE, (VALUE)); \
2024 fprintf (FILE, "\n"); \
2027 /* This is how to output an assembler line defining a `long' constant
2028 to an xdata segment. We also handle symbol output here. */
2030 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
2032 int need_closing_paren = 0; \
2033 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
2034 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
2035 && GET_CODE (VALUE) == SYMBOL_REF) \
2037 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
2038 need_closing_paren = 1; \
2040 output_addr_const (FILE, VALUE); \
2041 if (need_closing_paren) \
2042 fprintf (FILE, ")"); \
2043 fprintf (FILE, "\n"); \
2047 /* A C statement to output to the stdio stream STREAM an assembler instruction
2048 to assemble a single byte containing the number VALUE. */
2050 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
2051 fprintf (STREAM, "%s0x%x\n", ASM_BYTE_OP, (int)(VALUE) & 0xff)
2054 /* Output of Uninitialized Variables. */
2056 /* This is all handled by svr4.h. */
2059 /* Output and Generation of Labels. */
2061 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
2062 assembler definition of a label named NAME. */
2064 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
2065 why ia64_asm_output_label exists. */
2067 extern int ia64_asm_output_label;
2068 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
2070 ia64_asm_output_label = 1; \
2071 assemble_name (STREAM, NAME); \
2072 fputs (":\n", STREAM); \
2073 ia64_asm_output_label = 0; \
2076 /* A C statement (sans semicolon) to output to the stdio stream STREAM some
2077 commands that will make the label NAME global; that is, available for
2078 reference from other files. */
2080 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2082 fputs ("\t.global ", STREAM); \
2083 assemble_name (STREAM, NAME); \
2084 fputs ("\n", STREAM); \
2087 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
2088 necessary for declaring the name of an external symbol named NAME which is
2089 referenced in this compilation but not defined. */
2091 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
2092 ia64_asm_output_external (FILE, DECL, NAME)
2094 /* A C statement to store into the string STRING a label whose name is made
2095 from the string PREFIX and the number NUM. */
2097 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
2099 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
2102 /* A C expression to assign to OUTVAR (which is a variable of type `char *') a
2103 newly allocated string made from the string NAME and the number NUMBER, with
2104 some suitable punctuation added. */
2106 /* ??? Not sure if using a ? in the name for Intel as is safe. */
2108 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
2110 (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \
2111 sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \
2115 /* A C statement to output to the stdio stream STREAM assembler code which
2116 defines (equates) the symbol NAME to have the value VALUE. */
2118 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
2120 assemble_name (STREAM, NAME); \
2121 fputs (" = ", STREAM); \
2122 assemble_name (STREAM, VALUE); \
2123 fputc ('\n', STREAM); \
2127 /* Macros Controlling Initialization Routines. */
2129 /* This is handled by svr4.h and sysv4.h. */
2132 /* Output of Assembler Instructions. */
2134 /* A C initializer containing the assembler's names for the machine registers,
2135 each one as a C string constant. */
2137 #define REGISTER_NAMES \
2139 /* General registers. */ \
2140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
2141 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
2142 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
2144 /* Local registers. */ \
2145 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
2146 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
2147 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
2148 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
2149 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
2150 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
2151 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
2152 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
2153 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
2154 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
2155 /* Input registers. */ \
2156 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
2157 /* Output registers. */ \
2158 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
2159 /* Floating-point registers. */ \
2160 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
2161 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
2162 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
2163 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
2164 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
2165 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
2166 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
2167 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
2168 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
2169 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
2170 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
2171 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
2172 "f120","f121","f122","f123","f124","f125","f126","f127", \
2173 /* Predicate registers. */ \
2174 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
2175 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
2176 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
2177 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
2178 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
2179 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
2180 "p60", "p61", "p62", "p63", \
2181 /* Branch registers. */ \
2182 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
2183 /* Frame pointer. Return address. */ \
2184 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
2187 /* If defined, a C initializer for an array of structures containing a name and
2188 a register number. This macro defines additional names for hard registers,
2189 thus allowing the `asm' option in declarations to refer to registers using
2192 #define ADDITIONAL_REGISTER_NAMES \
2194 { "gp", R_GR (1) }, \
2195 { "sp", R_GR (12) }, \
2196 { "in0", IN_REG (0) }, \
2197 { "in1", IN_REG (1) }, \
2198 { "in2", IN_REG (2) }, \
2199 { "in3", IN_REG (3) }, \
2200 { "in4", IN_REG (4) }, \
2201 { "in5", IN_REG (5) }, \
2202 { "in6", IN_REG (6) }, \
2203 { "in7", IN_REG (7) }, \
2204 { "out0", OUT_REG (0) }, \
2205 { "out1", OUT_REG (1) }, \
2206 { "out2", OUT_REG (2) }, \
2207 { "out3", OUT_REG (3) }, \
2208 { "out4", OUT_REG (4) }, \
2209 { "out5", OUT_REG (5) }, \
2210 { "out6", OUT_REG (6) }, \
2211 { "out7", OUT_REG (7) }, \
2212 { "loc0", LOC_REG (0) }, \
2213 { "loc1", LOC_REG (1) }, \
2214 { "loc2", LOC_REG (2) }, \
2215 { "loc3", LOC_REG (3) }, \
2216 { "loc4", LOC_REG (4) }, \
2217 { "loc5", LOC_REG (5) }, \
2218 { "loc6", LOC_REG (6) }, \
2219 { "loc7", LOC_REG (7) }, \
2220 { "loc8", LOC_REG (8) }, \
2221 { "loc9", LOC_REG (9) }, \
2222 { "loc10", LOC_REG (10) }, \
2223 { "loc11", LOC_REG (11) }, \
2224 { "loc12", LOC_REG (12) }, \
2225 { "loc13", LOC_REG (13) }, \
2226 { "loc14", LOC_REG (14) }, \
2227 { "loc15", LOC_REG (15) }, \
2228 { "loc16", LOC_REG (16) }, \
2229 { "loc17", LOC_REG (17) }, \
2230 { "loc18", LOC_REG (18) }, \
2231 { "loc19", LOC_REG (19) }, \
2232 { "loc20", LOC_REG (20) }, \
2233 { "loc21", LOC_REG (21) }, \
2234 { "loc22", LOC_REG (22) }, \
2235 { "loc23", LOC_REG (23) }, \
2236 { "loc24", LOC_REG (24) }, \
2237 { "loc25", LOC_REG (25) }, \
2238 { "loc26", LOC_REG (26) }, \
2239 { "loc27", LOC_REG (27) }, \
2240 { "loc28", LOC_REG (28) }, \
2241 { "loc29", LOC_REG (29) }, \
2242 { "loc30", LOC_REG (30) }, \
2243 { "loc31", LOC_REG (31) }, \
2244 { "loc32", LOC_REG (32) }, \
2245 { "loc33", LOC_REG (33) }, \
2246 { "loc34", LOC_REG (34) }, \
2247 { "loc35", LOC_REG (35) }, \
2248 { "loc36", LOC_REG (36) }, \
2249 { "loc37", LOC_REG (37) }, \
2250 { "loc38", LOC_REG (38) }, \
2251 { "loc39", LOC_REG (39) }, \
2252 { "loc40", LOC_REG (40) }, \
2253 { "loc41", LOC_REG (41) }, \
2254 { "loc42", LOC_REG (42) }, \
2255 { "loc43", LOC_REG (43) }, \
2256 { "loc44", LOC_REG (44) }, \
2257 { "loc45", LOC_REG (45) }, \
2258 { "loc46", LOC_REG (46) }, \
2259 { "loc47", LOC_REG (47) }, \
2260 { "loc48", LOC_REG (48) }, \
2261 { "loc49", LOC_REG (49) }, \
2262 { "loc50", LOC_REG (50) }, \
2263 { "loc51", LOC_REG (51) }, \
2264 { "loc52", LOC_REG (52) }, \
2265 { "loc53", LOC_REG (53) }, \
2266 { "loc54", LOC_REG (54) }, \
2267 { "loc55", LOC_REG (55) }, \
2268 { "loc56", LOC_REG (56) }, \
2269 { "loc57", LOC_REG (57) }, \
2270 { "loc58", LOC_REG (58) }, \
2271 { "loc59", LOC_REG (59) }, \
2272 { "loc60", LOC_REG (60) }, \
2273 { "loc61", LOC_REG (61) }, \
2274 { "loc62", LOC_REG (62) }, \
2275 { "loc63", LOC_REG (63) }, \
2276 { "loc64", LOC_REG (64) }, \
2277 { "loc65", LOC_REG (65) }, \
2278 { "loc66", LOC_REG (66) }, \
2279 { "loc67", LOC_REG (67) }, \
2280 { "loc68", LOC_REG (68) }, \
2281 { "loc69", LOC_REG (69) }, \
2282 { "loc70", LOC_REG (70) }, \
2283 { "loc71", LOC_REG (71) }, \
2284 { "loc72", LOC_REG (72) }, \
2285 { "loc73", LOC_REG (73) }, \
2286 { "loc74", LOC_REG (74) }, \
2287 { "loc75", LOC_REG (75) }, \
2288 { "loc76", LOC_REG (76) }, \
2289 { "loc77", LOC_REG (77) }, \
2290 { "loc78", LOC_REG (78) }, \
2291 { "loc79", LOC_REG (79) }, \
2294 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2295 for an instruction operand X. X is an RTL expression. */
2297 #define PRINT_OPERAND(STREAM, X, CODE) \
2298 ia64_print_operand (STREAM, X, CODE)
2300 /* A C expression which evaluates to true if CODE is a valid punctuation
2301 character for use in the `PRINT_OPERAND' macro. */
2303 /* ??? Keep this around for now, as we might need it later. */
2305 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2306 ((CODE) == '+' || (CODE) == ',')
2308 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2309 for an instruction operand that is a memory reference whose address is X. X
2310 is an RTL expression. */
2312 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2313 ia64_print_operand_address (STREAM, X)
2315 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2316 `%I' options of `asm_fprintf' (see `final.c'). */
2318 #define REGISTER_PREFIX ""
2319 #define LOCAL_LABEL_PREFIX "."
2320 #define USER_LABEL_PREFIX ""
2321 #define IMMEDIATE_PREFIX ""
2324 /* Output of dispatch tables. */
2326 /* This macro should be provided on machines where the addresses in a dispatch
2327 table are relative to the table's own address. */
2329 /* ??? Depends on the pointer size. */
2331 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2332 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
2334 /* This is how to output an element of a case-vector that is absolute.
2335 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2337 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2339 /* Jump tables only need 8 byte alignment. */
2341 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2344 /* Assembler Commands for Exception Regions. */
2346 /* Select a format to encode pointers in exception handling data. CODE
2347 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2348 true if the symbol may be affected by dynamic relocations. */
2349 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2350 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2351 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2353 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2354 indirect are handled automatically. */
2355 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2357 const char *reltag = NULL; \
2358 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2359 reltag = "@segrel("; \
2360 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2361 reltag = "@gprel("; \
2364 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2365 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2366 : (abort (), "")), FILE); \
2367 fputs (reltag, FILE); \
2368 assemble_name (FILE, XSTR (ADDR, 0)); \
2369 fputc (')', FILE); \
2375 /* Assembler Commands for Alignment. */
2377 /* ??? Investigate. */
2379 /* The alignment (log base 2) to put in front of LABEL, which follows
2382 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2384 /* The desired alignment for the location counter at the beginning
2387 /* #define LOOP_ALIGN(LABEL) */
2389 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2390 section because it fails put zeros in the bytes that are skipped. */
2392 #define ASM_NO_SKIP_IN_TEXT 1
2394 /* A C statement to output to the stdio stream STREAM an assembler command to
2395 advance the location counter to a multiple of 2 to the POWER bytes. */
2397 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2398 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2401 /* Macros Affecting all Debug Formats. */
2403 /* This is handled in svr4.h and sysv4.h. */
2406 /* Specific Options for DBX Output. */
2408 /* This is handled by dbxelf.h which is included by svr4.h. */
2411 /* Open ended Hooks for DBX Output. */
2416 /* File names in DBX format. */
2421 /* Macros for SDB and Dwarf Output. */
2423 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2424 output in response to the `-g' option. */
2426 #define DWARF2_DEBUGGING_INFO
2428 /* C string constants giving the pseudo-op to use for a sequence of
2429 2, 4, and 8 byte unaligned constants. dwarf2out.c needs these. */
2431 #define UNALIGNED_SHORT_ASM_OP "\tdata2.ua\t"
2432 #define UNALIGNED_INT_ASM_OP "\tdata4.ua\t"
2433 #define UNALIGNED_DOUBLE_INT_ASM_OP "\tdata8.ua\t"
2435 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2437 /* Use tags for debug info labels, so that they don't break instruction
2438 bundles. This also avoids getting spurious DV warnings from the
2439 assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we
2440 add brackets around the label. */
2442 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2443 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2445 /* Use section-relative relocations for debugging offsets. Unlike other
2446 targets that fake this by putting the section VMA at 0, IA-64 has
2447 proper relocations for them. */
2448 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2450 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2451 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2452 : (abort (), "")), FILE); \
2453 fputs ("@secrel(", FILE); \
2454 assemble_name (FILE, LABEL); \
2455 fputc (')', FILE); \
2458 /* Emit a PC-relative relocation. */
2459 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2461 fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
2462 : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
2463 : (abort (), "")), FILE); \
2464 fputs ("@pcrel(", FILE); \
2465 assemble_name (FILE, LABEL); \
2466 fputc (')', FILE); \
2469 /* Cross Compilation and Floating Point. */
2471 /* Define to enable software floating point emulation. */
2472 #define REAL_ARITHMETIC
2475 /* Register Renaming Parameters. */
2477 /* A C expression that is nonzero if hard register number REGNO2 can be
2478 considered for use as a rename register for REGNO1 */
2480 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2481 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2483 /* Define this macro if the compiler should use extended basic blocks
2484 when renaming registers. Define this macro if the target has predicate
2487 #define RENAME_EXTENDED_BLOCKS
2490 /* Miscellaneous Parameters. */
2492 /* Define this if you have defined special-purpose predicates in the file
2493 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2494 expressions matched by the predicate. */
2496 #define PREDICATE_CODES \
2497 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2498 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2499 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2500 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2501 { "function_operand", {SYMBOL_REF}}, \
2502 { "setjmp_operand", {SYMBOL_REF}}, \
2503 { "destination_operand", {SUBREG, REG, MEM}}, \
2504 { "not_postinc_memory_operand", {MEM}}, \
2505 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2506 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2507 { "gr_register_operand", {SUBREG, REG}}, \
2508 { "fr_register_operand", {SUBREG, REG}}, \
2509 { "grfr_register_operand", {SUBREG, REG}}, \
2510 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2511 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2512 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2513 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2514 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2515 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2516 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2517 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2518 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2520 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2522 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2523 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2524 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2525 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2527 { "shladd_operand", {CONST_INT}}, \
2528 { "fetchadd_operand", {CONST_INT}}, \
2529 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2530 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2531 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2532 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2533 { "predicate_operator", {NE, EQ}}, \
2534 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2535 { "ar_lc_reg_operand", {REG}}, \
2536 { "ar_ccv_reg_operand", {REG}}, \
2537 { "ar_pfs_reg_operand", {REG}}, \
2538 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2539 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2540 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
2542 /* An alias for a machine mode name. This is the machine mode that elements of
2543 a jump-table should have. */
2545 #define CASE_VECTOR_MODE Pmode
2547 /* Define as C expression which evaluates to nonzero if the tablejump
2548 instruction expects the table to contain offsets from the address of the
2551 #define CASE_VECTOR_PC_RELATIVE 1
2553 /* Define this macro if operations between registers with integral mode smaller
2554 than a word are always performed on the entire register. */
2556 #define WORD_REGISTER_OPERATIONS
2558 /* Define this macro to be a C expression indicating when insns that read
2559 memory in MODE, an integral mode narrower than a word, set the bits outside
2560 of MODE to be either the sign-extension or the zero-extension of the data
2563 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2565 /* An alias for a tree code that should be used by default for conversion of
2566 floating point values to fixed point. */
2568 /* ??? Looks like this macro is obsolete and should be deleted everywhere. */
2570 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2572 /* An alias for a tree code that is the easiest kind of division to compile
2573 code for in the general case. */
2575 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2577 /* The maximum number of bytes that a single instruction can move quickly from
2578 memory to memory. */
2581 /* A C expression which is nonzero if on this machine it is safe to "convert"
2582 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2583 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2585 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2587 /* A C expression describing the value returned by a comparison operator with
2588 an integral mode and stored by a store-flag instruction (`sCOND') when the
2589 condition is true. */
2591 /* ??? Investigate using -1 instead of 1. */
2593 #define STORE_FLAG_VALUE 1
2595 /* An alias for the machine mode for pointers. */
2597 /* ??? This would change if we had ILP32 support. */
2599 #define Pmode DImode
2601 /* An alias for the machine mode used for memory references to functions being
2602 called, in `call' RTL expressions. */
2604 #define FUNCTION_MODE Pmode
2606 /* Define this macro to handle System V style pragmas: #pragma pack and
2607 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2610 /* If this architecture supports prefetch, define this to be the number of
2611 prefetch commands that can be executed in parallel.
2613 ??? This number is bogus and needs to be replaced before the value is
2614 actually used in optimizations. */
2616 #define SIMULTANEOUS_PREFETCHES 6
2618 /* If this architecture supports prefetch, define this to be the size of
2619 the cache line that is prefetched. */
2621 #define PREFETCH_BLOCK 32
2623 #define HANDLE_SYSV_PRAGMA
2625 /* In rare cases, correct code generation requires extra machine dependent
2626 processing between the second jump optimization pass and delayed branch
2627 scheduling. On those machines, define this macro as a C statement to act on
2628 the code starting at INSN. */
2630 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2632 /* A C expression for the maximum number of instructions to execute via
2633 conditional execution instructions instead of a branch. A value of
2634 BRANCH_COST+1 is the default if the machine does not use
2635 cc0, and 1 if it does use cc0. */
2636 /* ??? Investigate. */
2637 #define MAX_CONDITIONAL_EXECUTE 12
2639 extern int ia64_final_schedule;
2641 #define IA64_UNWIND_INFO 1
2642 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2644 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2646 /* This function contains machine specific function data. */
2647 struct machine_function
2649 /* The new stack pointer when unwinding from EH. */
2650 struct rtx_def* ia64_eh_epilogue_sp;
2652 /* The new bsp value when unwinding from EH. */
2653 struct rtx_def* ia64_eh_epilogue_bsp;
2655 /* The GP value save register. */
2656 struct rtx_def* ia64_gp_save;
2658 /* The number of varargs registers to save. */
2665 IA64_BUILTIN_SYNCHRONIZE,
2667 IA64_BUILTIN_FETCH_AND_ADD_SI,
2668 IA64_BUILTIN_FETCH_AND_SUB_SI,
2669 IA64_BUILTIN_FETCH_AND_OR_SI,
2670 IA64_BUILTIN_FETCH_AND_AND_SI,
2671 IA64_BUILTIN_FETCH_AND_XOR_SI,
2672 IA64_BUILTIN_FETCH_AND_NAND_SI,
2674 IA64_BUILTIN_ADD_AND_FETCH_SI,
2675 IA64_BUILTIN_SUB_AND_FETCH_SI,
2676 IA64_BUILTIN_OR_AND_FETCH_SI,
2677 IA64_BUILTIN_AND_AND_FETCH_SI,
2678 IA64_BUILTIN_XOR_AND_FETCH_SI,
2679 IA64_BUILTIN_NAND_AND_FETCH_SI,
2681 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2682 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2684 IA64_BUILTIN_SYNCHRONIZE_SI,
2686 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2688 IA64_BUILTIN_LOCK_RELEASE_SI,
2690 IA64_BUILTIN_FETCH_AND_ADD_DI,
2691 IA64_BUILTIN_FETCH_AND_SUB_DI,
2692 IA64_BUILTIN_FETCH_AND_OR_DI,
2693 IA64_BUILTIN_FETCH_AND_AND_DI,
2694 IA64_BUILTIN_FETCH_AND_XOR_DI,
2695 IA64_BUILTIN_FETCH_AND_NAND_DI,
2697 IA64_BUILTIN_ADD_AND_FETCH_DI,
2698 IA64_BUILTIN_SUB_AND_FETCH_DI,
2699 IA64_BUILTIN_OR_AND_FETCH_DI,
2700 IA64_BUILTIN_AND_AND_FETCH_DI,
2701 IA64_BUILTIN_XOR_AND_FETCH_DI,
2702 IA64_BUILTIN_NAND_AND_FETCH_DI,
2704 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2705 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2707 IA64_BUILTIN_SYNCHRONIZE_DI,
2709 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2711 IA64_BUILTIN_LOCK_RELEASE_DI,
2714 IA64_BUILTIN_FLUSHRS
2717 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2719 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
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