1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
34 /* Target CPU builtins. */
35 #define TARGET_CPU_CPP_BUILTINS() \
37 builtin_assert("cpu=ia64"); \
38 builtin_assert("machine=ia64"); \
39 builtin_define("__ia64"); \
40 builtin_define("__ia64__"); \
41 builtin_define("__itanium__"); \
42 builtin_define("__ELF__"); \
45 builtin_define("_LP64"); \
46 builtin_define("__LP64__"); \
48 if (TARGET_BIG_ENDIAN) \
49 builtin_define("__BIG_ENDIAN__"); \
53 { "asm_extra", ASM_EXTRA_SPEC },
55 #define CC1_SPEC "%(cc1_cpu) "
57 #define ASM_EXTRA_SPEC ""
60 /* This declaration should be present. */
61 extern int target_flags;
63 /* This series of macros is to allow compiler command arguments to enable or
64 disable the use of optional features of the target machine. */
66 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
68 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
70 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
72 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
74 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
76 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
78 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
80 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
82 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
84 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
86 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
88 #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
90 #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
92 #define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
94 #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
96 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
98 #define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */
100 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
102 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
104 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
106 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
108 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
110 #define TARGET_ILP32 (target_flags & MASK_ILP32)
112 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
114 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
116 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
118 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
120 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
122 #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
124 #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
126 #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
128 #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
130 #define TARGET_INLINE_FLOAT_DIV \
131 (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
133 #define TARGET_INLINE_INT_DIV \
134 (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
136 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
138 extern int ia64_tls_size;
139 #define TARGET_TLS14 (ia64_tls_size == 14)
140 #define TARGET_TLS22 (ia64_tls_size == 22)
141 #define TARGET_TLS64 (ia64_tls_size == 64)
142 #define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
144 #define TARGET_HPUX_LD 0
146 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
147 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
150 /* This macro defines names of command options to set and clear bits in
151 `target_flags'. Its definition is an initializer with a subgrouping for
152 each command option. */
154 #define TARGET_SWITCHES \
156 { "big-endian", MASK_BIG_ENDIAN, \
157 N_("Generate big endian code") }, \
158 { "little-endian", -MASK_BIG_ENDIAN, \
159 N_("Generate little endian code") }, \
160 { "gnu-as", MASK_GNU_AS, \
161 N_("Generate code for GNU as") }, \
162 { "no-gnu-as", -MASK_GNU_AS, \
163 N_("Generate code for Intel as") }, \
164 { "gnu-ld", MASK_GNU_LD, \
165 N_("Generate code for GNU ld") }, \
166 { "no-gnu-ld", -MASK_GNU_LD, \
167 N_("Generate code for Intel ld") }, \
168 { "no-pic", MASK_NO_PIC, \
169 N_("Generate code without GP reg") }, \
170 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
171 N_("Emit stop bits before and after volatile extended asms") }, \
172 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
173 N_("Don't emit stop bits before and after volatile extended asms") }, \
174 { "b-step", MASK_B_STEP, \
175 N_("Emit code for Itanium (TM) processor B step")}, \
176 { "register-names", MASK_REG_NAMES, \
177 N_("Use in/loc/out register names")}, \
178 { "no-sdata", MASK_NO_SDATA, \
179 N_("Disable use of sdata/scommon/sbss")}, \
180 { "sdata", -MASK_NO_SDATA, \
181 N_("Enable use of sdata/scommon/sbss")}, \
182 { "constant-gp", MASK_CONST_GP, \
183 N_("gp is constant (but save/restore gp on indirect calls)") }, \
184 { "auto-pic", MASK_AUTO_PIC, \
185 N_("Generate self-relocatable code") }, \
186 { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
187 N_("Generate inline floating point division, optimize for latency") },\
188 { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
189 N_("Generate inline floating point division, optimize for throughput") },\
190 { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
191 N_("Generate inline integer division, optimize for latency") }, \
192 { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
193 N_("Generate inline integer division, optimize for throughput") },\
194 { "dwarf2-asm", MASK_DWARF2_ASM, \
195 N_("Enable Dwarf 2 line debug info via GNU as")}, \
196 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
197 N_("Disable Dwarf 2 line debug info via GNU as")}, \
198 { "early-stop-bits", MASK_EARLY_STOP_BITS, \
199 N_("Enable earlier placing stop bits for better scheduling")}, \
200 { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
201 N_("Disable earlier placing stop bits")}, \
203 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
207 /* Default target_flags if no switches are specified */
209 #ifndef TARGET_DEFAULT
210 #define TARGET_DEFAULT MASK_DWARF2_ASM
213 #ifndef TARGET_CPU_DEFAULT
214 #define TARGET_CPU_DEFAULT 0
217 #ifndef SUBTARGET_SWITCHES
218 #define SUBTARGET_SWITCHES
221 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
222 options that have values. Its definition is an initializer with a
223 subgrouping for each command option. */
225 extern const char *ia64_fixed_range_string;
226 extern const char *ia64_tls_size_string;
228 /* Which processor to schedule for. The cpu attribute defines a list
229 that mirrors this list, so changes to i64.md must be made at the
234 PROCESSOR_ITANIUM, /* Original Itanium. */
239 extern enum processor_type ia64_tune;
241 extern const char *ia64_tune_string;
243 #define TARGET_OPTIONS \
245 { "fixed-range=", &ia64_fixed_range_string, \
246 N_("Specify range of registers to make fixed")}, \
247 { "tls-size=", &ia64_tls_size_string, \
248 N_("Specify bit size of immediate TLS offsets")}, \
249 { "tune=", &ia64_tune_string, \
250 N_("Schedule code for given CPU")}, \
253 /* Sometimes certain combinations of command options do not make sense on a
254 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
255 take account of this. This macro, if defined, is executed once just after
256 all the command options have been parsed. */
258 #define OVERRIDE_OPTIONS ia64_override_options ()
260 /* Some machines may desire to change what optimizations are performed for
261 various optimization levels. This macro, if defined, is executed once just
262 after the optimization level is determined and before the remainder of the
263 command options have been parsed. Values set in this macro are used as the
264 default values for the other command line options. */
266 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
268 /* Driver configuration */
270 /* A C string constant that tells the GNU CC driver program options to pass to
271 `cc1'. It can also specify how to translate options you give to GNU CC into
272 options for GNU CC to pass to the `cc1'. */
275 #define CC1_SPEC "%{G*}"
277 /* A C string constant that tells the GNU CC driver program options to pass to
278 `cc1plus'. It can also specify how to translate options you give to GNU CC
279 into options for GNU CC to pass to the `cc1plus'. */
281 /* #define CC1PLUS_SPEC "" */
285 /* Define this macro to have the value 1 if the most significant bit in a byte
286 has the lowest number; otherwise define it to have the value zero. */
288 #define BITS_BIG_ENDIAN 0
290 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
292 /* Define this macro to have the value 1 if, in a multiword object, the most
293 significant word has the lowest number. */
295 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
297 #if defined(__BIG_ENDIAN__)
298 #define LIBGCC2_WORDS_BIG_ENDIAN 1
300 #define LIBGCC2_WORDS_BIG_ENDIAN 0
303 #define UNITS_PER_WORD 8
305 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
307 /* A C expression whose value is zero if pointers that need to be extended
308 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
309 they are zero-extended and negative one if there is a ptr_extend operation.
311 You need not define this macro if the `POINTER_SIZE' is equal to the width
313 /* Need this for 32 bit pointers, see hpux.h for setting it. */
314 /* #define POINTERS_EXTEND_UNSIGNED */
316 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
317 which has the specified mode and signedness is to be stored in a register.
318 This macro is only called when TYPE is a scalar type. */
319 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
322 if (GET_MODE_CLASS (MODE) == MODE_INT \
323 && GET_MODE_SIZE (MODE) < 4) \
328 /* ??? ABI doesn't allow us to define this. */
329 /* #define PROMOTE_FUNCTION_ARGS */
331 /* ??? ABI doesn't allow us to define this. */
332 /* #define PROMOTE_FUNCTION_RETURN */
334 #define PARM_BOUNDARY 64
336 /* Define this macro if you wish to preserve a certain alignment for the stack
337 pointer. The definition is a C expression for the desired alignment
338 (measured in bits). */
340 #define STACK_BOUNDARY 128
342 /* Align frames on double word boundaries */
343 #ifndef IA64_STACK_ALIGN
344 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
347 #define FUNCTION_BOUNDARY 128
349 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
350 128 bit integers all require 128 bit alignment. */
351 #define BIGGEST_ALIGNMENT 128
353 /* If defined, a C expression to compute the alignment for a static variable.
354 TYPE is the data type, and ALIGN is the alignment that the object
355 would ordinarily have. The value of this macro is used instead of that
356 alignment to align the object. */
358 #define DATA_ALIGNMENT(TYPE, ALIGN) \
359 (TREE_CODE (TYPE) == ARRAY_TYPE \
360 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
361 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
363 /* If defined, a C expression to compute the alignment given to a constant that
364 is being placed in memory. CONSTANT is the constant and ALIGN is the
365 alignment that the object would ordinarily have. The value of this macro is
366 used instead of that alignment to align the object. */
368 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
369 (TREE_CODE (EXP) == STRING_CST \
370 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
372 #define STRICT_ALIGNMENT 1
374 /* Define this if you wish to imitate the way many other C compilers handle
375 alignment of bitfields and the structures that contain them.
376 The behavior is that the type written for a bit-field (`int', `short', or
377 other integer type) imposes an alignment for the entire structure, as if the
378 structure really did contain an ordinary field of that type. In addition,
379 the bit-field is placed within the structure so that it would fit within such
380 a field, not crossing a boundary for it. */
381 #define PCC_BITFIELD_TYPE_MATTERS 1
383 /* An integer expression for the size in bits of the largest integer machine
384 mode that should actually be used. */
386 /* Allow pairs of registers to be used, which is the intent of the default. */
387 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
389 /* By default, the C++ compiler will use function addresses in the
390 vtable entries. Setting this nonzero tells the compiler to use
391 function descriptors instead. The value of this macro says how
392 many words wide the descriptor is (normally 2). It is assumed
393 that the address of a function descriptor may be treated as a
394 pointer to a function.
396 For reasons known only to HP, the vtable entries (as opposed to
397 normal function descriptors) are 16 bytes wide in 32-bit mode as
398 well, even though the 3rd and 4th words are unused. */
399 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
401 /* Due to silliness in the HPUX linker, vtable entries must be
402 8-byte aligned even in 32-bit mode. Rather than create multiple
403 ABIs, force this restriction on everyone else too. */
404 #define TARGET_VTABLE_ENTRY_ALIGN 64
406 /* Due to the above, we need extra padding for the data entries below 0
407 to retain the alignment of the descriptors. */
408 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
410 /* Layout of Source Language Data Types */
412 #define INT_TYPE_SIZE 32
414 #define SHORT_TYPE_SIZE 16
416 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
418 #define MAX_LONG_TYPE_SIZE 64
420 #define LONG_LONG_TYPE_SIZE 64
422 #define FLOAT_TYPE_SIZE 32
424 #define DOUBLE_TYPE_SIZE 64
426 #define LONG_DOUBLE_TYPE_SIZE 128
428 /* By default we use the 80-bit Intel extended float format packaged
429 in a 128-bit entity. */
430 #define INTEL_EXTENDED_IEEE_FORMAT 1
432 #define DEFAULT_SIGNED_CHAR 1
434 /* A C expression for a string describing the name of the data type to use for
435 size values. The typedef name `size_t' is defined using the contents of the
437 /* ??? Needs to be defined for P64 code. */
438 /* #define SIZE_TYPE */
440 /* A C expression for a string describing the name of the data type to use for
441 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
442 defined using the contents of the string. See `SIZE_TYPE' above for more
444 /* ??? Needs to be defined for P64 code. */
445 /* #define PTRDIFF_TYPE */
447 /* A C expression for a string describing the name of the data type to use for
448 wide characters. The typedef name `wchar_t' is defined using the contents
449 of the string. See `SIZE_TYPE' above for more information. */
450 /* #define WCHAR_TYPE */
452 /* A C expression for the size in bits of the data type for wide characters.
453 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
454 /* #define WCHAR_TYPE_SIZE */
457 /* Register Basics */
459 /* Number of hardware registers known to the compiler.
460 We have 128 general registers, 128 floating point registers,
461 64 predicate registers, 8 branch registers, one frame pointer,
462 and several "application" registers. */
464 #define FIRST_PSEUDO_REGISTER 335
466 /* Ranges for the various kinds of registers. */
467 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
468 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
469 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
470 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
471 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
472 #define GENERAL_REGNO_P(REGNO) \
473 (GR_REGNO_P (REGNO) \
474 || (REGNO) == FRAME_POINTER_REGNUM \
475 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
477 #define GR_REG(REGNO) ((REGNO) + 0)
478 #define FR_REG(REGNO) ((REGNO) + 128)
479 #define PR_REG(REGNO) ((REGNO) + 256)
480 #define BR_REG(REGNO) ((REGNO) + 320)
481 #define OUT_REG(REGNO) ((REGNO) + 120)
482 #define IN_REG(REGNO) ((REGNO) + 112)
483 #define LOC_REG(REGNO) ((REGNO) + 32)
485 #define AR_CCV_REGNUM 330
486 #define AR_UNAT_REGNUM 331
487 #define AR_PFS_REGNUM 332
488 #define AR_LC_REGNUM 333
489 #define AR_EC_REGNUM 334
491 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
492 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
493 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
495 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
496 || (REGNO) == AR_UNAT_REGNUM)
497 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
498 && (REGNO) < FIRST_PSEUDO_REGISTER)
499 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
500 && (REGNO) < FIRST_PSEUDO_REGISTER)
503 /* ??? Don't really need two sets of macros. I like this one better because
504 it is less typing. */
505 #define R_GR(REGNO) GR_REG (REGNO)
506 #define R_FR(REGNO) FR_REG (REGNO)
507 #define R_PR(REGNO) PR_REG (REGNO)
508 #define R_BR(REGNO) BR_REG (REGNO)
510 /* An initializer that says which registers are used for fixed purposes all
511 throughout the compiled code and are therefore not available for general
515 r1: global pointer (gp)
516 r12: stack pointer (sp)
517 r13: thread pointer (tp)
521 fp: eliminable frame pointer */
523 /* The last 16 stacked regs are reserved for the 8 input and 8 output
526 #define FIXED_REGISTERS \
527 { /* General registers. */ \
528 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
534 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
536 /* Floating-point registers. */ \
537 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
540 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
543 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
545 /* Predicate registers. */ \
546 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
550 /* Branch registers. */ \
551 0, 0, 0, 0, 0, 0, 0, 0, \
552 /*FP RA CCV UNAT PFS LC EC */ \
553 1, 1, 1, 1, 1, 0, 1 \
556 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
557 (in general) by function calls as well as for fixed registers. This
558 macro therefore identifies the registers that are not available for
559 general allocation of values that must live across function calls. */
561 #define CALL_USED_REGISTERS \
562 { /* General registers. */ \
563 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
567 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
570 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
571 /* Floating-point registers. */ \
572 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
573 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
580 /* Predicate registers. */ \
581 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
585 /* Branch registers. */ \
586 1, 0, 0, 0, 0, 0, 1, 1, \
587 /*FP RA CCV UNAT PFS LC EC */ \
588 1, 1, 1, 1, 1, 0, 1 \
591 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
592 problem which makes CALL_USED_REGISTERS *always* include
593 all the FIXED_REGISTERS. Until this problem has been
594 resolved this macro can be used to overcome this situation.
595 In particular, block_propagate() requires this list
596 be accurate, or we can remove registers which should be live.
597 This macro is used in regs_invalidated_by_call. */
599 #define CALL_REALLY_USED_REGISTERS \
600 { /* General registers. */ \
601 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
608 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
609 /* Floating-point registers. */ \
610 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
611 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
612 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
614 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
615 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
616 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
617 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
618 /* Predicate registers. */ \
619 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
620 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
621 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
623 /* Branch registers. */ \
624 1, 0, 0, 0, 0, 0, 1, 1, \
625 /*FP RA CCV UNAT PFS LC EC */ \
626 0, 0, 1, 0, 1, 0, 0 \
630 /* Define this macro if the target machine has register windows. This C
631 expression returns the register number as seen by the called function
632 corresponding to the register number OUT as seen by the calling function.
633 Return OUT if register number OUT is not an outbound register. */
635 #define INCOMING_REGNO(OUT) \
636 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
638 /* Define this macro if the target machine has register windows. This C
639 expression returns the register number as seen by the calling function
640 corresponding to the register number IN as seen by the called function.
641 Return IN if register number IN is not an inbound register. */
643 #define OUTGOING_REGNO(IN) \
644 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
646 /* Define this macro if the target machine has register windows. This
647 C expression returns true if the register is call-saved but is in the
650 #define LOCAL_REGNO(REGNO) \
651 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
653 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
654 return the mode to be used for the comparison. Must be defined if
655 EXTRA_CC_MODES is defined. */
657 #define SELECT_CC_MODE(OP,X,Y) CCmode
659 /* Order of allocation of registers */
661 /* If defined, an initializer for a vector of integers, containing the numbers
662 of hard registers in the order in which GNU CC should prefer to use them
663 (from most preferred to least).
665 If this macro is not defined, registers are used lowest numbered first (all
668 One use of this macro is on machines where the highest numbered registers
669 must always be saved and the save-multiple-registers instruction supports
670 only sequences of consecutive registers. On such machines, define
671 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
672 allocatable register first. */
674 /* ??? Should the GR return value registers come before or after the rest
675 of the caller-save GRs? */
677 #define REG_ALLOC_ORDER \
679 /* Caller-saved general registers. */ \
680 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
681 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
682 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
683 R_GR (30), R_GR (31), \
684 /* Output registers. */ \
685 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
686 R_GR (126), R_GR (127), \
687 /* Caller-saved general registers, also used for return values. */ \
688 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
689 /* addl caller-saved general registers. */ \
690 R_GR (2), R_GR (3), \
691 /* Caller-saved FP registers. */ \
692 R_FR (6), R_FR (7), \
693 /* Caller-saved FP registers, used for parameters and return values. */ \
694 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
695 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
696 /* Rotating caller-saved FP registers. */ \
697 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
698 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
699 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
700 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
701 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
702 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
703 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
704 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
705 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
706 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
707 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
708 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
709 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
710 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
711 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
712 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
713 R_FR (126), R_FR (127), \
714 /* Caller-saved predicate registers. */ \
715 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
716 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
717 /* Rotating caller-saved predicate registers. */ \
718 R_PR (16), R_PR (17), \
719 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
720 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
721 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
722 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
723 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
724 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
725 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
726 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
727 /* Caller-saved branch registers. */ \
728 R_BR (6), R_BR (7), \
730 /* Stacked callee-saved general registers. */ \
731 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
732 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
733 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
734 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
735 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
736 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
737 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
738 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
739 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
740 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
741 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
742 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
743 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
745 /* Input registers. */ \
746 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
747 R_GR (118), R_GR (119), \
748 /* Callee-saved general registers. */ \
749 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
750 /* Callee-saved FP registers. */ \
751 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
752 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
753 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
754 R_FR (30), R_FR (31), \
755 /* Callee-saved predicate registers. */ \
756 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
757 /* Callee-saved branch registers. */ \
758 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
760 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
761 R_GR (109), R_GR (110), R_GR (111), \
763 /* Special general registers. */ \
764 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
765 /* Special FP registers. */ \
766 R_FR (0), R_FR (1), \
767 /* Special predicate registers. */ \
769 /* Special branch registers. */ \
771 /* Other fixed registers. */ \
772 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
773 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
777 /* How Values Fit in Registers */
779 /* A C expression for the number of consecutive hard registers, starting at
780 register number REGNO, required to hold a value of mode MODE. */
782 /* ??? We say that BImode PR values require two registers. This allows us to
783 easily store the normal and inverted values. We use CCImode to indicate
784 a single predicate register. */
786 #define HARD_REGNO_NREGS(REGNO, MODE) \
787 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
788 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
789 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
790 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
791 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
793 /* A C expression that is nonzero if it is permissible to store a value of mode
794 MODE in hard register number REGNO (or in several registers starting with
797 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
798 (FR_REGNO_P (REGNO) ? \
799 GET_MODE_CLASS (MODE) != MODE_CC && \
800 (MODE) != TImode && \
801 (MODE) != BImode && \
802 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
803 : PR_REGNO_P (REGNO) ? \
804 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
805 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
806 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
807 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
810 /* A C expression that is nonzero if it is desirable to choose register
811 allocation so as to avoid move instructions between a value of mode MODE1
812 and a value of mode MODE2.
814 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
815 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
817 /* Don't tie integer and FP modes, as that causes us to get integer registers
818 allocated for FP instructions. TFmode only supported in FP registers so
819 we can't tie it with any other modes. */
820 #define MODES_TIEABLE_P(MODE1, MODE2) \
821 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
822 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
823 && (((MODE1) == BImode) == ((MODE2) == BImode)))
825 /* Handling Leaf Functions */
827 /* A C initializer for a vector, indexed by hard register number, which
828 contains 1 for a register that is allowable in a candidate for leaf function
830 /* ??? This might be useful. */
831 /* #define LEAF_REGISTERS */
833 /* A C expression whose value is the register number to which REGNO should be
834 renumbered, when a function is treated as a leaf function. */
835 /* ??? This might be useful. */
836 /* #define LEAF_REG_REMAP(REGNO) */
839 /* Register Classes */
841 /* An enumeral type that must be defined with all the register class names as
842 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
843 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
844 which is not a register class but rather tells how many classes there
846 /* ??? When compiling without optimization, it is possible for the only use of
847 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
848 Regclass handles this case specially and does not assign any costs to the
849 pseudo. The pseudo then ends up using the last class before ALL_REGS.
850 Thus we must not let either PR_REGS or BR_REGS be the last class. The
851 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
868 #define GENERAL_REGS GR_REGS
870 /* The number of distinct register classes. */
871 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
873 /* An initializer containing the names of the register classes as C string
874 constants. These names are used in writing some of the debugging dumps. */
875 #define REG_CLASS_NAMES \
876 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
877 "ADDL_REGS", "GR_REGS", "FR_REGS", \
878 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
880 /* An initializer containing the contents of the register classes, as integers
881 which are bit masks. The Nth integer specifies the contents of class N.
882 The way the integer MASK is interpreted is that register R is in the class
883 if `MASK & (1 << R)' is 1. */
884 #define REG_CLASS_CONTENTS \
887 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
888 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
889 0x00000000, 0x00000000, 0x0000 }, \
891 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
892 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
893 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
895 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
896 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
897 0x00000000, 0x00000000, 0x00FF }, \
899 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
900 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
901 0x00000000, 0x00000000, 0x0C00 }, \
903 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
904 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
905 0x00000000, 0x00000000, 0x7000 }, \
907 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
908 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
909 0x00000000, 0x00000000, 0x0000 }, \
911 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
912 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
913 0x00000000, 0x00000000, 0x0300 }, \
915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
916 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
917 0x00000000, 0x00000000, 0x0000 }, \
918 /* GR_AND_BR_REGS. */ \
919 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
920 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
921 0x00000000, 0x00000000, 0x03FF }, \
922 /* GR_AND_FR_REGS. */ \
923 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
924 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
925 0x00000000, 0x00000000, 0x0300 }, \
927 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
928 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
929 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
932 /* A C expression whose value is a register class containing hard register
933 REGNO. In general there is more than one such class; choose a class which
934 is "minimal", meaning that no smaller class also contains the register. */
935 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
936 may call here with private (invalid) register numbers, such as
938 #define REGNO_REG_CLASS(REGNO) \
939 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
940 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
941 : FR_REGNO_P (REGNO) ? FR_REGS \
942 : PR_REGNO_P (REGNO) ? PR_REGS \
943 : BR_REGNO_P (REGNO) ? BR_REGS \
944 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
945 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
948 /* A macro whose definition is the name of the class to which a valid base
949 register must belong. A base register is one used in an address which is
950 the register value plus a displacement. */
951 #define BASE_REG_CLASS GENERAL_REGS
953 /* A macro whose definition is the name of the class to which a valid index
954 register must belong. An index register is one used in an address where its
955 value is either multiplied by a scale factor or added to another register
956 (as well as added to a displacement). This is needed for POST_MODIFY. */
957 #define INDEX_REG_CLASS GENERAL_REGS
959 /* A C expression which defines the machine-dependent operand constraint
960 letters for register classes. If CHAR is such a letter, the value should be
961 the register class corresponding to it. Otherwise, the value should be
962 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
963 will not be passed to this macro; you do not need to handle it. */
965 #define REG_CLASS_FROM_LETTER(CHAR) \
966 ((CHAR) == 'f' ? FR_REGS \
967 : (CHAR) == 'a' ? ADDL_REGS \
968 : (CHAR) == 'b' ? BR_REGS \
969 : (CHAR) == 'c' ? PR_REGS \
970 : (CHAR) == 'd' ? AR_M_REGS \
971 : (CHAR) == 'e' ? AR_I_REGS \
974 /* A C expression which is nonzero if register number NUM is suitable for use
975 as a base register in operand addresses. It may be either a suitable hard
976 register or a pseudo register that has been allocated such a hard reg. */
977 #define REGNO_OK_FOR_BASE_P(REGNO) \
978 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
980 /* A C expression which is nonzero if register number NUM is suitable for use
981 as an index register in operand addresses. It may be either a suitable hard
982 register or a pseudo register that has been allocated such a hard reg.
983 This is needed for POST_MODIFY. */
984 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
986 /* A C expression that places additional restrictions on the register class to
987 use when it is necessary to copy value X into a register in class CLASS.
988 The value is a register class; perhaps CLASS, or perhaps another, smaller
991 /* Don't allow volatile mem reloads into floating point registers. This
992 is defined to force reload to choose the r/m case instead of the f/f case
993 when reloading (set (reg fX) (mem/v)).
995 Do not reload expressions into AR regs. */
997 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
998 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
999 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
1000 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
1001 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
1004 /* You should define this macro to indicate to the reload phase that it may
1005 need to allocate at least one register for a reload in addition to the
1006 register to contain the data. Specifically, if copying X to a register
1007 CLASS in MODE requires an intermediate register, you should define this
1008 to return the largest register class all of whose registers can be used
1009 as intermediate registers or scratch registers. */
1011 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
1012 ia64_secondary_reload_class (CLASS, MODE, X)
1014 /* Certain machines have the property that some registers cannot be copied to
1015 some other registers without using memory. Define this macro on those
1016 machines to be a C expression that is nonzero if objects of mode M in
1017 registers of CLASS1 can only be copied to registers of class CLASS2 by
1018 storing a register of CLASS1 into memory and loading that memory location
1019 into a register of CLASS2. */
1022 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
1023 I'm not quite sure how it could be invoked. The normal problems
1024 with unions should be solved with the addressof fiddling done by
1025 movtf and friends. */
1026 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1027 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
1028 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
1031 /* A C expression for the maximum number of consecutive registers of
1032 class CLASS needed to hold a value of mode MODE.
1033 This is closely related to the macro `HARD_REGNO_NREGS'. */
1035 #define CLASS_MAX_NREGS(CLASS, MODE) \
1036 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
1037 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
1038 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1040 /* In FP regs, we can't change FP values to integer values and vice
1041 versa, but we can change e.g. DImode to SImode. */
1043 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1044 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
1045 ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
1047 /* A C expression that defines the machine-dependent operand constraint
1048 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1051 /* 14 bit signed immediate for arithmetic instructions. */
1052 #define CONST_OK_FOR_I(VALUE) \
1053 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1054 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1055 #define CONST_OK_FOR_J(VALUE) \
1056 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1057 /* 8 bit signed immediate for logical instructions. */
1058 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1059 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1060 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1061 /* 6 bit unsigned immediate for shift counts. */
1062 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1063 /* 9 bit signed immediate for load/store post-increments. */
1064 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1065 /* 0 for r0. Used by Linux kernel, do not change. */
1066 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1067 /* 0 or -1 for dep instruction. */
1068 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1070 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1071 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1072 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1073 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1074 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1075 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1076 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1077 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1078 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1081 /* A C expression that defines the machine-dependent operand constraint letters
1082 (`G', `H') that specify particular ranges of `const_double' values. */
1084 /* 0.0 and 1.0 for fr0 and fr1. */
1085 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1086 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1087 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1089 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1090 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1092 /* A C expression that defines the optional machine-dependent constraint
1093 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1094 types of operands, usually memory references, for the target machine. */
1096 /* Non-volatile memory for FP_REG loads/stores. */
1097 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1098 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1099 /* 1..4 for shladd arguments. */
1100 #define CONSTRAINT_OK_FOR_R(VALUE) \
1101 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1102 /* Non-post-inc memory for asms and other unsavory creatures. */
1103 #define CONSTRAINT_OK_FOR_S(VALUE) \
1104 (GET_CODE (VALUE) == MEM \
1105 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1106 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1108 #define EXTRA_CONSTRAINT(VALUE, C) \
1109 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1110 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1111 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1114 /* Basic Stack Layout */
1116 /* Define this macro if pushing a word onto the stack moves the stack pointer
1117 to a smaller address. */
1118 #define STACK_GROWS_DOWNWARD 1
1120 /* Define this macro if the addresses of local variable slots are at negative
1121 offsets from the frame pointer. */
1122 /* #define FRAME_GROWS_DOWNWARD */
1124 /* Offset from the frame pointer to the first local variable slot to
1126 #define STARTING_FRAME_OFFSET 0
1128 /* Offset from the stack pointer register to the first location at which
1129 outgoing arguments are placed. If not specified, the default value of zero
1130 is used. This is the proper value for most machines. */
1131 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1132 #define STACK_POINTER_OFFSET 16
1134 /* Offset from the argument pointer register to the first argument's address.
1135 On some machines it may depend on the data type of the function. */
1136 #define FIRST_PARM_OFFSET(FUNDECL) 0
1138 /* A C expression whose value is RTL representing the value of the return
1139 address for the frame COUNT steps up from the current frame, after the
1142 /* ??? Frames other than zero would likely require interpreting the frame
1143 unwind info, so we don't try to support them. We would also need to define
1144 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1146 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1147 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1149 /* A C expression whose value is RTL representing the location of the incoming
1150 return address at the beginning of any function, before the prologue. This
1151 RTL is either a `REG', indicating that the return value is saved in `REG',
1152 or a `MEM' representing a location in the stack. This enables DWARF2
1153 unwind info for C++ EH. */
1154 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1156 /* ??? This is not defined because of three problems.
1157 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1158 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1159 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1160 unused register number.
1161 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1162 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1163 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1164 to zero, despite what the documentation implies, because it is tested in
1165 a few places with #ifdef instead of #if. */
1166 #undef INCOMING_RETURN_ADDR_RTX
1168 /* A C expression whose value is an integer giving the offset, in bytes, from
1169 the value of the stack pointer register to the top of the stack frame at the
1170 beginning of any function, before the prologue. The top of the frame is
1171 defined to be the value of the stack pointer in the previous frame, just
1172 before the call instruction. */
1173 #define INCOMING_FRAME_SP_OFFSET 0
1176 /* Register That Address the Stack Frame. */
1178 /* The register number of the stack pointer register, which must also be a
1179 fixed register according to `FIXED_REGISTERS'. On most machines, the
1180 hardware determines which register this is. */
1182 #define STACK_POINTER_REGNUM 12
1184 /* The register number of the frame pointer register, which is used to access
1185 automatic variables in the stack frame. On some machines, the hardware
1186 determines which register this is. On other machines, you can choose any
1187 register you wish for this purpose. */
1189 #define FRAME_POINTER_REGNUM 328
1191 /* Base register for access to local variables of the function. */
1192 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1194 /* The register number of the arg pointer register, which is used to access the
1195 function's argument list. */
1196 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1198 #define ARG_POINTER_REGNUM R_GR(0)
1200 /* Due to the way varargs and argument spilling happens, the argument
1201 pointer is not 16-byte aligned like the stack pointer. */
1202 #define INIT_EXPANDERS \
1204 if (cfun && cfun->emit->regno_pointer_align) \
1205 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1208 /* The register number for the return address register. For IA-64, this
1209 is not actually a pointer as the name suggests, but that's a name that
1210 gen_rtx_REG already takes care to keep unique. We modify
1211 return_address_pointer_rtx in ia64_expand_prologue to reference the
1212 final output regnum. */
1213 #define RETURN_ADDRESS_POINTER_REGNUM 329
1215 /* Register numbers used for passing a function's static chain pointer. */
1216 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1217 #define STATIC_CHAIN_REGNUM 15
1219 /* Eliminating the Frame Pointer and the Arg Pointer */
1221 /* A C expression which is nonzero if a function must have and use a frame
1222 pointer. This expression is evaluated in the reload pass. If its value is
1223 nonzero the function will have a frame pointer. */
1224 #define FRAME_POINTER_REQUIRED 0
1226 /* Show we can debug even without a frame pointer. */
1227 #define CAN_DEBUG_WITHOUT_FP
1229 /* If defined, this macro specifies a table of register pairs used to eliminate
1230 unneeded registers that point into the stack frame. */
1232 #define ELIMINABLE_REGS \
1234 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1235 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1236 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1237 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1238 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1241 /* A C expression that returns nonzero if the compiler is allowed to try to
1242 replace register number FROM with register number TO. The frame pointer
1243 is automatically handled. */
1245 #define CAN_ELIMINATE(FROM, TO) \
1246 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1248 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1249 specifies the initial difference between the specified pair of
1250 registers. This macro must be defined if `ELIMINABLE_REGS' is
1252 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1253 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1255 /* Passing Function Arguments on the Stack */
1257 /* Define this macro if an argument declared in a prototype as an integral type
1258 smaller than `int' should actually be passed as an `int'. In addition to
1259 avoiding errors in certain cases of mismatch, it also makes for better code
1260 on certain machines. */
1261 /* ??? Investigate. */
1262 /* #define PROMOTE_PROTOTYPES */
1264 /* If defined, the maximum amount of space required for outgoing arguments will
1265 be computed and placed into the variable
1266 `current_function_outgoing_args_size'. */
1268 #define ACCUMULATE_OUTGOING_ARGS 1
1270 /* A C expression that should indicate the number of bytes of its own arguments
1271 that a function pops on returning, or 0 if the function pops no arguments
1272 and the caller must therefore pop them all after the function returns. */
1274 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1277 /* Function Arguments in Registers */
1279 #define MAX_ARGUMENT_SLOTS 8
1280 #define MAX_INT_RETURN_SLOTS 4
1281 #define GR_ARG_FIRST IN_REG (0)
1282 #define GR_RET_FIRST GR_REG (8)
1283 #define GR_RET_LAST GR_REG (11)
1284 #define FR_ARG_FIRST FR_REG (8)
1285 #define FR_RET_FIRST FR_REG (8)
1286 #define FR_RET_LAST FR_REG (15)
1287 #define AR_ARG_FIRST OUT_REG (0)
1289 /* A C expression that controls whether a function argument is passed in a
1290 register, and which register. */
1292 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1293 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1295 /* Define this macro if the target machine has "register windows", so that the
1296 register in which a function sees an arguments is not necessarily the same
1297 as the one in which the caller passed the argument. */
1299 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1300 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1302 /* A C expression for the number of words, at the beginning of an argument,
1303 must be put in registers. The value must be zero for arguments that are
1304 passed entirely in registers or that are entirely pushed on the stack. */
1306 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1307 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1309 /* A C expression that indicates when an argument must be passed by reference.
1310 If nonzero for an argument, a copy of that argument is made in memory and a
1311 pointer to the argument is passed instead of the argument itself. The
1312 pointer is passed in whatever way is appropriate for passing a pointer to
1315 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1316 ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1318 /* A C type for declaring a variable that is used as the first argument of
1319 `FUNCTION_ARG' and other related values. For some target machines, the type
1320 `int' suffices and can hold the number of bytes of argument so far. */
1322 typedef struct ia64_args
1324 int words; /* # words of arguments so far */
1325 int int_regs; /* # GR registers used so far */
1326 int fp_regs; /* # FR registers used so far */
1327 int prototype; /* whether function prototyped */
1330 /* A C statement (sans semicolon) for initializing the variable CUM for the
1331 state at the beginning of the argument list. */
1333 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1336 (CUM).int_regs = 0; \
1337 (CUM).fp_regs = 0; \
1338 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1341 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1342 arguments for the function being compiled. If this macro is undefined,
1343 `INIT_CUMULATIVE_ARGS' is used instead. */
1345 /* We set prototype to true so that we never try to return a PARALLEL from
1347 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1350 (CUM).int_regs = 0; \
1351 (CUM).fp_regs = 0; \
1352 (CUM).prototype = 1; \
1355 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1356 advance past an argument in the argument list. The values MODE, TYPE and
1357 NAMED describe that argument. Once this is done, the variable CUM is
1358 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1360 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1361 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1363 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1364 argument with the specified mode and type. */
1366 /* Arguments with alignment larger than 8 bytes start at the next even
1367 boundary. See ia64_function_arg. */
1369 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1370 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1371 : (((((MODE) == BLKmode \
1372 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1373 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1374 ? 128 : PARM_BOUNDARY)
1376 /* A C expression that is nonzero if REGNO is the number of a hard register in
1377 which function arguments are sometimes passed. This does *not* include
1378 implicit arguments such as the static chain and the structure-value address.
1379 On many machines, no registers can be used for this purpose since all
1380 function arguments are pushed on the stack. */
1381 #define FUNCTION_ARG_REGNO_P(REGNO) \
1382 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1383 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1385 /* Implement `va_arg'. */
1386 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1387 ia64_va_arg (valist, type)
1389 /* How Scalar Function Values are Returned */
1391 /* A C expression to create an RTX representing the place where a function
1392 returns a value of data type VALTYPE. */
1394 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1395 ia64_function_value (VALTYPE, FUNC)
1397 /* A C expression to create an RTX representing the place where a library
1398 function returns a value of mode MODE. */
1400 #define LIBCALL_VALUE(MODE) \
1401 gen_rtx_REG (MODE, \
1402 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1403 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1404 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1405 ? FR_RET_FIRST : GR_RET_FIRST))
1407 /* A C expression that is nonzero if REGNO is the number of a hard register in
1408 which the values of called function may come back. */
1410 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1411 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1412 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1415 /* How Large Values are Returned */
1417 /* A nonzero value says to return the function value in memory, just as large
1418 structures are always returned. */
1420 #define RETURN_IN_MEMORY(TYPE) \
1421 ia64_return_in_memory (TYPE)
1423 /* If you define this macro to be 0, then the conventions used for structure
1424 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1426 #define DEFAULT_PCC_STRUCT_RETURN 0
1428 /* If the structure value address is passed in a register, then
1429 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1431 #define STRUCT_VALUE_REGNUM GR_REG (8)
1434 /* Caller-Saves Register Allocation */
1436 /* A C expression to determine whether it is worthwhile to consider placing a
1437 pseudo-register in a call-clobbered hard register and saving and restoring
1438 it around each function call. The expression should be 1 when this is worth
1439 doing, and 0 otherwise.
1441 If you don't define this macro, a default is used which is good on most
1442 machines: `4 * CALLS < REFS'. */
1443 /* ??? Investigate. */
1444 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1447 /* Function Entry and Exit */
1449 /* Define this macro as a C expression that is nonzero if the return
1450 instruction or the function epilogue ignores the value of the stack pointer;
1451 in other words, if it is safe to delete an instruction to adjust the stack
1452 pointer before a return from the function. */
1454 #define EXIT_IGNORE_STACK 1
1456 /* Define this macro as a C expression that is nonzero for registers
1457 used by the epilogue or the `return' pattern. */
1459 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1461 /* Nonzero for registers used by the exception handling mechanism. */
1463 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1465 /* Output at beginning of assembler file. */
1467 #define ASM_FILE_START(FILE) \
1468 emit_safe_across_calls (FILE)
1470 /* Output part N of a function descriptor for DECL. For ia64, both
1471 words are emitted with a single relocation, so ignore N > 0. */
1472 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1477 fputs ("\tdata8.ua @iplt(", FILE); \
1479 fputs ("\tdata16.ua @iplt(", FILE); \
1480 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1481 fputs (")\n", FILE); \
1483 fputs ("\tdata8.ua 0\n", FILE); \
1487 /* Generating Code for Profiling. */
1489 /* A C statement or compound statement to output to FILE some assembler code to
1490 call the profiling subroutine `mcount'. */
1492 #undef FUNCTION_PROFILER
1493 #define FUNCTION_PROFILER(FILE, LABELNO) \
1496 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1497 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1498 if (TARGET_AUTO_PIC) \
1499 fputs ("\tmovl out3 = @gprel(", FILE); \
1501 fputs ("\taddl out3 = @ltoff(", FILE); \
1502 assemble_name (FILE, buf); \
1503 if (TARGET_AUTO_PIC) \
1504 fputs (");;\n", FILE); \
1506 fputs ("), r1;;\n", FILE); \
1507 fputs ("\tmov out1 = r1\n", FILE); \
1508 fputs ("\tmov out2 = b0\n", FILE); \
1509 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1512 /* Implementing the Varargs Macros. */
1514 /* Define this macro to store the anonymous register arguments into the stack
1515 so that all the arguments appear to have been passed consecutively on the
1518 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1519 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1521 /* Define this macro if the location where a function argument is passed
1522 depends on whether or not it is a named argument. */
1524 #define STRICT_ARGUMENT_NAMING 1
1527 /* Trampolines for Nested Functions. */
1529 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1530 the function containing a non-local goto target. */
1532 #define STACK_SAVEAREA_MODE(LEVEL) \
1533 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1535 /* Output assembler code for a block containing the constant parts of
1536 a trampoline, leaving space for the variable parts.
1538 The trampoline should set the static chain pointer to value placed
1539 into the trampoline and should branch to the specified routine.
1540 To make the normal indirect-subroutine calling convention work,
1541 the trampoline must look like a function descriptor; the first
1542 word being the target address and the second being the target's
1545 We abuse the concept of a global pointer by arranging for it
1546 to point to the data we need to load. The complete trampoline
1547 has the following form:
1549 +-------------------+ \
1550 TRAMP: | __ia64_trampoline | |
1551 +-------------------+ > fake function descriptor
1553 +-------------------+ /
1554 | target descriptor |
1555 +-------------------+
1557 +-------------------+
1560 /* A C expression for the size in bytes of the trampoline, as an integer. */
1562 #define TRAMPOLINE_SIZE 32
1564 /* Alignment required for trampolines, in bits. */
1566 #define TRAMPOLINE_ALIGNMENT 64
1568 /* A C statement to initialize the variable parts of a trampoline. */
1570 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1571 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1573 /* Implicit Calls to Library Routines */
1575 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1576 C) library functions `memcpy' and `memset' rather than the BSD functions
1577 `bcopy' and `bzero'. */
1579 #define TARGET_MEM_FUNCTIONS
1582 /* Addressing Modes */
1584 /* Define this macro if the machine supports post-increment addressing. */
1586 #define HAVE_POST_INCREMENT 1
1587 #define HAVE_POST_DECREMENT 1
1588 #define HAVE_POST_MODIFY_DISP 1
1589 #define HAVE_POST_MODIFY_REG 1
1591 /* A C expression that is 1 if the RTX X is a constant which is a valid
1594 #define CONSTANT_ADDRESS_P(X) 0
1596 /* The max number of registers that can appear in a valid memory address. */
1598 #define MAX_REGS_PER_ADDRESS 2
1600 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1601 RTX) is a legitimate memory address on the target machine for a memory
1602 operand of mode MODE. */
1604 #define LEGITIMATE_ADDRESS_REG(X) \
1605 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1606 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1607 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1609 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1610 (GET_CODE (X) == PLUS \
1611 && rtx_equal_p (R, XEXP (X, 0)) \
1612 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1613 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1614 && INTVAL (XEXP (X, 1)) >= -256 \
1615 && INTVAL (XEXP (X, 1)) < 256)))
1617 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1619 if (LEGITIMATE_ADDRESS_REG (X)) \
1621 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1622 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1623 && XEXP (X, 0) != arg_pointer_rtx) \
1625 else if (GET_CODE (X) == POST_MODIFY \
1626 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1627 && XEXP (X, 0) != arg_pointer_rtx \
1628 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1632 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1633 use as a base register. */
1635 #ifdef REG_OK_STRICT
1636 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1638 #define REG_OK_FOR_BASE_P(X) \
1639 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1642 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1643 use as an index register. This is needed for POST_MODIFY. */
1645 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1647 /* A C compound statement that attempts to replace X with a valid memory
1648 address for an operand of mode MODE.
1650 This must be present, but there is nothing useful to be done here. */
1652 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1654 /* A C statement or compound statement with a conditional `goto LABEL;'
1655 executed if memory address X (an RTX) can have different meanings depending
1656 on the machine mode of the memory reference it is used for or if the address
1657 is valid for some modes but not others. */
1659 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1660 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1663 /* A C expression that is nonzero if X is a legitimate constant for an
1664 immediate operand on the target machine. */
1666 #define LEGITIMATE_CONSTANT_P(X) \
1667 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1668 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1671 /* Condition Code Status */
1673 /* One some machines not all possible comparisons are defined, but you can
1674 convert an invalid comparison into a valid one. */
1675 /* ??? Investigate. See the alpha definition. */
1676 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1679 /* Describing Relative Costs of Operations */
1681 /* A C expression for the cost of moving data from a register in class FROM to
1682 one in class TO, using MODE. */
1684 #define REGISTER_MOVE_COST ia64_register_move_cost
1686 /* A C expression for the cost of moving data of mode M between a
1687 register and memory. */
1688 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1689 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1690 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1692 /* A C expression for the cost of a branch instruction. A value of 1 is the
1693 default; other values are interpreted relative to that. Used by the
1694 if-conversion code as max instruction count. */
1695 /* ??? This requires investigation. The primary effect might be how
1696 many additional insn groups we run into, vs how good the dynamic
1697 branch predictor is. */
1699 #define BRANCH_COST 6
1701 /* Define this macro as a C expression which is nonzero if accessing less than
1702 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1705 #define SLOW_BYTE_ACCESS 1
1707 /* Define this macro if it is as good or better to call a constant function
1708 address than to call an address kept in a register.
1710 Indirect function calls are more expensive that direct function calls, so
1711 don't cse function addresses. */
1713 #define NO_FUNCTION_CSE
1716 /* Dividing the output into sections. */
1718 /* A C expression whose value is a string containing the assembler operation
1719 that should precede instructions and read-only data. */
1721 #define TEXT_SECTION_ASM_OP "\t.text"
1723 /* A C expression whose value is a string containing the assembler operation to
1724 identify the following data as writable initialized data. */
1726 #define DATA_SECTION_ASM_OP "\t.data"
1728 /* If defined, a C expression whose value is a string containing the assembler
1729 operation to identify the following data as uninitialized global data. */
1731 #define BSS_SECTION_ASM_OP "\t.bss"
1733 #define ENCODE_SECTION_INFO_CHAR '@'
1735 #define IA64_DEFAULT_GVALUE 8
1737 /* Position Independent Code. */
1739 /* The register number of the register used to address a table of static data
1740 addresses in memory. */
1742 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1743 gen_rtx_REG (DImode, 1). */
1745 /* ??? Should we set flag_pic? Probably need to define
1746 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1748 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1750 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1751 clobbered by calls. */
1753 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1756 /* The Overall Framework of an Assembler File. */
1758 /* A C string constant describing how to begin a comment in the target
1759 assembler language. The compiler assumes that the comment will end at the
1762 #define ASM_COMMENT_START "//"
1764 /* A C string constant for text to be output before each `asm' statement or
1765 group of consecutive ones. */
1767 /* ??? This won't work with the Intel assembler, because it does not accept
1768 # as a comment start character. However, //APP does not work in gas, so we
1769 can't use that either. Same problem for ASM_APP_OFF below. */
1771 #define ASM_APP_ON "#APP\n"
1773 /* A C string constant for text to be output after each `asm' statement or
1774 group of consecutive ones. */
1776 #define ASM_APP_OFF "#NO_APP\n"
1779 /* Output of Data. */
1781 /* This is how to output an assembler line defining a `char' constant
1782 to an xdata segment. */
1784 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
1786 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
1787 output_addr_const (FILE, (VALUE)); \
1788 fprintf (FILE, "\n"); \
1791 /* This is how to output an assembler line defining a `short' constant
1792 to an xdata segment. */
1794 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
1796 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
1797 output_addr_const (FILE, (VALUE)); \
1798 fprintf (FILE, "\n"); \
1801 /* This is how to output an assembler line defining an `int' constant
1802 to an xdata segment. We also handle symbol output here. */
1804 /* ??? For ILP32, also need to handle function addresses here. */
1806 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
1808 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
1809 output_addr_const (FILE, (VALUE)); \
1810 fprintf (FILE, "\n"); \
1813 /* This is how to output an assembler line defining a `long' constant
1814 to an xdata segment. We also handle symbol output here. */
1816 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
1818 int need_closing_paren = 0; \
1819 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
1820 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
1821 && GET_CODE (VALUE) == SYMBOL_REF) \
1823 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
1824 need_closing_paren = 1; \
1826 output_addr_const (FILE, VALUE); \
1827 if (need_closing_paren) \
1828 fprintf (FILE, ")"); \
1829 fprintf (FILE, "\n"); \
1834 /* Output of Uninitialized Variables. */
1836 /* This is all handled by svr4.h. */
1839 /* Output and Generation of Labels. */
1841 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1842 assembler definition of a label named NAME. */
1844 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1845 why ia64_asm_output_label exists. */
1847 extern int ia64_asm_output_label;
1848 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1850 ia64_asm_output_label = 1; \
1851 assemble_name (STREAM, NAME); \
1852 fputs (":\n", STREAM); \
1853 ia64_asm_output_label = 0; \
1856 /* Globalizing directive for a label. */
1857 #define GLOBAL_ASM_OP "\t.global "
1859 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1860 necessary for declaring the name of an external symbol named NAME which is
1861 referenced in this compilation but not defined. */
1863 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1864 ia64_asm_output_external (FILE, DECL, NAME)
1866 /* A C statement to store into the string STRING a label whose name is made
1867 from the string PREFIX and the number NUM. */
1869 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1871 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1874 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1876 #define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
1878 /* A C statement to output to the stdio stream STREAM assembler code which
1879 defines (equates) the symbol NAME to have the value VALUE. */
1881 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1883 assemble_name (STREAM, NAME); \
1884 fputs (" = ", STREAM); \
1885 assemble_name (STREAM, VALUE); \
1886 fputc ('\n', STREAM); \
1890 /* Macros Controlling Initialization Routines. */
1892 /* This is handled by svr4.h and sysv4.h. */
1895 /* Output of Assembler Instructions. */
1897 /* A C initializer containing the assembler's names for the machine registers,
1898 each one as a C string constant. */
1900 #define REGISTER_NAMES \
1902 /* General registers. */ \
1903 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1904 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1905 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1907 /* Local registers. */ \
1908 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1909 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1910 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1911 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1912 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1913 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1914 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
1915 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
1916 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
1917 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
1918 /* Input registers. */ \
1919 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
1920 /* Output registers. */ \
1921 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
1922 /* Floating-point registers. */ \
1923 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1924 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1925 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1926 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
1927 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
1928 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
1929 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
1930 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
1931 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
1932 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
1933 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
1934 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
1935 "f120","f121","f122","f123","f124","f125","f126","f127", \
1936 /* Predicate registers. */ \
1937 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
1938 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
1939 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
1940 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
1941 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
1942 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
1943 "p60", "p61", "p62", "p63", \
1944 /* Branch registers. */ \
1945 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
1946 /* Frame pointer. Return address. */ \
1947 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
1950 /* If defined, a C initializer for an array of structures containing a name and
1951 a register number. This macro defines additional names for hard registers,
1952 thus allowing the `asm' option in declarations to refer to registers using
1955 #define ADDITIONAL_REGISTER_NAMES \
1957 { "gp", R_GR (1) }, \
1958 { "sp", R_GR (12) }, \
1959 { "in0", IN_REG (0) }, \
1960 { "in1", IN_REG (1) }, \
1961 { "in2", IN_REG (2) }, \
1962 { "in3", IN_REG (3) }, \
1963 { "in4", IN_REG (4) }, \
1964 { "in5", IN_REG (5) }, \
1965 { "in6", IN_REG (6) }, \
1966 { "in7", IN_REG (7) }, \
1967 { "out0", OUT_REG (0) }, \
1968 { "out1", OUT_REG (1) }, \
1969 { "out2", OUT_REG (2) }, \
1970 { "out3", OUT_REG (3) }, \
1971 { "out4", OUT_REG (4) }, \
1972 { "out5", OUT_REG (5) }, \
1973 { "out6", OUT_REG (6) }, \
1974 { "out7", OUT_REG (7) }, \
1975 { "loc0", LOC_REG (0) }, \
1976 { "loc1", LOC_REG (1) }, \
1977 { "loc2", LOC_REG (2) }, \
1978 { "loc3", LOC_REG (3) }, \
1979 { "loc4", LOC_REG (4) }, \
1980 { "loc5", LOC_REG (5) }, \
1981 { "loc6", LOC_REG (6) }, \
1982 { "loc7", LOC_REG (7) }, \
1983 { "loc8", LOC_REG (8) }, \
1984 { "loc9", LOC_REG (9) }, \
1985 { "loc10", LOC_REG (10) }, \
1986 { "loc11", LOC_REG (11) }, \
1987 { "loc12", LOC_REG (12) }, \
1988 { "loc13", LOC_REG (13) }, \
1989 { "loc14", LOC_REG (14) }, \
1990 { "loc15", LOC_REG (15) }, \
1991 { "loc16", LOC_REG (16) }, \
1992 { "loc17", LOC_REG (17) }, \
1993 { "loc18", LOC_REG (18) }, \
1994 { "loc19", LOC_REG (19) }, \
1995 { "loc20", LOC_REG (20) }, \
1996 { "loc21", LOC_REG (21) }, \
1997 { "loc22", LOC_REG (22) }, \
1998 { "loc23", LOC_REG (23) }, \
1999 { "loc24", LOC_REG (24) }, \
2000 { "loc25", LOC_REG (25) }, \
2001 { "loc26", LOC_REG (26) }, \
2002 { "loc27", LOC_REG (27) }, \
2003 { "loc28", LOC_REG (28) }, \
2004 { "loc29", LOC_REG (29) }, \
2005 { "loc30", LOC_REG (30) }, \
2006 { "loc31", LOC_REG (31) }, \
2007 { "loc32", LOC_REG (32) }, \
2008 { "loc33", LOC_REG (33) }, \
2009 { "loc34", LOC_REG (34) }, \
2010 { "loc35", LOC_REG (35) }, \
2011 { "loc36", LOC_REG (36) }, \
2012 { "loc37", LOC_REG (37) }, \
2013 { "loc38", LOC_REG (38) }, \
2014 { "loc39", LOC_REG (39) }, \
2015 { "loc40", LOC_REG (40) }, \
2016 { "loc41", LOC_REG (41) }, \
2017 { "loc42", LOC_REG (42) }, \
2018 { "loc43", LOC_REG (43) }, \
2019 { "loc44", LOC_REG (44) }, \
2020 { "loc45", LOC_REG (45) }, \
2021 { "loc46", LOC_REG (46) }, \
2022 { "loc47", LOC_REG (47) }, \
2023 { "loc48", LOC_REG (48) }, \
2024 { "loc49", LOC_REG (49) }, \
2025 { "loc50", LOC_REG (50) }, \
2026 { "loc51", LOC_REG (51) }, \
2027 { "loc52", LOC_REG (52) }, \
2028 { "loc53", LOC_REG (53) }, \
2029 { "loc54", LOC_REG (54) }, \
2030 { "loc55", LOC_REG (55) }, \
2031 { "loc56", LOC_REG (56) }, \
2032 { "loc57", LOC_REG (57) }, \
2033 { "loc58", LOC_REG (58) }, \
2034 { "loc59", LOC_REG (59) }, \
2035 { "loc60", LOC_REG (60) }, \
2036 { "loc61", LOC_REG (61) }, \
2037 { "loc62", LOC_REG (62) }, \
2038 { "loc63", LOC_REG (63) }, \
2039 { "loc64", LOC_REG (64) }, \
2040 { "loc65", LOC_REG (65) }, \
2041 { "loc66", LOC_REG (66) }, \
2042 { "loc67", LOC_REG (67) }, \
2043 { "loc68", LOC_REG (68) }, \
2044 { "loc69", LOC_REG (69) }, \
2045 { "loc70", LOC_REG (70) }, \
2046 { "loc71", LOC_REG (71) }, \
2047 { "loc72", LOC_REG (72) }, \
2048 { "loc73", LOC_REG (73) }, \
2049 { "loc74", LOC_REG (74) }, \
2050 { "loc75", LOC_REG (75) }, \
2051 { "loc76", LOC_REG (76) }, \
2052 { "loc77", LOC_REG (77) }, \
2053 { "loc78", LOC_REG (78) }, \
2054 { "loc79", LOC_REG (79) }, \
2057 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2058 for an instruction operand X. X is an RTL expression. */
2060 #define PRINT_OPERAND(STREAM, X, CODE) \
2061 ia64_print_operand (STREAM, X, CODE)
2063 /* A C expression which evaluates to true if CODE is a valid punctuation
2064 character for use in the `PRINT_OPERAND' macro. */
2066 /* ??? Keep this around for now, as we might need it later. */
2068 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2069 ((CODE) == '+' || (CODE) == ',')
2071 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2072 for an instruction operand that is a memory reference whose address is X. X
2073 is an RTL expression. */
2075 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2076 ia64_print_operand_address (STREAM, X)
2078 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2079 `%I' options of `asm_fprintf' (see `final.c'). */
2081 #define REGISTER_PREFIX ""
2082 #define LOCAL_LABEL_PREFIX "."
2083 #define USER_LABEL_PREFIX ""
2084 #define IMMEDIATE_PREFIX ""
2087 /* Output of dispatch tables. */
2089 /* This macro should be provided on machines where the addresses in a dispatch
2090 table are relative to the table's own address. */
2092 /* ??? Depends on the pointer size. */
2094 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2095 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
2097 /* This is how to output an element of a case-vector that is absolute.
2098 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2100 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2102 /* Jump tables only need 8 byte alignment. */
2104 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2107 /* Assembler Commands for Exception Regions. */
2109 /* Select a format to encode pointers in exception handling data. CODE
2110 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2111 true if the symbol may be affected by dynamic relocations. */
2112 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2113 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2114 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2116 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2117 indirect are handled automatically. */
2118 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2120 const char *reltag = NULL; \
2121 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2122 reltag = "@segrel("; \
2123 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2124 reltag = "@gprel("; \
2127 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2128 fputs (reltag, FILE); \
2129 assemble_name (FILE, XSTR (ADDR, 0)); \
2130 fputc (')', FILE); \
2136 /* Assembler Commands for Alignment. */
2138 /* ??? Investigate. */
2140 /* The alignment (log base 2) to put in front of LABEL, which follows
2143 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2145 /* The desired alignment for the location counter at the beginning
2148 /* #define LOOP_ALIGN(LABEL) */
2150 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2151 section because it fails put zeros in the bytes that are skipped. */
2153 #define ASM_NO_SKIP_IN_TEXT 1
2155 /* A C statement to output to the stdio stream STREAM an assembler command to
2156 advance the location counter to a multiple of 2 to the POWER bytes. */
2158 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2159 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2162 /* Macros Affecting all Debug Formats. */
2164 /* This is handled in svr4.h and sysv4.h. */
2167 /* Specific Options for DBX Output. */
2169 /* This is handled by dbxelf.h which is included by svr4.h. */
2172 /* Open ended Hooks for DBX Output. */
2177 /* File names in DBX format. */
2182 /* Macros for SDB and Dwarf Output. */
2184 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2185 output in response to the `-g' option. */
2187 #define DWARF2_DEBUGGING_INFO 1
2189 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2191 /* Use tags for debug info labels, so that they don't break instruction
2192 bundles. This also avoids getting spurious DV warnings from the
2193 assembler. This is similar to (*targetm.asm_out.internal_label), except that we
2194 add brackets around the label. */
2196 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2197 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2199 /* Use section-relative relocations for debugging offsets. Unlike other
2200 targets that fake this by putting the section VMA at 0, IA-64 has
2201 proper relocations for them. */
2202 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2204 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2205 fputs ("@secrel(", FILE); \
2206 assemble_name (FILE, LABEL); \
2207 fputc (')', FILE); \
2210 /* Emit a PC-relative relocation. */
2211 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2213 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2214 fputs ("@pcrel(", FILE); \
2215 assemble_name (FILE, LABEL); \
2216 fputc (')', FILE); \
2219 /* Register Renaming Parameters. */
2221 /* A C expression that is nonzero if hard register number REGNO2 can be
2222 considered for use as a rename register for REGNO1 */
2224 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2225 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2228 /* Miscellaneous Parameters. */
2230 /* Define this if you have defined special-purpose predicates in the file
2231 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2232 expressions matched by the predicate. */
2234 #define PREDICATE_CODES \
2235 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2236 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2237 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2238 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2239 { "function_operand", {SYMBOL_REF}}, \
2240 { "setjmp_operand", {SYMBOL_REF}}, \
2241 { "destination_operand", {SUBREG, REG, MEM}}, \
2242 { "not_postinc_memory_operand", {MEM}}, \
2243 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2244 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2245 { "gr_register_operand", {SUBREG, REG}}, \
2246 { "fr_register_operand", {SUBREG, REG}}, \
2247 { "grfr_register_operand", {SUBREG, REG}}, \
2248 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2249 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2250 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2251 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2252 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2253 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2254 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2255 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2256 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2258 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2260 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2261 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2262 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2263 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2265 { "shladd_operand", {CONST_INT}}, \
2266 { "fetchadd_operand", {CONST_INT}}, \
2267 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2268 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2269 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2270 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2271 { "predicate_operator", {NE, EQ}}, \
2272 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2273 { "ar_lc_reg_operand", {REG}}, \
2274 { "ar_ccv_reg_operand", {REG}}, \
2275 { "ar_pfs_reg_operand", {REG}}, \
2276 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2277 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2278 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
2279 { "basereg_operand", {SUBREG, REG}},
2281 /* An alias for a machine mode name. This is the machine mode that elements of
2282 a jump-table should have. */
2284 #define CASE_VECTOR_MODE Pmode
2286 /* Define as C expression which evaluates to nonzero if the tablejump
2287 instruction expects the table to contain offsets from the address of the
2290 #define CASE_VECTOR_PC_RELATIVE 1
2292 /* Define this macro if operations between registers with integral mode smaller
2293 than a word are always performed on the entire register. */
2295 #define WORD_REGISTER_OPERATIONS
2297 /* Define this macro to be a C expression indicating when insns that read
2298 memory in MODE, an integral mode narrower than a word, set the bits outside
2299 of MODE to be either the sign-extension or the zero-extension of the data
2302 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2304 /* The maximum number of bytes that a single instruction can move quickly from
2305 memory to memory. */
2308 /* A C expression which is nonzero if on this machine it is safe to "convert"
2309 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2310 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2312 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2314 /* A C expression describing the value returned by a comparison operator with
2315 an integral mode and stored by a store-flag instruction (`sCOND') when the
2316 condition is true. */
2318 /* ??? Investigate using -1 instead of 1. */
2320 #define STORE_FLAG_VALUE 1
2322 /* An alias for the machine mode for pointers. */
2324 /* ??? This would change if we had ILP32 support. */
2326 #define Pmode DImode
2328 /* An alias for the machine mode used for memory references to functions being
2329 called, in `call' RTL expressions. */
2331 #define FUNCTION_MODE Pmode
2333 /* Define this macro to handle System V style pragmas: #pragma pack and
2334 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2337 /* If this architecture supports prefetch, define this to be the number of
2338 prefetch commands that can be executed in parallel.
2340 ??? This number is bogus and needs to be replaced before the value is
2341 actually used in optimizations. */
2343 #define SIMULTANEOUS_PREFETCHES 6
2345 /* If this architecture supports prefetch, define this to be the size of
2346 the cache line that is prefetched. */
2348 #define PREFETCH_BLOCK 32
2350 #define HANDLE_SYSV_PRAGMA 1
2352 /* In rare cases, correct code generation requires extra machine dependent
2353 processing between the second jump optimization pass and delayed branch
2354 scheduling. On those machines, define this macro as a C statement to act on
2355 the code starting at INSN. */
2357 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2359 /* A C expression for the maximum number of instructions to execute via
2360 conditional execution instructions instead of a branch. A value of
2361 BRANCH_COST+1 is the default if the machine does not use
2362 cc0, and 1 if it does use cc0. */
2363 /* ??? Investigate. */
2364 #define MAX_CONDITIONAL_EXECUTE 12
2366 extern int ia64_final_schedule;
2368 #define IA64_UNWIND_INFO 1
2369 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2371 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2373 /* This function contains machine specific function data. */
2374 struct machine_function GTY(())
2376 /* The new stack pointer when unwinding from EH. */
2377 rtx ia64_eh_epilogue_sp;
2379 /* The new bsp value when unwinding from EH. */
2380 rtx ia64_eh_epilogue_bsp;
2382 /* The GP value save register. */
2385 /* The number of varargs registers to save. */
2392 IA64_BUILTIN_SYNCHRONIZE,
2394 IA64_BUILTIN_FETCH_AND_ADD_SI,
2395 IA64_BUILTIN_FETCH_AND_SUB_SI,
2396 IA64_BUILTIN_FETCH_AND_OR_SI,
2397 IA64_BUILTIN_FETCH_AND_AND_SI,
2398 IA64_BUILTIN_FETCH_AND_XOR_SI,
2399 IA64_BUILTIN_FETCH_AND_NAND_SI,
2401 IA64_BUILTIN_ADD_AND_FETCH_SI,
2402 IA64_BUILTIN_SUB_AND_FETCH_SI,
2403 IA64_BUILTIN_OR_AND_FETCH_SI,
2404 IA64_BUILTIN_AND_AND_FETCH_SI,
2405 IA64_BUILTIN_XOR_AND_FETCH_SI,
2406 IA64_BUILTIN_NAND_AND_FETCH_SI,
2408 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2409 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2411 IA64_BUILTIN_SYNCHRONIZE_SI,
2413 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2415 IA64_BUILTIN_LOCK_RELEASE_SI,
2417 IA64_BUILTIN_FETCH_AND_ADD_DI,
2418 IA64_BUILTIN_FETCH_AND_SUB_DI,
2419 IA64_BUILTIN_FETCH_AND_OR_DI,
2420 IA64_BUILTIN_FETCH_AND_AND_DI,
2421 IA64_BUILTIN_FETCH_AND_XOR_DI,
2422 IA64_BUILTIN_FETCH_AND_NAND_DI,
2424 IA64_BUILTIN_ADD_AND_FETCH_DI,
2425 IA64_BUILTIN_SUB_AND_FETCH_DI,
2426 IA64_BUILTIN_OR_AND_FETCH_DI,
2427 IA64_BUILTIN_AND_AND_FETCH_DI,
2428 IA64_BUILTIN_XOR_AND_FETCH_DI,
2429 IA64_BUILTIN_NAND_AND_FETCH_DI,
2431 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2432 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2434 IA64_BUILTIN_SYNCHRONIZE_DI,
2436 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2438 IA64_BUILTIN_LOCK_RELEASE_DI,
2441 IA64_BUILTIN_FLUSHRS
2444 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2446 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
2449 #define DONT_USE_BUILTIN_SETJMP
2451 /* Output any profiling code before the prologue. */
2453 #undef PROFILE_BEFORE_PROLOGUE
2454 #define PROFILE_BEFORE_PROLOGUE 1
2458 /* Switch on code for querying unit reservations. */
2459 #define CPU_UNITS_QUERY 1
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