1 /* Definitions of target machine GNU compiler. IA-64 version.
2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 /* ??? Look at ABI group documents for list of preprocessor macros and
24 other features required for ABI compliance. */
26 /* ??? Functions containing a non-local goto target save many registers. Why?
27 See for instance execute/920428-2.c. */
29 /* ??? Add support for short data/bss sections. */
32 /* Run-time target specifications */
35 { "cpp_cpu", CPP_CPU_SPEC }, \
36 { "asm_extra", ASM_EXTRA_SPEC },
38 #define CPP_CPU_SPEC " \
39 -Acpu=ia64 -Amachine=ia64 -D__ia64 -D__ia64__ %{!milp32:-D_LP64 -D__LP64__} \
42 #define CC1_SPEC "%(cc1_cpu) "
44 #define ASM_EXTRA_SPEC ""
47 /* This declaration should be present. */
48 extern int target_flags;
50 /* This series of macros is to allow compiler command arguments to enable or
51 disable the use of optional features of the target machine. */
53 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
55 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
57 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
59 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
61 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
63 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
65 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
67 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
69 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
71 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
73 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
75 #define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
77 #define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
79 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
81 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
83 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
85 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
87 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
89 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
91 #define TARGET_ILP32 (target_flags & MASK_ILP32)
93 #define TARGET_B_STEP (target_flags & MASK_B_STEP)
95 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
97 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
99 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
101 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
103 #define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
105 #define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
107 #define TARGET_INLINE_DIV \
108 (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
110 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
112 /* This macro defines names of command options to set and clear bits in
113 `target_flags'. Its definition is an initializer with a subgrouping for
114 each command option. */
116 #define TARGET_SWITCHES \
118 { "big-endian", MASK_BIG_ENDIAN, \
119 N_("Generate big endian code") }, \
120 { "little-endian", -MASK_BIG_ENDIAN, \
121 N_("Generate little endian code") }, \
122 { "gnu-as", MASK_GNU_AS, \
123 N_("Generate code for GNU as") }, \
124 { "no-gnu-as", -MASK_GNU_AS, \
125 N_("Generate code for Intel as") }, \
126 { "gnu-ld", MASK_GNU_LD, \
127 N_("Generate code for GNU ld") }, \
128 { "no-gnu-ld", -MASK_GNU_LD, \
129 N_("Generate code for Intel ld") }, \
130 { "no-pic", MASK_NO_PIC, \
131 N_("Generate code without GP reg") }, \
132 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \
133 N_("Emit stop bits before and after volatile extended asms") }, \
134 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
135 N_("Don't emit stop bits before and after volatile extended asms") }, \
136 { "b-step", MASK_B_STEP, \
137 N_("Emit code for Itanium (TM) processor B step")}, \
138 { "register-names", MASK_REG_NAMES, \
139 N_("Use in/loc/out register names")}, \
140 { "no-sdata", MASK_NO_SDATA, \
141 N_("Disable use of sdata/scommon/sbss")}, \
142 { "sdata", -MASK_NO_SDATA, \
143 N_("Enable use of sdata/scommon/sbss")}, \
144 { "constant-gp", MASK_CONST_GP, \
145 N_("gp is constant (but save/restore gp on indirect calls)") }, \
146 { "auto-pic", MASK_AUTO_PIC, \
147 N_("Generate self-relocatable code") }, \
148 { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
149 N_("Generate inline division, optimize for latency") }, \
150 { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
151 N_("Generate inline division, optimize for throughput") }, \
152 { "dwarf2-asm", MASK_DWARF2_ASM, \
153 N_("Enable Dwarf 2 line debug info via GNU as")}, \
154 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \
155 N_("Disable Dwarf 2 line debug info via GNU as")}, \
157 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
161 /* Default target_flags if no switches are specified */
163 #ifndef TARGET_DEFAULT
164 #define TARGET_DEFAULT MASK_DWARF2_ASM
167 #ifndef TARGET_CPU_DEFAULT
168 #define TARGET_CPU_DEFAULT 0
171 #ifndef SUBTARGET_SWITCHES
172 #define SUBTARGET_SWITCHES
175 /* This macro is similar to `TARGET_SWITCHES' but defines names of command
176 options that have values. Its definition is an initializer with a
177 subgrouping for each command option. */
179 extern const char *ia64_fixed_range_string;
180 #define TARGET_OPTIONS \
182 { "fixed-range=", &ia64_fixed_range_string, \
183 N_("Specify range of registers to make fixed")}, \
186 /* Sometimes certain combinations of command options do not make sense on a
187 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
188 take account of this. This macro, if defined, is executed once just after
189 all the command options have been parsed. */
191 #define OVERRIDE_OPTIONS ia64_override_options ()
193 /* Some machines may desire to change what optimizations are performed for
194 various optimization levels. This macro, if defined, is executed once just
195 after the optimization level is determined and before the remainder of the
196 command options have been parsed. Values set in this macro are used as the
197 default values for the other command line options. */
199 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */
201 /* Driver configuration */
203 /* A C string constant that tells the GNU CC driver program options to pass to
204 CPP. It can also specify how to translate options you give to GNU CC into
205 options for GNU CC to pass to the CPP. */
207 /* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */
208 /* ??? An alternative is to modify glimits.h to check for __LP64__ instead
209 of checked for CPU specific defines. We could also get rid of all LONG_MAX
210 defines in other tm.h files. */
212 "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
214 -D__LONG_MAX__=9223372036854775807L"
216 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
217 /* #define NO_BUILTIN_SIZE_TYPE */
219 /* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
220 /* #define NO_BUILTIN_PTRDIFF_TYPE */
222 /* A C string constant that tells the GNU CC driver program options to pass to
223 `cc1'. It can also specify how to translate options you give to GNU CC into
224 options for GNU CC to pass to the `cc1'. */
227 #define CC1_SPEC "%{G*}"
229 /* A C string constant that tells the GNU CC driver program options to pass to
230 `cc1plus'. It can also specify how to translate options you give to GNU CC
231 into options for GNU CC to pass to the `cc1plus'. */
233 /* #define CC1PLUS_SPEC "" */
237 /* Define this macro to have the value 1 if the most significant bit in a byte
238 has the lowest number; otherwise define it to have the value zero. */
240 #define BITS_BIG_ENDIAN 0
242 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
244 /* Define this macro to have the value 1 if, in a multiword object, the most
245 significant word has the lowest number. */
247 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
249 #if defined(__BIG_ENDIAN__)
250 #define LIBGCC2_WORDS_BIG_ENDIAN 1
252 #define LIBGCC2_WORDS_BIG_ENDIAN 0
255 #define UNITS_PER_WORD 8
257 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
259 /* A C expression whose value is zero if pointers that need to be extended
260 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
261 they are zero-extended and negative one if there is an ptr_extend operation.
263 You need not define this macro if the `POINTER_SIZE' is equal to the width
265 /* Need this for 32 bit pointers, see hpux.h for setting it. */
266 /* #define POINTERS_EXTEND_UNSIGNED */
268 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and
269 which has the specified mode and signedness is to be stored in a register.
270 This macro is only called when TYPE is a scalar type. */
271 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
274 if (GET_MODE_CLASS (MODE) == MODE_INT \
275 && GET_MODE_SIZE (MODE) < 4) \
280 /* ??? ABI doesn't allow us to define this. */
281 /* #define PROMOTE_FUNCTION_ARGS */
283 /* ??? ABI doesn't allow us to define this. */
284 /* #define PROMOTE_FUNCTION_RETURN */
286 #define PARM_BOUNDARY 64
288 /* Define this macro if you wish to preserve a certain alignment for the stack
289 pointer. The definition is a C expression for the desired alignment
290 (measured in bits). */
292 #define STACK_BOUNDARY 128
294 /* Align frames on double word boundaries */
295 #ifndef IA64_STACK_ALIGN
296 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
299 #define FUNCTION_BOUNDARY 128
301 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
302 128 bit integers all require 128 bit alignment. */
303 #define BIGGEST_ALIGNMENT 128
305 /* If defined, a C expression to compute the alignment for a static variable.
306 TYPE is the data type, and ALIGN is the alignment that the object
307 would ordinarily have. The value of this macro is used instead of that
308 alignment to align the object. */
310 #define DATA_ALIGNMENT(TYPE, ALIGN) \
311 (TREE_CODE (TYPE) == ARRAY_TYPE \
312 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
313 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
315 /* If defined, a C expression to compute the alignment given to a constant that
316 is being placed in memory. CONSTANT is the constant and ALIGN is the
317 alignment that the object would ordinarily have. The value of this macro is
318 used instead of that alignment to align the object. */
320 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
321 (TREE_CODE (EXP) == STRING_CST \
322 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
324 #define STRICT_ALIGNMENT 1
326 /* Define this if you wish to imitate the way many other C compilers handle
327 alignment of bitfields and the structures that contain them.
328 The behavior is that the type written for a bitfield (`int', `short', or
329 other integer type) imposes an alignment for the entire structure, as if the
330 structure really did contain an ordinary field of that type. In addition,
331 the bitfield is placed within the structure so that it would fit within such
332 a field, not crossing a boundary for it. */
333 #define PCC_BITFIELD_TYPE_MATTERS 1
335 /* An integer expression for the size in bits of the largest integer machine
336 mode that should actually be used. */
338 /* Allow pairs of registers to be used, which is the intent of the default. */
339 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
341 /* A code distinguishing the floating point format of the target machine. */
342 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
344 /* By default, the C++ compiler will use function addresses in the
345 vtable entries. Setting this non-zero tells the compiler to use
346 function descriptors instead. The value of this macro says how
347 many words wide the descriptor is (normally 2). It is assumed
348 that the address of a function descriptor may be treated as a
349 pointer to a function. */
350 #define TARGET_VTABLE_USES_DESCRIPTORS 2
352 /* Layout of Source Language Data Types */
354 #define INT_TYPE_SIZE 32
356 #define SHORT_TYPE_SIZE 16
358 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
360 #define MAX_LONG_TYPE_SIZE 64
362 #define LONG_LONG_TYPE_SIZE 64
364 #define FLOAT_TYPE_SIZE 32
366 #define DOUBLE_TYPE_SIZE 64
368 #define LONG_DOUBLE_TYPE_SIZE 128
370 /* Tell real.c that this is the 80-bit Intel extended float format
371 packaged in a 128-bit entity. */
373 #define INTEL_EXTENDED_IEEE_FORMAT 1
375 #define DEFAULT_SIGNED_CHAR 1
377 /* A C expression for a string describing the name of the data type to use for
378 size values. The typedef name `size_t' is defined using the contents of the
380 /* ??? Needs to be defined for P64 code. */
381 /* #define SIZE_TYPE */
383 /* A C expression for a string describing the name of the data type to use for
384 the result of subtracting two pointers. The typedef name `ptrdiff_t' is
385 defined using the contents of the string. See `SIZE_TYPE' above for more
387 /* ??? Needs to be defined for P64 code. */
388 /* #define PTRDIFF_TYPE */
390 /* A C expression for a string describing the name of the data type to use for
391 wide characters. The typedef name `wchar_t' is defined using the contents
392 of the string. See `SIZE_TYPE' above for more information. */
393 /* #define WCHAR_TYPE */
395 /* A C expression for the size in bits of the data type for wide characters.
396 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
397 /* #define WCHAR_TYPE_SIZE */
400 /* Register Basics */
402 /* Number of hardware registers known to the compiler.
403 We have 128 general registers, 128 floating point registers,
404 64 predicate registers, 8 branch registers, one frame pointer,
405 and several "application" registers. */
407 #define FIRST_PSEUDO_REGISTER 335
409 /* Ranges for the various kinds of registers. */
410 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
411 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127)
412 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255)
413 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
414 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
415 #define GENERAL_REGNO_P(REGNO) \
416 (GR_REGNO_P (REGNO) \
417 || (REGNO) == FRAME_POINTER_REGNUM \
418 || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
420 #define GR_REG(REGNO) ((REGNO) + 0)
421 #define FR_REG(REGNO) ((REGNO) + 128)
422 #define PR_REG(REGNO) ((REGNO) + 256)
423 #define BR_REG(REGNO) ((REGNO) + 320)
424 #define OUT_REG(REGNO) ((REGNO) + 120)
425 #define IN_REG(REGNO) ((REGNO) + 112)
426 #define LOC_REG(REGNO) ((REGNO) + 32)
428 #define AR_CCV_REGNUM 330
429 #define AR_UNAT_REGNUM 331
430 #define AR_PFS_REGNUM 332
431 #define AR_LC_REGNUM 333
432 #define AR_EC_REGNUM 334
434 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
435 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
436 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7))
438 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \
439 || (REGNO) == AR_UNAT_REGNUM)
440 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \
441 && (REGNO) < FIRST_PSEUDO_REGISTER)
442 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \
443 && (REGNO) < FIRST_PSEUDO_REGISTER)
446 /* ??? Don't really need two sets of macros. I like this one better because
447 it is less typing. */
448 #define R_GR(REGNO) GR_REG (REGNO)
449 #define R_FR(REGNO) FR_REG (REGNO)
450 #define R_PR(REGNO) PR_REG (REGNO)
451 #define R_BR(REGNO) BR_REG (REGNO)
453 /* An initializer that says which registers are used for fixed purposes all
454 throughout the compiled code and are therefore not available for general
458 r1: global pointer (gp)
459 r12: stack pointer (sp)
460 r13: thread pointer (tp)
464 fp: eliminable frame pointer */
466 /* The last 16 stacked regs are reserved for the 8 input and 8 output
469 #define FIXED_REGISTERS \
470 { /* General registers. */ \
471 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
479 /* Floating-point registers. */ \
480 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
483 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
486 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
487 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
488 /* Predicate registers. */ \
489 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
493 /* Branch registers. */ \
494 0, 0, 0, 0, 0, 0, 0, 0, \
495 /*FP RA CCV UNAT PFS LC EC */ \
496 1, 1, 1, 1, 1, 0, 1 \
499 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
500 (in general) by function calls as well as for fixed registers. This
501 macro therefore identifies the registers that are not available for
502 general allocation of values that must live across function calls. */
504 #define CALL_USED_REGISTERS \
505 { /* General registers. */ \
506 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
507 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
513 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
514 /* Floating-point registers. */ \
515 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
520 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
523 /* Predicate registers. */ \
524 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
527 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
528 /* Branch registers. */ \
529 1, 0, 0, 0, 0, 0, 1, 1, \
530 /*FP RA CCV UNAT PFS LC EC */ \
531 1, 1, 1, 1, 1, 0, 1 \
534 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
535 problem which makes CALL_USED_REGISTERS *always* include
536 all the FIXED_REGISTERS. Until this problem has been
537 resolved this macro can be used to overcome this situation.
538 In particular, block_propagate() requires this list
539 be acurate, or we can remove registers which should be live.
540 This macro is used in regs_invalidated_by_call. */
542 #define CALL_REALLY_USED_REGISTERS \
543 { /* General registers. */ \
544 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \
545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
551 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
552 /* Floating-point registers. */ \
553 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
554 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
561 /* Predicate registers. */ \
562 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
566 /* Branch registers. */ \
567 1, 0, 0, 0, 0, 0, 1, 1, \
568 /*FP RA CCV UNAT PFS LC EC */ \
569 0, 0, 1, 0, 1, 0, 0 \
573 /* Define this macro if the target machine has register windows. This C
574 expression returns the register number as seen by the called function
575 corresponding to the register number OUT as seen by the calling function.
576 Return OUT if register number OUT is not an outbound register. */
578 #define INCOMING_REGNO(OUT) \
579 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT))
581 /* Define this macro if the target machine has register windows. This C
582 expression returns the register number as seen by the calling function
583 corresponding to the register number IN as seen by the called function.
584 Return IN if register number IN is not an inbound register. */
586 #define OUTGOING_REGNO(IN) \
587 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN))
589 /* Define this macro if the target machine has register windows. This
590 C expression returns true if the register is call-saved but is in the
593 #define LOCAL_REGNO(REGNO) \
594 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
596 /* Add any extra modes needed to represent the condition code.
598 CCImode is used to mark a single predicate register instead
599 of a register pair. This is currently only used in reg_raw_mode
600 so that flow doesn't do something stupid. */
602 #define EXTRA_CC_MODES CC(CCImode, "CCI")
604 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
605 return the mode to be used for the comparison. Must be defined if
606 EXTRA_CC_MODES is defined. */
608 #define SELECT_CC_MODE(OP,X,Y) CCmode
610 /* Order of allocation of registers */
612 /* If defined, an initializer for a vector of integers, containing the numbers
613 of hard registers in the order in which GNU CC should prefer to use them
614 (from most preferred to least).
616 If this macro is not defined, registers are used lowest numbered first (all
619 One use of this macro is on machines where the highest numbered registers
620 must always be saved and the save-multiple-registers instruction supports
621 only sequences of consecutive registers. On such machines, define
622 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered
623 allocatable register first. */
625 /* ??? Should the GR return value registers come before or after the rest
626 of the caller-save GRs? */
628 #define REG_ALLOC_ORDER \
630 /* Caller-saved general registers. */ \
631 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \
632 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \
633 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \
634 R_GR (30), R_GR (31), \
635 /* Output registers. */ \
636 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \
637 R_GR (126), R_GR (127), \
638 /* Caller-saved general registers, also used for return values. */ \
639 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \
640 /* addl caller-saved general registers. */ \
641 R_GR (2), R_GR (3), \
642 /* Caller-saved FP registers. */ \
643 R_FR (6), R_FR (7), \
644 /* Caller-saved FP registers, used for parameters and return values. */ \
645 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \
646 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \
647 /* Rotating caller-saved FP registers. */ \
648 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \
649 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \
650 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \
651 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \
652 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \
653 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \
654 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \
655 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \
656 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \
657 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \
658 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \
659 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \
660 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \
661 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \
662 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \
663 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \
664 R_FR (126), R_FR (127), \
665 /* Caller-saved predicate registers. */ \
666 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \
667 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \
668 /* Rotating caller-saved predicate registers. */ \
669 R_PR (16), R_PR (17), \
670 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \
671 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \
672 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \
673 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \
674 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \
675 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \
676 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \
677 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \
678 /* Caller-saved branch registers. */ \
679 R_BR (6), R_BR (7), \
681 /* Stacked callee-saved general registers. */ \
682 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \
683 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \
684 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \
685 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \
686 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \
687 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \
688 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \
689 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \
690 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \
691 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \
692 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \
693 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \
694 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \
696 /* Input registers. */ \
697 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \
698 R_GR (118), R_GR (119), \
699 /* Callee-saved general registers. */ \
700 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \
701 /* Callee-saved FP registers. */ \
702 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \
703 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \
704 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \
705 R_FR (30), R_FR (31), \
706 /* Callee-saved predicate registers. */ \
707 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \
708 /* Callee-saved branch registers. */ \
709 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \
711 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \
712 R_GR (109), R_GR (110), R_GR (111), \
714 /* Special general registers. */ \
715 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \
716 /* Special FP registers. */ \
717 R_FR (0), R_FR (1), \
718 /* Special predicate registers. */ \
720 /* Special branch registers. */ \
722 /* Other fixed registers. */ \
723 FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
724 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
728 /* How Values Fit in Registers */
730 /* A C expression for the number of consecutive hard registers, starting at
731 register number REGNO, required to hold a value of mode MODE. */
733 /* ??? We say that BImode PR values require two registers. This allows us to
734 easily store the normal and inverted values. We use CCImode to indicate
735 a single predicate register. */
737 #define HARD_REGNO_NREGS(REGNO, MODE) \
738 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
739 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
740 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
741 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
742 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
744 /* A C expression that is nonzero if it is permissible to store a value of mode
745 MODE in hard register number REGNO (or in several registers starting with
748 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
749 (FR_REGNO_P (REGNO) ? \
750 GET_MODE_CLASS (MODE) != MODE_CC && \
751 (MODE) != TImode && \
752 (MODE) != BImode && \
753 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
754 : PR_REGNO_P (REGNO) ? \
755 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
756 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
757 : AR_REGNO_P (REGNO) ? (MODE) == DImode \
758 : BR_REGNO_P (REGNO) ? (MODE) == DImode \
761 /* A C expression that is nonzero if it is desirable to choose register
762 allocation so as to avoid move instructions between a value of mode MODE1
763 and a value of mode MODE2.
765 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are
766 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
768 /* Don't tie integer and FP modes, as that causes us to get integer registers
769 allocated for FP instructions. TFmode only supported in FP registers so
770 we can't tie it with any other modes. */
771 #define MODES_TIEABLE_P(MODE1, MODE2) \
772 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
773 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
774 && (((MODE1) == BImode) == ((MODE2) == BImode)))
776 /* Handling Leaf Functions */
778 /* A C initializer for a vector, indexed by hard register number, which
779 contains 1 for a register that is allowable in a candidate for leaf function
781 /* ??? This might be useful. */
782 /* #define LEAF_REGISTERS */
784 /* A C expression whose value is the register number to which REGNO should be
785 renumbered, when a function is treated as a leaf function. */
786 /* ??? This might be useful. */
787 /* #define LEAF_REG_REMAP(REGNO) */
790 /* Register Classes */
792 /* An enumeral type that must be defined with all the register class names as
793 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last
794 register class, followed by one more enumeral value, `LIM_REG_CLASSES',
795 which is not a register class but rather tells how many classes there
797 /* ??? When compiling without optimization, it is possible for the only use of
798 a pseudo to be a parameter load from the stack with a REG_EQUIV note.
799 Regclass handles this case specially and does not assign any costs to the
800 pseudo. The pseudo then ends up using the last class before ALL_REGS.
801 Thus we must not let either PR_REGS or BR_REGS be the last class. The
802 testcase for this is gcc.c-torture/execute/va-arg-7.c. */
819 #define GENERAL_REGS GR_REGS
821 /* The number of distinct register classes. */
822 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
824 /* An initializer containing the names of the register classes as C string
825 constants. These names are used in writing some of the debugging dumps. */
826 #define REG_CLASS_NAMES \
827 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
828 "ADDL_REGS", "GR_REGS", "FR_REGS", \
829 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
831 /* An initializer containing the contents of the register classes, as integers
832 which are bit masks. The Nth integer specifies the contents of class N.
833 The way the integer MASK is interpreted is that register R is in the class
834 if `MASK & (1 << R)' is 1. */
835 #define REG_CLASS_CONTENTS \
838 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
839 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
840 0x00000000, 0x00000000, 0x0000 }, \
842 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
843 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
844 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \
846 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
847 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
848 0x00000000, 0x00000000, 0x00FF }, \
850 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
851 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
852 0x00000000, 0x00000000, 0x0C00 }, \
854 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
855 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
856 0x00000000, 0x00000000, 0x7000 }, \
858 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
859 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
860 0x00000000, 0x00000000, 0x0000 }, \
862 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
863 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
864 0x00000000, 0x00000000, 0x0300 }, \
866 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
867 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
868 0x00000000, 0x00000000, 0x0000 }, \
869 /* GR_AND_BR_REGS. */ \
870 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
871 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
872 0x00000000, 0x00000000, 0x03FF }, \
873 /* GR_AND_FR_REGS. */ \
874 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
875 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
876 0x00000000, 0x00000000, 0x0300 }, \
878 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
879 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
880 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
883 /* A C expression whose value is a register class containing hard register
884 REGNO. In general there is more than one such class; choose a class which
885 is "minimal", meaning that no smaller class also contains the register. */
886 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which
887 may call here with private (invalid) register numbers, such as
889 #define REGNO_REG_CLASS(REGNO) \
890 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \
891 : GENERAL_REGNO_P (REGNO) ? GR_REGS \
892 : FR_REGNO_P (REGNO) ? FR_REGS \
893 : PR_REGNO_P (REGNO) ? PR_REGS \
894 : BR_REGNO_P (REGNO) ? BR_REGS \
895 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \
896 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \
899 /* A macro whose definition is the name of the class to which a valid base
900 register must belong. A base register is one used in an address which is
901 the register value plus a displacement. */
902 #define BASE_REG_CLASS GENERAL_REGS
904 /* A macro whose definition is the name of the class to which a valid index
905 register must belong. An index register is one used in an address where its
906 value is either multiplied by a scale factor or added to another register
907 (as well as added to a displacement). This is needed for POST_MODIFY. */
908 #define INDEX_REG_CLASS GENERAL_REGS
910 /* A C expression which defines the machine-dependent operand constraint
911 letters for register classes. If CHAR is such a letter, the value should be
912 the register class corresponding to it. Otherwise, the value should be
913 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS',
914 will not be passed to this macro; you do not need to handle it. */
916 #define REG_CLASS_FROM_LETTER(CHAR) \
917 ((CHAR) == 'f' ? FR_REGS \
918 : (CHAR) == 'a' ? ADDL_REGS \
919 : (CHAR) == 'b' ? BR_REGS \
920 : (CHAR) == 'c' ? PR_REGS \
921 : (CHAR) == 'd' ? AR_M_REGS \
922 : (CHAR) == 'e' ? AR_I_REGS \
925 /* A C expression which is nonzero if register number NUM is suitable for use
926 as a base register in operand addresses. It may be either a suitable hard
927 register or a pseudo register that has been allocated such a hard reg. */
928 #define REGNO_OK_FOR_BASE_P(REGNO) \
929 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO]))
931 /* A C expression which is nonzero if register number NUM is suitable for use
932 as an index register in operand addresses. It may be either a suitable hard
933 register or a pseudo register that has been allocated such a hard reg.
934 This is needed for POST_MODIFY. */
935 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM)
937 /* A C expression that places additional restrictions on the register class to
938 use when it is necessary to copy value X into a register in class CLASS.
939 The value is a register class; perhaps CLASS, or perhaps another, smaller
942 /* Don't allow volatile mem reloads into floating point registers. This
943 is defined to force reload to choose the r/m case instead of the f/f case
944 when reloading (set (reg fX) (mem/v)).
946 Do not reload expressions into AR regs. */
948 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
949 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
950 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
951 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
952 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
955 /* You should define this macro to indicate to the reload phase that it may
956 need to allocate at least one register for a reload in addition to the
957 register to contain the data. Specifically, if copying X to a register
958 CLASS in MODE requires an intermediate register, you should define this
959 to return the largest register class all of whose registers can be used
960 as intermediate registers or scratch registers. */
962 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
963 ia64_secondary_reload_class (CLASS, MODE, X)
965 /* Certain machines have the property that some registers cannot be copied to
966 some other registers without using memory. Define this macro on those
967 machines to be a C expression that is non-zero if objects of mode M in
968 registers of CLASS1 can only be copied to registers of class CLASS2 by
969 storing a register of CLASS1 into memory and loading that memory location
970 into a register of CLASS2. */
973 /* ??? May need this, but since we've disallowed TFmode in GR_REGS,
974 I'm not quite sure how it could be invoked. The normal problems
975 with unions should be solved with the addressof fiddling done by
976 movtf and friends. */
977 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
978 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
979 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
982 /* A C expression for the maximum number of consecutive registers of
983 class CLASS needed to hold a value of mode MODE.
984 This is closely related to the macro `HARD_REGNO_NREGS'. */
986 #define CLASS_MAX_NREGS(CLASS, MODE) \
987 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
988 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
989 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
991 /* If defined, gives a class of registers that cannot be used as the
992 operand of a SUBREG that changes the mode of the object illegally. */
994 #define CLASS_CANNOT_CHANGE_MODE FR_REGS
996 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
997 In FP regs, we can't change FP values to integer values and vice
998 versa, but we can change e.g. DImode to SImode. */
1000 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1001 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO))
1003 /* A C expression that defines the machine-dependent operand constraint
1004 letters (`I', `J', `K', .. 'P') that specify particular ranges of
1007 /* 14 bit signed immediate for arithmetic instructions. */
1008 #define CONST_OK_FOR_I(VALUE) \
1009 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000)
1010 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */
1011 #define CONST_OK_FOR_J(VALUE) \
1012 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000)
1013 /* 8 bit signed immediate for logical instructions. */
1014 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100)
1015 /* 8 bit adjusted signed immediate for compare pseudo-ops. */
1016 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100)
1017 /* 6 bit unsigned immediate for shift counts. */
1018 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40)
1019 /* 9 bit signed immediate for load/store post-increments. */
1020 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200)
1021 /* 0 for r0. Used by Linux kernel, do not change. */
1022 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0)
1023 /* 0 or -1 for dep instruction. */
1024 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1)
1026 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1027 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
1028 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \
1029 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
1030 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
1031 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1032 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1033 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \
1034 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \
1037 /* A C expression that defines the machine-dependent operand constraint letters
1038 (`G', `H') that specify particular ranges of `const_double' values. */
1040 /* 0.0 and 1.0 for fr0 and fr1. */
1041 #define CONST_DOUBLE_OK_FOR_G(VALUE) \
1042 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \
1043 || (VALUE) == CONST1_RTX (GET_MODE (VALUE)))
1045 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1046 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0)
1048 /* A C expression that defines the optional machine-dependent constraint
1049 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific
1050 types of operands, usually memory references, for the target machine. */
1052 /* Non-volatile memory for FP_REG loads/stores. */
1053 #define CONSTRAINT_OK_FOR_Q(VALUE) \
1054 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE))
1055 /* 1..4 for shladd arguments. */
1056 #define CONSTRAINT_OK_FOR_R(VALUE) \
1057 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4)
1058 /* Non-post-inc memory for asms and other unsavory creatures. */
1059 #define CONSTRAINT_OK_FOR_S(VALUE) \
1060 (GET_CODE (VALUE) == MEM \
1061 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
1062 && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
1064 #define EXTRA_CONSTRAINT(VALUE, C) \
1065 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
1066 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
1067 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
1070 /* Basic Stack Layout */
1072 /* Define this macro if pushing a word onto the stack moves the stack pointer
1073 to a smaller address. */
1074 #define STACK_GROWS_DOWNWARD 1
1076 /* Define this macro if the addresses of local variable slots are at negative
1077 offsets from the frame pointer. */
1078 /* #define FRAME_GROWS_DOWNWARD */
1080 /* Offset from the frame pointer to the first local variable slot to
1082 #define STARTING_FRAME_OFFSET 0
1084 /* Offset from the stack pointer register to the first location at which
1085 outgoing arguments are placed. If not specified, the default value of zero
1086 is used. This is the proper value for most machines. */
1087 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */
1088 #define STACK_POINTER_OFFSET 16
1090 /* Offset from the argument pointer register to the first argument's address.
1091 On some machines it may depend on the data type of the function. */
1092 #define FIRST_PARM_OFFSET(FUNDECL) 0
1094 /* A C expression whose value is RTL representing the value of the return
1095 address for the frame COUNT steps up from the current frame, after the
1098 /* ??? Frames other than zero would likely require interpreting the frame
1099 unwind info, so we don't try to support them. We would also need to define
1100 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
1102 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1103 ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
1105 /* A C expression whose value is RTL representing the location of the incoming
1106 return address at the beginning of any function, before the prologue. This
1107 RTL is either a `REG', indicating that the return value is saved in `REG',
1108 or a `MEM' representing a location in the stack. This enables DWARF2
1109 unwind info for C++ EH. */
1110 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0))
1112 /* ??? This is not defined because of three problems.
1113 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte.
1114 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be
1115 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise
1116 unused register number.
1117 2) dwarf2out_frame_debug core dumps while processing prologue insns. We
1118 need to refine which insns have RTX_FRAME_RELATED_P set and which don't.
1119 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO
1120 to zero, despite what the documentation implies, because it is tested in
1121 a few places with #ifdef instead of #if. */
1122 #undef INCOMING_RETURN_ADDR_RTX
1124 /* A C expression whose value is an integer giving the offset, in bytes, from
1125 the value of the stack pointer register to the top of the stack frame at the
1126 beginning of any function, before the prologue. The top of the frame is
1127 defined to be the value of the stack pointer in the previous frame, just
1128 before the call instruction. */
1129 #define INCOMING_FRAME_SP_OFFSET 0
1132 /* Register That Address the Stack Frame. */
1134 /* The register number of the stack pointer register, which must also be a
1135 fixed register according to `FIXED_REGISTERS'. On most machines, the
1136 hardware determines which register this is. */
1138 #define STACK_POINTER_REGNUM 12
1140 /* The register number of the frame pointer register, which is used to access
1141 automatic variables in the stack frame. On some machines, the hardware
1142 determines which register this is. On other machines, you can choose any
1143 register you wish for this purpose. */
1145 #define FRAME_POINTER_REGNUM 328
1147 /* Base register for access to local variables of the function. */
1148 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79)
1150 /* The register number of the arg pointer register, which is used to access the
1151 function's argument list. */
1152 /* r0 won't otherwise be used, so put the always eliminated argument pointer
1154 #define ARG_POINTER_REGNUM R_GR(0)
1156 /* Due to the way varargs and argument spilling happens, the argument
1157 pointer is not 16-byte aligned like the stack pointer. */
1158 #define INIT_EXPANDERS \
1160 if (cfun && cfun->emit->regno_pointer_align) \
1161 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
1164 /* The register number for the return address register. For IA-64, this
1165 is not actually a pointer as the name suggests, but that's a name that
1166 gen_rtx_REG already takes care to keep unique. We modify
1167 return_address_pointer_rtx in ia64_expand_prologue to reference the
1168 final output regnum. */
1169 #define RETURN_ADDRESS_POINTER_REGNUM 329
1171 /* Register numbers used for passing a function's static chain pointer. */
1172 /* ??? The ABI sez the static chain should be passed as a normal parameter. */
1173 #define STATIC_CHAIN_REGNUM 15
1175 /* Eliminating the Frame Pointer and the Arg Pointer */
1177 /* A C expression which is nonzero if a function must have and use a frame
1178 pointer. This expression is evaluated in the reload pass. If its value is
1179 nonzero the function will have a frame pointer. */
1180 #define FRAME_POINTER_REQUIRED 0
1182 /* Show we can debug even without a frame pointer. */
1183 #define CAN_DEBUG_WITHOUT_FP
1185 /* If defined, this macro specifies a table of register pairs used to eliminate
1186 unneeded registers that point into the stack frame. */
1188 #define ELIMINABLE_REGS \
1190 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1191 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1192 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1193 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1194 {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
1197 /* A C expression that returns non-zero if the compiler is allowed to try to
1198 replace register number FROM with register number TO. The frame pointer
1199 is automatically handled. */
1201 #define CAN_ELIMINATE(FROM, TO) \
1202 (TO == BR_REG (0) ? current_function_is_leaf : 1)
1204 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1205 specifies the initial difference between the specified pair of
1206 registers. This macro must be defined if `ELIMINABLE_REGS' is
1208 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1209 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO)))
1211 /* Passing Function Arguments on the Stack */
1213 /* Define this macro if an argument declared in a prototype as an integral type
1214 smaller than `int' should actually be passed as an `int'. In addition to
1215 avoiding errors in certain cases of mismatch, it also makes for better code
1216 on certain machines. */
1217 /* ??? Investigate. */
1218 /* #define PROMOTE_PROTOTYPES */
1220 /* If defined, the maximum amount of space required for outgoing arguments will
1221 be computed and placed into the variable
1222 `current_function_outgoing_args_size'. */
1224 #define ACCUMULATE_OUTGOING_ARGS 1
1226 /* A C expression that should indicate the number of bytes of its own arguments
1227 that a function pops on returning, or 0 if the function pops no arguments
1228 and the caller must therefore pop them all after the function returns. */
1230 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1233 /* Function Arguments in Registers */
1235 #define MAX_ARGUMENT_SLOTS 8
1236 #define MAX_INT_RETURN_SLOTS 4
1237 #define GR_ARG_FIRST IN_REG (0)
1238 #define GR_RET_FIRST GR_REG (8)
1239 #define GR_RET_LAST GR_REG (11)
1240 #define FR_ARG_FIRST FR_REG (8)
1241 #define FR_RET_FIRST FR_REG (8)
1242 #define FR_RET_LAST FR_REG (15)
1243 #define AR_ARG_FIRST OUT_REG (0)
1245 /* A C expression that controls whether a function argument is passed in a
1246 register, and which register. */
1248 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1249 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0)
1251 /* Define this macro if the target machine has "register windows", so that the
1252 register in which a function sees an arguments is not necessarily the same
1253 as the one in which the caller passed the argument. */
1255 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1256 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1)
1258 /* A C expression for the number of words, at the beginning of an argument,
1259 must be put in registers. The value must be zero for arguments that are
1260 passed entirely in registers or that are entirely pushed on the stack. */
1262 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1263 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1265 /* A C expression that indicates when an argument must be passed by reference.
1266 If nonzero for an argument, a copy of that argument is made in memory and a
1267 pointer to the argument is passed instead of the argument itself. The
1268 pointer is passed in whatever way is appropriate for passing a pointer to
1271 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1272 ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
1274 /* A C type for declaring a variable that is used as the first argument of
1275 `FUNCTION_ARG' and other related values. For some target machines, the type
1276 `int' suffices and can hold the number of bytes of argument so far. */
1278 typedef struct ia64_args
1280 int words; /* # words of arguments so far */
1281 int int_regs; /* # GR registers used so far */
1282 int fp_regs; /* # FR registers used so far */
1283 int prototype; /* whether function prototyped */
1286 /* A C statement (sans semicolon) for initializing the variable CUM for the
1287 state at the beginning of the argument list. */
1289 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1292 (CUM).int_regs = 0; \
1293 (CUM).fp_regs = 0; \
1294 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
1297 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the
1298 arguments for the function being compiled. If this macro is undefined,
1299 `INIT_CUMULATIVE_ARGS' is used instead. */
1301 /* We set prototype to true so that we never try to return a PARALLEL from
1303 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1306 (CUM).int_regs = 0; \
1307 (CUM).fp_regs = 0; \
1308 (CUM).prototype = 1; \
1311 /* A C statement (sans semicolon) to update the summarizer variable CUM to
1312 advance past an argument in the argument list. The values MODE, TYPE and
1313 NAMED describe that argument. Once this is done, the variable CUM is
1314 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */
1316 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1317 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED)
1319 /* If defined, a C expression that gives the alignment boundary, in bits, of an
1320 argument with the specified mode and type. */
1322 /* Arguments with alignment larger than 8 bytes start at the next even
1323 boundary. See ia64_function_arg. */
1325 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1326 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \
1327 : (((((MODE) == BLKmode \
1328 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1329 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \
1330 ? 128 : PARM_BOUNDARY)
1332 /* A C expression that is nonzero if REGNO is the number of a hard register in
1333 which function arguments are sometimes passed. This does *not* include
1334 implicit arguments such as the static chain and the structure-value address.
1335 On many machines, no registers can be used for this purpose since all
1336 function arguments are pushed on the stack. */
1337 #define FUNCTION_ARG_REGNO_P(REGNO) \
1338 (((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
1339 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
1341 /* Implement `va_start' for varargs and stdarg. */
1342 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1343 ia64_va_start (stdarg, valist, nextarg)
1345 /* Implement `va_arg'. */
1346 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1347 ia64_va_arg (valist, type)
1349 /* How Scalar Function Values are Returned */
1351 /* A C expression to create an RTX representing the place where a function
1352 returns a value of data type VALTYPE. */
1354 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1355 ia64_function_value (VALTYPE, FUNC)
1357 /* A C expression to create an RTX representing the place where a library
1358 function returns a value of mode MODE. */
1360 #define LIBCALL_VALUE(MODE) \
1361 gen_rtx_REG (MODE, \
1362 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1363 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
1364 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
1365 ? FR_RET_FIRST : GR_RET_FIRST))
1367 /* A C expression that is nonzero if REGNO is the number of a hard register in
1368 which the values of called function may come back. */
1370 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1371 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
1372 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
1375 /* How Large Values are Returned */
1377 /* A nonzero value says to return the function value in memory, just as large
1378 structures are always returned. */
1380 #define RETURN_IN_MEMORY(TYPE) \
1381 ia64_return_in_memory (TYPE)
1383 /* If you define this macro to be 0, then the conventions used for structure
1384 and union return values are decided by the `RETURN_IN_MEMORY' macro. */
1386 #define DEFAULT_PCC_STRUCT_RETURN 0
1388 /* If the structure value address is passed in a register, then
1389 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1391 #define STRUCT_VALUE_REGNUM GR_REG (8)
1394 /* Caller-Saves Register Allocation */
1396 /* A C expression to determine whether it is worthwhile to consider placing a
1397 pseudo-register in a call-clobbered hard register and saving and restoring
1398 it around each function call. The expression should be 1 when this is worth
1399 doing, and 0 otherwise.
1401 If you don't define this macro, a default is used which is good on most
1402 machines: `4 * CALLS < REFS'. */
1403 /* ??? Investigate. */
1404 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */
1407 /* Function Entry and Exit */
1409 /* Define this macro as a C expression that is nonzero if the return
1410 instruction or the function epilogue ignores the value of the stack pointer;
1411 in other words, if it is safe to delete an instruction to adjust the stack
1412 pointer before a return from the function. */
1414 #define EXIT_IGNORE_STACK 1
1416 /* Define this macro as a C expression that is nonzero for registers
1417 used by the epilogue or the `return' pattern. */
1419 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
1421 /* Nonzero for registers used by the exception handling mechanism. */
1423 #define EH_USES(REGNO) ia64_eh_uses (REGNO)
1425 /* Output at beginning of assembler file. */
1427 #define ASM_FILE_START(FILE) \
1428 emit_safe_across_calls (FILE)
1430 /* A C compound statement that outputs the assembler code for a thunk function,
1431 used to implement C++ virtual function calls with multiple inheritance. */
1433 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1435 if (CONST_OK_FOR_I (DELTA)) \
1437 fprintf (FILE, "\tadds r32 = "); \
1438 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1439 fprintf (FILE, ", r32\n"); \
1443 if (CONST_OK_FOR_J (DELTA)) \
1445 fprintf (FILE, "\taddl r2 = "); \
1446 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1447 fprintf (FILE, ", r0\n"); \
1451 fprintf (FILE, "\tmovl r2 = "); \
1452 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, (DELTA)); \
1453 fprintf (FILE, "\n"); \
1455 fprintf (FILE, "\t;;\n"); \
1456 fprintf (FILE, "\tadd r32 = r2, r32\n"); \
1458 fprintf (FILE, "\tbr "); \
1459 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1460 fprintf (FILE, "\n"); \
1463 /* Output part N of a function descriptor for DECL. For ia64, both
1464 words are emitted with a single relocation, so ignore N > 0. */
1465 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
1469 fputs ("\tdata16.ua @iplt(", FILE); \
1470 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
1471 fputs (")\n", FILE); \
1475 /* Generating Code for Profiling. */
1477 /* A C statement or compound statement to output to FILE some assembler code to
1478 call the profiling subroutine `mcount'. */
1480 #undef FUNCTION_PROFILER
1481 #define FUNCTION_PROFILER(FILE, LABELNO) \
1484 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
1485 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
1486 if (TARGET_AUTO_PIC) \
1487 fputs ("\tmovl out3 = @gprel(", FILE); \
1489 fputs ("\taddl out3 = @ltoff(", FILE); \
1490 assemble_name (FILE, buf); \
1491 if (TARGET_AUTO_PIC) \
1492 fputs (");;\n", FILE); \
1494 fputs ("), r1;;\n", FILE); \
1495 fputs ("\tmov out1 = r1\n", FILE); \
1496 fputs ("\tmov out2 = b0\n", FILE); \
1497 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
1500 /* Implementing the Varargs Macros. */
1502 /* Define this macro to store the anonymous register arguments into the stack
1503 so that all the arguments appear to have been passed consecutively on the
1506 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
1507 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
1509 /* Define this macro if the location where a function argument is passed
1510 depends on whether or not it is a named argument. */
1512 #define STRICT_ARGUMENT_NAMING 1
1515 /* Trampolines for Nested Functions. */
1517 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of
1518 the function containing a non-local goto target. */
1520 #define STACK_SAVEAREA_MODE(LEVEL) \
1521 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode)
1523 /* Output assembler code for a block containing the constant parts of
1524 a trampoline, leaving space for the variable parts.
1526 The trampoline should set the static chain pointer to value placed
1527 into the trampoline and should branch to the specified routine.
1528 To make the normal indirect-subroutine calling convention work,
1529 the trampoline must look like a function descriptor; the first
1530 word being the target address and the second being the target's
1533 We abuse the concept of a global pointer by arranging for it
1534 to point to the data we need to load. The complete trampoline
1535 has the following form:
1537 +-------------------+ \
1538 TRAMP: | __ia64_trampoline | |
1539 +-------------------+ > fake function descriptor
1541 +-------------------+ /
1542 | target descriptor |
1543 +-------------------+
1545 +-------------------+
1548 /* A C expression for the size in bytes of the trampoline, as an integer. */
1550 #define TRAMPOLINE_SIZE 32
1552 /* Alignment required for trampolines, in bits. */
1554 #define TRAMPOLINE_ALIGNMENT 64
1556 /* A C statement to initialize the variable parts of a trampoline. */
1558 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
1559 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN))
1561 /* Implicit Calls to Library Routines */
1563 /* Define this macro if GNU CC should generate calls to the System V (and ANSI
1564 C) library functions `memcpy' and `memset' rather than the BSD functions
1565 `bcopy' and `bzero'. */
1567 #define TARGET_MEM_FUNCTIONS
1570 /* Addressing Modes */
1572 /* Define this macro if the machine supports post-increment addressing. */
1574 #define HAVE_POST_INCREMENT 1
1575 #define HAVE_POST_DECREMENT 1
1576 #define HAVE_POST_MODIFY_DISP 1
1577 #define HAVE_POST_MODIFY_REG 1
1579 /* A C expression that is 1 if the RTX X is a constant which is a valid
1582 #define CONSTANT_ADDRESS_P(X) 0
1584 /* The max number of registers that can appear in a valid memory address. */
1586 #define MAX_REGS_PER_ADDRESS 2
1588 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
1589 RTX) is a legitimate memory address on the target machine for a memory
1590 operand of mode MODE. */
1592 #define LEGITIMATE_ADDRESS_REG(X) \
1593 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1594 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \
1595 && REG_OK_FOR_BASE_P (XEXP (X, 0))))
1597 #define LEGITIMATE_ADDRESS_DISP(R, X) \
1598 (GET_CODE (X) == PLUS \
1599 && rtx_equal_p (R, XEXP (X, 0)) \
1600 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \
1601 || (GET_CODE (XEXP (X, 1)) == CONST_INT \
1602 && INTVAL (XEXP (X, 1)) >= -256 \
1603 && INTVAL (XEXP (X, 1)) < 256)))
1605 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1607 if (LEGITIMATE_ADDRESS_REG (X)) \
1609 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
1610 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1611 && XEXP (X, 0) != arg_pointer_rtx) \
1613 else if (GET_CODE (X) == POST_MODIFY \
1614 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \
1615 && XEXP (X, 0) != arg_pointer_rtx \
1616 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \
1620 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1621 use as a base register. */
1623 #ifdef REG_OK_STRICT
1624 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1626 #define REG_OK_FOR_BASE_P(X) \
1627 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER))
1630 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for
1631 use as an index register. This is needed for POST_MODIFY. */
1633 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
1635 /* A C compound statement that attempts to replace X with a valid memory
1636 address for an operand of mode MODE.
1638 This must be present, but there is nothing useful to be done here. */
1640 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
1642 /* A C statement or compound statement with a conditional `goto LABEL;'
1643 executed if memory address X (an RTX) can have different meanings depending
1644 on the machine mode of the memory reference it is used for or if the address
1645 is valid for some modes but not others. */
1647 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1648 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \
1651 /* A C expression that is nonzero if X is a legitimate constant for an
1652 immediate operand on the target machine. */
1654 #define LEGITIMATE_CONSTANT_P(X) \
1655 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1656 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \
1659 /* Condition Code Status */
1661 /* One some machines not all possible comparisons are defined, but you can
1662 convert an invalid comparison into a valid one. */
1663 /* ??? Investigate. See the alpha definition. */
1664 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */
1667 /* Describing Relative Costs of Operations */
1669 /* A part of a C `switch' statement that describes the relative costs of
1670 constant RTL expressions. */
1672 /* ??? This is incomplete. */
1674 #define CONST_COSTS(X, CODE, OUTER_CODE) \
1676 if ((X) == const0_rtx) \
1678 switch (OUTER_CODE) \
1681 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
1683 if (CONST_OK_FOR_I (INTVAL (X))) \
1685 if (CONST_OK_FOR_J (INTVAL (X))) \
1687 return COSTS_N_INSNS (1); \
1689 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
1691 return COSTS_N_INSNS (1); \
1693 case CONST_DOUBLE: \
1694 return COSTS_N_INSNS (1); \
1698 return COSTS_N_INSNS (3);
1700 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
1702 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1704 /* For multiplies wider than HImode, we have to go to the FPU, \
1705 which normally involves copies. Plus there's the latency \
1706 of the multiply itself, and the latency of the instructions to \
1707 transfer integer regs to FP regs. */ \
1708 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
1709 return COSTS_N_INSNS (10); \
1710 return COSTS_N_INSNS (2); \
1716 return COSTS_N_INSNS (1); \
1721 /* We make divide expensive, so that divide-by-constant will be \
1722 optimized to a multiply. */ \
1723 return COSTS_N_INSNS (60);
1725 /* An expression giving the cost of an addressing mode that contains ADDRESS.
1726 If not defined, the cost is computed from the ADDRESS expression and the
1727 `CONST_COSTS' values. */
1729 #define ADDRESS_COST(ADDRESS) 0
1731 /* A C expression for the cost of moving data from a register in class FROM to
1732 one in class TO, using MODE. */
1734 #define REGISTER_MOVE_COST ia64_register_move_cost
1736 /* A C expression for the cost of moving data of mode M between a
1737 register and memory. */
1738 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
1739 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
1740 || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
1742 /* A C expression for the cost of a branch instruction. A value of 1 is the
1743 default; other values are interpreted relative to that. Used by the
1744 if-conversion code as max instruction count. */
1745 /* ??? This requires investigation. The primary effect might be how
1746 many additional insn groups we run into, vs how good the dynamic
1747 branch predictor is. */
1749 #define BRANCH_COST 6
1751 /* Define this macro as a C expression which is nonzero if accessing less than
1752 a word of memory (i.e. a `char' or a `short') is no faster than accessing a
1755 #define SLOW_BYTE_ACCESS 1
1757 /* Define this macro if it is as good or better to call a constant function
1758 address than to call an address kept in a register.
1760 Indirect function calls are more expensive that direct function calls, so
1761 don't cse function addresses. */
1763 #define NO_FUNCTION_CSE
1766 /* Dividing the output into sections. */
1768 /* A C expression whose value is a string containing the assembler operation
1769 that should precede instructions and read-only data. */
1771 #define TEXT_SECTION_ASM_OP "\t.text"
1773 /* A C expression whose value is a string containing the assembler operation to
1774 identify the following data as writable initialized data. */
1776 #define DATA_SECTION_ASM_OP "\t.data"
1778 /* If defined, a C expression whose value is a string containing the assembler
1779 operation to identify the following data as uninitialized global data. */
1781 #define BSS_SECTION_ASM_OP "\t.bss"
1783 /* Define this macro if references to a symbol must be treated differently
1784 depending on something about the variable or function named by the symbol
1785 (such as what section it is in). */
1787 #define ENCODE_SECTION_INFO(DECL, FIRST) ia64_encode_section_info (DECL, FIRST)
1789 #define SDATA_NAME_FLAG_CHAR '@'
1791 #define IA64_DEFAULT_GVALUE 8
1793 /* Decode SYM_NAME and store the real name part in VAR, sans the characters
1794 that encode section info. */
1796 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1798 (VAR) = (SYMBOL_NAME); \
1799 if ((VAR)[0] == SDATA_NAME_FLAG_CHAR) \
1801 if ((VAR)[0] == '*') \
1805 /* Position Independent Code. */
1807 /* The register number of the register used to address a table of static data
1808 addresses in memory. */
1810 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of
1811 gen_rtx_REG (DImode, 1). */
1813 /* ??? Should we set flag_pic? Probably need to define
1814 LEGITIMIZE_PIC_OPERAND_P to make that work. */
1816 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1)
1818 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is
1819 clobbered by calls. */
1821 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
1824 /* The Overall Framework of an Assembler File. */
1826 /* A C string constant describing how to begin a comment in the target
1827 assembler language. The compiler assumes that the comment will end at the
1830 #define ASM_COMMENT_START "//"
1832 /* A C string constant for text to be output before each `asm' statement or
1833 group of consecutive ones. */
1835 /* ??? This won't work with the Intel assembler, because it does not accept
1836 # as a comment start character. However, //APP does not work in gas, so we
1837 can't use that either. Same problem for ASM_APP_OFF below. */
1839 #define ASM_APP_ON "#APP\n"
1841 /* A C string constant for text to be output after each `asm' statement or
1842 group of consecutive ones. */
1844 #define ASM_APP_OFF "#NO_APP\n"
1847 /* Output of Data. */
1849 /* This is how to output an assembler line defining a `char' constant
1850 to an xdata segment. */
1852 #define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
1854 fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
1855 output_addr_const (FILE, (VALUE)); \
1856 fprintf (FILE, "\n"); \
1859 /* This is how to output an assembler line defining a `short' constant
1860 to an xdata segment. */
1862 #define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
1864 fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
1865 output_addr_const (FILE, (VALUE)); \
1866 fprintf (FILE, "\n"); \
1869 /* This is how to output an assembler line defining an `int' constant
1870 to an xdata segment. We also handle symbol output here. */
1872 /* ??? For ILP32, also need to handle function addresses here. */
1874 #define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
1876 fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
1877 output_addr_const (FILE, (VALUE)); \
1878 fprintf (FILE, "\n"); \
1881 /* This is how to output an assembler line defining a `long' constant
1882 to an xdata segment. We also handle symbol output here. */
1884 #define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
1886 int need_closing_paren = 0; \
1887 fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
1888 if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
1889 && GET_CODE (VALUE) == SYMBOL_REF) \
1891 fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
1892 need_closing_paren = 1; \
1894 output_addr_const (FILE, VALUE); \
1895 if (need_closing_paren) \
1896 fprintf (FILE, ")"); \
1897 fprintf (FILE, "\n"); \
1902 /* Output of Uninitialized Variables. */
1904 /* This is all handled by svr4.h. */
1907 /* Output and Generation of Labels. */
1909 /* A C statement (sans semicolon) to output to the stdio stream STREAM the
1910 assembler definition of a label named NAME. */
1912 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of
1913 why ia64_asm_output_label exists. */
1915 extern int ia64_asm_output_label;
1916 #define ASM_OUTPUT_LABEL(STREAM, NAME) \
1918 ia64_asm_output_label = 1; \
1919 assemble_name (STREAM, NAME); \
1920 fputs (":\n", STREAM); \
1921 ia64_asm_output_label = 0; \
1924 /* A C statement (sans semicolon) to output to the stdio stream STREAM some
1925 commands that will make the label NAME global; that is, available for
1926 reference from other files. */
1928 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1930 fputs ("\t.global ", STREAM); \
1931 assemble_name (STREAM, NAME); \
1932 fputs ("\n", STREAM); \
1935 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text
1936 necessary for declaring the name of an external symbol named NAME which is
1937 referenced in this compilation but not defined. */
1939 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1940 ia64_asm_output_external (FILE, DECL, NAME)
1942 /* A C statement to store into the string STRING a label whose name is made
1943 from the string PREFIX and the number NUM. */
1945 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1947 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
1950 /* A C expression to assign to OUTVAR (which is a variable of type `char *') a
1951 newly allocated string made from the string NAME and the number NUMBER, with
1952 some suitable punctuation added. */
1954 /* ??? Not sure if using a ? in the name for Intel as is safe. */
1956 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
1958 (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \
1959 sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \
1963 /* A C statement to output to the stdio stream STREAM assembler code which
1964 defines (equates) the symbol NAME to have the value VALUE. */
1966 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1968 assemble_name (STREAM, NAME); \
1969 fputs (" = ", STREAM); \
1970 assemble_name (STREAM, VALUE); \
1971 fputc ('\n', STREAM); \
1975 /* Macros Controlling Initialization Routines. */
1977 /* This is handled by svr4.h and sysv4.h. */
1980 /* Output of Assembler Instructions. */
1982 /* A C initializer containing the assembler's names for the machine registers,
1983 each one as a C string constant. */
1985 #define REGISTER_NAMES \
1987 /* General registers. */ \
1988 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
1989 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1990 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1992 /* Local registers. */ \
1993 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \
1994 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \
1995 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \
1996 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \
1997 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \
1998 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \
1999 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \
2000 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \
2001 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \
2002 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \
2003 /* Input registers. */ \
2004 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \
2005 /* Output registers. */ \
2006 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \
2007 /* Floating-point registers. */ \
2008 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
2009 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
2010 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
2011 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \
2012 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \
2013 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \
2014 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \
2015 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \
2016 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \
2017 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \
2018 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\
2019 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\
2020 "f120","f121","f122","f123","f124","f125","f126","f127", \
2021 /* Predicate registers. */ \
2022 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \
2023 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \
2024 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \
2025 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \
2026 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \
2027 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \
2028 "p60", "p61", "p62", "p63", \
2029 /* Branch registers. */ \
2030 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
2031 /* Frame pointer. Return address. */ \
2032 "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
2035 /* If defined, a C initializer for an array of structures containing a name and
2036 a register number. This macro defines additional names for hard registers,
2037 thus allowing the `asm' option in declarations to refer to registers using
2040 #define ADDITIONAL_REGISTER_NAMES \
2042 { "gp", R_GR (1) }, \
2043 { "sp", R_GR (12) }, \
2044 { "in0", IN_REG (0) }, \
2045 { "in1", IN_REG (1) }, \
2046 { "in2", IN_REG (2) }, \
2047 { "in3", IN_REG (3) }, \
2048 { "in4", IN_REG (4) }, \
2049 { "in5", IN_REG (5) }, \
2050 { "in6", IN_REG (6) }, \
2051 { "in7", IN_REG (7) }, \
2052 { "out0", OUT_REG (0) }, \
2053 { "out1", OUT_REG (1) }, \
2054 { "out2", OUT_REG (2) }, \
2055 { "out3", OUT_REG (3) }, \
2056 { "out4", OUT_REG (4) }, \
2057 { "out5", OUT_REG (5) }, \
2058 { "out6", OUT_REG (6) }, \
2059 { "out7", OUT_REG (7) }, \
2060 { "loc0", LOC_REG (0) }, \
2061 { "loc1", LOC_REG (1) }, \
2062 { "loc2", LOC_REG (2) }, \
2063 { "loc3", LOC_REG (3) }, \
2064 { "loc4", LOC_REG (4) }, \
2065 { "loc5", LOC_REG (5) }, \
2066 { "loc6", LOC_REG (6) }, \
2067 { "loc7", LOC_REG (7) }, \
2068 { "loc8", LOC_REG (8) }, \
2069 { "loc9", LOC_REG (9) }, \
2070 { "loc10", LOC_REG (10) }, \
2071 { "loc11", LOC_REG (11) }, \
2072 { "loc12", LOC_REG (12) }, \
2073 { "loc13", LOC_REG (13) }, \
2074 { "loc14", LOC_REG (14) }, \
2075 { "loc15", LOC_REG (15) }, \
2076 { "loc16", LOC_REG (16) }, \
2077 { "loc17", LOC_REG (17) }, \
2078 { "loc18", LOC_REG (18) }, \
2079 { "loc19", LOC_REG (19) }, \
2080 { "loc20", LOC_REG (20) }, \
2081 { "loc21", LOC_REG (21) }, \
2082 { "loc22", LOC_REG (22) }, \
2083 { "loc23", LOC_REG (23) }, \
2084 { "loc24", LOC_REG (24) }, \
2085 { "loc25", LOC_REG (25) }, \
2086 { "loc26", LOC_REG (26) }, \
2087 { "loc27", LOC_REG (27) }, \
2088 { "loc28", LOC_REG (28) }, \
2089 { "loc29", LOC_REG (29) }, \
2090 { "loc30", LOC_REG (30) }, \
2091 { "loc31", LOC_REG (31) }, \
2092 { "loc32", LOC_REG (32) }, \
2093 { "loc33", LOC_REG (33) }, \
2094 { "loc34", LOC_REG (34) }, \
2095 { "loc35", LOC_REG (35) }, \
2096 { "loc36", LOC_REG (36) }, \
2097 { "loc37", LOC_REG (37) }, \
2098 { "loc38", LOC_REG (38) }, \
2099 { "loc39", LOC_REG (39) }, \
2100 { "loc40", LOC_REG (40) }, \
2101 { "loc41", LOC_REG (41) }, \
2102 { "loc42", LOC_REG (42) }, \
2103 { "loc43", LOC_REG (43) }, \
2104 { "loc44", LOC_REG (44) }, \
2105 { "loc45", LOC_REG (45) }, \
2106 { "loc46", LOC_REG (46) }, \
2107 { "loc47", LOC_REG (47) }, \
2108 { "loc48", LOC_REG (48) }, \
2109 { "loc49", LOC_REG (49) }, \
2110 { "loc50", LOC_REG (50) }, \
2111 { "loc51", LOC_REG (51) }, \
2112 { "loc52", LOC_REG (52) }, \
2113 { "loc53", LOC_REG (53) }, \
2114 { "loc54", LOC_REG (54) }, \
2115 { "loc55", LOC_REG (55) }, \
2116 { "loc56", LOC_REG (56) }, \
2117 { "loc57", LOC_REG (57) }, \
2118 { "loc58", LOC_REG (58) }, \
2119 { "loc59", LOC_REG (59) }, \
2120 { "loc60", LOC_REG (60) }, \
2121 { "loc61", LOC_REG (61) }, \
2122 { "loc62", LOC_REG (62) }, \
2123 { "loc63", LOC_REG (63) }, \
2124 { "loc64", LOC_REG (64) }, \
2125 { "loc65", LOC_REG (65) }, \
2126 { "loc66", LOC_REG (66) }, \
2127 { "loc67", LOC_REG (67) }, \
2128 { "loc68", LOC_REG (68) }, \
2129 { "loc69", LOC_REG (69) }, \
2130 { "loc70", LOC_REG (70) }, \
2131 { "loc71", LOC_REG (71) }, \
2132 { "loc72", LOC_REG (72) }, \
2133 { "loc73", LOC_REG (73) }, \
2134 { "loc74", LOC_REG (74) }, \
2135 { "loc75", LOC_REG (75) }, \
2136 { "loc76", LOC_REG (76) }, \
2137 { "loc77", LOC_REG (77) }, \
2138 { "loc78", LOC_REG (78) }, \
2139 { "loc79", LOC_REG (79) }, \
2142 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2143 for an instruction operand X. X is an RTL expression. */
2145 #define PRINT_OPERAND(STREAM, X, CODE) \
2146 ia64_print_operand (STREAM, X, CODE)
2148 /* A C expression which evaluates to true if CODE is a valid punctuation
2149 character for use in the `PRINT_OPERAND' macro. */
2151 /* ??? Keep this around for now, as we might need it later. */
2153 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2154 ((CODE) == '+' || (CODE) == ',')
2156 /* A C compound statement to output to stdio stream STREAM the assembler syntax
2157 for an instruction operand that is a memory reference whose address is X. X
2158 is an RTL expression. */
2160 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2161 ia64_print_operand_address (STREAM, X)
2163 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and
2164 `%I' options of `asm_fprintf' (see `final.c'). */
2166 #define REGISTER_PREFIX ""
2167 #define LOCAL_LABEL_PREFIX "."
2168 #define USER_LABEL_PREFIX ""
2169 #define IMMEDIATE_PREFIX ""
2172 /* Output of dispatch tables. */
2174 /* This macro should be provided on machines where the addresses in a dispatch
2175 table are relative to the table's own address. */
2177 /* ??? Depends on the pointer size. */
2179 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2180 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
2182 /* This is how to output an element of a case-vector that is absolute.
2183 (Ia64 does not use such vectors, but we must define this macro anyway.) */
2185 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort ()
2187 /* Jump tables only need 8 byte alignment. */
2189 #define ADDR_VEC_ALIGN(ADDR_VEC) 3
2192 /* Assembler Commands for Exception Regions. */
2194 /* Select a format to encode pointers in exception handling data. CODE
2195 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2196 true if the symbol may be affected by dynamic relocations. */
2197 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2198 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
2199 | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
2201 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2202 indirect are handled automatically. */
2203 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2205 const char *reltag = NULL; \
2206 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \
2207 reltag = "@segrel("; \
2208 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \
2209 reltag = "@gprel("; \
2212 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2213 fputs (reltag, FILE); \
2214 assemble_name (FILE, XSTR (ADDR, 0)); \
2215 fputc (')', FILE); \
2221 /* Assembler Commands for Alignment. */
2223 /* ??? Investigate. */
2225 /* The alignment (log base 2) to put in front of LABEL, which follows
2228 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */
2230 /* The desired alignment for the location counter at the beginning
2233 /* #define LOOP_ALIGN(LABEL) */
2235 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text
2236 section because it fails put zeros in the bytes that are skipped. */
2238 #define ASM_NO_SKIP_IN_TEXT 1
2240 /* A C statement to output to the stdio stream STREAM an assembler command to
2241 advance the location counter to a multiple of 2 to the POWER bytes. */
2243 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
2244 fprintf (STREAM, "\t.align %d\n", 1<<(POWER))
2247 /* Macros Affecting all Debug Formats. */
2249 /* This is handled in svr4.h and sysv4.h. */
2252 /* Specific Options for DBX Output. */
2254 /* This is handled by dbxelf.h which is included by svr4.h. */
2257 /* Open ended Hooks for DBX Output. */
2262 /* File names in DBX format. */
2267 /* Macros for SDB and Dwarf Output. */
2269 /* Define this macro if GNU CC should produce dwarf version 2 format debugging
2270 output in response to the `-g' option. */
2272 #define DWARF2_DEBUGGING_INFO
2274 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
2276 /* Use tags for debug info labels, so that they don't break instruction
2277 bundles. This also avoids getting spurious DV warnings from the
2278 assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we
2279 add brackets around the label. */
2281 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2282 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
2284 /* Use section-relative relocations for debugging offsets. Unlike other
2285 targets that fake this by putting the section VMA at 0, IA-64 has
2286 proper relocations for them. */
2287 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
2289 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2290 fputs ("@secrel(", FILE); \
2291 assemble_name (FILE, LABEL); \
2292 fputc (')', FILE); \
2295 /* Emit a PC-relative relocation. */
2296 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
2298 fputs (integer_asm_op (SIZE, FALSE), FILE); \
2299 fputs ("@pcrel(", FILE); \
2300 assemble_name (FILE, LABEL); \
2301 fputc (')', FILE); \
2304 /* Register Renaming Parameters. */
2306 /* A C expression that is nonzero if hard register number REGNO2 can be
2307 considered for use as a rename register for REGNO1 */
2309 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
2310 ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
2313 /* Miscellaneous Parameters. */
2315 /* Define this if you have defined special-purpose predicates in the file
2316 `MACHINE.c'. For each predicate, list all rtl codes that can be in
2317 expressions matched by the predicate. */
2319 #define PREDICATE_CODES \
2320 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
2321 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2322 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
2323 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2324 { "function_operand", {SYMBOL_REF}}, \
2325 { "setjmp_operand", {SYMBOL_REF}}, \
2326 { "destination_operand", {SUBREG, REG, MEM}}, \
2327 { "not_postinc_memory_operand", {MEM}}, \
2328 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2329 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \
2330 { "gr_register_operand", {SUBREG, REG}}, \
2331 { "fr_register_operand", {SUBREG, REG}}, \
2332 { "grfr_register_operand", {SUBREG, REG}}, \
2333 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2334 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2335 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \
2336 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2337 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2338 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2339 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2340 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2341 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \
2343 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \
2345 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2346 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2347 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
2348 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \
2350 { "shladd_operand", {CONST_INT}}, \
2351 { "fetchadd_operand", {CONST_INT}}, \
2352 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2353 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \
2354 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \
2355 { "signed_inequality_operator", {GE, GT, LE, LT}}, \
2356 { "predicate_operator", {NE, EQ}}, \
2357 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \
2358 { "ar_lc_reg_operand", {REG}}, \
2359 { "ar_ccv_reg_operand", {REG}}, \
2360 { "ar_pfs_reg_operand", {REG}}, \
2361 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2362 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
2363 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
2364 { "basereg_operand", {SUBREG, REG}},
2366 /* An alias for a machine mode name. This is the machine mode that elements of
2367 a jump-table should have. */
2369 #define CASE_VECTOR_MODE Pmode
2371 /* Define as C expression which evaluates to nonzero if the tablejump
2372 instruction expects the table to contain offsets from the address of the
2375 #define CASE_VECTOR_PC_RELATIVE 1
2377 /* Define this macro if operations between registers with integral mode smaller
2378 than a word are always performed on the entire register. */
2380 #define WORD_REGISTER_OPERATIONS
2382 /* Define this macro to be a C expression indicating when insns that read
2383 memory in MODE, an integral mode narrower than a word, set the bits outside
2384 of MODE to be either the sign-extension or the zero-extension of the data
2387 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2389 /* The maximum number of bytes that a single instruction can move quickly from
2390 memory to memory. */
2393 /* A C expression which is nonzero if on this machine it is safe to "convert"
2394 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller
2395 than INPREC) by merely operating on it as if it had only OUTPREC bits. */
2397 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2399 /* A C expression describing the value returned by a comparison operator with
2400 an integral mode and stored by a store-flag instruction (`sCOND') when the
2401 condition is true. */
2403 /* ??? Investigate using -1 instead of 1. */
2405 #define STORE_FLAG_VALUE 1
2407 /* An alias for the machine mode for pointers. */
2409 /* ??? This would change if we had ILP32 support. */
2411 #define Pmode DImode
2413 /* An alias for the machine mode used for memory references to functions being
2414 called, in `call' RTL expressions. */
2416 #define FUNCTION_MODE Pmode
2418 /* Define this macro to handle System V style pragmas: #pragma pack and
2419 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
2422 /* If this architecture supports prefetch, define this to be the number of
2423 prefetch commands that can be executed in parallel.
2425 ??? This number is bogus and needs to be replaced before the value is
2426 actually used in optimizations. */
2428 #define SIMULTANEOUS_PREFETCHES 6
2430 /* If this architecture supports prefetch, define this to be the size of
2431 the cache line that is prefetched. */
2433 #define PREFETCH_BLOCK 32
2435 #define HANDLE_SYSV_PRAGMA
2437 /* In rare cases, correct code generation requires extra machine dependent
2438 processing between the second jump optimization pass and delayed branch
2439 scheduling. On those machines, define this macro as a C statement to act on
2440 the code starting at INSN. */
2442 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
2444 /* A C expression for the maximum number of instructions to execute via
2445 conditional execution instructions instead of a branch. A value of
2446 BRANCH_COST+1 is the default if the machine does not use
2447 cc0, and 1 if it does use cc0. */
2448 /* ??? Investigate. */
2449 #define MAX_CONDITIONAL_EXECUTE 12
2451 extern int ia64_final_schedule;
2453 #define IA64_UNWIND_INFO 1
2454 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i)
2456 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
2458 /* This function contains machine specific function data. */
2459 struct machine_function
2461 /* The new stack pointer when unwinding from EH. */
2462 struct rtx_def* ia64_eh_epilogue_sp;
2464 /* The new bsp value when unwinding from EH. */
2465 struct rtx_def* ia64_eh_epilogue_bsp;
2467 /* The GP value save register. */
2468 struct rtx_def* ia64_gp_save;
2470 /* The number of varargs registers to save. */
2477 IA64_BUILTIN_SYNCHRONIZE,
2479 IA64_BUILTIN_FETCH_AND_ADD_SI,
2480 IA64_BUILTIN_FETCH_AND_SUB_SI,
2481 IA64_BUILTIN_FETCH_AND_OR_SI,
2482 IA64_BUILTIN_FETCH_AND_AND_SI,
2483 IA64_BUILTIN_FETCH_AND_XOR_SI,
2484 IA64_BUILTIN_FETCH_AND_NAND_SI,
2486 IA64_BUILTIN_ADD_AND_FETCH_SI,
2487 IA64_BUILTIN_SUB_AND_FETCH_SI,
2488 IA64_BUILTIN_OR_AND_FETCH_SI,
2489 IA64_BUILTIN_AND_AND_FETCH_SI,
2490 IA64_BUILTIN_XOR_AND_FETCH_SI,
2491 IA64_BUILTIN_NAND_AND_FETCH_SI,
2493 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI,
2494 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI,
2496 IA64_BUILTIN_SYNCHRONIZE_SI,
2498 IA64_BUILTIN_LOCK_TEST_AND_SET_SI,
2500 IA64_BUILTIN_LOCK_RELEASE_SI,
2502 IA64_BUILTIN_FETCH_AND_ADD_DI,
2503 IA64_BUILTIN_FETCH_AND_SUB_DI,
2504 IA64_BUILTIN_FETCH_AND_OR_DI,
2505 IA64_BUILTIN_FETCH_AND_AND_DI,
2506 IA64_BUILTIN_FETCH_AND_XOR_DI,
2507 IA64_BUILTIN_FETCH_AND_NAND_DI,
2509 IA64_BUILTIN_ADD_AND_FETCH_DI,
2510 IA64_BUILTIN_SUB_AND_FETCH_DI,
2511 IA64_BUILTIN_OR_AND_FETCH_DI,
2512 IA64_BUILTIN_AND_AND_FETCH_DI,
2513 IA64_BUILTIN_XOR_AND_FETCH_DI,
2514 IA64_BUILTIN_NAND_AND_FETCH_DI,
2516 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI,
2517 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI,
2519 IA64_BUILTIN_SYNCHRONIZE_DI,
2521 IA64_BUILTIN_LOCK_TEST_AND_SET_DI,
2523 IA64_BUILTIN_LOCK_RELEASE_DI,
2526 IA64_BUILTIN_FLUSHRS
2529 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */
2531 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
2534 #define DONT_USE_BUILTIN_SETJMP
2536 /* Output any profiling code before the prologue. */
2538 #undef PROFILE_BEFORE_PROLOGUE
2539 #define PROFILE_BEFORE_PROLOGUE 1
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