1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
53 /* This is used for communication between ASM_OUTPUT_LABEL and
54 ASM_OUTPUT_LABELREF. */
55 int ia64_asm_output_label = 0;
57 /* Define the information needed to generate branch and scc insns. This is
58 stored from the compare operation. */
59 struct rtx_def * ia64_compare_op0;
60 struct rtx_def * ia64_compare_op1;
62 /* Register names for ia64_expand_prologue. */
63 static const char * const ia64_reg_numbers[96] =
64 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
65 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
66 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
67 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
68 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
69 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
70 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
71 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
72 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
73 "r104","r105","r106","r107","r108","r109","r110","r111",
74 "r112","r113","r114","r115","r116","r117","r118","r119",
75 "r120","r121","r122","r123","r124","r125","r126","r127"};
77 /* ??? These strings could be shared with REGISTER_NAMES. */
78 static const char * const ia64_input_reg_names[8] =
79 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
81 /* ??? These strings could be shared with REGISTER_NAMES. */
82 static const char * const ia64_local_reg_names[80] =
83 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
84 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
85 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
86 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
87 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
88 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
89 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
90 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
91 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
92 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
94 /* ??? These strings could be shared with REGISTER_NAMES. */
95 static const char * const ia64_output_reg_names[8] =
96 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
98 /* String used with the -mfixed-range= option. */
99 const char *ia64_fixed_range_string;
101 /* Determines whether we use adds, addl, or movl to generate our
102 TLS immediate offsets. */
103 int ia64_tls_size = 22;
105 /* String used with the -mtls-size= option. */
106 const char *ia64_tls_size_string;
108 /* Which cpu are we scheduling for. */
109 enum processor_type ia64_tune;
111 /* String used with the -tune= option. */
112 const char *ia64_tune_string;
114 /* Determines whether we run our final scheduling pass or not. We always
115 avoid the normal second scheduling pass. */
116 static int ia64_flag_schedule_insns2;
118 /* Variables which are this size or smaller are put in the sdata/sbss
121 unsigned int ia64_section_threshold;
123 /* The following variable is used by the DFA insn scheduler. The value is
124 TRUE if we do insn bundling instead of insn scheduling. */
127 /* Structure to be filled in by ia64_compute_frame_size with register
128 save masks and offsets for the current function. */
130 struct ia64_frame_info
132 HOST_WIDE_INT total_size; /* size of the stack frame, not including
133 the caller's scratch area. */
134 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
135 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
136 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
137 HARD_REG_SET mask; /* mask of saved registers. */
138 unsigned int gr_used_mask; /* mask of registers in use as gr spill
139 registers or long-term scratches. */
140 int n_spilled; /* number of spilled registers. */
141 int reg_fp; /* register for fp. */
142 int reg_save_b0; /* save register for b0. */
143 int reg_save_pr; /* save register for prs. */
144 int reg_save_ar_pfs; /* save register for ar.pfs. */
145 int reg_save_ar_unat; /* save register for ar.unat. */
146 int reg_save_ar_lc; /* save register for ar.lc. */
147 int reg_save_gp; /* save register for gp. */
148 int n_input_regs; /* number of input registers used. */
149 int n_local_regs; /* number of local registers used. */
150 int n_output_regs; /* number of output registers used. */
151 int n_rotate_regs; /* number of rotating registers used. */
153 char need_regstk; /* true if a .regstk directive needed. */
154 char initialized; /* true if the data is finalized. */
157 /* Current frame information calculated by ia64_compute_frame_size. */
158 static struct ia64_frame_info current_frame_info;
160 static int ia64_use_dfa_pipeline_interface PARAMS ((void));
161 static int ia64_first_cycle_multipass_dfa_lookahead PARAMS ((void));
162 static void ia64_dependencies_evaluation_hook PARAMS ((rtx, rtx));
163 static void ia64_init_dfa_pre_cycle_insn PARAMS ((void));
164 static rtx ia64_dfa_pre_cycle_insn PARAMS ((void));
165 static int ia64_first_cycle_multipass_dfa_lookahead_guard PARAMS ((rtx));
166 static int ia64_dfa_new_cycle PARAMS ((FILE *, int, rtx, int, int, int *));
167 static rtx gen_tls_get_addr PARAMS ((void));
168 static rtx gen_thread_pointer PARAMS ((void));
169 static rtx ia64_expand_tls_address PARAMS ((enum tls_model, rtx, rtx));
170 static int find_gr_spill PARAMS ((int));
171 static int next_scratch_gr_reg PARAMS ((void));
172 static void mark_reg_gr_used_mask PARAMS ((rtx, void *));
173 static void ia64_compute_frame_size PARAMS ((HOST_WIDE_INT));
174 static void setup_spill_pointers PARAMS ((int, rtx, HOST_WIDE_INT));
175 static void finish_spill_pointers PARAMS ((void));
176 static rtx spill_restore_mem PARAMS ((rtx, HOST_WIDE_INT));
177 static void do_spill PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx));
178 static void do_restore PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT));
179 static rtx gen_movdi_x PARAMS ((rtx, rtx, rtx));
180 static rtx gen_fr_spill_x PARAMS ((rtx, rtx, rtx));
181 static rtx gen_fr_restore_x PARAMS ((rtx, rtx, rtx));
183 static enum machine_mode hfa_element_mode PARAMS ((tree, int));
184 static bool ia64_function_ok_for_sibcall PARAMS ((tree, tree));
185 static bool ia64_rtx_costs PARAMS ((rtx, int, int, int *));
186 static void fix_range PARAMS ((const char *));
187 static struct machine_function * ia64_init_machine_status PARAMS ((void));
188 static void emit_insn_group_barriers PARAMS ((FILE *, rtx));
189 static void emit_all_insn_group_barriers PARAMS ((FILE *, rtx));
190 static void final_emit_insn_group_barriers PARAMS ((FILE *));
191 static void emit_predicate_relation_info PARAMS ((void));
192 static bool ia64_in_small_data_p PARAMS ((tree));
193 static void process_epilogue PARAMS ((void));
194 static int process_set PARAMS ((FILE *, rtx));
196 static rtx ia64_expand_fetch_and_op PARAMS ((optab, enum machine_mode,
198 static rtx ia64_expand_op_and_fetch PARAMS ((optab, enum machine_mode,
200 static rtx ia64_expand_compare_and_swap PARAMS ((enum machine_mode, int,
202 static rtx ia64_expand_lock_test_and_set PARAMS ((enum machine_mode,
204 static rtx ia64_expand_lock_release PARAMS ((enum machine_mode, tree, rtx));
205 static bool ia64_assemble_integer PARAMS ((rtx, unsigned int, int));
206 static void ia64_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
207 static void ia64_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
208 static void ia64_output_function_end_prologue PARAMS ((FILE *));
210 static int ia64_issue_rate PARAMS ((void));
211 static int ia64_adjust_cost PARAMS ((rtx, rtx, rtx, int));
212 static void ia64_sched_init PARAMS ((FILE *, int, int));
213 static void ia64_sched_finish PARAMS ((FILE *, int));
214 static int ia64_dfa_sched_reorder PARAMS ((FILE *, int, rtx *, int *,
216 static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
217 static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
218 static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
220 static struct bundle_state *get_free_bundle_state PARAMS ((void));
221 static void free_bundle_state PARAMS ((struct bundle_state *));
222 static void initiate_bundle_states PARAMS ((void));
223 static void finish_bundle_states PARAMS ((void));
224 static unsigned bundle_state_hash PARAMS ((const void *));
225 static int bundle_state_eq_p PARAMS ((const void *, const void *));
226 static int insert_bundle_state PARAMS ((struct bundle_state *));
227 static void initiate_bundle_state_table PARAMS ((void));
228 static void finish_bundle_state_table PARAMS ((void));
229 static int try_issue_nops PARAMS ((struct bundle_state *, int));
230 static int try_issue_insn PARAMS ((struct bundle_state *, rtx));
231 static void issue_nops_and_insn PARAMS ((struct bundle_state *, int,
233 static int get_max_pos PARAMS ((state_t));
234 static int get_template PARAMS ((state_t, int));
236 static rtx get_next_important_insn PARAMS ((rtx, rtx));
237 static void bundling PARAMS ((FILE *, int, rtx, rtx));
239 static void ia64_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
240 HOST_WIDE_INT, tree));
242 static void ia64_select_rtx_section PARAMS ((enum machine_mode, rtx,
243 unsigned HOST_WIDE_INT));
244 static void ia64_rwreloc_select_section PARAMS ((tree, int,
245 unsigned HOST_WIDE_INT))
247 static void ia64_rwreloc_unique_section PARAMS ((tree, int))
249 static void ia64_rwreloc_select_rtx_section PARAMS ((enum machine_mode, rtx,
250 unsigned HOST_WIDE_INT))
252 static unsigned int ia64_rwreloc_section_type_flags
253 PARAMS ((tree, const char *, int))
256 static void ia64_hpux_add_extern_decl PARAMS ((const char *name))
259 /* Table of valid machine attributes. */
260 static const struct attribute_spec ia64_attribute_table[] =
262 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
263 { "syscall_linkage", 0, 0, false, true, true, NULL },
264 { NULL, 0, 0, false, false, false, NULL }
267 /* Initialize the GCC target structure. */
268 #undef TARGET_ATTRIBUTE_TABLE
269 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
271 #undef TARGET_INIT_BUILTINS
272 #define TARGET_INIT_BUILTINS ia64_init_builtins
274 #undef TARGET_EXPAND_BUILTIN
275 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
277 #undef TARGET_ASM_BYTE_OP
278 #define TARGET_ASM_BYTE_OP "\tdata1\t"
279 #undef TARGET_ASM_ALIGNED_HI_OP
280 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
281 #undef TARGET_ASM_ALIGNED_SI_OP
282 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
283 #undef TARGET_ASM_ALIGNED_DI_OP
284 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
285 #undef TARGET_ASM_UNALIGNED_HI_OP
286 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
287 #undef TARGET_ASM_UNALIGNED_SI_OP
288 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
289 #undef TARGET_ASM_UNALIGNED_DI_OP
290 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
291 #undef TARGET_ASM_INTEGER
292 #define TARGET_ASM_INTEGER ia64_assemble_integer
294 #undef TARGET_ASM_FUNCTION_PROLOGUE
295 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
296 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
297 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
298 #undef TARGET_ASM_FUNCTION_EPILOGUE
299 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
301 #undef TARGET_IN_SMALL_DATA_P
302 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
304 #undef TARGET_SCHED_ADJUST_COST
305 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
306 #undef TARGET_SCHED_ISSUE_RATE
307 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
308 #undef TARGET_SCHED_VARIABLE_ISSUE
309 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
310 #undef TARGET_SCHED_INIT
311 #define TARGET_SCHED_INIT ia64_sched_init
312 #undef TARGET_SCHED_FINISH
313 #define TARGET_SCHED_FINISH ia64_sched_finish
314 #undef TARGET_SCHED_REORDER
315 #define TARGET_SCHED_REORDER ia64_sched_reorder
316 #undef TARGET_SCHED_REORDER2
317 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
319 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
320 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
322 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
323 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
325 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
326 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
328 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
329 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
330 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
331 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
333 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
334 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
335 ia64_first_cycle_multipass_dfa_lookahead_guard
337 #undef TARGET_SCHED_DFA_NEW_CYCLE
338 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
341 #undef TARGET_HAVE_TLS
342 #define TARGET_HAVE_TLS true
345 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
346 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
348 #undef TARGET_ASM_OUTPUT_MI_THUNK
349 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
350 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
351 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
353 #undef TARGET_RTX_COSTS
354 #define TARGET_RTX_COSTS ia64_rtx_costs
355 #undef TARGET_ADDRESS_COST
356 #define TARGET_ADDRESS_COST hook_int_rtx_0
358 struct gcc_target targetm = TARGET_INITIALIZER;
360 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
363 call_operand (op, mode)
365 enum machine_mode mode;
367 if (mode != GET_MODE (op) && mode != VOIDmode)
370 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
371 || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
374 /* Return 1 if OP refers to a symbol in the sdata section. */
377 sdata_symbolic_operand (op, mode)
379 enum machine_mode mode ATTRIBUTE_UNUSED;
381 switch (GET_CODE (op))
384 if (GET_CODE (XEXP (op, 0)) != PLUS
385 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
387 op = XEXP (XEXP (op, 0), 0);
391 if (CONSTANT_POOL_ADDRESS_P (op))
392 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
394 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
403 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
406 got_symbolic_operand (op, mode)
408 enum machine_mode mode ATTRIBUTE_UNUSED;
410 switch (GET_CODE (op))
414 if (GET_CODE (op) != PLUS)
416 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
419 if (GET_CODE (op) != CONST_INT)
424 /* Ok if we're not using GOT entries at all. */
425 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
428 /* "Ok" while emitting rtl, since otherwise we won't be provided
429 with the entire offset during emission, which makes it very
430 hard to split the offset into high and low parts. */
431 if (rtx_equal_function_value_matters)
434 /* Force the low 14 bits of the constant to zero so that we do not
435 use up so many GOT entries. */
436 return (INTVAL (op) & 0x3fff) == 0;
448 /* Return 1 if OP refers to a symbol. */
451 symbolic_operand (op, mode)
453 enum machine_mode mode ATTRIBUTE_UNUSED;
455 switch (GET_CODE (op))
468 /* Return tls_model if OP refers to a TLS symbol. */
471 tls_symbolic_operand (op, mode)
473 enum machine_mode mode ATTRIBUTE_UNUSED;
475 if (GET_CODE (op) != SYMBOL_REF)
477 return SYMBOL_REF_TLS_MODEL (op);
481 /* Return 1 if OP refers to a function. */
484 function_operand (op, mode)
486 enum machine_mode mode ATTRIBUTE_UNUSED;
488 if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
494 /* Return 1 if OP is setjmp or a similar function. */
496 /* ??? This is an unsatisfying solution. Should rethink. */
499 setjmp_operand (op, mode)
501 enum machine_mode mode ATTRIBUTE_UNUSED;
506 if (GET_CODE (op) != SYMBOL_REF)
511 /* The following code is borrowed from special_function_p in calls.c. */
513 /* Disregard prefix _, __ or __x. */
516 if (name[1] == '_' && name[2] == 'x')
518 else if (name[1] == '_')
528 && (! strcmp (name, "setjmp")
529 || ! strcmp (name, "setjmp_syscall")))
531 && ! strcmp (name, "sigsetjmp"))
533 && ! strcmp (name, "savectx")));
535 else if ((name[0] == 'q' && name[1] == 's'
536 && ! strcmp (name, "qsetjmp"))
537 || (name[0] == 'v' && name[1] == 'f'
538 && ! strcmp (name, "vfork")))
544 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
547 move_operand (op, mode)
549 enum machine_mode mode;
551 return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
554 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
557 gr_register_operand (op, mode)
559 enum machine_mode mode;
561 if (! register_operand (op, mode))
563 if (GET_CODE (op) == SUBREG)
564 op = SUBREG_REG (op);
565 if (GET_CODE (op) == REG)
567 unsigned int regno = REGNO (op);
568 if (regno < FIRST_PSEUDO_REGISTER)
569 return GENERAL_REGNO_P (regno);
574 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
577 fr_register_operand (op, mode)
579 enum machine_mode mode;
581 if (! register_operand (op, mode))
583 if (GET_CODE (op) == SUBREG)
584 op = SUBREG_REG (op);
585 if (GET_CODE (op) == REG)
587 unsigned int regno = REGNO (op);
588 if (regno < FIRST_PSEUDO_REGISTER)
589 return FR_REGNO_P (regno);
594 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
597 grfr_register_operand (op, mode)
599 enum machine_mode mode;
601 if (! register_operand (op, mode))
603 if (GET_CODE (op) == SUBREG)
604 op = SUBREG_REG (op);
605 if (GET_CODE (op) == REG)
607 unsigned int regno = REGNO (op);
608 if (regno < FIRST_PSEUDO_REGISTER)
609 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
614 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
617 gr_nonimmediate_operand (op, mode)
619 enum machine_mode mode;
621 if (! nonimmediate_operand (op, mode))
623 if (GET_CODE (op) == SUBREG)
624 op = SUBREG_REG (op);
625 if (GET_CODE (op) == REG)
627 unsigned int regno = REGNO (op);
628 if (regno < FIRST_PSEUDO_REGISTER)
629 return GENERAL_REGNO_P (regno);
634 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
637 fr_nonimmediate_operand (op, mode)
639 enum machine_mode mode;
641 if (! nonimmediate_operand (op, mode))
643 if (GET_CODE (op) == SUBREG)
644 op = SUBREG_REG (op);
645 if (GET_CODE (op) == REG)
647 unsigned int regno = REGNO (op);
648 if (regno < FIRST_PSEUDO_REGISTER)
649 return FR_REGNO_P (regno);
654 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
657 grfr_nonimmediate_operand (op, mode)
659 enum machine_mode mode;
661 if (! nonimmediate_operand (op, mode))
663 if (GET_CODE (op) == SUBREG)
664 op = SUBREG_REG (op);
665 if (GET_CODE (op) == REG)
667 unsigned int regno = REGNO (op);
668 if (regno < FIRST_PSEUDO_REGISTER)
669 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
674 /* Return 1 if OP is a GR register operand, or zero. */
677 gr_reg_or_0_operand (op, mode)
679 enum machine_mode mode;
681 return (op == const0_rtx || gr_register_operand (op, mode));
684 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
687 gr_reg_or_5bit_operand (op, mode)
689 enum machine_mode mode;
691 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
692 || GET_CODE (op) == CONSTANT_P_RTX
693 || gr_register_operand (op, mode));
696 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
699 gr_reg_or_6bit_operand (op, mode)
701 enum machine_mode mode;
703 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
704 || GET_CODE (op) == CONSTANT_P_RTX
705 || gr_register_operand (op, mode));
708 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
711 gr_reg_or_8bit_operand (op, mode)
713 enum machine_mode mode;
715 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
716 || GET_CODE (op) == CONSTANT_P_RTX
717 || gr_register_operand (op, mode));
720 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
723 grfr_reg_or_8bit_operand (op, mode)
725 enum machine_mode mode;
727 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
728 || GET_CODE (op) == CONSTANT_P_RTX
729 || grfr_register_operand (op, mode));
732 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
736 gr_reg_or_8bit_adjusted_operand (op, mode)
738 enum machine_mode mode;
740 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
741 || GET_CODE (op) == CONSTANT_P_RTX
742 || gr_register_operand (op, mode));
745 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
746 immediate and an 8 bit adjusted immediate operand. This is necessary
747 because when we emit a compare, we don't know what the condition will be,
748 so we need the union of the immediates accepted by GT and LT. */
751 gr_reg_or_8bit_and_adjusted_operand (op, mode)
753 enum machine_mode mode;
755 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
756 && CONST_OK_FOR_L (INTVAL (op)))
757 || GET_CODE (op) == CONSTANT_P_RTX
758 || gr_register_operand (op, mode));
761 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
764 gr_reg_or_14bit_operand (op, mode)
766 enum machine_mode mode;
768 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
769 || GET_CODE (op) == CONSTANT_P_RTX
770 || gr_register_operand (op, mode));
773 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
776 gr_reg_or_22bit_operand (op, mode)
778 enum machine_mode mode;
780 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
781 || GET_CODE (op) == CONSTANT_P_RTX
782 || gr_register_operand (op, mode));
785 /* Return 1 if OP is a 6 bit immediate operand. */
788 shift_count_operand (op, mode)
790 enum machine_mode mode ATTRIBUTE_UNUSED;
792 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
793 || GET_CODE (op) == CONSTANT_P_RTX);
796 /* Return 1 if OP is a 5 bit immediate operand. */
799 shift_32bit_count_operand (op, mode)
801 enum machine_mode mode ATTRIBUTE_UNUSED;
803 return ((GET_CODE (op) == CONST_INT
804 && (INTVAL (op) >= 0 && INTVAL (op) < 32))
805 || GET_CODE (op) == CONSTANT_P_RTX);
808 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
811 shladd_operand (op, mode)
813 enum machine_mode mode ATTRIBUTE_UNUSED;
815 return (GET_CODE (op) == CONST_INT
816 && (INTVAL (op) == 2 || INTVAL (op) == 4
817 || INTVAL (op) == 8 || INTVAL (op) == 16));
820 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
823 fetchadd_operand (op, mode)
825 enum machine_mode mode ATTRIBUTE_UNUSED;
827 return (GET_CODE (op) == CONST_INT
828 && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
829 INTVAL (op) == -4 || INTVAL (op) == -1 ||
830 INTVAL (op) == 1 || INTVAL (op) == 4 ||
831 INTVAL (op) == 8 || INTVAL (op) == 16));
834 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
837 fr_reg_or_fp01_operand (op, mode)
839 enum machine_mode mode;
841 return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
842 || fr_register_operand (op, mode));
845 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
846 POST_MODIFY with a REG as displacement. */
849 destination_operand (op, mode)
851 enum machine_mode mode;
853 if (! nonimmediate_operand (op, mode))
855 if (GET_CODE (op) == MEM
856 && GET_CODE (XEXP (op, 0)) == POST_MODIFY
857 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
862 /* Like memory_operand, but don't allow post-increments. */
865 not_postinc_memory_operand (op, mode)
867 enum machine_mode mode;
869 return (memory_operand (op, mode)
870 && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
873 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
874 signed immediate operand. */
877 normal_comparison_operator (op, mode)
879 enum machine_mode mode;
881 enum rtx_code code = GET_CODE (op);
882 return ((mode == VOIDmode || GET_MODE (op) == mode)
883 && (code == EQ || code == NE
884 || code == GT || code == LE || code == GTU || code == LEU));
887 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
888 signed immediate operand. */
891 adjusted_comparison_operator (op, mode)
893 enum machine_mode mode;
895 enum rtx_code code = GET_CODE (op);
896 return ((mode == VOIDmode || GET_MODE (op) == mode)
897 && (code == LT || code == GE || code == LTU || code == GEU));
900 /* Return 1 if this is a signed inequality operator. */
903 signed_inequality_operator (op, mode)
905 enum machine_mode mode;
907 enum rtx_code code = GET_CODE (op);
908 return ((mode == VOIDmode || GET_MODE (op) == mode)
909 && (code == GE || code == GT
910 || code == LE || code == LT));
913 /* Return 1 if this operator is valid for predication. */
916 predicate_operator (op, mode)
918 enum machine_mode mode;
920 enum rtx_code code = GET_CODE (op);
921 return ((GET_MODE (op) == mode || mode == VOIDmode)
922 && (code == EQ || code == NE));
925 /* Return 1 if this operator can be used in a conditional operation. */
928 condop_operator (op, mode)
930 enum machine_mode mode;
932 enum rtx_code code = GET_CODE (op);
933 return ((GET_MODE (op) == mode || mode == VOIDmode)
934 && (code == PLUS || code == MINUS || code == AND
935 || code == IOR || code == XOR));
938 /* Return 1 if this is the ar.lc register. */
941 ar_lc_reg_operand (op, mode)
943 enum machine_mode mode;
945 return (GET_MODE (op) == DImode
946 && (mode == DImode || mode == VOIDmode)
947 && GET_CODE (op) == REG
948 && REGNO (op) == AR_LC_REGNUM);
951 /* Return 1 if this is the ar.ccv register. */
954 ar_ccv_reg_operand (op, mode)
956 enum machine_mode mode;
958 return ((GET_MODE (op) == mode || mode == VOIDmode)
959 && GET_CODE (op) == REG
960 && REGNO (op) == AR_CCV_REGNUM);
963 /* Return 1 if this is the ar.pfs register. */
966 ar_pfs_reg_operand (op, mode)
968 enum machine_mode mode;
970 return ((GET_MODE (op) == mode || mode == VOIDmode)
971 && GET_CODE (op) == REG
972 && REGNO (op) == AR_PFS_REGNUM);
975 /* Like general_operand, but don't allow (mem (addressof)). */
978 general_tfmode_operand (op, mode)
980 enum machine_mode mode;
982 if (! general_operand (op, mode))
984 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
992 destination_tfmode_operand (op, mode)
994 enum machine_mode mode;
996 if (! destination_operand (op, mode))
998 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1006 tfreg_or_fp01_operand (op, mode)
1008 enum machine_mode mode;
1010 if (GET_CODE (op) == SUBREG)
1012 return fr_reg_or_fp01_operand (op, mode);
1015 /* Return 1 if OP is valid as a base register in a reg + offset address. */
1018 basereg_operand (op, mode)
1020 enum machine_mode mode;
1022 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
1023 checks from pa.c basereg_operand as well? Seems to be OK without them
1026 return (register_operand (op, mode) &&
1027 REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
1030 /* Return 1 if the operands of a move are ok. */
1033 ia64_move_ok (dst, src)
1036 /* If we're under init_recog_no_volatile, we'll not be able to use
1037 memory_operand. So check the code directly and don't worry about
1038 the validity of the underlying address, which should have been
1039 checked elsewhere anyway. */
1040 if (GET_CODE (dst) != MEM)
1042 if (GET_CODE (src) == MEM)
1044 if (register_operand (src, VOIDmode))
1047 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1048 if (INTEGRAL_MODE_P (GET_MODE (dst)))
1049 return src == const0_rtx;
1051 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
1054 /* Return 0 if we are doing C++ code. This optimization fails with
1055 C++ because of GNAT c++/6685. */
1058 addp4_optimize_ok (op1, op2)
1062 if (!strcmp (lang_hooks.name, "GNU C++"))
1065 return (basereg_operand (op1, GET_MODE(op1)) !=
1066 basereg_operand (op2, GET_MODE(op2)));
1069 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1070 Return the length of the field, or <= 0 on failure. */
1073 ia64_depz_field_mask (rop, rshift)
1076 unsigned HOST_WIDE_INT op = INTVAL (rop);
1077 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
1079 /* Get rid of the zero bits we're shifting in. */
1082 /* We must now have a solid block of 1's at bit 0. */
1083 return exact_log2 (op + 1);
1086 /* Expand a symbolic constant load. */
1089 ia64_expand_load_address (dest, src)
1092 if (tls_symbolic_operand (src, VOIDmode))
1094 if (GET_CODE (dest) != REG)
1097 if (TARGET_AUTO_PIC)
1099 emit_insn (gen_load_gprel64 (dest, src));
1102 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1104 emit_insn (gen_load_fptr (dest, src));
1107 else if (sdata_symbolic_operand (src, VOIDmode))
1109 emit_insn (gen_load_gprel (dest, src));
1113 if (GET_CODE (src) == CONST
1114 && GET_CODE (XEXP (src, 0)) == PLUS
1115 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
1116 && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
1118 rtx sym = XEXP (XEXP (src, 0), 0);
1119 HOST_WIDE_INT ofs, hi, lo;
1121 /* Split the offset into a sign extended 14-bit low part
1122 and a complementary high part. */
1123 ofs = INTVAL (XEXP (XEXP (src, 0), 1));
1124 lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
1127 emit_insn (gen_load_symptr (dest, plus_constant (sym, hi), dest));
1128 emit_insn (gen_adddi3 (dest, dest, GEN_INT (lo)));
1131 emit_insn (gen_load_symptr (dest, src, dest));
1134 static GTY(()) rtx gen_tls_tga;
1139 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1143 static GTY(()) rtx thread_pointer_rtx;
1145 gen_thread_pointer ()
1147 if (!thread_pointer_rtx)
1149 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1150 RTX_UNCHANGING_P (thread_pointer_rtx) = 1;
1152 return thread_pointer_rtx;
1156 ia64_expand_tls_address (tls_kind, op0, op1)
1157 enum tls_model tls_kind;
1160 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1164 case TLS_MODEL_GLOBAL_DYNAMIC:
1167 tga_op1 = gen_reg_rtx (Pmode);
1168 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1169 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1170 RTX_UNCHANGING_P (tga_op1) = 1;
1172 tga_op2 = gen_reg_rtx (Pmode);
1173 emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
1174 tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
1175 RTX_UNCHANGING_P (tga_op2) = 1;
1177 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1178 LCT_CONST, Pmode, 2, tga_op1,
1179 Pmode, tga_op2, Pmode);
1181 insns = get_insns ();
1184 emit_libcall_block (insns, op0, tga_ret, op1);
1187 case TLS_MODEL_LOCAL_DYNAMIC:
1188 /* ??? This isn't the completely proper way to do local-dynamic
1189 If the call to __tls_get_addr is used only by a single symbol,
1190 then we should (somehow) move the dtprel to the second arg
1191 to avoid the extra add. */
1194 tga_op1 = gen_reg_rtx (Pmode);
1195 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1196 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1197 RTX_UNCHANGING_P (tga_op1) = 1;
1199 tga_op2 = const0_rtx;
1201 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1202 LCT_CONST, Pmode, 2, tga_op1,
1203 Pmode, tga_op2, Pmode);
1205 insns = get_insns ();
1208 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1210 tmp = gen_reg_rtx (Pmode);
1211 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1213 if (register_operand (op0, Pmode))
1216 tga_ret = gen_reg_rtx (Pmode);
1219 emit_insn (gen_load_dtprel (tga_ret, op1));
1220 emit_insn (gen_adddi3 (tga_ret, tmp, tga_ret));
1223 emit_insn (gen_add_dtprel (tga_ret, tmp, op1));
1225 return (tga_ret == op0 ? NULL_RTX : tga_ret);
1227 case TLS_MODEL_INITIAL_EXEC:
1228 tmp = gen_reg_rtx (Pmode);
1229 emit_insn (gen_load_ltoff_tprel (tmp, op1));
1230 tmp = gen_rtx_MEM (Pmode, tmp);
1231 RTX_UNCHANGING_P (tmp) = 1;
1232 tmp = force_reg (Pmode, tmp);
1234 if (register_operand (op0, Pmode))
1237 op1 = gen_reg_rtx (Pmode);
1238 emit_insn (gen_adddi3 (op1, tmp, gen_thread_pointer ()));
1240 return (op1 == op0 ? NULL_RTX : op1);
1242 case TLS_MODEL_LOCAL_EXEC:
1243 if (register_operand (op0, Pmode))
1246 tmp = gen_reg_rtx (Pmode);
1249 emit_insn (gen_load_tprel (tmp, op1));
1250 emit_insn (gen_adddi3 (tmp, gen_thread_pointer (), tmp));
1253 emit_insn (gen_add_tprel (tmp, gen_thread_pointer (), op1));
1255 return (tmp == op0 ? NULL_RTX : tmp);
1263 ia64_expand_move (op0, op1)
1266 enum machine_mode mode = GET_MODE (op0);
1268 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1269 op1 = force_reg (mode, op1);
1271 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1273 enum tls_model tls_kind;
1274 if ((tls_kind = tls_symbolic_operand (op1, VOIDmode)))
1275 return ia64_expand_tls_address (tls_kind, op0, op1);
1277 if (!TARGET_NO_PIC && reload_completed)
1279 ia64_expand_load_address (op0, op1);
1287 /* Split a move from OP1 to OP0 conditional on COND. */
1290 ia64_emit_cond_move (op0, op1, cond)
1293 rtx insn, first = get_last_insn ();
1295 emit_move_insn (op0, op1);
1297 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1299 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1303 /* Split a post-reload TImode reference into two DImode components. */
1306 ia64_split_timode (out, in, scratch)
1310 switch (GET_CODE (in))
1313 out[0] = gen_rtx_REG (DImode, REGNO (in));
1314 out[1] = gen_rtx_REG (DImode, REGNO (in) + 1);
1319 rtx base = XEXP (in, 0);
1321 switch (GET_CODE (base))
1324 out[0] = adjust_address (in, DImode, 0);
1327 base = XEXP (base, 0);
1328 out[0] = adjust_address (in, DImode, 0);
1331 /* Since we're changing the mode, we need to change to POST_MODIFY
1332 as well to preserve the size of the increment. Either that or
1333 do the update in two steps, but we've already got this scratch
1334 register handy so let's use it. */
1336 base = XEXP (base, 0);
1338 = change_address (in, DImode,
1340 (Pmode, base, plus_constant (base, 16)));
1343 base = XEXP (base, 0);
1345 = change_address (in, DImode,
1347 (Pmode, base, plus_constant (base, -16)));
1353 if (scratch == NULL_RTX)
1355 out[1] = change_address (in, DImode, scratch);
1356 return gen_adddi3 (scratch, base, GEN_INT (8));
1361 split_double (in, &out[0], &out[1]);
1369 /* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
1370 through memory plus an extra GR scratch register. Except that you can
1371 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1372 SECONDARY_RELOAD_CLASS, but not both.
1374 We got into problems in the first place by allowing a construct like
1375 (subreg:TF (reg:TI)), which we got from a union containing a long double.
1376 This solution attempts to prevent this situation from occurring. When
1377 we see something like the above, we spill the inner register to memory. */
1380 spill_tfmode_operand (in, force)
1384 if (GET_CODE (in) == SUBREG
1385 && GET_MODE (SUBREG_REG (in)) == TImode
1386 && GET_CODE (SUBREG_REG (in)) == REG)
1388 rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
1389 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1391 else if (force && GET_CODE (in) == REG)
1393 rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
1394 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1396 else if (GET_CODE (in) == MEM
1397 && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
1398 return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
1403 /* Emit comparison instruction if necessary, returning the expression
1404 that holds the compare result in the proper mode. */
1407 ia64_expand_compare (code, mode)
1409 enum machine_mode mode;
1411 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1414 /* If we have a BImode input, then we already have a compare result, and
1415 do not need to emit another comparison. */
1416 if (GET_MODE (op0) == BImode)
1418 if ((code == NE || code == EQ) && op1 == const0_rtx)
1425 cmp = gen_reg_rtx (BImode);
1426 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1427 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1431 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1434 /* Emit the appropriate sequence for a call. */
1437 ia64_expand_call (retval, addr, nextarg, sibcall_p)
1440 rtx nextarg ATTRIBUTE_UNUSED;
1445 addr = XEXP (addr, 0);
1446 b0 = gen_rtx_REG (DImode, R_BR (0));
1448 /* ??? Should do this for functions known to bind local too. */
1449 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1452 insn = gen_sibcall_nogp (addr);
1454 insn = gen_call_nogp (addr, b0);
1456 insn = gen_call_value_nogp (retval, addr, b0);
1457 insn = emit_call_insn (insn);
1462 insn = gen_sibcall_gp (addr);
1464 insn = gen_call_gp (addr, b0);
1466 insn = gen_call_value_gp (retval, addr, b0);
1467 insn = emit_call_insn (insn);
1469 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1474 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1475 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
1476 gen_rtx_REG (DImode, AR_PFS_REGNUM));
1485 if (current_frame_info.reg_save_gp)
1486 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1489 HOST_WIDE_INT offset;
1491 offset = (current_frame_info.spill_cfa_off
1492 + current_frame_info.spill_size);
1493 if (frame_pointer_needed)
1495 tmp = hard_frame_pointer_rtx;
1500 tmp = stack_pointer_rtx;
1501 offset = current_frame_info.total_size - offset;
1504 if (CONST_OK_FOR_I (offset))
1505 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1506 tmp, GEN_INT (offset)));
1509 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1510 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1511 pic_offset_table_rtx, tmp));
1514 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1517 emit_move_insn (pic_offset_table_rtx, tmp);
1521 ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
1522 noreturn_p, sibcall_p)
1523 rtx retval, addr, retaddr, scratch_r, scratch_b;
1524 int noreturn_p, sibcall_p;
1527 bool is_desc = false;
1529 /* If we find we're calling through a register, then we're actually
1530 calling through a descriptor, so load up the values. */
1536 /* ??? We are currently constrained to *not* use peep2, because
1537 we can legitimiately change the global lifetime of the GP
1538 (in the form of killing where previously live). This is
1539 because a call through a descriptor doesn't use the previous
1540 value of the GP, while a direct call does, and we do not
1541 commit to either form until the split here.
1543 That said, this means that we lack precise life info for
1544 whether ADDR is dead after this call. This is not terribly
1545 important, since we can fix things up essentially for free
1546 with the POST_DEC below, but it's nice to not use it when we
1547 can immediately tell it's not necessary. */
1548 addr_dead_p = ((noreturn_p || sibcall_p
1549 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1551 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1553 /* Load the code address into scratch_b. */
1554 tmp = gen_rtx_POST_INC (Pmode, addr);
1555 tmp = gen_rtx_MEM (Pmode, tmp);
1556 emit_move_insn (scratch_r, tmp);
1557 emit_move_insn (scratch_b, scratch_r);
1559 /* Load the GP address. If ADDR is not dead here, then we must
1560 revert the change made above via the POST_INCREMENT. */
1562 tmp = gen_rtx_POST_DEC (Pmode, addr);
1565 tmp = gen_rtx_MEM (Pmode, tmp);
1566 emit_move_insn (pic_offset_table_rtx, tmp);
1573 insn = gen_sibcall_nogp (addr);
1575 insn = gen_call_value_nogp (retval, addr, retaddr);
1577 insn = gen_call_nogp (addr, retaddr);
1578 emit_call_insn (insn);
1580 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1584 /* Begin the assembly file. */
1587 emit_safe_across_calls (f)
1590 unsigned int rs, re;
1597 while (rs < 64 && call_used_regs[PR_REG (rs)])
1601 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1605 fputs ("\t.pred.safe_across_calls ", f);
1611 fprintf (f, "p%u", rs);
1613 fprintf (f, "p%u-p%u", rs, re - 1);
1620 /* Helper function for ia64_compute_frame_size: find an appropriate general
1621 register to spill some special register to. SPECIAL_SPILL_MASK contains
1622 bits in GR0 to GR31 that have already been allocated by this routine.
1623 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1626 find_gr_spill (try_locals)
1631 /* If this is a leaf function, first try an otherwise unused
1632 call-clobbered register. */
1633 if (current_function_is_leaf)
1635 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1636 if (! regs_ever_live[regno]
1637 && call_used_regs[regno]
1638 && ! fixed_regs[regno]
1639 && ! global_regs[regno]
1640 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1642 current_frame_info.gr_used_mask |= 1 << regno;
1649 regno = current_frame_info.n_local_regs;
1650 /* If there is a frame pointer, then we can't use loc79, because
1651 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1652 reg_name switching code in ia64_expand_prologue. */
1653 if (regno < (80 - frame_pointer_needed))
1655 current_frame_info.n_local_regs = regno + 1;
1656 return LOC_REG (0) + regno;
1660 /* Failed to find a general register to spill to. Must use stack. */
1664 /* In order to make for nice schedules, we try to allocate every temporary
1665 to a different register. We must of course stay away from call-saved,
1666 fixed, and global registers. We must also stay away from registers
1667 allocated in current_frame_info.gr_used_mask, since those include regs
1668 used all through the prologue.
1670 Any register allocated here must be used immediately. The idea is to
1671 aid scheduling, not to solve data flow problems. */
1673 static int last_scratch_gr_reg;
1676 next_scratch_gr_reg ()
1680 for (i = 0; i < 32; ++i)
1682 regno = (last_scratch_gr_reg + i + 1) & 31;
1683 if (call_used_regs[regno]
1684 && ! fixed_regs[regno]
1685 && ! global_regs[regno]
1686 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1688 last_scratch_gr_reg = regno;
1693 /* There must be _something_ available. */
1697 /* Helper function for ia64_compute_frame_size, called through
1698 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1701 mark_reg_gr_used_mask (reg, data)
1703 void *data ATTRIBUTE_UNUSED;
1705 unsigned int regno = REGNO (reg);
1708 unsigned int i, n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
1709 for (i = 0; i < n; ++i)
1710 current_frame_info.gr_used_mask |= 1 << (regno + i);
1714 /* Returns the number of bytes offset between the frame pointer and the stack
1715 pointer for the current function. SIZE is the number of bytes of space
1716 needed for local variables. */
1719 ia64_compute_frame_size (size)
1722 HOST_WIDE_INT total_size;
1723 HOST_WIDE_INT spill_size = 0;
1724 HOST_WIDE_INT extra_spill_size = 0;
1725 HOST_WIDE_INT pretend_args_size;
1728 int spilled_gr_p = 0;
1729 int spilled_fr_p = 0;
1733 if (current_frame_info.initialized)
1736 memset (¤t_frame_info, 0, sizeof current_frame_info);
1737 CLEAR_HARD_REG_SET (mask);
1739 /* Don't allocate scratches to the return register. */
1740 diddle_return_value (mark_reg_gr_used_mask, NULL);
1742 /* Don't allocate scratches to the EH scratch registers. */
1743 if (cfun->machine->ia64_eh_epilogue_sp)
1744 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
1745 if (cfun->machine->ia64_eh_epilogue_bsp)
1746 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
1748 /* Find the size of the register stack frame. We have only 80 local
1749 registers, because we reserve 8 for the inputs and 8 for the
1752 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1753 since we'll be adjusting that down later. */
1754 regno = LOC_REG (78) + ! frame_pointer_needed;
1755 for (; regno >= LOC_REG (0); regno--)
1756 if (regs_ever_live[regno])
1758 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
1760 /* For functions marked with the syscall_linkage attribute, we must mark
1761 all eight input registers as in use, so that locals aren't visible to
1764 if (cfun->machine->n_varargs > 0
1765 || lookup_attribute ("syscall_linkage",
1766 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
1767 current_frame_info.n_input_regs = 8;
1770 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
1771 if (regs_ever_live[regno])
1773 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
1776 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
1777 if (regs_ever_live[regno])
1779 i = regno - OUT_REG (0) + 1;
1781 /* When -p profiling, we need one output register for the mcount argument.
1782 Likewise for -a profiling for the bb_init_func argument. For -ax
1783 profiling, we need two output registers for the two bb_init_trace_func
1785 if (current_function_profile)
1787 current_frame_info.n_output_regs = i;
1789 /* ??? No rotating register support yet. */
1790 current_frame_info.n_rotate_regs = 0;
1792 /* Discover which registers need spilling, and how much room that
1793 will take. Begin with floating point and general registers,
1794 which will always wind up on the stack. */
1796 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
1797 if (regs_ever_live[regno] && ! call_used_regs[regno])
1799 SET_HARD_REG_BIT (mask, regno);
1805 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1806 if (regs_ever_live[regno] && ! call_used_regs[regno])
1808 SET_HARD_REG_BIT (mask, regno);
1814 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
1815 if (regs_ever_live[regno] && ! call_used_regs[regno])
1817 SET_HARD_REG_BIT (mask, regno);
1822 /* Now come all special registers that might get saved in other
1823 general registers. */
1825 if (frame_pointer_needed)
1827 current_frame_info.reg_fp = find_gr_spill (1);
1828 /* If we did not get a register, then we take LOC79. This is guaranteed
1829 to be free, even if regs_ever_live is already set, because this is
1830 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1831 as we don't count loc79 above. */
1832 if (current_frame_info.reg_fp == 0)
1834 current_frame_info.reg_fp = LOC_REG (79);
1835 current_frame_info.n_local_regs++;
1839 if (! current_function_is_leaf)
1841 /* Emit a save of BR0 if we call other functions. Do this even
1842 if this function doesn't return, as EH depends on this to be
1843 able to unwind the stack. */
1844 SET_HARD_REG_BIT (mask, BR_REG (0));
1846 current_frame_info.reg_save_b0 = find_gr_spill (1);
1847 if (current_frame_info.reg_save_b0 == 0)
1853 /* Similarly for ar.pfs. */
1854 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1855 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1856 if (current_frame_info.reg_save_ar_pfs == 0)
1858 extra_spill_size += 8;
1862 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1863 registers are clobbered, so we fall back to the stack. */
1864 current_frame_info.reg_save_gp
1865 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
1866 if (current_frame_info.reg_save_gp == 0)
1868 SET_HARD_REG_BIT (mask, GR_REG (1));
1875 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
1877 SET_HARD_REG_BIT (mask, BR_REG (0));
1883 /* Unwind descriptor hackery: things are most efficient if we allocate
1884 consecutive GR save registers for RP, PFS, FP in that order. However,
1885 it is absolutely critical that FP get the only hard register that's
1886 guaranteed to be free, so we allocated it first. If all three did
1887 happen to be allocated hard regs, and are consecutive, rearrange them
1888 into the preferred order now. */
1889 if (current_frame_info.reg_fp != 0
1890 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
1891 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
1893 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
1894 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
1895 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
1898 /* See if we need to store the predicate register block. */
1899 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1900 if (regs_ever_live[regno] && ! call_used_regs[regno])
1902 if (regno <= PR_REG (63))
1904 SET_HARD_REG_BIT (mask, PR_REG (0));
1905 current_frame_info.reg_save_pr = find_gr_spill (1);
1906 if (current_frame_info.reg_save_pr == 0)
1908 extra_spill_size += 8;
1912 /* ??? Mark them all as used so that register renaming and such
1913 are free to use them. */
1914 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1915 regs_ever_live[regno] = 1;
1918 /* If we're forced to use st8.spill, we're forced to save and restore
1920 if (spilled_gr_p || cfun->machine->n_varargs)
1922 regs_ever_live[AR_UNAT_REGNUM] = 1;
1923 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
1924 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
1925 if (current_frame_info.reg_save_ar_unat == 0)
1927 extra_spill_size += 8;
1932 if (regs_ever_live[AR_LC_REGNUM])
1934 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
1935 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
1936 if (current_frame_info.reg_save_ar_lc == 0)
1938 extra_spill_size += 8;
1943 /* If we have an odd number of words of pretend arguments written to
1944 the stack, then the FR save area will be unaligned. We round the
1945 size of this area up to keep things 16 byte aligned. */
1947 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
1949 pretend_args_size = current_function_pretend_args_size;
1951 total_size = (spill_size + extra_spill_size + size + pretend_args_size
1952 + current_function_outgoing_args_size);
1953 total_size = IA64_STACK_ALIGN (total_size);
1955 /* We always use the 16-byte scratch area provided by the caller, but
1956 if we are a leaf function, there's no one to which we need to provide
1958 if (current_function_is_leaf)
1959 total_size = MAX (0, total_size - 16);
1961 current_frame_info.total_size = total_size;
1962 current_frame_info.spill_cfa_off = pretend_args_size - 16;
1963 current_frame_info.spill_size = spill_size;
1964 current_frame_info.extra_spill_size = extra_spill_size;
1965 COPY_HARD_REG_SET (current_frame_info.mask, mask);
1966 current_frame_info.n_spilled = n_spilled;
1967 current_frame_info.initialized = reload_completed;
1970 /* Compute the initial difference between the specified pair of registers. */
1973 ia64_initial_elimination_offset (from, to)
1976 HOST_WIDE_INT offset;
1978 ia64_compute_frame_size (get_frame_size ());
1981 case FRAME_POINTER_REGNUM:
1982 if (to == HARD_FRAME_POINTER_REGNUM)
1984 if (current_function_is_leaf)
1985 offset = -current_frame_info.total_size;
1987 offset = -(current_frame_info.total_size
1988 - current_function_outgoing_args_size - 16);
1990 else if (to == STACK_POINTER_REGNUM)
1992 if (current_function_is_leaf)
1995 offset = 16 + current_function_outgoing_args_size;
2001 case ARG_POINTER_REGNUM:
2002 /* Arguments start above the 16 byte save area, unless stdarg
2003 in which case we store through the 16 byte save area. */
2004 if (to == HARD_FRAME_POINTER_REGNUM)
2005 offset = 16 - current_function_pretend_args_size;
2006 else if (to == STACK_POINTER_REGNUM)
2007 offset = (current_frame_info.total_size
2008 + 16 - current_function_pretend_args_size);
2013 case RETURN_ADDRESS_POINTER_REGNUM:
2024 /* If there are more than a trivial number of register spills, we use
2025 two interleaved iterators so that we can get two memory references
2028 In order to simplify things in the prologue and epilogue expanders,
2029 we use helper functions to fix up the memory references after the
2030 fact with the appropriate offsets to a POST_MODIFY memory mode.
2031 The following data structure tracks the state of the two iterators
2032 while insns are being emitted. */
2034 struct spill_fill_data
2036 rtx init_after; /* point at which to emit initializations */
2037 rtx init_reg[2]; /* initial base register */
2038 rtx iter_reg[2]; /* the iterator registers */
2039 rtx *prev_addr[2]; /* address of last memory use */
2040 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2041 HOST_WIDE_INT prev_off[2]; /* last offset */
2042 int n_iter; /* number of iterators in use */
2043 int next_iter; /* next iterator to use */
2044 unsigned int save_gr_used_mask;
2047 static struct spill_fill_data spill_fill_data;
2050 setup_spill_pointers (n_spills, init_reg, cfa_off)
2053 HOST_WIDE_INT cfa_off;
2057 spill_fill_data.init_after = get_last_insn ();
2058 spill_fill_data.init_reg[0] = init_reg;
2059 spill_fill_data.init_reg[1] = init_reg;
2060 spill_fill_data.prev_addr[0] = NULL;
2061 spill_fill_data.prev_addr[1] = NULL;
2062 spill_fill_data.prev_insn[0] = NULL;
2063 spill_fill_data.prev_insn[1] = NULL;
2064 spill_fill_data.prev_off[0] = cfa_off;
2065 spill_fill_data.prev_off[1] = cfa_off;
2066 spill_fill_data.next_iter = 0;
2067 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2069 spill_fill_data.n_iter = 1 + (n_spills > 2);
2070 for (i = 0; i < spill_fill_data.n_iter; ++i)
2072 int regno = next_scratch_gr_reg ();
2073 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2074 current_frame_info.gr_used_mask |= 1 << regno;
2079 finish_spill_pointers ()
2081 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2085 spill_restore_mem (reg, cfa_off)
2087 HOST_WIDE_INT cfa_off;
2089 int iter = spill_fill_data.next_iter;
2090 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2091 rtx disp_rtx = GEN_INT (disp);
2094 if (spill_fill_data.prev_addr[iter])
2096 if (CONST_OK_FOR_N (disp))
2098 *spill_fill_data.prev_addr[iter]
2099 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2100 gen_rtx_PLUS (DImode,
2101 spill_fill_data.iter_reg[iter],
2103 REG_NOTES (spill_fill_data.prev_insn[iter])
2104 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2105 REG_NOTES (spill_fill_data.prev_insn[iter]));
2109 /* ??? Could use register post_modify for loads. */
2110 if (! CONST_OK_FOR_I (disp))
2112 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2113 emit_move_insn (tmp, disp_rtx);
2116 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2117 spill_fill_data.iter_reg[iter], disp_rtx));
2120 /* Micro-optimization: if we've created a frame pointer, it's at
2121 CFA 0, which may allow the real iterator to be initialized lower,
2122 slightly increasing parallelism. Also, if there are few saves
2123 it may eliminate the iterator entirely. */
2125 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2126 && frame_pointer_needed)
2128 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2129 set_mem_alias_set (mem, get_varargs_alias_set ());
2137 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2138 spill_fill_data.init_reg[iter]);
2143 if (! CONST_OK_FOR_I (disp))
2145 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2146 emit_move_insn (tmp, disp_rtx);
2150 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2151 spill_fill_data.init_reg[iter],
2158 /* Careful for being the first insn in a sequence. */
2159 if (spill_fill_data.init_after)
2160 insn = emit_insn_after (seq, spill_fill_data.init_after);
2163 rtx first = get_insns ();
2165 insn = emit_insn_before (seq, first);
2167 insn = emit_insn (seq);
2169 spill_fill_data.init_after = insn;
2171 /* If DISP is 0, we may or may not have a further adjustment
2172 afterward. If we do, then the load/store insn may be modified
2173 to be a post-modify. If we don't, then this copy may be
2174 eliminated by copyprop_hardreg_forward, which makes this
2175 insn garbage, which runs afoul of the sanity check in
2176 propagate_one_insn. So mark this insn as legal to delete. */
2178 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2182 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2184 /* ??? Not all of the spills are for varargs, but some of them are.
2185 The rest of the spills belong in an alias set of their own. But
2186 it doesn't actually hurt to include them here. */
2187 set_mem_alias_set (mem, get_varargs_alias_set ());
2189 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2190 spill_fill_data.prev_off[iter] = cfa_off;
2192 if (++iter >= spill_fill_data.n_iter)
2194 spill_fill_data.next_iter = iter;
2200 do_spill (move_fn, reg, cfa_off, frame_reg)
2201 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2203 HOST_WIDE_INT cfa_off;
2205 int iter = spill_fill_data.next_iter;
2208 mem = spill_restore_mem (reg, cfa_off);
2209 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2210 spill_fill_data.prev_insn[iter] = insn;
2217 RTX_FRAME_RELATED_P (insn) = 1;
2219 /* Don't even pretend that the unwind code can intuit its way
2220 through a pair of interleaved post_modify iterators. Just
2221 provide the correct answer. */
2223 if (frame_pointer_needed)
2225 base = hard_frame_pointer_rtx;
2230 base = stack_pointer_rtx;
2231 off = current_frame_info.total_size - cfa_off;
2235 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2236 gen_rtx_SET (VOIDmode,
2237 gen_rtx_MEM (GET_MODE (reg),
2238 plus_constant (base, off)),
2245 do_restore (move_fn, reg, cfa_off)
2246 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2248 HOST_WIDE_INT cfa_off;
2250 int iter = spill_fill_data.next_iter;
2253 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2254 GEN_INT (cfa_off)));
2255 spill_fill_data.prev_insn[iter] = insn;
2258 /* Wrapper functions that discards the CONST_INT spill offset. These
2259 exist so that we can give gr_spill/gr_fill the offset they need and
2260 use a consistent function interface. */
2263 gen_movdi_x (dest, src, offset)
2265 rtx offset ATTRIBUTE_UNUSED;
2267 return gen_movdi (dest, src);
2271 gen_fr_spill_x (dest, src, offset)
2273 rtx offset ATTRIBUTE_UNUSED;
2275 return gen_fr_spill (dest, src);
2279 gen_fr_restore_x (dest, src, offset)
2281 rtx offset ATTRIBUTE_UNUSED;
2283 return gen_fr_restore (dest, src);
2286 /* Called after register allocation to add any instructions needed for the
2287 prologue. Using a prologue insn is favored compared to putting all of the
2288 instructions in output_function_prologue(), since it allows the scheduler
2289 to intermix instructions with the saves of the caller saved registers. In
2290 some cases, it might be necessary to emit a barrier instruction as the last
2291 insn to prevent such scheduling.
2293 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2294 so that the debug info generation code can handle them properly.
2296 The register save area is layed out like so:
2298 [ varargs spill area ]
2299 [ fr register spill area ]
2300 [ br register spill area ]
2301 [ ar register spill area ]
2302 [ pr register spill area ]
2303 [ gr register spill area ] */
2305 /* ??? Get inefficient code when the frame size is larger than can fit in an
2306 adds instruction. */
2309 ia64_expand_prologue ()
2311 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2312 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2315 ia64_compute_frame_size (get_frame_size ());
2316 last_scratch_gr_reg = 15;
2318 /* If there is no epilogue, then we don't need some prologue insns.
2319 We need to avoid emitting the dead prologue insns, because flow
2320 will complain about them. */
2325 for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
2326 if ((e->flags & EDGE_FAKE) == 0
2327 && (e->flags & EDGE_FALLTHRU) != 0)
2329 epilogue_p = (e != NULL);
2334 /* Set the local, input, and output register names. We need to do this
2335 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2336 half. If we use in/loc/out register names, then we get assembler errors
2337 in crtn.S because there is no alloc insn or regstk directive in there. */
2338 if (! TARGET_REG_NAMES)
2340 int inputs = current_frame_info.n_input_regs;
2341 int locals = current_frame_info.n_local_regs;
2342 int outputs = current_frame_info.n_output_regs;
2344 for (i = 0; i < inputs; i++)
2345 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2346 for (i = 0; i < locals; i++)
2347 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2348 for (i = 0; i < outputs; i++)
2349 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2352 /* Set the frame pointer register name. The regnum is logically loc79,
2353 but of course we'll not have allocated that many locals. Rather than
2354 worrying about renumbering the existing rtxs, we adjust the name. */
2355 /* ??? This code means that we can never use one local register when
2356 there is a frame pointer. loc79 gets wasted in this case, as it is
2357 renamed to a register that will never be used. See also the try_locals
2358 code in find_gr_spill. */
2359 if (current_frame_info.reg_fp)
2361 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2362 reg_names[HARD_FRAME_POINTER_REGNUM]
2363 = reg_names[current_frame_info.reg_fp];
2364 reg_names[current_frame_info.reg_fp] = tmp;
2367 /* Fix up the return address placeholder. */
2368 /* ??? We can fail if __builtin_return_address is used, and we didn't
2369 allocate a register in which to save b0. I can't think of a way to
2370 eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
2371 then be sure that I got the right one. Further, reload doesn't seem
2372 to care if an eliminable register isn't used, and "eliminates" it
2374 if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
2375 && current_frame_info.reg_save_b0 != 0)
2376 XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
2378 /* We don't need an alloc instruction if we've used no outputs or locals. */
2379 if (current_frame_info.n_local_regs == 0
2380 && current_frame_info.n_output_regs == 0
2381 && current_frame_info.n_input_regs <= current_function_args_info.int_regs)
2383 /* If there is no alloc, but there are input registers used, then we
2384 need a .regstk directive. */
2385 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2386 ar_pfs_save_reg = NULL_RTX;
2390 current_frame_info.need_regstk = 0;
2392 if (current_frame_info.reg_save_ar_pfs)
2393 regno = current_frame_info.reg_save_ar_pfs;
2395 regno = next_scratch_gr_reg ();
2396 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2398 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2399 GEN_INT (current_frame_info.n_input_regs),
2400 GEN_INT (current_frame_info.n_local_regs),
2401 GEN_INT (current_frame_info.n_output_regs),
2402 GEN_INT (current_frame_info.n_rotate_regs)));
2403 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2406 /* Set up frame pointer, stack pointer, and spill iterators. */
2408 n_varargs = cfun->machine->n_varargs;
2409 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2410 stack_pointer_rtx, 0);
2412 if (frame_pointer_needed)
2414 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2415 RTX_FRAME_RELATED_P (insn) = 1;
2418 if (current_frame_info.total_size != 0)
2420 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2423 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2424 offset = frame_size_rtx;
2427 regno = next_scratch_gr_reg ();
2428 offset = gen_rtx_REG (DImode, regno);
2429 emit_move_insn (offset, frame_size_rtx);
2432 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2433 stack_pointer_rtx, offset));
2435 if (! frame_pointer_needed)
2437 RTX_FRAME_RELATED_P (insn) = 1;
2438 if (GET_CODE (offset) != CONST_INT)
2441 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2442 gen_rtx_SET (VOIDmode,
2444 gen_rtx_PLUS (DImode,
2451 /* ??? At this point we must generate a magic insn that appears to
2452 modify the stack pointer, the frame pointer, and all spill
2453 iterators. This would allow the most scheduling freedom. For
2454 now, just hard stop. */
2455 emit_insn (gen_blockage ());
2458 /* Must copy out ar.unat before doing any integer spills. */
2459 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2461 if (current_frame_info.reg_save_ar_unat)
2463 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2466 alt_regno = next_scratch_gr_reg ();
2467 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2468 current_frame_info.gr_used_mask |= 1 << alt_regno;
2471 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2472 insn = emit_move_insn (ar_unat_save_reg, reg);
2473 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2475 /* Even if we're not going to generate an epilogue, we still
2476 need to save the register so that EH works. */
2477 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2478 emit_insn (gen_prologue_use (ar_unat_save_reg));
2481 ar_unat_save_reg = NULL_RTX;
2483 /* Spill all varargs registers. Do this before spilling any GR registers,
2484 since we want the UNAT bits for the GR registers to override the UNAT
2485 bits from varargs, which we don't care about. */
2488 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2490 reg = gen_rtx_REG (DImode, regno);
2491 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2494 /* Locate the bottom of the register save area. */
2495 cfa_off = (current_frame_info.spill_cfa_off
2496 + current_frame_info.spill_size
2497 + current_frame_info.extra_spill_size);
2499 /* Save the predicate register block either in a register or in memory. */
2500 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2502 reg = gen_rtx_REG (DImode, PR_REG (0));
2503 if (current_frame_info.reg_save_pr != 0)
2505 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2506 insn = emit_move_insn (alt_reg, reg);
2508 /* ??? Denote pr spill/fill by a DImode move that modifies all
2509 64 hard registers. */
2510 RTX_FRAME_RELATED_P (insn) = 1;
2512 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2513 gen_rtx_SET (VOIDmode, alt_reg, reg),
2516 /* Even if we're not going to generate an epilogue, we still
2517 need to save the register so that EH works. */
2519 emit_insn (gen_prologue_use (alt_reg));
2523 alt_regno = next_scratch_gr_reg ();
2524 alt_reg = gen_rtx_REG (DImode, alt_regno);
2525 insn = emit_move_insn (alt_reg, reg);
2526 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2531 /* Handle AR regs in numerical order. All of them get special handling. */
2532 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2533 && current_frame_info.reg_save_ar_unat == 0)
2535 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2536 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2540 /* The alloc insn already copied ar.pfs into a general register. The
2541 only thing we have to do now is copy that register to a stack slot
2542 if we'd not allocated a local register for the job. */
2543 if (current_frame_info.reg_save_ar_pfs == 0
2544 && ! current_function_is_leaf)
2546 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2547 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2551 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2553 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2554 if (current_frame_info.reg_save_ar_lc != 0)
2556 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2557 insn = emit_move_insn (alt_reg, reg);
2558 RTX_FRAME_RELATED_P (insn) = 1;
2560 /* Even if we're not going to generate an epilogue, we still
2561 need to save the register so that EH works. */
2563 emit_insn (gen_prologue_use (alt_reg));
2567 alt_regno = next_scratch_gr_reg ();
2568 alt_reg = gen_rtx_REG (DImode, alt_regno);
2569 emit_move_insn (alt_reg, reg);
2570 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2575 if (current_frame_info.reg_save_gp)
2577 insn = emit_move_insn (gen_rtx_REG (DImode,
2578 current_frame_info.reg_save_gp),
2579 pic_offset_table_rtx);
2580 /* We don't know for sure yet if this is actually needed, since
2581 we've not split the PIC call patterns. If all of the calls
2582 are indirect, and not followed by any uses of the gp, then
2583 this save is dead. Allow it to go away. */
2585 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2588 /* We should now be at the base of the gr/br/fr spill area. */
2589 if (cfa_off != (current_frame_info.spill_cfa_off
2590 + current_frame_info.spill_size))
2593 /* Spill all general registers. */
2594 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2595 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2597 reg = gen_rtx_REG (DImode, regno);
2598 do_spill (gen_gr_spill, reg, cfa_off, reg);
2602 /* Handle BR0 specially -- it may be getting stored permanently in
2603 some GR register. */
2604 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2606 reg = gen_rtx_REG (DImode, BR_REG (0));
2607 if (current_frame_info.reg_save_b0 != 0)
2609 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2610 insn = emit_move_insn (alt_reg, reg);
2611 RTX_FRAME_RELATED_P (insn) = 1;
2613 /* Even if we're not going to generate an epilogue, we still
2614 need to save the register so that EH works. */
2616 emit_insn (gen_prologue_use (alt_reg));
2620 alt_regno = next_scratch_gr_reg ();
2621 alt_reg = gen_rtx_REG (DImode, alt_regno);
2622 emit_move_insn (alt_reg, reg);
2623 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2628 /* Spill the rest of the BR registers. */
2629 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2630 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2632 alt_regno = next_scratch_gr_reg ();
2633 alt_reg = gen_rtx_REG (DImode, alt_regno);
2634 reg = gen_rtx_REG (DImode, regno);
2635 emit_move_insn (alt_reg, reg);
2636 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2640 /* Align the frame and spill all FR registers. */
2641 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2642 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2646 reg = gen_rtx_REG (TFmode, regno);
2647 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2651 if (cfa_off != current_frame_info.spill_cfa_off)
2654 finish_spill_pointers ();
2657 /* Called after register allocation to add any instructions needed for the
2658 epilogue. Using an epilogue insn is favored compared to putting all of the
2659 instructions in output_function_prologue(), since it allows the scheduler
2660 to intermix instructions with the saves of the caller saved registers. In
2661 some cases, it might be necessary to emit a barrier instruction as the last
2662 insn to prevent such scheduling. */
2665 ia64_expand_epilogue (sibcall_p)
2668 rtx insn, reg, alt_reg, ar_unat_save_reg;
2669 int regno, alt_regno, cfa_off;
2671 ia64_compute_frame_size (get_frame_size ());
2673 /* If there is a frame pointer, then we use it instead of the stack
2674 pointer, so that the stack pointer does not need to be valid when
2675 the epilogue starts. See EXIT_IGNORE_STACK. */
2676 if (frame_pointer_needed)
2677 setup_spill_pointers (current_frame_info.n_spilled,
2678 hard_frame_pointer_rtx, 0);
2680 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2681 current_frame_info.total_size);
2683 if (current_frame_info.total_size != 0)
2685 /* ??? At this point we must generate a magic insn that appears to
2686 modify the spill iterators and the frame pointer. This would
2687 allow the most scheduling freedom. For now, just hard stop. */
2688 emit_insn (gen_blockage ());
2691 /* Locate the bottom of the register save area. */
2692 cfa_off = (current_frame_info.spill_cfa_off
2693 + current_frame_info.spill_size
2694 + current_frame_info.extra_spill_size);
2696 /* Restore the predicate registers. */
2697 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2699 if (current_frame_info.reg_save_pr != 0)
2700 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2703 alt_regno = next_scratch_gr_reg ();
2704 alt_reg = gen_rtx_REG (DImode, alt_regno);
2705 do_restore (gen_movdi_x, alt_reg, cfa_off);
2708 reg = gen_rtx_REG (DImode, PR_REG (0));
2709 emit_move_insn (reg, alt_reg);
2712 /* Restore the application registers. */
2714 /* Load the saved unat from the stack, but do not restore it until
2715 after the GRs have been restored. */
2716 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2718 if (current_frame_info.reg_save_ar_unat != 0)
2720 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2723 alt_regno = next_scratch_gr_reg ();
2724 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2725 current_frame_info.gr_used_mask |= 1 << alt_regno;
2726 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
2731 ar_unat_save_reg = NULL_RTX;
2733 if (current_frame_info.reg_save_ar_pfs != 0)
2735 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
2736 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2737 emit_move_insn (reg, alt_reg);
2739 else if (! current_function_is_leaf)
2741 alt_regno = next_scratch_gr_reg ();
2742 alt_reg = gen_rtx_REG (DImode, alt_regno);
2743 do_restore (gen_movdi_x, alt_reg, cfa_off);
2745 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2746 emit_move_insn (reg, alt_reg);
2749 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2751 if (current_frame_info.reg_save_ar_lc != 0)
2752 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2755 alt_regno = next_scratch_gr_reg ();
2756 alt_reg = gen_rtx_REG (DImode, alt_regno);
2757 do_restore (gen_movdi_x, alt_reg, cfa_off);
2760 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2761 emit_move_insn (reg, alt_reg);
2764 /* We should now be at the base of the gr/br/fr spill area. */
2765 if (cfa_off != (current_frame_info.spill_cfa_off
2766 + current_frame_info.spill_size))
2769 /* The GP may be stored on the stack in the prologue, but it's
2770 never restored in the epilogue. Skip the stack slot. */
2771 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
2774 /* Restore all general registers. */
2775 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
2776 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2778 reg = gen_rtx_REG (DImode, regno);
2779 do_restore (gen_gr_restore, reg, cfa_off);
2783 /* Restore the branch registers. Handle B0 specially, as it may
2784 have gotten stored in some GR register. */
2785 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2787 if (current_frame_info.reg_save_b0 != 0)
2788 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2791 alt_regno = next_scratch_gr_reg ();
2792 alt_reg = gen_rtx_REG (DImode, alt_regno);
2793 do_restore (gen_movdi_x, alt_reg, cfa_off);
2796 reg = gen_rtx_REG (DImode, BR_REG (0));
2797 emit_move_insn (reg, alt_reg);
2800 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2801 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2803 alt_regno = next_scratch_gr_reg ();
2804 alt_reg = gen_rtx_REG (DImode, alt_regno);
2805 do_restore (gen_movdi_x, alt_reg, cfa_off);
2807 reg = gen_rtx_REG (DImode, regno);
2808 emit_move_insn (reg, alt_reg);
2811 /* Restore floating point registers. */
2812 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2813 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2817 reg = gen_rtx_REG (TFmode, regno);
2818 do_restore (gen_fr_restore_x, reg, cfa_off);
2822 /* Restore ar.unat for real. */
2823 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2825 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2826 emit_move_insn (reg, ar_unat_save_reg);
2829 if (cfa_off != current_frame_info.spill_cfa_off)
2832 finish_spill_pointers ();
2834 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
2836 /* ??? At this point we must generate a magic insn that appears to
2837 modify the spill iterators, the stack pointer, and the frame
2838 pointer. This would allow the most scheduling freedom. For now,
2840 emit_insn (gen_blockage ());
2843 if (cfun->machine->ia64_eh_epilogue_sp)
2844 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
2845 else if (frame_pointer_needed)
2847 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
2848 RTX_FRAME_RELATED_P (insn) = 1;
2850 else if (current_frame_info.total_size)
2852 rtx offset, frame_size_rtx;
2854 frame_size_rtx = GEN_INT (current_frame_info.total_size);
2855 if (CONST_OK_FOR_I (current_frame_info.total_size))
2856 offset = frame_size_rtx;
2859 regno = next_scratch_gr_reg ();
2860 offset = gen_rtx_REG (DImode, regno);
2861 emit_move_insn (offset, frame_size_rtx);
2864 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
2867 RTX_FRAME_RELATED_P (insn) = 1;
2868 if (GET_CODE (offset) != CONST_INT)
2871 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2872 gen_rtx_SET (VOIDmode,
2874 gen_rtx_PLUS (DImode,
2881 if (cfun->machine->ia64_eh_epilogue_bsp)
2882 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
2885 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
2888 int fp = GR_REG (2);
2889 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2890 first available call clobbered register. If there was a frame_pointer
2891 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2892 so we have to make sure we're using the string "r2" when emitting
2893 the register name for the assembler. */
2894 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
2895 fp = HARD_FRAME_POINTER_REGNUM;
2897 /* We must emit an alloc to force the input registers to become output
2898 registers. Otherwise, if the callee tries to pass its parameters
2899 through to another call without an intervening alloc, then these
2901 /* ??? We don't need to preserve all input registers. We only need to
2902 preserve those input registers used as arguments to the sibling call.
2903 It is unclear how to compute that number here. */
2904 if (current_frame_info.n_input_regs != 0)
2905 emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
2906 GEN_INT (0), GEN_INT (0),
2907 GEN_INT (current_frame_info.n_input_regs),
2912 /* Return 1 if br.ret can do all the work required to return from a
2916 ia64_direct_return ()
2918 if (reload_completed && ! frame_pointer_needed)
2920 ia64_compute_frame_size (get_frame_size ());
2922 return (current_frame_info.total_size == 0
2923 && current_frame_info.n_spilled == 0
2924 && current_frame_info.reg_save_b0 == 0
2925 && current_frame_info.reg_save_pr == 0
2926 && current_frame_info.reg_save_ar_pfs == 0
2927 && current_frame_info.reg_save_ar_unat == 0
2928 && current_frame_info.reg_save_ar_lc == 0);
2934 ia64_hard_regno_rename_ok (from, to)
2938 /* Don't clobber any of the registers we reserved for the prologue. */
2939 if (to == current_frame_info.reg_fp
2940 || to == current_frame_info.reg_save_b0
2941 || to == current_frame_info.reg_save_pr
2942 || to == current_frame_info.reg_save_ar_pfs
2943 || to == current_frame_info.reg_save_ar_unat
2944 || to == current_frame_info.reg_save_ar_lc)
2947 if (from == current_frame_info.reg_fp
2948 || from == current_frame_info.reg_save_b0
2949 || from == current_frame_info.reg_save_pr
2950 || from == current_frame_info.reg_save_ar_pfs
2951 || from == current_frame_info.reg_save_ar_unat
2952 || from == current_frame_info.reg_save_ar_lc)
2955 /* Don't use output registers outside the register frame. */
2956 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
2959 /* Retain even/oddness on predicate register pairs. */
2960 if (PR_REGNO_P (from) && PR_REGNO_P (to))
2961 return (from & 1) == (to & 1);
2966 /* Target hook for assembling integer objects. Handle word-sized
2967 aligned objects and detect the cases when @fptr is needed. */
2970 ia64_assemble_integer (x, size, aligned_p)
2975 if (size == (TARGET_ILP32 ? 4 : 8)
2977 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
2978 && GET_CODE (x) == SYMBOL_REF
2979 && SYMBOL_REF_FUNCTION_P (x))
2982 fputs ("\tdata4\t@fptr(", asm_out_file);
2984 fputs ("\tdata8\t@fptr(", asm_out_file);
2985 output_addr_const (asm_out_file, x);
2986 fputs (")\n", asm_out_file);
2989 return default_assemble_integer (x, size, aligned_p);
2992 /* Emit the function prologue. */
2995 ia64_output_function_prologue (file, size)
2997 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
2999 int mask, grsave, grsave_prev;
3001 if (current_frame_info.need_regstk)
3002 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3003 current_frame_info.n_input_regs,
3004 current_frame_info.n_local_regs,
3005 current_frame_info.n_output_regs,
3006 current_frame_info.n_rotate_regs);
3008 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3011 /* Emit the .prologue directive. */
3014 grsave = grsave_prev = 0;
3015 if (current_frame_info.reg_save_b0 != 0)
3018 grsave = grsave_prev = current_frame_info.reg_save_b0;
3020 if (current_frame_info.reg_save_ar_pfs != 0
3021 && (grsave_prev == 0
3022 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3025 if (grsave_prev == 0)
3026 grsave = current_frame_info.reg_save_ar_pfs;
3027 grsave_prev = current_frame_info.reg_save_ar_pfs;
3029 if (current_frame_info.reg_fp != 0
3030 && (grsave_prev == 0
3031 || current_frame_info.reg_fp == grsave_prev + 1))
3034 if (grsave_prev == 0)
3035 grsave = HARD_FRAME_POINTER_REGNUM;
3036 grsave_prev = current_frame_info.reg_fp;
3038 if (current_frame_info.reg_save_pr != 0
3039 && (grsave_prev == 0
3040 || current_frame_info.reg_save_pr == grsave_prev + 1))
3043 if (grsave_prev == 0)
3044 grsave = current_frame_info.reg_save_pr;
3048 fprintf (file, "\t.prologue %d, %d\n", mask,
3049 ia64_dbx_register_number (grsave));
3051 fputs ("\t.prologue\n", file);
3053 /* Emit a .spill directive, if necessary, to relocate the base of
3054 the register spill area. */
3055 if (current_frame_info.spill_cfa_off != -16)
3056 fprintf (file, "\t.spill %ld\n",
3057 (long) (current_frame_info.spill_cfa_off
3058 + current_frame_info.spill_size));
3061 /* Emit the .body directive at the scheduled end of the prologue. */
3064 ia64_output_function_end_prologue (file)
3067 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3070 fputs ("\t.body\n", file);
3073 /* Emit the function epilogue. */
3076 ia64_output_function_epilogue (file, size)
3077 FILE *file ATTRIBUTE_UNUSED;
3078 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3082 /* Reset from the function's potential modifications. */
3083 XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
3085 if (current_frame_info.reg_fp)
3087 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3088 reg_names[HARD_FRAME_POINTER_REGNUM]
3089 = reg_names[current_frame_info.reg_fp];
3090 reg_names[current_frame_info.reg_fp] = tmp;
3092 if (! TARGET_REG_NAMES)
3094 for (i = 0; i < current_frame_info.n_input_regs; i++)
3095 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3096 for (i = 0; i < current_frame_info.n_local_regs; i++)
3097 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3098 for (i = 0; i < current_frame_info.n_output_regs; i++)
3099 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3102 current_frame_info.initialized = 0;
3106 ia64_dbx_register_number (regno)
3109 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3110 from its home at loc79 to something inside the register frame. We
3111 must perform the same renumbering here for the debug info. */
3112 if (current_frame_info.reg_fp)
3114 if (regno == HARD_FRAME_POINTER_REGNUM)
3115 regno = current_frame_info.reg_fp;
3116 else if (regno == current_frame_info.reg_fp)
3117 regno = HARD_FRAME_POINTER_REGNUM;
3120 if (IN_REGNO_P (regno))
3121 return 32 + regno - IN_REG (0);
3122 else if (LOC_REGNO_P (regno))
3123 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3124 else if (OUT_REGNO_P (regno))
3125 return (32 + current_frame_info.n_input_regs
3126 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3132 ia64_initialize_trampoline (addr, fnaddr, static_chain)
3133 rtx addr, fnaddr, static_chain;
3135 rtx addr_reg, eight = GEN_INT (8);
3137 /* Load up our iterator. */
3138 addr_reg = gen_reg_rtx (Pmode);
3139 emit_move_insn (addr_reg, addr);
3141 /* The first two words are the fake descriptor:
3142 __ia64_trampoline, ADDR+16. */
3143 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3144 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3145 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3147 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3148 copy_to_reg (plus_constant (addr, 16)));
3149 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3151 /* The third word is the target descriptor. */
3152 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3153 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3155 /* The fourth word is the static chain. */
3156 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3159 /* Do any needed setup for a variadic function. CUM has not been updated
3160 for the last named argument which has type TYPE and mode MODE.
3162 We generate the actual spill instructions during prologue generation. */
3165 ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
3166 CUMULATIVE_ARGS cum;
3170 int second_time ATTRIBUTE_UNUSED;
3172 /* Skip the current argument. */
3173 ia64_function_arg_advance (&cum, int_mode, type, 1);
3175 if (cum.words < MAX_ARGUMENT_SLOTS)
3177 int n = MAX_ARGUMENT_SLOTS - cum.words;
3178 *pretend_size = n * UNITS_PER_WORD;
3179 cfun->machine->n_varargs = n;
3183 /* Check whether TYPE is a homogeneous floating point aggregate. If
3184 it is, return the mode of the floating point type that appears
3185 in all leafs. If it is not, return VOIDmode.
3187 An aggregate is a homogeneous floating point aggregate is if all
3188 fields/elements in it have the same floating point type (e.g,
3189 SFmode). 128-bit quad-precision floats are excluded. */
3191 static enum machine_mode
3192 hfa_element_mode (type, nested)
3196 enum machine_mode element_mode = VOIDmode;
3197 enum machine_mode mode;
3198 enum tree_code code = TREE_CODE (type);
3199 int know_element_mode = 0;
3204 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3205 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3206 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3207 case FILE_TYPE: case SET_TYPE: case LANG_TYPE:
3211 /* Fortran complex types are supposed to be HFAs, so we need to handle
3212 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3215 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3216 && (TYPE_MODE (type) != TCmode || INTEL_EXTENDED_IEEE_FORMAT))
3217 return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type))
3218 * BITS_PER_UNIT, MODE_FLOAT, 0);
3223 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3224 mode if this is contained within an aggregate. */
3225 if (nested && (TYPE_MODE (type) != TFmode || INTEL_EXTENDED_IEEE_FORMAT))
3226 return TYPE_MODE (type);
3231 return hfa_element_mode (TREE_TYPE (type), 1);
3235 case QUAL_UNION_TYPE:
3236 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3238 if (TREE_CODE (t) != FIELD_DECL)
3241 mode = hfa_element_mode (TREE_TYPE (t), 1);
3242 if (know_element_mode)
3244 if (mode != element_mode)
3247 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3251 know_element_mode = 1;
3252 element_mode = mode;
3255 return element_mode;
3258 /* If we reach here, we probably have some front-end specific type
3259 that the backend doesn't know about. This can happen via the
3260 aggregate_value_p call in init_function_start. All we can do is
3261 ignore unknown tree types. */
3268 /* Return rtx for register where argument is passed, or zero if it is passed
3271 /* ??? 128-bit quad-precision floats are always passed in general
3275 ia64_function_arg (cum, mode, type, named, incoming)
3276 CUMULATIVE_ARGS *cum;
3277 enum machine_mode mode;
3282 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3283 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3284 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3287 enum machine_mode hfa_mode = VOIDmode;
3289 /* Integer and float arguments larger than 8 bytes start at the next even
3290 boundary. Aggregates larger than 8 bytes start at the next even boundary
3291 if the aggregate has 16 byte alignment. Net effect is that types with
3292 alignment greater than 8 start at the next even boundary. */
3293 /* ??? The ABI does not specify how to handle aggregates with alignment from
3294 9 to 15 bytes, or greater than 16. We handle them all as if they had
3295 16 byte alignment. Such aggregates can occur only if gcc extensions are
3297 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3299 && (cum->words & 1))
3302 /* If all argument slots are used, then it must go on the stack. */
3303 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3306 /* Check for and handle homogeneous FP aggregates. */
3308 hfa_mode = hfa_element_mode (type, 0);
3310 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3311 and unprototyped hfas are passed specially. */
3312 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3316 int fp_regs = cum->fp_regs;
3317 int int_regs = cum->words + offset;
3318 int hfa_size = GET_MODE_SIZE (hfa_mode);
3322 /* If prototyped, pass it in FR regs then GR regs.
3323 If not prototyped, pass it in both FR and GR regs.
3325 If this is an SFmode aggregate, then it is possible to run out of
3326 FR regs while GR regs are still left. In that case, we pass the
3327 remaining part in the GR regs. */
3329 /* Fill the FP regs. We do this always. We stop if we reach the end
3330 of the argument, the last FP register, or the last argument slot. */
3332 byte_size = ((mode == BLKmode)
3333 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3334 args_byte_size = int_regs * UNITS_PER_WORD;
3336 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3337 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3339 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3340 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3344 args_byte_size += hfa_size;
3348 /* If no prototype, then the whole thing must go in GR regs. */
3349 if (! cum->prototype)
3351 /* If this is an SFmode aggregate, then we might have some left over
3352 that needs to go in GR regs. */
3353 else if (byte_size != offset)
3354 int_regs += offset / UNITS_PER_WORD;
3356 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3358 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3360 enum machine_mode gr_mode = DImode;
3362 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3363 then this goes in a GR reg left adjusted/little endian, right
3364 adjusted/big endian. */
3365 /* ??? Currently this is handled wrong, because 4-byte hunks are
3366 always right adjusted/little endian. */
3369 /* If we have an even 4 byte hunk because the aggregate is a
3370 multiple of 4 bytes in size, then this goes in a GR reg right
3371 adjusted/little endian. */
3372 else if (byte_size - offset == 4)
3374 /* Complex floats need to have float mode. */
3375 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3378 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3379 gen_rtx_REG (gr_mode, (basereg
3382 offset += GET_MODE_SIZE (gr_mode);
3383 int_regs += GET_MODE_SIZE (gr_mode) <= UNITS_PER_WORD
3384 ? 1 : GET_MODE_SIZE (gr_mode) / UNITS_PER_WORD;
3387 /* If we ended up using just one location, just return that one loc. */
3389 return XEXP (loc[0], 0);
3391 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3394 /* Integral and aggregates go in general registers. If we have run out of
3395 FR registers, then FP values must also go in general registers. This can
3396 happen when we have a SFmode HFA. */
3397 else if (((mode == TFmode) && ! INTEL_EXTENDED_IEEE_FORMAT)
3398 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3400 int byte_size = ((mode == BLKmode)
3401 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3402 if (BYTES_BIG_ENDIAN
3403 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3404 && byte_size < UNITS_PER_WORD
3407 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3408 gen_rtx_REG (DImode,
3409 (basereg + cum->words
3412 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3415 return gen_rtx_REG (mode, basereg + cum->words + offset);
3419 /* If there is a prototype, then FP values go in a FR register when
3420 named, and in a GR register when unnamed. */
3421 else if (cum->prototype)
3424 return gen_rtx_REG (mode, basereg + cum->words + offset);
3426 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3428 /* If there is no prototype, then FP values go in both FR and GR
3432 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3433 gen_rtx_REG (mode, (FR_ARG_FIRST
3436 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3438 (basereg + cum->words
3442 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3446 /* Return number of words, at the beginning of the argument, that must be
3447 put in registers. 0 is the argument is entirely in registers or entirely
3451 ia64_function_arg_partial_nregs (cum, mode, type, named)
3452 CUMULATIVE_ARGS *cum;
3453 enum machine_mode mode;
3455 int named ATTRIBUTE_UNUSED;
3457 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3458 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3462 /* Arguments with alignment larger than 8 bytes start at the next even
3464 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3466 && (cum->words & 1))
3469 /* If all argument slots are used, then it must go on the stack. */
3470 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3473 /* It doesn't matter whether the argument goes in FR or GR regs. If
3474 it fits within the 8 argument slots, then it goes entirely in
3475 registers. If it extends past the last argument slot, then the rest
3476 goes on the stack. */
3478 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3481 return MAX_ARGUMENT_SLOTS - cum->words - offset;
3484 /* Update CUM to point after this argument. This is patterned after
3485 ia64_function_arg. */
3488 ia64_function_arg_advance (cum, mode, type, named)
3489 CUMULATIVE_ARGS *cum;
3490 enum machine_mode mode;
3494 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3495 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3498 enum machine_mode hfa_mode = VOIDmode;
3500 /* If all arg slots are already full, then there is nothing to do. */
3501 if (cum->words >= MAX_ARGUMENT_SLOTS)
3504 /* Arguments with alignment larger than 8 bytes start at the next even
3506 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3508 && (cum->words & 1))
3511 cum->words += words + offset;
3513 /* Check for and handle homogeneous FP aggregates. */
3515 hfa_mode = hfa_element_mode (type, 0);
3517 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3518 and unprototyped hfas are passed specially. */
3519 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3521 int fp_regs = cum->fp_regs;
3522 /* This is the original value of cum->words + offset. */
3523 int int_regs = cum->words - words;
3524 int hfa_size = GET_MODE_SIZE (hfa_mode);
3528 /* If prototyped, pass it in FR regs then GR regs.
3529 If not prototyped, pass it in both FR and GR regs.
3531 If this is an SFmode aggregate, then it is possible to run out of
3532 FR regs while GR regs are still left. In that case, we pass the
3533 remaining part in the GR regs. */
3535 /* Fill the FP regs. We do this always. We stop if we reach the end
3536 of the argument, the last FP register, or the last argument slot. */
3538 byte_size = ((mode == BLKmode)
3539 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3540 args_byte_size = int_regs * UNITS_PER_WORD;
3542 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3543 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3546 args_byte_size += hfa_size;
3550 cum->fp_regs = fp_regs;
3553 /* Integral and aggregates go in general registers. If we have run out of
3554 FR registers, then FP values must also go in general registers. This can
3555 happen when we have a SFmode HFA. */
3556 else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
3557 cum->int_regs = cum->words;
3559 /* If there is a prototype, then FP values go in a FR register when
3560 named, and in a GR register when unnamed. */
3561 else if (cum->prototype)
3564 cum->int_regs = cum->words;
3566 /* ??? Complex types should not reach here. */
3567 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3569 /* If there is no prototype, then FP values go in both FR and GR
3573 /* ??? Complex types should not reach here. */
3574 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3575 cum->int_regs = cum->words;
3579 /* Variable sized types are passed by reference. */
3580 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3583 ia64_function_arg_pass_by_reference (cum, mode, type, named)
3584 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3585 enum machine_mode mode ATTRIBUTE_UNUSED;
3587 int named ATTRIBUTE_UNUSED;
3589 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3592 /* True if it is OK to do sibling call optimization for the specified
3593 call expression EXP. DECL will be the called function, or NULL if
3594 this is an indirect call. */
3596 ia64_function_ok_for_sibcall (decl, exp)
3599 /* Direct calls are always ok. */
3603 /* If TARGET_CONST_GP is in effect, then our caller expects us to
3604 return with our current GP. This means that we'll always have
3605 a GP reload after an indirect call. */
3606 return !ia64_epilogue_uses (R_GR (1));
3610 /* Implement va_arg. */
3613 ia64_va_arg (valist, type)
3618 /* Variable sized types are passed by reference. */
3619 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3621 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
3622 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
3625 /* Arguments with alignment larger than 8 bytes start at the next even
3627 if (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3629 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3630 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3631 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3632 build_int_2 (-2 * UNITS_PER_WORD, -1));
3633 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3634 TREE_SIDE_EFFECTS (t) = 1;
3635 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3638 return std_expand_builtin_va_arg (valist, type);
3641 /* Return 1 if function return value returned in memory. Return 0 if it is
3645 ia64_return_in_memory (valtype)
3648 enum machine_mode mode;
3649 enum machine_mode hfa_mode;
3650 HOST_WIDE_INT byte_size;
3652 mode = TYPE_MODE (valtype);
3653 byte_size = GET_MODE_SIZE (mode);
3654 if (mode == BLKmode)
3656 byte_size = int_size_in_bytes (valtype);
3661 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3663 hfa_mode = hfa_element_mode (valtype, 0);
3664 if (hfa_mode != VOIDmode)
3666 int hfa_size = GET_MODE_SIZE (hfa_mode);
3668 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
3673 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
3679 /* Return rtx for register that holds the function return value. */
3682 ia64_function_value (valtype, func)
3684 tree func ATTRIBUTE_UNUSED;
3686 enum machine_mode mode;
3687 enum machine_mode hfa_mode;
3689 mode = TYPE_MODE (valtype);
3690 hfa_mode = hfa_element_mode (valtype, 0);
3692 if (hfa_mode != VOIDmode)
3700 hfa_size = GET_MODE_SIZE (hfa_mode);
3701 byte_size = ((mode == BLKmode)
3702 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
3704 for (i = 0; offset < byte_size; i++)
3706 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3707 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
3713 return XEXP (loc[0], 0);
3715 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3717 else if (FLOAT_TYPE_P (valtype) &&
3718 ((mode != TFmode) || INTEL_EXTENDED_IEEE_FORMAT))
3719 return gen_rtx_REG (mode, FR_ARG_FIRST);
3722 if (BYTES_BIG_ENDIAN
3723 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
3731 bytesize = int_size_in_bytes (valtype);
3732 for (i = 0; offset < bytesize; i++)
3734 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3735 gen_rtx_REG (DImode,
3738 offset += UNITS_PER_WORD;
3740 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3743 return gen_rtx_REG (mode, GR_RET_FIRST);
3747 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3748 We need to emit DTP-relative relocations. */
3751 ia64_output_dwarf_dtprel (file, size, x)
3758 fputs ("\tdata8.ua\t@dtprel(", file);
3759 output_addr_const (file, x);
3763 /* Print a memory address as an operand to reference that memory location. */
3765 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3766 also call this from ia64_print_operand for memory addresses. */
3769 ia64_print_operand_address (stream, address)
3770 FILE * stream ATTRIBUTE_UNUSED;
3771 rtx address ATTRIBUTE_UNUSED;
3775 /* Print an operand to an assembler instruction.
3776 C Swap and print a comparison operator.
3777 D Print an FP comparison operator.
3778 E Print 32 - constant, for SImode shifts as extract.
3779 e Print 64 - constant, for DImode rotates.
3780 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3781 a floating point register emitted normally.
3782 I Invert a predicate register by adding 1.
3783 J Select the proper predicate register for a condition.
3784 j Select the inverse predicate register for a condition.
3785 O Append .acq for volatile load.
3786 P Postincrement of a MEM.
3787 Q Append .rel for volatile store.
3788 S Shift amount for shladd instruction.
3789 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3790 for Intel assembler.
3791 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3792 for Intel assembler.
3793 r Print register name, or constant 0 as r0. HP compatibility for
3796 ia64_print_operand (file, x, code)
3806 /* Handled below. */
3811 enum rtx_code c = swap_condition (GET_CODE (x));
3812 fputs (GET_RTX_NAME (c), file);
3817 switch (GET_CODE (x))
3829 str = GET_RTX_NAME (GET_CODE (x));
3836 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
3840 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
3844 if (x == CONST0_RTX (GET_MODE (x)))
3845 str = reg_names [FR_REG (0)];
3846 else if (x == CONST1_RTX (GET_MODE (x)))
3847 str = reg_names [FR_REG (1)];
3848 else if (GET_CODE (x) == REG)
3849 str = reg_names [REGNO (x)];
3856 fputs (reg_names [REGNO (x) + 1], file);
3862 unsigned int regno = REGNO (XEXP (x, 0));
3863 if (GET_CODE (x) == EQ)
3867 fputs (reg_names [regno], file);
3872 if (MEM_VOLATILE_P (x))
3873 fputs(".acq", file);
3878 HOST_WIDE_INT value;
3880 switch (GET_CODE (XEXP (x, 0)))
3886 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
3887 if (GET_CODE (x) == CONST_INT)
3889 else if (GET_CODE (x) == REG)
3891 fprintf (file, ", %s", reg_names[REGNO (x)]);
3899 value = GET_MODE_SIZE (GET_MODE (x));
3903 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
3909 fprintf (file, HOST_WIDE_INT_PRINT_DEC, value);
3914 if (MEM_VOLATILE_P (x))
3915 fputs(".rel", file);
3919 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3923 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3925 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
3931 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3933 const char *prefix = "0x";
3934 if (INTVAL (x) & 0x80000000)
3936 fprintf (file, "0xffffffff");
3939 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
3945 /* If this operand is the constant zero, write it as register zero.
3946 Any register, zero, or CONST_INT value is OK here. */
3947 if (GET_CODE (x) == REG)
3948 fputs (reg_names[REGNO (x)], file);
3949 else if (x == CONST0_RTX (GET_MODE (x)))
3951 else if (GET_CODE (x) == CONST_INT)
3952 output_addr_const (file, x);
3954 output_operand_lossage ("invalid %%r value");
3961 /* For conditional branches, returns or calls, substitute
3962 sptk, dptk, dpnt, or spnt for %s. */
3963 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
3966 int pred_val = INTVAL (XEXP (x, 0));
3968 /* Guess top and bottom 10% statically predicted. */
3969 if (pred_val < REG_BR_PROB_BASE / 50)
3971 else if (pred_val < REG_BR_PROB_BASE / 2)
3973 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
3978 else if (GET_CODE (current_output_insn) == CALL_INSN)
3983 fputs (which, file);
3988 x = current_insn_predicate;
3991 unsigned int regno = REGNO (XEXP (x, 0));
3992 if (GET_CODE (x) == EQ)
3994 fprintf (file, "(%s) ", reg_names [regno]);
3999 output_operand_lossage ("ia64_print_operand: unknown code");
4003 switch (GET_CODE (x))
4005 /* This happens for the spill/restore instructions. */
4010 /* ... fall through ... */
4013 fputs (reg_names [REGNO (x)], file);
4018 rtx addr = XEXP (x, 0);
4019 if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
4020 addr = XEXP (addr, 0);
4021 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4026 output_addr_const (file, x);
4033 /* Compute a (partial) cost for rtx X. Return true if the complete
4034 cost has been computed, and false if subexpressions should be
4035 scanned. In either case, *TOTAL contains the cost result. */
4036 /* ??? This is incomplete. */
4039 ia64_rtx_costs (x, code, outer_code, total)
4041 int code, outer_code;
4050 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4053 if (CONST_OK_FOR_I (INTVAL (x)))
4055 else if (CONST_OK_FOR_J (INTVAL (x)))
4058 *total = COSTS_N_INSNS (1);
4061 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4064 *total = COSTS_N_INSNS (1);
4069 *total = COSTS_N_INSNS (1);
4075 *total = COSTS_N_INSNS (3);
4079 /* For multiplies wider than HImode, we have to go to the FPU,
4080 which normally involves copies. Plus there's the latency
4081 of the multiply itself, and the latency of the instructions to
4082 transfer integer regs to FP regs. */
4083 /* ??? Check for FP mode. */
4084 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4085 *total = COSTS_N_INSNS (10);
4087 *total = COSTS_N_INSNS (2);
4095 *total = COSTS_N_INSNS (1);
4102 /* We make divide expensive, so that divide-by-constant will be
4103 optimized to a multiply. */
4104 *total = COSTS_N_INSNS (60);
4112 /* Calculate the cost of moving data from a register in class FROM to
4113 one in class TO, using MODE. */
4116 ia64_register_move_cost (mode, from, to)
4117 enum machine_mode mode;
4118 enum reg_class from, to;
4120 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4121 if (to == ADDL_REGS)
4123 if (from == ADDL_REGS)
4126 /* All costs are symmetric, so reduce cases by putting the
4127 lower number class as the destination. */
4130 enum reg_class tmp = to;
4131 to = from, from = tmp;
4134 /* Moving from FR<->GR in TFmode must be more expensive than 2,
4135 so that we get secondary memory reloads. Between FR_REGS,
4136 we have to make this at least as expensive as MEMORY_MOVE_COST
4137 to avoid spectacularly poor register class preferencing. */
4140 if (to != GR_REGS || from != GR_REGS)
4141 return MEMORY_MOVE_COST (mode, to, 0);
4149 /* Moving between PR registers takes two insns. */
4150 if (from == PR_REGS)
4152 /* Moving between PR and anything but GR is impossible. */
4153 if (from != GR_REGS)
4154 return MEMORY_MOVE_COST (mode, to, 0);
4158 /* Moving between BR and anything but GR is impossible. */
4159 if (from != GR_REGS && from != GR_AND_BR_REGS)
4160 return MEMORY_MOVE_COST (mode, to, 0);
4165 /* Moving between AR and anything but GR is impossible. */
4166 if (from != GR_REGS)
4167 return MEMORY_MOVE_COST (mode, to, 0);
4172 case GR_AND_FR_REGS:
4173 case GR_AND_BR_REGS:
4184 /* This function returns the register class required for a secondary
4185 register when copying between one of the registers in CLASS, and X,
4186 using MODE. A return value of NO_REGS means that no secondary register
4190 ia64_secondary_reload_class (class, mode, x)
4191 enum reg_class class;
4192 enum machine_mode mode ATTRIBUTE_UNUSED;
4197 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4198 regno = true_regnum (x);
4205 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4206 interaction. We end up with two pseudos with overlapping lifetimes
4207 both of which are equiv to the same constant, and both which need
4208 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4209 changes depending on the path length, which means the qty_first_reg
4210 check in make_regs_eqv can give different answers at different times.
4211 At some point I'll probably need a reload_indi pattern to handle
4214 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4215 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4216 non-general registers for good measure. */
4217 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4220 /* This is needed if a pseudo used as a call_operand gets spilled to a
4222 if (GET_CODE (x) == MEM)
4227 /* Need to go through general regsters to get to other class regs. */
4228 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4231 /* This can happen when a paradoxical subreg is an operand to the
4233 /* ??? This shouldn't be necessary after instruction scheduling is
4234 enabled, because paradoxical subregs are not accepted by
4235 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4236 stop the paradoxical subreg stupidity in the *_operand functions
4238 if (GET_CODE (x) == MEM
4239 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4240 || GET_MODE (x) == QImode))
4243 /* This can happen because of the ior/and/etc patterns that accept FP
4244 registers as operands. If the third operand is a constant, then it
4245 needs to be reloaded into a FP register. */
4246 if (GET_CODE (x) == CONST_INT)
4249 /* This can happen because of register elimination in a muldi3 insn.
4250 E.g. `26107 * (unsigned long)&u'. */
4251 if (GET_CODE (x) == PLUS)
4256 /* ??? This happens if we cse/gcse a BImode value across a call,
4257 and the function has a nonlocal goto. This is because global
4258 does not allocate call crossing pseudos to hard registers when
4259 current_function_has_nonlocal_goto is true. This is relatively
4260 common for C++ programs that use exceptions. To reproduce,
4261 return NO_REGS and compile libstdc++. */
4262 if (GET_CODE (x) == MEM)
4265 /* This can happen when we take a BImode subreg of a DImode value,
4266 and that DImode value winds up in some non-GR register. */
4267 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4272 /* Since we have no offsettable memory addresses, we need a temporary
4273 to hold the address of the second word. */
4286 /* Emit text to declare externally defined variables and functions, because
4287 the Intel assembler does not support undefined externals. */
4290 ia64_asm_output_external (file, decl, name)
4295 int save_referenced;
4297 /* GNU as does not need anything here, but the HP linker does need
4298 something for external functions. */
4302 || TREE_CODE (decl) != FUNCTION_DECL
4303 || strstr(name, "__builtin_") == name))
4306 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4307 the linker when we do this, so we need to be careful not to do this for
4308 builtin functions which have no library equivalent. Unfortunately, we
4309 can't tell here whether or not a function will actually be called by
4310 expand_expr, so we pull in library functions even if we may not need
4312 if (! strcmp (name, "__builtin_next_arg")
4313 || ! strcmp (name, "alloca")
4314 || ! strcmp (name, "__builtin_constant_p")
4315 || ! strcmp (name, "__builtin_args_info"))
4319 ia64_hpux_add_extern_decl (name);
4322 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4324 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4325 if (TREE_CODE (decl) == FUNCTION_DECL)
4326 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4327 (*targetm.asm_out.globalize_label) (file, name);
4328 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4332 /* Parse the -mfixed-range= option string. */
4335 fix_range (const_str)
4336 const char *const_str;
4339 char *str, *dash, *comma;
4341 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4342 REG2 are either register names or register numbers. The effect
4343 of this option is to mark the registers in the range from REG1 to
4344 REG2 as ``fixed'' so they won't be used by the compiler. This is
4345 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4347 i = strlen (const_str);
4348 str = (char *) alloca (i + 1);
4349 memcpy (str, const_str, i + 1);
4353 dash = strchr (str, '-');
4356 warning ("value of -mfixed-range must have form REG1-REG2");
4361 comma = strchr (dash + 1, ',');
4365 first = decode_reg_name (str);
4368 warning ("unknown register name: %s", str);
4372 last = decode_reg_name (dash + 1);
4375 warning ("unknown register name: %s", dash + 1);
4383 warning ("%s-%s is an empty range", str, dash + 1);
4387 for (i = first; i <= last; ++i)
4388 fixed_regs[i] = call_used_regs[i] = 1;
4398 static struct machine_function *
4399 ia64_init_machine_status ()
4401 return ggc_alloc_cleared (sizeof (struct machine_function));
4404 /* Handle TARGET_OPTIONS switches. */
4407 ia64_override_options ()
4411 const char *const name; /* processor name or nickname. */
4412 const enum processor_type processor;
4414 const processor_alias_table[] =
4416 {"itanium", PROCESSOR_ITANIUM},
4417 {"itanium1", PROCESSOR_ITANIUM},
4418 {"merced", PROCESSOR_ITANIUM},
4419 {"itanium2", PROCESSOR_ITANIUM2},
4420 {"mckinley", PROCESSOR_ITANIUM2},
4423 int const pta_size = ARRAY_SIZE (processor_alias_table);
4426 if (TARGET_AUTO_PIC)
4427 target_flags |= MASK_CONST_GP;
4429 if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
4431 warning ("cannot optimize floating point division for both latency and throughput");
4432 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4435 if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
4437 warning ("cannot optimize integer division for both latency and throughput");
4438 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4441 if (ia64_fixed_range_string)
4442 fix_range (ia64_fixed_range_string);
4444 if (ia64_tls_size_string)
4447 unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
4448 if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
4449 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
4451 ia64_tls_size = tmp;
4454 if (!ia64_tune_string)
4455 ia64_tune_string = "itanium2";
4457 for (i = 0; i < pta_size; i++)
4458 if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
4460 ia64_tune = processor_alias_table[i].processor;
4465 error ("bad value (%s) for -tune= switch", ia64_tune_string);
4467 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4468 flag_schedule_insns_after_reload = 0;
4470 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4472 init_machine_status = ia64_init_machine_status;
4474 /* Tell the compiler which flavor of TFmode we're using. */
4475 if (INTEL_EXTENDED_IEEE_FORMAT)
4476 real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
4479 static enum attr_itanium_class ia64_safe_itanium_class PARAMS((rtx));
4480 static enum attr_type ia64_safe_type PARAMS((rtx));
4482 static enum attr_itanium_class
4483 ia64_safe_itanium_class (insn)
4486 if (recog_memoized (insn) >= 0)
4487 return get_attr_itanium_class (insn);
4489 return ITANIUM_CLASS_UNKNOWN;
4492 static enum attr_type
4493 ia64_safe_type (insn)
4496 if (recog_memoized (insn) >= 0)
4497 return get_attr_type (insn);
4499 return TYPE_UNKNOWN;
4502 /* The following collection of routines emit instruction group stop bits as
4503 necessary to avoid dependencies. */
4505 /* Need to track some additional registers as far as serialization is
4506 concerned so we can properly handle br.call and br.ret. We could
4507 make these registers visible to gcc, but since these registers are
4508 never explicitly used in gcc generated code, it seems wasteful to
4509 do so (plus it would make the call and return patterns needlessly
4511 #define REG_GP (GR_REG (1))
4512 #define REG_RP (BR_REG (0))
4513 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4514 /* This is used for volatile asms which may require a stop bit immediately
4515 before and after them. */
4516 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4517 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4518 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4520 /* For each register, we keep track of how it has been written in the
4521 current instruction group.
4523 If a register is written unconditionally (no qualifying predicate),
4524 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4526 If a register is written if its qualifying predicate P is true, we
4527 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4528 may be written again by the complement of P (P^1) and when this happens,
4529 WRITE_COUNT gets set to 2.
4531 The result of this is that whenever an insn attempts to write a register
4532 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4534 If a predicate register is written by a floating-point insn, we set
4535 WRITTEN_BY_FP to true.
4537 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4538 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4540 struct reg_write_state
4542 unsigned int write_count : 2;
4543 unsigned int first_pred : 16;
4544 unsigned int written_by_fp : 1;
4545 unsigned int written_by_and : 1;
4546 unsigned int written_by_or : 1;
4549 /* Cumulative info for the current instruction group. */
4550 struct reg_write_state rws_sum[NUM_REGS];
4551 /* Info for the current instruction. This gets copied to rws_sum after a
4552 stop bit is emitted. */
4553 struct reg_write_state rws_insn[NUM_REGS];
4555 /* Indicates whether this is the first instruction after a stop bit,
4556 in which case we don't need another stop bit. Without this, we hit
4557 the abort in ia64_variable_issue when scheduling an alloc. */
4558 static int first_instruction;
4560 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4561 RTL for one instruction. */
4564 unsigned int is_write : 1; /* Is register being written? */
4565 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4566 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4567 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4568 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4569 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4572 static void rws_update PARAMS ((struct reg_write_state *, int,
4573 struct reg_flags, int));
4574 static int rws_access_regno PARAMS ((int, struct reg_flags, int));
4575 static int rws_access_reg PARAMS ((rtx, struct reg_flags, int));
4576 static void update_set_flags PARAMS ((rtx, struct reg_flags *, int *, rtx *));
4577 static int set_src_needs_barrier PARAMS ((rtx, struct reg_flags, int, rtx));
4578 static int rtx_needs_barrier PARAMS ((rtx, struct reg_flags, int));
4579 static void init_insn_group_barriers PARAMS ((void));
4580 static int group_barrier_needed_p PARAMS ((rtx));
4581 static int safe_group_barrier_needed_p PARAMS ((rtx));
4583 /* Update *RWS for REGNO, which is being written by the current instruction,
4584 with predicate PRED, and associated register flags in FLAGS. */
4587 rws_update (rws, regno, flags, pred)
4588 struct reg_write_state *rws;
4590 struct reg_flags flags;
4594 rws[regno].write_count++;
4596 rws[regno].write_count = 2;
4597 rws[regno].written_by_fp |= flags.is_fp;
4598 /* ??? Not tracking and/or across differing predicates. */
4599 rws[regno].written_by_and = flags.is_and;
4600 rws[regno].written_by_or = flags.is_or;
4601 rws[regno].first_pred = pred;
4604 /* Handle an access to register REGNO of type FLAGS using predicate register
4605 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4606 a dependency with an earlier instruction in the same group. */
4609 rws_access_regno (regno, flags, pred)
4611 struct reg_flags flags;
4614 int need_barrier = 0;
4616 if (regno >= NUM_REGS)
4619 if (! PR_REGNO_P (regno))
4620 flags.is_and = flags.is_or = 0;
4626 /* One insn writes same reg multiple times? */
4627 if (rws_insn[regno].write_count > 0)
4630 /* Update info for current instruction. */
4631 rws_update (rws_insn, regno, flags, pred);
4632 write_count = rws_sum[regno].write_count;
4634 switch (write_count)
4637 /* The register has not been written yet. */
4638 rws_update (rws_sum, regno, flags, pred);
4642 /* The register has been written via a predicate. If this is
4643 not a complementary predicate, then we need a barrier. */
4644 /* ??? This assumes that P and P+1 are always complementary
4645 predicates for P even. */
4646 if (flags.is_and && rws_sum[regno].written_by_and)
4648 else if (flags.is_or && rws_sum[regno].written_by_or)
4650 else if ((rws_sum[regno].first_pred ^ 1) != pred)
4652 rws_update (rws_sum, regno, flags, pred);
4656 /* The register has been unconditionally written already. We
4658 if (flags.is_and && rws_sum[regno].written_by_and)
4660 else if (flags.is_or && rws_sum[regno].written_by_or)
4664 rws_sum[regno].written_by_and = flags.is_and;
4665 rws_sum[regno].written_by_or = flags.is_or;
4674 if (flags.is_branch)
4676 /* Branches have several RAW exceptions that allow to avoid
4679 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
4680 /* RAW dependencies on branch regs are permissible as long
4681 as the writer is a non-branch instruction. Since we
4682 never generate code that uses a branch register written
4683 by a branch instruction, handling this case is
4687 if (REGNO_REG_CLASS (regno) == PR_REGS
4688 && ! rws_sum[regno].written_by_fp)
4689 /* The predicates of a branch are available within the
4690 same insn group as long as the predicate was written by
4691 something other than a floating-point instruction. */
4695 if (flags.is_and && rws_sum[regno].written_by_and)
4697 if (flags.is_or && rws_sum[regno].written_by_or)
4700 switch (rws_sum[regno].write_count)
4703 /* The register has not been written yet. */
4707 /* The register has been written via a predicate. If this is
4708 not a complementary predicate, then we need a barrier. */
4709 /* ??? This assumes that P and P+1 are always complementary
4710 predicates for P even. */
4711 if ((rws_sum[regno].first_pred ^ 1) != pred)
4716 /* The register has been unconditionally written already. We
4726 return need_barrier;
4730 rws_access_reg (reg, flags, pred)
4732 struct reg_flags flags;
4735 int regno = REGNO (reg);
4736 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4739 return rws_access_regno (regno, flags, pred);
4742 int need_barrier = 0;
4744 need_barrier |= rws_access_regno (regno + n, flags, pred);
4745 return need_barrier;
4749 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4750 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4753 update_set_flags (x, pflags, ppred, pcond)
4755 struct reg_flags *pflags;
4759 rtx src = SET_SRC (x);
4763 switch (GET_CODE (src))
4769 if (SET_DEST (x) == pc_rtx)
4770 /* X is a conditional branch. */
4774 int is_complemented = 0;
4776 /* X is a conditional move. */
4777 rtx cond = XEXP (src, 0);
4778 if (GET_CODE (cond) == EQ)
4779 is_complemented = 1;
4780 cond = XEXP (cond, 0);
4781 if (GET_CODE (cond) != REG
4782 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4785 if (XEXP (src, 1) == SET_DEST (x)
4786 || XEXP (src, 2) == SET_DEST (x))
4788 /* X is a conditional move that conditionally writes the
4791 /* We need another complement in this case. */
4792 if (XEXP (src, 1) == SET_DEST (x))
4793 is_complemented = ! is_complemented;
4795 *ppred = REGNO (cond);
4796 if (is_complemented)
4800 /* ??? If this is a conditional write to the dest, then this
4801 instruction does not actually read one source. This probably
4802 doesn't matter, because that source is also the dest. */
4803 /* ??? Multiple writes to predicate registers are allowed
4804 if they are all AND type compares, or if they are all OR
4805 type compares. We do not generate such instructions
4808 /* ... fall through ... */
4811 if (GET_RTX_CLASS (GET_CODE (src)) == '<'
4812 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
4813 /* Set pflags->is_fp to 1 so that we know we're dealing
4814 with a floating point comparison when processing the
4815 destination of the SET. */
4818 /* Discover if this is a parallel comparison. We only handle
4819 and.orcm and or.andcm at present, since we must retain a
4820 strict inverse on the predicate pair. */
4821 else if (GET_CODE (src) == AND)
4823 else if (GET_CODE (src) == IOR)
4830 /* Subroutine of rtx_needs_barrier; this function determines whether the
4831 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
4832 are as in rtx_needs_barrier. COND is an rtx that holds the condition
4836 set_src_needs_barrier (x, flags, pred, cond)
4838 struct reg_flags flags;
4842 int need_barrier = 0;
4844 rtx src = SET_SRC (x);
4846 if (GET_CODE (src) == CALL)
4847 /* We don't need to worry about the result registers that
4848 get written by subroutine call. */
4849 return rtx_needs_barrier (src, flags, pred);
4850 else if (SET_DEST (x) == pc_rtx)
4852 /* X is a conditional branch. */
4853 /* ??? This seems redundant, as the caller sets this bit for
4855 flags.is_branch = 1;
4856 return rtx_needs_barrier (src, flags, pred);
4859 need_barrier = rtx_needs_barrier (src, flags, pred);
4861 /* This instruction unconditionally uses a predicate register. */
4863 need_barrier |= rws_access_reg (cond, flags, 0);
4866 if (GET_CODE (dst) == ZERO_EXTRACT)
4868 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
4869 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
4870 dst = XEXP (dst, 0);
4872 return need_barrier;
4875 /* Handle an access to rtx X of type FLAGS using predicate register PRED.
4876 Return 1 is this access creates a dependency with an earlier instruction
4877 in the same group. */
4880 rtx_needs_barrier (x, flags, pred)
4882 struct reg_flags flags;
4886 int is_complemented = 0;
4887 int need_barrier = 0;
4888 const char *format_ptr;
4889 struct reg_flags new_flags;
4897 switch (GET_CODE (x))
4900 update_set_flags (x, &new_flags, &pred, &cond);
4901 need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
4902 if (GET_CODE (SET_SRC (x)) != CALL)
4904 new_flags.is_write = 1;
4905 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
4910 new_flags.is_write = 0;
4911 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
4913 /* Avoid multiple register writes, in case this is a pattern with
4914 multiple CALL rtx. This avoids an abort in rws_access_reg. */
4915 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
4917 new_flags.is_write = 1;
4918 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
4919 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
4920 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4925 /* X is a predicated instruction. */
4927 cond = COND_EXEC_TEST (x);
4930 need_barrier = rtx_needs_barrier (cond, flags, 0);
4932 if (GET_CODE (cond) == EQ)
4933 is_complemented = 1;
4934 cond = XEXP (cond, 0);
4935 if (GET_CODE (cond) != REG
4936 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4938 pred = REGNO (cond);
4939 if (is_complemented)
4942 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
4943 return need_barrier;
4947 /* Clobber & use are for earlier compiler-phases only. */
4952 /* We always emit stop bits for traditional asms. We emit stop bits
4953 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
4954 if (GET_CODE (x) != ASM_OPERANDS
4955 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
4957 /* Avoid writing the register multiple times if we have multiple
4958 asm outputs. This avoids an abort in rws_access_reg. */
4959 if (! rws_insn[REG_VOLATILE].write_count)
4961 new_flags.is_write = 1;
4962 rws_access_regno (REG_VOLATILE, new_flags, pred);
4967 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
4968 We can not just fall through here since then we would be confused
4969 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
4970 traditional asms unlike their normal usage. */
4972 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
4973 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
4978 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
4980 rtx pat = XVECEXP (x, 0, i);
4981 if (GET_CODE (pat) == SET)
4983 update_set_flags (pat, &new_flags, &pred, &cond);
4984 need_barrier |= set_src_needs_barrier (pat, new_flags, pred, cond);
4986 else if (GET_CODE (pat) == USE
4987 || GET_CODE (pat) == CALL
4988 || GET_CODE (pat) == ASM_OPERANDS)
4989 need_barrier |= rtx_needs_barrier (pat, flags, pred);
4990 else if (GET_CODE (pat) != CLOBBER && GET_CODE (pat) != RETURN)
4993 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
4995 rtx pat = XVECEXP (x, 0, i);
4996 if (GET_CODE (pat) == SET)
4998 if (GET_CODE (SET_SRC (pat)) != CALL)
5000 new_flags.is_write = 1;
5001 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5005 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5006 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5014 if (REGNO (x) == AR_UNAT_REGNUM)
5016 for (i = 0; i < 64; ++i)
5017 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5020 need_barrier = rws_access_reg (x, flags, pred);
5024 /* Find the regs used in memory address computation. */
5025 new_flags.is_write = 0;
5026 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5029 case CONST_INT: case CONST_DOUBLE:
5030 case SYMBOL_REF: case LABEL_REF: case CONST:
5033 /* Operators with side-effects. */
5034 case POST_INC: case POST_DEC:
5035 if (GET_CODE (XEXP (x, 0)) != REG)
5038 new_flags.is_write = 0;
5039 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5040 new_flags.is_write = 1;
5041 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5045 if (GET_CODE (XEXP (x, 0)) != REG)
5048 new_flags.is_write = 0;
5049 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5050 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5051 new_flags.is_write = 1;
5052 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5055 /* Handle common unary and binary ops for efficiency. */
5056 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5057 case MOD: case UDIV: case UMOD: case AND: case IOR:
5058 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5059 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5060 case NE: case EQ: case GE: case GT: case LE:
5061 case LT: case GEU: case GTU: case LEU: case LTU:
5062 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5063 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5066 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5067 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5068 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5069 case SQRT: case FFS: case POPCOUNT:
5070 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5074 switch (XINT (x, 1))
5076 case UNSPEC_LTOFF_DTPMOD:
5077 case UNSPEC_LTOFF_DTPREL:
5079 case UNSPEC_LTOFF_TPREL:
5081 case UNSPEC_PRED_REL_MUTEX:
5082 case UNSPEC_PIC_CALL:
5084 case UNSPEC_FETCHADD_ACQ:
5085 case UNSPEC_BSP_VALUE:
5086 case UNSPEC_FLUSHRS:
5087 case UNSPEC_BUNDLE_SELECTOR:
5090 case UNSPEC_GR_SPILL:
5091 case UNSPEC_GR_RESTORE:
5093 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5094 HOST_WIDE_INT bit = (offset >> 3) & 63;
5096 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5097 new_flags.is_write = (XINT (x, 1) == 1);
5098 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5103 case UNSPEC_FR_SPILL:
5104 case UNSPEC_FR_RESTORE:
5105 case UNSPEC_GETF_EXP:
5107 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5110 case UNSPEC_FR_RECIP_APPROX:
5111 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5112 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5115 case UNSPEC_CMPXCHG_ACQ:
5116 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5117 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5125 case UNSPEC_VOLATILE:
5126 switch (XINT (x, 1))
5129 /* Alloc must always be the first instruction of a group.
5130 We force this by always returning true. */
5131 /* ??? We might get better scheduling if we explicitly check for
5132 input/local/output register dependencies, and modify the
5133 scheduler so that alloc is always reordered to the start of
5134 the current group. We could then eliminate all of the
5135 first_instruction code. */
5136 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5138 new_flags.is_write = 1;
5139 rws_access_regno (REG_AR_CFM, new_flags, pred);
5142 case UNSPECV_SET_BSP:
5146 case UNSPECV_BLOCKAGE:
5147 case UNSPECV_INSN_GROUP_BARRIER:
5149 case UNSPECV_PSAC_ALL:
5150 case UNSPECV_PSAC_NORMAL:
5159 new_flags.is_write = 0;
5160 need_barrier = rws_access_regno (REG_RP, flags, pred);
5161 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5163 new_flags.is_write = 1;
5164 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5165 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5169 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5170 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5171 switch (format_ptr[i])
5173 case '0': /* unused field */
5174 case 'i': /* integer */
5175 case 'n': /* note */
5176 case 'w': /* wide integer */
5177 case 's': /* pointer to string */
5178 case 'S': /* optional pointer to string */
5182 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5187 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5188 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5197 return need_barrier;
5200 /* Clear out the state for group_barrier_needed_p at the start of a
5201 sequence of insns. */
5204 init_insn_group_barriers ()
5206 memset (rws_sum, 0, sizeof (rws_sum));
5207 first_instruction = 1;
5210 /* Given the current state, recorded by previous calls to this function,
5211 determine whether a group barrier (a stop bit) is necessary before INSN.
5212 Return nonzero if so. */
5215 group_barrier_needed_p (insn)
5219 int need_barrier = 0;
5220 struct reg_flags flags;
5222 memset (&flags, 0, sizeof (flags));
5223 switch (GET_CODE (insn))
5229 /* A barrier doesn't imply an instruction group boundary. */
5233 memset (rws_insn, 0, sizeof (rws_insn));
5237 flags.is_branch = 1;
5238 flags.is_sibcall = SIBLING_CALL_P (insn);
5239 memset (rws_insn, 0, sizeof (rws_insn));
5241 /* Don't bundle a call following another call. */
5242 if ((pat = prev_active_insn (insn))
5243 && GET_CODE (pat) == CALL_INSN)
5249 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5253 flags.is_branch = 1;
5255 /* Don't bundle a jump following a call. */
5256 if ((pat = prev_active_insn (insn))
5257 && GET_CODE (pat) == CALL_INSN)
5265 if (GET_CODE (PATTERN (insn)) == USE
5266 || GET_CODE (PATTERN (insn)) == CLOBBER)
5267 /* Don't care about USE and CLOBBER "insns"---those are used to
5268 indicate to the optimizer that it shouldn't get rid of
5269 certain operations. */
5272 pat = PATTERN (insn);
5274 /* Ug. Hack hacks hacked elsewhere. */
5275 switch (recog_memoized (insn))
5277 /* We play dependency tricks with the epilogue in order
5278 to get proper schedules. Undo this for dv analysis. */
5279 case CODE_FOR_epilogue_deallocate_stack:
5280 case CODE_FOR_prologue_allocate_stack:
5281 pat = XVECEXP (pat, 0, 0);
5284 /* The pattern we use for br.cloop confuses the code above.
5285 The second element of the vector is representative. */
5286 case CODE_FOR_doloop_end_internal:
5287 pat = XVECEXP (pat, 0, 1);
5290 /* Doesn't generate code. */
5291 case CODE_FOR_pred_rel_mutex:
5292 case CODE_FOR_prologue_use:
5299 memset (rws_insn, 0, sizeof (rws_insn));
5300 need_barrier = rtx_needs_barrier (pat, flags, 0);
5302 /* Check to see if the previous instruction was a volatile
5305 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5312 if (first_instruction && INSN_P (insn)
5313 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5314 && GET_CODE (PATTERN (insn)) != USE
5315 && GET_CODE (PATTERN (insn)) != CLOBBER)
5318 first_instruction = 0;
5321 return need_barrier;
5324 /* Like group_barrier_needed_p, but do not clobber the current state. */
5327 safe_group_barrier_needed_p (insn)
5330 struct reg_write_state rws_saved[NUM_REGS];
5331 int saved_first_instruction;
5334 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5335 saved_first_instruction = first_instruction;
5337 t = group_barrier_needed_p (insn);
5339 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5340 first_instruction = saved_first_instruction;
5345 /* INSNS is a chain of instructions. Scan the chain, and insert stop bits
5346 as necessary to eliminate dependencies. This function assumes that
5347 a final instruction scheduling pass has been run which has already
5348 inserted most of the necessary stop bits. This function only inserts
5349 new ones at basic block boundaries, since these are invisible to the
5353 emit_insn_group_barriers (dump, insns)
5359 int insns_since_last_label = 0;
5361 init_insn_group_barriers ();
5363 for (insn = insns; insn; insn = NEXT_INSN (insn))
5365 if (GET_CODE (insn) == CODE_LABEL)
5367 if (insns_since_last_label)
5369 insns_since_last_label = 0;
5371 else if (GET_CODE (insn) == NOTE
5372 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5374 if (insns_since_last_label)
5376 insns_since_last_label = 0;
5378 else if (GET_CODE (insn) == INSN
5379 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5380 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5382 init_insn_group_barriers ();
5385 else if (INSN_P (insn))
5387 insns_since_last_label = 1;
5389 if (group_barrier_needed_p (insn))
5394 fprintf (dump, "Emitting stop before label %d\n",
5395 INSN_UID (last_label));
5396 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5399 init_insn_group_barriers ();
5407 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5408 This function has to emit all necessary group barriers. */
5411 emit_all_insn_group_barriers (dump, insns)
5412 FILE *dump ATTRIBUTE_UNUSED;
5417 init_insn_group_barriers ();
5419 for (insn = insns; insn; insn = NEXT_INSN (insn))
5421 if (GET_CODE (insn) == BARRIER)
5423 rtx last = prev_active_insn (insn);
5427 if (GET_CODE (last) == JUMP_INSN
5428 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5429 last = prev_active_insn (last);
5430 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5431 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5433 init_insn_group_barriers ();
5435 else if (INSN_P (insn))
5437 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5438 init_insn_group_barriers ();
5439 else if (group_barrier_needed_p (insn))
5441 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5442 init_insn_group_barriers ();
5443 group_barrier_needed_p (insn);
5450 static int errata_find_address_regs PARAMS ((rtx *, void *));
5451 static void errata_emit_nops PARAMS ((rtx));
5452 static void fixup_errata PARAMS ((void));
5454 /* This structure is used to track some details about the previous insns
5455 groups so we can determine if it may be necessary to insert NOPs to
5456 workaround hardware errata. */
5459 HARD_REG_SET p_reg_set;
5460 HARD_REG_SET gr_reg_conditionally_set;
5463 /* Index into the last_group array. */
5464 static int group_idx;
5466 /* Called through for_each_rtx; determines if a hard register that was
5467 conditionally set in the previous group is used as an address register.
5468 It ensures that for_each_rtx returns 1 in that case. */
5470 errata_find_address_regs (xp, data)
5472 void *data ATTRIBUTE_UNUSED;
5475 if (GET_CODE (x) != MEM)
5478 if (GET_CODE (x) == POST_MODIFY)
5480 if (GET_CODE (x) == REG)
5482 struct group *prev_group = last_group + (group_idx ^ 1);
5483 if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set,
5491 /* Called for each insn; this function keeps track of the state in
5492 last_group and emits additional NOPs if necessary to work around
5493 an Itanium A/B step erratum. */
5495 errata_emit_nops (insn)
5498 struct group *this_group = last_group + group_idx;
5499 struct group *prev_group = last_group + (group_idx ^ 1);
5500 rtx pat = PATTERN (insn);
5501 rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0;
5502 rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat;
5503 enum attr_type type;
5506 if (GET_CODE (real_pat) == USE
5507 || GET_CODE (real_pat) == CLOBBER
5508 || GET_CODE (real_pat) == ASM_INPUT
5509 || GET_CODE (real_pat) == ADDR_VEC
5510 || GET_CODE (real_pat) == ADDR_DIFF_VEC
5511 || asm_noperands (PATTERN (insn)) >= 0)
5514 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5517 if (GET_CODE (set) == PARALLEL)
5520 set = XVECEXP (real_pat, 0, 0);
5521 for (i = 1; i < XVECLEN (real_pat, 0); i++)
5522 if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE
5523 && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER)
5530 if (set && GET_CODE (set) != SET)
5533 type = get_attr_type (insn);
5536 && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set))))
5537 SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set)));
5539 if ((type == TYPE_M || type == TYPE_A) && cond && set
5540 && REG_P (SET_DEST (set))
5541 && GET_CODE (SET_SRC (set)) != PLUS
5542 && GET_CODE (SET_SRC (set)) != MINUS
5543 && (GET_CODE (SET_SRC (set)) != ASHIFT
5544 || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode))
5545 && (GET_CODE (SET_SRC (set)) != MEM
5546 || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY)
5547 && GENERAL_REGNO_P (REGNO (SET_DEST (set))))
5549 if (GET_RTX_CLASS (GET_CODE (cond)) != '<'
5550 || ! REG_P (XEXP (cond, 0)))
5553 if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0))))
5554 SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set)));
5556 if (for_each_rtx (&real_pat, errata_find_address_regs, NULL))
5558 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5559 emit_insn_before (gen_nop (), insn);
5560 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5562 memset (last_group, 0, sizeof last_group);
5566 /* Emit extra nops if they are required to work around hardware errata. */
5573 if (! TARGET_B_STEP)
5577 memset (last_group, 0, sizeof last_group);
5579 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5584 if (ia64_safe_type (insn) == TYPE_S)
5587 memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
5590 errata_emit_nops (insn);
5595 /* Instruction scheduling support. */
5597 #define NR_BUNDLES 10
5599 /* A list of names of all available bundles. */
5601 static const char *bundle_name [NR_BUNDLES] =
5607 #if NR_BUNDLES == 10
5617 /* Nonzero if we should insert stop bits into the schedule. */
5619 int ia64_final_schedule = 0;
5621 /* Codes of the corresponding quieryied units: */
5623 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5624 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5626 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5627 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5629 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5631 /* The following variable value is an insn group barrier. */
5633 static rtx dfa_stop_insn;
5635 /* The following variable value is the last issued insn. */
5637 static rtx last_scheduled_insn;
5639 /* The following variable value is size of the DFA state. */
5641 static size_t dfa_state_size;
5643 /* The following variable value is pointer to a DFA state used as
5644 temporary variable. */
5646 static state_t temp_dfa_state = NULL;
5648 /* The following variable value is DFA state after issuing the last
5651 static state_t prev_cycle_state = NULL;
5653 /* The following array element values are TRUE if the corresponding
5654 insn requires to add stop bits before it. */
5656 static char *stops_p;
5658 /* The following variable is used to set up the mentioned above array. */
5660 static int stop_before_p = 0;
5662 /* The following variable value is length of the arrays `clocks' and
5665 static int clocks_length;
5667 /* The following array element values are cycles on which the
5668 corresponding insn will be issued. The array is used only for
5673 /* The following array element values are numbers of cycles should be
5674 added to improve insn scheduling for MM_insns for Itanium1. */
5676 static int *add_cycles;
5678 static rtx ia64_single_set PARAMS ((rtx));
5679 static void ia64_emit_insn_before PARAMS ((rtx, rtx));
5681 /* Map a bundle number to its pseudo-op. */
5687 return bundle_name[b];
5691 /* Return the maximum number of instructions a cpu can issue. */
5699 /* Helper function - like single_set, but look inside COND_EXEC. */
5702 ia64_single_set (insn)
5705 rtx x = PATTERN (insn), ret;
5706 if (GET_CODE (x) == COND_EXEC)
5707 x = COND_EXEC_CODE (x);
5708 if (GET_CODE (x) == SET)
5711 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5712 Although they are not classical single set, the second set is there just
5713 to protect it from moving past FP-relative stack accesses. */
5714 switch (recog_memoized (insn))
5716 case CODE_FOR_prologue_allocate_stack:
5717 case CODE_FOR_epilogue_deallocate_stack:
5718 ret = XVECEXP (x, 0, 0);
5722 ret = single_set_2 (insn, x);
5729 /* Adjust the cost of a scheduling dependency. Return the new cost of
5730 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5733 ia64_adjust_cost (insn, link, dep_insn, cost)
5734 rtx insn, link, dep_insn;
5737 enum attr_itanium_class dep_class;
5738 enum attr_itanium_class insn_class;
5740 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
5743 insn_class = ia64_safe_itanium_class (insn);
5744 dep_class = ia64_safe_itanium_class (dep_insn);
5745 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
5746 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
5752 /* Like emit_insn_before, but skip cycle_display notes.
5753 ??? When cycle display notes are implemented, update this. */
5756 ia64_emit_insn_before (insn, before)
5759 emit_insn_before (insn, before);
5762 /* The following function marks insns who produce addresses for load
5763 and store insns. Such insns will be placed into M slots because it
5764 decrease latency time for Itanium1 (see function
5765 `ia64_produce_address_p' and the DFA descriptions). */
5768 ia64_dependencies_evaluation_hook (head, tail)
5771 rtx insn, link, next, next_tail;
5773 next_tail = NEXT_INSN (tail);
5774 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5777 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5779 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
5781 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
5783 next = XEXP (link, 0);
5784 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
5785 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
5786 && ia64_st_address_bypass_p (insn, next))
5788 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
5789 || ia64_safe_itanium_class (next)
5790 == ITANIUM_CLASS_FLD)
5791 && ia64_ld_address_bypass_p (insn, next))
5794 insn->call = link != 0;
5798 /* We're beginning a new block. Initialize data structures as necessary. */
5801 ia64_sched_init (dump, sched_verbose, max_ready)
5802 FILE *dump ATTRIBUTE_UNUSED;
5803 int sched_verbose ATTRIBUTE_UNUSED;
5804 int max_ready ATTRIBUTE_UNUSED;
5806 #ifdef ENABLE_CHECKING
5809 if (reload_completed)
5810 for (insn = NEXT_INSN (current_sched_info->prev_head);
5811 insn != current_sched_info->next_tail;
5812 insn = NEXT_INSN (insn))
5813 if (SCHED_GROUP_P (insn))
5816 last_scheduled_insn = NULL_RTX;
5817 init_insn_group_barriers ();
5820 /* We are about to being issuing insns for this clock cycle.
5821 Override the default sort algorithm to better slot instructions. */
5824 ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5825 clock_var, reorder_type)
5830 int clock_var ATTRIBUTE_UNUSED;
5834 int n_ready = *pn_ready;
5835 rtx *e_ready = ready + n_ready;
5839 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
5841 if (reorder_type == 0)
5843 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5845 for (insnp = ready; insnp < e_ready; insnp++)
5846 if (insnp < e_ready)
5849 enum attr_type t = ia64_safe_type (insn);
5850 if (t == TYPE_UNKNOWN)
5852 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
5853 || asm_noperands (PATTERN (insn)) >= 0)
5855 rtx lowest = ready[n_asms];
5856 ready[n_asms] = insn;
5862 rtx highest = ready[n_ready - 1];
5863 ready[n_ready - 1] = insn;
5870 if (n_asms < n_ready)
5872 /* Some normal insns to process. Skip the asms. */
5876 else if (n_ready > 0)
5880 if (ia64_final_schedule)
5883 int nr_need_stop = 0;
5885 for (insnp = ready; insnp < e_ready; insnp++)
5886 if (safe_group_barrier_needed_p (*insnp))
5889 if (reorder_type == 1 && n_ready == nr_need_stop)
5891 if (reorder_type == 0)
5894 /* Move down everything that needs a stop bit, preserving
5896 while (insnp-- > ready + deleted)
5897 while (insnp >= ready + deleted)
5900 if (! safe_group_barrier_needed_p (insn))
5902 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
5913 /* We are about to being issuing insns for this clock cycle. Override
5914 the default sort algorithm to better slot instructions. */
5917 ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
5924 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
5925 pn_ready, clock_var, 0);
5928 /* Like ia64_sched_reorder, but called after issuing each insn.
5929 Override the default sort algorithm to better slot instructions. */
5932 ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
5933 FILE *dump ATTRIBUTE_UNUSED;
5934 int sched_verbose ATTRIBUTE_UNUSED;
5939 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
5940 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
5941 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5945 /* We are about to issue INSN. Return the number of insns left on the
5946 ready queue that can be issued this cycle. */
5949 ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
5950 FILE *dump ATTRIBUTE_UNUSED;
5951 int sched_verbose ATTRIBUTE_UNUSED;
5952 rtx insn ATTRIBUTE_UNUSED;
5953 int can_issue_more ATTRIBUTE_UNUSED;
5955 last_scheduled_insn = insn;
5956 memcpy (prev_cycle_state, curr_state, dfa_state_size);
5957 if (reload_completed)
5959 if (group_barrier_needed_p (insn))
5961 if (GET_CODE (insn) == CALL_INSN)
5962 init_insn_group_barriers ();
5963 stops_p [INSN_UID (insn)] = stop_before_p;
5969 /* We are choosing insn from the ready queue. Return nonzero if INSN
5973 ia64_first_cycle_multipass_dfa_lookahead_guard (insn)
5976 if (insn == NULL_RTX || !INSN_P (insn))
5978 return (!reload_completed
5979 || !safe_group_barrier_needed_p (insn));
5982 /* The following variable value is pseudo-insn used by the DFA insn
5983 scheduler to change the DFA state when the simulated clock is
5986 static rtx dfa_pre_cycle_insn;
5988 /* We are about to being issuing INSN. Return nonzero if we can not
5989 issue it on given cycle CLOCK and return zero if we should not sort
5990 the ready queue on the next clock start. */
5993 ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
5997 int last_clock, clock;
6000 int setup_clocks_p = FALSE;
6002 if (insn == NULL_RTX || !INSN_P (insn))
6004 if ((reload_completed && safe_group_barrier_needed_p (insn))
6005 || (last_scheduled_insn
6006 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6007 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6008 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6010 init_insn_group_barriers ();
6011 if (verbose && dump)
6012 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6013 last_clock == clock ? " + cycle advance" : "");
6015 if (last_clock == clock)
6017 state_transition (curr_state, dfa_stop_insn);
6018 if (TARGET_EARLY_STOP_BITS)
6019 *sort_p = (last_scheduled_insn == NULL_RTX
6020 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6025 else if (reload_completed)
6026 setup_clocks_p = TRUE;
6027 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6028 state_transition (curr_state, dfa_stop_insn);
6029 state_transition (curr_state, dfa_pre_cycle_insn);
6030 state_transition (curr_state, NULL);
6032 else if (reload_completed)
6033 setup_clocks_p = TRUE;
6034 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
6036 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6038 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6043 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6044 if (REG_NOTE_KIND (link) == 0)
6046 enum attr_itanium_class dep_class;
6047 rtx dep_insn = XEXP (link, 0);
6049 dep_class = ia64_safe_itanium_class (dep_insn);
6050 if ((dep_class == ITANIUM_CLASS_MMMUL
6051 || dep_class == ITANIUM_CLASS_MMSHF)
6052 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6054 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6055 d = last_clock - clocks [INSN_UID (dep_insn)];
6058 add_cycles [INSN_UID (insn)] = 3 - d;
6066 /* The following page contains abstract data `bundle states' which are
6067 used for bundling insns (inserting nops and template generation). */
6069 /* The following describes state of insn bundling. */
6073 /* Unique bundle state number to identify them in the debugging
6076 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6077 /* number nops before and after the insn */
6078 short before_nops_num, after_nops_num;
6079 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6081 int cost; /* cost of the state in cycles */
6082 int accumulated_insns_num; /* number of all previous insns including
6083 nops. L is considered as 2 insns */
6084 int branch_deviation; /* deviation of previous branches from 3rd slots */
6085 struct bundle_state *next; /* next state with the same insn_num */
6086 struct bundle_state *originator; /* originator (previous insn state) */
6087 /* All bundle states are in the following chain. */
6088 struct bundle_state *allocated_states_chain;
6089 /* The DFA State after issuing the insn and the nops. */
6093 /* The following is map insn number to the corresponding bundle state. */
6095 static struct bundle_state **index_to_bundle_states;
6097 /* The unique number of next bundle state. */
6099 static int bundle_states_num;
6101 /* All allocated bundle states are in the following chain. */
6103 static struct bundle_state *allocated_bundle_states_chain;
6105 /* All allocated but not used bundle states are in the following
6108 static struct bundle_state *free_bundle_state_chain;
6111 /* The following function returns a free bundle state. */
6113 static struct bundle_state *
6114 get_free_bundle_state ()
6116 struct bundle_state *result;
6118 if (free_bundle_state_chain != NULL)
6120 result = free_bundle_state_chain;
6121 free_bundle_state_chain = result->next;
6125 result = xmalloc (sizeof (struct bundle_state));
6126 result->dfa_state = xmalloc (dfa_state_size);
6127 result->allocated_states_chain = allocated_bundle_states_chain;
6128 allocated_bundle_states_chain = result;
6130 result->unique_num = bundle_states_num++;
6135 /* The following function frees given bundle state. */
6138 free_bundle_state (state)
6139 struct bundle_state *state;
6141 state->next = free_bundle_state_chain;
6142 free_bundle_state_chain = state;
6145 /* Start work with abstract data `bundle states'. */
6148 initiate_bundle_states ()
6150 bundle_states_num = 0;
6151 free_bundle_state_chain = NULL;
6152 allocated_bundle_states_chain = NULL;
6155 /* Finish work with abstract data `bundle states'. */
6158 finish_bundle_states ()
6160 struct bundle_state *curr_state, *next_state;
6162 for (curr_state = allocated_bundle_states_chain;
6164 curr_state = next_state)
6166 next_state = curr_state->allocated_states_chain;
6167 free (curr_state->dfa_state);
6172 /* Hash table of the bundle states. The key is dfa_state and insn_num
6173 of the bundle states. */
6175 static htab_t bundle_state_table;
6177 /* The function returns hash of BUNDLE_STATE. */
6180 bundle_state_hash (bundle_state)
6181 const void *bundle_state;
6183 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6186 for (result = i = 0; i < dfa_state_size; i++)
6187 result += (((unsigned char *) state->dfa_state) [i]
6188 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6189 return result + state->insn_num;
6192 /* The function returns nonzero if the bundle state keys are equal. */
6195 bundle_state_eq_p (bundle_state_1, bundle_state_2)
6196 const void *bundle_state_1;
6197 const void *bundle_state_2;
6199 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6200 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6202 return (state1->insn_num == state2->insn_num
6203 && memcmp (state1->dfa_state, state2->dfa_state,
6204 dfa_state_size) == 0);
6207 /* The function inserts the BUNDLE_STATE into the hash table. The
6208 function returns nonzero if the bundle has been inserted into the
6209 table. The table contains the best bundle state with given key. */
6212 insert_bundle_state (bundle_state)
6213 struct bundle_state *bundle_state;
6217 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6218 if (*entry_ptr == NULL)
6220 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6221 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6222 *entry_ptr = (void *) bundle_state;
6225 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6226 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6227 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6228 > bundle_state->accumulated_insns_num
6229 || (((struct bundle_state *)
6230 *entry_ptr)->accumulated_insns_num
6231 == bundle_state->accumulated_insns_num
6232 && ((struct bundle_state *)
6233 *entry_ptr)->branch_deviation
6234 > bundle_state->branch_deviation))))
6237 struct bundle_state temp;
6239 temp = *(struct bundle_state *) *entry_ptr;
6240 *(struct bundle_state *) *entry_ptr = *bundle_state;
6241 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6242 *bundle_state = temp;
6247 /* Start work with the hash table. */
6250 initiate_bundle_state_table ()
6252 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6256 /* Finish work with the hash table. */
6259 finish_bundle_state_table ()
6261 htab_delete (bundle_state_table);
6266 /* The following variable is a insn `nop' used to check bundle states
6267 with different number of inserted nops. */
6269 static rtx ia64_nop;
6271 /* The following function tries to issue NOPS_NUM nops for the current
6272 state without advancing processor cycle. If it failed, the
6273 function returns FALSE and frees the current state. */
6276 try_issue_nops (curr_state, nops_num)
6277 struct bundle_state *curr_state;
6282 for (i = 0; i < nops_num; i++)
6283 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6285 free_bundle_state (curr_state);
6291 /* The following function tries to issue INSN for the current
6292 state without advancing processor cycle. If it failed, the
6293 function returns FALSE and frees the current state. */
6296 try_issue_insn (curr_state, insn)
6297 struct bundle_state *curr_state;
6300 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6302 free_bundle_state (curr_state);
6308 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6309 starting with ORIGINATOR without advancing processor cycle. If
6310 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6311 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6312 If it was successful, the function creates new bundle state and
6313 insert into the hash table and into `index_to_bundle_states'. */
6316 issue_nops_and_insn (originator, before_nops_num, insn, try_bundle_end_p,
6318 struct bundle_state *originator;
6319 int before_nops_num;
6321 int try_bundle_end_p, only_bundle_end_p;
6323 struct bundle_state *curr_state;
6325 curr_state = get_free_bundle_state ();
6326 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6327 curr_state->insn = insn;
6328 curr_state->insn_num = originator->insn_num + 1;
6329 curr_state->cost = originator->cost;
6330 curr_state->originator = originator;
6331 curr_state->before_nops_num = before_nops_num;
6332 curr_state->after_nops_num = 0;
6333 curr_state->accumulated_insns_num
6334 = originator->accumulated_insns_num + before_nops_num;
6335 curr_state->branch_deviation = originator->branch_deviation;
6336 if (insn == NULL_RTX)
6338 else if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6340 if (GET_MODE (insn) == TImode)
6342 if (!try_issue_nops (curr_state, before_nops_num))
6344 if (!try_issue_insn (curr_state, insn))
6346 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6347 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6348 && curr_state->accumulated_insns_num % 3 != 0)
6350 free_bundle_state (curr_state);
6354 else if (GET_MODE (insn) != TImode)
6356 if (!try_issue_nops (curr_state, before_nops_num))
6358 if (!try_issue_insn (curr_state, insn))
6360 curr_state->accumulated_insns_num++;
6361 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6362 || asm_noperands (PATTERN (insn)) >= 0)
6364 if (ia64_safe_type (insn) == TYPE_L)
6365 curr_state->accumulated_insns_num++;
6369 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6370 state_transition (curr_state->dfa_state, NULL);
6372 if (!try_issue_nops (curr_state, before_nops_num))
6374 if (!try_issue_insn (curr_state, insn))
6376 curr_state->accumulated_insns_num++;
6377 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6378 || asm_noperands (PATTERN (insn)) >= 0)
6380 /* Finish bundle containing asm insn. */
6381 curr_state->after_nops_num
6382 = 3 - curr_state->accumulated_insns_num % 3;
6383 curr_state->accumulated_insns_num
6384 += 3 - curr_state->accumulated_insns_num % 3;
6386 else if (ia64_safe_type (insn) == TYPE_L)
6387 curr_state->accumulated_insns_num++;
6389 if (ia64_safe_type (insn) == TYPE_B)
6390 curr_state->branch_deviation
6391 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6392 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6394 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6397 struct bundle_state *curr_state1;
6398 struct bundle_state *allocated_states_chain;
6400 curr_state1 = get_free_bundle_state ();
6401 dfa_state = curr_state1->dfa_state;
6402 allocated_states_chain = curr_state1->allocated_states_chain;
6403 *curr_state1 = *curr_state;
6404 curr_state1->dfa_state = dfa_state;
6405 curr_state1->allocated_states_chain = allocated_states_chain;
6406 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6408 curr_state = curr_state1;
6410 if (!try_issue_nops (curr_state,
6411 3 - curr_state->accumulated_insns_num % 3))
6413 curr_state->after_nops_num
6414 = 3 - curr_state->accumulated_insns_num % 3;
6415 curr_state->accumulated_insns_num
6416 += 3 - curr_state->accumulated_insns_num % 3;
6418 if (!insert_bundle_state (curr_state))
6419 free_bundle_state (curr_state);
6423 /* The following function returns position in the two window bundle
6430 if (cpu_unit_reservation_p (state, pos_6))
6432 else if (cpu_unit_reservation_p (state, pos_5))
6434 else if (cpu_unit_reservation_p (state, pos_4))
6436 else if (cpu_unit_reservation_p (state, pos_3))
6438 else if (cpu_unit_reservation_p (state, pos_2))
6440 else if (cpu_unit_reservation_p (state, pos_1))
6446 /* The function returns code of a possible template for given position
6447 and state. The function should be called only with 2 values of
6448 position equal to 3 or 6. */
6451 get_template (state, pos)
6458 if (cpu_unit_reservation_p (state, _0mii_))
6460 else if (cpu_unit_reservation_p (state, _0mmi_))
6462 else if (cpu_unit_reservation_p (state, _0mfi_))
6464 else if (cpu_unit_reservation_p (state, _0mmf_))
6466 else if (cpu_unit_reservation_p (state, _0bbb_))
6468 else if (cpu_unit_reservation_p (state, _0mbb_))
6470 else if (cpu_unit_reservation_p (state, _0mib_))
6472 else if (cpu_unit_reservation_p (state, _0mmb_))
6474 else if (cpu_unit_reservation_p (state, _0mfb_))
6476 else if (cpu_unit_reservation_p (state, _0mlx_))
6481 if (cpu_unit_reservation_p (state, _1mii_))
6483 else if (cpu_unit_reservation_p (state, _1mmi_))
6485 else if (cpu_unit_reservation_p (state, _1mfi_))
6487 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6489 else if (cpu_unit_reservation_p (state, _1bbb_))
6491 else if (cpu_unit_reservation_p (state, _1mbb_))
6493 else if (cpu_unit_reservation_p (state, _1mib_))
6495 else if (cpu_unit_reservation_p (state, _1mmb_))
6497 else if (cpu_unit_reservation_p (state, _1mfb_))
6499 else if (cpu_unit_reservation_p (state, _1mlx_))
6508 /* The following function returns an insn important for insn bundling
6509 followed by INSN and before TAIL. */
6512 get_next_important_insn (insn, tail)
6515 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6517 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6518 && GET_CODE (PATTERN (insn)) != USE
6519 && GET_CODE (PATTERN (insn)) != CLOBBER)
6524 /* The following function does insn bundling. Bundling algorithm is
6525 based on dynamic programming. It tries to insert different number of
6526 nop insns before/after the real insns. At the end of EBB, it chooses the
6527 best alternative and then, moving back in EBB, inserts templates for
6528 the best alternative. The algorithm is directed by information
6529 (changes of simulated processor cycle) created by the 2nd insn
6533 bundling (dump, verbose, prev_head_insn, tail)
6536 rtx prev_head_insn, tail;
6538 struct bundle_state *curr_state, *next_state, *best_state;
6539 rtx insn, next_insn;
6541 int i, bundle_end_p, only_bundle_end_p, asm_p;
6542 int pos, max_pos, template0, template1;
6545 enum attr_type type;
6548 for (insn = NEXT_INSN (prev_head_insn);
6549 insn && insn != tail;
6550 insn = NEXT_INSN (insn))
6556 dfa_clean_insn_cache ();
6557 initiate_bundle_state_table ();
6558 index_to_bundle_states = xmalloc ((insn_num + 2)
6559 * sizeof (struct bundle_state *));
6560 /* First (forward) pass -- generates states. */
6561 curr_state = get_free_bundle_state ();
6562 curr_state->insn = NULL;
6563 curr_state->before_nops_num = 0;
6564 curr_state->after_nops_num = 0;
6565 curr_state->insn_num = 0;
6566 curr_state->cost = 0;
6567 curr_state->accumulated_insns_num = 0;
6568 curr_state->branch_deviation = 0;
6569 curr_state->next = NULL;
6570 curr_state->originator = NULL;
6571 state_reset (curr_state->dfa_state);
6572 index_to_bundle_states [0] = curr_state;
6574 for (insn = NEXT_INSN (prev_head_insn);
6576 insn = NEXT_INSN (insn))
6578 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6579 || GET_CODE (PATTERN (insn)) == USE
6580 || GET_CODE (PATTERN (insn)) == CLOBBER)
6581 && GET_MODE (insn) == TImode)
6583 PUT_MODE (insn, VOIDmode);
6584 for (next_insn = NEXT_INSN (insn);
6586 next_insn = NEXT_INSN (next_insn))
6587 if (INSN_P (next_insn)
6588 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6589 && GET_CODE (PATTERN (next_insn)) != USE
6590 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6592 PUT_MODE (next_insn, TImode);
6596 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6601 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6602 || GET_CODE (PATTERN (insn)) == USE
6603 || GET_CODE (PATTERN (insn)) == CLOBBER)
6605 type = ia64_safe_type (insn);
6606 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6608 index_to_bundle_states [insn_num] = NULL;
6609 for (curr_state = index_to_bundle_states [insn_num - 1];
6611 curr_state = next_state)
6613 pos = curr_state->accumulated_insns_num % 3;
6614 next_state = curr_state->next;
6615 /* Finish the current bundle in order to start a subsequent
6616 asm insn in a new bundle. */
6618 = (next_insn != NULL_RTX
6619 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6620 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6622 = (only_bundle_end_p || next_insn == NULL_RTX
6623 || (GET_MODE (next_insn) == TImode
6624 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6625 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6627 /* We need to insert 2 Nops for cases like M_MII. */
6628 || (type == TYPE_M && ia64_tune == PROCESSOR_ITANIUM
6629 && !bundle_end_p && pos == 1))
6630 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6632 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6634 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6637 if (index_to_bundle_states [insn_num] == NULL)
6639 for (curr_state = index_to_bundle_states [insn_num];
6641 curr_state = curr_state->next)
6642 if (verbose >= 2 && dump)
6646 unsigned short one_automaton_state;
6647 unsigned short oneb_automaton_state;
6648 unsigned short two_automaton_state;
6649 unsigned short twob_automaton_state;
6654 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6655 curr_state->unique_num,
6656 (curr_state->originator == NULL
6657 ? -1 : curr_state->originator->unique_num),
6659 curr_state->before_nops_num, curr_state->after_nops_num,
6660 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6661 (ia64_tune == PROCESSOR_ITANIUM
6662 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6663 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6667 if (index_to_bundle_states [insn_num] == NULL)
6669 /* Finding state with a minimal cost: */
6671 for (curr_state = index_to_bundle_states [insn_num];
6673 curr_state = curr_state->next)
6674 if (curr_state->accumulated_insns_num % 3 == 0
6675 && (best_state == NULL || best_state->cost > curr_state->cost
6676 || (best_state->cost == curr_state->cost
6677 && (curr_state->accumulated_insns_num
6678 < best_state->accumulated_insns_num
6679 || (curr_state->accumulated_insns_num
6680 == best_state->accumulated_insns_num
6681 && curr_state->branch_deviation
6682 < best_state->branch_deviation)))))
6683 best_state = curr_state;
6684 /* Second (backward) pass: adding nops and templates: */
6685 insn_num = best_state->before_nops_num;
6686 template0 = template1 = -1;
6687 for (curr_state = best_state;
6688 curr_state->originator != NULL;
6689 curr_state = curr_state->originator)
6691 insn = curr_state->insn;
6692 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
6693 || asm_noperands (PATTERN (insn)) >= 0);
6695 if (verbose >= 2 && dump)
6699 unsigned short one_automaton_state;
6700 unsigned short oneb_automaton_state;
6701 unsigned short two_automaton_state;
6702 unsigned short twob_automaton_state;
6707 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6708 curr_state->unique_num,
6709 (curr_state->originator == NULL
6710 ? -1 : curr_state->originator->unique_num),
6712 curr_state->before_nops_num, curr_state->after_nops_num,
6713 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6714 (ia64_tune == PROCESSOR_ITANIUM
6715 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6716 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6719 max_pos = get_max_pos (curr_state->dfa_state);
6720 if (max_pos == 6 || (max_pos == 3 && template0 < 0))
6724 template0 = get_template (curr_state->dfa_state, 3);
6727 template1 = get_template (curr_state->dfa_state, 3);
6728 template0 = get_template (curr_state->dfa_state, 6);
6731 if (max_pos > 3 && template1 < 0)
6735 template1 = get_template (curr_state->dfa_state, 3);
6739 for (i = 0; i < curr_state->after_nops_num; i++)
6742 emit_insn_after (nop, insn);
6750 b = gen_bundle_selector (GEN_INT (template0));
6751 ia64_emit_insn_before (b, nop);
6752 template0 = template1;
6756 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6757 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6758 && asm_noperands (PATTERN (insn)) < 0)
6760 if (ia64_safe_type (insn) == TYPE_L)
6765 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6766 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6767 && asm_noperands (PATTERN (insn)) < 0)
6771 b = gen_bundle_selector (GEN_INT (template0));
6772 ia64_emit_insn_before (b, insn);
6773 b = PREV_INSN (insn);
6775 template0 = template1;
6778 for (i = 0; i < curr_state->before_nops_num; i++)
6781 ia64_emit_insn_before (nop, insn);
6782 nop = PREV_INSN (insn);
6791 b = gen_bundle_selector (GEN_INT (template0));
6792 ia64_emit_insn_before (b, insn);
6793 b = PREV_INSN (insn);
6795 template0 = template1;
6800 if (ia64_tune == PROCESSOR_ITANIUM)
6801 /* Insert additional cycles for MM-insns: */
6802 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6807 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6808 || GET_CODE (PATTERN (insn)) == USE
6809 || GET_CODE (PATTERN (insn)) == CLOBBER)
6811 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6812 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
6818 last = prev_active_insn (insn);
6819 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
6821 last = prev_active_insn (last);
6823 for (;; last = prev_active_insn (last))
6824 if (recog_memoized (last) == CODE_FOR_bundle_selector)
6826 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
6829 = gen_bundle_selector (GEN_INT (2)); /* -> MFI */
6832 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6834 if ((pred_stop_p && n == 0) || n > 2
6835 || (template0 == 9 && n != 0))
6837 for (j = 3 - n; j > 0; j --)
6838 ia64_emit_insn_before (gen_nop (), insn);
6839 add_cycles [INSN_UID (insn)]--;
6840 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
6841 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6844 add_cycles [INSN_UID (insn)]--;
6845 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
6847 /* Insert .MII bundle. */
6848 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
6850 ia64_emit_insn_before (gen_nop (), insn);
6851 ia64_emit_insn_before (gen_nop (), insn);
6854 ia64_emit_insn_before
6855 (gen_insn_group_barrier (GEN_INT (3)), insn);
6858 ia64_emit_insn_before (gen_nop (), insn);
6859 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6862 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
6864 for (j = n; j > 0; j --)
6865 ia64_emit_insn_before (gen_nop (), insn);
6867 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6871 free (index_to_bundle_states);
6872 finish_bundle_state_table ();
6874 dfa_clean_insn_cache ();
6877 /* The following function is called at the end of scheduling BB or
6878 EBB. After reload, it inserts stop bits and does insn bundling. */
6881 ia64_sched_finish (dump, sched_verbose)
6886 fprintf (dump, "// Finishing schedule.\n");
6887 if (!reload_completed)
6889 if (reload_completed)
6891 final_emit_insn_group_barriers (dump);
6892 bundling (dump, sched_verbose, current_sched_info->prev_head,
6893 current_sched_info->next_tail);
6894 if (sched_verbose && dump)
6895 fprintf (dump, "// finishing %d-%d\n",
6896 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
6897 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
6903 /* The following function inserts stop bits in scheduled BB or EBB. */
6906 final_emit_insn_group_barriers (dump)
6907 FILE *dump ATTRIBUTE_UNUSED;
6910 int need_barrier_p = 0;
6911 rtx prev_insn = NULL_RTX;
6913 init_insn_group_barriers ();
6915 for (insn = NEXT_INSN (current_sched_info->prev_head);
6916 insn != current_sched_info->next_tail;
6917 insn = NEXT_INSN (insn))
6919 if (GET_CODE (insn) == BARRIER)
6921 rtx last = prev_active_insn (insn);
6925 if (GET_CODE (last) == JUMP_INSN
6926 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6927 last = prev_active_insn (last);
6928 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6929 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6931 init_insn_group_barriers ();
6933 prev_insn = NULL_RTX;
6935 else if (INSN_P (insn))
6937 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6939 init_insn_group_barriers ();
6941 prev_insn = NULL_RTX;
6943 else if (need_barrier_p || group_barrier_needed_p (insn))
6945 if (TARGET_EARLY_STOP_BITS)
6950 last != current_sched_info->prev_head;
6951 last = PREV_INSN (last))
6952 if (INSN_P (last) && GET_MODE (last) == TImode
6953 && stops_p [INSN_UID (last)])
6955 if (last == current_sched_info->prev_head)
6957 last = prev_active_insn (last);
6959 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
6960 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
6962 init_insn_group_barriers ();
6963 for (last = NEXT_INSN (last);
6965 last = NEXT_INSN (last))
6967 group_barrier_needed_p (last);
6971 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6973 init_insn_group_barriers ();
6975 group_barrier_needed_p (insn);
6976 prev_insn = NULL_RTX;
6978 else if (recog_memoized (insn) >= 0)
6980 need_barrier_p = (GET_CODE (insn) == CALL_INSN
6981 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6982 || asm_noperands (PATTERN (insn)) >= 0);
6989 /* If the following function returns TRUE, we will use the the DFA
6993 ia64_use_dfa_pipeline_interface ()
6998 /* If the following function returns TRUE, we will use the the DFA
7002 ia64_first_cycle_multipass_dfa_lookahead ()
7004 return (reload_completed ? 6 : 4);
7007 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7010 ia64_init_dfa_pre_cycle_insn ()
7012 if (temp_dfa_state == NULL)
7014 dfa_state_size = state_size ();
7015 temp_dfa_state = xmalloc (dfa_state_size);
7016 prev_cycle_state = xmalloc (dfa_state_size);
7018 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7019 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7020 recog_memoized (dfa_pre_cycle_insn);
7021 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7022 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7023 recog_memoized (dfa_stop_insn);
7026 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7027 used by the DFA insn scheduler. */
7030 ia64_dfa_pre_cycle_insn ()
7032 return dfa_pre_cycle_insn;
7035 /* The following function returns TRUE if PRODUCER (of type ilog or
7036 ld) produces address for CONSUMER (of type st or stf). */
7039 ia64_st_address_bypass_p (producer, consumer)
7045 if (producer == NULL_RTX || consumer == NULL_RTX)
7047 dest = ia64_single_set (producer);
7048 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7049 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7051 if (GET_CODE (reg) == SUBREG)
7052 reg = SUBREG_REG (reg);
7053 dest = ia64_single_set (consumer);
7054 if (dest == NULL_RTX || (mem = SET_DEST (dest)) == NULL_RTX
7055 || GET_CODE (mem) != MEM)
7057 return reg_mentioned_p (reg, mem);
7060 /* The following function returns TRUE if PRODUCER (of type ilog or
7061 ld) produces address for CONSUMER (of type ld or fld). */
7064 ia64_ld_address_bypass_p (producer, consumer)
7068 rtx dest, src, reg, mem;
7070 if (producer == NULL_RTX || consumer == NULL_RTX)
7072 dest = ia64_single_set (producer);
7073 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7074 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7076 if (GET_CODE (reg) == SUBREG)
7077 reg = SUBREG_REG (reg);
7078 src = ia64_single_set (consumer);
7079 if (src == NULL_RTX || (mem = SET_SRC (src)) == NULL_RTX)
7081 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7082 mem = XVECEXP (mem, 0, 0);
7083 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7084 mem = XEXP (mem, 0);
7086 /* Note that LO_SUM is used for GOT loads. */
7087 if (GET_CODE (mem) != LO_SUM && GET_CODE (mem) != MEM)
7090 return reg_mentioned_p (reg, mem);
7093 /* The following function returns TRUE if INSN produces address for a
7094 load/store insn. We will place such insns into M slot because it
7095 decreases its latency time. */
7098 ia64_produce_address_p (insn)
7105 /* Emit pseudo-ops for the assembler to describe predicate relations.
7106 At present this assumes that we only consider predicate pairs to
7107 be mutex, and that the assembler can deduce proper values from
7108 straight-line code. */
7111 emit_predicate_relation_info ()
7115 FOR_EACH_BB_REVERSE (bb)
7118 rtx head = bb->head;
7120 /* We only need such notes at code labels. */
7121 if (GET_CODE (head) != CODE_LABEL)
7123 if (GET_CODE (NEXT_INSN (head)) == NOTE
7124 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7125 head = NEXT_INSN (head);
7127 for (r = PR_REG (0); r < PR_REG (64); r += 2)
7128 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7130 rtx p = gen_rtx_REG (BImode, r);
7131 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7132 if (head == bb->end)
7138 /* Look for conditional calls that do not return, and protect predicate
7139 relations around them. Otherwise the assembler will assume the call
7140 returns, and complain about uses of call-clobbered predicates after
7142 FOR_EACH_BB_REVERSE (bb)
7144 rtx insn = bb->head;
7148 if (GET_CODE (insn) == CALL_INSN
7149 && GET_CODE (PATTERN (insn)) == COND_EXEC
7150 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7152 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7153 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7154 if (bb->head == insn)
7156 if (bb->end == insn)
7160 if (insn == bb->end)
7162 insn = NEXT_INSN (insn);
7167 /* Perform machine dependent operations on the rtl chain INSNS. */
7173 /* We are freeing block_for_insn in the toplev to keep compatibility
7174 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7175 compute_bb_for_insn ();
7177 /* If optimizing, we'll have split before scheduling. */
7179 split_all_insns (0);
7181 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7182 non-optimizing bootstrap. */
7183 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7185 if (ia64_flag_schedule_insns2)
7187 timevar_push (TV_SCHED2);
7188 ia64_final_schedule = 1;
7190 initiate_bundle_states ();
7191 ia64_nop = make_insn_raw (gen_nop ());
7192 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7193 recog_memoized (ia64_nop);
7194 clocks_length = get_max_uid () + 1;
7195 stops_p = (char *) xmalloc (clocks_length);
7196 memset (stops_p, 0, clocks_length);
7197 if (ia64_tune == PROCESSOR_ITANIUM)
7199 clocks = (int *) xmalloc (clocks_length * sizeof (int));
7200 memset (clocks, 0, clocks_length * sizeof (int));
7201 add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
7202 memset (add_cycles, 0, clocks_length * sizeof (int));
7204 if (ia64_tune == PROCESSOR_ITANIUM2)
7206 pos_1 = get_cpu_unit_code ("2_1");
7207 pos_2 = get_cpu_unit_code ("2_2");
7208 pos_3 = get_cpu_unit_code ("2_3");
7209 pos_4 = get_cpu_unit_code ("2_4");
7210 pos_5 = get_cpu_unit_code ("2_5");
7211 pos_6 = get_cpu_unit_code ("2_6");
7212 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7213 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7214 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7215 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7216 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7217 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7218 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7219 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7220 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7221 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7222 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7223 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7224 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7225 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7226 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7227 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7228 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7229 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7230 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7231 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7235 pos_1 = get_cpu_unit_code ("1_1");
7236 pos_2 = get_cpu_unit_code ("1_2");
7237 pos_3 = get_cpu_unit_code ("1_3");
7238 pos_4 = get_cpu_unit_code ("1_4");
7239 pos_5 = get_cpu_unit_code ("1_5");
7240 pos_6 = get_cpu_unit_code ("1_6");
7241 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7242 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7243 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7244 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7245 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7246 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7247 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7248 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7249 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7250 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7251 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7252 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7253 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7254 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7255 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7256 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7257 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7258 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7259 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7260 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7262 schedule_ebbs (rtl_dump_file);
7263 finish_bundle_states ();
7264 if (ia64_tune == PROCESSOR_ITANIUM)
7270 emit_insn_group_barriers (rtl_dump_file, insns);
7272 ia64_final_schedule = 0;
7273 timevar_pop (TV_SCHED2);
7276 emit_all_insn_group_barriers (rtl_dump_file, insns);
7278 /* A call must not be the last instruction in a function, so that the
7279 return address is still within the function, so that unwinding works
7280 properly. Note that IA-64 differs from dwarf2 on this point. */
7281 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7286 insn = get_last_insn ();
7287 if (! INSN_P (insn))
7288 insn = prev_active_insn (insn);
7289 if (GET_CODE (insn) == INSN
7290 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7291 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7294 insn = prev_active_insn (insn);
7296 if (GET_CODE (insn) == CALL_INSN)
7299 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7300 emit_insn (gen_break_f ());
7301 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7306 emit_predicate_relation_info ();
7309 /* Return true if REGNO is used by the epilogue. */
7312 ia64_epilogue_uses (regno)
7318 /* When a function makes a call through a function descriptor, we
7319 will write a (potentially) new value to "gp". After returning
7320 from such a call, we need to make sure the function restores the
7321 original gp-value, even if the function itself does not use the
7323 return (TARGET_CONST_GP && !(TARGET_AUTO_PIC || TARGET_NO_PIC));
7325 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7326 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7327 /* For functions defined with the syscall_linkage attribute, all
7328 input registers are marked as live at all function exits. This
7329 prevents the register allocator from using the input registers,
7330 which in turn makes it possible to restart a system call after
7331 an interrupt without having to save/restore the input registers.
7332 This also prevents kernel data from leaking to application code. */
7333 return lookup_attribute ("syscall_linkage",
7334 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7337 /* Conditional return patterns can't represent the use of `b0' as
7338 the return address, so we force the value live this way. */
7342 /* Likewise for ar.pfs, which is used by br.ret. */
7350 /* Return true if REGNO is used by the frame unwinder. */
7353 ia64_eh_uses (regno)
7356 if (! reload_completed)
7359 if (current_frame_info.reg_save_b0
7360 && regno == current_frame_info.reg_save_b0)
7362 if (current_frame_info.reg_save_pr
7363 && regno == current_frame_info.reg_save_pr)
7365 if (current_frame_info.reg_save_ar_pfs
7366 && regno == current_frame_info.reg_save_ar_pfs)
7368 if (current_frame_info.reg_save_ar_unat
7369 && regno == current_frame_info.reg_save_ar_unat)
7371 if (current_frame_info.reg_save_ar_lc
7372 && regno == current_frame_info.reg_save_ar_lc)
7378 /* Return true if this goes in small data/bss. */
7380 /* ??? We could also support own long data here. Generating movl/add/ld8
7381 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7382 code faster because there is one less load. This also includes incomplete
7383 types which can't go in sdata/sbss. */
7386 ia64_in_small_data_p (exp)
7389 if (TARGET_NO_SDATA)
7392 /* We want to merge strings, so we never consider them small data. */
7393 if (TREE_CODE (exp) == STRING_CST)
7396 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7398 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7399 if (strcmp (section, ".sdata") == 0
7400 || strcmp (section, ".sbss") == 0)
7405 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7407 /* If this is an incomplete type with size 0, then we can't put it
7408 in sdata because it might be too big when completed. */
7409 if (size > 0 && size <= ia64_section_threshold)
7416 /* Output assembly directives for prologue regions. */
7418 /* The current basic block number. */
7420 static bool last_block;
7422 /* True if we need a copy_state command at the start of the next block. */
7424 static bool need_copy_state;
7426 /* The function emits unwind directives for the start of an epilogue. */
7431 /* If this isn't the last block of the function, then we need to label the
7432 current state, and copy it back in at the start of the next block. */
7436 fprintf (asm_out_file, "\t.label_state 1\n");
7437 need_copy_state = true;
7440 fprintf (asm_out_file, "\t.restore sp\n");
7443 /* This function processes a SET pattern looking for specific patterns
7444 which result in emitting an assembly directive required for unwinding. */
7447 process_set (asm_out_file, pat)
7451 rtx src = SET_SRC (pat);
7452 rtx dest = SET_DEST (pat);
7453 int src_regno, dest_regno;
7455 /* Look for the ALLOC insn. */
7456 if (GET_CODE (src) == UNSPEC_VOLATILE
7457 && XINT (src, 1) == UNSPECV_ALLOC
7458 && GET_CODE (dest) == REG)
7460 dest_regno = REGNO (dest);
7462 /* If this isn't the final destination for ar.pfs, the alloc
7463 shouldn't have been marked frame related. */
7464 if (dest_regno != current_frame_info.reg_save_ar_pfs)
7467 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7468 ia64_dbx_register_number (dest_regno));
7472 /* Look for SP = .... */
7473 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7475 if (GET_CODE (src) == PLUS)
7477 rtx op0 = XEXP (src, 0);
7478 rtx op1 = XEXP (src, 1);
7479 if (op0 == dest && GET_CODE (op1) == CONST_INT)
7481 if (INTVAL (op1) < 0)
7483 fputs ("\t.fframe ", asm_out_file);
7484 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC,
7486 fputc ('\n', asm_out_file);
7489 process_epilogue ();
7494 else if (GET_CODE (src) == REG
7495 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
7496 process_epilogue ();
7503 /* Register move we need to look at. */
7504 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7506 src_regno = REGNO (src);
7507 dest_regno = REGNO (dest);
7512 /* Saving return address pointer. */
7513 if (dest_regno != current_frame_info.reg_save_b0)
7515 fprintf (asm_out_file, "\t.save rp, r%d\n",
7516 ia64_dbx_register_number (dest_regno));
7520 if (dest_regno != current_frame_info.reg_save_pr)
7522 fprintf (asm_out_file, "\t.save pr, r%d\n",
7523 ia64_dbx_register_number (dest_regno));
7526 case AR_UNAT_REGNUM:
7527 if (dest_regno != current_frame_info.reg_save_ar_unat)
7529 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7530 ia64_dbx_register_number (dest_regno));
7534 if (dest_regno != current_frame_info.reg_save_ar_lc)
7536 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7537 ia64_dbx_register_number (dest_regno));
7540 case STACK_POINTER_REGNUM:
7541 if (dest_regno != HARD_FRAME_POINTER_REGNUM
7542 || ! frame_pointer_needed)
7544 fprintf (asm_out_file, "\t.vframe r%d\n",
7545 ia64_dbx_register_number (dest_regno));
7549 /* Everything else should indicate being stored to memory. */
7554 /* Memory store we need to look at. */
7555 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7561 if (GET_CODE (XEXP (dest, 0)) == REG)
7563 base = XEXP (dest, 0);
7566 else if (GET_CODE (XEXP (dest, 0)) == PLUS
7567 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
7569 base = XEXP (XEXP (dest, 0), 0);
7570 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7575 if (base == hard_frame_pointer_rtx)
7577 saveop = ".savepsp";
7580 else if (base == stack_pointer_rtx)
7585 src_regno = REGNO (src);
7589 if (current_frame_info.reg_save_b0 != 0)
7591 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7595 if (current_frame_info.reg_save_pr != 0)
7597 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7601 if (current_frame_info.reg_save_ar_lc != 0)
7603 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7607 if (current_frame_info.reg_save_ar_pfs != 0)
7609 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7612 case AR_UNAT_REGNUM:
7613 if (current_frame_info.reg_save_ar_unat != 0)
7615 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
7622 fprintf (asm_out_file, "\t.save.g 0x%x\n",
7623 1 << (src_regno - GR_REG (4)));
7631 fprintf (asm_out_file, "\t.save.b 0x%x\n",
7632 1 << (src_regno - BR_REG (1)));
7639 fprintf (asm_out_file, "\t.save.f 0x%x\n",
7640 1 << (src_regno - FR_REG (2)));
7643 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7644 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7645 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7646 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7647 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
7648 1 << (src_regno - FR_REG (12)));
7660 /* This function looks at a single insn and emits any directives
7661 required to unwind this insn. */
7663 process_for_unwind_directive (asm_out_file, insn)
7667 if (flag_unwind_tables
7668 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7672 if (GET_CODE (insn) == NOTE
7673 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
7675 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
7677 /* Restore unwind state from immediately before the epilogue. */
7678 if (need_copy_state)
7680 fprintf (asm_out_file, "\t.body\n");
7681 fprintf (asm_out_file, "\t.copy_state 1\n");
7682 need_copy_state = false;
7686 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
7689 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
7691 pat = XEXP (pat, 0);
7693 pat = PATTERN (insn);
7695 switch (GET_CODE (pat))
7698 process_set (asm_out_file, pat);
7704 int limit = XVECLEN (pat, 0);
7705 for (par_index = 0; par_index < limit; par_index++)
7707 rtx x = XVECEXP (pat, 0, par_index);
7708 if (GET_CODE (x) == SET)
7709 process_set (asm_out_file, x);
7722 ia64_init_builtins ()
7724 tree psi_type_node = build_pointer_type (integer_type_node);
7725 tree pdi_type_node = build_pointer_type (long_integer_type_node);
7727 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7728 tree si_ftype_psi_si_si
7729 = build_function_type_list (integer_type_node,
7730 psi_type_node, integer_type_node,
7731 integer_type_node, NULL_TREE);
7733 /* __sync_val_compare_and_swap_di */
7734 tree di_ftype_pdi_di_di
7735 = build_function_type_list (long_integer_type_node,
7736 pdi_type_node, long_integer_type_node,
7737 long_integer_type_node, NULL_TREE);
7738 /* __sync_bool_compare_and_swap_di */
7739 tree si_ftype_pdi_di_di
7740 = build_function_type_list (integer_type_node,
7741 pdi_type_node, long_integer_type_node,
7742 long_integer_type_node, NULL_TREE);
7743 /* __sync_synchronize */
7744 tree void_ftype_void
7745 = build_function_type (void_type_node, void_list_node);
7747 /* __sync_lock_test_and_set_si */
7748 tree si_ftype_psi_si
7749 = build_function_type_list (integer_type_node,
7750 psi_type_node, integer_type_node, NULL_TREE);
7752 /* __sync_lock_test_and_set_di */
7753 tree di_ftype_pdi_di
7754 = build_function_type_list (long_integer_type_node,
7755 pdi_type_node, long_integer_type_node,
7758 /* __sync_lock_release_si */
7760 = build_function_type_list (void_type_node, psi_type_node, NULL_TREE);
7762 /* __sync_lock_release_di */
7764 = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
7766 #define def_builtin(name, type, code) \
7767 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
7769 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
7770 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
7771 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
7772 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
7773 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
7774 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
7775 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di,
7776 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
7778 def_builtin ("__sync_synchronize", void_ftype_void,
7779 IA64_BUILTIN_SYNCHRONIZE);
7781 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
7782 IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
7783 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
7784 IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
7785 def_builtin ("__sync_lock_release_si", void_ftype_psi,
7786 IA64_BUILTIN_LOCK_RELEASE_SI);
7787 def_builtin ("__sync_lock_release_di", void_ftype_pdi,
7788 IA64_BUILTIN_LOCK_RELEASE_DI);
7790 def_builtin ("__builtin_ia64_bsp",
7791 build_function_type (ptr_type_node, void_list_node),
7794 def_builtin ("__builtin_ia64_flushrs",
7795 build_function_type (void_type_node, void_list_node),
7796 IA64_BUILTIN_FLUSHRS);
7798 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
7799 IA64_BUILTIN_FETCH_AND_ADD_SI);
7800 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
7801 IA64_BUILTIN_FETCH_AND_SUB_SI);
7802 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
7803 IA64_BUILTIN_FETCH_AND_OR_SI);
7804 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
7805 IA64_BUILTIN_FETCH_AND_AND_SI);
7806 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
7807 IA64_BUILTIN_FETCH_AND_XOR_SI);
7808 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
7809 IA64_BUILTIN_FETCH_AND_NAND_SI);
7811 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
7812 IA64_BUILTIN_ADD_AND_FETCH_SI);
7813 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
7814 IA64_BUILTIN_SUB_AND_FETCH_SI);
7815 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
7816 IA64_BUILTIN_OR_AND_FETCH_SI);
7817 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
7818 IA64_BUILTIN_AND_AND_FETCH_SI);
7819 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
7820 IA64_BUILTIN_XOR_AND_FETCH_SI);
7821 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
7822 IA64_BUILTIN_NAND_AND_FETCH_SI);
7824 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
7825 IA64_BUILTIN_FETCH_AND_ADD_DI);
7826 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
7827 IA64_BUILTIN_FETCH_AND_SUB_DI);
7828 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
7829 IA64_BUILTIN_FETCH_AND_OR_DI);
7830 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
7831 IA64_BUILTIN_FETCH_AND_AND_DI);
7832 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
7833 IA64_BUILTIN_FETCH_AND_XOR_DI);
7834 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
7835 IA64_BUILTIN_FETCH_AND_NAND_DI);
7837 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
7838 IA64_BUILTIN_ADD_AND_FETCH_DI);
7839 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
7840 IA64_BUILTIN_SUB_AND_FETCH_DI);
7841 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
7842 IA64_BUILTIN_OR_AND_FETCH_DI);
7843 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
7844 IA64_BUILTIN_AND_AND_FETCH_DI);
7845 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
7846 IA64_BUILTIN_XOR_AND_FETCH_DI);
7847 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
7848 IA64_BUILTIN_NAND_AND_FETCH_DI);
7853 /* Expand fetch_and_op intrinsics. The basic code sequence is:
7861 cmpxchgsz.acq tmp = [ptr], tmp
7862 } while (tmp != ret)
7866 ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
7868 enum machine_mode mode;
7872 rtx ret, label, tmp, ccv, insn, mem, value;
7875 arg0 = TREE_VALUE (arglist);
7876 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7877 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
7878 #ifdef POINTERS_EXTEND_UNSIGNED
7879 if (GET_MODE(mem) != Pmode)
7880 mem = convert_memory_address (Pmode, mem);
7882 value = expand_expr (arg1, NULL_RTX, mode, 0);
7884 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
7885 MEM_VOLATILE_P (mem) = 1;
7887 if (target && register_operand (target, mode))
7890 ret = gen_reg_rtx (mode);
7892 emit_insn (gen_mf ());
7894 /* Special case for fetchadd instructions. */
7895 if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
7898 insn = gen_fetchadd_acq_si (ret, mem, value);
7900 insn = gen_fetchadd_acq_di (ret, mem, value);
7905 tmp = gen_reg_rtx (mode);
7906 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
7907 emit_move_insn (tmp, mem);
7909 label = gen_label_rtx ();
7911 emit_move_insn (ret, tmp);
7912 emit_move_insn (ccv, tmp);
7914 /* Perform the specific operation. Special case NAND by noticing
7915 one_cmpl_optab instead. */
7916 if (binoptab == one_cmpl_optab)
7918 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
7919 binoptab = and_optab;
7921 tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
7924 insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
7926 insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
7929 emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, label);
7934 /* Expand op_and_fetch intrinsics. The basic code sequence is:
7941 ret = tmp <op> value;
7942 cmpxchgsz.acq tmp = [ptr], ret
7943 } while (tmp != old)
7947 ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
7949 enum machine_mode mode;
7953 rtx old, label, tmp, ret, ccv, insn, mem, value;
7956 arg0 = TREE_VALUE (arglist);
7957 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7958 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
7959 #ifdef POINTERS_EXTEND_UNSIGNED
7960 if (GET_MODE(mem) != Pmode)
7961 mem = convert_memory_address (Pmode, mem);
7964 value = expand_expr (arg1, NULL_RTX, mode, 0);
7966 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
7967 MEM_VOLATILE_P (mem) = 1;
7969 if (target && ! register_operand (target, mode))
7972 emit_insn (gen_mf ());
7973 tmp = gen_reg_rtx (mode);
7974 old = gen_reg_rtx (mode);
7975 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
7977 emit_move_insn (tmp, mem);
7979 label = gen_label_rtx ();
7981 emit_move_insn (old, tmp);
7982 emit_move_insn (ccv, tmp);
7984 /* Perform the specific operation. Special case NAND by noticing
7985 one_cmpl_optab instead. */
7986 if (binoptab == one_cmpl_optab)
7988 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
7989 binoptab = and_optab;
7991 ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
7994 insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
7996 insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
7999 emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, label);
8004 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8008 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8011 For bool_ it's the same except return ret == oldval.
8015 ia64_expand_compare_and_swap (mode, boolp, arglist, target)
8016 enum machine_mode mode;
8021 tree arg0, arg1, arg2;
8022 rtx mem, old, new, ccv, tmp, insn;
8024 arg0 = TREE_VALUE (arglist);
8025 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8026 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8027 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8028 old = expand_expr (arg1, NULL_RTX, mode, 0);
8029 new = expand_expr (arg2, NULL_RTX, mode, 0);
8031 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8032 MEM_VOLATILE_P (mem) = 1;
8034 if (! register_operand (old, mode))
8035 old = copy_to_mode_reg (mode, old);
8036 if (! register_operand (new, mode))
8037 new = copy_to_mode_reg (mode, new);
8039 if (! boolp && target && register_operand (target, mode))
8042 tmp = gen_reg_rtx (mode);
8044 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8046 emit_move_insn (ccv, old);
8049 rtx ccvtmp = gen_reg_rtx (DImode);
8050 emit_insn (gen_zero_extendsidi2 (ccvtmp, old));
8051 emit_move_insn (ccv, ccvtmp);
8053 emit_insn (gen_mf ());
8055 insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
8057 insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
8063 target = gen_reg_rtx (mode);
8064 return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
8070 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8073 ia64_expand_lock_test_and_set (mode, arglist, target)
8074 enum machine_mode mode;
8079 rtx mem, new, ret, insn;
8081 arg0 = TREE_VALUE (arglist);
8082 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8083 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8084 new = expand_expr (arg1, NULL_RTX, mode, 0);
8086 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8087 MEM_VOLATILE_P (mem) = 1;
8088 if (! register_operand (new, mode))
8089 new = copy_to_mode_reg (mode, new);
8091 if (target && register_operand (target, mode))
8094 ret = gen_reg_rtx (mode);
8097 insn = gen_xchgsi (ret, mem, new);
8099 insn = gen_xchgdi (ret, mem, new);
8105 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8108 ia64_expand_lock_release (mode, arglist, target)
8109 enum machine_mode mode;
8111 rtx target ATTRIBUTE_UNUSED;
8116 arg0 = TREE_VALUE (arglist);
8117 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8119 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8120 MEM_VOLATILE_P (mem) = 1;
8122 emit_move_insn (mem, const0_rtx);
8128 ia64_expand_builtin (exp, target, subtarget, mode, ignore)
8131 rtx subtarget ATTRIBUTE_UNUSED;
8132 enum machine_mode mode ATTRIBUTE_UNUSED;
8133 int ignore ATTRIBUTE_UNUSED;
8135 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8136 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8137 tree arglist = TREE_OPERAND (exp, 1);
8141 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8142 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8143 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8144 case IA64_BUILTIN_LOCK_RELEASE_SI:
8145 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8146 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8147 case IA64_BUILTIN_FETCH_AND_OR_SI:
8148 case IA64_BUILTIN_FETCH_AND_AND_SI:
8149 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8150 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8151 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8152 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8153 case IA64_BUILTIN_OR_AND_FETCH_SI:
8154 case IA64_BUILTIN_AND_AND_FETCH_SI:
8155 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8156 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8160 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8161 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8162 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8163 case IA64_BUILTIN_LOCK_RELEASE_DI:
8164 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8165 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8166 case IA64_BUILTIN_FETCH_AND_OR_DI:
8167 case IA64_BUILTIN_FETCH_AND_AND_DI:
8168 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8169 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8170 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8171 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8172 case IA64_BUILTIN_OR_AND_FETCH_DI:
8173 case IA64_BUILTIN_AND_AND_FETCH_DI:
8174 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8175 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8185 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8186 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8187 return ia64_expand_compare_and_swap (mode, 1, arglist, target);
8189 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8190 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8191 return ia64_expand_compare_and_swap (mode, 0, arglist, target);
8193 case IA64_BUILTIN_SYNCHRONIZE:
8194 emit_insn (gen_mf ());
8197 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8198 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8199 return ia64_expand_lock_test_and_set (mode, arglist, target);
8201 case IA64_BUILTIN_LOCK_RELEASE_SI:
8202 case IA64_BUILTIN_LOCK_RELEASE_DI:
8203 return ia64_expand_lock_release (mode, arglist, target);
8205 case IA64_BUILTIN_BSP:
8206 if (! target || ! register_operand (target, DImode))
8207 target = gen_reg_rtx (DImode);
8208 emit_insn (gen_bsp_value (target));
8211 case IA64_BUILTIN_FLUSHRS:
8212 emit_insn (gen_flushrs ());
8215 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8216 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8217 return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
8219 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8220 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8221 return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
8223 case IA64_BUILTIN_FETCH_AND_OR_SI:
8224 case IA64_BUILTIN_FETCH_AND_OR_DI:
8225 return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
8227 case IA64_BUILTIN_FETCH_AND_AND_SI:
8228 case IA64_BUILTIN_FETCH_AND_AND_DI:
8229 return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
8231 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8232 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8233 return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
8235 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8236 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8237 return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
8239 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8240 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8241 return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
8243 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8244 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8245 return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
8247 case IA64_BUILTIN_OR_AND_FETCH_SI:
8248 case IA64_BUILTIN_OR_AND_FETCH_DI:
8249 return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
8251 case IA64_BUILTIN_AND_AND_FETCH_SI:
8252 case IA64_BUILTIN_AND_AND_FETCH_DI:
8253 return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
8255 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8256 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8257 return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
8259 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8260 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8261 return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
8270 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8271 most significant bits of the stack slot. */
8274 ia64_hpux_function_arg_padding (mode, type)
8275 enum machine_mode mode;
8278 /* Exception to normal case for structures/unions/etc. */
8280 if (type && AGGREGATE_TYPE_P (type)
8281 && int_size_in_bytes (type) < UNITS_PER_WORD)
8284 /* This is the standard FUNCTION_ARG_PADDING with !BYTES_BIG_ENDIAN
8285 hardwired to be true. */
8287 return((mode == BLKmode
8288 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
8289 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
8290 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
8291 ? downward : upward);
8294 /* Linked list of all external functions that are to be emitted by GCC.
8295 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8296 order to avoid putting out names that are never really used. */
8298 struct extern_func_list
8300 struct extern_func_list *next; /* next external */
8301 char *name; /* name of the external */
8302 } *extern_func_head = 0;
8305 ia64_hpux_add_extern_decl (name)
8308 struct extern_func_list *p;
8310 p = (struct extern_func_list *) xmalloc (sizeof (struct extern_func_list));
8311 p->name = xmalloc (strlen (name) + 1);
8312 strcpy(p->name, name);
8313 p->next = extern_func_head;
8314 extern_func_head = p;
8317 /* Print out the list of used global functions. */
8320 ia64_hpux_asm_file_end (file)
8323 while (extern_func_head)
8325 const char *real_name;
8328 real_name = (* targetm.strip_name_encoding) (extern_func_head->name);
8329 decl = maybe_get_identifier (real_name);
8332 || (! TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (decl)))
8335 TREE_ASM_WRITTEN (decl) = 1;
8336 (*targetm.asm_out.globalize_label) (file, extern_func_head->name);
8337 fprintf (file, "%s", TYPE_ASM_OP);
8338 assemble_name (file, extern_func_head->name);
8340 fprintf (file, TYPE_OPERAND_FMT, "function");
8343 extern_func_head = extern_func_head->next;
8348 /* Switch to the section to which we should output X. The only thing
8349 special we do here is to honor small data. */
8352 ia64_select_rtx_section (mode, x, align)
8353 enum machine_mode mode;
8355 unsigned HOST_WIDE_INT align;
8357 if (GET_MODE_SIZE (mode) > 0
8358 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8361 default_elf_select_rtx_section (mode, x, align);
8364 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8365 Pretend flag_pic is always set. */
8368 ia64_rwreloc_select_section (exp, reloc, align)
8371 unsigned HOST_WIDE_INT align;
8373 default_elf_select_section_1 (exp, reloc, align, true);
8377 ia64_rwreloc_unique_section (decl, reloc)
8381 default_unique_section_1 (decl, reloc, true);
8385 ia64_rwreloc_select_rtx_section (mode, x, align)
8386 enum machine_mode mode;
8388 unsigned HOST_WIDE_INT align;
8390 int save_pic = flag_pic;
8392 ia64_select_rtx_section (mode, x, align);
8393 flag_pic = save_pic;
8397 ia64_rwreloc_section_type_flags (decl, name, reloc)
8402 return default_section_type_flags_1 (decl, name, reloc, true);
8406 /* Output the assembler code for a thunk function. THUNK_DECL is the
8407 declaration for the thunk function itself, FUNCTION is the decl for
8408 the target function. DELTA is an immediate constant offset to be
8409 added to THIS. If VCALL_OFFSET is nonzero, the word at
8410 *(*this + vcall_offset) should be added to THIS. */
8413 ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
8415 tree thunk ATTRIBUTE_UNUSED;
8416 HOST_WIDE_INT delta;
8417 HOST_WIDE_INT vcall_offset;
8420 rtx this, insn, funexp;
8422 reload_completed = 1;
8425 /* Set things up as ia64_expand_prologue might. */
8426 last_scratch_gr_reg = 15;
8428 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8429 current_frame_info.spill_cfa_off = -16;
8430 current_frame_info.n_input_regs = 1;
8431 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8433 if (!TARGET_REG_NAMES)
8434 reg_names[IN_REG (0)] = ia64_reg_numbers[0];
8436 /* Mark the end of the (empty) prologue. */
8437 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8439 this = gen_rtx_REG (Pmode, IN_REG (0));
8441 /* Apply the constant offset, if required. */
8444 rtx delta_rtx = GEN_INT (delta);
8446 if (!CONST_OK_FOR_I (delta))
8448 rtx tmp = gen_rtx_REG (Pmode, 2);
8449 emit_move_insn (tmp, delta_rtx);
8452 emit_insn (gen_adddi3 (this, this, delta_rtx));
8455 /* Apply the offset from the vtable, if required. */
8458 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8459 rtx tmp = gen_rtx_REG (Pmode, 2);
8461 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8463 if (!CONST_OK_FOR_J (vcall_offset))
8465 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8466 emit_move_insn (tmp2, vcall_offset_rtx);
8467 vcall_offset_rtx = tmp2;
8469 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8471 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8473 emit_insn (gen_adddi3 (this, this, tmp));
8476 /* Generate a tail call to the target function. */
8477 if (! TREE_USED (function))
8479 assemble_external (function);
8480 TREE_USED (function) = 1;
8482 funexp = XEXP (DECL_RTL (function), 0);
8483 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8484 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8485 insn = get_last_insn ();
8486 SIBLING_CALL_P (insn) = 1;
8488 /* Code generation for calls relies on splitting. */
8489 reload_completed = 1;
8490 try_split (PATTERN (insn), insn, 0);
8494 /* Run just enough of rest_of_compilation to get the insns emitted.
8495 There's not really enough bulk here to make other passes such as
8496 instruction scheduling worth while. Note that use_thunk calls
8497 assemble_start_function and assemble_end_function. */
8499 insn = get_insns ();
8500 emit_all_insn_group_barriers (NULL, insn);
8501 shorten_branches (insn);
8502 final_start_function (insn, file, 1);
8503 final (insn, file, 1, 0);
8504 final_end_function ();
8506 reload_completed = 0;
8510 #include "gt-ia64.h"