1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
52 #include "cfglayout.h"
54 /* This is used for communication between ASM_OUTPUT_LABEL and
55 ASM_OUTPUT_LABELREF. */
56 int ia64_asm_output_label = 0;
58 /* Define the information needed to generate branch and scc insns. This is
59 stored from the compare operation. */
60 struct rtx_def * ia64_compare_op0;
61 struct rtx_def * ia64_compare_op1;
63 /* Register names for ia64_expand_prologue. */
64 static const char * const ia64_reg_numbers[96] =
65 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
66 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
67 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
68 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
69 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
70 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
71 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
72 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
73 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
74 "r104","r105","r106","r107","r108","r109","r110","r111",
75 "r112","r113","r114","r115","r116","r117","r118","r119",
76 "r120","r121","r122","r123","r124","r125","r126","r127"};
78 /* ??? These strings could be shared with REGISTER_NAMES. */
79 static const char * const ia64_input_reg_names[8] =
80 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
82 /* ??? These strings could be shared with REGISTER_NAMES. */
83 static const char * const ia64_local_reg_names[80] =
84 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
85 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
86 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
87 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
88 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
89 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
90 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
91 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
92 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
93 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
95 /* ??? These strings could be shared with REGISTER_NAMES. */
96 static const char * const ia64_output_reg_names[8] =
97 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
99 /* String used with the -mfixed-range= option. */
100 const char *ia64_fixed_range_string;
102 /* Determines whether we use adds, addl, or movl to generate our
103 TLS immediate offsets. */
104 int ia64_tls_size = 22;
106 /* String used with the -mtls-size= option. */
107 const char *ia64_tls_size_string;
109 /* Which cpu are we scheduling for. */
110 enum processor_type ia64_tune;
112 /* String used with the -tune= option. */
113 const char *ia64_tune_string;
115 /* Determines whether we run our final scheduling pass or not. We always
116 avoid the normal second scheduling pass. */
117 static int ia64_flag_schedule_insns2;
119 /* Variables which are this size or smaller are put in the sdata/sbss
122 unsigned int ia64_section_threshold;
124 /* The following variable is used by the DFA insn scheduler. The value is
125 TRUE if we do insn bundling instead of insn scheduling. */
128 /* Structure to be filled in by ia64_compute_frame_size with register
129 save masks and offsets for the current function. */
131 struct ia64_frame_info
133 HOST_WIDE_INT total_size; /* size of the stack frame, not including
134 the caller's scratch area. */
135 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
136 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
137 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
138 HARD_REG_SET mask; /* mask of saved registers. */
139 unsigned int gr_used_mask; /* mask of registers in use as gr spill
140 registers or long-term scratches. */
141 int n_spilled; /* number of spilled registers. */
142 int reg_fp; /* register for fp. */
143 int reg_save_b0; /* save register for b0. */
144 int reg_save_pr; /* save register for prs. */
145 int reg_save_ar_pfs; /* save register for ar.pfs. */
146 int reg_save_ar_unat; /* save register for ar.unat. */
147 int reg_save_ar_lc; /* save register for ar.lc. */
148 int reg_save_gp; /* save register for gp. */
149 int n_input_regs; /* number of input registers used. */
150 int n_local_regs; /* number of local registers used. */
151 int n_output_regs; /* number of output registers used. */
152 int n_rotate_regs; /* number of rotating registers used. */
154 char need_regstk; /* true if a .regstk directive needed. */
155 char initialized; /* true if the data is finalized. */
158 /* Current frame information calculated by ia64_compute_frame_size. */
159 static struct ia64_frame_info current_frame_info;
161 static int ia64_use_dfa_pipeline_interface PARAMS ((void));
162 static int ia64_first_cycle_multipass_dfa_lookahead PARAMS ((void));
163 static void ia64_dependencies_evaluation_hook PARAMS ((rtx, rtx));
164 static void ia64_init_dfa_pre_cycle_insn PARAMS ((void));
165 static rtx ia64_dfa_pre_cycle_insn PARAMS ((void));
166 static int ia64_first_cycle_multipass_dfa_lookahead_guard PARAMS ((rtx));
167 static int ia64_dfa_new_cycle PARAMS ((FILE *, int, rtx, int, int, int *));
168 static rtx gen_tls_get_addr PARAMS ((void));
169 static rtx gen_thread_pointer PARAMS ((void));
170 static rtx ia64_expand_tls_address PARAMS ((enum tls_model, rtx, rtx));
171 static int find_gr_spill PARAMS ((int));
172 static int next_scratch_gr_reg PARAMS ((void));
173 static void mark_reg_gr_used_mask PARAMS ((rtx, void *));
174 static void ia64_compute_frame_size PARAMS ((HOST_WIDE_INT));
175 static void setup_spill_pointers PARAMS ((int, rtx, HOST_WIDE_INT));
176 static void finish_spill_pointers PARAMS ((void));
177 static rtx spill_restore_mem PARAMS ((rtx, HOST_WIDE_INT));
178 static void do_spill PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx));
179 static void do_restore PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT));
180 static rtx gen_movdi_x PARAMS ((rtx, rtx, rtx));
181 static rtx gen_fr_spill_x PARAMS ((rtx, rtx, rtx));
182 static rtx gen_fr_restore_x PARAMS ((rtx, rtx, rtx));
184 static enum machine_mode hfa_element_mode PARAMS ((tree, int));
185 static bool ia64_function_ok_for_sibcall PARAMS ((tree, tree));
186 static bool ia64_rtx_costs PARAMS ((rtx, int, int, int *));
187 static void fix_range PARAMS ((const char *));
188 static struct machine_function * ia64_init_machine_status PARAMS ((void));
189 static void emit_insn_group_barriers PARAMS ((FILE *));
190 static void emit_all_insn_group_barriers PARAMS ((FILE *));
191 static void final_emit_insn_group_barriers PARAMS ((FILE *));
192 static void emit_predicate_relation_info PARAMS ((void));
193 static void ia64_reorg PARAMS ((void));
194 static bool ia64_in_small_data_p PARAMS ((tree));
195 static void process_epilogue PARAMS ((void));
196 static int process_set PARAMS ((FILE *, rtx));
198 static rtx ia64_expand_fetch_and_op PARAMS ((optab, enum machine_mode,
200 static rtx ia64_expand_op_and_fetch PARAMS ((optab, enum machine_mode,
202 static rtx ia64_expand_compare_and_swap PARAMS ((enum machine_mode,
205 static rtx ia64_expand_lock_test_and_set PARAMS ((enum machine_mode,
207 static rtx ia64_expand_lock_release PARAMS ((enum machine_mode, tree, rtx));
208 static bool ia64_assemble_integer PARAMS ((rtx, unsigned int, int));
209 static void ia64_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
210 static void ia64_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
211 static void ia64_output_function_end_prologue PARAMS ((FILE *));
213 static int ia64_issue_rate PARAMS ((void));
214 static int ia64_adjust_cost PARAMS ((rtx, rtx, rtx, int));
215 static void ia64_sched_init PARAMS ((FILE *, int, int));
216 static void ia64_sched_finish PARAMS ((FILE *, int));
217 static int ia64_dfa_sched_reorder PARAMS ((FILE *, int, rtx *, int *,
219 static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
220 static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
221 static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
223 static struct bundle_state *get_free_bundle_state PARAMS ((void));
224 static void free_bundle_state PARAMS ((struct bundle_state *));
225 static void initiate_bundle_states PARAMS ((void));
226 static void finish_bundle_states PARAMS ((void));
227 static unsigned bundle_state_hash PARAMS ((const void *));
228 static int bundle_state_eq_p PARAMS ((const void *, const void *));
229 static int insert_bundle_state PARAMS ((struct bundle_state *));
230 static void initiate_bundle_state_table PARAMS ((void));
231 static void finish_bundle_state_table PARAMS ((void));
232 static int try_issue_nops PARAMS ((struct bundle_state *, int));
233 static int try_issue_insn PARAMS ((struct bundle_state *, rtx));
234 static void issue_nops_and_insn PARAMS ((struct bundle_state *, int,
236 static int get_max_pos PARAMS ((state_t));
237 static int get_template PARAMS ((state_t, int));
239 static rtx get_next_important_insn PARAMS ((rtx, rtx));
240 static void bundling PARAMS ((FILE *, int, rtx, rtx));
242 static void ia64_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
243 HOST_WIDE_INT, tree));
244 static void ia64_file_start PARAMS ((void));
246 static void ia64_select_rtx_section PARAMS ((enum machine_mode, rtx,
247 unsigned HOST_WIDE_INT));
248 static void ia64_rwreloc_select_section PARAMS ((tree, int,
249 unsigned HOST_WIDE_INT))
251 static void ia64_rwreloc_unique_section PARAMS ((tree, int))
253 static void ia64_rwreloc_select_rtx_section PARAMS ((enum machine_mode, rtx,
254 unsigned HOST_WIDE_INT))
256 static unsigned int ia64_rwreloc_section_type_flags
257 PARAMS ((tree, const char *, int))
260 static void ia64_hpux_add_extern_decl PARAMS ((const char *name))
262 static void ia64_hpux_file_end PARAMS ((void))
266 /* Table of valid machine attributes. */
267 static const struct attribute_spec ia64_attribute_table[] =
269 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
270 { "syscall_linkage", 0, 0, false, true, true, NULL },
271 { NULL, 0, 0, false, false, false, NULL }
274 /* Initialize the GCC target structure. */
275 #undef TARGET_ATTRIBUTE_TABLE
276 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
278 #undef TARGET_INIT_BUILTINS
279 #define TARGET_INIT_BUILTINS ia64_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
284 #undef TARGET_ASM_BYTE_OP
285 #define TARGET_ASM_BYTE_OP "\tdata1\t"
286 #undef TARGET_ASM_ALIGNED_HI_OP
287 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
288 #undef TARGET_ASM_ALIGNED_SI_OP
289 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
292 #undef TARGET_ASM_UNALIGNED_HI_OP
293 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
294 #undef TARGET_ASM_UNALIGNED_SI_OP
295 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
296 #undef TARGET_ASM_UNALIGNED_DI_OP
297 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
298 #undef TARGET_ASM_INTEGER
299 #define TARGET_ASM_INTEGER ia64_assemble_integer
301 #undef TARGET_ASM_FUNCTION_PROLOGUE
302 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
303 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
304 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
305 #undef TARGET_ASM_FUNCTION_EPILOGUE
306 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
308 #undef TARGET_IN_SMALL_DATA_P
309 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
311 #undef TARGET_SCHED_ADJUST_COST
312 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
315 #undef TARGET_SCHED_VARIABLE_ISSUE
316 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
317 #undef TARGET_SCHED_INIT
318 #define TARGET_SCHED_INIT ia64_sched_init
319 #undef TARGET_SCHED_FINISH
320 #define TARGET_SCHED_FINISH ia64_sched_finish
321 #undef TARGET_SCHED_REORDER
322 #define TARGET_SCHED_REORDER ia64_sched_reorder
323 #undef TARGET_SCHED_REORDER2
324 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
326 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
327 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
329 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
330 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
332 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
333 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
335 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
336 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
337 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
338 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
340 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
341 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
342 ia64_first_cycle_multipass_dfa_lookahead_guard
344 #undef TARGET_SCHED_DFA_NEW_CYCLE
345 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
348 #undef TARGET_HAVE_TLS
349 #define TARGET_HAVE_TLS true
352 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
353 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
355 #undef TARGET_ASM_OUTPUT_MI_THUNK
356 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
357 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
358 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
360 #undef TARGET_ASM_FILE_START
361 #define TARGET_ASM_FILE_START ia64_file_start
363 #undef TARGET_RTX_COSTS
364 #define TARGET_RTX_COSTS ia64_rtx_costs
365 #undef TARGET_ADDRESS_COST
366 #define TARGET_ADDRESS_COST hook_int_rtx_0
368 #undef TARGET_MACHINE_DEPENDENT_REORG
369 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
371 struct gcc_target targetm = TARGET_INITIALIZER;
373 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
376 call_operand (op, mode)
378 enum machine_mode mode;
380 if (mode != GET_MODE (op) && mode != VOIDmode)
383 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
384 || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
387 /* Return 1 if OP refers to a symbol in the sdata section. */
390 sdata_symbolic_operand (op, mode)
392 enum machine_mode mode ATTRIBUTE_UNUSED;
394 switch (GET_CODE (op))
397 if (GET_CODE (XEXP (op, 0)) != PLUS
398 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
400 op = XEXP (XEXP (op, 0), 0);
404 if (CONSTANT_POOL_ADDRESS_P (op))
405 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
407 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
416 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
419 got_symbolic_operand (op, mode)
421 enum machine_mode mode ATTRIBUTE_UNUSED;
423 switch (GET_CODE (op))
427 if (GET_CODE (op) != PLUS)
429 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
432 if (GET_CODE (op) != CONST_INT)
437 /* Ok if we're not using GOT entries at all. */
438 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
441 /* "Ok" while emitting rtl, since otherwise we won't be provided
442 with the entire offset during emission, which makes it very
443 hard to split the offset into high and low parts. */
444 if (rtx_equal_function_value_matters)
447 /* Force the low 14 bits of the constant to zero so that we do not
448 use up so many GOT entries. */
449 return (INTVAL (op) & 0x3fff) == 0;
461 /* Return 1 if OP refers to a symbol. */
464 symbolic_operand (op, mode)
466 enum machine_mode mode ATTRIBUTE_UNUSED;
468 switch (GET_CODE (op))
481 /* Return tls_model if OP refers to a TLS symbol. */
484 tls_symbolic_operand (op, mode)
486 enum machine_mode mode ATTRIBUTE_UNUSED;
488 if (GET_CODE (op) != SYMBOL_REF)
490 return SYMBOL_REF_TLS_MODEL (op);
494 /* Return 1 if OP refers to a function. */
497 function_operand (op, mode)
499 enum machine_mode mode ATTRIBUTE_UNUSED;
501 if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
507 /* Return 1 if OP is setjmp or a similar function. */
509 /* ??? This is an unsatisfying solution. Should rethink. */
512 setjmp_operand (op, mode)
514 enum machine_mode mode ATTRIBUTE_UNUSED;
519 if (GET_CODE (op) != SYMBOL_REF)
524 /* The following code is borrowed from special_function_p in calls.c. */
526 /* Disregard prefix _, __ or __x. */
529 if (name[1] == '_' && name[2] == 'x')
531 else if (name[1] == '_')
541 && (! strcmp (name, "setjmp")
542 || ! strcmp (name, "setjmp_syscall")))
544 && ! strcmp (name, "sigsetjmp"))
546 && ! strcmp (name, "savectx")));
548 else if ((name[0] == 'q' && name[1] == 's'
549 && ! strcmp (name, "qsetjmp"))
550 || (name[0] == 'v' && name[1] == 'f'
551 && ! strcmp (name, "vfork")))
557 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
560 move_operand (op, mode)
562 enum machine_mode mode;
564 return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
567 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
570 gr_register_operand (op, mode)
572 enum machine_mode mode;
574 if (! register_operand (op, mode))
576 if (GET_CODE (op) == SUBREG)
577 op = SUBREG_REG (op);
578 if (GET_CODE (op) == REG)
580 unsigned int regno = REGNO (op);
581 if (regno < FIRST_PSEUDO_REGISTER)
582 return GENERAL_REGNO_P (regno);
587 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
590 fr_register_operand (op, mode)
592 enum machine_mode mode;
594 if (! register_operand (op, mode))
596 if (GET_CODE (op) == SUBREG)
597 op = SUBREG_REG (op);
598 if (GET_CODE (op) == REG)
600 unsigned int regno = REGNO (op);
601 if (regno < FIRST_PSEUDO_REGISTER)
602 return FR_REGNO_P (regno);
607 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
610 grfr_register_operand (op, mode)
612 enum machine_mode mode;
614 if (! register_operand (op, mode))
616 if (GET_CODE (op) == SUBREG)
617 op = SUBREG_REG (op);
618 if (GET_CODE (op) == REG)
620 unsigned int regno = REGNO (op);
621 if (regno < FIRST_PSEUDO_REGISTER)
622 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
627 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
630 gr_nonimmediate_operand (op, mode)
632 enum machine_mode mode;
634 if (! nonimmediate_operand (op, mode))
636 if (GET_CODE (op) == SUBREG)
637 op = SUBREG_REG (op);
638 if (GET_CODE (op) == REG)
640 unsigned int regno = REGNO (op);
641 if (regno < FIRST_PSEUDO_REGISTER)
642 return GENERAL_REGNO_P (regno);
647 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
650 fr_nonimmediate_operand (op, mode)
652 enum machine_mode mode;
654 if (! nonimmediate_operand (op, mode))
656 if (GET_CODE (op) == SUBREG)
657 op = SUBREG_REG (op);
658 if (GET_CODE (op) == REG)
660 unsigned int regno = REGNO (op);
661 if (regno < FIRST_PSEUDO_REGISTER)
662 return FR_REGNO_P (regno);
667 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
670 grfr_nonimmediate_operand (op, mode)
672 enum machine_mode mode;
674 if (! nonimmediate_operand (op, mode))
676 if (GET_CODE (op) == SUBREG)
677 op = SUBREG_REG (op);
678 if (GET_CODE (op) == REG)
680 unsigned int regno = REGNO (op);
681 if (regno < FIRST_PSEUDO_REGISTER)
682 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
687 /* Return 1 if OP is a GR register operand, or zero. */
690 gr_reg_or_0_operand (op, mode)
692 enum machine_mode mode;
694 return (op == const0_rtx || gr_register_operand (op, mode));
697 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
700 gr_reg_or_5bit_operand (op, mode)
702 enum machine_mode mode;
704 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
705 || GET_CODE (op) == CONSTANT_P_RTX
706 || gr_register_operand (op, mode));
709 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
712 gr_reg_or_6bit_operand (op, mode)
714 enum machine_mode mode;
716 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
717 || GET_CODE (op) == CONSTANT_P_RTX
718 || gr_register_operand (op, mode));
721 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
724 gr_reg_or_8bit_operand (op, mode)
726 enum machine_mode mode;
728 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
729 || GET_CODE (op) == CONSTANT_P_RTX
730 || gr_register_operand (op, mode));
733 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
736 grfr_reg_or_8bit_operand (op, mode)
738 enum machine_mode mode;
740 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
741 || GET_CODE (op) == CONSTANT_P_RTX
742 || grfr_register_operand (op, mode));
745 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
749 gr_reg_or_8bit_adjusted_operand (op, mode)
751 enum machine_mode mode;
753 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
754 || GET_CODE (op) == CONSTANT_P_RTX
755 || gr_register_operand (op, mode));
758 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
759 immediate and an 8 bit adjusted immediate operand. This is necessary
760 because when we emit a compare, we don't know what the condition will be,
761 so we need the union of the immediates accepted by GT and LT. */
764 gr_reg_or_8bit_and_adjusted_operand (op, mode)
766 enum machine_mode mode;
768 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
769 && CONST_OK_FOR_L (INTVAL (op)))
770 || GET_CODE (op) == CONSTANT_P_RTX
771 || gr_register_operand (op, mode));
774 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
777 gr_reg_or_14bit_operand (op, mode)
779 enum machine_mode mode;
781 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
782 || GET_CODE (op) == CONSTANT_P_RTX
783 || gr_register_operand (op, mode));
786 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
789 gr_reg_or_22bit_operand (op, mode)
791 enum machine_mode mode;
793 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
794 || GET_CODE (op) == CONSTANT_P_RTX
795 || gr_register_operand (op, mode));
798 /* Return 1 if OP is a 6 bit immediate operand. */
801 shift_count_operand (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
806 || GET_CODE (op) == CONSTANT_P_RTX);
809 /* Return 1 if OP is a 5 bit immediate operand. */
812 shift_32bit_count_operand (op, mode)
814 enum machine_mode mode ATTRIBUTE_UNUSED;
816 return ((GET_CODE (op) == CONST_INT
817 && (INTVAL (op) >= 0 && INTVAL (op) < 32))
818 || GET_CODE (op) == CONSTANT_P_RTX);
821 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
824 shladd_operand (op, mode)
826 enum machine_mode mode ATTRIBUTE_UNUSED;
828 return (GET_CODE (op) == CONST_INT
829 && (INTVAL (op) == 2 || INTVAL (op) == 4
830 || INTVAL (op) == 8 || INTVAL (op) == 16));
833 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
836 fetchadd_operand (op, mode)
838 enum machine_mode mode ATTRIBUTE_UNUSED;
840 return (GET_CODE (op) == CONST_INT
841 && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
842 INTVAL (op) == -4 || INTVAL (op) == -1 ||
843 INTVAL (op) == 1 || INTVAL (op) == 4 ||
844 INTVAL (op) == 8 || INTVAL (op) == 16));
847 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
850 fr_reg_or_fp01_operand (op, mode)
852 enum machine_mode mode;
854 return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
855 || fr_register_operand (op, mode));
858 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
859 POST_MODIFY with a REG as displacement. */
862 destination_operand (op, mode)
864 enum machine_mode mode;
866 if (! nonimmediate_operand (op, mode))
868 if (GET_CODE (op) == MEM
869 && GET_CODE (XEXP (op, 0)) == POST_MODIFY
870 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
875 /* Like memory_operand, but don't allow post-increments. */
878 not_postinc_memory_operand (op, mode)
880 enum machine_mode mode;
882 return (memory_operand (op, mode)
883 && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
886 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
887 signed immediate operand. */
890 normal_comparison_operator (op, mode)
892 enum machine_mode mode;
894 enum rtx_code code = GET_CODE (op);
895 return ((mode == VOIDmode || GET_MODE (op) == mode)
896 && (code == EQ || code == NE
897 || code == GT || code == LE || code == GTU || code == LEU));
900 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
901 signed immediate operand. */
904 adjusted_comparison_operator (op, mode)
906 enum machine_mode mode;
908 enum rtx_code code = GET_CODE (op);
909 return ((mode == VOIDmode || GET_MODE (op) == mode)
910 && (code == LT || code == GE || code == LTU || code == GEU));
913 /* Return 1 if this is a signed inequality operator. */
916 signed_inequality_operator (op, mode)
918 enum machine_mode mode;
920 enum rtx_code code = GET_CODE (op);
921 return ((mode == VOIDmode || GET_MODE (op) == mode)
922 && (code == GE || code == GT
923 || code == LE || code == LT));
926 /* Return 1 if this operator is valid for predication. */
929 predicate_operator (op, mode)
931 enum machine_mode mode;
933 enum rtx_code code = GET_CODE (op);
934 return ((GET_MODE (op) == mode || mode == VOIDmode)
935 && (code == EQ || code == NE));
938 /* Return 1 if this operator can be used in a conditional operation. */
941 condop_operator (op, mode)
943 enum machine_mode mode;
945 enum rtx_code code = GET_CODE (op);
946 return ((GET_MODE (op) == mode || mode == VOIDmode)
947 && (code == PLUS || code == MINUS || code == AND
948 || code == IOR || code == XOR));
951 /* Return 1 if this is the ar.lc register. */
954 ar_lc_reg_operand (op, mode)
956 enum machine_mode mode;
958 return (GET_MODE (op) == DImode
959 && (mode == DImode || mode == VOIDmode)
960 && GET_CODE (op) == REG
961 && REGNO (op) == AR_LC_REGNUM);
964 /* Return 1 if this is the ar.ccv register. */
967 ar_ccv_reg_operand (op, mode)
969 enum machine_mode mode;
971 return ((GET_MODE (op) == mode || mode == VOIDmode)
972 && GET_CODE (op) == REG
973 && REGNO (op) == AR_CCV_REGNUM);
976 /* Return 1 if this is the ar.pfs register. */
979 ar_pfs_reg_operand (op, mode)
981 enum machine_mode mode;
983 return ((GET_MODE (op) == mode || mode == VOIDmode)
984 && GET_CODE (op) == REG
985 && REGNO (op) == AR_PFS_REGNUM);
988 /* Like general_operand, but don't allow (mem (addressof)). */
991 general_tfmode_operand (op, mode)
993 enum machine_mode mode;
995 if (! general_operand (op, mode))
997 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1005 destination_tfmode_operand (op, mode)
1007 enum machine_mode mode;
1009 if (! destination_operand (op, mode))
1011 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1019 tfreg_or_fp01_operand (op, mode)
1021 enum machine_mode mode;
1023 if (GET_CODE (op) == SUBREG)
1025 return fr_reg_or_fp01_operand (op, mode);
1028 /* Return 1 if OP is valid as a base register in a reg + offset address. */
1031 basereg_operand (op, mode)
1033 enum machine_mode mode;
1035 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
1036 checks from pa.c basereg_operand as well? Seems to be OK without them
1039 return (register_operand (op, mode) &&
1040 REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
1043 /* Return 1 if the operands of a move are ok. */
1046 ia64_move_ok (dst, src)
1049 /* If we're under init_recog_no_volatile, we'll not be able to use
1050 memory_operand. So check the code directly and don't worry about
1051 the validity of the underlying address, which should have been
1052 checked elsewhere anyway. */
1053 if (GET_CODE (dst) != MEM)
1055 if (GET_CODE (src) == MEM)
1057 if (register_operand (src, VOIDmode))
1060 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1061 if (INTEGRAL_MODE_P (GET_MODE (dst)))
1062 return src == const0_rtx;
1064 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
1067 /* Return 0 if we are doing C++ code. This optimization fails with
1068 C++ because of GNAT c++/6685. */
1071 addp4_optimize_ok (op1, op2)
1075 if (!strcmp (lang_hooks.name, "GNU C++"))
1078 return (basereg_operand (op1, GET_MODE(op1)) !=
1079 basereg_operand (op2, GET_MODE(op2)));
1082 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1083 Return the length of the field, or <= 0 on failure. */
1086 ia64_depz_field_mask (rop, rshift)
1089 unsigned HOST_WIDE_INT op = INTVAL (rop);
1090 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
1092 /* Get rid of the zero bits we're shifting in. */
1095 /* We must now have a solid block of 1's at bit 0. */
1096 return exact_log2 (op + 1);
1099 /* Expand a symbolic constant load. */
1102 ia64_expand_load_address (dest, src)
1105 if (tls_symbolic_operand (src, VOIDmode))
1107 if (GET_CODE (dest) != REG)
1110 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1111 having to pointer-extend the value afterward. Other forms of address
1112 computation below are also more natural to compute as 64-bit quantities.
1113 If we've been given an SImode destination register, change it. */
1114 if (GET_MODE (dest) != Pmode)
1115 dest = gen_rtx_REG (Pmode, REGNO (dest));
1117 if (TARGET_AUTO_PIC)
1119 emit_insn (gen_load_gprel64 (dest, src));
1122 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1124 emit_insn (gen_load_fptr (dest, src));
1127 else if (sdata_symbolic_operand (src, VOIDmode))
1129 emit_insn (gen_load_gprel (dest, src));
1133 if (GET_CODE (src) == CONST
1134 && GET_CODE (XEXP (src, 0)) == PLUS
1135 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
1136 && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
1138 rtx sym = XEXP (XEXP (src, 0), 0);
1139 HOST_WIDE_INT ofs, hi, lo;
1141 /* Split the offset into a sign extended 14-bit low part
1142 and a complementary high part. */
1143 ofs = INTVAL (XEXP (XEXP (src, 0), 1));
1144 lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
1147 ia64_expand_load_address (dest, plus_constant (sym, hi));
1148 emit_insn (gen_adddi3 (dest, dest, GEN_INT (lo)));
1154 tmp = gen_rtx_HIGH (Pmode, src);
1155 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1156 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1158 tmp = gen_rtx_LO_SUM (GET_MODE (dest), dest, src);
1159 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1163 static GTY(()) rtx gen_tls_tga;
1168 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1172 static GTY(()) rtx thread_pointer_rtx;
1174 gen_thread_pointer ()
1176 if (!thread_pointer_rtx)
1178 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1179 RTX_UNCHANGING_P (thread_pointer_rtx) = 1;
1181 return thread_pointer_rtx;
1185 ia64_expand_tls_address (tls_kind, op0, op1)
1186 enum tls_model tls_kind;
1189 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1193 case TLS_MODEL_GLOBAL_DYNAMIC:
1196 tga_op1 = gen_reg_rtx (Pmode);
1197 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1198 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1199 RTX_UNCHANGING_P (tga_op1) = 1;
1201 tga_op2 = gen_reg_rtx (Pmode);
1202 emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
1203 tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
1204 RTX_UNCHANGING_P (tga_op2) = 1;
1206 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1207 LCT_CONST, Pmode, 2, tga_op1,
1208 Pmode, tga_op2, Pmode);
1210 insns = get_insns ();
1213 emit_libcall_block (insns, op0, tga_ret, op1);
1216 case TLS_MODEL_LOCAL_DYNAMIC:
1217 /* ??? This isn't the completely proper way to do local-dynamic
1218 If the call to __tls_get_addr is used only by a single symbol,
1219 then we should (somehow) move the dtprel to the second arg
1220 to avoid the extra add. */
1223 tga_op1 = gen_reg_rtx (Pmode);
1224 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1225 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1226 RTX_UNCHANGING_P (tga_op1) = 1;
1228 tga_op2 = const0_rtx;
1230 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1231 LCT_CONST, Pmode, 2, tga_op1,
1232 Pmode, tga_op2, Pmode);
1234 insns = get_insns ();
1237 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1239 tmp = gen_reg_rtx (Pmode);
1240 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1242 if (register_operand (op0, Pmode))
1245 tga_ret = gen_reg_rtx (Pmode);
1248 emit_insn (gen_load_dtprel (tga_ret, op1));
1249 emit_insn (gen_adddi3 (tga_ret, tmp, tga_ret));
1252 emit_insn (gen_add_dtprel (tga_ret, tmp, op1));
1254 return (tga_ret == op0 ? NULL_RTX : tga_ret);
1256 case TLS_MODEL_INITIAL_EXEC:
1257 tmp = gen_reg_rtx (Pmode);
1258 emit_insn (gen_load_ltoff_tprel (tmp, op1));
1259 tmp = gen_rtx_MEM (Pmode, tmp);
1260 RTX_UNCHANGING_P (tmp) = 1;
1261 tmp = force_reg (Pmode, tmp);
1263 if (register_operand (op0, Pmode))
1266 op1 = gen_reg_rtx (Pmode);
1267 emit_insn (gen_adddi3 (op1, tmp, gen_thread_pointer ()));
1269 return (op1 == op0 ? NULL_RTX : op1);
1271 case TLS_MODEL_LOCAL_EXEC:
1272 if (register_operand (op0, Pmode))
1275 tmp = gen_reg_rtx (Pmode);
1278 emit_insn (gen_load_tprel (tmp, op1));
1279 emit_insn (gen_adddi3 (tmp, gen_thread_pointer (), tmp));
1282 emit_insn (gen_add_tprel (tmp, gen_thread_pointer (), op1));
1284 return (tmp == op0 ? NULL_RTX : tmp);
1292 ia64_expand_move (op0, op1)
1295 enum machine_mode mode = GET_MODE (op0);
1297 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1298 op1 = force_reg (mode, op1);
1300 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1302 enum tls_model tls_kind;
1303 if ((tls_kind = tls_symbolic_operand (op1, VOIDmode)))
1304 return ia64_expand_tls_address (tls_kind, op0, op1);
1306 if (!TARGET_NO_PIC && reload_completed)
1308 ia64_expand_load_address (op0, op1);
1316 /* Split a move from OP1 to OP0 conditional on COND. */
1319 ia64_emit_cond_move (op0, op1, cond)
1322 rtx insn, first = get_last_insn ();
1324 emit_move_insn (op0, op1);
1326 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1328 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1332 /* Split a post-reload TImode reference into two DImode components. */
1335 ia64_split_timode (out, in, scratch)
1339 switch (GET_CODE (in))
1342 out[0] = gen_rtx_REG (DImode, REGNO (in));
1343 out[1] = gen_rtx_REG (DImode, REGNO (in) + 1);
1348 rtx base = XEXP (in, 0);
1350 switch (GET_CODE (base))
1353 out[0] = adjust_address (in, DImode, 0);
1356 base = XEXP (base, 0);
1357 out[0] = adjust_address (in, DImode, 0);
1360 /* Since we're changing the mode, we need to change to POST_MODIFY
1361 as well to preserve the size of the increment. Either that or
1362 do the update in two steps, but we've already got this scratch
1363 register handy so let's use it. */
1365 base = XEXP (base, 0);
1367 = change_address (in, DImode,
1369 (Pmode, base, plus_constant (base, 16)));
1372 base = XEXP (base, 0);
1374 = change_address (in, DImode,
1376 (Pmode, base, plus_constant (base, -16)));
1382 if (scratch == NULL_RTX)
1384 out[1] = change_address (in, DImode, scratch);
1385 return gen_adddi3 (scratch, base, GEN_INT (8));
1390 split_double (in, &out[0], &out[1]);
1398 /* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
1399 through memory plus an extra GR scratch register. Except that you can
1400 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1401 SECONDARY_RELOAD_CLASS, but not both.
1403 We got into problems in the first place by allowing a construct like
1404 (subreg:TF (reg:TI)), which we got from a union containing a long double.
1405 This solution attempts to prevent this situation from occurring. When
1406 we see something like the above, we spill the inner register to memory. */
1409 spill_tfmode_operand (in, force)
1413 if (GET_CODE (in) == SUBREG
1414 && GET_MODE (SUBREG_REG (in)) == TImode
1415 && GET_CODE (SUBREG_REG (in)) == REG)
1417 rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
1418 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1420 else if (force && GET_CODE (in) == REG)
1422 rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
1423 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1425 else if (GET_CODE (in) == MEM
1426 && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
1427 return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
1432 /* Emit comparison instruction if necessary, returning the expression
1433 that holds the compare result in the proper mode. */
1436 ia64_expand_compare (code, mode)
1438 enum machine_mode mode;
1440 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1443 /* If we have a BImode input, then we already have a compare result, and
1444 do not need to emit another comparison. */
1445 if (GET_MODE (op0) == BImode)
1447 if ((code == NE || code == EQ) && op1 == const0_rtx)
1454 cmp = gen_reg_rtx (BImode);
1455 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1456 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1460 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1463 /* Emit the appropriate sequence for a call. */
1466 ia64_expand_call (retval, addr, nextarg, sibcall_p)
1469 rtx nextarg ATTRIBUTE_UNUSED;
1474 addr = XEXP (addr, 0);
1475 b0 = gen_rtx_REG (DImode, R_BR (0));
1477 /* ??? Should do this for functions known to bind local too. */
1478 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1481 insn = gen_sibcall_nogp (addr);
1483 insn = gen_call_nogp (addr, b0);
1485 insn = gen_call_value_nogp (retval, addr, b0);
1486 insn = emit_call_insn (insn);
1491 insn = gen_sibcall_gp (addr);
1493 insn = gen_call_gp (addr, b0);
1495 insn = gen_call_value_gp (retval, addr, b0);
1496 insn = emit_call_insn (insn);
1498 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1503 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1504 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
1505 gen_rtx_REG (DImode, AR_PFS_REGNUM));
1514 if (current_frame_info.reg_save_gp)
1515 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1518 HOST_WIDE_INT offset;
1520 offset = (current_frame_info.spill_cfa_off
1521 + current_frame_info.spill_size);
1522 if (frame_pointer_needed)
1524 tmp = hard_frame_pointer_rtx;
1529 tmp = stack_pointer_rtx;
1530 offset = current_frame_info.total_size - offset;
1533 if (CONST_OK_FOR_I (offset))
1534 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1535 tmp, GEN_INT (offset)));
1538 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1539 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1540 pic_offset_table_rtx, tmp));
1543 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1546 emit_move_insn (pic_offset_table_rtx, tmp);
1550 ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
1551 noreturn_p, sibcall_p)
1552 rtx retval, addr, retaddr, scratch_r, scratch_b;
1553 int noreturn_p, sibcall_p;
1556 bool is_desc = false;
1558 /* If we find we're calling through a register, then we're actually
1559 calling through a descriptor, so load up the values. */
1565 /* ??? We are currently constrained to *not* use peep2, because
1566 we can legitimiately change the global lifetime of the GP
1567 (in the form of killing where previously live). This is
1568 because a call through a descriptor doesn't use the previous
1569 value of the GP, while a direct call does, and we do not
1570 commit to either form until the split here.
1572 That said, this means that we lack precise life info for
1573 whether ADDR is dead after this call. This is not terribly
1574 important, since we can fix things up essentially for free
1575 with the POST_DEC below, but it's nice to not use it when we
1576 can immediately tell it's not necessary. */
1577 addr_dead_p = ((noreturn_p || sibcall_p
1578 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1580 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1582 /* Load the code address into scratch_b. */
1583 tmp = gen_rtx_POST_INC (Pmode, addr);
1584 tmp = gen_rtx_MEM (Pmode, tmp);
1585 emit_move_insn (scratch_r, tmp);
1586 emit_move_insn (scratch_b, scratch_r);
1588 /* Load the GP address. If ADDR is not dead here, then we must
1589 revert the change made above via the POST_INCREMENT. */
1591 tmp = gen_rtx_POST_DEC (Pmode, addr);
1594 tmp = gen_rtx_MEM (Pmode, tmp);
1595 emit_move_insn (pic_offset_table_rtx, tmp);
1602 insn = gen_sibcall_nogp (addr);
1604 insn = gen_call_value_nogp (retval, addr, retaddr);
1606 insn = gen_call_nogp (addr, retaddr);
1607 emit_call_insn (insn);
1609 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1613 /* Begin the assembly file. */
1618 default_file_start ();
1619 emit_safe_across_calls ();
1623 emit_safe_across_calls ()
1625 unsigned int rs, re;
1632 while (rs < 64 && call_used_regs[PR_REG (rs)])
1636 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1640 fputs ("\t.pred.safe_across_calls ", asm_out_file);
1644 fputc (',', asm_out_file);
1646 fprintf (asm_out_file, "p%u", rs);
1648 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
1652 fputc ('\n', asm_out_file);
1655 /* Helper function for ia64_compute_frame_size: find an appropriate general
1656 register to spill some special register to. SPECIAL_SPILL_MASK contains
1657 bits in GR0 to GR31 that have already been allocated by this routine.
1658 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1661 find_gr_spill (try_locals)
1666 /* If this is a leaf function, first try an otherwise unused
1667 call-clobbered register. */
1668 if (current_function_is_leaf)
1670 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1671 if (! regs_ever_live[regno]
1672 && call_used_regs[regno]
1673 && ! fixed_regs[regno]
1674 && ! global_regs[regno]
1675 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1677 current_frame_info.gr_used_mask |= 1 << regno;
1684 regno = current_frame_info.n_local_regs;
1685 /* If there is a frame pointer, then we can't use loc79, because
1686 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1687 reg_name switching code in ia64_expand_prologue. */
1688 if (regno < (80 - frame_pointer_needed))
1690 current_frame_info.n_local_regs = regno + 1;
1691 return LOC_REG (0) + regno;
1695 /* Failed to find a general register to spill to. Must use stack. */
1699 /* In order to make for nice schedules, we try to allocate every temporary
1700 to a different register. We must of course stay away from call-saved,
1701 fixed, and global registers. We must also stay away from registers
1702 allocated in current_frame_info.gr_used_mask, since those include regs
1703 used all through the prologue.
1705 Any register allocated here must be used immediately. The idea is to
1706 aid scheduling, not to solve data flow problems. */
1708 static int last_scratch_gr_reg;
1711 next_scratch_gr_reg ()
1715 for (i = 0; i < 32; ++i)
1717 regno = (last_scratch_gr_reg + i + 1) & 31;
1718 if (call_used_regs[regno]
1719 && ! fixed_regs[regno]
1720 && ! global_regs[regno]
1721 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1723 last_scratch_gr_reg = regno;
1728 /* There must be _something_ available. */
1732 /* Helper function for ia64_compute_frame_size, called through
1733 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1736 mark_reg_gr_used_mask (reg, data)
1738 void *data ATTRIBUTE_UNUSED;
1740 unsigned int regno = REGNO (reg);
1743 unsigned int i, n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
1744 for (i = 0; i < n; ++i)
1745 current_frame_info.gr_used_mask |= 1 << (regno + i);
1749 /* Returns the number of bytes offset between the frame pointer and the stack
1750 pointer for the current function. SIZE is the number of bytes of space
1751 needed for local variables. */
1754 ia64_compute_frame_size (size)
1757 HOST_WIDE_INT total_size;
1758 HOST_WIDE_INT spill_size = 0;
1759 HOST_WIDE_INT extra_spill_size = 0;
1760 HOST_WIDE_INT pretend_args_size;
1763 int spilled_gr_p = 0;
1764 int spilled_fr_p = 0;
1768 if (current_frame_info.initialized)
1771 memset (¤t_frame_info, 0, sizeof current_frame_info);
1772 CLEAR_HARD_REG_SET (mask);
1774 /* Don't allocate scratches to the return register. */
1775 diddle_return_value (mark_reg_gr_used_mask, NULL);
1777 /* Don't allocate scratches to the EH scratch registers. */
1778 if (cfun->machine->ia64_eh_epilogue_sp)
1779 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
1780 if (cfun->machine->ia64_eh_epilogue_bsp)
1781 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
1783 /* Find the size of the register stack frame. We have only 80 local
1784 registers, because we reserve 8 for the inputs and 8 for the
1787 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1788 since we'll be adjusting that down later. */
1789 regno = LOC_REG (78) + ! frame_pointer_needed;
1790 for (; regno >= LOC_REG (0); regno--)
1791 if (regs_ever_live[regno])
1793 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
1795 /* For functions marked with the syscall_linkage attribute, we must mark
1796 all eight input registers as in use, so that locals aren't visible to
1799 if (cfun->machine->n_varargs > 0
1800 || lookup_attribute ("syscall_linkage",
1801 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
1802 current_frame_info.n_input_regs = 8;
1805 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
1806 if (regs_ever_live[regno])
1808 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
1811 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
1812 if (regs_ever_live[regno])
1814 i = regno - OUT_REG (0) + 1;
1816 /* When -p profiling, we need one output register for the mcount argument.
1817 Likewise for -a profiling for the bb_init_func argument. For -ax
1818 profiling, we need two output registers for the two bb_init_trace_func
1820 if (current_function_profile)
1822 current_frame_info.n_output_regs = i;
1824 /* ??? No rotating register support yet. */
1825 current_frame_info.n_rotate_regs = 0;
1827 /* Discover which registers need spilling, and how much room that
1828 will take. Begin with floating point and general registers,
1829 which will always wind up on the stack. */
1831 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
1832 if (regs_ever_live[regno] && ! call_used_regs[regno])
1834 SET_HARD_REG_BIT (mask, regno);
1840 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1841 if (regs_ever_live[regno] && ! call_used_regs[regno])
1843 SET_HARD_REG_BIT (mask, regno);
1849 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
1850 if (regs_ever_live[regno] && ! call_used_regs[regno])
1852 SET_HARD_REG_BIT (mask, regno);
1857 /* Now come all special registers that might get saved in other
1858 general registers. */
1860 if (frame_pointer_needed)
1862 current_frame_info.reg_fp = find_gr_spill (1);
1863 /* If we did not get a register, then we take LOC79. This is guaranteed
1864 to be free, even if regs_ever_live is already set, because this is
1865 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1866 as we don't count loc79 above. */
1867 if (current_frame_info.reg_fp == 0)
1869 current_frame_info.reg_fp = LOC_REG (79);
1870 current_frame_info.n_local_regs++;
1874 if (! current_function_is_leaf)
1876 /* Emit a save of BR0 if we call other functions. Do this even
1877 if this function doesn't return, as EH depends on this to be
1878 able to unwind the stack. */
1879 SET_HARD_REG_BIT (mask, BR_REG (0));
1881 current_frame_info.reg_save_b0 = find_gr_spill (1);
1882 if (current_frame_info.reg_save_b0 == 0)
1888 /* Similarly for ar.pfs. */
1889 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1890 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1891 if (current_frame_info.reg_save_ar_pfs == 0)
1893 extra_spill_size += 8;
1897 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1898 registers are clobbered, so we fall back to the stack. */
1899 current_frame_info.reg_save_gp
1900 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
1901 if (current_frame_info.reg_save_gp == 0)
1903 SET_HARD_REG_BIT (mask, GR_REG (1));
1910 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
1912 SET_HARD_REG_BIT (mask, BR_REG (0));
1917 if (regs_ever_live[AR_PFS_REGNUM])
1919 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1920 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1921 if (current_frame_info.reg_save_ar_pfs == 0)
1923 extra_spill_size += 8;
1929 /* Unwind descriptor hackery: things are most efficient if we allocate
1930 consecutive GR save registers for RP, PFS, FP in that order. However,
1931 it is absolutely critical that FP get the only hard register that's
1932 guaranteed to be free, so we allocated it first. If all three did
1933 happen to be allocated hard regs, and are consecutive, rearrange them
1934 into the preferred order now. */
1935 if (current_frame_info.reg_fp != 0
1936 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
1937 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
1939 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
1940 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
1941 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
1944 /* See if we need to store the predicate register block. */
1945 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1946 if (regs_ever_live[regno] && ! call_used_regs[regno])
1948 if (regno <= PR_REG (63))
1950 SET_HARD_REG_BIT (mask, PR_REG (0));
1951 current_frame_info.reg_save_pr = find_gr_spill (1);
1952 if (current_frame_info.reg_save_pr == 0)
1954 extra_spill_size += 8;
1958 /* ??? Mark them all as used so that register renaming and such
1959 are free to use them. */
1960 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1961 regs_ever_live[regno] = 1;
1964 /* If we're forced to use st8.spill, we're forced to save and restore
1965 ar.unat as well. The check for existing liveness allows inline asm
1966 to touch ar.unat. */
1967 if (spilled_gr_p || cfun->machine->n_varargs
1968 || regs_ever_live[AR_UNAT_REGNUM])
1970 regs_ever_live[AR_UNAT_REGNUM] = 1;
1971 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
1972 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
1973 if (current_frame_info.reg_save_ar_unat == 0)
1975 extra_spill_size += 8;
1980 if (regs_ever_live[AR_LC_REGNUM])
1982 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
1983 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
1984 if (current_frame_info.reg_save_ar_lc == 0)
1986 extra_spill_size += 8;
1991 /* If we have an odd number of words of pretend arguments written to
1992 the stack, then the FR save area will be unaligned. We round the
1993 size of this area up to keep things 16 byte aligned. */
1995 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
1997 pretend_args_size = current_function_pretend_args_size;
1999 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2000 + current_function_outgoing_args_size);
2001 total_size = IA64_STACK_ALIGN (total_size);
2003 /* We always use the 16-byte scratch area provided by the caller, but
2004 if we are a leaf function, there's no one to which we need to provide
2006 if (current_function_is_leaf)
2007 total_size = MAX (0, total_size - 16);
2009 current_frame_info.total_size = total_size;
2010 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2011 current_frame_info.spill_size = spill_size;
2012 current_frame_info.extra_spill_size = extra_spill_size;
2013 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2014 current_frame_info.n_spilled = n_spilled;
2015 current_frame_info.initialized = reload_completed;
2018 /* Compute the initial difference between the specified pair of registers. */
2021 ia64_initial_elimination_offset (from, to)
2024 HOST_WIDE_INT offset;
2026 ia64_compute_frame_size (get_frame_size ());
2029 case FRAME_POINTER_REGNUM:
2030 if (to == HARD_FRAME_POINTER_REGNUM)
2032 if (current_function_is_leaf)
2033 offset = -current_frame_info.total_size;
2035 offset = -(current_frame_info.total_size
2036 - current_function_outgoing_args_size - 16);
2038 else if (to == STACK_POINTER_REGNUM)
2040 if (current_function_is_leaf)
2043 offset = 16 + current_function_outgoing_args_size;
2049 case ARG_POINTER_REGNUM:
2050 /* Arguments start above the 16 byte save area, unless stdarg
2051 in which case we store through the 16 byte save area. */
2052 if (to == HARD_FRAME_POINTER_REGNUM)
2053 offset = 16 - current_function_pretend_args_size;
2054 else if (to == STACK_POINTER_REGNUM)
2055 offset = (current_frame_info.total_size
2056 + 16 - current_function_pretend_args_size);
2061 case RETURN_ADDRESS_POINTER_REGNUM:
2072 /* If there are more than a trivial number of register spills, we use
2073 two interleaved iterators so that we can get two memory references
2076 In order to simplify things in the prologue and epilogue expanders,
2077 we use helper functions to fix up the memory references after the
2078 fact with the appropriate offsets to a POST_MODIFY memory mode.
2079 The following data structure tracks the state of the two iterators
2080 while insns are being emitted. */
2082 struct spill_fill_data
2084 rtx init_after; /* point at which to emit initializations */
2085 rtx init_reg[2]; /* initial base register */
2086 rtx iter_reg[2]; /* the iterator registers */
2087 rtx *prev_addr[2]; /* address of last memory use */
2088 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2089 HOST_WIDE_INT prev_off[2]; /* last offset */
2090 int n_iter; /* number of iterators in use */
2091 int next_iter; /* next iterator to use */
2092 unsigned int save_gr_used_mask;
2095 static struct spill_fill_data spill_fill_data;
2098 setup_spill_pointers (n_spills, init_reg, cfa_off)
2101 HOST_WIDE_INT cfa_off;
2105 spill_fill_data.init_after = get_last_insn ();
2106 spill_fill_data.init_reg[0] = init_reg;
2107 spill_fill_data.init_reg[1] = init_reg;
2108 spill_fill_data.prev_addr[0] = NULL;
2109 spill_fill_data.prev_addr[1] = NULL;
2110 spill_fill_data.prev_insn[0] = NULL;
2111 spill_fill_data.prev_insn[1] = NULL;
2112 spill_fill_data.prev_off[0] = cfa_off;
2113 spill_fill_data.prev_off[1] = cfa_off;
2114 spill_fill_data.next_iter = 0;
2115 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2117 spill_fill_data.n_iter = 1 + (n_spills > 2);
2118 for (i = 0; i < spill_fill_data.n_iter; ++i)
2120 int regno = next_scratch_gr_reg ();
2121 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2122 current_frame_info.gr_used_mask |= 1 << regno;
2127 finish_spill_pointers ()
2129 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2133 spill_restore_mem (reg, cfa_off)
2135 HOST_WIDE_INT cfa_off;
2137 int iter = spill_fill_data.next_iter;
2138 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2139 rtx disp_rtx = GEN_INT (disp);
2142 if (spill_fill_data.prev_addr[iter])
2144 if (CONST_OK_FOR_N (disp))
2146 *spill_fill_data.prev_addr[iter]
2147 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2148 gen_rtx_PLUS (DImode,
2149 spill_fill_data.iter_reg[iter],
2151 REG_NOTES (spill_fill_data.prev_insn[iter])
2152 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2153 REG_NOTES (spill_fill_data.prev_insn[iter]));
2157 /* ??? Could use register post_modify for loads. */
2158 if (! CONST_OK_FOR_I (disp))
2160 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2161 emit_move_insn (tmp, disp_rtx);
2164 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2165 spill_fill_data.iter_reg[iter], disp_rtx));
2168 /* Micro-optimization: if we've created a frame pointer, it's at
2169 CFA 0, which may allow the real iterator to be initialized lower,
2170 slightly increasing parallelism. Also, if there are few saves
2171 it may eliminate the iterator entirely. */
2173 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2174 && frame_pointer_needed)
2176 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2177 set_mem_alias_set (mem, get_varargs_alias_set ());
2185 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2186 spill_fill_data.init_reg[iter]);
2191 if (! CONST_OK_FOR_I (disp))
2193 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2194 emit_move_insn (tmp, disp_rtx);
2198 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2199 spill_fill_data.init_reg[iter],
2206 /* Careful for being the first insn in a sequence. */
2207 if (spill_fill_data.init_after)
2208 insn = emit_insn_after (seq, spill_fill_data.init_after);
2211 rtx first = get_insns ();
2213 insn = emit_insn_before (seq, first);
2215 insn = emit_insn (seq);
2217 spill_fill_data.init_after = insn;
2219 /* If DISP is 0, we may or may not have a further adjustment
2220 afterward. If we do, then the load/store insn may be modified
2221 to be a post-modify. If we don't, then this copy may be
2222 eliminated by copyprop_hardreg_forward, which makes this
2223 insn garbage, which runs afoul of the sanity check in
2224 propagate_one_insn. So mark this insn as legal to delete. */
2226 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2230 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2232 /* ??? Not all of the spills are for varargs, but some of them are.
2233 The rest of the spills belong in an alias set of their own. But
2234 it doesn't actually hurt to include them here. */
2235 set_mem_alias_set (mem, get_varargs_alias_set ());
2237 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2238 spill_fill_data.prev_off[iter] = cfa_off;
2240 if (++iter >= spill_fill_data.n_iter)
2242 spill_fill_data.next_iter = iter;
2248 do_spill (move_fn, reg, cfa_off, frame_reg)
2249 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2251 HOST_WIDE_INT cfa_off;
2253 int iter = spill_fill_data.next_iter;
2256 mem = spill_restore_mem (reg, cfa_off);
2257 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2258 spill_fill_data.prev_insn[iter] = insn;
2265 RTX_FRAME_RELATED_P (insn) = 1;
2267 /* Don't even pretend that the unwind code can intuit its way
2268 through a pair of interleaved post_modify iterators. Just
2269 provide the correct answer. */
2271 if (frame_pointer_needed)
2273 base = hard_frame_pointer_rtx;
2278 base = stack_pointer_rtx;
2279 off = current_frame_info.total_size - cfa_off;
2283 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2284 gen_rtx_SET (VOIDmode,
2285 gen_rtx_MEM (GET_MODE (reg),
2286 plus_constant (base, off)),
2293 do_restore (move_fn, reg, cfa_off)
2294 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2296 HOST_WIDE_INT cfa_off;
2298 int iter = spill_fill_data.next_iter;
2301 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2302 GEN_INT (cfa_off)));
2303 spill_fill_data.prev_insn[iter] = insn;
2306 /* Wrapper functions that discards the CONST_INT spill offset. These
2307 exist so that we can give gr_spill/gr_fill the offset they need and
2308 use a consistent function interface. */
2311 gen_movdi_x (dest, src, offset)
2313 rtx offset ATTRIBUTE_UNUSED;
2315 return gen_movdi (dest, src);
2319 gen_fr_spill_x (dest, src, offset)
2321 rtx offset ATTRIBUTE_UNUSED;
2323 return gen_fr_spill (dest, src);
2327 gen_fr_restore_x (dest, src, offset)
2329 rtx offset ATTRIBUTE_UNUSED;
2331 return gen_fr_restore (dest, src);
2334 /* Called after register allocation to add any instructions needed for the
2335 prologue. Using a prologue insn is favored compared to putting all of the
2336 instructions in output_function_prologue(), since it allows the scheduler
2337 to intermix instructions with the saves of the caller saved registers. In
2338 some cases, it might be necessary to emit a barrier instruction as the last
2339 insn to prevent such scheduling.
2341 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2342 so that the debug info generation code can handle them properly.
2344 The register save area is layed out like so:
2346 [ varargs spill area ]
2347 [ fr register spill area ]
2348 [ br register spill area ]
2349 [ ar register spill area ]
2350 [ pr register spill area ]
2351 [ gr register spill area ] */
2353 /* ??? Get inefficient code when the frame size is larger than can fit in an
2354 adds instruction. */
2357 ia64_expand_prologue ()
2359 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2360 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2363 ia64_compute_frame_size (get_frame_size ());
2364 last_scratch_gr_reg = 15;
2366 /* If there is no epilogue, then we don't need some prologue insns.
2367 We need to avoid emitting the dead prologue insns, because flow
2368 will complain about them. */
2373 for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
2374 if ((e->flags & EDGE_FAKE) == 0
2375 && (e->flags & EDGE_FALLTHRU) != 0)
2377 epilogue_p = (e != NULL);
2382 /* Set the local, input, and output register names. We need to do this
2383 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2384 half. If we use in/loc/out register names, then we get assembler errors
2385 in crtn.S because there is no alloc insn or regstk directive in there. */
2386 if (! TARGET_REG_NAMES)
2388 int inputs = current_frame_info.n_input_regs;
2389 int locals = current_frame_info.n_local_regs;
2390 int outputs = current_frame_info.n_output_regs;
2392 for (i = 0; i < inputs; i++)
2393 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2394 for (i = 0; i < locals; i++)
2395 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2396 for (i = 0; i < outputs; i++)
2397 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2400 /* Set the frame pointer register name. The regnum is logically loc79,
2401 but of course we'll not have allocated that many locals. Rather than
2402 worrying about renumbering the existing rtxs, we adjust the name. */
2403 /* ??? This code means that we can never use one local register when
2404 there is a frame pointer. loc79 gets wasted in this case, as it is
2405 renamed to a register that will never be used. See also the try_locals
2406 code in find_gr_spill. */
2407 if (current_frame_info.reg_fp)
2409 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2410 reg_names[HARD_FRAME_POINTER_REGNUM]
2411 = reg_names[current_frame_info.reg_fp];
2412 reg_names[current_frame_info.reg_fp] = tmp;
2415 /* Fix up the return address placeholder. */
2416 /* ??? We can fail if __builtin_return_address is used, and we didn't
2417 allocate a register in which to save b0. I can't think of a way to
2418 eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
2419 then be sure that I got the right one. Further, reload doesn't seem
2420 to care if an eliminable register isn't used, and "eliminates" it
2422 if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
2423 && current_frame_info.reg_save_b0 != 0)
2424 XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
2426 /* We don't need an alloc instruction if we've used no outputs or locals. */
2427 if (current_frame_info.n_local_regs == 0
2428 && current_frame_info.n_output_regs == 0
2429 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2430 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2432 /* If there is no alloc, but there are input registers used, then we
2433 need a .regstk directive. */
2434 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2435 ar_pfs_save_reg = NULL_RTX;
2439 current_frame_info.need_regstk = 0;
2441 if (current_frame_info.reg_save_ar_pfs)
2442 regno = current_frame_info.reg_save_ar_pfs;
2444 regno = next_scratch_gr_reg ();
2445 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2447 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2448 GEN_INT (current_frame_info.n_input_regs),
2449 GEN_INT (current_frame_info.n_local_regs),
2450 GEN_INT (current_frame_info.n_output_regs),
2451 GEN_INT (current_frame_info.n_rotate_regs)));
2452 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2455 /* Set up frame pointer, stack pointer, and spill iterators. */
2457 n_varargs = cfun->machine->n_varargs;
2458 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2459 stack_pointer_rtx, 0);
2461 if (frame_pointer_needed)
2463 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2464 RTX_FRAME_RELATED_P (insn) = 1;
2467 if (current_frame_info.total_size != 0)
2469 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2472 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2473 offset = frame_size_rtx;
2476 regno = next_scratch_gr_reg ();
2477 offset = gen_rtx_REG (DImode, regno);
2478 emit_move_insn (offset, frame_size_rtx);
2481 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2482 stack_pointer_rtx, offset));
2484 if (! frame_pointer_needed)
2486 RTX_FRAME_RELATED_P (insn) = 1;
2487 if (GET_CODE (offset) != CONST_INT)
2490 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2491 gen_rtx_SET (VOIDmode,
2493 gen_rtx_PLUS (DImode,
2500 /* ??? At this point we must generate a magic insn that appears to
2501 modify the stack pointer, the frame pointer, and all spill
2502 iterators. This would allow the most scheduling freedom. For
2503 now, just hard stop. */
2504 emit_insn (gen_blockage ());
2507 /* Must copy out ar.unat before doing any integer spills. */
2508 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2510 if (current_frame_info.reg_save_ar_unat)
2512 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2515 alt_regno = next_scratch_gr_reg ();
2516 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2517 current_frame_info.gr_used_mask |= 1 << alt_regno;
2520 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2521 insn = emit_move_insn (ar_unat_save_reg, reg);
2522 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2524 /* Even if we're not going to generate an epilogue, we still
2525 need to save the register so that EH works. */
2526 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2527 emit_insn (gen_prologue_use (ar_unat_save_reg));
2530 ar_unat_save_reg = NULL_RTX;
2532 /* Spill all varargs registers. Do this before spilling any GR registers,
2533 since we want the UNAT bits for the GR registers to override the UNAT
2534 bits from varargs, which we don't care about. */
2537 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2539 reg = gen_rtx_REG (DImode, regno);
2540 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2543 /* Locate the bottom of the register save area. */
2544 cfa_off = (current_frame_info.spill_cfa_off
2545 + current_frame_info.spill_size
2546 + current_frame_info.extra_spill_size);
2548 /* Save the predicate register block either in a register or in memory. */
2549 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2551 reg = gen_rtx_REG (DImode, PR_REG (0));
2552 if (current_frame_info.reg_save_pr != 0)
2554 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2555 insn = emit_move_insn (alt_reg, reg);
2557 /* ??? Denote pr spill/fill by a DImode move that modifies all
2558 64 hard registers. */
2559 RTX_FRAME_RELATED_P (insn) = 1;
2561 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2562 gen_rtx_SET (VOIDmode, alt_reg, reg),
2565 /* Even if we're not going to generate an epilogue, we still
2566 need to save the register so that EH works. */
2568 emit_insn (gen_prologue_use (alt_reg));
2572 alt_regno = next_scratch_gr_reg ();
2573 alt_reg = gen_rtx_REG (DImode, alt_regno);
2574 insn = emit_move_insn (alt_reg, reg);
2575 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2580 /* Handle AR regs in numerical order. All of them get special handling. */
2581 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2582 && current_frame_info.reg_save_ar_unat == 0)
2584 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2585 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2589 /* The alloc insn already copied ar.pfs into a general register. The
2590 only thing we have to do now is copy that register to a stack slot
2591 if we'd not allocated a local register for the job. */
2592 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2593 && current_frame_info.reg_save_ar_pfs == 0)
2595 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2596 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2600 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2602 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2603 if (current_frame_info.reg_save_ar_lc != 0)
2605 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2606 insn = emit_move_insn (alt_reg, reg);
2607 RTX_FRAME_RELATED_P (insn) = 1;
2609 /* Even if we're not going to generate an epilogue, we still
2610 need to save the register so that EH works. */
2612 emit_insn (gen_prologue_use (alt_reg));
2616 alt_regno = next_scratch_gr_reg ();
2617 alt_reg = gen_rtx_REG (DImode, alt_regno);
2618 emit_move_insn (alt_reg, reg);
2619 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2624 if (current_frame_info.reg_save_gp)
2626 insn = emit_move_insn (gen_rtx_REG (DImode,
2627 current_frame_info.reg_save_gp),
2628 pic_offset_table_rtx);
2629 /* We don't know for sure yet if this is actually needed, since
2630 we've not split the PIC call patterns. If all of the calls
2631 are indirect, and not followed by any uses of the gp, then
2632 this save is dead. Allow it to go away. */
2634 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2637 /* We should now be at the base of the gr/br/fr spill area. */
2638 if (cfa_off != (current_frame_info.spill_cfa_off
2639 + current_frame_info.spill_size))
2642 /* Spill all general registers. */
2643 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2644 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2646 reg = gen_rtx_REG (DImode, regno);
2647 do_spill (gen_gr_spill, reg, cfa_off, reg);
2651 /* Handle BR0 specially -- it may be getting stored permanently in
2652 some GR register. */
2653 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2655 reg = gen_rtx_REG (DImode, BR_REG (0));
2656 if (current_frame_info.reg_save_b0 != 0)
2658 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2659 insn = emit_move_insn (alt_reg, reg);
2660 RTX_FRAME_RELATED_P (insn) = 1;
2662 /* Even if we're not going to generate an epilogue, we still
2663 need to save the register so that EH works. */
2665 emit_insn (gen_prologue_use (alt_reg));
2669 alt_regno = next_scratch_gr_reg ();
2670 alt_reg = gen_rtx_REG (DImode, alt_regno);
2671 emit_move_insn (alt_reg, reg);
2672 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2677 /* Spill the rest of the BR registers. */
2678 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2679 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2681 alt_regno = next_scratch_gr_reg ();
2682 alt_reg = gen_rtx_REG (DImode, alt_regno);
2683 reg = gen_rtx_REG (DImode, regno);
2684 emit_move_insn (alt_reg, reg);
2685 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2689 /* Align the frame and spill all FR registers. */
2690 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2691 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2695 reg = gen_rtx_REG (TFmode, regno);
2696 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2700 if (cfa_off != current_frame_info.spill_cfa_off)
2703 finish_spill_pointers ();
2706 /* Called after register allocation to add any instructions needed for the
2707 epilogue. Using an epilogue insn is favored compared to putting all of the
2708 instructions in output_function_prologue(), since it allows the scheduler
2709 to intermix instructions with the saves of the caller saved registers. In
2710 some cases, it might be necessary to emit a barrier instruction as the last
2711 insn to prevent such scheduling. */
2714 ia64_expand_epilogue (sibcall_p)
2717 rtx insn, reg, alt_reg, ar_unat_save_reg;
2718 int regno, alt_regno, cfa_off;
2720 ia64_compute_frame_size (get_frame_size ());
2722 /* If there is a frame pointer, then we use it instead of the stack
2723 pointer, so that the stack pointer does not need to be valid when
2724 the epilogue starts. See EXIT_IGNORE_STACK. */
2725 if (frame_pointer_needed)
2726 setup_spill_pointers (current_frame_info.n_spilled,
2727 hard_frame_pointer_rtx, 0);
2729 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2730 current_frame_info.total_size);
2732 if (current_frame_info.total_size != 0)
2734 /* ??? At this point we must generate a magic insn that appears to
2735 modify the spill iterators and the frame pointer. This would
2736 allow the most scheduling freedom. For now, just hard stop. */
2737 emit_insn (gen_blockage ());
2740 /* Locate the bottom of the register save area. */
2741 cfa_off = (current_frame_info.spill_cfa_off
2742 + current_frame_info.spill_size
2743 + current_frame_info.extra_spill_size);
2745 /* Restore the predicate registers. */
2746 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2748 if (current_frame_info.reg_save_pr != 0)
2749 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2752 alt_regno = next_scratch_gr_reg ();
2753 alt_reg = gen_rtx_REG (DImode, alt_regno);
2754 do_restore (gen_movdi_x, alt_reg, cfa_off);
2757 reg = gen_rtx_REG (DImode, PR_REG (0));
2758 emit_move_insn (reg, alt_reg);
2761 /* Restore the application registers. */
2763 /* Load the saved unat from the stack, but do not restore it until
2764 after the GRs have been restored. */
2765 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2767 if (current_frame_info.reg_save_ar_unat != 0)
2769 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2772 alt_regno = next_scratch_gr_reg ();
2773 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2774 current_frame_info.gr_used_mask |= 1 << alt_regno;
2775 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
2780 ar_unat_save_reg = NULL_RTX;
2782 if (current_frame_info.reg_save_ar_pfs != 0)
2784 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
2785 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2786 emit_move_insn (reg, alt_reg);
2788 else if (! current_function_is_leaf)
2790 alt_regno = next_scratch_gr_reg ();
2791 alt_reg = gen_rtx_REG (DImode, alt_regno);
2792 do_restore (gen_movdi_x, alt_reg, cfa_off);
2794 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2795 emit_move_insn (reg, alt_reg);
2798 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2800 if (current_frame_info.reg_save_ar_lc != 0)
2801 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2804 alt_regno = next_scratch_gr_reg ();
2805 alt_reg = gen_rtx_REG (DImode, alt_regno);
2806 do_restore (gen_movdi_x, alt_reg, cfa_off);
2809 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2810 emit_move_insn (reg, alt_reg);
2813 /* We should now be at the base of the gr/br/fr spill area. */
2814 if (cfa_off != (current_frame_info.spill_cfa_off
2815 + current_frame_info.spill_size))
2818 /* The GP may be stored on the stack in the prologue, but it's
2819 never restored in the epilogue. Skip the stack slot. */
2820 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
2823 /* Restore all general registers. */
2824 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
2825 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2827 reg = gen_rtx_REG (DImode, regno);
2828 do_restore (gen_gr_restore, reg, cfa_off);
2832 /* Restore the branch registers. Handle B0 specially, as it may
2833 have gotten stored in some GR register. */
2834 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2836 if (current_frame_info.reg_save_b0 != 0)
2837 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2840 alt_regno = next_scratch_gr_reg ();
2841 alt_reg = gen_rtx_REG (DImode, alt_regno);
2842 do_restore (gen_movdi_x, alt_reg, cfa_off);
2845 reg = gen_rtx_REG (DImode, BR_REG (0));
2846 emit_move_insn (reg, alt_reg);
2849 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2850 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2852 alt_regno = next_scratch_gr_reg ();
2853 alt_reg = gen_rtx_REG (DImode, alt_regno);
2854 do_restore (gen_movdi_x, alt_reg, cfa_off);
2856 reg = gen_rtx_REG (DImode, regno);
2857 emit_move_insn (reg, alt_reg);
2860 /* Restore floating point registers. */
2861 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2862 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2866 reg = gen_rtx_REG (TFmode, regno);
2867 do_restore (gen_fr_restore_x, reg, cfa_off);
2871 /* Restore ar.unat for real. */
2872 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2874 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2875 emit_move_insn (reg, ar_unat_save_reg);
2878 if (cfa_off != current_frame_info.spill_cfa_off)
2881 finish_spill_pointers ();
2883 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
2885 /* ??? At this point we must generate a magic insn that appears to
2886 modify the spill iterators, the stack pointer, and the frame
2887 pointer. This would allow the most scheduling freedom. For now,
2889 emit_insn (gen_blockage ());
2892 if (cfun->machine->ia64_eh_epilogue_sp)
2893 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
2894 else if (frame_pointer_needed)
2896 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
2897 RTX_FRAME_RELATED_P (insn) = 1;
2899 else if (current_frame_info.total_size)
2901 rtx offset, frame_size_rtx;
2903 frame_size_rtx = GEN_INT (current_frame_info.total_size);
2904 if (CONST_OK_FOR_I (current_frame_info.total_size))
2905 offset = frame_size_rtx;
2908 regno = next_scratch_gr_reg ();
2909 offset = gen_rtx_REG (DImode, regno);
2910 emit_move_insn (offset, frame_size_rtx);
2913 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
2916 RTX_FRAME_RELATED_P (insn) = 1;
2917 if (GET_CODE (offset) != CONST_INT)
2920 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2921 gen_rtx_SET (VOIDmode,
2923 gen_rtx_PLUS (DImode,
2930 if (cfun->machine->ia64_eh_epilogue_bsp)
2931 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
2934 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
2937 int fp = GR_REG (2);
2938 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2939 first available call clobbered register. If there was a frame_pointer
2940 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2941 so we have to make sure we're using the string "r2" when emitting
2942 the register name for the assembler. */
2943 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
2944 fp = HARD_FRAME_POINTER_REGNUM;
2946 /* We must emit an alloc to force the input registers to become output
2947 registers. Otherwise, if the callee tries to pass its parameters
2948 through to another call without an intervening alloc, then these
2950 /* ??? We don't need to preserve all input registers. We only need to
2951 preserve those input registers used as arguments to the sibling call.
2952 It is unclear how to compute that number here. */
2953 if (current_frame_info.n_input_regs != 0)
2954 emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
2955 GEN_INT (0), GEN_INT (0),
2956 GEN_INT (current_frame_info.n_input_regs),
2961 /* Return 1 if br.ret can do all the work required to return from a
2965 ia64_direct_return ()
2967 if (reload_completed && ! frame_pointer_needed)
2969 ia64_compute_frame_size (get_frame_size ());
2971 return (current_frame_info.total_size == 0
2972 && current_frame_info.n_spilled == 0
2973 && current_frame_info.reg_save_b0 == 0
2974 && current_frame_info.reg_save_pr == 0
2975 && current_frame_info.reg_save_ar_pfs == 0
2976 && current_frame_info.reg_save_ar_unat == 0
2977 && current_frame_info.reg_save_ar_lc == 0);
2983 ia64_hard_regno_rename_ok (from, to)
2987 /* Don't clobber any of the registers we reserved for the prologue. */
2988 if (to == current_frame_info.reg_fp
2989 || to == current_frame_info.reg_save_b0
2990 || to == current_frame_info.reg_save_pr
2991 || to == current_frame_info.reg_save_ar_pfs
2992 || to == current_frame_info.reg_save_ar_unat
2993 || to == current_frame_info.reg_save_ar_lc)
2996 if (from == current_frame_info.reg_fp
2997 || from == current_frame_info.reg_save_b0
2998 || from == current_frame_info.reg_save_pr
2999 || from == current_frame_info.reg_save_ar_pfs
3000 || from == current_frame_info.reg_save_ar_unat
3001 || from == current_frame_info.reg_save_ar_lc)
3004 /* Don't use output registers outside the register frame. */
3005 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3008 /* Retain even/oddness on predicate register pairs. */
3009 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3010 return (from & 1) == (to & 1);
3015 /* Target hook for assembling integer objects. Handle word-sized
3016 aligned objects and detect the cases when @fptr is needed. */
3019 ia64_assemble_integer (x, size, aligned_p)
3024 if (size == (TARGET_ILP32 ? 4 : 8)
3026 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3027 && GET_CODE (x) == SYMBOL_REF
3028 && SYMBOL_REF_FUNCTION_P (x))
3031 fputs ("\tdata4\t@fptr(", asm_out_file);
3033 fputs ("\tdata8\t@fptr(", asm_out_file);
3034 output_addr_const (asm_out_file, x);
3035 fputs (")\n", asm_out_file);
3038 return default_assemble_integer (x, size, aligned_p);
3041 /* Emit the function prologue. */
3044 ia64_output_function_prologue (file, size)
3046 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3048 int mask, grsave, grsave_prev;
3050 if (current_frame_info.need_regstk)
3051 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3052 current_frame_info.n_input_regs,
3053 current_frame_info.n_local_regs,
3054 current_frame_info.n_output_regs,
3055 current_frame_info.n_rotate_regs);
3057 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3060 /* Emit the .prologue directive. */
3063 grsave = grsave_prev = 0;
3064 if (current_frame_info.reg_save_b0 != 0)
3067 grsave = grsave_prev = current_frame_info.reg_save_b0;
3069 if (current_frame_info.reg_save_ar_pfs != 0
3070 && (grsave_prev == 0
3071 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3074 if (grsave_prev == 0)
3075 grsave = current_frame_info.reg_save_ar_pfs;
3076 grsave_prev = current_frame_info.reg_save_ar_pfs;
3078 if (current_frame_info.reg_fp != 0
3079 && (grsave_prev == 0
3080 || current_frame_info.reg_fp == grsave_prev + 1))
3083 if (grsave_prev == 0)
3084 grsave = HARD_FRAME_POINTER_REGNUM;
3085 grsave_prev = current_frame_info.reg_fp;
3087 if (current_frame_info.reg_save_pr != 0
3088 && (grsave_prev == 0
3089 || current_frame_info.reg_save_pr == grsave_prev + 1))
3092 if (grsave_prev == 0)
3093 grsave = current_frame_info.reg_save_pr;
3097 fprintf (file, "\t.prologue %d, %d\n", mask,
3098 ia64_dbx_register_number (grsave));
3100 fputs ("\t.prologue\n", file);
3102 /* Emit a .spill directive, if necessary, to relocate the base of
3103 the register spill area. */
3104 if (current_frame_info.spill_cfa_off != -16)
3105 fprintf (file, "\t.spill %ld\n",
3106 (long) (current_frame_info.spill_cfa_off
3107 + current_frame_info.spill_size));
3110 /* Emit the .body directive at the scheduled end of the prologue. */
3113 ia64_output_function_end_prologue (file)
3116 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3119 fputs ("\t.body\n", file);
3122 /* Emit the function epilogue. */
3125 ia64_output_function_epilogue (file, size)
3126 FILE *file ATTRIBUTE_UNUSED;
3127 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3131 /* Reset from the function's potential modifications. */
3132 XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
3134 if (current_frame_info.reg_fp)
3136 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3137 reg_names[HARD_FRAME_POINTER_REGNUM]
3138 = reg_names[current_frame_info.reg_fp];
3139 reg_names[current_frame_info.reg_fp] = tmp;
3141 if (! TARGET_REG_NAMES)
3143 for (i = 0; i < current_frame_info.n_input_regs; i++)
3144 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3145 for (i = 0; i < current_frame_info.n_local_regs; i++)
3146 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3147 for (i = 0; i < current_frame_info.n_output_regs; i++)
3148 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3151 current_frame_info.initialized = 0;
3155 ia64_dbx_register_number (regno)
3158 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3159 from its home at loc79 to something inside the register frame. We
3160 must perform the same renumbering here for the debug info. */
3161 if (current_frame_info.reg_fp)
3163 if (regno == HARD_FRAME_POINTER_REGNUM)
3164 regno = current_frame_info.reg_fp;
3165 else if (regno == current_frame_info.reg_fp)
3166 regno = HARD_FRAME_POINTER_REGNUM;
3169 if (IN_REGNO_P (regno))
3170 return 32 + regno - IN_REG (0);
3171 else if (LOC_REGNO_P (regno))
3172 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3173 else if (OUT_REGNO_P (regno))
3174 return (32 + current_frame_info.n_input_regs
3175 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3181 ia64_initialize_trampoline (addr, fnaddr, static_chain)
3182 rtx addr, fnaddr, static_chain;
3184 rtx addr_reg, eight = GEN_INT (8);
3186 /* Load up our iterator. */
3187 addr_reg = gen_reg_rtx (Pmode);
3188 emit_move_insn (addr_reg, addr);
3190 /* The first two words are the fake descriptor:
3191 __ia64_trampoline, ADDR+16. */
3192 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3193 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3194 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3196 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3197 copy_to_reg (plus_constant (addr, 16)));
3198 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3200 /* The third word is the target descriptor. */
3201 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3202 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3204 /* The fourth word is the static chain. */
3205 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3208 /* Do any needed setup for a variadic function. CUM has not been updated
3209 for the last named argument which has type TYPE and mode MODE.
3211 We generate the actual spill instructions during prologue generation. */
3214 ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
3215 CUMULATIVE_ARGS cum;
3219 int second_time ATTRIBUTE_UNUSED;
3221 /* Skip the current argument. */
3222 ia64_function_arg_advance (&cum, int_mode, type, 1);
3224 if (cum.words < MAX_ARGUMENT_SLOTS)
3226 int n = MAX_ARGUMENT_SLOTS - cum.words;
3227 *pretend_size = n * UNITS_PER_WORD;
3228 cfun->machine->n_varargs = n;
3232 /* Check whether TYPE is a homogeneous floating point aggregate. If
3233 it is, return the mode of the floating point type that appears
3234 in all leafs. If it is not, return VOIDmode.
3236 An aggregate is a homogeneous floating point aggregate is if all
3237 fields/elements in it have the same floating point type (e.g,
3238 SFmode). 128-bit quad-precision floats are excluded. */
3240 static enum machine_mode
3241 hfa_element_mode (type, nested)
3245 enum machine_mode element_mode = VOIDmode;
3246 enum machine_mode mode;
3247 enum tree_code code = TREE_CODE (type);
3248 int know_element_mode = 0;
3253 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3254 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3255 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3256 case FILE_TYPE: case SET_TYPE: case LANG_TYPE:
3260 /* Fortran complex types are supposed to be HFAs, so we need to handle
3261 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3264 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3265 && (TYPE_MODE (type) != TCmode || INTEL_EXTENDED_IEEE_FORMAT))
3266 return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type))
3267 * BITS_PER_UNIT, MODE_FLOAT, 0);
3272 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3273 mode if this is contained within an aggregate. */
3274 if (nested && (TYPE_MODE (type) != TFmode || INTEL_EXTENDED_IEEE_FORMAT))
3275 return TYPE_MODE (type);
3280 return hfa_element_mode (TREE_TYPE (type), 1);
3284 case QUAL_UNION_TYPE:
3285 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3287 if (TREE_CODE (t) != FIELD_DECL)
3290 mode = hfa_element_mode (TREE_TYPE (t), 1);
3291 if (know_element_mode)
3293 if (mode != element_mode)
3296 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3300 know_element_mode = 1;
3301 element_mode = mode;
3304 return element_mode;
3307 /* If we reach here, we probably have some front-end specific type
3308 that the backend doesn't know about. This can happen via the
3309 aggregate_value_p call in init_function_start. All we can do is
3310 ignore unknown tree types. */
3317 /* Return rtx for register where argument is passed, or zero if it is passed
3320 /* ??? 128-bit quad-precision floats are always passed in general
3324 ia64_function_arg (cum, mode, type, named, incoming)
3325 CUMULATIVE_ARGS *cum;
3326 enum machine_mode mode;
3331 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3332 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3333 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3336 enum machine_mode hfa_mode = VOIDmode;
3338 /* Integer and float arguments larger than 8 bytes start at the next even
3339 boundary. Aggregates larger than 8 bytes start at the next even boundary
3340 if the aggregate has 16 byte alignment. Net effect is that types with
3341 alignment greater than 8 start at the next even boundary. */
3342 /* ??? The ABI does not specify how to handle aggregates with alignment from
3343 9 to 15 bytes, or greater than 16. We handle them all as if they had
3344 16 byte alignment. Such aggregates can occur only if gcc extensions are
3346 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3348 && (cum->words & 1))
3351 /* If all argument slots are used, then it must go on the stack. */
3352 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3355 /* Check for and handle homogeneous FP aggregates. */
3357 hfa_mode = hfa_element_mode (type, 0);
3359 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3360 and unprototyped hfas are passed specially. */
3361 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3365 int fp_regs = cum->fp_regs;
3366 int int_regs = cum->words + offset;
3367 int hfa_size = GET_MODE_SIZE (hfa_mode);
3371 /* If prototyped, pass it in FR regs then GR regs.
3372 If not prototyped, pass it in both FR and GR regs.
3374 If this is an SFmode aggregate, then it is possible to run out of
3375 FR regs while GR regs are still left. In that case, we pass the
3376 remaining part in the GR regs. */
3378 /* Fill the FP regs. We do this always. We stop if we reach the end
3379 of the argument, the last FP register, or the last argument slot. */
3381 byte_size = ((mode == BLKmode)
3382 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3383 args_byte_size = int_regs * UNITS_PER_WORD;
3385 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3386 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3388 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3389 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3393 args_byte_size += hfa_size;
3397 /* If no prototype, then the whole thing must go in GR regs. */
3398 if (! cum->prototype)
3400 /* If this is an SFmode aggregate, then we might have some left over
3401 that needs to go in GR regs. */
3402 else if (byte_size != offset)
3403 int_regs += offset / UNITS_PER_WORD;
3405 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3407 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3409 enum machine_mode gr_mode = DImode;
3411 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3412 then this goes in a GR reg left adjusted/little endian, right
3413 adjusted/big endian. */
3414 /* ??? Currently this is handled wrong, because 4-byte hunks are
3415 always right adjusted/little endian. */
3418 /* If we have an even 4 byte hunk because the aggregate is a
3419 multiple of 4 bytes in size, then this goes in a GR reg right
3420 adjusted/little endian. */
3421 else if (byte_size - offset == 4)
3423 /* Complex floats need to have float mode. */
3424 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3427 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3428 gen_rtx_REG (gr_mode, (basereg
3431 offset += GET_MODE_SIZE (gr_mode);
3432 int_regs += GET_MODE_SIZE (gr_mode) <= UNITS_PER_WORD
3433 ? 1 : GET_MODE_SIZE (gr_mode) / UNITS_PER_WORD;
3436 /* If we ended up using just one location, just return that one loc. */
3438 return XEXP (loc[0], 0);
3440 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3443 /* Integral and aggregates go in general registers. If we have run out of
3444 FR registers, then FP values must also go in general registers. This can
3445 happen when we have a SFmode HFA. */
3446 else if (((mode == TFmode) && ! INTEL_EXTENDED_IEEE_FORMAT)
3447 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3449 int byte_size = ((mode == BLKmode)
3450 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3451 if (BYTES_BIG_ENDIAN
3452 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3453 && byte_size < UNITS_PER_WORD
3456 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3457 gen_rtx_REG (DImode,
3458 (basereg + cum->words
3461 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3464 return gen_rtx_REG (mode, basereg + cum->words + offset);
3468 /* If there is a prototype, then FP values go in a FR register when
3469 named, and in a GR register when unnamed. */
3470 else if (cum->prototype)
3473 return gen_rtx_REG (mode, basereg + cum->words + offset);
3475 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3477 /* If there is no prototype, then FP values go in both FR and GR
3481 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3482 gen_rtx_REG (mode, (FR_ARG_FIRST
3485 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3487 (basereg + cum->words
3491 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3495 /* Return number of words, at the beginning of the argument, that must be
3496 put in registers. 0 is the argument is entirely in registers or entirely
3500 ia64_function_arg_partial_nregs (cum, mode, type, named)
3501 CUMULATIVE_ARGS *cum;
3502 enum machine_mode mode;
3504 int named ATTRIBUTE_UNUSED;
3506 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3507 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3511 /* Arguments with alignment larger than 8 bytes start at the next even
3513 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3515 && (cum->words & 1))
3518 /* If all argument slots are used, then it must go on the stack. */
3519 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3522 /* It doesn't matter whether the argument goes in FR or GR regs. If
3523 it fits within the 8 argument slots, then it goes entirely in
3524 registers. If it extends past the last argument slot, then the rest
3525 goes on the stack. */
3527 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3530 return MAX_ARGUMENT_SLOTS - cum->words - offset;
3533 /* Update CUM to point after this argument. This is patterned after
3534 ia64_function_arg. */
3537 ia64_function_arg_advance (cum, mode, type, named)
3538 CUMULATIVE_ARGS *cum;
3539 enum machine_mode mode;
3543 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3544 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3547 enum machine_mode hfa_mode = VOIDmode;
3549 /* If all arg slots are already full, then there is nothing to do. */
3550 if (cum->words >= MAX_ARGUMENT_SLOTS)
3553 /* Arguments with alignment larger than 8 bytes start at the next even
3555 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3557 && (cum->words & 1))
3560 cum->words += words + offset;
3562 /* Check for and handle homogeneous FP aggregates. */
3564 hfa_mode = hfa_element_mode (type, 0);
3566 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3567 and unprototyped hfas are passed specially. */
3568 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3570 int fp_regs = cum->fp_regs;
3571 /* This is the original value of cum->words + offset. */
3572 int int_regs = cum->words - words;
3573 int hfa_size = GET_MODE_SIZE (hfa_mode);
3577 /* If prototyped, pass it in FR regs then GR regs.
3578 If not prototyped, pass it in both FR and GR regs.
3580 If this is an SFmode aggregate, then it is possible to run out of
3581 FR regs while GR regs are still left. In that case, we pass the
3582 remaining part in the GR regs. */
3584 /* Fill the FP regs. We do this always. We stop if we reach the end
3585 of the argument, the last FP register, or the last argument slot. */
3587 byte_size = ((mode == BLKmode)
3588 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3589 args_byte_size = int_regs * UNITS_PER_WORD;
3591 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3592 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3595 args_byte_size += hfa_size;
3599 cum->fp_regs = fp_regs;
3602 /* Integral and aggregates go in general registers. If we have run out of
3603 FR registers, then FP values must also go in general registers. This can
3604 happen when we have a SFmode HFA. */
3605 else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
3606 cum->int_regs = cum->words;
3608 /* If there is a prototype, then FP values go in a FR register when
3609 named, and in a GR register when unnamed. */
3610 else if (cum->prototype)
3613 cum->int_regs = cum->words;
3615 /* ??? Complex types should not reach here. */
3616 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3618 /* If there is no prototype, then FP values go in both FR and GR
3622 /* ??? Complex types should not reach here. */
3623 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3624 cum->int_regs = cum->words;
3628 /* Variable sized types are passed by reference. */
3629 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3632 ia64_function_arg_pass_by_reference (cum, mode, type, named)
3633 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3634 enum machine_mode mode ATTRIBUTE_UNUSED;
3636 int named ATTRIBUTE_UNUSED;
3638 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3641 /* True if it is OK to do sibling call optimization for the specified
3642 call expression EXP. DECL will be the called function, or NULL if
3643 this is an indirect call. */
3645 ia64_function_ok_for_sibcall (decl, exp)
3647 tree exp ATTRIBUTE_UNUSED;
3649 /* Direct calls are always ok. */
3653 /* If TARGET_CONST_GP is in effect, then our caller expects us to
3654 return with our current GP. This means that we'll always have
3655 a GP reload after an indirect call. */
3656 return !ia64_epilogue_uses (R_GR (1));
3660 /* Implement va_arg. */
3663 ia64_va_arg (valist, type)
3668 /* Variable sized types are passed by reference. */
3669 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3671 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
3672 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
3675 /* Arguments with alignment larger than 8 bytes start at the next even
3677 if (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3679 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3680 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3681 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3682 build_int_2 (-2 * UNITS_PER_WORD, -1));
3683 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3684 TREE_SIDE_EFFECTS (t) = 1;
3685 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3688 return std_expand_builtin_va_arg (valist, type);
3691 /* Return 1 if function return value returned in memory. Return 0 if it is
3695 ia64_return_in_memory (valtype)
3698 enum machine_mode mode;
3699 enum machine_mode hfa_mode;
3700 HOST_WIDE_INT byte_size;
3702 mode = TYPE_MODE (valtype);
3703 byte_size = GET_MODE_SIZE (mode);
3704 if (mode == BLKmode)
3706 byte_size = int_size_in_bytes (valtype);
3711 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3713 hfa_mode = hfa_element_mode (valtype, 0);
3714 if (hfa_mode != VOIDmode)
3716 int hfa_size = GET_MODE_SIZE (hfa_mode);
3718 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
3723 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
3729 /* Return rtx for register that holds the function return value. */
3732 ia64_function_value (valtype, func)
3734 tree func ATTRIBUTE_UNUSED;
3736 enum machine_mode mode;
3737 enum machine_mode hfa_mode;
3739 mode = TYPE_MODE (valtype);
3740 hfa_mode = hfa_element_mode (valtype, 0);
3742 if (hfa_mode != VOIDmode)
3750 hfa_size = GET_MODE_SIZE (hfa_mode);
3751 byte_size = ((mode == BLKmode)
3752 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
3754 for (i = 0; offset < byte_size; i++)
3756 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3757 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
3763 return XEXP (loc[0], 0);
3765 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3767 else if (FLOAT_TYPE_P (valtype) &&
3768 ((mode != TFmode) || INTEL_EXTENDED_IEEE_FORMAT))
3769 return gen_rtx_REG (mode, FR_ARG_FIRST);
3772 if (BYTES_BIG_ENDIAN
3773 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
3781 bytesize = int_size_in_bytes (valtype);
3782 for (i = 0; offset < bytesize; i++)
3784 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3785 gen_rtx_REG (DImode,
3788 offset += UNITS_PER_WORD;
3790 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3793 return gen_rtx_REG (mode, GR_RET_FIRST);
3797 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3798 We need to emit DTP-relative relocations. */
3801 ia64_output_dwarf_dtprel (file, size, x)
3808 fputs ("\tdata8.ua\t@dtprel(", file);
3809 output_addr_const (file, x);
3813 /* Print a memory address as an operand to reference that memory location. */
3815 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3816 also call this from ia64_print_operand for memory addresses. */
3819 ia64_print_operand_address (stream, address)
3820 FILE * stream ATTRIBUTE_UNUSED;
3821 rtx address ATTRIBUTE_UNUSED;
3825 /* Print an operand to an assembler instruction.
3826 C Swap and print a comparison operator.
3827 D Print an FP comparison operator.
3828 E Print 32 - constant, for SImode shifts as extract.
3829 e Print 64 - constant, for DImode rotates.
3830 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3831 a floating point register emitted normally.
3832 I Invert a predicate register by adding 1.
3833 J Select the proper predicate register for a condition.
3834 j Select the inverse predicate register for a condition.
3835 O Append .acq for volatile load.
3836 P Postincrement of a MEM.
3837 Q Append .rel for volatile store.
3838 S Shift amount for shladd instruction.
3839 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3840 for Intel assembler.
3841 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3842 for Intel assembler.
3843 r Print register name, or constant 0 as r0. HP compatibility for
3846 ia64_print_operand (file, x, code)
3856 /* Handled below. */
3861 enum rtx_code c = swap_condition (GET_CODE (x));
3862 fputs (GET_RTX_NAME (c), file);
3867 switch (GET_CODE (x))
3879 str = GET_RTX_NAME (GET_CODE (x));
3886 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
3890 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
3894 if (x == CONST0_RTX (GET_MODE (x)))
3895 str = reg_names [FR_REG (0)];
3896 else if (x == CONST1_RTX (GET_MODE (x)))
3897 str = reg_names [FR_REG (1)];
3898 else if (GET_CODE (x) == REG)
3899 str = reg_names [REGNO (x)];
3906 fputs (reg_names [REGNO (x) + 1], file);
3912 unsigned int regno = REGNO (XEXP (x, 0));
3913 if (GET_CODE (x) == EQ)
3917 fputs (reg_names [regno], file);
3922 if (MEM_VOLATILE_P (x))
3923 fputs(".acq", file);
3928 HOST_WIDE_INT value;
3930 switch (GET_CODE (XEXP (x, 0)))
3936 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
3937 if (GET_CODE (x) == CONST_INT)
3939 else if (GET_CODE (x) == REG)
3941 fprintf (file, ", %s", reg_names[REGNO (x)]);
3949 value = GET_MODE_SIZE (GET_MODE (x));
3953 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
3957 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
3962 if (MEM_VOLATILE_P (x))
3963 fputs(".rel", file);
3967 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3971 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3973 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
3979 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3981 const char *prefix = "0x";
3982 if (INTVAL (x) & 0x80000000)
3984 fprintf (file, "0xffffffff");
3987 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
3993 /* If this operand is the constant zero, write it as register zero.
3994 Any register, zero, or CONST_INT value is OK here. */
3995 if (GET_CODE (x) == REG)
3996 fputs (reg_names[REGNO (x)], file);
3997 else if (x == CONST0_RTX (GET_MODE (x)))
3999 else if (GET_CODE (x) == CONST_INT)
4000 output_addr_const (file, x);
4002 output_operand_lossage ("invalid %%r value");
4009 /* For conditional branches, returns or calls, substitute
4010 sptk, dptk, dpnt, or spnt for %s. */
4011 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4014 int pred_val = INTVAL (XEXP (x, 0));
4016 /* Guess top and bottom 10% statically predicted. */
4017 if (pred_val < REG_BR_PROB_BASE / 50)
4019 else if (pred_val < REG_BR_PROB_BASE / 2)
4021 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4026 else if (GET_CODE (current_output_insn) == CALL_INSN)
4031 fputs (which, file);
4036 x = current_insn_predicate;
4039 unsigned int regno = REGNO (XEXP (x, 0));
4040 if (GET_CODE (x) == EQ)
4042 fprintf (file, "(%s) ", reg_names [regno]);
4047 output_operand_lossage ("ia64_print_operand: unknown code");
4051 switch (GET_CODE (x))
4053 /* This happens for the spill/restore instructions. */
4058 /* ... fall through ... */
4061 fputs (reg_names [REGNO (x)], file);
4066 rtx addr = XEXP (x, 0);
4067 if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
4068 addr = XEXP (addr, 0);
4069 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4074 output_addr_const (file, x);
4081 /* Compute a (partial) cost for rtx X. Return true if the complete
4082 cost has been computed, and false if subexpressions should be
4083 scanned. In either case, *TOTAL contains the cost result. */
4084 /* ??? This is incomplete. */
4087 ia64_rtx_costs (x, code, outer_code, total)
4089 int code, outer_code;
4098 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4101 if (CONST_OK_FOR_I (INTVAL (x)))
4103 else if (CONST_OK_FOR_J (INTVAL (x)))
4106 *total = COSTS_N_INSNS (1);
4109 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4112 *total = COSTS_N_INSNS (1);
4117 *total = COSTS_N_INSNS (1);
4123 *total = COSTS_N_INSNS (3);
4127 /* For multiplies wider than HImode, we have to go to the FPU,
4128 which normally involves copies. Plus there's the latency
4129 of the multiply itself, and the latency of the instructions to
4130 transfer integer regs to FP regs. */
4131 /* ??? Check for FP mode. */
4132 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4133 *total = COSTS_N_INSNS (10);
4135 *total = COSTS_N_INSNS (2);
4143 *total = COSTS_N_INSNS (1);
4150 /* We make divide expensive, so that divide-by-constant will be
4151 optimized to a multiply. */
4152 *total = COSTS_N_INSNS (60);
4160 /* Calculate the cost of moving data from a register in class FROM to
4161 one in class TO, using MODE. */
4164 ia64_register_move_cost (mode, from, to)
4165 enum machine_mode mode;
4166 enum reg_class from, to;
4168 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4169 if (to == ADDL_REGS)
4171 if (from == ADDL_REGS)
4174 /* All costs are symmetric, so reduce cases by putting the
4175 lower number class as the destination. */
4178 enum reg_class tmp = to;
4179 to = from, from = tmp;
4182 /* Moving from FR<->GR in TFmode must be more expensive than 2,
4183 so that we get secondary memory reloads. Between FR_REGS,
4184 we have to make this at least as expensive as MEMORY_MOVE_COST
4185 to avoid spectacularly poor register class preferencing. */
4188 if (to != GR_REGS || from != GR_REGS)
4189 return MEMORY_MOVE_COST (mode, to, 0);
4197 /* Moving between PR registers takes two insns. */
4198 if (from == PR_REGS)
4200 /* Moving between PR and anything but GR is impossible. */
4201 if (from != GR_REGS)
4202 return MEMORY_MOVE_COST (mode, to, 0);
4206 /* Moving between BR and anything but GR is impossible. */
4207 if (from != GR_REGS && from != GR_AND_BR_REGS)
4208 return MEMORY_MOVE_COST (mode, to, 0);
4213 /* Moving between AR and anything but GR is impossible. */
4214 if (from != GR_REGS)
4215 return MEMORY_MOVE_COST (mode, to, 0);
4220 case GR_AND_FR_REGS:
4221 case GR_AND_BR_REGS:
4232 /* This function returns the register class required for a secondary
4233 register when copying between one of the registers in CLASS, and X,
4234 using MODE. A return value of NO_REGS means that no secondary register
4238 ia64_secondary_reload_class (class, mode, x)
4239 enum reg_class class;
4240 enum machine_mode mode ATTRIBUTE_UNUSED;
4245 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4246 regno = true_regnum (x);
4253 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4254 interaction. We end up with two pseudos with overlapping lifetimes
4255 both of which are equiv to the same constant, and both which need
4256 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4257 changes depending on the path length, which means the qty_first_reg
4258 check in make_regs_eqv can give different answers at different times.
4259 At some point I'll probably need a reload_indi pattern to handle
4262 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4263 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4264 non-general registers for good measure. */
4265 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4268 /* This is needed if a pseudo used as a call_operand gets spilled to a
4270 if (GET_CODE (x) == MEM)
4275 /* Need to go through general regsters to get to other class regs. */
4276 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4279 /* This can happen when a paradoxical subreg is an operand to the
4281 /* ??? This shouldn't be necessary after instruction scheduling is
4282 enabled, because paradoxical subregs are not accepted by
4283 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4284 stop the paradoxical subreg stupidity in the *_operand functions
4286 if (GET_CODE (x) == MEM
4287 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4288 || GET_MODE (x) == QImode))
4291 /* This can happen because of the ior/and/etc patterns that accept FP
4292 registers as operands. If the third operand is a constant, then it
4293 needs to be reloaded into a FP register. */
4294 if (GET_CODE (x) == CONST_INT)
4297 /* This can happen because of register elimination in a muldi3 insn.
4298 E.g. `26107 * (unsigned long)&u'. */
4299 if (GET_CODE (x) == PLUS)
4304 /* ??? This happens if we cse/gcse a BImode value across a call,
4305 and the function has a nonlocal goto. This is because global
4306 does not allocate call crossing pseudos to hard registers when
4307 current_function_has_nonlocal_goto is true. This is relatively
4308 common for C++ programs that use exceptions. To reproduce,
4309 return NO_REGS and compile libstdc++. */
4310 if (GET_CODE (x) == MEM)
4313 /* This can happen when we take a BImode subreg of a DImode value,
4314 and that DImode value winds up in some non-GR register. */
4315 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4320 /* Since we have no offsettable memory addresses, we need a temporary
4321 to hold the address of the second word. */
4334 /* Emit text to declare externally defined variables and functions, because
4335 the Intel assembler does not support undefined externals. */
4338 ia64_asm_output_external (file, decl, name)
4343 int save_referenced;
4345 /* GNU as does not need anything here, but the HP linker does need
4346 something for external functions. */
4350 || TREE_CODE (decl) != FUNCTION_DECL
4351 || strstr(name, "__builtin_") == name))
4354 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4355 the linker when we do this, so we need to be careful not to do this for
4356 builtin functions which have no library equivalent. Unfortunately, we
4357 can't tell here whether or not a function will actually be called by
4358 expand_expr, so we pull in library functions even if we may not need
4360 if (! strcmp (name, "__builtin_next_arg")
4361 || ! strcmp (name, "alloca")
4362 || ! strcmp (name, "__builtin_constant_p")
4363 || ! strcmp (name, "__builtin_args_info"))
4367 ia64_hpux_add_extern_decl (name);
4370 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4372 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4373 if (TREE_CODE (decl) == FUNCTION_DECL)
4374 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4375 (*targetm.asm_out.globalize_label) (file, name);
4376 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4380 /* Parse the -mfixed-range= option string. */
4383 fix_range (const_str)
4384 const char *const_str;
4387 char *str, *dash, *comma;
4389 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4390 REG2 are either register names or register numbers. The effect
4391 of this option is to mark the registers in the range from REG1 to
4392 REG2 as ``fixed'' so they won't be used by the compiler. This is
4393 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4395 i = strlen (const_str);
4396 str = (char *) alloca (i + 1);
4397 memcpy (str, const_str, i + 1);
4401 dash = strchr (str, '-');
4404 warning ("value of -mfixed-range must have form REG1-REG2");
4409 comma = strchr (dash + 1, ',');
4413 first = decode_reg_name (str);
4416 warning ("unknown register name: %s", str);
4420 last = decode_reg_name (dash + 1);
4423 warning ("unknown register name: %s", dash + 1);
4431 warning ("%s-%s is an empty range", str, dash + 1);
4435 for (i = first; i <= last; ++i)
4436 fixed_regs[i] = call_used_regs[i] = 1;
4446 static struct machine_function *
4447 ia64_init_machine_status ()
4449 return ggc_alloc_cleared (sizeof (struct machine_function));
4452 /* Handle TARGET_OPTIONS switches. */
4455 ia64_override_options ()
4459 const char *const name; /* processor name or nickname. */
4460 const enum processor_type processor;
4462 const processor_alias_table[] =
4464 {"itanium", PROCESSOR_ITANIUM},
4465 {"itanium1", PROCESSOR_ITANIUM},
4466 {"merced", PROCESSOR_ITANIUM},
4467 {"itanium2", PROCESSOR_ITANIUM2},
4468 {"mckinley", PROCESSOR_ITANIUM2},
4471 int const pta_size = ARRAY_SIZE (processor_alias_table);
4474 if (TARGET_AUTO_PIC)
4475 target_flags |= MASK_CONST_GP;
4477 if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
4479 warning ("cannot optimize floating point division for both latency and throughput");
4480 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4483 if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
4485 warning ("cannot optimize integer division for both latency and throughput");
4486 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4489 if (ia64_fixed_range_string)
4490 fix_range (ia64_fixed_range_string);
4492 if (ia64_tls_size_string)
4495 unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
4496 if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
4497 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
4499 ia64_tls_size = tmp;
4502 if (!ia64_tune_string)
4503 ia64_tune_string = "itanium2";
4505 for (i = 0; i < pta_size; i++)
4506 if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
4508 ia64_tune = processor_alias_table[i].processor;
4513 error ("bad value (%s) for -tune= switch", ia64_tune_string);
4515 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4516 flag_schedule_insns_after_reload = 0;
4518 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4520 init_machine_status = ia64_init_machine_status;
4522 /* Tell the compiler which flavor of TFmode we're using. */
4523 if (INTEL_EXTENDED_IEEE_FORMAT)
4524 real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
4527 static enum attr_itanium_class ia64_safe_itanium_class PARAMS((rtx));
4528 static enum attr_type ia64_safe_type PARAMS((rtx));
4530 static enum attr_itanium_class
4531 ia64_safe_itanium_class (insn)
4534 if (recog_memoized (insn) >= 0)
4535 return get_attr_itanium_class (insn);
4537 return ITANIUM_CLASS_UNKNOWN;
4540 static enum attr_type
4541 ia64_safe_type (insn)
4544 if (recog_memoized (insn) >= 0)
4545 return get_attr_type (insn);
4547 return TYPE_UNKNOWN;
4550 /* The following collection of routines emit instruction group stop bits as
4551 necessary to avoid dependencies. */
4553 /* Need to track some additional registers as far as serialization is
4554 concerned so we can properly handle br.call and br.ret. We could
4555 make these registers visible to gcc, but since these registers are
4556 never explicitly used in gcc generated code, it seems wasteful to
4557 do so (plus it would make the call and return patterns needlessly
4559 #define REG_GP (GR_REG (1))
4560 #define REG_RP (BR_REG (0))
4561 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4562 /* This is used for volatile asms which may require a stop bit immediately
4563 before and after them. */
4564 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4565 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4566 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4568 /* For each register, we keep track of how it has been written in the
4569 current instruction group.
4571 If a register is written unconditionally (no qualifying predicate),
4572 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4574 If a register is written if its qualifying predicate P is true, we
4575 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4576 may be written again by the complement of P (P^1) and when this happens,
4577 WRITE_COUNT gets set to 2.
4579 The result of this is that whenever an insn attempts to write a register
4580 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4582 If a predicate register is written by a floating-point insn, we set
4583 WRITTEN_BY_FP to true.
4585 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4586 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4588 struct reg_write_state
4590 unsigned int write_count : 2;
4591 unsigned int first_pred : 16;
4592 unsigned int written_by_fp : 1;
4593 unsigned int written_by_and : 1;
4594 unsigned int written_by_or : 1;
4597 /* Cumulative info for the current instruction group. */
4598 struct reg_write_state rws_sum[NUM_REGS];
4599 /* Info for the current instruction. This gets copied to rws_sum after a
4600 stop bit is emitted. */
4601 struct reg_write_state rws_insn[NUM_REGS];
4603 /* Indicates whether this is the first instruction after a stop bit,
4604 in which case we don't need another stop bit. Without this, we hit
4605 the abort in ia64_variable_issue when scheduling an alloc. */
4606 static int first_instruction;
4608 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4609 RTL for one instruction. */
4612 unsigned int is_write : 1; /* Is register being written? */
4613 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4614 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4615 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4616 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4617 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4620 static void rws_update PARAMS ((struct reg_write_state *, int,
4621 struct reg_flags, int));
4622 static int rws_access_regno PARAMS ((int, struct reg_flags, int));
4623 static int rws_access_reg PARAMS ((rtx, struct reg_flags, int));
4624 static void update_set_flags PARAMS ((rtx, struct reg_flags *, int *, rtx *));
4625 static int set_src_needs_barrier PARAMS ((rtx, struct reg_flags, int, rtx));
4626 static int rtx_needs_barrier PARAMS ((rtx, struct reg_flags, int));
4627 static void init_insn_group_barriers PARAMS ((void));
4628 static int group_barrier_needed_p PARAMS ((rtx));
4629 static int safe_group_barrier_needed_p PARAMS ((rtx));
4631 /* Update *RWS for REGNO, which is being written by the current instruction,
4632 with predicate PRED, and associated register flags in FLAGS. */
4635 rws_update (rws, regno, flags, pred)
4636 struct reg_write_state *rws;
4638 struct reg_flags flags;
4642 rws[regno].write_count++;
4644 rws[regno].write_count = 2;
4645 rws[regno].written_by_fp |= flags.is_fp;
4646 /* ??? Not tracking and/or across differing predicates. */
4647 rws[regno].written_by_and = flags.is_and;
4648 rws[regno].written_by_or = flags.is_or;
4649 rws[regno].first_pred = pred;
4652 /* Handle an access to register REGNO of type FLAGS using predicate register
4653 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4654 a dependency with an earlier instruction in the same group. */
4657 rws_access_regno (regno, flags, pred)
4659 struct reg_flags flags;
4662 int need_barrier = 0;
4664 if (regno >= NUM_REGS)
4667 if (! PR_REGNO_P (regno))
4668 flags.is_and = flags.is_or = 0;
4674 /* One insn writes same reg multiple times? */
4675 if (rws_insn[regno].write_count > 0)
4678 /* Update info for current instruction. */
4679 rws_update (rws_insn, regno, flags, pred);
4680 write_count = rws_sum[regno].write_count;
4682 switch (write_count)
4685 /* The register has not been written yet. */
4686 rws_update (rws_sum, regno, flags, pred);
4690 /* The register has been written via a predicate. If this is
4691 not a complementary predicate, then we need a barrier. */
4692 /* ??? This assumes that P and P+1 are always complementary
4693 predicates for P even. */
4694 if (flags.is_and && rws_sum[regno].written_by_and)
4696 else if (flags.is_or && rws_sum[regno].written_by_or)
4698 else if ((rws_sum[regno].first_pred ^ 1) != pred)
4700 rws_update (rws_sum, regno, flags, pred);
4704 /* The register has been unconditionally written already. We
4706 if (flags.is_and && rws_sum[regno].written_by_and)
4708 else if (flags.is_or && rws_sum[regno].written_by_or)
4712 rws_sum[regno].written_by_and = flags.is_and;
4713 rws_sum[regno].written_by_or = flags.is_or;
4722 if (flags.is_branch)
4724 /* Branches have several RAW exceptions that allow to avoid
4727 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
4728 /* RAW dependencies on branch regs are permissible as long
4729 as the writer is a non-branch instruction. Since we
4730 never generate code that uses a branch register written
4731 by a branch instruction, handling this case is
4735 if (REGNO_REG_CLASS (regno) == PR_REGS
4736 && ! rws_sum[regno].written_by_fp)
4737 /* The predicates of a branch are available within the
4738 same insn group as long as the predicate was written by
4739 something other than a floating-point instruction. */
4743 if (flags.is_and && rws_sum[regno].written_by_and)
4745 if (flags.is_or && rws_sum[regno].written_by_or)
4748 switch (rws_sum[regno].write_count)
4751 /* The register has not been written yet. */
4755 /* The register has been written via a predicate. If this is
4756 not a complementary predicate, then we need a barrier. */
4757 /* ??? This assumes that P and P+1 are always complementary
4758 predicates for P even. */
4759 if ((rws_sum[regno].first_pred ^ 1) != pred)
4764 /* The register has been unconditionally written already. We
4774 return need_barrier;
4778 rws_access_reg (reg, flags, pred)
4780 struct reg_flags flags;
4783 int regno = REGNO (reg);
4784 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4787 return rws_access_regno (regno, flags, pred);
4790 int need_barrier = 0;
4792 need_barrier |= rws_access_regno (regno + n, flags, pred);
4793 return need_barrier;
4797 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4798 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4801 update_set_flags (x, pflags, ppred, pcond)
4803 struct reg_flags *pflags;
4807 rtx src = SET_SRC (x);
4811 switch (GET_CODE (src))
4817 if (SET_DEST (x) == pc_rtx)
4818 /* X is a conditional branch. */
4822 int is_complemented = 0;
4824 /* X is a conditional move. */
4825 rtx cond = XEXP (src, 0);
4826 if (GET_CODE (cond) == EQ)
4827 is_complemented = 1;
4828 cond = XEXP (cond, 0);
4829 if (GET_CODE (cond) != REG
4830 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4833 if (XEXP (src, 1) == SET_DEST (x)
4834 || XEXP (src, 2) == SET_DEST (x))
4836 /* X is a conditional move that conditionally writes the
4839 /* We need another complement in this case. */
4840 if (XEXP (src, 1) == SET_DEST (x))
4841 is_complemented = ! is_complemented;
4843 *ppred = REGNO (cond);
4844 if (is_complemented)
4848 /* ??? If this is a conditional write to the dest, then this
4849 instruction does not actually read one source. This probably
4850 doesn't matter, because that source is also the dest. */
4851 /* ??? Multiple writes to predicate registers are allowed
4852 if they are all AND type compares, or if they are all OR
4853 type compares. We do not generate such instructions
4856 /* ... fall through ... */
4859 if (GET_RTX_CLASS (GET_CODE (src)) == '<'
4860 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
4861 /* Set pflags->is_fp to 1 so that we know we're dealing
4862 with a floating point comparison when processing the
4863 destination of the SET. */
4866 /* Discover if this is a parallel comparison. We only handle
4867 and.orcm and or.andcm at present, since we must retain a
4868 strict inverse on the predicate pair. */
4869 else if (GET_CODE (src) == AND)
4871 else if (GET_CODE (src) == IOR)
4878 /* Subroutine of rtx_needs_barrier; this function determines whether the
4879 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
4880 are as in rtx_needs_barrier. COND is an rtx that holds the condition
4884 set_src_needs_barrier (x, flags, pred, cond)
4886 struct reg_flags flags;
4890 int need_barrier = 0;
4892 rtx src = SET_SRC (x);
4894 if (GET_CODE (src) == CALL)
4895 /* We don't need to worry about the result registers that
4896 get written by subroutine call. */
4897 return rtx_needs_barrier (src, flags, pred);
4898 else if (SET_DEST (x) == pc_rtx)
4900 /* X is a conditional branch. */
4901 /* ??? This seems redundant, as the caller sets this bit for
4903 flags.is_branch = 1;
4904 return rtx_needs_barrier (src, flags, pred);
4907 need_barrier = rtx_needs_barrier (src, flags, pred);
4909 /* This instruction unconditionally uses a predicate register. */
4911 need_barrier |= rws_access_reg (cond, flags, 0);
4914 if (GET_CODE (dst) == ZERO_EXTRACT)
4916 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
4917 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
4918 dst = XEXP (dst, 0);
4920 return need_barrier;
4923 /* Handle an access to rtx X of type FLAGS using predicate register PRED.
4924 Return 1 is this access creates a dependency with an earlier instruction
4925 in the same group. */
4928 rtx_needs_barrier (x, flags, pred)
4930 struct reg_flags flags;
4934 int is_complemented = 0;
4935 int need_barrier = 0;
4936 const char *format_ptr;
4937 struct reg_flags new_flags;
4945 switch (GET_CODE (x))
4948 update_set_flags (x, &new_flags, &pred, &cond);
4949 need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
4950 if (GET_CODE (SET_SRC (x)) != CALL)
4952 new_flags.is_write = 1;
4953 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
4958 new_flags.is_write = 0;
4959 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
4961 /* Avoid multiple register writes, in case this is a pattern with
4962 multiple CALL rtx. This avoids an abort in rws_access_reg. */
4963 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
4965 new_flags.is_write = 1;
4966 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
4967 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
4968 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4973 /* X is a predicated instruction. */
4975 cond = COND_EXEC_TEST (x);
4978 need_barrier = rtx_needs_barrier (cond, flags, 0);
4980 if (GET_CODE (cond) == EQ)
4981 is_complemented = 1;
4982 cond = XEXP (cond, 0);
4983 if (GET_CODE (cond) != REG
4984 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4986 pred = REGNO (cond);
4987 if (is_complemented)
4990 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
4991 return need_barrier;
4995 /* Clobber & use are for earlier compiler-phases only. */
5000 /* We always emit stop bits for traditional asms. We emit stop bits
5001 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5002 if (GET_CODE (x) != ASM_OPERANDS
5003 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5005 /* Avoid writing the register multiple times if we have multiple
5006 asm outputs. This avoids an abort in rws_access_reg. */
5007 if (! rws_insn[REG_VOLATILE].write_count)
5009 new_flags.is_write = 1;
5010 rws_access_regno (REG_VOLATILE, new_flags, pred);
5015 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5016 We can not just fall through here since then we would be confused
5017 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5018 traditional asms unlike their normal usage. */
5020 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5021 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5026 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5028 rtx pat = XVECEXP (x, 0, i);
5029 if (GET_CODE (pat) == SET)
5031 update_set_flags (pat, &new_flags, &pred, &cond);
5032 need_barrier |= set_src_needs_barrier (pat, new_flags, pred, cond);
5034 else if (GET_CODE (pat) == USE
5035 || GET_CODE (pat) == CALL
5036 || GET_CODE (pat) == ASM_OPERANDS)
5037 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5038 else if (GET_CODE (pat) != CLOBBER && GET_CODE (pat) != RETURN)
5041 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5043 rtx pat = XVECEXP (x, 0, i);
5044 if (GET_CODE (pat) == SET)
5046 if (GET_CODE (SET_SRC (pat)) != CALL)
5048 new_flags.is_write = 1;
5049 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5053 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5054 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5062 if (REGNO (x) == AR_UNAT_REGNUM)
5064 for (i = 0; i < 64; ++i)
5065 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5068 need_barrier = rws_access_reg (x, flags, pred);
5072 /* Find the regs used in memory address computation. */
5073 new_flags.is_write = 0;
5074 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5077 case CONST_INT: case CONST_DOUBLE:
5078 case SYMBOL_REF: case LABEL_REF: case CONST:
5081 /* Operators with side-effects. */
5082 case POST_INC: case POST_DEC:
5083 if (GET_CODE (XEXP (x, 0)) != REG)
5086 new_flags.is_write = 0;
5087 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5088 new_flags.is_write = 1;
5089 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5093 if (GET_CODE (XEXP (x, 0)) != REG)
5096 new_flags.is_write = 0;
5097 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5098 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5099 new_flags.is_write = 1;
5100 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5103 /* Handle common unary and binary ops for efficiency. */
5104 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5105 case MOD: case UDIV: case UMOD: case AND: case IOR:
5106 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5107 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5108 case NE: case EQ: case GE: case GT: case LE:
5109 case LT: case GEU: case GTU: case LEU: case LTU:
5110 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5111 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5114 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5115 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5116 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5117 case SQRT: case FFS: case POPCOUNT:
5118 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5122 switch (XINT (x, 1))
5124 case UNSPEC_LTOFF_DTPMOD:
5125 case UNSPEC_LTOFF_DTPREL:
5127 case UNSPEC_LTOFF_TPREL:
5129 case UNSPEC_PRED_REL_MUTEX:
5130 case UNSPEC_PIC_CALL:
5132 case UNSPEC_FETCHADD_ACQ:
5133 case UNSPEC_BSP_VALUE:
5134 case UNSPEC_FLUSHRS:
5135 case UNSPEC_BUNDLE_SELECTOR:
5138 case UNSPEC_GR_SPILL:
5139 case UNSPEC_GR_RESTORE:
5141 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5142 HOST_WIDE_INT bit = (offset >> 3) & 63;
5144 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5145 new_flags.is_write = (XINT (x, 1) == 1);
5146 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5151 case UNSPEC_FR_SPILL:
5152 case UNSPEC_FR_RESTORE:
5153 case UNSPEC_GETF_EXP:
5155 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5158 case UNSPEC_FR_RECIP_APPROX:
5159 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5160 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5163 case UNSPEC_CMPXCHG_ACQ:
5164 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5165 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5173 case UNSPEC_VOLATILE:
5174 switch (XINT (x, 1))
5177 /* Alloc must always be the first instruction of a group.
5178 We force this by always returning true. */
5179 /* ??? We might get better scheduling if we explicitly check for
5180 input/local/output register dependencies, and modify the
5181 scheduler so that alloc is always reordered to the start of
5182 the current group. We could then eliminate all of the
5183 first_instruction code. */
5184 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5186 new_flags.is_write = 1;
5187 rws_access_regno (REG_AR_CFM, new_flags, pred);
5190 case UNSPECV_SET_BSP:
5194 case UNSPECV_BLOCKAGE:
5195 case UNSPECV_INSN_GROUP_BARRIER:
5197 case UNSPECV_PSAC_ALL:
5198 case UNSPECV_PSAC_NORMAL:
5207 new_flags.is_write = 0;
5208 need_barrier = rws_access_regno (REG_RP, flags, pred);
5209 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5211 new_flags.is_write = 1;
5212 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5213 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5217 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5218 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5219 switch (format_ptr[i])
5221 case '0': /* unused field */
5222 case 'i': /* integer */
5223 case 'n': /* note */
5224 case 'w': /* wide integer */
5225 case 's': /* pointer to string */
5226 case 'S': /* optional pointer to string */
5230 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5235 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5236 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5245 return need_barrier;
5248 /* Clear out the state for group_barrier_needed_p at the start of a
5249 sequence of insns. */
5252 init_insn_group_barriers ()
5254 memset (rws_sum, 0, sizeof (rws_sum));
5255 first_instruction = 1;
5258 /* Given the current state, recorded by previous calls to this function,
5259 determine whether a group barrier (a stop bit) is necessary before INSN.
5260 Return nonzero if so. */
5263 group_barrier_needed_p (insn)
5267 int need_barrier = 0;
5268 struct reg_flags flags;
5270 memset (&flags, 0, sizeof (flags));
5271 switch (GET_CODE (insn))
5277 /* A barrier doesn't imply an instruction group boundary. */
5281 memset (rws_insn, 0, sizeof (rws_insn));
5285 flags.is_branch = 1;
5286 flags.is_sibcall = SIBLING_CALL_P (insn);
5287 memset (rws_insn, 0, sizeof (rws_insn));
5289 /* Don't bundle a call following another call. */
5290 if ((pat = prev_active_insn (insn))
5291 && GET_CODE (pat) == CALL_INSN)
5297 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5301 flags.is_branch = 1;
5303 /* Don't bundle a jump following a call. */
5304 if ((pat = prev_active_insn (insn))
5305 && GET_CODE (pat) == CALL_INSN)
5313 if (GET_CODE (PATTERN (insn)) == USE
5314 || GET_CODE (PATTERN (insn)) == CLOBBER)
5315 /* Don't care about USE and CLOBBER "insns"---those are used to
5316 indicate to the optimizer that it shouldn't get rid of
5317 certain operations. */
5320 pat = PATTERN (insn);
5322 /* Ug. Hack hacks hacked elsewhere. */
5323 switch (recog_memoized (insn))
5325 /* We play dependency tricks with the epilogue in order
5326 to get proper schedules. Undo this for dv analysis. */
5327 case CODE_FOR_epilogue_deallocate_stack:
5328 case CODE_FOR_prologue_allocate_stack:
5329 pat = XVECEXP (pat, 0, 0);
5332 /* The pattern we use for br.cloop confuses the code above.
5333 The second element of the vector is representative. */
5334 case CODE_FOR_doloop_end_internal:
5335 pat = XVECEXP (pat, 0, 1);
5338 /* Doesn't generate code. */
5339 case CODE_FOR_pred_rel_mutex:
5340 case CODE_FOR_prologue_use:
5347 memset (rws_insn, 0, sizeof (rws_insn));
5348 need_barrier = rtx_needs_barrier (pat, flags, 0);
5350 /* Check to see if the previous instruction was a volatile
5353 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5360 if (first_instruction && INSN_P (insn)
5361 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5362 && GET_CODE (PATTERN (insn)) != USE
5363 && GET_CODE (PATTERN (insn)) != CLOBBER)
5366 first_instruction = 0;
5369 return need_barrier;
5372 /* Like group_barrier_needed_p, but do not clobber the current state. */
5375 safe_group_barrier_needed_p (insn)
5378 struct reg_write_state rws_saved[NUM_REGS];
5379 int saved_first_instruction;
5382 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5383 saved_first_instruction = first_instruction;
5385 t = group_barrier_needed_p (insn);
5387 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5388 first_instruction = saved_first_instruction;
5393 /* Scan the current function and insert stop bits as necessary to
5394 eliminate dependencies. This function assumes that a final
5395 instruction scheduling pass has been run which has already
5396 inserted most of the necessary stop bits. This function only
5397 inserts new ones at basic block boundaries, since these are
5398 invisible to the scheduler. */
5401 emit_insn_group_barriers (dump)
5406 int insns_since_last_label = 0;
5408 init_insn_group_barriers ();
5410 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5412 if (GET_CODE (insn) == CODE_LABEL)
5414 if (insns_since_last_label)
5416 insns_since_last_label = 0;
5418 else if (GET_CODE (insn) == NOTE
5419 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5421 if (insns_since_last_label)
5423 insns_since_last_label = 0;
5425 else if (GET_CODE (insn) == INSN
5426 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5427 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5429 init_insn_group_barriers ();
5432 else if (INSN_P (insn))
5434 insns_since_last_label = 1;
5436 if (group_barrier_needed_p (insn))
5441 fprintf (dump, "Emitting stop before label %d\n",
5442 INSN_UID (last_label));
5443 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5446 init_insn_group_barriers ();
5454 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5455 This function has to emit all necessary group barriers. */
5458 emit_all_insn_group_barriers (dump)
5459 FILE *dump ATTRIBUTE_UNUSED;
5463 init_insn_group_barriers ();
5465 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5467 if (GET_CODE (insn) == BARRIER)
5469 rtx last = prev_active_insn (insn);
5473 if (GET_CODE (last) == JUMP_INSN
5474 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5475 last = prev_active_insn (last);
5476 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5477 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5479 init_insn_group_barriers ();
5481 else if (INSN_P (insn))
5483 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5484 init_insn_group_barriers ();
5485 else if (group_barrier_needed_p (insn))
5487 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5488 init_insn_group_barriers ();
5489 group_barrier_needed_p (insn);
5496 static int errata_find_address_regs PARAMS ((rtx *, void *));
5497 static void errata_emit_nops PARAMS ((rtx));
5498 static void fixup_errata PARAMS ((void));
5500 /* This structure is used to track some details about the previous insns
5501 groups so we can determine if it may be necessary to insert NOPs to
5502 workaround hardware errata. */
5505 HARD_REG_SET p_reg_set;
5506 HARD_REG_SET gr_reg_conditionally_set;
5509 /* Index into the last_group array. */
5510 static int group_idx;
5512 /* Called through for_each_rtx; determines if a hard register that was
5513 conditionally set in the previous group is used as an address register.
5514 It ensures that for_each_rtx returns 1 in that case. */
5516 errata_find_address_regs (xp, data)
5518 void *data ATTRIBUTE_UNUSED;
5521 if (GET_CODE (x) != MEM)
5524 if (GET_CODE (x) == POST_MODIFY)
5526 if (GET_CODE (x) == REG)
5528 struct group *prev_group = last_group + (group_idx ^ 1);
5529 if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set,
5537 /* Called for each insn; this function keeps track of the state in
5538 last_group and emits additional NOPs if necessary to work around
5539 an Itanium A/B step erratum. */
5541 errata_emit_nops (insn)
5544 struct group *this_group = last_group + group_idx;
5545 struct group *prev_group = last_group + (group_idx ^ 1);
5546 rtx pat = PATTERN (insn);
5547 rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0;
5548 rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat;
5549 enum attr_type type;
5552 if (GET_CODE (real_pat) == USE
5553 || GET_CODE (real_pat) == CLOBBER
5554 || GET_CODE (real_pat) == ASM_INPUT
5555 || GET_CODE (real_pat) == ADDR_VEC
5556 || GET_CODE (real_pat) == ADDR_DIFF_VEC
5557 || asm_noperands (PATTERN (insn)) >= 0)
5560 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5563 if (GET_CODE (set) == PARALLEL)
5566 set = XVECEXP (real_pat, 0, 0);
5567 for (i = 1; i < XVECLEN (real_pat, 0); i++)
5568 if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE
5569 && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER)
5576 if (set && GET_CODE (set) != SET)
5579 type = get_attr_type (insn);
5582 && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set))))
5583 SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set)));
5585 if ((type == TYPE_M || type == TYPE_A) && cond && set
5586 && REG_P (SET_DEST (set))
5587 && GET_CODE (SET_SRC (set)) != PLUS
5588 && GET_CODE (SET_SRC (set)) != MINUS
5589 && (GET_CODE (SET_SRC (set)) != ASHIFT
5590 || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode))
5591 && (GET_CODE (SET_SRC (set)) != MEM
5592 || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY)
5593 && GENERAL_REGNO_P (REGNO (SET_DEST (set))))
5595 if (GET_RTX_CLASS (GET_CODE (cond)) != '<'
5596 || ! REG_P (XEXP (cond, 0)))
5599 if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0))))
5600 SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set)));
5602 if (for_each_rtx (&real_pat, errata_find_address_regs, NULL))
5604 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5605 emit_insn_before (gen_nop (), insn);
5606 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5608 memset (last_group, 0, sizeof last_group);
5612 /* Emit extra nops if they are required to work around hardware errata. */
5619 if (! TARGET_B_STEP)
5623 memset (last_group, 0, sizeof last_group);
5625 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5630 if (ia64_safe_type (insn) == TYPE_S)
5633 memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
5636 errata_emit_nops (insn);
5641 /* Instruction scheduling support. */
5643 #define NR_BUNDLES 10
5645 /* A list of names of all available bundles. */
5647 static const char *bundle_name [NR_BUNDLES] =
5653 #if NR_BUNDLES == 10
5663 /* Nonzero if we should insert stop bits into the schedule. */
5665 int ia64_final_schedule = 0;
5667 /* Codes of the corresponding quieryied units: */
5669 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5670 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5672 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5673 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5675 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5677 /* The following variable value is an insn group barrier. */
5679 static rtx dfa_stop_insn;
5681 /* The following variable value is the last issued insn. */
5683 static rtx last_scheduled_insn;
5685 /* The following variable value is size of the DFA state. */
5687 static size_t dfa_state_size;
5689 /* The following variable value is pointer to a DFA state used as
5690 temporary variable. */
5692 static state_t temp_dfa_state = NULL;
5694 /* The following variable value is DFA state after issuing the last
5697 static state_t prev_cycle_state = NULL;
5699 /* The following array element values are TRUE if the corresponding
5700 insn requires to add stop bits before it. */
5702 static char *stops_p;
5704 /* The following variable is used to set up the mentioned above array. */
5706 static int stop_before_p = 0;
5708 /* The following variable value is length of the arrays `clocks' and
5711 static int clocks_length;
5713 /* The following array element values are cycles on which the
5714 corresponding insn will be issued. The array is used only for
5719 /* The following array element values are numbers of cycles should be
5720 added to improve insn scheduling for MM_insns for Itanium1. */
5722 static int *add_cycles;
5724 static rtx ia64_single_set PARAMS ((rtx));
5725 static void ia64_emit_insn_before PARAMS ((rtx, rtx));
5727 /* Map a bundle number to its pseudo-op. */
5733 return bundle_name[b];
5737 /* Return the maximum number of instructions a cpu can issue. */
5745 /* Helper function - like single_set, but look inside COND_EXEC. */
5748 ia64_single_set (insn)
5751 rtx x = PATTERN (insn), ret;
5752 if (GET_CODE (x) == COND_EXEC)
5753 x = COND_EXEC_CODE (x);
5754 if (GET_CODE (x) == SET)
5757 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5758 Although they are not classical single set, the second set is there just
5759 to protect it from moving past FP-relative stack accesses. */
5760 switch (recog_memoized (insn))
5762 case CODE_FOR_prologue_allocate_stack:
5763 case CODE_FOR_epilogue_deallocate_stack:
5764 ret = XVECEXP (x, 0, 0);
5768 ret = single_set_2 (insn, x);
5775 /* Adjust the cost of a scheduling dependency. Return the new cost of
5776 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5779 ia64_adjust_cost (insn, link, dep_insn, cost)
5780 rtx insn, link, dep_insn;
5783 enum attr_itanium_class dep_class;
5784 enum attr_itanium_class insn_class;
5786 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
5789 insn_class = ia64_safe_itanium_class (insn);
5790 dep_class = ia64_safe_itanium_class (dep_insn);
5791 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
5792 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
5798 /* Like emit_insn_before, but skip cycle_display notes.
5799 ??? When cycle display notes are implemented, update this. */
5802 ia64_emit_insn_before (insn, before)
5805 emit_insn_before (insn, before);
5808 /* The following function marks insns who produce addresses for load
5809 and store insns. Such insns will be placed into M slots because it
5810 decrease latency time for Itanium1 (see function
5811 `ia64_produce_address_p' and the DFA descriptions). */
5814 ia64_dependencies_evaluation_hook (head, tail)
5817 rtx insn, link, next, next_tail;
5819 next_tail = NEXT_INSN (tail);
5820 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5823 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5825 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
5827 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
5829 next = XEXP (link, 0);
5830 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
5831 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
5832 && ia64_st_address_bypass_p (insn, next))
5834 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
5835 || ia64_safe_itanium_class (next)
5836 == ITANIUM_CLASS_FLD)
5837 && ia64_ld_address_bypass_p (insn, next))
5840 insn->call = link != 0;
5844 /* We're beginning a new block. Initialize data structures as necessary. */
5847 ia64_sched_init (dump, sched_verbose, max_ready)
5848 FILE *dump ATTRIBUTE_UNUSED;
5849 int sched_verbose ATTRIBUTE_UNUSED;
5850 int max_ready ATTRIBUTE_UNUSED;
5852 #ifdef ENABLE_CHECKING
5855 if (reload_completed)
5856 for (insn = NEXT_INSN (current_sched_info->prev_head);
5857 insn != current_sched_info->next_tail;
5858 insn = NEXT_INSN (insn))
5859 if (SCHED_GROUP_P (insn))
5862 last_scheduled_insn = NULL_RTX;
5863 init_insn_group_barriers ();
5866 /* We are about to being issuing insns for this clock cycle.
5867 Override the default sort algorithm to better slot instructions. */
5870 ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5871 clock_var, reorder_type)
5876 int clock_var ATTRIBUTE_UNUSED;
5880 int n_ready = *pn_ready;
5881 rtx *e_ready = ready + n_ready;
5885 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
5887 if (reorder_type == 0)
5889 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5891 for (insnp = ready; insnp < e_ready; insnp++)
5892 if (insnp < e_ready)
5895 enum attr_type t = ia64_safe_type (insn);
5896 if (t == TYPE_UNKNOWN)
5898 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
5899 || asm_noperands (PATTERN (insn)) >= 0)
5901 rtx lowest = ready[n_asms];
5902 ready[n_asms] = insn;
5908 rtx highest = ready[n_ready - 1];
5909 ready[n_ready - 1] = insn;
5916 if (n_asms < n_ready)
5918 /* Some normal insns to process. Skip the asms. */
5922 else if (n_ready > 0)
5926 if (ia64_final_schedule)
5929 int nr_need_stop = 0;
5931 for (insnp = ready; insnp < e_ready; insnp++)
5932 if (safe_group_barrier_needed_p (*insnp))
5935 if (reorder_type == 1 && n_ready == nr_need_stop)
5937 if (reorder_type == 0)
5940 /* Move down everything that needs a stop bit, preserving
5942 while (insnp-- > ready + deleted)
5943 while (insnp >= ready + deleted)
5946 if (! safe_group_barrier_needed_p (insn))
5948 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
5959 /* We are about to being issuing insns for this clock cycle. Override
5960 the default sort algorithm to better slot instructions. */
5963 ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
5970 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
5971 pn_ready, clock_var, 0);
5974 /* Like ia64_sched_reorder, but called after issuing each insn.
5975 Override the default sort algorithm to better slot instructions. */
5978 ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
5979 FILE *dump ATTRIBUTE_UNUSED;
5980 int sched_verbose ATTRIBUTE_UNUSED;
5985 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
5986 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
5987 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5991 /* We are about to issue INSN. Return the number of insns left on the
5992 ready queue that can be issued this cycle. */
5995 ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
5996 FILE *dump ATTRIBUTE_UNUSED;
5997 int sched_verbose ATTRIBUTE_UNUSED;
5998 rtx insn ATTRIBUTE_UNUSED;
5999 int can_issue_more ATTRIBUTE_UNUSED;
6001 last_scheduled_insn = insn;
6002 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6003 if (reload_completed)
6005 if (group_barrier_needed_p (insn))
6007 if (GET_CODE (insn) == CALL_INSN)
6008 init_insn_group_barriers ();
6009 stops_p [INSN_UID (insn)] = stop_before_p;
6015 /* We are choosing insn from the ready queue. Return nonzero if INSN
6019 ia64_first_cycle_multipass_dfa_lookahead_guard (insn)
6022 if (insn == NULL_RTX || !INSN_P (insn))
6024 return (!reload_completed
6025 || !safe_group_barrier_needed_p (insn));
6028 /* The following variable value is pseudo-insn used by the DFA insn
6029 scheduler to change the DFA state when the simulated clock is
6032 static rtx dfa_pre_cycle_insn;
6034 /* We are about to being issuing INSN. Return nonzero if we can not
6035 issue it on given cycle CLOCK and return zero if we should not sort
6036 the ready queue on the next clock start. */
6039 ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
6043 int last_clock, clock;
6046 int setup_clocks_p = FALSE;
6048 if (insn == NULL_RTX || !INSN_P (insn))
6050 if ((reload_completed && safe_group_barrier_needed_p (insn))
6051 || (last_scheduled_insn
6052 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6053 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6054 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6056 init_insn_group_barriers ();
6057 if (verbose && dump)
6058 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6059 last_clock == clock ? " + cycle advance" : "");
6061 if (last_clock == clock)
6063 state_transition (curr_state, dfa_stop_insn);
6064 if (TARGET_EARLY_STOP_BITS)
6065 *sort_p = (last_scheduled_insn == NULL_RTX
6066 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6071 else if (reload_completed)
6072 setup_clocks_p = TRUE;
6073 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6074 state_transition (curr_state, dfa_stop_insn);
6075 state_transition (curr_state, dfa_pre_cycle_insn);
6076 state_transition (curr_state, NULL);
6078 else if (reload_completed)
6079 setup_clocks_p = TRUE;
6080 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
6082 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6084 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6089 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6090 if (REG_NOTE_KIND (link) == 0)
6092 enum attr_itanium_class dep_class;
6093 rtx dep_insn = XEXP (link, 0);
6095 dep_class = ia64_safe_itanium_class (dep_insn);
6096 if ((dep_class == ITANIUM_CLASS_MMMUL
6097 || dep_class == ITANIUM_CLASS_MMSHF)
6098 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6100 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6101 d = last_clock - clocks [INSN_UID (dep_insn)];
6104 add_cycles [INSN_UID (insn)] = 3 - d;
6112 /* The following page contains abstract data `bundle states' which are
6113 used for bundling insns (inserting nops and template generation). */
6115 /* The following describes state of insn bundling. */
6119 /* Unique bundle state number to identify them in the debugging
6122 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6123 /* number nops before and after the insn */
6124 short before_nops_num, after_nops_num;
6125 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6127 int cost; /* cost of the state in cycles */
6128 int accumulated_insns_num; /* number of all previous insns including
6129 nops. L is considered as 2 insns */
6130 int branch_deviation; /* deviation of previous branches from 3rd slots */
6131 struct bundle_state *next; /* next state with the same insn_num */
6132 struct bundle_state *originator; /* originator (previous insn state) */
6133 /* All bundle states are in the following chain. */
6134 struct bundle_state *allocated_states_chain;
6135 /* The DFA State after issuing the insn and the nops. */
6139 /* The following is map insn number to the corresponding bundle state. */
6141 static struct bundle_state **index_to_bundle_states;
6143 /* The unique number of next bundle state. */
6145 static int bundle_states_num;
6147 /* All allocated bundle states are in the following chain. */
6149 static struct bundle_state *allocated_bundle_states_chain;
6151 /* All allocated but not used bundle states are in the following
6154 static struct bundle_state *free_bundle_state_chain;
6157 /* The following function returns a free bundle state. */
6159 static struct bundle_state *
6160 get_free_bundle_state ()
6162 struct bundle_state *result;
6164 if (free_bundle_state_chain != NULL)
6166 result = free_bundle_state_chain;
6167 free_bundle_state_chain = result->next;
6171 result = xmalloc (sizeof (struct bundle_state));
6172 result->dfa_state = xmalloc (dfa_state_size);
6173 result->allocated_states_chain = allocated_bundle_states_chain;
6174 allocated_bundle_states_chain = result;
6176 result->unique_num = bundle_states_num++;
6181 /* The following function frees given bundle state. */
6184 free_bundle_state (state)
6185 struct bundle_state *state;
6187 state->next = free_bundle_state_chain;
6188 free_bundle_state_chain = state;
6191 /* Start work with abstract data `bundle states'. */
6194 initiate_bundle_states ()
6196 bundle_states_num = 0;
6197 free_bundle_state_chain = NULL;
6198 allocated_bundle_states_chain = NULL;
6201 /* Finish work with abstract data `bundle states'. */
6204 finish_bundle_states ()
6206 struct bundle_state *curr_state, *next_state;
6208 for (curr_state = allocated_bundle_states_chain;
6210 curr_state = next_state)
6212 next_state = curr_state->allocated_states_chain;
6213 free (curr_state->dfa_state);
6218 /* Hash table of the bundle states. The key is dfa_state and insn_num
6219 of the bundle states. */
6221 static htab_t bundle_state_table;
6223 /* The function returns hash of BUNDLE_STATE. */
6226 bundle_state_hash (bundle_state)
6227 const void *bundle_state;
6229 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6232 for (result = i = 0; i < dfa_state_size; i++)
6233 result += (((unsigned char *) state->dfa_state) [i]
6234 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6235 return result + state->insn_num;
6238 /* The function returns nonzero if the bundle state keys are equal. */
6241 bundle_state_eq_p (bundle_state_1, bundle_state_2)
6242 const void *bundle_state_1;
6243 const void *bundle_state_2;
6245 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6246 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6248 return (state1->insn_num == state2->insn_num
6249 && memcmp (state1->dfa_state, state2->dfa_state,
6250 dfa_state_size) == 0);
6253 /* The function inserts the BUNDLE_STATE into the hash table. The
6254 function returns nonzero if the bundle has been inserted into the
6255 table. The table contains the best bundle state with given key. */
6258 insert_bundle_state (bundle_state)
6259 struct bundle_state *bundle_state;
6263 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6264 if (*entry_ptr == NULL)
6266 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6267 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6268 *entry_ptr = (void *) bundle_state;
6271 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6272 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6273 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6274 > bundle_state->accumulated_insns_num
6275 || (((struct bundle_state *)
6276 *entry_ptr)->accumulated_insns_num
6277 == bundle_state->accumulated_insns_num
6278 && ((struct bundle_state *)
6279 *entry_ptr)->branch_deviation
6280 > bundle_state->branch_deviation))))
6283 struct bundle_state temp;
6285 temp = *(struct bundle_state *) *entry_ptr;
6286 *(struct bundle_state *) *entry_ptr = *bundle_state;
6287 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6288 *bundle_state = temp;
6293 /* Start work with the hash table. */
6296 initiate_bundle_state_table ()
6298 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6302 /* Finish work with the hash table. */
6305 finish_bundle_state_table ()
6307 htab_delete (bundle_state_table);
6312 /* The following variable is a insn `nop' used to check bundle states
6313 with different number of inserted nops. */
6315 static rtx ia64_nop;
6317 /* The following function tries to issue NOPS_NUM nops for the current
6318 state without advancing processor cycle. If it failed, the
6319 function returns FALSE and frees the current state. */
6322 try_issue_nops (curr_state, nops_num)
6323 struct bundle_state *curr_state;
6328 for (i = 0; i < nops_num; i++)
6329 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6331 free_bundle_state (curr_state);
6337 /* The following function tries to issue INSN for the current
6338 state without advancing processor cycle. If it failed, the
6339 function returns FALSE and frees the current state. */
6342 try_issue_insn (curr_state, insn)
6343 struct bundle_state *curr_state;
6346 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6348 free_bundle_state (curr_state);
6354 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6355 starting with ORIGINATOR without advancing processor cycle. If
6356 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6357 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6358 If it was successful, the function creates new bundle state and
6359 insert into the hash table and into `index_to_bundle_states'. */
6362 issue_nops_and_insn (originator, before_nops_num, insn, try_bundle_end_p,
6364 struct bundle_state *originator;
6365 int before_nops_num;
6367 int try_bundle_end_p, only_bundle_end_p;
6369 struct bundle_state *curr_state;
6371 curr_state = get_free_bundle_state ();
6372 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6373 curr_state->insn = insn;
6374 curr_state->insn_num = originator->insn_num + 1;
6375 curr_state->cost = originator->cost;
6376 curr_state->originator = originator;
6377 curr_state->before_nops_num = before_nops_num;
6378 curr_state->after_nops_num = 0;
6379 curr_state->accumulated_insns_num
6380 = originator->accumulated_insns_num + before_nops_num;
6381 curr_state->branch_deviation = originator->branch_deviation;
6382 if (insn == NULL_RTX)
6384 else if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6386 if (GET_MODE (insn) == TImode)
6388 if (!try_issue_nops (curr_state, before_nops_num))
6390 if (!try_issue_insn (curr_state, insn))
6392 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6393 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6394 && curr_state->accumulated_insns_num % 3 != 0)
6396 free_bundle_state (curr_state);
6400 else if (GET_MODE (insn) != TImode)
6402 if (!try_issue_nops (curr_state, before_nops_num))
6404 if (!try_issue_insn (curr_state, insn))
6406 curr_state->accumulated_insns_num++;
6407 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6408 || asm_noperands (PATTERN (insn)) >= 0)
6410 if (ia64_safe_type (insn) == TYPE_L)
6411 curr_state->accumulated_insns_num++;
6415 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6416 state_transition (curr_state->dfa_state, NULL);
6418 if (!try_issue_nops (curr_state, before_nops_num))
6420 if (!try_issue_insn (curr_state, insn))
6422 curr_state->accumulated_insns_num++;
6423 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6424 || asm_noperands (PATTERN (insn)) >= 0)
6426 /* Finish bundle containing asm insn. */
6427 curr_state->after_nops_num
6428 = 3 - curr_state->accumulated_insns_num % 3;
6429 curr_state->accumulated_insns_num
6430 += 3 - curr_state->accumulated_insns_num % 3;
6432 else if (ia64_safe_type (insn) == TYPE_L)
6433 curr_state->accumulated_insns_num++;
6435 if (ia64_safe_type (insn) == TYPE_B)
6436 curr_state->branch_deviation
6437 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6438 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6440 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6443 struct bundle_state *curr_state1;
6444 struct bundle_state *allocated_states_chain;
6446 curr_state1 = get_free_bundle_state ();
6447 dfa_state = curr_state1->dfa_state;
6448 allocated_states_chain = curr_state1->allocated_states_chain;
6449 *curr_state1 = *curr_state;
6450 curr_state1->dfa_state = dfa_state;
6451 curr_state1->allocated_states_chain = allocated_states_chain;
6452 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6454 curr_state = curr_state1;
6456 if (!try_issue_nops (curr_state,
6457 3 - curr_state->accumulated_insns_num % 3))
6459 curr_state->after_nops_num
6460 = 3 - curr_state->accumulated_insns_num % 3;
6461 curr_state->accumulated_insns_num
6462 += 3 - curr_state->accumulated_insns_num % 3;
6464 if (!insert_bundle_state (curr_state))
6465 free_bundle_state (curr_state);
6469 /* The following function returns position in the two window bundle
6476 if (cpu_unit_reservation_p (state, pos_6))
6478 else if (cpu_unit_reservation_p (state, pos_5))
6480 else if (cpu_unit_reservation_p (state, pos_4))
6482 else if (cpu_unit_reservation_p (state, pos_3))
6484 else if (cpu_unit_reservation_p (state, pos_2))
6486 else if (cpu_unit_reservation_p (state, pos_1))
6492 /* The function returns code of a possible template for given position
6493 and state. The function should be called only with 2 values of
6494 position equal to 3 or 6. */
6497 get_template (state, pos)
6504 if (cpu_unit_reservation_p (state, _0mii_))
6506 else if (cpu_unit_reservation_p (state, _0mmi_))
6508 else if (cpu_unit_reservation_p (state, _0mfi_))
6510 else if (cpu_unit_reservation_p (state, _0mmf_))
6512 else if (cpu_unit_reservation_p (state, _0bbb_))
6514 else if (cpu_unit_reservation_p (state, _0mbb_))
6516 else if (cpu_unit_reservation_p (state, _0mib_))
6518 else if (cpu_unit_reservation_p (state, _0mmb_))
6520 else if (cpu_unit_reservation_p (state, _0mfb_))
6522 else if (cpu_unit_reservation_p (state, _0mlx_))
6527 if (cpu_unit_reservation_p (state, _1mii_))
6529 else if (cpu_unit_reservation_p (state, _1mmi_))
6531 else if (cpu_unit_reservation_p (state, _1mfi_))
6533 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6535 else if (cpu_unit_reservation_p (state, _1bbb_))
6537 else if (cpu_unit_reservation_p (state, _1mbb_))
6539 else if (cpu_unit_reservation_p (state, _1mib_))
6541 else if (cpu_unit_reservation_p (state, _1mmb_))
6543 else if (cpu_unit_reservation_p (state, _1mfb_))
6545 else if (cpu_unit_reservation_p (state, _1mlx_))
6554 /* The following function returns an insn important for insn bundling
6555 followed by INSN and before TAIL. */
6558 get_next_important_insn (insn, tail)
6561 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6563 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6564 && GET_CODE (PATTERN (insn)) != USE
6565 && GET_CODE (PATTERN (insn)) != CLOBBER)
6570 /* The following function does insn bundling. Bundling algorithm is
6571 based on dynamic programming. It tries to insert different number of
6572 nop insns before/after the real insns. At the end of EBB, it chooses the
6573 best alternative and then, moving back in EBB, inserts templates for
6574 the best alternative. The algorithm is directed by information
6575 (changes of simulated processor cycle) created by the 2nd insn
6579 bundling (dump, verbose, prev_head_insn, tail)
6582 rtx prev_head_insn, tail;
6584 struct bundle_state *curr_state, *next_state, *best_state;
6585 rtx insn, next_insn;
6587 int i, bundle_end_p, only_bundle_end_p, asm_p;
6588 int pos = 0, max_pos, template0, template1;
6591 enum attr_type type;
6594 for (insn = NEXT_INSN (prev_head_insn);
6595 insn && insn != tail;
6596 insn = NEXT_INSN (insn))
6602 dfa_clean_insn_cache ();
6603 initiate_bundle_state_table ();
6604 index_to_bundle_states = xmalloc ((insn_num + 2)
6605 * sizeof (struct bundle_state *));
6606 /* First (forward) pass -- generates states. */
6607 curr_state = get_free_bundle_state ();
6608 curr_state->insn = NULL;
6609 curr_state->before_nops_num = 0;
6610 curr_state->after_nops_num = 0;
6611 curr_state->insn_num = 0;
6612 curr_state->cost = 0;
6613 curr_state->accumulated_insns_num = 0;
6614 curr_state->branch_deviation = 0;
6615 curr_state->next = NULL;
6616 curr_state->originator = NULL;
6617 state_reset (curr_state->dfa_state);
6618 index_to_bundle_states [0] = curr_state;
6620 for (insn = NEXT_INSN (prev_head_insn);
6622 insn = NEXT_INSN (insn))
6624 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6625 || GET_CODE (PATTERN (insn)) == USE
6626 || GET_CODE (PATTERN (insn)) == CLOBBER)
6627 && GET_MODE (insn) == TImode)
6629 PUT_MODE (insn, VOIDmode);
6630 for (next_insn = NEXT_INSN (insn);
6632 next_insn = NEXT_INSN (next_insn))
6633 if (INSN_P (next_insn)
6634 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6635 && GET_CODE (PATTERN (next_insn)) != USE
6636 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6638 PUT_MODE (next_insn, TImode);
6642 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6647 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6648 || GET_CODE (PATTERN (insn)) == USE
6649 || GET_CODE (PATTERN (insn)) == CLOBBER)
6651 type = ia64_safe_type (insn);
6652 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6654 index_to_bundle_states [insn_num] = NULL;
6655 for (curr_state = index_to_bundle_states [insn_num - 1];
6657 curr_state = next_state)
6659 pos = curr_state->accumulated_insns_num % 3;
6660 next_state = curr_state->next;
6661 /* Finish the current bundle in order to start a subsequent
6662 asm insn in a new bundle. */
6664 = (next_insn != NULL_RTX
6665 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6666 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6668 = (only_bundle_end_p || next_insn == NULL_RTX
6669 || (GET_MODE (next_insn) == TImode
6670 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6671 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6673 /* We need to insert 2 Nops for cases like M_MII. */
6674 || (type == TYPE_M && ia64_tune == PROCESSOR_ITANIUM
6675 && !bundle_end_p && pos == 1))
6676 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6678 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6680 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6683 if (index_to_bundle_states [insn_num] == NULL)
6685 for (curr_state = index_to_bundle_states [insn_num];
6687 curr_state = curr_state->next)
6688 if (verbose >= 2 && dump)
6692 unsigned short one_automaton_state;
6693 unsigned short oneb_automaton_state;
6694 unsigned short two_automaton_state;
6695 unsigned short twob_automaton_state;
6700 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6701 curr_state->unique_num,
6702 (curr_state->originator == NULL
6703 ? -1 : curr_state->originator->unique_num),
6705 curr_state->before_nops_num, curr_state->after_nops_num,
6706 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6707 (ia64_tune == PROCESSOR_ITANIUM
6708 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6709 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6713 if (index_to_bundle_states [insn_num] == NULL)
6715 /* Finding state with a minimal cost: */
6717 for (curr_state = index_to_bundle_states [insn_num];
6719 curr_state = curr_state->next)
6720 if (curr_state->accumulated_insns_num % 3 == 0
6721 && (best_state == NULL || best_state->cost > curr_state->cost
6722 || (best_state->cost == curr_state->cost
6723 && (curr_state->accumulated_insns_num
6724 < best_state->accumulated_insns_num
6725 || (curr_state->accumulated_insns_num
6726 == best_state->accumulated_insns_num
6727 && curr_state->branch_deviation
6728 < best_state->branch_deviation)))))
6729 best_state = curr_state;
6730 /* Second (backward) pass: adding nops and templates: */
6731 insn_num = best_state->before_nops_num;
6732 template0 = template1 = -1;
6733 for (curr_state = best_state;
6734 curr_state->originator != NULL;
6735 curr_state = curr_state->originator)
6737 insn = curr_state->insn;
6738 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
6739 || asm_noperands (PATTERN (insn)) >= 0);
6741 if (verbose >= 2 && dump)
6745 unsigned short one_automaton_state;
6746 unsigned short oneb_automaton_state;
6747 unsigned short two_automaton_state;
6748 unsigned short twob_automaton_state;
6753 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6754 curr_state->unique_num,
6755 (curr_state->originator == NULL
6756 ? -1 : curr_state->originator->unique_num),
6758 curr_state->before_nops_num, curr_state->after_nops_num,
6759 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6760 (ia64_tune == PROCESSOR_ITANIUM
6761 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6762 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6765 max_pos = get_max_pos (curr_state->dfa_state);
6766 if (max_pos == 6 || (max_pos == 3 && template0 < 0))
6770 template0 = get_template (curr_state->dfa_state, 3);
6773 template1 = get_template (curr_state->dfa_state, 3);
6774 template0 = get_template (curr_state->dfa_state, 6);
6777 if (max_pos > 3 && template1 < 0)
6781 template1 = get_template (curr_state->dfa_state, 3);
6785 for (i = 0; i < curr_state->after_nops_num; i++)
6788 emit_insn_after (nop, insn);
6796 b = gen_bundle_selector (GEN_INT (template0));
6797 ia64_emit_insn_before (b, nop);
6798 template0 = template1;
6802 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6803 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6804 && asm_noperands (PATTERN (insn)) < 0)
6806 if (ia64_safe_type (insn) == TYPE_L)
6811 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6812 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6813 && asm_noperands (PATTERN (insn)) < 0)
6817 b = gen_bundle_selector (GEN_INT (template0));
6818 ia64_emit_insn_before (b, insn);
6819 b = PREV_INSN (insn);
6821 template0 = template1;
6824 for (i = 0; i < curr_state->before_nops_num; i++)
6827 ia64_emit_insn_before (nop, insn);
6828 nop = PREV_INSN (insn);
6837 b = gen_bundle_selector (GEN_INT (template0));
6838 ia64_emit_insn_before (b, insn);
6839 b = PREV_INSN (insn);
6841 template0 = template1;
6846 if (ia64_tune == PROCESSOR_ITANIUM)
6847 /* Insert additional cycles for MM-insns: */
6848 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6853 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6854 || GET_CODE (PATTERN (insn)) == USE
6855 || GET_CODE (PATTERN (insn)) == CLOBBER)
6857 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6858 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
6864 last = prev_active_insn (insn);
6865 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
6867 last = prev_active_insn (last);
6869 for (;; last = prev_active_insn (last))
6870 if (recog_memoized (last) == CODE_FOR_bundle_selector)
6872 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
6875 = gen_bundle_selector (GEN_INT (2)); /* -> MFI */
6878 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6880 if ((pred_stop_p && n == 0) || n > 2
6881 || (template0 == 9 && n != 0))
6883 for (j = 3 - n; j > 0; j --)
6884 ia64_emit_insn_before (gen_nop (), insn);
6885 add_cycles [INSN_UID (insn)]--;
6886 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
6887 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6890 add_cycles [INSN_UID (insn)]--;
6891 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
6893 /* Insert .MII bundle. */
6894 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
6896 ia64_emit_insn_before (gen_nop (), insn);
6897 ia64_emit_insn_before (gen_nop (), insn);
6900 ia64_emit_insn_before
6901 (gen_insn_group_barrier (GEN_INT (3)), insn);
6904 ia64_emit_insn_before (gen_nop (), insn);
6905 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6908 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
6910 for (j = n; j > 0; j --)
6911 ia64_emit_insn_before (gen_nop (), insn);
6913 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6917 free (index_to_bundle_states);
6918 finish_bundle_state_table ();
6920 dfa_clean_insn_cache ();
6923 /* The following function is called at the end of scheduling BB or
6924 EBB. After reload, it inserts stop bits and does insn bundling. */
6927 ia64_sched_finish (dump, sched_verbose)
6932 fprintf (dump, "// Finishing schedule.\n");
6933 if (!reload_completed)
6935 if (reload_completed)
6937 final_emit_insn_group_barriers (dump);
6938 bundling (dump, sched_verbose, current_sched_info->prev_head,
6939 current_sched_info->next_tail);
6940 if (sched_verbose && dump)
6941 fprintf (dump, "// finishing %d-%d\n",
6942 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
6943 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
6949 /* The following function inserts stop bits in scheduled BB or EBB. */
6952 final_emit_insn_group_barriers (dump)
6953 FILE *dump ATTRIBUTE_UNUSED;
6956 int need_barrier_p = 0;
6957 rtx prev_insn = NULL_RTX;
6959 init_insn_group_barriers ();
6961 for (insn = NEXT_INSN (current_sched_info->prev_head);
6962 insn != current_sched_info->next_tail;
6963 insn = NEXT_INSN (insn))
6965 if (GET_CODE (insn) == BARRIER)
6967 rtx last = prev_active_insn (insn);
6971 if (GET_CODE (last) == JUMP_INSN
6972 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6973 last = prev_active_insn (last);
6974 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6975 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6977 init_insn_group_barriers ();
6979 prev_insn = NULL_RTX;
6981 else if (INSN_P (insn))
6983 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6985 init_insn_group_barriers ();
6987 prev_insn = NULL_RTX;
6989 else if (need_barrier_p || group_barrier_needed_p (insn))
6991 if (TARGET_EARLY_STOP_BITS)
6996 last != current_sched_info->prev_head;
6997 last = PREV_INSN (last))
6998 if (INSN_P (last) && GET_MODE (last) == TImode
6999 && stops_p [INSN_UID (last)])
7001 if (last == current_sched_info->prev_head)
7003 last = prev_active_insn (last);
7005 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7006 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7008 init_insn_group_barriers ();
7009 for (last = NEXT_INSN (last);
7011 last = NEXT_INSN (last))
7013 group_barrier_needed_p (last);
7017 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7019 init_insn_group_barriers ();
7021 group_barrier_needed_p (insn);
7022 prev_insn = NULL_RTX;
7024 else if (recog_memoized (insn) >= 0)
7026 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7027 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7028 || asm_noperands (PATTERN (insn)) >= 0);
7035 /* If the following function returns TRUE, we will use the the DFA
7039 ia64_use_dfa_pipeline_interface ()
7044 /* If the following function returns TRUE, we will use the the DFA
7048 ia64_first_cycle_multipass_dfa_lookahead ()
7050 return (reload_completed ? 6 : 4);
7053 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7056 ia64_init_dfa_pre_cycle_insn ()
7058 if (temp_dfa_state == NULL)
7060 dfa_state_size = state_size ();
7061 temp_dfa_state = xmalloc (dfa_state_size);
7062 prev_cycle_state = xmalloc (dfa_state_size);
7064 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7065 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7066 recog_memoized (dfa_pre_cycle_insn);
7067 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7068 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7069 recog_memoized (dfa_stop_insn);
7072 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7073 used by the DFA insn scheduler. */
7076 ia64_dfa_pre_cycle_insn ()
7078 return dfa_pre_cycle_insn;
7081 /* The following function returns TRUE if PRODUCER (of type ilog or
7082 ld) produces address for CONSUMER (of type st or stf). */
7085 ia64_st_address_bypass_p (producer, consumer)
7091 if (producer == NULL_RTX || consumer == NULL_RTX)
7093 dest = ia64_single_set (producer);
7094 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7095 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7097 if (GET_CODE (reg) == SUBREG)
7098 reg = SUBREG_REG (reg);
7099 dest = ia64_single_set (consumer);
7100 if (dest == NULL_RTX || (mem = SET_DEST (dest)) == NULL_RTX
7101 || GET_CODE (mem) != MEM)
7103 return reg_mentioned_p (reg, mem);
7106 /* The following function returns TRUE if PRODUCER (of type ilog or
7107 ld) produces address for CONSUMER (of type ld or fld). */
7110 ia64_ld_address_bypass_p (producer, consumer)
7114 rtx dest, src, reg, mem;
7116 if (producer == NULL_RTX || consumer == NULL_RTX)
7118 dest = ia64_single_set (producer);
7119 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7120 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7122 if (GET_CODE (reg) == SUBREG)
7123 reg = SUBREG_REG (reg);
7124 src = ia64_single_set (consumer);
7125 if (src == NULL_RTX || (mem = SET_SRC (src)) == NULL_RTX)
7127 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7128 mem = XVECEXP (mem, 0, 0);
7129 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7130 mem = XEXP (mem, 0);
7132 /* Note that LO_SUM is used for GOT loads. */
7133 if (GET_CODE (mem) != LO_SUM && GET_CODE (mem) != MEM)
7136 return reg_mentioned_p (reg, mem);
7139 /* The following function returns TRUE if INSN produces address for a
7140 load/store insn. We will place such insns into M slot because it
7141 decreases its latency time. */
7144 ia64_produce_address_p (insn)
7151 /* Emit pseudo-ops for the assembler to describe predicate relations.
7152 At present this assumes that we only consider predicate pairs to
7153 be mutex, and that the assembler can deduce proper values from
7154 straight-line code. */
7157 emit_predicate_relation_info ()
7161 FOR_EACH_BB_REVERSE (bb)
7164 rtx head = bb->head;
7166 /* We only need such notes at code labels. */
7167 if (GET_CODE (head) != CODE_LABEL)
7169 if (GET_CODE (NEXT_INSN (head)) == NOTE
7170 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7171 head = NEXT_INSN (head);
7173 for (r = PR_REG (0); r < PR_REG (64); r += 2)
7174 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7176 rtx p = gen_rtx_REG (BImode, r);
7177 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7178 if (head == bb->end)
7184 /* Look for conditional calls that do not return, and protect predicate
7185 relations around them. Otherwise the assembler will assume the call
7186 returns, and complain about uses of call-clobbered predicates after
7188 FOR_EACH_BB_REVERSE (bb)
7190 rtx insn = bb->head;
7194 if (GET_CODE (insn) == CALL_INSN
7195 && GET_CODE (PATTERN (insn)) == COND_EXEC
7196 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7198 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7199 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7200 if (bb->head == insn)
7202 if (bb->end == insn)
7206 if (insn == bb->end)
7208 insn = NEXT_INSN (insn);
7213 /* Perform machine dependent operations on the rtl chain INSNS. */
7218 /* We are freeing block_for_insn in the toplev to keep compatibility
7219 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7220 compute_bb_for_insn ();
7222 /* If optimizing, we'll have split before scheduling. */
7224 split_all_insns (0);
7226 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7227 non-optimizing bootstrap. */
7228 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7230 if (ia64_flag_schedule_insns2)
7232 timevar_push (TV_SCHED2);
7233 ia64_final_schedule = 1;
7235 initiate_bundle_states ();
7236 ia64_nop = make_insn_raw (gen_nop ());
7237 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7238 recog_memoized (ia64_nop);
7239 clocks_length = get_max_uid () + 1;
7240 stops_p = (char *) xmalloc (clocks_length);
7241 memset (stops_p, 0, clocks_length);
7242 if (ia64_tune == PROCESSOR_ITANIUM)
7244 clocks = (int *) xmalloc (clocks_length * sizeof (int));
7245 memset (clocks, 0, clocks_length * sizeof (int));
7246 add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
7247 memset (add_cycles, 0, clocks_length * sizeof (int));
7249 if (ia64_tune == PROCESSOR_ITANIUM2)
7251 pos_1 = get_cpu_unit_code ("2_1");
7252 pos_2 = get_cpu_unit_code ("2_2");
7253 pos_3 = get_cpu_unit_code ("2_3");
7254 pos_4 = get_cpu_unit_code ("2_4");
7255 pos_5 = get_cpu_unit_code ("2_5");
7256 pos_6 = get_cpu_unit_code ("2_6");
7257 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7258 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7259 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7260 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7261 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7262 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7263 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7264 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7265 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7266 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7267 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7268 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7269 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7270 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7271 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7272 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7273 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7274 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7275 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7276 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7280 pos_1 = get_cpu_unit_code ("1_1");
7281 pos_2 = get_cpu_unit_code ("1_2");
7282 pos_3 = get_cpu_unit_code ("1_3");
7283 pos_4 = get_cpu_unit_code ("1_4");
7284 pos_5 = get_cpu_unit_code ("1_5");
7285 pos_6 = get_cpu_unit_code ("1_6");
7286 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7287 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7288 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7289 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7290 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7291 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7292 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7293 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7294 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7295 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7296 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7297 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7298 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7299 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7300 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7301 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7302 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7303 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7304 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7305 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7307 schedule_ebbs (rtl_dump_file);
7308 finish_bundle_states ();
7309 if (ia64_tune == PROCESSOR_ITANIUM)
7315 emit_insn_group_barriers (rtl_dump_file);
7317 ia64_final_schedule = 0;
7318 timevar_pop (TV_SCHED2);
7321 emit_all_insn_group_barriers (rtl_dump_file);
7323 /* A call must not be the last instruction in a function, so that the
7324 return address is still within the function, so that unwinding works
7325 properly. Note that IA-64 differs from dwarf2 on this point. */
7326 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7331 insn = get_last_insn ();
7332 if (! INSN_P (insn))
7333 insn = prev_active_insn (insn);
7334 if (GET_CODE (insn) == INSN
7335 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7336 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7339 insn = prev_active_insn (insn);
7341 if (GET_CODE (insn) == CALL_INSN)
7344 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7345 emit_insn (gen_break_f ());
7346 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7351 emit_predicate_relation_info ();
7354 /* Return true if REGNO is used by the epilogue. */
7357 ia64_epilogue_uses (regno)
7363 /* When a function makes a call through a function descriptor, we
7364 will write a (potentially) new value to "gp". After returning
7365 from such a call, we need to make sure the function restores the
7366 original gp-value, even if the function itself does not use the
7368 return (TARGET_CONST_GP && !(TARGET_AUTO_PIC || TARGET_NO_PIC));
7370 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7371 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7372 /* For functions defined with the syscall_linkage attribute, all
7373 input registers are marked as live at all function exits. This
7374 prevents the register allocator from using the input registers,
7375 which in turn makes it possible to restart a system call after
7376 an interrupt without having to save/restore the input registers.
7377 This also prevents kernel data from leaking to application code. */
7378 return lookup_attribute ("syscall_linkage",
7379 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7382 /* Conditional return patterns can't represent the use of `b0' as
7383 the return address, so we force the value live this way. */
7387 /* Likewise for ar.pfs, which is used by br.ret. */
7395 /* Return true if REGNO is used by the frame unwinder. */
7398 ia64_eh_uses (regno)
7401 if (! reload_completed)
7404 if (current_frame_info.reg_save_b0
7405 && regno == current_frame_info.reg_save_b0)
7407 if (current_frame_info.reg_save_pr
7408 && regno == current_frame_info.reg_save_pr)
7410 if (current_frame_info.reg_save_ar_pfs
7411 && regno == current_frame_info.reg_save_ar_pfs)
7413 if (current_frame_info.reg_save_ar_unat
7414 && regno == current_frame_info.reg_save_ar_unat)
7416 if (current_frame_info.reg_save_ar_lc
7417 && regno == current_frame_info.reg_save_ar_lc)
7423 /* Return true if this goes in small data/bss. */
7425 /* ??? We could also support own long data here. Generating movl/add/ld8
7426 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7427 code faster because there is one less load. This also includes incomplete
7428 types which can't go in sdata/sbss. */
7431 ia64_in_small_data_p (exp)
7434 if (TARGET_NO_SDATA)
7437 /* We want to merge strings, so we never consider them small data. */
7438 if (TREE_CODE (exp) == STRING_CST)
7441 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7443 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7444 if (strcmp (section, ".sdata") == 0
7445 || strcmp (section, ".sbss") == 0)
7450 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7452 /* If this is an incomplete type with size 0, then we can't put it
7453 in sdata because it might be too big when completed. */
7454 if (size > 0 && size <= ia64_section_threshold)
7461 /* Output assembly directives for prologue regions. */
7463 /* The current basic block number. */
7465 static bool last_block;
7467 /* True if we need a copy_state command at the start of the next block. */
7469 static bool need_copy_state;
7471 /* The function emits unwind directives for the start of an epilogue. */
7476 /* If this isn't the last block of the function, then we need to label the
7477 current state, and copy it back in at the start of the next block. */
7481 fprintf (asm_out_file, "\t.label_state 1\n");
7482 need_copy_state = true;
7485 fprintf (asm_out_file, "\t.restore sp\n");
7488 /* This function processes a SET pattern looking for specific patterns
7489 which result in emitting an assembly directive required for unwinding. */
7492 process_set (asm_out_file, pat)
7496 rtx src = SET_SRC (pat);
7497 rtx dest = SET_DEST (pat);
7498 int src_regno, dest_regno;
7500 /* Look for the ALLOC insn. */
7501 if (GET_CODE (src) == UNSPEC_VOLATILE
7502 && XINT (src, 1) == UNSPECV_ALLOC
7503 && GET_CODE (dest) == REG)
7505 dest_regno = REGNO (dest);
7507 /* If this isn't the final destination for ar.pfs, the alloc
7508 shouldn't have been marked frame related. */
7509 if (dest_regno != current_frame_info.reg_save_ar_pfs)
7512 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7513 ia64_dbx_register_number (dest_regno));
7517 /* Look for SP = .... */
7518 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7520 if (GET_CODE (src) == PLUS)
7522 rtx op0 = XEXP (src, 0);
7523 rtx op1 = XEXP (src, 1);
7524 if (op0 == dest && GET_CODE (op1) == CONST_INT)
7526 if (INTVAL (op1) < 0)
7527 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7530 process_epilogue ();
7535 else if (GET_CODE (src) == REG
7536 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
7537 process_epilogue ();
7544 /* Register move we need to look at. */
7545 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7547 src_regno = REGNO (src);
7548 dest_regno = REGNO (dest);
7553 /* Saving return address pointer. */
7554 if (dest_regno != current_frame_info.reg_save_b0)
7556 fprintf (asm_out_file, "\t.save rp, r%d\n",
7557 ia64_dbx_register_number (dest_regno));
7561 if (dest_regno != current_frame_info.reg_save_pr)
7563 fprintf (asm_out_file, "\t.save pr, r%d\n",
7564 ia64_dbx_register_number (dest_regno));
7567 case AR_UNAT_REGNUM:
7568 if (dest_regno != current_frame_info.reg_save_ar_unat)
7570 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7571 ia64_dbx_register_number (dest_regno));
7575 if (dest_regno != current_frame_info.reg_save_ar_lc)
7577 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7578 ia64_dbx_register_number (dest_regno));
7581 case STACK_POINTER_REGNUM:
7582 if (dest_regno != HARD_FRAME_POINTER_REGNUM
7583 || ! frame_pointer_needed)
7585 fprintf (asm_out_file, "\t.vframe r%d\n",
7586 ia64_dbx_register_number (dest_regno));
7590 /* Everything else should indicate being stored to memory. */
7595 /* Memory store we need to look at. */
7596 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7602 if (GET_CODE (XEXP (dest, 0)) == REG)
7604 base = XEXP (dest, 0);
7607 else if (GET_CODE (XEXP (dest, 0)) == PLUS
7608 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
7610 base = XEXP (XEXP (dest, 0), 0);
7611 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7616 if (base == hard_frame_pointer_rtx)
7618 saveop = ".savepsp";
7621 else if (base == stack_pointer_rtx)
7626 src_regno = REGNO (src);
7630 if (current_frame_info.reg_save_b0 != 0)
7632 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7636 if (current_frame_info.reg_save_pr != 0)
7638 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7642 if (current_frame_info.reg_save_ar_lc != 0)
7644 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7648 if (current_frame_info.reg_save_ar_pfs != 0)
7650 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7653 case AR_UNAT_REGNUM:
7654 if (current_frame_info.reg_save_ar_unat != 0)
7656 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
7663 fprintf (asm_out_file, "\t.save.g 0x%x\n",
7664 1 << (src_regno - GR_REG (4)));
7672 fprintf (asm_out_file, "\t.save.b 0x%x\n",
7673 1 << (src_regno - BR_REG (1)));
7680 fprintf (asm_out_file, "\t.save.f 0x%x\n",
7681 1 << (src_regno - FR_REG (2)));
7684 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7685 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7686 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7687 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7688 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
7689 1 << (src_regno - FR_REG (12)));
7701 /* This function looks at a single insn and emits any directives
7702 required to unwind this insn. */
7704 process_for_unwind_directive (asm_out_file, insn)
7708 if (flag_unwind_tables
7709 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7713 if (GET_CODE (insn) == NOTE
7714 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
7716 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
7718 /* Restore unwind state from immediately before the epilogue. */
7719 if (need_copy_state)
7721 fprintf (asm_out_file, "\t.body\n");
7722 fprintf (asm_out_file, "\t.copy_state 1\n");
7723 need_copy_state = false;
7727 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
7730 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
7732 pat = XEXP (pat, 0);
7734 pat = PATTERN (insn);
7736 switch (GET_CODE (pat))
7739 process_set (asm_out_file, pat);
7745 int limit = XVECLEN (pat, 0);
7746 for (par_index = 0; par_index < limit; par_index++)
7748 rtx x = XVECEXP (pat, 0, par_index);
7749 if (GET_CODE (x) == SET)
7750 process_set (asm_out_file, x);
7763 ia64_init_builtins ()
7765 tree psi_type_node = build_pointer_type (integer_type_node);
7766 tree pdi_type_node = build_pointer_type (long_integer_type_node);
7768 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7769 tree si_ftype_psi_si_si
7770 = build_function_type_list (integer_type_node,
7771 psi_type_node, integer_type_node,
7772 integer_type_node, NULL_TREE);
7774 /* __sync_val_compare_and_swap_di */
7775 tree di_ftype_pdi_di_di
7776 = build_function_type_list (long_integer_type_node,
7777 pdi_type_node, long_integer_type_node,
7778 long_integer_type_node, NULL_TREE);
7779 /* __sync_bool_compare_and_swap_di */
7780 tree si_ftype_pdi_di_di
7781 = build_function_type_list (integer_type_node,
7782 pdi_type_node, long_integer_type_node,
7783 long_integer_type_node, NULL_TREE);
7784 /* __sync_synchronize */
7785 tree void_ftype_void
7786 = build_function_type (void_type_node, void_list_node);
7788 /* __sync_lock_test_and_set_si */
7789 tree si_ftype_psi_si
7790 = build_function_type_list (integer_type_node,
7791 psi_type_node, integer_type_node, NULL_TREE);
7793 /* __sync_lock_test_and_set_di */
7794 tree di_ftype_pdi_di
7795 = build_function_type_list (long_integer_type_node,
7796 pdi_type_node, long_integer_type_node,
7799 /* __sync_lock_release_si */
7801 = build_function_type_list (void_type_node, psi_type_node, NULL_TREE);
7803 /* __sync_lock_release_di */
7805 = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
7807 #define def_builtin(name, type, code) \
7808 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
7810 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
7811 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
7812 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
7813 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
7814 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
7815 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
7816 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di,
7817 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
7819 def_builtin ("__sync_synchronize", void_ftype_void,
7820 IA64_BUILTIN_SYNCHRONIZE);
7822 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
7823 IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
7824 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
7825 IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
7826 def_builtin ("__sync_lock_release_si", void_ftype_psi,
7827 IA64_BUILTIN_LOCK_RELEASE_SI);
7828 def_builtin ("__sync_lock_release_di", void_ftype_pdi,
7829 IA64_BUILTIN_LOCK_RELEASE_DI);
7831 def_builtin ("__builtin_ia64_bsp",
7832 build_function_type (ptr_type_node, void_list_node),
7835 def_builtin ("__builtin_ia64_flushrs",
7836 build_function_type (void_type_node, void_list_node),
7837 IA64_BUILTIN_FLUSHRS);
7839 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
7840 IA64_BUILTIN_FETCH_AND_ADD_SI);
7841 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
7842 IA64_BUILTIN_FETCH_AND_SUB_SI);
7843 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
7844 IA64_BUILTIN_FETCH_AND_OR_SI);
7845 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
7846 IA64_BUILTIN_FETCH_AND_AND_SI);
7847 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
7848 IA64_BUILTIN_FETCH_AND_XOR_SI);
7849 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
7850 IA64_BUILTIN_FETCH_AND_NAND_SI);
7852 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
7853 IA64_BUILTIN_ADD_AND_FETCH_SI);
7854 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
7855 IA64_BUILTIN_SUB_AND_FETCH_SI);
7856 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
7857 IA64_BUILTIN_OR_AND_FETCH_SI);
7858 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
7859 IA64_BUILTIN_AND_AND_FETCH_SI);
7860 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
7861 IA64_BUILTIN_XOR_AND_FETCH_SI);
7862 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
7863 IA64_BUILTIN_NAND_AND_FETCH_SI);
7865 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
7866 IA64_BUILTIN_FETCH_AND_ADD_DI);
7867 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
7868 IA64_BUILTIN_FETCH_AND_SUB_DI);
7869 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
7870 IA64_BUILTIN_FETCH_AND_OR_DI);
7871 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
7872 IA64_BUILTIN_FETCH_AND_AND_DI);
7873 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
7874 IA64_BUILTIN_FETCH_AND_XOR_DI);
7875 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
7876 IA64_BUILTIN_FETCH_AND_NAND_DI);
7878 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
7879 IA64_BUILTIN_ADD_AND_FETCH_DI);
7880 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
7881 IA64_BUILTIN_SUB_AND_FETCH_DI);
7882 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
7883 IA64_BUILTIN_OR_AND_FETCH_DI);
7884 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
7885 IA64_BUILTIN_AND_AND_FETCH_DI);
7886 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
7887 IA64_BUILTIN_XOR_AND_FETCH_DI);
7888 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
7889 IA64_BUILTIN_NAND_AND_FETCH_DI);
7894 /* Expand fetch_and_op intrinsics. The basic code sequence is:
7902 cmpxchgsz.acq tmp = [ptr], tmp
7903 } while (tmp != ret)
7907 ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
7909 enum machine_mode mode;
7913 rtx ret, label, tmp, ccv, insn, mem, value;
7916 arg0 = TREE_VALUE (arglist);
7917 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7918 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
7919 #ifdef POINTERS_EXTEND_UNSIGNED
7920 if (GET_MODE(mem) != Pmode)
7921 mem = convert_memory_address (Pmode, mem);
7923 value = expand_expr (arg1, NULL_RTX, mode, 0);
7925 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
7926 MEM_VOLATILE_P (mem) = 1;
7928 if (target && register_operand (target, mode))
7931 ret = gen_reg_rtx (mode);
7933 emit_insn (gen_mf ());
7935 /* Special case for fetchadd instructions. */
7936 if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
7939 insn = gen_fetchadd_acq_si (ret, mem, value);
7941 insn = gen_fetchadd_acq_di (ret, mem, value);
7946 tmp = gen_reg_rtx (mode);
7947 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
7948 emit_move_insn (tmp, mem);
7950 label = gen_label_rtx ();
7952 emit_move_insn (ret, tmp);
7953 emit_move_insn (ccv, tmp);
7955 /* Perform the specific operation. Special case NAND by noticing
7956 one_cmpl_optab instead. */
7957 if (binoptab == one_cmpl_optab)
7959 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
7960 binoptab = and_optab;
7962 tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
7965 insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
7967 insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
7970 emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, label);
7975 /* Expand op_and_fetch intrinsics. The basic code sequence is:
7982 ret = tmp <op> value;
7983 cmpxchgsz.acq tmp = [ptr], ret
7984 } while (tmp != old)
7988 ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
7990 enum machine_mode mode;
7994 rtx old, label, tmp, ret, ccv, insn, mem, value;
7997 arg0 = TREE_VALUE (arglist);
7998 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7999 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
8000 #ifdef POINTERS_EXTEND_UNSIGNED
8001 if (GET_MODE(mem) != Pmode)
8002 mem = convert_memory_address (Pmode, mem);
8005 value = expand_expr (arg1, NULL_RTX, mode, 0);
8007 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8008 MEM_VOLATILE_P (mem) = 1;
8010 if (target && ! register_operand (target, mode))
8013 emit_insn (gen_mf ());
8014 tmp = gen_reg_rtx (mode);
8015 old = gen_reg_rtx (mode);
8016 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
8018 emit_move_insn (tmp, mem);
8020 label = gen_label_rtx ();
8022 emit_move_insn (old, tmp);
8023 emit_move_insn (ccv, tmp);
8025 /* Perform the specific operation. Special case NAND by noticing
8026 one_cmpl_optab instead. */
8027 if (binoptab == one_cmpl_optab)
8029 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8030 binoptab = and_optab;
8032 ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
8035 insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
8037 insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
8040 emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, label);
8045 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8049 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8052 For bool_ it's the same except return ret == oldval.
8056 ia64_expand_compare_and_swap (rmode, mode, boolp, arglist, target)
8057 enum machine_mode rmode;
8058 enum machine_mode mode;
8063 tree arg0, arg1, arg2;
8064 rtx mem, old, new, ccv, tmp, insn;
8066 arg0 = TREE_VALUE (arglist);
8067 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8068 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8069 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8070 old = expand_expr (arg1, NULL_RTX, mode, 0);
8071 new = expand_expr (arg2, NULL_RTX, mode, 0);
8073 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8074 MEM_VOLATILE_P (mem) = 1;
8076 if (! register_operand (old, mode))
8077 old = copy_to_mode_reg (mode, old);
8078 if (! register_operand (new, mode))
8079 new = copy_to_mode_reg (mode, new);
8081 if (! boolp && target && register_operand (target, mode))
8084 tmp = gen_reg_rtx (mode);
8086 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8088 emit_move_insn (ccv, old);
8091 rtx ccvtmp = gen_reg_rtx (DImode);
8092 emit_insn (gen_zero_extendsidi2 (ccvtmp, old));
8093 emit_move_insn (ccv, ccvtmp);
8095 emit_insn (gen_mf ());
8097 insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
8099 insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
8105 target = gen_reg_rtx (rmode);
8106 return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
8112 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8115 ia64_expand_lock_test_and_set (mode, arglist, target)
8116 enum machine_mode mode;
8121 rtx mem, new, ret, insn;
8123 arg0 = TREE_VALUE (arglist);
8124 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8125 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8126 new = expand_expr (arg1, NULL_RTX, mode, 0);
8128 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8129 MEM_VOLATILE_P (mem) = 1;
8130 if (! register_operand (new, mode))
8131 new = copy_to_mode_reg (mode, new);
8133 if (target && register_operand (target, mode))
8136 ret = gen_reg_rtx (mode);
8139 insn = gen_xchgsi (ret, mem, new);
8141 insn = gen_xchgdi (ret, mem, new);
8147 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8150 ia64_expand_lock_release (mode, arglist, target)
8151 enum machine_mode mode;
8153 rtx target ATTRIBUTE_UNUSED;
8158 arg0 = TREE_VALUE (arglist);
8159 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8161 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8162 MEM_VOLATILE_P (mem) = 1;
8164 emit_move_insn (mem, const0_rtx);
8170 ia64_expand_builtin (exp, target, subtarget, mode, ignore)
8173 rtx subtarget ATTRIBUTE_UNUSED;
8174 enum machine_mode mode ATTRIBUTE_UNUSED;
8175 int ignore ATTRIBUTE_UNUSED;
8177 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8178 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8179 tree arglist = TREE_OPERAND (exp, 1);
8180 enum machine_mode rmode = VOIDmode;
8184 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8185 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8190 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8191 case IA64_BUILTIN_LOCK_RELEASE_SI:
8192 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8193 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8194 case IA64_BUILTIN_FETCH_AND_OR_SI:
8195 case IA64_BUILTIN_FETCH_AND_AND_SI:
8196 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8197 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8198 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8199 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8200 case IA64_BUILTIN_OR_AND_FETCH_SI:
8201 case IA64_BUILTIN_AND_AND_FETCH_SI:
8202 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8203 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8207 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8212 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8217 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8218 case IA64_BUILTIN_LOCK_RELEASE_DI:
8219 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8220 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8221 case IA64_BUILTIN_FETCH_AND_OR_DI:
8222 case IA64_BUILTIN_FETCH_AND_AND_DI:
8223 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8224 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8225 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8226 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8227 case IA64_BUILTIN_OR_AND_FETCH_DI:
8228 case IA64_BUILTIN_AND_AND_FETCH_DI:
8229 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8230 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8240 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8241 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8242 return ia64_expand_compare_and_swap (rmode, mode, 1, arglist,
8245 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8246 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8247 return ia64_expand_compare_and_swap (rmode, mode, 0, arglist,
8250 case IA64_BUILTIN_SYNCHRONIZE:
8251 emit_insn (gen_mf ());
8254 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8255 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8256 return ia64_expand_lock_test_and_set (mode, arglist, target);
8258 case IA64_BUILTIN_LOCK_RELEASE_SI:
8259 case IA64_BUILTIN_LOCK_RELEASE_DI:
8260 return ia64_expand_lock_release (mode, arglist, target);
8262 case IA64_BUILTIN_BSP:
8263 if (! target || ! register_operand (target, DImode))
8264 target = gen_reg_rtx (DImode);
8265 emit_insn (gen_bsp_value (target));
8266 #ifdef POINTERS_EXTEND_UNSIGNED
8267 target = convert_memory_address (ptr_mode, target);
8271 case IA64_BUILTIN_FLUSHRS:
8272 emit_insn (gen_flushrs ());
8275 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8276 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8277 return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
8279 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8280 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8281 return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
8283 case IA64_BUILTIN_FETCH_AND_OR_SI:
8284 case IA64_BUILTIN_FETCH_AND_OR_DI:
8285 return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
8287 case IA64_BUILTIN_FETCH_AND_AND_SI:
8288 case IA64_BUILTIN_FETCH_AND_AND_DI:
8289 return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
8291 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8292 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8293 return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
8295 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8296 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8297 return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
8299 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8300 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8301 return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
8303 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8304 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8305 return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
8307 case IA64_BUILTIN_OR_AND_FETCH_SI:
8308 case IA64_BUILTIN_OR_AND_FETCH_DI:
8309 return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
8311 case IA64_BUILTIN_AND_AND_FETCH_SI:
8312 case IA64_BUILTIN_AND_AND_FETCH_DI:
8313 return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
8315 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8316 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8317 return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
8319 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8320 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8321 return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
8330 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8331 most significant bits of the stack slot. */
8334 ia64_hpux_function_arg_padding (mode, type)
8335 enum machine_mode mode;
8338 /* Exception to normal case for structures/unions/etc. */
8340 if (type && AGGREGATE_TYPE_P (type)
8341 && int_size_in_bytes (type) < UNITS_PER_WORD)
8344 /* This is the standard FUNCTION_ARG_PADDING with !BYTES_BIG_ENDIAN
8345 hardwired to be true. */
8347 return((mode == BLKmode
8348 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
8349 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
8350 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
8351 ? downward : upward);
8354 /* Linked list of all external functions that are to be emitted by GCC.
8355 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8356 order to avoid putting out names that are never really used. */
8358 struct extern_func_list
8360 struct extern_func_list *next; /* next external */
8361 char *name; /* name of the external */
8362 } *extern_func_head = 0;
8365 ia64_hpux_add_extern_decl (name)
8368 struct extern_func_list *p;
8370 p = (struct extern_func_list *) xmalloc (sizeof (struct extern_func_list));
8371 p->name = xmalloc (strlen (name) + 1);
8372 strcpy(p->name, name);
8373 p->next = extern_func_head;
8374 extern_func_head = p;
8377 /* Print out the list of used global functions. */
8380 ia64_hpux_file_end ()
8382 while (extern_func_head)
8384 const char *real_name;
8387 real_name = (* targetm.strip_name_encoding) (extern_func_head->name);
8388 decl = maybe_get_identifier (real_name);
8391 || (! TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (decl)))
8394 TREE_ASM_WRITTEN (decl) = 1;
8395 (*targetm.asm_out.globalize_label) (asm_out_file,
8396 extern_func_head->name);
8397 fputs (TYPE_ASM_OP, asm_out_file);
8398 assemble_name (asm_out_file, extern_func_head->name);
8399 putc (',', asm_out_file);
8400 fprintf (asm_out_file, TYPE_OPERAND_FMT, "function");
8401 putc ('\n', asm_out_file);
8403 extern_func_head = extern_func_head->next;
8408 /* Switch to the section to which we should output X. The only thing
8409 special we do here is to honor small data. */
8412 ia64_select_rtx_section (mode, x, align)
8413 enum machine_mode mode;
8415 unsigned HOST_WIDE_INT align;
8417 if (GET_MODE_SIZE (mode) > 0
8418 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8421 default_elf_select_rtx_section (mode, x, align);
8424 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8425 Pretend flag_pic is always set. */
8428 ia64_rwreloc_select_section (exp, reloc, align)
8431 unsigned HOST_WIDE_INT align;
8433 default_elf_select_section_1 (exp, reloc, align, true);
8437 ia64_rwreloc_unique_section (decl, reloc)
8441 default_unique_section_1 (decl, reloc, true);
8445 ia64_rwreloc_select_rtx_section (mode, x, align)
8446 enum machine_mode mode;
8448 unsigned HOST_WIDE_INT align;
8450 int save_pic = flag_pic;
8452 ia64_select_rtx_section (mode, x, align);
8453 flag_pic = save_pic;
8457 ia64_rwreloc_section_type_flags (decl, name, reloc)
8462 return default_section_type_flags_1 (decl, name, reloc, true);
8466 /* Output the assembler code for a thunk function. THUNK_DECL is the
8467 declaration for the thunk function itself, FUNCTION is the decl for
8468 the target function. DELTA is an immediate constant offset to be
8469 added to THIS. If VCALL_OFFSET is nonzero, the word at
8470 *(*this + vcall_offset) should be added to THIS. */
8473 ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
8475 tree thunk ATTRIBUTE_UNUSED;
8476 HOST_WIDE_INT delta;
8477 HOST_WIDE_INT vcall_offset;
8480 rtx this, insn, funexp;
8482 reload_completed = 1;
8483 epilogue_completed = 1;
8486 /* Set things up as ia64_expand_prologue might. */
8487 last_scratch_gr_reg = 15;
8489 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8490 current_frame_info.spill_cfa_off = -16;
8491 current_frame_info.n_input_regs = 1;
8492 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8494 if (!TARGET_REG_NAMES)
8495 reg_names[IN_REG (0)] = ia64_reg_numbers[0];
8497 /* Mark the end of the (empty) prologue. */
8498 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
8500 this = gen_rtx_REG (Pmode, IN_REG (0));
8502 /* Apply the constant offset, if required. */
8505 rtx delta_rtx = GEN_INT (delta);
8507 if (!CONST_OK_FOR_I (delta))
8509 rtx tmp = gen_rtx_REG (Pmode, 2);
8510 emit_move_insn (tmp, delta_rtx);
8513 emit_insn (gen_adddi3 (this, this, delta_rtx));
8516 /* Apply the offset from the vtable, if required. */
8519 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8520 rtx tmp = gen_rtx_REG (Pmode, 2);
8522 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8524 if (!CONST_OK_FOR_J (vcall_offset))
8526 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8527 emit_move_insn (tmp2, vcall_offset_rtx);
8528 vcall_offset_rtx = tmp2;
8530 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8532 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8534 emit_insn (gen_adddi3 (this, this, tmp));
8537 /* Generate a tail call to the target function. */
8538 if (! TREE_USED (function))
8540 assemble_external (function);
8541 TREE_USED (function) = 1;
8543 funexp = XEXP (DECL_RTL (function), 0);
8544 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8545 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8546 insn = get_last_insn ();
8547 SIBLING_CALL_P (insn) = 1;
8549 /* Code generation for calls relies on splitting. */
8550 reload_completed = 1;
8551 epilogue_completed = 1;
8552 try_split (PATTERN (insn), insn, 0);
8556 /* Run just enough of rest_of_compilation to get the insns emitted.
8557 There's not really enough bulk here to make other passes such as
8558 instruction scheduling worth while. Note that use_thunk calls
8559 assemble_start_function and assemble_end_function. */
8561 insn_locators_initialize ();
8562 emit_all_insn_group_barriers (NULL);
8563 insn = get_insns ();
8564 shorten_branches (insn);
8565 final_start_function (insn, file, 1);
8566 final (insn, file, 1, 0);
8567 final_end_function ();
8569 reload_completed = 0;
8570 epilogue_completed = 0;
8574 #include "gt-ia64.h"