1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
57 /* This is used for communication between ASM_OUTPUT_LABEL and
58 ASM_OUTPUT_LABELREF. */
59 int ia64_asm_output_label = 0;
61 /* Define the information needed to generate branch and scc insns. This is
62 stored from the compare operation. */
63 struct rtx_def * ia64_compare_op0;
64 struct rtx_def * ia64_compare_op1;
66 /* Register names for ia64_expand_prologue. */
67 static const char * const ia64_reg_numbers[96] =
68 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
69 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
70 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
71 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
72 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
73 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
74 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
75 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
76 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
77 "r104","r105","r106","r107","r108","r109","r110","r111",
78 "r112","r113","r114","r115","r116","r117","r118","r119",
79 "r120","r121","r122","r123","r124","r125","r126","r127"};
81 /* ??? These strings could be shared with REGISTER_NAMES. */
82 static const char * const ia64_input_reg_names[8] =
83 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
85 /* ??? These strings could be shared with REGISTER_NAMES. */
86 static const char * const ia64_local_reg_names[80] =
87 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
88 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
89 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
90 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
91 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
92 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
93 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
94 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
95 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
96 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
98 /* ??? These strings could be shared with REGISTER_NAMES. */
99 static const char * const ia64_output_reg_names[8] =
100 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
102 /* Which cpu are we scheduling for. */
103 enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
105 /* Determines whether we run our final scheduling pass or not. We always
106 avoid the normal second scheduling pass. */
107 static int ia64_flag_schedule_insns2;
109 /* Determines whether we run variable tracking in machine dependent
111 static int ia64_flag_var_tracking;
113 /* Variables which are this size or smaller are put in the sdata/sbss
116 unsigned int ia64_section_threshold;
118 /* The following variable is used by the DFA insn scheduler. The value is
119 TRUE if we do insn bundling instead of insn scheduling. */
122 /* Structure to be filled in by ia64_compute_frame_size with register
123 save masks and offsets for the current function. */
125 struct ia64_frame_info
127 HOST_WIDE_INT total_size; /* size of the stack frame, not including
128 the caller's scratch area. */
129 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
130 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
131 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
132 HARD_REG_SET mask; /* mask of saved registers. */
133 unsigned int gr_used_mask; /* mask of registers in use as gr spill
134 registers or long-term scratches. */
135 int n_spilled; /* number of spilled registers. */
136 int reg_fp; /* register for fp. */
137 int reg_save_b0; /* save register for b0. */
138 int reg_save_pr; /* save register for prs. */
139 int reg_save_ar_pfs; /* save register for ar.pfs. */
140 int reg_save_ar_unat; /* save register for ar.unat. */
141 int reg_save_ar_lc; /* save register for ar.lc. */
142 int reg_save_gp; /* save register for gp. */
143 int n_input_regs; /* number of input registers used. */
144 int n_local_regs; /* number of local registers used. */
145 int n_output_regs; /* number of output registers used. */
146 int n_rotate_regs; /* number of rotating registers used. */
148 char need_regstk; /* true if a .regstk directive needed. */
149 char initialized; /* true if the data is finalized. */
152 /* Current frame information calculated by ia64_compute_frame_size. */
153 static struct ia64_frame_info current_frame_info;
155 static int ia64_first_cycle_multipass_dfa_lookahead (void);
156 static void ia64_dependencies_evaluation_hook (rtx, rtx);
157 static void ia64_init_dfa_pre_cycle_insn (void);
158 static rtx ia64_dfa_pre_cycle_insn (void);
159 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
160 static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
161 static rtx gen_tls_get_addr (void);
162 static rtx gen_thread_pointer (void);
163 static int find_gr_spill (int);
164 static int next_scratch_gr_reg (void);
165 static void mark_reg_gr_used_mask (rtx, void *);
166 static void ia64_compute_frame_size (HOST_WIDE_INT);
167 static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
168 static void finish_spill_pointers (void);
169 static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
170 static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
171 static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
172 static rtx gen_movdi_x (rtx, rtx, rtx);
173 static rtx gen_fr_spill_x (rtx, rtx, rtx);
174 static rtx gen_fr_restore_x (rtx, rtx, rtx);
176 static enum machine_mode hfa_element_mode (tree, bool);
177 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
179 static bool ia64_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
181 static int ia64_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
183 static bool ia64_function_ok_for_sibcall (tree, tree);
184 static bool ia64_return_in_memory (tree, tree);
185 static bool ia64_rtx_costs (rtx, int, int, int *);
186 static void fix_range (const char *);
187 static bool ia64_handle_option (size_t, const char *, int);
188 static struct machine_function * ia64_init_machine_status (void);
189 static void emit_insn_group_barriers (FILE *);
190 static void emit_all_insn_group_barriers (FILE *);
191 static void final_emit_insn_group_barriers (FILE *);
192 static void emit_predicate_relation_info (void);
193 static void ia64_reorg (void);
194 static bool ia64_in_small_data_p (tree);
195 static void process_epilogue (void);
196 static int process_set (FILE *, rtx);
198 static bool ia64_assemble_integer (rtx, unsigned int, int);
199 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
200 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
201 static void ia64_output_function_end_prologue (FILE *);
203 static int ia64_issue_rate (void);
204 static int ia64_adjust_cost (rtx, rtx, rtx, int);
205 static void ia64_sched_init (FILE *, int, int);
206 static void ia64_sched_finish (FILE *, int);
207 static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
208 static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
209 static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
210 static int ia64_variable_issue (FILE *, int, rtx, int);
212 static struct bundle_state *get_free_bundle_state (void);
213 static void free_bundle_state (struct bundle_state *);
214 static void initiate_bundle_states (void);
215 static void finish_bundle_states (void);
216 static unsigned bundle_state_hash (const void *);
217 static int bundle_state_eq_p (const void *, const void *);
218 static int insert_bundle_state (struct bundle_state *);
219 static void initiate_bundle_state_table (void);
220 static void finish_bundle_state_table (void);
221 static int try_issue_nops (struct bundle_state *, int);
222 static int try_issue_insn (struct bundle_state *, rtx);
223 static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
224 static int get_max_pos (state_t);
225 static int get_template (state_t, int);
227 static rtx get_next_important_insn (rtx, rtx);
228 static void bundling (FILE *, int, rtx, rtx);
230 static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
231 HOST_WIDE_INT, tree);
232 static void ia64_file_start (void);
234 static void ia64_select_rtx_section (enum machine_mode, rtx,
235 unsigned HOST_WIDE_INT);
236 static void ia64_output_dwarf_dtprel (FILE *, int, rtx)
238 static void ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
240 static void ia64_rwreloc_unique_section (tree, int)
242 static void ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
243 unsigned HOST_WIDE_INT)
245 static unsigned int ia64_section_type_flags (tree, const char *, int);
246 static void ia64_hpux_add_extern_decl (tree decl)
248 static void ia64_hpux_file_end (void)
250 static void ia64_init_libfuncs (void)
252 static void ia64_hpux_init_libfuncs (void)
254 static void ia64_sysv4_init_libfuncs (void)
256 static void ia64_vms_init_libfuncs (void)
259 static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
260 static void ia64_encode_section_info (tree, rtx, int);
261 static rtx ia64_struct_value_rtx (tree, int);
262 static tree ia64_gimplify_va_arg (tree, tree, tree *, tree *);
263 static bool ia64_scalar_mode_supported_p (enum machine_mode mode);
264 static bool ia64_vector_mode_supported_p (enum machine_mode mode);
265 static bool ia64_cannot_force_const_mem (rtx);
266 static const char *ia64_mangle_fundamental_type (tree);
267 static const char *ia64_invalid_conversion (tree, tree);
268 static const char *ia64_invalid_unary_op (int, tree);
269 static const char *ia64_invalid_binary_op (int, tree, tree);
271 /* Table of valid machine attributes. */
272 static const struct attribute_spec ia64_attribute_table[] =
274 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
275 { "syscall_linkage", 0, 0, false, true, true, NULL },
276 { "model", 1, 1, true, false, false, ia64_handle_model_attribute },
277 { NULL, 0, 0, false, false, false, NULL }
280 /* Initialize the GCC target structure. */
281 #undef TARGET_ATTRIBUTE_TABLE
282 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
284 #undef TARGET_INIT_BUILTINS
285 #define TARGET_INIT_BUILTINS ia64_init_builtins
287 #undef TARGET_EXPAND_BUILTIN
288 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
290 #undef TARGET_ASM_BYTE_OP
291 #define TARGET_ASM_BYTE_OP "\tdata1\t"
292 #undef TARGET_ASM_ALIGNED_HI_OP
293 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
294 #undef TARGET_ASM_ALIGNED_SI_OP
295 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
296 #undef TARGET_ASM_ALIGNED_DI_OP
297 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
298 #undef TARGET_ASM_UNALIGNED_HI_OP
299 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
300 #undef TARGET_ASM_UNALIGNED_SI_OP
301 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
302 #undef TARGET_ASM_UNALIGNED_DI_OP
303 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
304 #undef TARGET_ASM_INTEGER
305 #define TARGET_ASM_INTEGER ia64_assemble_integer
307 #undef TARGET_ASM_FUNCTION_PROLOGUE
308 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
309 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
310 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
311 #undef TARGET_ASM_FUNCTION_EPILOGUE
312 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
314 #undef TARGET_IN_SMALL_DATA_P
315 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
317 #undef TARGET_SCHED_ADJUST_COST
318 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
319 #undef TARGET_SCHED_ISSUE_RATE
320 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
321 #undef TARGET_SCHED_VARIABLE_ISSUE
322 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
323 #undef TARGET_SCHED_INIT
324 #define TARGET_SCHED_INIT ia64_sched_init
325 #undef TARGET_SCHED_FINISH
326 #define TARGET_SCHED_FINISH ia64_sched_finish
327 #undef TARGET_SCHED_REORDER
328 #define TARGET_SCHED_REORDER ia64_sched_reorder
329 #undef TARGET_SCHED_REORDER2
330 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
332 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
333 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
335 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
336 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
338 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
339 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
340 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
341 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
343 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
344 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
345 ia64_first_cycle_multipass_dfa_lookahead_guard
347 #undef TARGET_SCHED_DFA_NEW_CYCLE
348 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
350 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
351 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
352 #undef TARGET_PASS_BY_REFERENCE
353 #define TARGET_PASS_BY_REFERENCE ia64_pass_by_reference
354 #undef TARGET_ARG_PARTIAL_BYTES
355 #define TARGET_ARG_PARTIAL_BYTES ia64_arg_partial_bytes
357 #undef TARGET_ASM_OUTPUT_MI_THUNK
358 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
359 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
360 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
362 #undef TARGET_ASM_FILE_START
363 #define TARGET_ASM_FILE_START ia64_file_start
365 #undef TARGET_RTX_COSTS
366 #define TARGET_RTX_COSTS ia64_rtx_costs
367 #undef TARGET_ADDRESS_COST
368 #define TARGET_ADDRESS_COST hook_int_rtx_0
370 #undef TARGET_MACHINE_DEPENDENT_REORG
371 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
373 #undef TARGET_ENCODE_SECTION_INFO
374 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
376 #undef TARGET_SECTION_TYPE_FLAGS
377 #define TARGET_SECTION_TYPE_FLAGS ia64_section_type_flags
380 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
381 #define TARGET_ASM_OUTPUT_DWARF_DTPREL ia64_output_dwarf_dtprel
384 /* ??? ABI doesn't allow us to define this. */
386 #undef TARGET_PROMOTE_FUNCTION_ARGS
387 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
390 /* ??? ABI doesn't allow us to define this. */
392 #undef TARGET_PROMOTE_FUNCTION_RETURN
393 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
396 /* ??? Investigate. */
398 #undef TARGET_PROMOTE_PROTOTYPES
399 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
402 #undef TARGET_STRUCT_VALUE_RTX
403 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
404 #undef TARGET_RETURN_IN_MEMORY
405 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
406 #undef TARGET_SETUP_INCOMING_VARARGS
407 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
408 #undef TARGET_STRICT_ARGUMENT_NAMING
409 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
410 #undef TARGET_MUST_PASS_IN_STACK
411 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
413 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
414 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
416 #undef TARGET_UNWIND_EMIT
417 #define TARGET_UNWIND_EMIT process_for_unwind_directive
419 #undef TARGET_SCALAR_MODE_SUPPORTED_P
420 #define TARGET_SCALAR_MODE_SUPPORTED_P ia64_scalar_mode_supported_p
421 #undef TARGET_VECTOR_MODE_SUPPORTED_P
422 #define TARGET_VECTOR_MODE_SUPPORTED_P ia64_vector_mode_supported_p
424 /* ia64 architecture manual 4.4.7: ... reads, writes, and flushes may occur
425 in an order different from the specified program order. */
426 #undef TARGET_RELAXED_ORDERING
427 #define TARGET_RELAXED_ORDERING true
429 #undef TARGET_DEFAULT_TARGET_FLAGS
430 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
431 #undef TARGET_HANDLE_OPTION
432 #define TARGET_HANDLE_OPTION ia64_handle_option
434 #undef TARGET_CANNOT_FORCE_CONST_MEM
435 #define TARGET_CANNOT_FORCE_CONST_MEM ia64_cannot_force_const_mem
437 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
438 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ia64_mangle_fundamental_type
440 #undef TARGET_INVALID_CONVERSION
441 #define TARGET_INVALID_CONVERSION ia64_invalid_conversion
442 #undef TARGET_INVALID_UNARY_OP
443 #define TARGET_INVALID_UNARY_OP ia64_invalid_unary_op
444 #undef TARGET_INVALID_BINARY_OP
445 #define TARGET_INVALID_BINARY_OP ia64_invalid_binary_op
447 struct gcc_target targetm = TARGET_INITIALIZER;
451 ADDR_AREA_NORMAL, /* normal address area */
452 ADDR_AREA_SMALL /* addressable by "addl" (-2MB < addr < 2MB) */
456 static GTY(()) tree small_ident1;
457 static GTY(()) tree small_ident2;
462 if (small_ident1 == 0)
464 small_ident1 = get_identifier ("small");
465 small_ident2 = get_identifier ("__small__");
469 /* Retrieve the address area that has been chosen for the given decl. */
471 static ia64_addr_area
472 ia64_get_addr_area (tree decl)
476 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
482 id = TREE_VALUE (TREE_VALUE (model_attr));
483 if (id == small_ident1 || id == small_ident2)
484 return ADDR_AREA_SMALL;
486 return ADDR_AREA_NORMAL;
490 ia64_handle_model_attribute (tree *node, tree name, tree args,
491 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
493 ia64_addr_area addr_area = ADDR_AREA_NORMAL;
495 tree arg, decl = *node;
498 arg = TREE_VALUE (args);
499 if (arg == small_ident1 || arg == small_ident2)
501 addr_area = ADDR_AREA_SMALL;
505 warning (OPT_Wattributes, "invalid argument of %qs attribute",
506 IDENTIFIER_POINTER (name));
507 *no_add_attrs = true;
510 switch (TREE_CODE (decl))
513 if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
515 && !TREE_STATIC (decl))
517 error ("%Jan address area attribute cannot be specified for "
518 "local variables", decl, decl);
519 *no_add_attrs = true;
521 area = ia64_get_addr_area (decl);
522 if (area != ADDR_AREA_NORMAL && addr_area != area)
524 error ("%Jaddress area of '%s' conflicts with previous "
525 "declaration", decl, decl);
526 *no_add_attrs = true;
531 error ("%Jaddress area attribute cannot be specified for functions",
533 *no_add_attrs = true;
537 warning (OPT_Wattributes, "%qs attribute ignored",
538 IDENTIFIER_POINTER (name));
539 *no_add_attrs = true;
547 ia64_encode_addr_area (tree decl, rtx symbol)
551 flags = SYMBOL_REF_FLAGS (symbol);
552 switch (ia64_get_addr_area (decl))
554 case ADDR_AREA_NORMAL: break;
555 case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
556 default: gcc_unreachable ();
558 SYMBOL_REF_FLAGS (symbol) = flags;
562 ia64_encode_section_info (tree decl, rtx rtl, int first)
564 default_encode_section_info (decl, rtl, first);
566 /* Careful not to prod global register variables. */
567 if (TREE_CODE (decl) == VAR_DECL
568 && GET_CODE (DECL_RTL (decl)) == MEM
569 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
570 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
571 ia64_encode_addr_area (decl, XEXP (rtl, 0));
574 /* Implement CONST_OK_FOR_LETTER_P. */
577 ia64_const_ok_for_letter_p (HOST_WIDE_INT value, char c)
582 return CONST_OK_FOR_I (value);
584 return CONST_OK_FOR_J (value);
586 return CONST_OK_FOR_K (value);
588 return CONST_OK_FOR_L (value);
590 return CONST_OK_FOR_M (value);
592 return CONST_OK_FOR_N (value);
594 return CONST_OK_FOR_O (value);
596 return CONST_OK_FOR_P (value);
602 /* Implement CONST_DOUBLE_OK_FOR_LETTER_P. */
605 ia64_const_double_ok_for_letter_p (rtx value, char c)
610 return CONST_DOUBLE_OK_FOR_G (value);
616 /* Implement EXTRA_CONSTRAINT. */
619 ia64_extra_constraint (rtx value, char c)
624 /* Non-volatile memory for FP_REG loads/stores. */
625 return memory_operand(value, VOIDmode) && !MEM_VOLATILE_P (value);
628 /* 1..4 for shladd arguments. */
629 return (GET_CODE (value) == CONST_INT
630 && INTVAL (value) >= 1 && INTVAL (value) <= 4);
633 /* Non-post-inc memory for asms and other unsavory creatures. */
634 return (GET_CODE (value) == MEM
635 && GET_RTX_CLASS (GET_CODE (XEXP (value, 0))) != RTX_AUTOINC
636 && (reload_in_progress || memory_operand (value, VOIDmode)));
639 /* Symbol ref to small-address-area. */
640 return small_addr_symbolic_operand (value, VOIDmode);
644 return value == CONST0_RTX (GET_MODE (value));
647 /* An integer vector, such that conversion to an integer yields a
648 value appropriate for an integer 'J' constraint. */
649 if (GET_CODE (value) == CONST_VECTOR
650 && GET_MODE_CLASS (GET_MODE (value)) == MODE_VECTOR_INT)
652 value = simplify_subreg (DImode, value, GET_MODE (value), 0);
653 return ia64_const_ok_for_letter_p (INTVAL (value), 'J');
658 /* A V2SF vector containing elements that satisfy 'G'. */
660 (GET_CODE (value) == CONST_VECTOR
661 && GET_MODE (value) == V2SFmode
662 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 0), 'G')
663 && ia64_const_double_ok_for_letter_p (XVECEXP (value, 0, 1), 'G'));
670 /* Return 1 if the operands of a move are ok. */
673 ia64_move_ok (rtx dst, rtx src)
675 /* If we're under init_recog_no_volatile, we'll not be able to use
676 memory_operand. So check the code directly and don't worry about
677 the validity of the underlying address, which should have been
678 checked elsewhere anyway. */
679 if (GET_CODE (dst) != MEM)
681 if (GET_CODE (src) == MEM)
683 if (register_operand (src, VOIDmode))
686 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
687 if (INTEGRAL_MODE_P (GET_MODE (dst)))
688 return src == const0_rtx;
690 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
694 addp4_optimize_ok (rtx op1, rtx op2)
696 return (basereg_operand (op1, GET_MODE(op1)) !=
697 basereg_operand (op2, GET_MODE(op2)));
700 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
701 Return the length of the field, or <= 0 on failure. */
704 ia64_depz_field_mask (rtx rop, rtx rshift)
706 unsigned HOST_WIDE_INT op = INTVAL (rop);
707 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
709 /* Get rid of the zero bits we're shifting in. */
712 /* We must now have a solid block of 1's at bit 0. */
713 return exact_log2 (op + 1);
716 /* Return the TLS model to use for ADDR. */
718 static enum tls_model
719 tls_symbolic_operand_type (rtx addr)
721 enum tls_model tls_kind = 0;
723 if (GET_CODE (addr) == CONST)
725 if (GET_CODE (XEXP (addr, 0)) == PLUS
726 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
727 tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
729 else if (GET_CODE (addr) == SYMBOL_REF)
730 tls_kind = SYMBOL_REF_TLS_MODEL (addr);
735 /* Return true if X is a constant that is valid for some immediate
736 field in an instruction. */
739 ia64_legitimate_constant_p (rtx x)
741 switch (GET_CODE (x))
748 if (GET_MODE (x) == VOIDmode)
750 return CONST_DOUBLE_OK_FOR_G (x);
754 return tls_symbolic_operand_type (x) == 0;
758 enum machine_mode mode = GET_MODE (x);
760 if (mode == V2SFmode)
761 return ia64_extra_constraint (x, 'Y');
763 return (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
764 && GET_MODE_SIZE (mode) <= 8);
772 /* Don't allow TLS addresses to get spilled to memory. */
775 ia64_cannot_force_const_mem (rtx x)
777 return tls_symbolic_operand_type (x) != 0;
780 /* Expand a symbolic constant load. */
783 ia64_expand_load_address (rtx dest, rtx src)
785 gcc_assert (GET_CODE (dest) == REG);
787 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
788 having to pointer-extend the value afterward. Other forms of address
789 computation below are also more natural to compute as 64-bit quantities.
790 If we've been given an SImode destination register, change it. */
791 if (GET_MODE (dest) != Pmode)
792 dest = gen_rtx_REG_offset (dest, Pmode, REGNO (dest), 0);
796 if (small_addr_symbolic_operand (src, VOIDmode))
800 emit_insn (gen_load_gprel64 (dest, src));
801 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
802 emit_insn (gen_load_fptr (dest, src));
803 else if (sdata_symbolic_operand (src, VOIDmode))
804 emit_insn (gen_load_gprel (dest, src));
807 HOST_WIDE_INT addend = 0;
810 /* We did split constant offsets in ia64_expand_move, and we did try
811 to keep them split in move_operand, but we also allowed reload to
812 rematerialize arbitrary constants rather than spill the value to
813 the stack and reload it. So we have to be prepared here to split
815 if (GET_CODE (src) == CONST)
817 HOST_WIDE_INT hi, lo;
819 hi = INTVAL (XEXP (XEXP (src, 0), 1));
820 lo = ((hi & 0x3fff) ^ 0x2000) - 0x2000;
826 src = plus_constant (XEXP (XEXP (src, 0), 0), hi);
830 tmp = gen_rtx_HIGH (Pmode, src);
831 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
832 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
834 tmp = gen_rtx_LO_SUM (Pmode, dest, src);
835 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
839 tmp = gen_rtx_PLUS (Pmode, dest, GEN_INT (addend));
840 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
847 static GTY(()) rtx gen_tls_tga;
849 gen_tls_get_addr (void)
852 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
856 static GTY(()) rtx thread_pointer_rtx;
858 gen_thread_pointer (void)
860 if (!thread_pointer_rtx)
861 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
862 return thread_pointer_rtx;
866 ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1,
867 HOST_WIDE_INT addend)
869 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
870 rtx orig_op0 = op0, orig_op1 = op1;
871 HOST_WIDE_INT addend_lo, addend_hi;
873 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
874 addend_hi = addend - addend_lo;
878 case TLS_MODEL_GLOBAL_DYNAMIC:
881 tga_op1 = gen_reg_rtx (Pmode);
882 emit_insn (gen_load_dtpmod (tga_op1, op1));
884 tga_op2 = gen_reg_rtx (Pmode);
885 emit_insn (gen_load_dtprel (tga_op2, op1));
887 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
888 LCT_CONST, Pmode, 2, tga_op1,
889 Pmode, tga_op2, Pmode);
891 insns = get_insns ();
894 if (GET_MODE (op0) != Pmode)
896 emit_libcall_block (insns, op0, tga_ret, op1);
899 case TLS_MODEL_LOCAL_DYNAMIC:
900 /* ??? This isn't the completely proper way to do local-dynamic
901 If the call to __tls_get_addr is used only by a single symbol,
902 then we should (somehow) move the dtprel to the second arg
903 to avoid the extra add. */
906 tga_op1 = gen_reg_rtx (Pmode);
907 emit_insn (gen_load_dtpmod (tga_op1, op1));
909 tga_op2 = const0_rtx;
911 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
912 LCT_CONST, Pmode, 2, tga_op1,
913 Pmode, tga_op2, Pmode);
915 insns = get_insns ();
918 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
920 tmp = gen_reg_rtx (Pmode);
921 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
923 if (!register_operand (op0, Pmode))
924 op0 = gen_reg_rtx (Pmode);
927 emit_insn (gen_load_dtprel (op0, op1));
928 emit_insn (gen_adddi3 (op0, tmp, op0));
931 emit_insn (gen_add_dtprel (op0, op1, tmp));
934 case TLS_MODEL_INITIAL_EXEC:
935 op1 = plus_constant (op1, addend_hi);
938 tmp = gen_reg_rtx (Pmode);
939 emit_insn (gen_load_tprel (tmp, op1));
941 if (!register_operand (op0, Pmode))
942 op0 = gen_reg_rtx (Pmode);
943 emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
946 case TLS_MODEL_LOCAL_EXEC:
947 if (!register_operand (op0, Pmode))
948 op0 = gen_reg_rtx (Pmode);
954 emit_insn (gen_load_tprel (op0, op1));
955 emit_insn (gen_adddi3 (op0, op0, gen_thread_pointer ()));
958 emit_insn (gen_add_tprel (op0, op1, gen_thread_pointer ()));
966 op0 = expand_simple_binop (Pmode, PLUS, op0, GEN_INT (addend),
967 orig_op0, 1, OPTAB_DIRECT);
970 if (GET_MODE (orig_op0) == Pmode)
972 return gen_lowpart (GET_MODE (orig_op0), op0);
976 ia64_expand_move (rtx op0, rtx op1)
978 enum machine_mode mode = GET_MODE (op0);
980 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
981 op1 = force_reg (mode, op1);
983 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
985 HOST_WIDE_INT addend = 0;
986 enum tls_model tls_kind;
989 if (GET_CODE (op1) == CONST
990 && GET_CODE (XEXP (op1, 0)) == PLUS
991 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
993 addend = INTVAL (XEXP (XEXP (op1, 0), 1));
994 sym = XEXP (XEXP (op1, 0), 0);
997 tls_kind = tls_symbolic_operand_type (sym);
999 return ia64_expand_tls_address (tls_kind, op0, sym, addend);
1001 if (any_offset_symbol_operand (sym, mode))
1003 else if (aligned_offset_symbol_operand (sym, mode))
1005 HOST_WIDE_INT addend_lo, addend_hi;
1007 addend_lo = ((addend & 0x3fff) ^ 0x2000) - 0x2000;
1008 addend_hi = addend - addend_lo;
1012 op1 = plus_constant (sym, addend_hi);
1021 if (reload_completed)
1023 /* We really should have taken care of this offset earlier. */
1024 gcc_assert (addend == 0);
1025 if (ia64_expand_load_address (op0, op1))
1031 rtx subtarget = no_new_pseudos ? op0 : gen_reg_rtx (mode);
1033 emit_insn (gen_rtx_SET (VOIDmode, subtarget, op1));
1035 op1 = expand_simple_binop (mode, PLUS, subtarget,
1036 GEN_INT (addend), op0, 1, OPTAB_DIRECT);
1045 /* Split a move from OP1 to OP0 conditional on COND. */
1048 ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
1050 rtx insn, first = get_last_insn ();
1052 emit_move_insn (op0, op1);
1054 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1056 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1060 /* Split a post-reload TImode or TFmode reference into two DImode
1061 components. This is made extra difficult by the fact that we do
1062 not get any scratch registers to work with, because reload cannot
1063 be prevented from giving us a scratch that overlaps the register
1064 pair involved. So instead, when addressing memory, we tweak the
1065 pointer register up and back down with POST_INCs. Or up and not
1066 back down when we can get away with it.
1068 REVERSED is true when the loads must be done in reversed order
1069 (high word first) for correctness. DEAD is true when the pointer
1070 dies with the second insn we generate and therefore the second
1071 address must not carry a postmodify.
1073 May return an insn which is to be emitted after the moves. */
1076 ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
1080 switch (GET_CODE (in))
1083 out[reversed] = gen_rtx_REG (DImode, REGNO (in));
1084 out[!reversed] = gen_rtx_REG (DImode, REGNO (in) + 1);
1089 /* Cannot occur reversed. */
1090 gcc_assert (!reversed);
1092 if (GET_MODE (in) != TFmode)
1093 split_double (in, &out[0], &out[1]);
1095 /* split_double does not understand how to split a TFmode
1096 quantity into a pair of DImode constants. */
1099 unsigned HOST_WIDE_INT p[2];
1100 long l[4]; /* TFmode is 128 bits */
1102 REAL_VALUE_FROM_CONST_DOUBLE (r, in);
1103 real_to_target (l, &r, TFmode);
1105 if (FLOAT_WORDS_BIG_ENDIAN)
1107 p[0] = (((unsigned HOST_WIDE_INT) l[0]) << 32) + l[1];
1108 p[1] = (((unsigned HOST_WIDE_INT) l[2]) << 32) + l[3];
1112 p[0] = (((unsigned HOST_WIDE_INT) l[3]) << 32) + l[2];
1113 p[1] = (((unsigned HOST_WIDE_INT) l[1]) << 32) + l[0];
1115 out[0] = GEN_INT (p[0]);
1116 out[1] = GEN_INT (p[1]);
1122 rtx base = XEXP (in, 0);
1125 switch (GET_CODE (base))
1130 out[0] = adjust_automodify_address
1131 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1132 out[1] = adjust_automodify_address
1133 (in, DImode, dead ? 0 : gen_rtx_POST_DEC (Pmode, base), 8);
1137 /* Reversal requires a pre-increment, which can only
1138 be done as a separate insn. */
1139 emit_insn (gen_adddi3 (base, base, GEN_INT (8)));
1140 out[0] = adjust_automodify_address
1141 (in, DImode, gen_rtx_POST_DEC (Pmode, base), 8);
1142 out[1] = adjust_address (in, DImode, 0);
1147 gcc_assert (!reversed && !dead);
1149 /* Just do the increment in two steps. */
1150 out[0] = adjust_automodify_address (in, DImode, 0, 0);
1151 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1155 gcc_assert (!reversed && !dead);
1157 /* Add 8, subtract 24. */
1158 base = XEXP (base, 0);
1159 out[0] = adjust_automodify_address
1160 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1161 out[1] = adjust_automodify_address
1163 gen_rtx_POST_MODIFY (Pmode, base, plus_constant (base, -24)),
1168 gcc_assert (!reversed && !dead);
1170 /* Extract and adjust the modification. This case is
1171 trickier than the others, because we might have an
1172 index register, or we might have a combined offset that
1173 doesn't fit a signed 9-bit displacement field. We can
1174 assume the incoming expression is already legitimate. */
1175 offset = XEXP (base, 1);
1176 base = XEXP (base, 0);
1178 out[0] = adjust_automodify_address
1179 (in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
1181 if (GET_CODE (XEXP (offset, 1)) == REG)
1183 /* Can't adjust the postmodify to match. Emit the
1184 original, then a separate addition insn. */
1185 out[1] = adjust_automodify_address (in, DImode, 0, 8);
1186 fixup = gen_adddi3 (base, base, GEN_INT (-8));
1190 gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
1191 if (INTVAL (XEXP (offset, 1)) < -256 + 8)
1193 /* Again the postmodify cannot be made to match,
1194 but in this case it's more efficient to get rid
1195 of the postmodify entirely and fix up with an
1197 out[1] = adjust_automodify_address (in, DImode, base, 8);
1199 (base, base, GEN_INT (INTVAL (XEXP (offset, 1)) - 8));
1203 /* Combined offset still fits in the displacement field.
1204 (We cannot overflow it at the high end.) */
1205 out[1] = adjust_automodify_address
1206 (in, DImode, gen_rtx_POST_MODIFY
1207 (Pmode, base, gen_rtx_PLUS
1209 GEN_INT (INTVAL (XEXP (offset, 1)) - 8))),
1228 /* Split a TImode or TFmode move instruction after reload.
1229 This is used by *movtf_internal and *movti_internal. */
1231 ia64_split_tmode_move (rtx operands[])
1233 rtx in[2], out[2], insn;
1236 bool reversed = false;
1238 /* It is possible for reload to decide to overwrite a pointer with
1239 the value it points to. In that case we have to do the loads in
1240 the appropriate order so that the pointer is not destroyed too
1241 early. Also we must not generate a postmodify for that second
1242 load, or rws_access_regno will die. */
1243 if (GET_CODE (operands[1]) == MEM
1244 && reg_overlap_mentioned_p (operands[0], operands[1]))
1246 rtx base = XEXP (operands[1], 0);
1247 while (GET_CODE (base) != REG)
1248 base = XEXP (base, 0);
1250 if (REGNO (base) == REGNO (operands[0]))
1254 /* Another reason to do the moves in reversed order is if the first
1255 element of the target register pair is also the second element of
1256 the source register pair. */
1257 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
1258 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1261 fixup[0] = ia64_split_tmode (in, operands[1], reversed, dead);
1262 fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
1264 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1265 if (GET_CODE (EXP) == MEM \
1266 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1267 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1268 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1269 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1270 XEXP (XEXP (EXP, 0), 0), \
1273 insn = emit_insn (gen_rtx_SET (VOIDmode, out[0], in[0]));
1274 MAYBE_ADD_REG_INC_NOTE (insn, in[0]);
1275 MAYBE_ADD_REG_INC_NOTE (insn, out[0]);
1277 insn = emit_insn (gen_rtx_SET (VOIDmode, out[1], in[1]));
1278 MAYBE_ADD_REG_INC_NOTE (insn, in[1]);
1279 MAYBE_ADD_REG_INC_NOTE (insn, out[1]);
1282 emit_insn (fixup[0]);
1284 emit_insn (fixup[1]);
1286 #undef MAYBE_ADD_REG_INC_NOTE
1289 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1290 through memory plus an extra GR scratch register. Except that you can
1291 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1292 SECONDARY_RELOAD_CLASS, but not both.
1294 We got into problems in the first place by allowing a construct like
1295 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1296 This solution attempts to prevent this situation from occurring. When
1297 we see something like the above, we spill the inner register to memory. */
1300 spill_xfmode_rfmode_operand (rtx in, int force, enum machine_mode mode)
1302 if (GET_CODE (in) == SUBREG
1303 && GET_MODE (SUBREG_REG (in)) == TImode
1304 && GET_CODE (SUBREG_REG (in)) == REG)
1306 rtx memt = assign_stack_temp (TImode, 16, 0);
1307 emit_move_insn (memt, SUBREG_REG (in));
1308 return adjust_address (memt, mode, 0);
1310 else if (force && GET_CODE (in) == REG)
1312 rtx memx = assign_stack_temp (mode, 16, 0);
1313 emit_move_insn (memx, in);
1320 /* Expand the movxf or movrf pattern (MODE says which) with the given
1321 OPERANDS, returning true if the pattern should then invoke
1325 ia64_expand_movxf_movrf (enum machine_mode mode, rtx operands[])
1327 rtx op0 = operands[0];
1329 if (GET_CODE (op0) == SUBREG)
1330 op0 = SUBREG_REG (op0);
1332 /* We must support XFmode loads into general registers for stdarg/vararg,
1333 unprototyped calls, and a rare case where a long double is passed as
1334 an argument after a float HFA fills the FP registers. We split them into
1335 DImode loads for convenience. We also need to support XFmode stores
1336 for the last case. This case does not happen for stdarg/vararg routines,
1337 because we do a block store to memory of unnamed arguments. */
1339 if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
1343 /* We're hoping to transform everything that deals with XFmode
1344 quantities and GR registers early in the compiler. */
1345 gcc_assert (!no_new_pseudos);
1347 /* Struct to register can just use TImode instead. */
1348 if ((GET_CODE (operands[1]) == SUBREG
1349 && GET_MODE (SUBREG_REG (operands[1])) == TImode)
1350 || (GET_CODE (operands[1]) == REG
1351 && GR_REGNO_P (REGNO (operands[1]))))
1353 rtx op1 = operands[1];
1355 if (GET_CODE (op1) == SUBREG)
1356 op1 = SUBREG_REG (op1);
1358 op1 = gen_rtx_REG (TImode, REGNO (op1));
1360 emit_move_insn (gen_rtx_REG (TImode, REGNO (op0)), op1);
1364 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1366 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
1367 operand_subword (operands[1], 0, 0, mode));
1368 emit_move_insn (gen_rtx_REG (DImode, REGNO (op0) + 1),
1369 operand_subword (operands[1], 1, 0, mode));
1373 /* If the quantity is in a register not known to be GR, spill it. */
1374 if (register_operand (operands[1], mode))
1375 operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
1377 gcc_assert (GET_CODE (operands[1]) == MEM);
1379 out[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0));
1380 out[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (op0) + 1);
1382 emit_move_insn (out[0], adjust_address (operands[1], DImode, 0));
1383 emit_move_insn (out[1], adjust_address (operands[1], DImode, 8));
1387 if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
1389 /* We're hoping to transform everything that deals with XFmode
1390 quantities and GR registers early in the compiler. */
1391 gcc_assert (!no_new_pseudos);
1393 /* Op0 can't be a GR_REG here, as that case is handled above.
1394 If op0 is a register, then we spill op1, so that we now have a
1395 MEM operand. This requires creating an XFmode subreg of a TImode reg
1396 to force the spill. */
1397 if (register_operand (operands[0], mode))
1399 rtx op1 = gen_rtx_REG (TImode, REGNO (operands[1]));
1400 op1 = gen_rtx_SUBREG (mode, op1, 0);
1401 operands[1] = spill_xfmode_rfmode_operand (op1, 0, mode);
1408 gcc_assert (GET_CODE (operands[0]) == MEM);
1409 in[WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]));
1410 in[!WORDS_BIG_ENDIAN] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
1412 emit_move_insn (adjust_address (operands[0], DImode, 0), in[0]);
1413 emit_move_insn (adjust_address (operands[0], DImode, 8), in[1]);
1418 if (!reload_in_progress && !reload_completed)
1420 operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
1422 if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
1424 rtx memt, memx, in = operands[1];
1425 if (CONSTANT_P (in))
1426 in = validize_mem (force_const_mem (mode, in));
1427 if (GET_CODE (in) == MEM)
1428 memt = adjust_address (in, TImode, 0);
1431 memt = assign_stack_temp (TImode, 16, 0);
1432 memx = adjust_address (memt, mode, 0);
1433 emit_move_insn (memx, in);
1435 emit_move_insn (op0, memt);
1439 if (!ia64_move_ok (operands[0], operands[1]))
1440 operands[1] = force_reg (mode, operands[1]);
1446 /* Emit comparison instruction if necessary, returning the expression
1447 that holds the compare result in the proper mode. */
1449 static GTY(()) rtx cmptf_libfunc;
1452 ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
1454 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1457 /* If we have a BImode input, then we already have a compare result, and
1458 do not need to emit another comparison. */
1459 if (GET_MODE (op0) == BImode)
1461 gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
1464 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1465 magic number as its third argument, that indicates what to do.
1466 The return value is an integer to be compared against zero. */
1467 else if (GET_MODE (op0) == TFmode)
1470 QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
1476 enum rtx_code ncode;
1479 gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
1482 /* 1 = equal, 0 = not equal. Equality operators do
1483 not raise FP_INVALID when given an SNaN operand. */
1484 case EQ: magic = QCMP_EQ; ncode = NE; break;
1485 case NE: magic = QCMP_EQ; ncode = EQ; break;
1486 /* isunordered() from C99. */
1487 case UNORDERED: magic = QCMP_UNORD; ncode = NE; break;
1488 case ORDERED: magic = QCMP_UNORD; ncode = EQ; break;
1489 /* Relational operators raise FP_INVALID when given
1491 case LT: magic = QCMP_LT |QCMP_INV; ncode = NE; break;
1492 case LE: magic = QCMP_LT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1493 case GT: magic = QCMP_GT |QCMP_INV; ncode = NE; break;
1494 case GE: magic = QCMP_GT|QCMP_EQ|QCMP_INV; ncode = NE; break;
1495 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1496 Expanders for buneq etc. weuld have to be added to ia64.md
1497 for this to be useful. */
1498 default: gcc_unreachable ();
1503 ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
1504 op0, TFmode, op1, TFmode,
1505 GEN_INT (magic), DImode);
1506 cmp = gen_reg_rtx (BImode);
1507 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1508 gen_rtx_fmt_ee (ncode, BImode,
1511 insns = get_insns ();
1514 emit_libcall_block (insns, cmp, cmp,
1515 gen_rtx_fmt_ee (code, BImode, op0, op1));
1520 cmp = gen_reg_rtx (BImode);
1521 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1522 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1526 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1529 /* Generate an integral vector comparison. Return true if the condition has
1530 been reversed, and so the sense of the comparison should be inverted. */
1533 ia64_expand_vecint_compare (enum rtx_code code, enum machine_mode mode,
1534 rtx dest, rtx op0, rtx op1)
1536 bool negate = false;
1539 /* Canonicalize the comparison to EQ, GT, GTU. */
1550 code = reverse_condition (code);
1556 code = reverse_condition (code);
1562 code = swap_condition (code);
1563 x = op0, op0 = op1, op1 = x;
1570 /* Unsigned parallel compare is not supported by the hardware. Play some
1571 tricks to turn this into a signed comparison against 0. */
1580 /* Perform a parallel modulo subtraction. */
1581 t1 = gen_reg_rtx (V2SImode);
1582 emit_insn (gen_subv2si3 (t1, op0, op1));
1584 /* Extract the original sign bit of op0. */
1585 mask = GEN_INT (-0x80000000);
1586 mask = gen_rtx_CONST_VECTOR (V2SImode, gen_rtvec (2, mask, mask));
1587 mask = force_reg (V2SImode, mask);
1588 t2 = gen_reg_rtx (V2SImode);
1589 emit_insn (gen_andv2si3 (t2, op0, mask));
1591 /* XOR it back into the result of the subtraction. This results
1592 in the sign bit set iff we saw unsigned underflow. */
1593 x = gen_reg_rtx (V2SImode);
1594 emit_insn (gen_xorv2si3 (x, t1, t2));
1598 op1 = CONST0_RTX (mode);
1604 /* Perform a parallel unsigned saturating subtraction. */
1605 x = gen_reg_rtx (mode);
1606 emit_insn (gen_rtx_SET (VOIDmode, x,
1607 gen_rtx_US_MINUS (mode, op0, op1)));
1611 op1 = CONST0_RTX (mode);
1620 x = gen_rtx_fmt_ee (code, mode, op0, op1);
1621 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1626 /* Emit an integral vector conditional move. */
1629 ia64_expand_vecint_cmov (rtx operands[])
1631 enum machine_mode mode = GET_MODE (operands[0]);
1632 enum rtx_code code = GET_CODE (operands[3]);
1636 cmp = gen_reg_rtx (mode);
1637 negate = ia64_expand_vecint_compare (code, mode, cmp,
1638 operands[4], operands[5]);
1640 ot = operands[1+negate];
1641 of = operands[2-negate];
1643 if (ot == CONST0_RTX (mode))
1645 if (of == CONST0_RTX (mode))
1647 emit_move_insn (operands[0], ot);
1651 x = gen_rtx_NOT (mode, cmp);
1652 x = gen_rtx_AND (mode, x, of);
1653 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1655 else if (of == CONST0_RTX (mode))
1657 x = gen_rtx_AND (mode, cmp, ot);
1658 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1664 t = gen_reg_rtx (mode);
1665 x = gen_rtx_AND (mode, cmp, operands[1+negate]);
1666 emit_insn (gen_rtx_SET (VOIDmode, t, x));
1668 f = gen_reg_rtx (mode);
1669 x = gen_rtx_NOT (mode, cmp);
1670 x = gen_rtx_AND (mode, x, operands[2-negate]);
1671 emit_insn (gen_rtx_SET (VOIDmode, f, x));
1673 x = gen_rtx_IOR (mode, t, f);
1674 emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
1678 /* Emit an integral vector min or max operation. Return true if all done. */
1681 ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
1686 /* These four combinations are supported directly. */
1687 if (mode == V8QImode && (code == UMIN || code == UMAX))
1689 if (mode == V4HImode && (code == SMIN || code == SMAX))
1692 /* Everything else implemented via vector comparisons. */
1693 xops[0] = operands[0];
1694 xops[4] = xops[1] = operands[1];
1695 xops[5] = xops[2] = operands[2];
1714 xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
1716 ia64_expand_vecint_cmov (xops);
1720 /* Emit the appropriate sequence for a call. */
1723 ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
1728 addr = XEXP (addr, 0);
1729 addr = convert_memory_address (DImode, addr);
1730 b0 = gen_rtx_REG (DImode, R_BR (0));
1732 /* ??? Should do this for functions known to bind local too. */
1733 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1736 insn = gen_sibcall_nogp (addr);
1738 insn = gen_call_nogp (addr, b0);
1740 insn = gen_call_value_nogp (retval, addr, b0);
1741 insn = emit_call_insn (insn);
1746 insn = gen_sibcall_gp (addr);
1748 insn = gen_call_gp (addr, b0);
1750 insn = gen_call_value_gp (retval, addr, b0);
1751 insn = emit_call_insn (insn);
1753 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1757 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1761 ia64_reload_gp (void)
1765 if (current_frame_info.reg_save_gp)
1766 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1769 HOST_WIDE_INT offset;
1771 offset = (current_frame_info.spill_cfa_off
1772 + current_frame_info.spill_size);
1773 if (frame_pointer_needed)
1775 tmp = hard_frame_pointer_rtx;
1780 tmp = stack_pointer_rtx;
1781 offset = current_frame_info.total_size - offset;
1784 if (CONST_OK_FOR_I (offset))
1785 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1786 tmp, GEN_INT (offset)));
1789 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1790 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1791 pic_offset_table_rtx, tmp));
1794 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1797 emit_move_insn (pic_offset_table_rtx, tmp);
1801 ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
1802 rtx scratch_b, int noreturn_p, int sibcall_p)
1805 bool is_desc = false;
1807 /* If we find we're calling through a register, then we're actually
1808 calling through a descriptor, so load up the values. */
1809 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
1814 /* ??? We are currently constrained to *not* use peep2, because
1815 we can legitimately change the global lifetime of the GP
1816 (in the form of killing where previously live). This is
1817 because a call through a descriptor doesn't use the previous
1818 value of the GP, while a direct call does, and we do not
1819 commit to either form until the split here.
1821 That said, this means that we lack precise life info for
1822 whether ADDR is dead after this call. This is not terribly
1823 important, since we can fix things up essentially for free
1824 with the POST_DEC below, but it's nice to not use it when we
1825 can immediately tell it's not necessary. */
1826 addr_dead_p = ((noreturn_p || sibcall_p
1827 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1829 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1831 /* Load the code address into scratch_b. */
1832 tmp = gen_rtx_POST_INC (Pmode, addr);
1833 tmp = gen_rtx_MEM (Pmode, tmp);
1834 emit_move_insn (scratch_r, tmp);
1835 emit_move_insn (scratch_b, scratch_r);
1837 /* Load the GP address. If ADDR is not dead here, then we must
1838 revert the change made above via the POST_INCREMENT. */
1840 tmp = gen_rtx_POST_DEC (Pmode, addr);
1843 tmp = gen_rtx_MEM (Pmode, tmp);
1844 emit_move_insn (pic_offset_table_rtx, tmp);
1851 insn = gen_sibcall_nogp (addr);
1853 insn = gen_call_value_nogp (retval, addr, retaddr);
1855 insn = gen_call_nogp (addr, retaddr);
1856 emit_call_insn (insn);
1858 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1862 /* Expand an atomic operation. We want to perform MEM <CODE>= VAL atomically.
1864 This differs from the generic code in that we know about the zero-extending
1865 properties of cmpxchg, and the zero-extending requirements of ar.ccv. We
1866 also know that ld.acq+cmpxchg.rel equals a full barrier.
1868 The loop we want to generate looks like
1873 new_reg = cmp_reg op val;
1874 cmp_reg = compare-and-swap(mem, old_reg, new_reg)
1875 if (cmp_reg != old_reg)
1878 Note that we only do the plain load from memory once. Subsequent
1879 iterations use the value loaded by the compare-and-swap pattern. */
1882 ia64_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
1883 rtx old_dst, rtx new_dst)
1885 enum machine_mode mode = GET_MODE (mem);
1886 rtx old_reg, new_reg, cmp_reg, ar_ccv, label;
1887 enum insn_code icode;
1889 /* Special case for using fetchadd. */
1890 if ((mode == SImode || mode == DImode) && fetchadd_operand (val, mode))
1893 old_dst = gen_reg_rtx (mode);
1895 emit_insn (gen_memory_barrier ());
1898 icode = CODE_FOR_fetchadd_acq_si;
1900 icode = CODE_FOR_fetchadd_acq_di;
1901 emit_insn (GEN_FCN (icode) (old_dst, mem, val));
1905 new_reg = expand_simple_binop (mode, PLUS, old_dst, val, new_dst,
1907 if (new_reg != new_dst)
1908 emit_move_insn (new_dst, new_reg);
1913 /* Because of the volatile mem read, we get an ld.acq, which is the
1914 front half of the full barrier. The end half is the cmpxchg.rel. */
1915 gcc_assert (MEM_VOLATILE_P (mem));
1917 old_reg = gen_reg_rtx (DImode);
1918 cmp_reg = gen_reg_rtx (DImode);
1919 label = gen_label_rtx ();
1923 val = simplify_gen_subreg (DImode, val, mode, 0);
1924 emit_insn (gen_extend_insn (cmp_reg, mem, DImode, mode, 1));
1927 emit_move_insn (cmp_reg, mem);
1931 ar_ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
1932 emit_move_insn (old_reg, cmp_reg);
1933 emit_move_insn (ar_ccv, cmp_reg);
1936 emit_move_insn (old_dst, gen_lowpart (mode, cmp_reg));
1941 new_reg = expand_simple_unop (DImode, NOT, new_reg, NULL_RTX, true);
1944 new_reg = expand_simple_binop (DImode, code, new_reg, val, NULL_RTX,
1945 true, OPTAB_DIRECT);
1948 new_reg = gen_lowpart (mode, new_reg);
1950 emit_move_insn (new_dst, new_reg);
1954 case QImode: icode = CODE_FOR_cmpxchg_rel_qi; break;
1955 case HImode: icode = CODE_FOR_cmpxchg_rel_hi; break;
1956 case SImode: icode = CODE_FOR_cmpxchg_rel_si; break;
1957 case DImode: icode = CODE_FOR_cmpxchg_rel_di; break;
1962 emit_insn (GEN_FCN (icode) (cmp_reg, mem, ar_ccv, new_reg));
1964 emit_cmp_and_jump_insns (cmp_reg, old_reg, EQ, NULL, DImode, true, label);
1967 /* Begin the assembly file. */
1970 ia64_file_start (void)
1972 /* Variable tracking should be run after all optimizations which change order
1973 of insns. It also needs a valid CFG. This can't be done in
1974 ia64_override_options, because flag_var_tracking is finalized after
1976 ia64_flag_var_tracking = flag_var_tracking;
1977 flag_var_tracking = 0;
1979 default_file_start ();
1980 emit_safe_across_calls ();
1984 emit_safe_across_calls (void)
1986 unsigned int rs, re;
1993 while (rs < 64 && call_used_regs[PR_REG (rs)])
1997 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
2001 fputs ("\t.pred.safe_across_calls ", asm_out_file);
2005 fputc (',', asm_out_file);
2007 fprintf (asm_out_file, "p%u", rs);
2009 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
2013 fputc ('\n', asm_out_file);
2016 /* Helper function for ia64_compute_frame_size: find an appropriate general
2017 register to spill some special register to. SPECIAL_SPILL_MASK contains
2018 bits in GR0 to GR31 that have already been allocated by this routine.
2019 TRY_LOCALS is true if we should attempt to locate a local regnum. */
2022 find_gr_spill (int try_locals)
2026 /* If this is a leaf function, first try an otherwise unused
2027 call-clobbered register. */
2028 if (current_function_is_leaf)
2030 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2031 if (! regs_ever_live[regno]
2032 && call_used_regs[regno]
2033 && ! fixed_regs[regno]
2034 && ! global_regs[regno]
2035 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2037 current_frame_info.gr_used_mask |= 1 << regno;
2044 regno = current_frame_info.n_local_regs;
2045 /* If there is a frame pointer, then we can't use loc79, because
2046 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
2047 reg_name switching code in ia64_expand_prologue. */
2048 if (regno < (80 - frame_pointer_needed))
2050 current_frame_info.n_local_regs = regno + 1;
2051 return LOC_REG (0) + regno;
2055 /* Failed to find a general register to spill to. Must use stack. */
2059 /* In order to make for nice schedules, we try to allocate every temporary
2060 to a different register. We must of course stay away from call-saved,
2061 fixed, and global registers. We must also stay away from registers
2062 allocated in current_frame_info.gr_used_mask, since those include regs
2063 used all through the prologue.
2065 Any register allocated here must be used immediately. The idea is to
2066 aid scheduling, not to solve data flow problems. */
2068 static int last_scratch_gr_reg;
2071 next_scratch_gr_reg (void)
2075 for (i = 0; i < 32; ++i)
2077 regno = (last_scratch_gr_reg + i + 1) & 31;
2078 if (call_used_regs[regno]
2079 && ! fixed_regs[regno]
2080 && ! global_regs[regno]
2081 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
2083 last_scratch_gr_reg = regno;
2088 /* There must be _something_ available. */
2092 /* Helper function for ia64_compute_frame_size, called through
2093 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2096 mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
2098 unsigned int regno = REGNO (reg);
2101 unsigned int i, n = hard_regno_nregs[regno][GET_MODE (reg)];
2102 for (i = 0; i < n; ++i)
2103 current_frame_info.gr_used_mask |= 1 << (regno + i);
2107 /* Returns the number of bytes offset between the frame pointer and the stack
2108 pointer for the current function. SIZE is the number of bytes of space
2109 needed for local variables. */
2112 ia64_compute_frame_size (HOST_WIDE_INT size)
2114 HOST_WIDE_INT total_size;
2115 HOST_WIDE_INT spill_size = 0;
2116 HOST_WIDE_INT extra_spill_size = 0;
2117 HOST_WIDE_INT pretend_args_size;
2120 int spilled_gr_p = 0;
2121 int spilled_fr_p = 0;
2125 if (current_frame_info.initialized)
2128 memset (¤t_frame_info, 0, sizeof current_frame_info);
2129 CLEAR_HARD_REG_SET (mask);
2131 /* Don't allocate scratches to the return register. */
2132 diddle_return_value (mark_reg_gr_used_mask, NULL);
2134 /* Don't allocate scratches to the EH scratch registers. */
2135 if (cfun->machine->ia64_eh_epilogue_sp)
2136 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
2137 if (cfun->machine->ia64_eh_epilogue_bsp)
2138 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
2140 /* Find the size of the register stack frame. We have only 80 local
2141 registers, because we reserve 8 for the inputs and 8 for the
2144 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2145 since we'll be adjusting that down later. */
2146 regno = LOC_REG (78) + ! frame_pointer_needed;
2147 for (; regno >= LOC_REG (0); regno--)
2148 if (regs_ever_live[regno])
2150 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
2152 /* For functions marked with the syscall_linkage attribute, we must mark
2153 all eight input registers as in use, so that locals aren't visible to
2156 if (cfun->machine->n_varargs > 0
2157 || lookup_attribute ("syscall_linkage",
2158 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
2159 current_frame_info.n_input_regs = 8;
2162 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
2163 if (regs_ever_live[regno])
2165 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
2168 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
2169 if (regs_ever_live[regno])
2171 i = regno - OUT_REG (0) + 1;
2173 #ifndef PROFILE_HOOK
2174 /* When -p profiling, we need one output register for the mcount argument.
2175 Likewise for -a profiling for the bb_init_func argument. For -ax
2176 profiling, we need two output registers for the two bb_init_trace_func
2178 if (current_function_profile)
2181 current_frame_info.n_output_regs = i;
2183 /* ??? No rotating register support yet. */
2184 current_frame_info.n_rotate_regs = 0;
2186 /* Discover which registers need spilling, and how much room that
2187 will take. Begin with floating point and general registers,
2188 which will always wind up on the stack. */
2190 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
2191 if (regs_ever_live[regno] && ! call_used_regs[regno])
2193 SET_HARD_REG_BIT (mask, regno);
2199 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
2200 if (regs_ever_live[regno] && ! call_used_regs[regno])
2202 SET_HARD_REG_BIT (mask, regno);
2208 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
2209 if (regs_ever_live[regno] && ! call_used_regs[regno])
2211 SET_HARD_REG_BIT (mask, regno);
2216 /* Now come all special registers that might get saved in other
2217 general registers. */
2219 if (frame_pointer_needed)
2221 current_frame_info.reg_fp = find_gr_spill (1);
2222 /* If we did not get a register, then we take LOC79. This is guaranteed
2223 to be free, even if regs_ever_live is already set, because this is
2224 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2225 as we don't count loc79 above. */
2226 if (current_frame_info.reg_fp == 0)
2228 current_frame_info.reg_fp = LOC_REG (79);
2229 current_frame_info.n_local_regs++;
2233 if (! current_function_is_leaf)
2235 /* Emit a save of BR0 if we call other functions. Do this even
2236 if this function doesn't return, as EH depends on this to be
2237 able to unwind the stack. */
2238 SET_HARD_REG_BIT (mask, BR_REG (0));
2240 current_frame_info.reg_save_b0 = find_gr_spill (1);
2241 if (current_frame_info.reg_save_b0 == 0)
2247 /* Similarly for ar.pfs. */
2248 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2249 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2250 if (current_frame_info.reg_save_ar_pfs == 0)
2252 extra_spill_size += 8;
2256 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2257 registers are clobbered, so we fall back to the stack. */
2258 current_frame_info.reg_save_gp
2259 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
2260 if (current_frame_info.reg_save_gp == 0)
2262 SET_HARD_REG_BIT (mask, GR_REG (1));
2269 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
2271 SET_HARD_REG_BIT (mask, BR_REG (0));
2276 if (regs_ever_live[AR_PFS_REGNUM])
2278 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
2279 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
2280 if (current_frame_info.reg_save_ar_pfs == 0)
2282 extra_spill_size += 8;
2288 /* Unwind descriptor hackery: things are most efficient if we allocate
2289 consecutive GR save registers for RP, PFS, FP in that order. However,
2290 it is absolutely critical that FP get the only hard register that's
2291 guaranteed to be free, so we allocated it first. If all three did
2292 happen to be allocated hard regs, and are consecutive, rearrange them
2293 into the preferred order now. */
2294 if (current_frame_info.reg_fp != 0
2295 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
2296 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
2298 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
2299 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
2300 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
2303 /* See if we need to store the predicate register block. */
2304 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2305 if (regs_ever_live[regno] && ! call_used_regs[regno])
2307 if (regno <= PR_REG (63))
2309 SET_HARD_REG_BIT (mask, PR_REG (0));
2310 current_frame_info.reg_save_pr = find_gr_spill (1);
2311 if (current_frame_info.reg_save_pr == 0)
2313 extra_spill_size += 8;
2317 /* ??? Mark them all as used so that register renaming and such
2318 are free to use them. */
2319 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
2320 regs_ever_live[regno] = 1;
2323 /* If we're forced to use st8.spill, we're forced to save and restore
2324 ar.unat as well. The check for existing liveness allows inline asm
2325 to touch ar.unat. */
2326 if (spilled_gr_p || cfun->machine->n_varargs
2327 || regs_ever_live[AR_UNAT_REGNUM])
2329 regs_ever_live[AR_UNAT_REGNUM] = 1;
2330 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
2331 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
2332 if (current_frame_info.reg_save_ar_unat == 0)
2334 extra_spill_size += 8;
2339 if (regs_ever_live[AR_LC_REGNUM])
2341 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
2342 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
2343 if (current_frame_info.reg_save_ar_lc == 0)
2345 extra_spill_size += 8;
2350 /* If we have an odd number of words of pretend arguments written to
2351 the stack, then the FR save area will be unaligned. We round the
2352 size of this area up to keep things 16 byte aligned. */
2354 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
2356 pretend_args_size = current_function_pretend_args_size;
2358 total_size = (spill_size + extra_spill_size + size + pretend_args_size
2359 + current_function_outgoing_args_size);
2360 total_size = IA64_STACK_ALIGN (total_size);
2362 /* We always use the 16-byte scratch area provided by the caller, but
2363 if we are a leaf function, there's no one to which we need to provide
2365 if (current_function_is_leaf)
2366 total_size = MAX (0, total_size - 16);
2368 current_frame_info.total_size = total_size;
2369 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2370 current_frame_info.spill_size = spill_size;
2371 current_frame_info.extra_spill_size = extra_spill_size;
2372 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2373 current_frame_info.n_spilled = n_spilled;
2374 current_frame_info.initialized = reload_completed;
2377 /* Compute the initial difference between the specified pair of registers. */
2380 ia64_initial_elimination_offset (int from, int to)
2382 HOST_WIDE_INT offset;
2384 ia64_compute_frame_size (get_frame_size ());
2387 case FRAME_POINTER_REGNUM:
2390 case HARD_FRAME_POINTER_REGNUM:
2391 if (current_function_is_leaf)
2392 offset = -current_frame_info.total_size;
2394 offset = -(current_frame_info.total_size
2395 - current_function_outgoing_args_size - 16);
2398 case STACK_POINTER_REGNUM:
2399 if (current_function_is_leaf)
2402 offset = 16 + current_function_outgoing_args_size;
2410 case ARG_POINTER_REGNUM:
2411 /* Arguments start above the 16 byte save area, unless stdarg
2412 in which case we store through the 16 byte save area. */
2415 case HARD_FRAME_POINTER_REGNUM:
2416 offset = 16 - current_function_pretend_args_size;
2419 case STACK_POINTER_REGNUM:
2420 offset = (current_frame_info.total_size
2421 + 16 - current_function_pretend_args_size);
2436 /* If there are more than a trivial number of register spills, we use
2437 two interleaved iterators so that we can get two memory references
2440 In order to simplify things in the prologue and epilogue expanders,
2441 we use helper functions to fix up the memory references after the
2442 fact with the appropriate offsets to a POST_MODIFY memory mode.
2443 The following data structure tracks the state of the two iterators
2444 while insns are being emitted. */
2446 struct spill_fill_data
2448 rtx init_after; /* point at which to emit initializations */
2449 rtx init_reg[2]; /* initial base register */
2450 rtx iter_reg[2]; /* the iterator registers */
2451 rtx *prev_addr[2]; /* address of last memory use */
2452 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2453 HOST_WIDE_INT prev_off[2]; /* last offset */
2454 int n_iter; /* number of iterators in use */
2455 int next_iter; /* next iterator to use */
2456 unsigned int save_gr_used_mask;
2459 static struct spill_fill_data spill_fill_data;
2462 setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
2466 spill_fill_data.init_after = get_last_insn ();
2467 spill_fill_data.init_reg[0] = init_reg;
2468 spill_fill_data.init_reg[1] = init_reg;
2469 spill_fill_data.prev_addr[0] = NULL;
2470 spill_fill_data.prev_addr[1] = NULL;
2471 spill_fill_data.prev_insn[0] = NULL;
2472 spill_fill_data.prev_insn[1] = NULL;
2473 spill_fill_data.prev_off[0] = cfa_off;
2474 spill_fill_data.prev_off[1] = cfa_off;
2475 spill_fill_data.next_iter = 0;
2476 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2478 spill_fill_data.n_iter = 1 + (n_spills > 2);
2479 for (i = 0; i < spill_fill_data.n_iter; ++i)
2481 int regno = next_scratch_gr_reg ();
2482 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2483 current_frame_info.gr_used_mask |= 1 << regno;
2488 finish_spill_pointers (void)
2490 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2494 spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
2496 int iter = spill_fill_data.next_iter;
2497 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2498 rtx disp_rtx = GEN_INT (disp);
2501 if (spill_fill_data.prev_addr[iter])
2503 if (CONST_OK_FOR_N (disp))
2505 *spill_fill_data.prev_addr[iter]
2506 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2507 gen_rtx_PLUS (DImode,
2508 spill_fill_data.iter_reg[iter],
2510 REG_NOTES (spill_fill_data.prev_insn[iter])
2511 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2512 REG_NOTES (spill_fill_data.prev_insn[iter]));
2516 /* ??? Could use register post_modify for loads. */
2517 if (! CONST_OK_FOR_I (disp))
2519 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2520 emit_move_insn (tmp, disp_rtx);
2523 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2524 spill_fill_data.iter_reg[iter], disp_rtx));
2527 /* Micro-optimization: if we've created a frame pointer, it's at
2528 CFA 0, which may allow the real iterator to be initialized lower,
2529 slightly increasing parallelism. Also, if there are few saves
2530 it may eliminate the iterator entirely. */
2532 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2533 && frame_pointer_needed)
2535 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2536 set_mem_alias_set (mem, get_varargs_alias_set ());
2544 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2545 spill_fill_data.init_reg[iter]);
2550 if (! CONST_OK_FOR_I (disp))
2552 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2553 emit_move_insn (tmp, disp_rtx);
2557 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2558 spill_fill_data.init_reg[iter],
2565 /* Careful for being the first insn in a sequence. */
2566 if (spill_fill_data.init_after)
2567 insn = emit_insn_after (seq, spill_fill_data.init_after);
2570 rtx first = get_insns ();
2572 insn = emit_insn_before (seq, first);
2574 insn = emit_insn (seq);
2576 spill_fill_data.init_after = insn;
2578 /* If DISP is 0, we may or may not have a further adjustment
2579 afterward. If we do, then the load/store insn may be modified
2580 to be a post-modify. If we don't, then this copy may be
2581 eliminated by copyprop_hardreg_forward, which makes this
2582 insn garbage, which runs afoul of the sanity check in
2583 propagate_one_insn. So mark this insn as legal to delete. */
2585 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2589 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2591 /* ??? Not all of the spills are for varargs, but some of them are.
2592 The rest of the spills belong in an alias set of their own. But
2593 it doesn't actually hurt to include them here. */
2594 set_mem_alias_set (mem, get_varargs_alias_set ());
2596 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2597 spill_fill_data.prev_off[iter] = cfa_off;
2599 if (++iter >= spill_fill_data.n_iter)
2601 spill_fill_data.next_iter = iter;
2607 do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
2610 int iter = spill_fill_data.next_iter;
2613 mem = spill_restore_mem (reg, cfa_off);
2614 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2615 spill_fill_data.prev_insn[iter] = insn;
2622 RTX_FRAME_RELATED_P (insn) = 1;
2624 /* Don't even pretend that the unwind code can intuit its way
2625 through a pair of interleaved post_modify iterators. Just
2626 provide the correct answer. */
2628 if (frame_pointer_needed)
2630 base = hard_frame_pointer_rtx;
2635 base = stack_pointer_rtx;
2636 off = current_frame_info.total_size - cfa_off;
2640 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2641 gen_rtx_SET (VOIDmode,
2642 gen_rtx_MEM (GET_MODE (reg),
2643 plus_constant (base, off)),
2650 do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
2652 int iter = spill_fill_data.next_iter;
2655 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2656 GEN_INT (cfa_off)));
2657 spill_fill_data.prev_insn[iter] = insn;
2660 /* Wrapper functions that discards the CONST_INT spill offset. These
2661 exist so that we can give gr_spill/gr_fill the offset they need and
2662 use a consistent function interface. */
2665 gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2667 return gen_movdi (dest, src);
2671 gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2673 return gen_fr_spill (dest, src);
2677 gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
2679 return gen_fr_restore (dest, src);
2682 /* Called after register allocation to add any instructions needed for the
2683 prologue. Using a prologue insn is favored compared to putting all of the
2684 instructions in output_function_prologue(), since it allows the scheduler
2685 to intermix instructions with the saves of the caller saved registers. In
2686 some cases, it might be necessary to emit a barrier instruction as the last
2687 insn to prevent such scheduling.
2689 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2690 so that the debug info generation code can handle them properly.
2692 The register save area is layed out like so:
2694 [ varargs spill area ]
2695 [ fr register spill area ]
2696 [ br register spill area ]
2697 [ ar register spill area ]
2698 [ pr register spill area ]
2699 [ gr register spill area ] */
2701 /* ??? Get inefficient code when the frame size is larger than can fit in an
2702 adds instruction. */
2705 ia64_expand_prologue (void)
2707 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2708 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2711 ia64_compute_frame_size (get_frame_size ());
2712 last_scratch_gr_reg = 15;
2714 /* If there is no epilogue, then we don't need some prologue insns.
2715 We need to avoid emitting the dead prologue insns, because flow
2716 will complain about them. */
2722 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
2723 if ((e->flags & EDGE_FAKE) == 0
2724 && (e->flags & EDGE_FALLTHRU) != 0)
2726 epilogue_p = (e != NULL);
2731 /* Set the local, input, and output register names. We need to do this
2732 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2733 half. If we use in/loc/out register names, then we get assembler errors
2734 in crtn.S because there is no alloc insn or regstk directive in there. */
2735 if (! TARGET_REG_NAMES)
2737 int inputs = current_frame_info.n_input_regs;
2738 int locals = current_frame_info.n_local_regs;
2739 int outputs = current_frame_info.n_output_regs;
2741 for (i = 0; i < inputs; i++)
2742 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2743 for (i = 0; i < locals; i++)
2744 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2745 for (i = 0; i < outputs; i++)
2746 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2749 /* Set the frame pointer register name. The regnum is logically loc79,
2750 but of course we'll not have allocated that many locals. Rather than
2751 worrying about renumbering the existing rtxs, we adjust the name. */
2752 /* ??? This code means that we can never use one local register when
2753 there is a frame pointer. loc79 gets wasted in this case, as it is
2754 renamed to a register that will never be used. See also the try_locals
2755 code in find_gr_spill. */
2756 if (current_frame_info.reg_fp)
2758 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2759 reg_names[HARD_FRAME_POINTER_REGNUM]
2760 = reg_names[current_frame_info.reg_fp];
2761 reg_names[current_frame_info.reg_fp] = tmp;
2764 /* We don't need an alloc instruction if we've used no outputs or locals. */
2765 if (current_frame_info.n_local_regs == 0
2766 && current_frame_info.n_output_regs == 0
2767 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2768 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2770 /* If there is no alloc, but there are input registers used, then we
2771 need a .regstk directive. */
2772 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2773 ar_pfs_save_reg = NULL_RTX;
2777 current_frame_info.need_regstk = 0;
2779 if (current_frame_info.reg_save_ar_pfs)
2780 regno = current_frame_info.reg_save_ar_pfs;
2782 regno = next_scratch_gr_reg ();
2783 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2785 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2786 GEN_INT (current_frame_info.n_input_regs),
2787 GEN_INT (current_frame_info.n_local_regs),
2788 GEN_INT (current_frame_info.n_output_regs),
2789 GEN_INT (current_frame_info.n_rotate_regs)));
2790 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2793 /* Set up frame pointer, stack pointer, and spill iterators. */
2795 n_varargs = cfun->machine->n_varargs;
2796 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2797 stack_pointer_rtx, 0);
2799 if (frame_pointer_needed)
2801 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2802 RTX_FRAME_RELATED_P (insn) = 1;
2805 if (current_frame_info.total_size != 0)
2807 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2810 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2811 offset = frame_size_rtx;
2814 regno = next_scratch_gr_reg ();
2815 offset = gen_rtx_REG (DImode, regno);
2816 emit_move_insn (offset, frame_size_rtx);
2819 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2820 stack_pointer_rtx, offset));
2822 if (! frame_pointer_needed)
2824 RTX_FRAME_RELATED_P (insn) = 1;
2825 if (GET_CODE (offset) != CONST_INT)
2828 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2829 gen_rtx_SET (VOIDmode,
2831 gen_rtx_PLUS (DImode,
2838 /* ??? At this point we must generate a magic insn that appears to
2839 modify the stack pointer, the frame pointer, and all spill
2840 iterators. This would allow the most scheduling freedom. For
2841 now, just hard stop. */
2842 emit_insn (gen_blockage ());
2845 /* Must copy out ar.unat before doing any integer spills. */
2846 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2848 if (current_frame_info.reg_save_ar_unat)
2850 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2853 alt_regno = next_scratch_gr_reg ();
2854 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2855 current_frame_info.gr_used_mask |= 1 << alt_regno;
2858 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2859 insn = emit_move_insn (ar_unat_save_reg, reg);
2860 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2862 /* Even if we're not going to generate an epilogue, we still
2863 need to save the register so that EH works. */
2864 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2865 emit_insn (gen_prologue_use (ar_unat_save_reg));
2868 ar_unat_save_reg = NULL_RTX;
2870 /* Spill all varargs registers. Do this before spilling any GR registers,
2871 since we want the UNAT bits for the GR registers to override the UNAT
2872 bits from varargs, which we don't care about. */
2875 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2877 reg = gen_rtx_REG (DImode, regno);
2878 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2881 /* Locate the bottom of the register save area. */
2882 cfa_off = (current_frame_info.spill_cfa_off
2883 + current_frame_info.spill_size
2884 + current_frame_info.extra_spill_size);
2886 /* Save the predicate register block either in a register or in memory. */
2887 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2889 reg = gen_rtx_REG (DImode, PR_REG (0));
2890 if (current_frame_info.reg_save_pr != 0)
2892 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2893 insn = emit_move_insn (alt_reg, reg);
2895 /* ??? Denote pr spill/fill by a DImode move that modifies all
2896 64 hard registers. */
2897 RTX_FRAME_RELATED_P (insn) = 1;
2899 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2900 gen_rtx_SET (VOIDmode, alt_reg, reg),
2903 /* Even if we're not going to generate an epilogue, we still
2904 need to save the register so that EH works. */
2906 emit_insn (gen_prologue_use (alt_reg));
2910 alt_regno = next_scratch_gr_reg ();
2911 alt_reg = gen_rtx_REG (DImode, alt_regno);
2912 insn = emit_move_insn (alt_reg, reg);
2913 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2918 /* Handle AR regs in numerical order. All of them get special handling. */
2919 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2920 && current_frame_info.reg_save_ar_unat == 0)
2922 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2923 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2927 /* The alloc insn already copied ar.pfs into a general register. The
2928 only thing we have to do now is copy that register to a stack slot
2929 if we'd not allocated a local register for the job. */
2930 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2931 && current_frame_info.reg_save_ar_pfs == 0)
2933 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2934 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2938 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2940 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2941 if (current_frame_info.reg_save_ar_lc != 0)
2943 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2944 insn = emit_move_insn (alt_reg, reg);
2945 RTX_FRAME_RELATED_P (insn) = 1;
2947 /* Even if we're not going to generate an epilogue, we still
2948 need to save the register so that EH works. */
2950 emit_insn (gen_prologue_use (alt_reg));
2954 alt_regno = next_scratch_gr_reg ();
2955 alt_reg = gen_rtx_REG (DImode, alt_regno);
2956 emit_move_insn (alt_reg, reg);
2957 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2962 if (current_frame_info.reg_save_gp)
2964 insn = emit_move_insn (gen_rtx_REG (DImode,
2965 current_frame_info.reg_save_gp),
2966 pic_offset_table_rtx);
2967 /* We don't know for sure yet if this is actually needed, since
2968 we've not split the PIC call patterns. If all of the calls
2969 are indirect, and not followed by any uses of the gp, then
2970 this save is dead. Allow it to go away. */
2972 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2975 /* We should now be at the base of the gr/br/fr spill area. */
2976 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
2977 + current_frame_info.spill_size));
2979 /* Spill all general registers. */
2980 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2981 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2983 reg = gen_rtx_REG (DImode, regno);
2984 do_spill (gen_gr_spill, reg, cfa_off, reg);
2988 /* Handle BR0 specially -- it may be getting stored permanently in
2989 some GR register. */
2990 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2992 reg = gen_rtx_REG (DImode, BR_REG (0));
2993 if (current_frame_info.reg_save_b0 != 0)
2995 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2996 insn = emit_move_insn (alt_reg, reg);
2997 RTX_FRAME_RELATED_P (insn) = 1;
2999 /* Even if we're not going to generate an epilogue, we still
3000 need to save the register so that EH works. */
3002 emit_insn (gen_prologue_use (alt_reg));
3006 alt_regno = next_scratch_gr_reg ();
3007 alt_reg = gen_rtx_REG (DImode, alt_regno);
3008 emit_move_insn (alt_reg, reg);
3009 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3014 /* Spill the rest of the BR registers. */
3015 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3016 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3018 alt_regno = next_scratch_gr_reg ();
3019 alt_reg = gen_rtx_REG (DImode, alt_regno);
3020 reg = gen_rtx_REG (DImode, regno);
3021 emit_move_insn (alt_reg, reg);
3022 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
3026 /* Align the frame and spill all FR registers. */
3027 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3028 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3030 gcc_assert (!(cfa_off & 15));
3031 reg = gen_rtx_REG (XFmode, regno);
3032 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
3036 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3038 finish_spill_pointers ();
3041 /* Called after register allocation to add any instructions needed for the
3042 epilogue. Using an epilogue insn is favored compared to putting all of the
3043 instructions in output_function_prologue(), since it allows the scheduler
3044 to intermix instructions with the saves of the caller saved registers. In
3045 some cases, it might be necessary to emit a barrier instruction as the last
3046 insn to prevent such scheduling. */
3049 ia64_expand_epilogue (int sibcall_p)
3051 rtx insn, reg, alt_reg, ar_unat_save_reg;
3052 int regno, alt_regno, cfa_off;
3054 ia64_compute_frame_size (get_frame_size ());
3056 /* If there is a frame pointer, then we use it instead of the stack
3057 pointer, so that the stack pointer does not need to be valid when
3058 the epilogue starts. See EXIT_IGNORE_STACK. */
3059 if (frame_pointer_needed)
3060 setup_spill_pointers (current_frame_info.n_spilled,
3061 hard_frame_pointer_rtx, 0);
3063 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
3064 current_frame_info.total_size);
3066 if (current_frame_info.total_size != 0)
3068 /* ??? At this point we must generate a magic insn that appears to
3069 modify the spill iterators and the frame pointer. This would
3070 allow the most scheduling freedom. For now, just hard stop. */
3071 emit_insn (gen_blockage ());
3074 /* Locate the bottom of the register save area. */
3075 cfa_off = (current_frame_info.spill_cfa_off
3076 + current_frame_info.spill_size
3077 + current_frame_info.extra_spill_size);
3079 /* Restore the predicate registers. */
3080 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
3082 if (current_frame_info.reg_save_pr != 0)
3083 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
3086 alt_regno = next_scratch_gr_reg ();
3087 alt_reg = gen_rtx_REG (DImode, alt_regno);
3088 do_restore (gen_movdi_x, alt_reg, cfa_off);
3091 reg = gen_rtx_REG (DImode, PR_REG (0));
3092 emit_move_insn (reg, alt_reg);
3095 /* Restore the application registers. */
3097 /* Load the saved unat from the stack, but do not restore it until
3098 after the GRs have been restored. */
3099 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3101 if (current_frame_info.reg_save_ar_unat != 0)
3103 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
3106 alt_regno = next_scratch_gr_reg ();
3107 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
3108 current_frame_info.gr_used_mask |= 1 << alt_regno;
3109 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
3114 ar_unat_save_reg = NULL_RTX;
3116 if (current_frame_info.reg_save_ar_pfs != 0)
3118 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
3119 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3120 emit_move_insn (reg, alt_reg);
3122 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
3124 alt_regno = next_scratch_gr_reg ();
3125 alt_reg = gen_rtx_REG (DImode, alt_regno);
3126 do_restore (gen_movdi_x, alt_reg, cfa_off);
3128 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
3129 emit_move_insn (reg, alt_reg);
3132 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
3134 if (current_frame_info.reg_save_ar_lc != 0)
3135 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
3138 alt_regno = next_scratch_gr_reg ();
3139 alt_reg = gen_rtx_REG (DImode, alt_regno);
3140 do_restore (gen_movdi_x, alt_reg, cfa_off);
3143 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
3144 emit_move_insn (reg, alt_reg);
3147 /* We should now be at the base of the gr/br/fr spill area. */
3148 gcc_assert (cfa_off == (current_frame_info.spill_cfa_off
3149 + current_frame_info.spill_size));
3151 /* The GP may be stored on the stack in the prologue, but it's
3152 never restored in the epilogue. Skip the stack slot. */
3153 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
3156 /* Restore all general registers. */
3157 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
3158 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3160 reg = gen_rtx_REG (DImode, regno);
3161 do_restore (gen_gr_restore, reg, cfa_off);
3165 /* Restore the branch registers. Handle B0 specially, as it may
3166 have gotten stored in some GR register. */
3167 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3169 if (current_frame_info.reg_save_b0 != 0)
3170 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3173 alt_regno = next_scratch_gr_reg ();
3174 alt_reg = gen_rtx_REG (DImode, alt_regno);
3175 do_restore (gen_movdi_x, alt_reg, cfa_off);
3178 reg = gen_rtx_REG (DImode, BR_REG (0));
3179 emit_move_insn (reg, alt_reg);
3182 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
3183 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3185 alt_regno = next_scratch_gr_reg ();
3186 alt_reg = gen_rtx_REG (DImode, alt_regno);
3187 do_restore (gen_movdi_x, alt_reg, cfa_off);
3189 reg = gen_rtx_REG (DImode, regno);
3190 emit_move_insn (reg, alt_reg);
3193 /* Restore floating point registers. */
3194 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
3195 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3197 gcc_assert (!(cfa_off & 15));
3198 reg = gen_rtx_REG (XFmode, regno);
3199 do_restore (gen_fr_restore_x, reg, cfa_off);
3203 /* Restore ar.unat for real. */
3204 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
3206 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
3207 emit_move_insn (reg, ar_unat_save_reg);
3210 gcc_assert (cfa_off == current_frame_info.spill_cfa_off);
3212 finish_spill_pointers ();
3214 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
3216 /* ??? At this point we must generate a magic insn that appears to
3217 modify the spill iterators, the stack pointer, and the frame
3218 pointer. This would allow the most scheduling freedom. For now,
3220 emit_insn (gen_blockage ());
3223 if (cfun->machine->ia64_eh_epilogue_sp)
3224 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
3225 else if (frame_pointer_needed)
3227 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
3228 RTX_FRAME_RELATED_P (insn) = 1;
3230 else if (current_frame_info.total_size)
3232 rtx offset, frame_size_rtx;
3234 frame_size_rtx = GEN_INT (current_frame_info.total_size);
3235 if (CONST_OK_FOR_I (current_frame_info.total_size))
3236 offset = frame_size_rtx;
3239 regno = next_scratch_gr_reg ();
3240 offset = gen_rtx_REG (DImode, regno);
3241 emit_move_insn (offset, frame_size_rtx);
3244 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
3247 RTX_FRAME_RELATED_P (insn) = 1;
3248 if (GET_CODE (offset) != CONST_INT)
3251 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3252 gen_rtx_SET (VOIDmode,
3254 gen_rtx_PLUS (DImode,
3261 if (cfun->machine->ia64_eh_epilogue_bsp)
3262 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
3265 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
3268 int fp = GR_REG (2);
3269 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3270 first available call clobbered register. If there was a frame_pointer
3271 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3272 so we have to make sure we're using the string "r2" when emitting
3273 the register name for the assembler. */
3274 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
3275 fp = HARD_FRAME_POINTER_REGNUM;
3277 /* We must emit an alloc to force the input registers to become output
3278 registers. Otherwise, if the callee tries to pass its parameters
3279 through to another call without an intervening alloc, then these
3281 /* ??? We don't need to preserve all input registers. We only need to
3282 preserve those input registers used as arguments to the sibling call.
3283 It is unclear how to compute that number here. */
3284 if (current_frame_info.n_input_regs != 0)
3286 rtx n_inputs = GEN_INT (current_frame_info.n_input_regs);
3287 insn = emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
3288 const0_rtx, const0_rtx,
3289 n_inputs, const0_rtx));
3290 RTX_FRAME_RELATED_P (insn) = 1;
3295 /* Return 1 if br.ret can do all the work required to return from a
3299 ia64_direct_return (void)
3301 if (reload_completed && ! frame_pointer_needed)
3303 ia64_compute_frame_size (get_frame_size ());
3305 return (current_frame_info.total_size == 0
3306 && current_frame_info.n_spilled == 0
3307 && current_frame_info.reg_save_b0 == 0
3308 && current_frame_info.reg_save_pr == 0
3309 && current_frame_info.reg_save_ar_pfs == 0
3310 && current_frame_info.reg_save_ar_unat == 0
3311 && current_frame_info.reg_save_ar_lc == 0);
3316 /* Return the magic cookie that we use to hold the return address
3317 during early compilation. */
3320 ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
3324 return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
3327 /* Split this value after reload, now that we know where the return
3328 address is saved. */
3331 ia64_split_return_addr_rtx (rtx dest)
3335 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
3337 if (current_frame_info.reg_save_b0 != 0)
3338 src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
3344 /* Compute offset from CFA for BR0. */
3345 /* ??? Must be kept in sync with ia64_expand_prologue. */
3346 off = (current_frame_info.spill_cfa_off
3347 + current_frame_info.spill_size);
3348 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
3349 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
3352 /* Convert CFA offset to a register based offset. */
3353 if (frame_pointer_needed)
3354 src = hard_frame_pointer_rtx;
3357 src = stack_pointer_rtx;
3358 off += current_frame_info.total_size;
3361 /* Load address into scratch register. */
3362 if (CONST_OK_FOR_I (off))
3363 emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
3366 emit_move_insn (dest, GEN_INT (off));
3367 emit_insn (gen_adddi3 (dest, src, dest));
3370 src = gen_rtx_MEM (Pmode, dest);
3374 src = gen_rtx_REG (DImode, BR_REG (0));
3376 emit_move_insn (dest, src);
3380 ia64_hard_regno_rename_ok (int from, int to)
3382 /* Don't clobber any of the registers we reserved for the prologue. */
3383 if (to == current_frame_info.reg_fp
3384 || to == current_frame_info.reg_save_b0
3385 || to == current_frame_info.reg_save_pr
3386 || to == current_frame_info.reg_save_ar_pfs
3387 || to == current_frame_info.reg_save_ar_unat
3388 || to == current_frame_info.reg_save_ar_lc)
3391 if (from == current_frame_info.reg_fp
3392 || from == current_frame_info.reg_save_b0
3393 || from == current_frame_info.reg_save_pr
3394 || from == current_frame_info.reg_save_ar_pfs
3395 || from == current_frame_info.reg_save_ar_unat
3396 || from == current_frame_info.reg_save_ar_lc)
3399 /* Don't use output registers outside the register frame. */
3400 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3403 /* Retain even/oddness on predicate register pairs. */
3404 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3405 return (from & 1) == (to & 1);
3410 /* Target hook for assembling integer objects. Handle word-sized
3411 aligned objects and detect the cases when @fptr is needed. */
3414 ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
3416 if (size == POINTER_SIZE / BITS_PER_UNIT
3417 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3418 && GET_CODE (x) == SYMBOL_REF
3419 && SYMBOL_REF_FUNCTION_P (x))
3421 static const char * const directive[2][2] = {
3422 /* 64-bit pointer */ /* 32-bit pointer */
3423 { "\tdata8.ua\t@fptr(", "\tdata4.ua\t@fptr("}, /* unaligned */
3424 { "\tdata8\t@fptr(", "\tdata4\t@fptr("} /* aligned */
3426 fputs (directive[(aligned_p != 0)][POINTER_SIZE == 32], asm_out_file);
3427 output_addr_const (asm_out_file, x);
3428 fputs (")\n", asm_out_file);
3431 return default_assemble_integer (x, size, aligned_p);
3434 /* Emit the function prologue. */
3437 ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3439 int mask, grsave, grsave_prev;
3441 if (current_frame_info.need_regstk)
3442 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3443 current_frame_info.n_input_regs,
3444 current_frame_info.n_local_regs,
3445 current_frame_info.n_output_regs,
3446 current_frame_info.n_rotate_regs);
3448 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3451 /* Emit the .prologue directive. */
3454 grsave = grsave_prev = 0;
3455 if (current_frame_info.reg_save_b0 != 0)
3458 grsave = grsave_prev = current_frame_info.reg_save_b0;
3460 if (current_frame_info.reg_save_ar_pfs != 0
3461 && (grsave_prev == 0
3462 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3465 if (grsave_prev == 0)
3466 grsave = current_frame_info.reg_save_ar_pfs;
3467 grsave_prev = current_frame_info.reg_save_ar_pfs;
3469 if (current_frame_info.reg_fp != 0
3470 && (grsave_prev == 0
3471 || current_frame_info.reg_fp == grsave_prev + 1))
3474 if (grsave_prev == 0)
3475 grsave = HARD_FRAME_POINTER_REGNUM;
3476 grsave_prev = current_frame_info.reg_fp;
3478 if (current_frame_info.reg_save_pr != 0
3479 && (grsave_prev == 0
3480 || current_frame_info.reg_save_pr == grsave_prev + 1))
3483 if (grsave_prev == 0)
3484 grsave = current_frame_info.reg_save_pr;
3487 if (mask && TARGET_GNU_AS)
3488 fprintf (file, "\t.prologue %d, %d\n", mask,
3489 ia64_dbx_register_number (grsave));
3491 fputs ("\t.prologue\n", file);
3493 /* Emit a .spill directive, if necessary, to relocate the base of
3494 the register spill area. */
3495 if (current_frame_info.spill_cfa_off != -16)
3496 fprintf (file, "\t.spill %ld\n",
3497 (long) (current_frame_info.spill_cfa_off
3498 + current_frame_info.spill_size));
3501 /* Emit the .body directive at the scheduled end of the prologue. */
3504 ia64_output_function_end_prologue (FILE *file)
3506 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3509 fputs ("\t.body\n", file);
3512 /* Emit the function epilogue. */
3515 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
3516 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3520 if (current_frame_info.reg_fp)
3522 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3523 reg_names[HARD_FRAME_POINTER_REGNUM]
3524 = reg_names[current_frame_info.reg_fp];
3525 reg_names[current_frame_info.reg_fp] = tmp;
3527 if (! TARGET_REG_NAMES)
3529 for (i = 0; i < current_frame_info.n_input_regs; i++)
3530 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3531 for (i = 0; i < current_frame_info.n_local_regs; i++)
3532 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3533 for (i = 0; i < current_frame_info.n_output_regs; i++)
3534 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3537 current_frame_info.initialized = 0;
3541 ia64_dbx_register_number (int regno)
3543 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3544 from its home at loc79 to something inside the register frame. We
3545 must perform the same renumbering here for the debug info. */
3546 if (current_frame_info.reg_fp)
3548 if (regno == HARD_FRAME_POINTER_REGNUM)
3549 regno = current_frame_info.reg_fp;
3550 else if (regno == current_frame_info.reg_fp)
3551 regno = HARD_FRAME_POINTER_REGNUM;
3554 if (IN_REGNO_P (regno))
3555 return 32 + regno - IN_REG (0);
3556 else if (LOC_REGNO_P (regno))
3557 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3558 else if (OUT_REGNO_P (regno))
3559 return (32 + current_frame_info.n_input_regs
3560 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3566 ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
3568 rtx addr_reg, eight = GEN_INT (8);
3570 /* The Intel assembler requires that the global __ia64_trampoline symbol
3571 be declared explicitly */
3574 static bool declared_ia64_trampoline = false;
3576 if (!declared_ia64_trampoline)
3578 declared_ia64_trampoline = true;
3579 (*targetm.asm_out.globalize_label) (asm_out_file,
3580 "__ia64_trampoline");
3584 /* Make sure addresses are Pmode even if we are in ILP32 mode. */
3585 addr = convert_memory_address (Pmode, addr);
3586 fnaddr = convert_memory_address (Pmode, fnaddr);
3587 static_chain = convert_memory_address (Pmode, static_chain);
3589 /* Load up our iterator. */
3590 addr_reg = gen_reg_rtx (Pmode);
3591 emit_move_insn (addr_reg, addr);
3593 /* The first two words are the fake descriptor:
3594 __ia64_trampoline, ADDR+16. */
3595 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3596 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3597 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3599 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3600 copy_to_reg (plus_constant (addr, 16)));
3601 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3603 /* The third word is the target descriptor. */
3604 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3605 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3607 /* The fourth word is the static chain. */
3608 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3611 /* Do any needed setup for a variadic function. CUM has not been updated
3612 for the last named argument which has type TYPE and mode MODE.
3614 We generate the actual spill instructions during prologue generation. */
3617 ia64_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3618 tree type, int * pretend_size,
3619 int second_time ATTRIBUTE_UNUSED)
3621 CUMULATIVE_ARGS next_cum = *cum;
3623 /* Skip the current argument. */
3624 ia64_function_arg_advance (&next_cum, mode, type, 1);
3626 if (next_cum.words < MAX_ARGUMENT_SLOTS)
3628 int n = MAX_ARGUMENT_SLOTS - next_cum.words;
3629 *pretend_size = n * UNITS_PER_WORD;
3630 cfun->machine->n_varargs = n;
3634 /* Check whether TYPE is a homogeneous floating point aggregate. If
3635 it is, return the mode of the floating point type that appears
3636 in all leafs. If it is not, return VOIDmode.
3638 An aggregate is a homogeneous floating point aggregate is if all
3639 fields/elements in it have the same floating point type (e.g,
3640 SFmode). 128-bit quad-precision floats are excluded.
3642 Variable sized aggregates should never arrive here, since we should
3643 have already decided to pass them by reference. Top-level zero-sized
3644 aggregates are excluded because our parallels crash the middle-end. */
3646 static enum machine_mode
3647 hfa_element_mode (tree type, bool nested)
3649 enum machine_mode element_mode = VOIDmode;
3650 enum machine_mode mode;
3651 enum tree_code code = TREE_CODE (type);
3652 int know_element_mode = 0;
3655 if (!nested && (!TYPE_SIZE (type) || integer_zerop (TYPE_SIZE (type))))
3660 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3661 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3662 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3663 case LANG_TYPE: case FUNCTION_TYPE:
3666 /* Fortran complex types are supposed to be HFAs, so we need to handle
3667 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3670 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3671 && TYPE_MODE (type) != TCmode)
3672 return GET_MODE_INNER (TYPE_MODE (type));
3677 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3678 mode if this is contained within an aggregate. */
3679 if (nested && TYPE_MODE (type) != TFmode)
3680 return TYPE_MODE (type);
3685 return hfa_element_mode (TREE_TYPE (type), 1);
3689 case QUAL_UNION_TYPE:
3690 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3692 if (TREE_CODE (t) != FIELD_DECL)
3695 mode = hfa_element_mode (TREE_TYPE (t), 1);
3696 if (know_element_mode)
3698 if (mode != element_mode)
3701 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3705 know_element_mode = 1;
3706 element_mode = mode;
3709 return element_mode;
3712 /* If we reach here, we probably have some front-end specific type
3713 that the backend doesn't know about. This can happen via the
3714 aggregate_value_p call in init_function_start. All we can do is
3715 ignore unknown tree types. */
3722 /* Return the number of words required to hold a quantity of TYPE and MODE
3723 when passed as an argument. */
3725 ia64_function_arg_words (tree type, enum machine_mode mode)
3729 if (mode == BLKmode)
3730 words = int_size_in_bytes (type);
3732 words = GET_MODE_SIZE (mode);
3734 return (words + UNITS_PER_WORD - 1) / UNITS_PER_WORD; /* round up */
3737 /* Return the number of registers that should be skipped so the current
3738 argument (described by TYPE and WORDS) will be properly aligned.
3740 Integer and float arguments larger than 8 bytes start at the next
3741 even boundary. Aggregates larger than 8 bytes start at the next
3742 even boundary if the aggregate has 16 byte alignment. Note that
3743 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3744 but are still to be aligned in registers.
3746 ??? The ABI does not specify how to handle aggregates with
3747 alignment from 9 to 15 bytes, or greater than 16. We handle them
3748 all as if they had 16 byte alignment. Such aggregates can occur
3749 only if gcc extensions are used. */
3751 ia64_function_arg_offset (CUMULATIVE_ARGS *cum, tree type, int words)
3753 if ((cum->words & 1) == 0)
3757 && TREE_CODE (type) != INTEGER_TYPE
3758 && TREE_CODE (type) != REAL_TYPE)
3759 return TYPE_ALIGN (type) > 8 * BITS_PER_UNIT;
3764 /* Return rtx for register where argument is passed, or zero if it is passed
3766 /* ??? 128-bit quad-precision floats are always passed in general
3770 ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
3771 int named, int incoming)
3773 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3774 int words = ia64_function_arg_words (type, mode);
3775 int offset = ia64_function_arg_offset (cum, type, words);
3776 enum machine_mode hfa_mode = VOIDmode;
3778 /* If all argument slots are used, then it must go on the stack. */
3779 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3782 /* Check for and handle homogeneous FP aggregates. */
3784 hfa_mode = hfa_element_mode (type, 0);
3786 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3787 and unprototyped hfas are passed specially. */
3788 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3792 int fp_regs = cum->fp_regs;
3793 int int_regs = cum->words + offset;
3794 int hfa_size = GET_MODE_SIZE (hfa_mode);
3798 /* If prototyped, pass it in FR regs then GR regs.
3799 If not prototyped, pass it in both FR and GR regs.
3801 If this is an SFmode aggregate, then it is possible to run out of
3802 FR regs while GR regs are still left. In that case, we pass the
3803 remaining part in the GR regs. */
3805 /* Fill the FP regs. We do this always. We stop if we reach the end
3806 of the argument, the last FP register, or the last argument slot. */
3808 byte_size = ((mode == BLKmode)
3809 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3810 args_byte_size = int_regs * UNITS_PER_WORD;
3812 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3813 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3815 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3816 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3820 args_byte_size += hfa_size;
3824 /* If no prototype, then the whole thing must go in GR regs. */
3825 if (! cum->prototype)
3827 /* If this is an SFmode aggregate, then we might have some left over
3828 that needs to go in GR regs. */
3829 else if (byte_size != offset)
3830 int_regs += offset / UNITS_PER_WORD;
3832 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3834 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3836 enum machine_mode gr_mode = DImode;
3837 unsigned int gr_size;
3839 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3840 then this goes in a GR reg left adjusted/little endian, right
3841 adjusted/big endian. */
3842 /* ??? Currently this is handled wrong, because 4-byte hunks are
3843 always right adjusted/little endian. */
3846 /* If we have an even 4 byte hunk because the aggregate is a
3847 multiple of 4 bytes in size, then this goes in a GR reg right
3848 adjusted/little endian. */
3849 else if (byte_size - offset == 4)
3852 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3853 gen_rtx_REG (gr_mode, (basereg
3857 gr_size = GET_MODE_SIZE (gr_mode);
3859 if (gr_size == UNITS_PER_WORD
3860 || (gr_size < UNITS_PER_WORD && offset % UNITS_PER_WORD == 0))
3862 else if (gr_size > UNITS_PER_WORD)
3863 int_regs += gr_size / UNITS_PER_WORD;
3865 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3868 /* Integral and aggregates go in general registers. If we have run out of
3869 FR registers, then FP values must also go in general registers. This can
3870 happen when we have a SFmode HFA. */
3871 else if (mode == TFmode || mode == TCmode
3872 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3874 int byte_size = ((mode == BLKmode)
3875 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3876 if (BYTES_BIG_ENDIAN
3877 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3878 && byte_size < UNITS_PER_WORD
3881 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3882 gen_rtx_REG (DImode,
3883 (basereg + cum->words
3886 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3889 return gen_rtx_REG (mode, basereg + cum->words + offset);
3893 /* If there is a prototype, then FP values go in a FR register when
3894 named, and in a GR register when unnamed. */
3895 else if (cum->prototype)
3898 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3899 /* In big-endian mode, an anonymous SFmode value must be represented
3900 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3901 the value into the high half of the general register. */
3902 else if (BYTES_BIG_ENDIAN && mode == SFmode)
3903 return gen_rtx_PARALLEL (mode,
3905 gen_rtx_EXPR_LIST (VOIDmode,
3906 gen_rtx_REG (DImode, basereg + cum->words + offset),
3908 /* Similarly, an anonymous XFmode or RFmode value must be split
3909 into two registers and padded appropriately. */
3910 else if (BYTES_BIG_ENDIAN && (mode == XFmode || mode == RFmode))
3913 loc[0] = gen_rtx_EXPR_LIST (VOIDmode,
3914 gen_rtx_REG (DImode, basereg + cum->words + offset),
3916 loc[1] = gen_rtx_EXPR_LIST (VOIDmode,
3917 gen_rtx_REG (DImode, basereg + cum->words + offset + 1),
3918 GEN_INT (UNITS_PER_WORD));
3919 return gen_rtx_PARALLEL (mode, gen_rtvec_v (2, loc));
3922 return gen_rtx_REG (mode, basereg + cum->words + offset);
3924 /* If there is no prototype, then FP values go in both FR and GR
3928 /* See comment above. */
3929 enum machine_mode inner_mode =
3930 (BYTES_BIG_ENDIAN && mode == SFmode) ? DImode : mode;
3932 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3933 gen_rtx_REG (mode, (FR_ARG_FIRST
3936 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3937 gen_rtx_REG (inner_mode,
3938 (basereg + cum->words
3942 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3946 /* Return number of bytes, at the beginning of the argument, that must be
3947 put in registers. 0 is the argument is entirely in registers or entirely
3951 ia64_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3952 tree type, bool named ATTRIBUTE_UNUSED)
3954 int words = ia64_function_arg_words (type, mode);
3955 int offset = ia64_function_arg_offset (cum, type, words);
3957 /* If all argument slots are used, then it must go on the stack. */
3958 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3961 /* It doesn't matter whether the argument goes in FR or GR regs. If
3962 it fits within the 8 argument slots, then it goes entirely in
3963 registers. If it extends past the last argument slot, then the rest
3964 goes on the stack. */
3966 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3969 return (MAX_ARGUMENT_SLOTS - cum->words - offset) * UNITS_PER_WORD;
3972 /* Update CUM to point after this argument. This is patterned after
3973 ia64_function_arg. */
3976 ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3977 tree type, int named)
3979 int words = ia64_function_arg_words (type, mode);
3980 int offset = ia64_function_arg_offset (cum, type, words);
3981 enum machine_mode hfa_mode = VOIDmode;
3983 /* If all arg slots are already full, then there is nothing to do. */
3984 if (cum->words >= MAX_ARGUMENT_SLOTS)
3987 cum->words += words + offset;
3989 /* Check for and handle homogeneous FP aggregates. */
3991 hfa_mode = hfa_element_mode (type, 0);
3993 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3994 and unprototyped hfas are passed specially. */
3995 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3997 int fp_regs = cum->fp_regs;
3998 /* This is the original value of cum->words + offset. */
3999 int int_regs = cum->words - words;
4000 int hfa_size = GET_MODE_SIZE (hfa_mode);
4004 /* If prototyped, pass it in FR regs then GR regs.
4005 If not prototyped, pass it in both FR and GR regs.
4007 If this is an SFmode aggregate, then it is possible to run out of
4008 FR regs while GR regs are still left. In that case, we pass the
4009 remaining part in the GR regs. */
4011 /* Fill the FP regs. We do this always. We stop if we reach the end
4012 of the argument, the last FP register, or the last argument slot. */
4014 byte_size = ((mode == BLKmode)
4015 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
4016 args_byte_size = int_regs * UNITS_PER_WORD;
4018 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
4019 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
4022 args_byte_size += hfa_size;
4026 cum->fp_regs = fp_regs;
4029 /* Integral and aggregates go in general registers. So do TFmode FP values.
4030 If we have run out of FR registers, then other FP values must also go in
4031 general registers. This can happen when we have a SFmode HFA. */
4032 else if (mode == TFmode || mode == TCmode
4033 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
4034 cum->int_regs = cum->words;
4036 /* If there is a prototype, then FP values go in a FR register when
4037 named, and in a GR register when unnamed. */
4038 else if (cum->prototype)
4041 cum->int_regs = cum->words;
4043 /* ??? Complex types should not reach here. */
4044 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4046 /* If there is no prototype, then FP values go in both FR and GR
4050 /* ??? Complex types should not reach here. */
4051 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
4052 cum->int_regs = cum->words;
4056 /* Arguments with alignment larger than 8 bytes start at the next even
4057 boundary. On ILP32 HPUX, TFmode arguments start on next even boundary
4058 even though their normal alignment is 8 bytes. See ia64_function_arg. */
4061 ia64_function_arg_boundary (enum machine_mode mode, tree type)
4064 if (mode == TFmode && TARGET_HPUX && TARGET_ILP32)
4065 return PARM_BOUNDARY * 2;
4069 if (TYPE_ALIGN (type) > PARM_BOUNDARY)
4070 return PARM_BOUNDARY * 2;
4072 return PARM_BOUNDARY;
4075 if (GET_MODE_BITSIZE (mode) > PARM_BOUNDARY)
4076 return PARM_BOUNDARY * 2;
4078 return PARM_BOUNDARY;
4081 /* Variable sized types are passed by reference. */
4082 /* ??? At present this is a GCC extension to the IA-64 ABI. */
4085 ia64_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4086 enum machine_mode mode ATTRIBUTE_UNUSED,
4087 tree type, bool named ATTRIBUTE_UNUSED)
4089 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
4092 /* True if it is OK to do sibling call optimization for the specified
4093 call expression EXP. DECL will be the called function, or NULL if
4094 this is an indirect call. */
4096 ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
4098 /* We can't perform a sibcall if the current function has the syscall_linkage
4100 if (lookup_attribute ("syscall_linkage",
4101 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
4104 /* We must always return with our current GP. This means we can
4105 only sibcall to functions defined in the current module. */
4106 return decl && (*targetm.binds_local_p) (decl);
4110 /* Implement va_arg. */
4113 ia64_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4115 /* Variable sized types are passed by reference. */
4116 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4118 tree ptrtype = build_pointer_type (type);
4119 tree addr = std_gimplify_va_arg_expr (valist, ptrtype, pre_p, post_p);
4120 return build_va_arg_indirect_ref (addr);
4123 /* Aggregate arguments with alignment larger than 8 bytes start at
4124 the next even boundary. Integer and floating point arguments
4125 do so if they are larger than 8 bytes, whether or not they are
4126 also aligned larger than 8 bytes. */
4127 if ((TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == INTEGER_TYPE)
4128 ? int_size_in_bytes (type) > 8 : TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
4130 tree t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4131 build_int_cst (NULL_TREE, 2 * UNITS_PER_WORD - 1));
4132 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4133 build_int_cst (NULL_TREE, -2 * UNITS_PER_WORD));
4134 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4135 gimplify_and_add (t, pre_p);
4138 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4141 /* Return 1 if function return value returned in memory. Return 0 if it is
4145 ia64_return_in_memory (tree valtype, tree fntype ATTRIBUTE_UNUSED)
4147 enum machine_mode mode;
4148 enum machine_mode hfa_mode;
4149 HOST_WIDE_INT byte_size;
4151 mode = TYPE_MODE (valtype);
4152 byte_size = GET_MODE_SIZE (mode);
4153 if (mode == BLKmode)
4155 byte_size = int_size_in_bytes (valtype);
4160 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4162 hfa_mode = hfa_element_mode (valtype, 0);
4163 if (hfa_mode != VOIDmode)
4165 int hfa_size = GET_MODE_SIZE (hfa_mode);
4167 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
4172 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
4178 /* Return rtx for register that holds the function return value. */
4181 ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
4183 enum machine_mode mode;
4184 enum machine_mode hfa_mode;
4186 mode = TYPE_MODE (valtype);
4187 hfa_mode = hfa_element_mode (valtype, 0);
4189 if (hfa_mode != VOIDmode)
4197 hfa_size = GET_MODE_SIZE (hfa_mode);
4198 byte_size = ((mode == BLKmode)
4199 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
4201 for (i = 0; offset < byte_size; i++)
4203 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4204 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
4208 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4210 else if (FLOAT_TYPE_P (valtype) && mode != TFmode && mode != TCmode)
4211 return gen_rtx_REG (mode, FR_ARG_FIRST);
4214 bool need_parallel = false;
4216 /* In big-endian mode, we need to manage the layout of aggregates
4217 in the registers so that we get the bits properly aligned in
4218 the highpart of the registers. */
4219 if (BYTES_BIG_ENDIAN
4220 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
4221 need_parallel = true;
4223 /* Something like struct S { long double x; char a[0] } is not an
4224 HFA structure, and therefore doesn't go in fp registers. But
4225 the middle-end will give it XFmode anyway, and XFmode values
4226 don't normally fit in integer registers. So we need to smuggle
4227 the value inside a parallel. */
4228 else if (mode == XFmode || mode == XCmode || mode == RFmode)
4229 need_parallel = true;
4239 bytesize = int_size_in_bytes (valtype);
4240 /* An empty PARALLEL is invalid here, but the return value
4241 doesn't matter for empty structs. */
4243 return gen_rtx_REG (mode, GR_RET_FIRST);
4244 for (i = 0; offset < bytesize; i++)
4246 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
4247 gen_rtx_REG (DImode,
4250 offset += UNITS_PER_WORD;
4252 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
4255 return gen_rtx_REG (mode, GR_RET_FIRST);
4259 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4260 We need to emit DTP-relative relocations. */
4263 ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
4265 gcc_assert (size == 8);
4266 fputs ("\tdata8.ua\t@dtprel(", file);
4267 output_addr_const (file, x);
4271 /* Print a memory address as an operand to reference that memory location. */
4273 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4274 also call this from ia64_print_operand for memory addresses. */
4277 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
4278 rtx address ATTRIBUTE_UNUSED)
4282 /* Print an operand to an assembler instruction.
4283 C Swap and print a comparison operator.
4284 D Print an FP comparison operator.
4285 E Print 32 - constant, for SImode shifts as extract.
4286 e Print 64 - constant, for DImode rotates.
4287 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4288 a floating point register emitted normally.
4289 I Invert a predicate register by adding 1.
4290 J Select the proper predicate register for a condition.
4291 j Select the inverse predicate register for a condition.
4292 O Append .acq for volatile load.
4293 P Postincrement of a MEM.
4294 Q Append .rel for volatile store.
4295 S Shift amount for shladd instruction.
4296 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4297 for Intel assembler.
4298 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4299 for Intel assembler.
4300 r Print register name, or constant 0 as r0. HP compatibility for
4302 v Print vector constant value as an 8-byte integer value. */
4305 ia64_print_operand (FILE * file, rtx x, int code)
4312 /* Handled below. */
4317 enum rtx_code c = swap_condition (GET_CODE (x));
4318 fputs (GET_RTX_NAME (c), file);
4323 switch (GET_CODE (x))
4335 str = GET_RTX_NAME (GET_CODE (x));
4342 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
4346 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
4350 if (x == CONST0_RTX (GET_MODE (x)))
4351 str = reg_names [FR_REG (0)];
4352 else if (x == CONST1_RTX (GET_MODE (x)))
4353 str = reg_names [FR_REG (1)];
4356 gcc_assert (GET_CODE (x) == REG);
4357 str = reg_names [REGNO (x)];
4363 fputs (reg_names [REGNO (x) + 1], file);
4369 unsigned int regno = REGNO (XEXP (x, 0));
4370 if (GET_CODE (x) == EQ)
4374 fputs (reg_names [regno], file);
4379 if (MEM_VOLATILE_P (x))
4380 fputs(".acq", file);
4385 HOST_WIDE_INT value;
4387 switch (GET_CODE (XEXP (x, 0)))
4393 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
4394 if (GET_CODE (x) == CONST_INT)
4398 gcc_assert (GET_CODE (x) == REG);
4399 fprintf (file, ", %s", reg_names[REGNO (x)]);
4405 value = GET_MODE_SIZE (GET_MODE (x));
4409 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
4413 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
4418 if (MEM_VOLATILE_P (x))
4419 fputs(".rel", file);
4423 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4427 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4429 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
4435 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
4437 const char *prefix = "0x";
4438 if (INTVAL (x) & 0x80000000)
4440 fprintf (file, "0xffffffff");
4443 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
4449 /* If this operand is the constant zero, write it as register zero.
4450 Any register, zero, or CONST_INT value is OK here. */
4451 if (GET_CODE (x) == REG)
4452 fputs (reg_names[REGNO (x)], file);
4453 else if (x == CONST0_RTX (GET_MODE (x)))
4455 else if (GET_CODE (x) == CONST_INT)
4456 output_addr_const (file, x);
4458 output_operand_lossage ("invalid %%r value");
4462 gcc_assert (GET_CODE (x) == CONST_VECTOR);
4463 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
4470 /* For conditional branches, returns or calls, substitute
4471 sptk, dptk, dpnt, or spnt for %s. */
4472 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4475 int pred_val = INTVAL (XEXP (x, 0));
4477 /* Guess top and bottom 10% statically predicted. */
4478 if (pred_val < REG_BR_PROB_BASE / 50)
4480 else if (pred_val < REG_BR_PROB_BASE / 2)
4482 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4487 else if (GET_CODE (current_output_insn) == CALL_INSN)
4492 fputs (which, file);
4497 x = current_insn_predicate;
4500 unsigned int regno = REGNO (XEXP (x, 0));
4501 if (GET_CODE (x) == EQ)
4503 fprintf (file, "(%s) ", reg_names [regno]);
4508 output_operand_lossage ("ia64_print_operand: unknown code");
4512 switch (GET_CODE (x))
4514 /* This happens for the spill/restore instructions. */
4519 /* ... fall through ... */
4522 fputs (reg_names [REGNO (x)], file);
4527 rtx addr = XEXP (x, 0);
4528 if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
4529 addr = XEXP (addr, 0);
4530 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4535 output_addr_const (file, x);
4542 /* Compute a (partial) cost for rtx X. Return true if the complete
4543 cost has been computed, and false if subexpressions should be
4544 scanned. In either case, *TOTAL contains the cost result. */
4545 /* ??? This is incomplete. */
4548 ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
4556 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4559 if (CONST_OK_FOR_I (INTVAL (x)))
4561 else if (CONST_OK_FOR_J (INTVAL (x)))
4564 *total = COSTS_N_INSNS (1);
4567 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4570 *total = COSTS_N_INSNS (1);
4575 *total = COSTS_N_INSNS (1);
4581 *total = COSTS_N_INSNS (3);
4585 /* For multiplies wider than HImode, we have to go to the FPU,
4586 which normally involves copies. Plus there's the latency
4587 of the multiply itself, and the latency of the instructions to
4588 transfer integer regs to FP regs. */
4589 /* ??? Check for FP mode. */
4590 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4591 *total = COSTS_N_INSNS (10);
4593 *total = COSTS_N_INSNS (2);
4601 *total = COSTS_N_INSNS (1);
4608 /* We make divide expensive, so that divide-by-constant will be
4609 optimized to a multiply. */
4610 *total = COSTS_N_INSNS (60);
4618 /* Calculate the cost of moving data from a register in class FROM to
4619 one in class TO, using MODE. */
4622 ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
4625 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4626 if (to == ADDL_REGS)
4628 if (from == ADDL_REGS)
4631 /* All costs are symmetric, so reduce cases by putting the
4632 lower number class as the destination. */
4635 enum reg_class tmp = to;
4636 to = from, from = tmp;
4639 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4640 so that we get secondary memory reloads. Between FR_REGS,
4641 we have to make this at least as expensive as MEMORY_MOVE_COST
4642 to avoid spectacularly poor register class preferencing. */
4643 if (mode == XFmode || mode == RFmode)
4645 if (to != GR_REGS || from != GR_REGS)
4646 return MEMORY_MOVE_COST (mode, to, 0);
4654 /* Moving between PR registers takes two insns. */
4655 if (from == PR_REGS)
4657 /* Moving between PR and anything but GR is impossible. */
4658 if (from != GR_REGS)
4659 return MEMORY_MOVE_COST (mode, to, 0);
4663 /* Moving between BR and anything but GR is impossible. */
4664 if (from != GR_REGS && from != GR_AND_BR_REGS)
4665 return MEMORY_MOVE_COST (mode, to, 0);
4670 /* Moving between AR and anything but GR is impossible. */
4671 if (from != GR_REGS)
4672 return MEMORY_MOVE_COST (mode, to, 0);
4677 case GR_AND_FR_REGS:
4678 case GR_AND_BR_REGS:
4689 /* Implement PREFERRED_RELOAD_CLASS. Place additional restrictions on CLASS
4690 to use when copying X into that class. */
4693 ia64_preferred_reload_class (rtx x, enum reg_class class)
4698 /* Don't allow volatile mem reloads into floating point registers.
4699 This is defined to force reload to choose the r/m case instead
4700 of the f/f case when reloading (set (reg fX) (mem/v)). */
4701 if (MEM_P (x) && MEM_VOLATILE_P (x))
4704 /* Force all unrecognized constants into the constant pool. */
4722 /* This function returns the register class required for a secondary
4723 register when copying between one of the registers in CLASS, and X,
4724 using MODE. A return value of NO_REGS means that no secondary register
4728 ia64_secondary_reload_class (enum reg_class class,
4729 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
4733 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4734 regno = true_regnum (x);
4741 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4742 interaction. We end up with two pseudos with overlapping lifetimes
4743 both of which are equiv to the same constant, and both which need
4744 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4745 changes depending on the path length, which means the qty_first_reg
4746 check in make_regs_eqv can give different answers at different times.
4747 At some point I'll probably need a reload_indi pattern to handle
4750 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4751 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4752 non-general registers for good measure. */
4753 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4756 /* This is needed if a pseudo used as a call_operand gets spilled to a
4758 if (GET_CODE (x) == MEM)
4763 /* Need to go through general registers to get to other class regs. */
4764 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4767 /* This can happen when a paradoxical subreg is an operand to the
4769 /* ??? This shouldn't be necessary after instruction scheduling is
4770 enabled, because paradoxical subregs are not accepted by
4771 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4772 stop the paradoxical subreg stupidity in the *_operand functions
4774 if (GET_CODE (x) == MEM
4775 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4776 || GET_MODE (x) == QImode))
4779 /* This can happen because of the ior/and/etc patterns that accept FP
4780 registers as operands. If the third operand is a constant, then it
4781 needs to be reloaded into a FP register. */
4782 if (GET_CODE (x) == CONST_INT)
4785 /* This can happen because of register elimination in a muldi3 insn.
4786 E.g. `26107 * (unsigned long)&u'. */
4787 if (GET_CODE (x) == PLUS)
4792 /* ??? This happens if we cse/gcse a BImode value across a call,
4793 and the function has a nonlocal goto. This is because global
4794 does not allocate call crossing pseudos to hard registers when
4795 current_function_has_nonlocal_goto is true. This is relatively
4796 common for C++ programs that use exceptions. To reproduce,
4797 return NO_REGS and compile libstdc++. */
4798 if (GET_CODE (x) == MEM)
4801 /* This can happen when we take a BImode subreg of a DImode value,
4802 and that DImode value winds up in some non-GR register. */
4803 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4815 /* Emit text to declare externally defined variables and functions, because
4816 the Intel assembler does not support undefined externals. */
4819 ia64_asm_output_external (FILE *file, tree decl, const char *name)
4821 int save_referenced;
4823 /* GNU as does not need anything here, but the HP linker does need
4824 something for external functions. */
4828 || TREE_CODE (decl) != FUNCTION_DECL
4829 || strstr (name, "__builtin_") == name))
4832 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4833 the linker when we do this, so we need to be careful not to do this for
4834 builtin functions which have no library equivalent. Unfortunately, we
4835 can't tell here whether or not a function will actually be called by
4836 expand_expr, so we pull in library functions even if we may not need
4838 if (! strcmp (name, "__builtin_next_arg")
4839 || ! strcmp (name, "alloca")
4840 || ! strcmp (name, "__builtin_constant_p")
4841 || ! strcmp (name, "__builtin_args_info"))
4845 ia64_hpux_add_extern_decl (decl);
4848 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4850 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4851 if (TREE_CODE (decl) == FUNCTION_DECL)
4852 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4853 (*targetm.asm_out.globalize_label) (file, name);
4854 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4858 /* Parse the -mfixed-range= option string. */
4861 fix_range (const char *const_str)
4864 char *str, *dash, *comma;
4866 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4867 REG2 are either register names or register numbers. The effect
4868 of this option is to mark the registers in the range from REG1 to
4869 REG2 as ``fixed'' so they won't be used by the compiler. This is
4870 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4872 i = strlen (const_str);
4873 str = (char *) alloca (i + 1);
4874 memcpy (str, const_str, i + 1);
4878 dash = strchr (str, '-');
4881 warning (0, "value of -mfixed-range must have form REG1-REG2");
4886 comma = strchr (dash + 1, ',');
4890 first = decode_reg_name (str);
4893 warning (0, "unknown register name: %s", str);
4897 last = decode_reg_name (dash + 1);
4900 warning (0, "unknown register name: %s", dash + 1);
4908 warning (0, "%s-%s is an empty range", str, dash + 1);
4912 for (i = first; i <= last; ++i)
4913 fixed_regs[i] = call_used_regs[i] = 1;
4923 /* Implement TARGET_HANDLE_OPTION. */
4926 ia64_handle_option (size_t code, const char *arg, int value)
4930 case OPT_mfixed_range_:
4934 case OPT_mtls_size_:
4935 if (value != 14 && value != 22 && value != 64)
4936 error ("bad value %<%s%> for -mtls-size= switch", arg);
4943 const char *name; /* processor name or nickname. */
4944 enum processor_type processor;
4946 const processor_alias_table[] =
4948 {"itanium", PROCESSOR_ITANIUM},
4949 {"itanium1", PROCESSOR_ITANIUM},
4950 {"merced", PROCESSOR_ITANIUM},
4951 {"itanium2", PROCESSOR_ITANIUM2},
4952 {"mckinley", PROCESSOR_ITANIUM2},
4954 int const pta_size = ARRAY_SIZE (processor_alias_table);
4957 for (i = 0; i < pta_size; i++)
4958 if (!strcmp (arg, processor_alias_table[i].name))
4960 ia64_tune = processor_alias_table[i].processor;
4964 error ("bad value %<%s%> for -mtune= switch", arg);
4973 /* Implement OVERRIDE_OPTIONS. */
4976 ia64_override_options (void)
4978 if (TARGET_AUTO_PIC)
4979 target_flags |= MASK_CONST_GP;
4981 if (TARGET_INLINE_SQRT == INL_MIN_LAT)
4983 warning (0, "not yet implemented: latency-optimized inline square root");
4984 TARGET_INLINE_SQRT = INL_MAX_THR;
4987 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4988 flag_schedule_insns_after_reload = 0;
4990 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4992 init_machine_status = ia64_init_machine_status;
4995 static struct machine_function *
4996 ia64_init_machine_status (void)
4998 return ggc_alloc_cleared (sizeof (struct machine_function));
5001 static enum attr_itanium_class ia64_safe_itanium_class (rtx);
5002 static enum attr_type ia64_safe_type (rtx);
5004 static enum attr_itanium_class
5005 ia64_safe_itanium_class (rtx insn)
5007 if (recog_memoized (insn) >= 0)
5008 return get_attr_itanium_class (insn);
5010 return ITANIUM_CLASS_UNKNOWN;
5013 static enum attr_type
5014 ia64_safe_type (rtx insn)
5016 if (recog_memoized (insn) >= 0)
5017 return get_attr_type (insn);
5019 return TYPE_UNKNOWN;
5022 /* The following collection of routines emit instruction group stop bits as
5023 necessary to avoid dependencies. */
5025 /* Need to track some additional registers as far as serialization is
5026 concerned so we can properly handle br.call and br.ret. We could
5027 make these registers visible to gcc, but since these registers are
5028 never explicitly used in gcc generated code, it seems wasteful to
5029 do so (plus it would make the call and return patterns needlessly
5031 #define REG_RP (BR_REG (0))
5032 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
5033 /* This is used for volatile asms which may require a stop bit immediately
5034 before and after them. */
5035 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
5036 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
5037 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
5039 /* For each register, we keep track of how it has been written in the
5040 current instruction group.
5042 If a register is written unconditionally (no qualifying predicate),
5043 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
5045 If a register is written if its qualifying predicate P is true, we
5046 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
5047 may be written again by the complement of P (P^1) and when this happens,
5048 WRITE_COUNT gets set to 2.
5050 The result of this is that whenever an insn attempts to write a register
5051 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
5053 If a predicate register is written by a floating-point insn, we set
5054 WRITTEN_BY_FP to true.
5056 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
5057 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
5059 struct reg_write_state
5061 unsigned int write_count : 2;
5062 unsigned int first_pred : 16;
5063 unsigned int written_by_fp : 1;
5064 unsigned int written_by_and : 1;
5065 unsigned int written_by_or : 1;
5068 /* Cumulative info for the current instruction group. */
5069 struct reg_write_state rws_sum[NUM_REGS];
5070 /* Info for the current instruction. This gets copied to rws_sum after a
5071 stop bit is emitted. */
5072 struct reg_write_state rws_insn[NUM_REGS];
5074 /* Indicates whether this is the first instruction after a stop bit,
5075 in which case we don't need another stop bit. Without this,
5076 ia64_variable_issue will die when scheduling an alloc. */
5077 static int first_instruction;
5079 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
5080 RTL for one instruction. */
5083 unsigned int is_write : 1; /* Is register being written? */
5084 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
5085 unsigned int is_branch : 1; /* Is register used as part of a branch? */
5086 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
5087 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
5088 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
5091 static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
5092 static int rws_access_regno (int, struct reg_flags, int);
5093 static int rws_access_reg (rtx, struct reg_flags, int);
5094 static void update_set_flags (rtx, struct reg_flags *);
5095 static int set_src_needs_barrier (rtx, struct reg_flags, int);
5096 static int rtx_needs_barrier (rtx, struct reg_flags, int);
5097 static void init_insn_group_barriers (void);
5098 static int group_barrier_needed (rtx);
5099 static int safe_group_barrier_needed (rtx);
5101 /* Update *RWS for REGNO, which is being written by the current instruction,
5102 with predicate PRED, and associated register flags in FLAGS. */
5105 rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
5108 rws[regno].write_count++;
5110 rws[regno].write_count = 2;
5111 rws[regno].written_by_fp |= flags.is_fp;
5112 /* ??? Not tracking and/or across differing predicates. */
5113 rws[regno].written_by_and = flags.is_and;
5114 rws[regno].written_by_or = flags.is_or;
5115 rws[regno].first_pred = pred;
5118 /* Handle an access to register REGNO of type FLAGS using predicate register
5119 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
5120 a dependency with an earlier instruction in the same group. */
5123 rws_access_regno (int regno, struct reg_flags flags, int pred)
5125 int need_barrier = 0;
5127 gcc_assert (regno < NUM_REGS);
5129 if (! PR_REGNO_P (regno))
5130 flags.is_and = flags.is_or = 0;
5136 /* One insn writes same reg multiple times? */
5137 gcc_assert (!rws_insn[regno].write_count);
5139 /* Update info for current instruction. */
5140 rws_update (rws_insn, regno, flags, pred);
5141 write_count = rws_sum[regno].write_count;
5143 switch (write_count)
5146 /* The register has not been written yet. */
5147 rws_update (rws_sum, regno, flags, pred);
5151 /* The register has been written via a predicate. If this is
5152 not a complementary predicate, then we need a barrier. */
5153 /* ??? This assumes that P and P+1 are always complementary
5154 predicates for P even. */
5155 if (flags.is_and && rws_sum[regno].written_by_and)
5157 else if (flags.is_or && rws_sum[regno].written_by_or)
5159 else if ((rws_sum[regno].first_pred ^ 1) != pred)
5161 rws_update (rws_sum, regno, flags, pred);
5165 /* The register has been unconditionally written already. We
5167 if (flags.is_and && rws_sum[regno].written_by_and)
5169 else if (flags.is_or && rws_sum[regno].written_by_or)
5173 rws_sum[regno].written_by_and = flags.is_and;
5174 rws_sum[regno].written_by_or = flags.is_or;
5183 if (flags.is_branch)
5185 /* Branches have several RAW exceptions that allow to avoid
5188 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
5189 /* RAW dependencies on branch regs are permissible as long
5190 as the writer is a non-branch instruction. Since we
5191 never generate code that uses a branch register written
5192 by a branch instruction, handling this case is
5196 if (REGNO_REG_CLASS (regno) == PR_REGS
5197 && ! rws_sum[regno].written_by_fp)
5198 /* The predicates of a branch are available within the
5199 same insn group as long as the predicate was written by
5200 something other than a floating-point instruction. */
5204 if (flags.is_and && rws_sum[regno].written_by_and)
5206 if (flags.is_or && rws_sum[regno].written_by_or)
5209 switch (rws_sum[regno].write_count)
5212 /* The register has not been written yet. */
5216 /* The register has been written via a predicate. If this is
5217 not a complementary predicate, then we need a barrier. */
5218 /* ??? This assumes that P and P+1 are always complementary
5219 predicates for P even. */
5220 if ((rws_sum[regno].first_pred ^ 1) != pred)
5225 /* The register has been unconditionally written already. We
5235 return need_barrier;
5239 rws_access_reg (rtx reg, struct reg_flags flags, int pred)
5241 int regno = REGNO (reg);
5242 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
5245 return rws_access_regno (regno, flags, pred);
5248 int need_barrier = 0;
5250 need_barrier |= rws_access_regno (regno + n, flags, pred);
5251 return need_barrier;
5255 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5256 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5259 update_set_flags (rtx x, struct reg_flags *pflags)
5261 rtx src = SET_SRC (x);
5263 switch (GET_CODE (src))
5269 /* There are three cases here:
5270 (1) The destination is (pc), in which case this is a branch,
5271 nothing here applies.
5272 (2) The destination is ar.lc, in which case this is a
5273 doloop_end_internal,
5274 (3) The destination is an fp register, in which case this is
5275 an fselect instruction.
5276 In all cases, nothing we do in this function applies. */
5280 if (COMPARISON_P (src)
5281 && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
5282 /* Set pflags->is_fp to 1 so that we know we're dealing
5283 with a floating point comparison when processing the
5284 destination of the SET. */
5287 /* Discover if this is a parallel comparison. We only handle
5288 and.orcm and or.andcm at present, since we must retain a
5289 strict inverse on the predicate pair. */
5290 else if (GET_CODE (src) == AND)
5292 else if (GET_CODE (src) == IOR)
5299 /* Subroutine of rtx_needs_barrier; this function determines whether the
5300 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5301 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5305 set_src_needs_barrier (rtx x, struct reg_flags flags, int pred)
5307 int need_barrier = 0;
5309 rtx src = SET_SRC (x);
5311 if (GET_CODE (src) == CALL)
5312 /* We don't need to worry about the result registers that
5313 get written by subroutine call. */
5314 return rtx_needs_barrier (src, flags, pred);
5315 else if (SET_DEST (x) == pc_rtx)
5317 /* X is a conditional branch. */
5318 /* ??? This seems redundant, as the caller sets this bit for
5320 flags.is_branch = 1;
5321 return rtx_needs_barrier (src, flags, pred);
5324 need_barrier = rtx_needs_barrier (src, flags, pred);
5327 if (GET_CODE (dst) == ZERO_EXTRACT)
5329 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
5330 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
5331 dst = XEXP (dst, 0);
5333 return need_barrier;
5336 /* Handle an access to rtx X of type FLAGS using predicate register
5337 PRED. Return 1 if this access creates a dependency with an earlier
5338 instruction in the same group. */
5341 rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
5344 int is_complemented = 0;
5345 int need_barrier = 0;
5346 const char *format_ptr;
5347 struct reg_flags new_flags;
5355 switch (GET_CODE (x))
5358 update_set_flags (x, &new_flags);
5359 need_barrier = set_src_needs_barrier (x, new_flags, pred);
5360 if (GET_CODE (SET_SRC (x)) != CALL)
5362 new_flags.is_write = 1;
5363 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
5368 new_flags.is_write = 0;
5369 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5371 /* Avoid multiple register writes, in case this is a pattern with
5372 multiple CALL rtx. This avoids a failure in rws_access_reg. */
5373 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
5375 new_flags.is_write = 1;
5376 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
5377 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
5378 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5383 /* X is a predicated instruction. */
5385 cond = COND_EXEC_TEST (x);
5387 need_barrier = rtx_needs_barrier (cond, flags, 0);
5389 if (GET_CODE (cond) == EQ)
5390 is_complemented = 1;
5391 cond = XEXP (cond, 0);
5392 gcc_assert (GET_CODE (cond) == REG
5393 && REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
5394 pred = REGNO (cond);
5395 if (is_complemented)
5398 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
5399 return need_barrier;
5403 /* Clobber & use are for earlier compiler-phases only. */
5408 /* We always emit stop bits for traditional asms. We emit stop bits
5409 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5410 if (GET_CODE (x) != ASM_OPERANDS
5411 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5413 /* Avoid writing the register multiple times if we have multiple
5414 asm outputs. This avoids a failure in rws_access_reg. */
5415 if (! rws_insn[REG_VOLATILE].write_count)
5417 new_flags.is_write = 1;
5418 rws_access_regno (REG_VOLATILE, new_flags, pred);
5423 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5424 We cannot just fall through here since then we would be confused
5425 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5426 traditional asms unlike their normal usage. */
5428 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5429 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5434 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5436 rtx pat = XVECEXP (x, 0, i);
5437 switch (GET_CODE (pat))
5440 update_set_flags (pat, &new_flags);
5441 need_barrier |= set_src_needs_barrier (pat, new_flags, pred);
5447 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5458 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5460 rtx pat = XVECEXP (x, 0, i);
5461 if (GET_CODE (pat) == SET)
5463 if (GET_CODE (SET_SRC (pat)) != CALL)
5465 new_flags.is_write = 1;
5466 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5470 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5471 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5476 need_barrier |= rtx_needs_barrier (SUBREG_REG (x), flags, pred);
5479 if (REGNO (x) == AR_UNAT_REGNUM)
5481 for (i = 0; i < 64; ++i)
5482 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5485 need_barrier = rws_access_reg (x, flags, pred);
5489 /* Find the regs used in memory address computation. */
5490 new_flags.is_write = 0;
5491 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5494 case CONST_INT: case CONST_DOUBLE: case CONST_VECTOR:
5495 case SYMBOL_REF: case LABEL_REF: case CONST:
5498 /* Operators with side-effects. */
5499 case POST_INC: case POST_DEC:
5500 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5502 new_flags.is_write = 0;
5503 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5504 new_flags.is_write = 1;
5505 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5509 gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
5511 new_flags.is_write = 0;
5512 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5513 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5514 new_flags.is_write = 1;
5515 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5518 /* Handle common unary and binary ops for efficiency. */
5519 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5520 case MOD: case UDIV: case UMOD: case AND: case IOR:
5521 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5522 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5523 case NE: case EQ: case GE: case GT: case LE:
5524 case LT: case GEU: case GTU: case LEU: case LTU:
5525 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5526 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5529 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5530 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5531 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5532 case SQRT: case FFS: case POPCOUNT:
5533 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5537 /* VEC_SELECT's second argument is a PARALLEL with integers that
5538 describe the elements selected. On ia64, those integers are
5539 always constants. Avoid walking the PARALLEL so that we don't
5540 get confused with "normal" parallels and then die. */
5541 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5545 switch (XINT (x, 1))
5547 case UNSPEC_LTOFF_DTPMOD:
5548 case UNSPEC_LTOFF_DTPREL:
5550 case UNSPEC_LTOFF_TPREL:
5552 case UNSPEC_PRED_REL_MUTEX:
5553 case UNSPEC_PIC_CALL:
5555 case UNSPEC_FETCHADD_ACQ:
5556 case UNSPEC_BSP_VALUE:
5557 case UNSPEC_FLUSHRS:
5558 case UNSPEC_BUNDLE_SELECTOR:
5561 case UNSPEC_GR_SPILL:
5562 case UNSPEC_GR_RESTORE:
5564 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5565 HOST_WIDE_INT bit = (offset >> 3) & 63;
5567 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5568 new_flags.is_write = (XINT (x, 1) == UNSPEC_GR_SPILL);
5569 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5574 case UNSPEC_FR_SPILL:
5575 case UNSPEC_FR_RESTORE:
5576 case UNSPEC_GETF_EXP:
5577 case UNSPEC_SETF_EXP:
5579 case UNSPEC_FR_SQRT_RECIP_APPROX:
5580 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5583 case UNSPEC_FR_RECIP_APPROX:
5585 case UNSPEC_COPYSIGN:
5586 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5587 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5590 case UNSPEC_CMPXCHG_ACQ:
5591 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5592 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5600 case UNSPEC_VOLATILE:
5601 switch (XINT (x, 1))
5604 /* Alloc must always be the first instruction of a group.
5605 We force this by always returning true. */
5606 /* ??? We might get better scheduling if we explicitly check for
5607 input/local/output register dependencies, and modify the
5608 scheduler so that alloc is always reordered to the start of
5609 the current group. We could then eliminate all of the
5610 first_instruction code. */
5611 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5613 new_flags.is_write = 1;
5614 rws_access_regno (REG_AR_CFM, new_flags, pred);
5617 case UNSPECV_SET_BSP:
5621 case UNSPECV_BLOCKAGE:
5622 case UNSPECV_INSN_GROUP_BARRIER:
5624 case UNSPECV_PSAC_ALL:
5625 case UNSPECV_PSAC_NORMAL:
5634 new_flags.is_write = 0;
5635 need_barrier = rws_access_regno (REG_RP, flags, pred);
5636 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5638 new_flags.is_write = 1;
5639 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5640 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5644 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5645 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5646 switch (format_ptr[i])
5648 case '0': /* unused field */
5649 case 'i': /* integer */
5650 case 'n': /* note */
5651 case 'w': /* wide integer */
5652 case 's': /* pointer to string */
5653 case 'S': /* optional pointer to string */
5657 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5662 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5663 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5672 return need_barrier;
5675 /* Clear out the state for group_barrier_needed at the start of a
5676 sequence of insns. */
5679 init_insn_group_barriers (void)
5681 memset (rws_sum, 0, sizeof (rws_sum));
5682 first_instruction = 1;
5685 /* Given the current state, determine whether a group barrier (a stop bit) is
5686 necessary before INSN. Return nonzero if so. This modifies the state to
5687 include the effects of INSN as a side-effect. */
5690 group_barrier_needed (rtx insn)
5693 int need_barrier = 0;
5694 struct reg_flags flags;
5696 memset (&flags, 0, sizeof (flags));
5697 switch (GET_CODE (insn))
5703 /* A barrier doesn't imply an instruction group boundary. */
5707 memset (rws_insn, 0, sizeof (rws_insn));
5711 flags.is_branch = 1;
5712 flags.is_sibcall = SIBLING_CALL_P (insn);
5713 memset (rws_insn, 0, sizeof (rws_insn));
5715 /* Don't bundle a call following another call. */
5716 if ((pat = prev_active_insn (insn))
5717 && GET_CODE (pat) == CALL_INSN)
5723 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5727 flags.is_branch = 1;
5729 /* Don't bundle a jump following a call. */
5730 if ((pat = prev_active_insn (insn))
5731 && GET_CODE (pat) == CALL_INSN)
5739 if (GET_CODE (PATTERN (insn)) == USE
5740 || GET_CODE (PATTERN (insn)) == CLOBBER)
5741 /* Don't care about USE and CLOBBER "insns"---those are used to
5742 indicate to the optimizer that it shouldn't get rid of
5743 certain operations. */
5746 pat = PATTERN (insn);
5748 /* Ug. Hack hacks hacked elsewhere. */
5749 switch (recog_memoized (insn))
5751 /* We play dependency tricks with the epilogue in order
5752 to get proper schedules. Undo this for dv analysis. */
5753 case CODE_FOR_epilogue_deallocate_stack:
5754 case CODE_FOR_prologue_allocate_stack:
5755 pat = XVECEXP (pat, 0, 0);
5758 /* The pattern we use for br.cloop confuses the code above.
5759 The second element of the vector is representative. */
5760 case CODE_FOR_doloop_end_internal:
5761 pat = XVECEXP (pat, 0, 1);
5764 /* Doesn't generate code. */
5765 case CODE_FOR_pred_rel_mutex:
5766 case CODE_FOR_prologue_use:
5773 memset (rws_insn, 0, sizeof (rws_insn));
5774 need_barrier = rtx_needs_barrier (pat, flags, 0);
5776 /* Check to see if the previous instruction was a volatile
5779 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5786 if (first_instruction && INSN_P (insn)
5787 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5788 && GET_CODE (PATTERN (insn)) != USE
5789 && GET_CODE (PATTERN (insn)) != CLOBBER)
5792 first_instruction = 0;
5795 return need_barrier;
5798 /* Like group_barrier_needed, but do not clobber the current state. */
5801 safe_group_barrier_needed (rtx insn)
5803 struct reg_write_state rws_saved[NUM_REGS];
5804 int saved_first_instruction;
5807 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5808 saved_first_instruction = first_instruction;
5810 t = group_barrier_needed (insn);
5812 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5813 first_instruction = saved_first_instruction;
5818 /* Scan the current function and insert stop bits as necessary to
5819 eliminate dependencies. This function assumes that a final
5820 instruction scheduling pass has been run which has already
5821 inserted most of the necessary stop bits. This function only
5822 inserts new ones at basic block boundaries, since these are
5823 invisible to the scheduler. */
5826 emit_insn_group_barriers (FILE *dump)
5830 int insns_since_last_label = 0;
5832 init_insn_group_barriers ();
5834 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5836 if (GET_CODE (insn) == CODE_LABEL)
5838 if (insns_since_last_label)
5840 insns_since_last_label = 0;
5842 else if (GET_CODE (insn) == NOTE
5843 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5845 if (insns_since_last_label)
5847 insns_since_last_label = 0;
5849 else if (GET_CODE (insn) == INSN
5850 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5851 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5853 init_insn_group_barriers ();
5856 else if (INSN_P (insn))
5858 insns_since_last_label = 1;
5860 if (group_barrier_needed (insn))
5865 fprintf (dump, "Emitting stop before label %d\n",
5866 INSN_UID (last_label));
5867 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5870 init_insn_group_barriers ();
5878 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5879 This function has to emit all necessary group barriers. */
5882 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
5886 init_insn_group_barriers ();
5888 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5890 if (GET_CODE (insn) == BARRIER)
5892 rtx last = prev_active_insn (insn);
5896 if (GET_CODE (last) == JUMP_INSN
5897 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5898 last = prev_active_insn (last);
5899 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5900 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5902 init_insn_group_barriers ();
5904 else if (INSN_P (insn))
5906 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5907 init_insn_group_barriers ();
5908 else if (group_barrier_needed (insn))
5910 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5911 init_insn_group_barriers ();
5912 group_barrier_needed (insn);
5920 /* Instruction scheduling support. */
5922 #define NR_BUNDLES 10
5924 /* A list of names of all available bundles. */
5926 static const char *bundle_name [NR_BUNDLES] =
5932 #if NR_BUNDLES == 10
5942 /* Nonzero if we should insert stop bits into the schedule. */
5944 int ia64_final_schedule = 0;
5946 /* Codes of the corresponding queried units: */
5948 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5949 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5951 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5952 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5954 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5956 /* The following variable value is an insn group barrier. */
5958 static rtx dfa_stop_insn;
5960 /* The following variable value is the last issued insn. */
5962 static rtx last_scheduled_insn;
5964 /* The following variable value is size of the DFA state. */
5966 static size_t dfa_state_size;
5968 /* The following variable value is pointer to a DFA state used as
5969 temporary variable. */
5971 static state_t temp_dfa_state = NULL;
5973 /* The following variable value is DFA state after issuing the last
5976 static state_t prev_cycle_state = NULL;
5978 /* The following array element values are TRUE if the corresponding
5979 insn requires to add stop bits before it. */
5981 static char *stops_p;
5983 /* The following variable is used to set up the mentioned above array. */
5985 static int stop_before_p = 0;
5987 /* The following variable value is length of the arrays `clocks' and
5990 static int clocks_length;
5992 /* The following array element values are cycles on which the
5993 corresponding insn will be issued. The array is used only for
5998 /* The following array element values are numbers of cycles should be
5999 added to improve insn scheduling for MM_insns for Itanium1. */
6001 static int *add_cycles;
6003 static rtx ia64_single_set (rtx);
6004 static void ia64_emit_insn_before (rtx, rtx);
6006 /* Map a bundle number to its pseudo-op. */
6009 get_bundle_name (int b)
6011 return bundle_name[b];
6015 /* Return the maximum number of instructions a cpu can issue. */
6018 ia64_issue_rate (void)
6023 /* Helper function - like single_set, but look inside COND_EXEC. */
6026 ia64_single_set (rtx insn)
6028 rtx x = PATTERN (insn), ret;
6029 if (GET_CODE (x) == COND_EXEC)
6030 x = COND_EXEC_CODE (x);
6031 if (GET_CODE (x) == SET)
6034 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6035 Although they are not classical single set, the second set is there just
6036 to protect it from moving past FP-relative stack accesses. */
6037 switch (recog_memoized (insn))
6039 case CODE_FOR_prologue_allocate_stack:
6040 case CODE_FOR_epilogue_deallocate_stack:
6041 ret = XVECEXP (x, 0, 0);
6045 ret = single_set_2 (insn, x);
6052 /* Adjust the cost of a scheduling dependency. Return the new cost of
6053 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6056 ia64_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
6058 enum attr_itanium_class dep_class;
6059 enum attr_itanium_class insn_class;
6061 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
6064 insn_class = ia64_safe_itanium_class (insn);
6065 dep_class = ia64_safe_itanium_class (dep_insn);
6066 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
6067 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
6073 /* Like emit_insn_before, but skip cycle_display notes.
6074 ??? When cycle display notes are implemented, update this. */
6077 ia64_emit_insn_before (rtx insn, rtx before)
6079 emit_insn_before (insn, before);
6082 /* The following function marks insns who produce addresses for load
6083 and store insns. Such insns will be placed into M slots because it
6084 decrease latency time for Itanium1 (see function
6085 `ia64_produce_address_p' and the DFA descriptions). */
6088 ia64_dependencies_evaluation_hook (rtx head, rtx tail)
6090 rtx insn, link, next, next_tail;
6092 /* Before reload, which_alternative is not set, which means that
6093 ia64_safe_itanium_class will produce wrong results for (at least)
6094 move instructions. */
6095 if (!reload_completed)
6098 next_tail = NEXT_INSN (tail);
6099 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6102 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
6104 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
6106 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
6108 if (REG_NOTE_KIND (link) != REG_DEP_TRUE)
6110 next = XEXP (link, 0);
6111 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
6112 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
6113 && ia64_st_address_bypass_p (insn, next))
6115 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
6116 || ia64_safe_itanium_class (next)
6117 == ITANIUM_CLASS_FLD)
6118 && ia64_ld_address_bypass_p (insn, next))
6121 insn->call = link != 0;
6125 /* We're beginning a new block. Initialize data structures as necessary. */
6128 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
6129 int sched_verbose ATTRIBUTE_UNUSED,
6130 int max_ready ATTRIBUTE_UNUSED)
6132 #ifdef ENABLE_CHECKING
6135 if (reload_completed)
6136 for (insn = NEXT_INSN (current_sched_info->prev_head);
6137 insn != current_sched_info->next_tail;
6138 insn = NEXT_INSN (insn))
6139 gcc_assert (!SCHED_GROUP_P (insn));
6141 last_scheduled_insn = NULL_RTX;
6142 init_insn_group_barriers ();
6145 /* We are about to being issuing insns for this clock cycle.
6146 Override the default sort algorithm to better slot instructions. */
6149 ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
6150 int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
6154 int n_ready = *pn_ready;
6155 rtx *e_ready = ready + n_ready;
6159 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
6161 if (reorder_type == 0)
6163 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6165 for (insnp = ready; insnp < e_ready; insnp++)
6166 if (insnp < e_ready)
6169 enum attr_type t = ia64_safe_type (insn);
6170 if (t == TYPE_UNKNOWN)
6172 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6173 || asm_noperands (PATTERN (insn)) >= 0)
6175 rtx lowest = ready[n_asms];
6176 ready[n_asms] = insn;
6182 rtx highest = ready[n_ready - 1];
6183 ready[n_ready - 1] = insn;
6190 if (n_asms < n_ready)
6192 /* Some normal insns to process. Skip the asms. */
6196 else if (n_ready > 0)
6200 if (ia64_final_schedule)
6203 int nr_need_stop = 0;
6205 for (insnp = ready; insnp < e_ready; insnp++)
6206 if (safe_group_barrier_needed (*insnp))
6209 if (reorder_type == 1 && n_ready == nr_need_stop)
6211 if (reorder_type == 0)
6214 /* Move down everything that needs a stop bit, preserving
6216 while (insnp-- > ready + deleted)
6217 while (insnp >= ready + deleted)
6220 if (! safe_group_barrier_needed (insn))
6222 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
6233 /* We are about to being issuing insns for this clock cycle. Override
6234 the default sort algorithm to better slot instructions. */
6237 ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
6240 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
6241 pn_ready, clock_var, 0);
6244 /* Like ia64_sched_reorder, but called after issuing each insn.
6245 Override the default sort algorithm to better slot instructions. */
6248 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
6249 int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
6250 int *pn_ready, int clock_var)
6252 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
6253 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
6254 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
6258 /* We are about to issue INSN. Return the number of insns left on the
6259 ready queue that can be issued this cycle. */
6262 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
6263 int sched_verbose ATTRIBUTE_UNUSED,
6264 rtx insn ATTRIBUTE_UNUSED,
6265 int can_issue_more ATTRIBUTE_UNUSED)
6267 last_scheduled_insn = insn;
6268 memcpy (prev_cycle_state, curr_state, dfa_state_size);
6269 if (reload_completed)
6271 int needed = group_barrier_needed (insn);
6273 gcc_assert (!needed);
6274 if (GET_CODE (insn) == CALL_INSN)
6275 init_insn_group_barriers ();
6276 stops_p [INSN_UID (insn)] = stop_before_p;
6282 /* We are choosing insn from the ready queue. Return nonzero if INSN
6286 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
6288 gcc_assert (insn && INSN_P (insn));
6289 return (!reload_completed
6290 || !safe_group_barrier_needed (insn));
6293 /* The following variable value is pseudo-insn used by the DFA insn
6294 scheduler to change the DFA state when the simulated clock is
6297 static rtx dfa_pre_cycle_insn;
6299 /* We are about to being issuing INSN. Return nonzero if we cannot
6300 issue it on given cycle CLOCK and return zero if we should not sort
6301 the ready queue on the next clock start. */
6304 ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
6305 int clock, int *sort_p)
6307 int setup_clocks_p = FALSE;
6309 gcc_assert (insn && INSN_P (insn));
6310 if ((reload_completed && safe_group_barrier_needed (insn))
6311 || (last_scheduled_insn
6312 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6313 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6314 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6316 init_insn_group_barriers ();
6317 if (verbose && dump)
6318 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6319 last_clock == clock ? " + cycle advance" : "");
6321 if (last_clock == clock)
6323 state_transition (curr_state, dfa_stop_insn);
6324 if (TARGET_EARLY_STOP_BITS)
6325 *sort_p = (last_scheduled_insn == NULL_RTX
6326 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6331 else if (reload_completed)
6332 setup_clocks_p = TRUE;
6333 if (GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6334 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)
6335 state_reset (curr_state);
6338 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6339 state_transition (curr_state, dfa_stop_insn);
6340 state_transition (curr_state, dfa_pre_cycle_insn);
6341 state_transition (curr_state, NULL);
6344 else if (reload_completed)
6345 setup_clocks_p = TRUE;
6346 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM
6347 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6348 && asm_noperands (PATTERN (insn)) < 0)
6350 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6352 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6357 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6358 if (REG_NOTE_KIND (link) == 0)
6360 enum attr_itanium_class dep_class;
6361 rtx dep_insn = XEXP (link, 0);
6363 dep_class = ia64_safe_itanium_class (dep_insn);
6364 if ((dep_class == ITANIUM_CLASS_MMMUL
6365 || dep_class == ITANIUM_CLASS_MMSHF)
6366 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6368 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6369 d = last_clock - clocks [INSN_UID (dep_insn)];
6372 add_cycles [INSN_UID (insn)] = 3 - d;
6380 /* The following page contains abstract data `bundle states' which are
6381 used for bundling insns (inserting nops and template generation). */
6383 /* The following describes state of insn bundling. */
6387 /* Unique bundle state number to identify them in the debugging
6390 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6391 /* number nops before and after the insn */
6392 short before_nops_num, after_nops_num;
6393 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6395 int cost; /* cost of the state in cycles */
6396 int accumulated_insns_num; /* number of all previous insns including
6397 nops. L is considered as 2 insns */
6398 int branch_deviation; /* deviation of previous branches from 3rd slots */
6399 struct bundle_state *next; /* next state with the same insn_num */
6400 struct bundle_state *originator; /* originator (previous insn state) */
6401 /* All bundle states are in the following chain. */
6402 struct bundle_state *allocated_states_chain;
6403 /* The DFA State after issuing the insn and the nops. */
6407 /* The following is map insn number to the corresponding bundle state. */
6409 static struct bundle_state **index_to_bundle_states;
6411 /* The unique number of next bundle state. */
6413 static int bundle_states_num;
6415 /* All allocated bundle states are in the following chain. */
6417 static struct bundle_state *allocated_bundle_states_chain;
6419 /* All allocated but not used bundle states are in the following
6422 static struct bundle_state *free_bundle_state_chain;
6425 /* The following function returns a free bundle state. */
6427 static struct bundle_state *
6428 get_free_bundle_state (void)
6430 struct bundle_state *result;
6432 if (free_bundle_state_chain != NULL)
6434 result = free_bundle_state_chain;
6435 free_bundle_state_chain = result->next;
6439 result = xmalloc (sizeof (struct bundle_state));
6440 result->dfa_state = xmalloc (dfa_state_size);
6441 result->allocated_states_chain = allocated_bundle_states_chain;
6442 allocated_bundle_states_chain = result;
6444 result->unique_num = bundle_states_num++;
6449 /* The following function frees given bundle state. */
6452 free_bundle_state (struct bundle_state *state)
6454 state->next = free_bundle_state_chain;
6455 free_bundle_state_chain = state;
6458 /* Start work with abstract data `bundle states'. */
6461 initiate_bundle_states (void)
6463 bundle_states_num = 0;
6464 free_bundle_state_chain = NULL;
6465 allocated_bundle_states_chain = NULL;
6468 /* Finish work with abstract data `bundle states'. */
6471 finish_bundle_states (void)
6473 struct bundle_state *curr_state, *next_state;
6475 for (curr_state = allocated_bundle_states_chain;
6477 curr_state = next_state)
6479 next_state = curr_state->allocated_states_chain;
6480 free (curr_state->dfa_state);
6485 /* Hash table of the bundle states. The key is dfa_state and insn_num
6486 of the bundle states. */
6488 static htab_t bundle_state_table;
6490 /* The function returns hash of BUNDLE_STATE. */
6493 bundle_state_hash (const void *bundle_state)
6495 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6498 for (result = i = 0; i < dfa_state_size; i++)
6499 result += (((unsigned char *) state->dfa_state) [i]
6500 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6501 return result + state->insn_num;
6504 /* The function returns nonzero if the bundle state keys are equal. */
6507 bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
6509 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6510 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6512 return (state1->insn_num == state2->insn_num
6513 && memcmp (state1->dfa_state, state2->dfa_state,
6514 dfa_state_size) == 0);
6517 /* The function inserts the BUNDLE_STATE into the hash table. The
6518 function returns nonzero if the bundle has been inserted into the
6519 table. The table contains the best bundle state with given key. */
6522 insert_bundle_state (struct bundle_state *bundle_state)
6526 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6527 if (*entry_ptr == NULL)
6529 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6530 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6531 *entry_ptr = (void *) bundle_state;
6534 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6535 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6536 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6537 > bundle_state->accumulated_insns_num
6538 || (((struct bundle_state *)
6539 *entry_ptr)->accumulated_insns_num
6540 == bundle_state->accumulated_insns_num
6541 && ((struct bundle_state *)
6542 *entry_ptr)->branch_deviation
6543 > bundle_state->branch_deviation))))
6546 struct bundle_state temp;
6548 temp = *(struct bundle_state *) *entry_ptr;
6549 *(struct bundle_state *) *entry_ptr = *bundle_state;
6550 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6551 *bundle_state = temp;
6556 /* Start work with the hash table. */
6559 initiate_bundle_state_table (void)
6561 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6565 /* Finish work with the hash table. */
6568 finish_bundle_state_table (void)
6570 htab_delete (bundle_state_table);
6575 /* The following variable is a insn `nop' used to check bundle states
6576 with different number of inserted nops. */
6578 static rtx ia64_nop;
6580 /* The following function tries to issue NOPS_NUM nops for the current
6581 state without advancing processor cycle. If it failed, the
6582 function returns FALSE and frees the current state. */
6585 try_issue_nops (struct bundle_state *curr_state, int nops_num)
6589 for (i = 0; i < nops_num; i++)
6590 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6592 free_bundle_state (curr_state);
6598 /* The following function tries to issue INSN for the current
6599 state without advancing processor cycle. If it failed, the
6600 function returns FALSE and frees the current state. */
6603 try_issue_insn (struct bundle_state *curr_state, rtx insn)
6605 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6607 free_bundle_state (curr_state);
6613 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6614 starting with ORIGINATOR without advancing processor cycle. If
6615 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6616 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6617 If it was successful, the function creates new bundle state and
6618 insert into the hash table and into `index_to_bundle_states'. */
6621 issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
6622 rtx insn, int try_bundle_end_p, int only_bundle_end_p)
6624 struct bundle_state *curr_state;
6626 curr_state = get_free_bundle_state ();
6627 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6628 curr_state->insn = insn;
6629 curr_state->insn_num = originator->insn_num + 1;
6630 curr_state->cost = originator->cost;
6631 curr_state->originator = originator;
6632 curr_state->before_nops_num = before_nops_num;
6633 curr_state->after_nops_num = 0;
6634 curr_state->accumulated_insns_num
6635 = originator->accumulated_insns_num + before_nops_num;
6636 curr_state->branch_deviation = originator->branch_deviation;
6638 if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6640 gcc_assert (GET_MODE (insn) != TImode);
6641 if (!try_issue_nops (curr_state, before_nops_num))
6643 if (!try_issue_insn (curr_state, insn))
6645 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6646 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6647 && curr_state->accumulated_insns_num % 3 != 0)
6649 free_bundle_state (curr_state);
6653 else if (GET_MODE (insn) != TImode)
6655 if (!try_issue_nops (curr_state, before_nops_num))
6657 if (!try_issue_insn (curr_state, insn))
6659 curr_state->accumulated_insns_num++;
6660 gcc_assert (GET_CODE (PATTERN (insn)) != ASM_INPUT
6661 && asm_noperands (PATTERN (insn)) < 0);
6663 if (ia64_safe_type (insn) == TYPE_L)
6664 curr_state->accumulated_insns_num++;
6668 /* If this is an insn that must be first in a group, then don't allow
6669 nops to be emitted before it. Currently, alloc is the only such
6670 supported instruction. */
6671 /* ??? The bundling automatons should handle this for us, but they do
6672 not yet have support for the first_insn attribute. */
6673 if (before_nops_num > 0 && get_attr_first_insn (insn) == FIRST_INSN_YES)
6675 free_bundle_state (curr_state);
6679 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6680 state_transition (curr_state->dfa_state, NULL);
6682 if (!try_issue_nops (curr_state, before_nops_num))
6684 if (!try_issue_insn (curr_state, insn))
6686 curr_state->accumulated_insns_num++;
6687 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6688 || asm_noperands (PATTERN (insn)) >= 0)
6690 /* Finish bundle containing asm insn. */
6691 curr_state->after_nops_num
6692 = 3 - curr_state->accumulated_insns_num % 3;
6693 curr_state->accumulated_insns_num
6694 += 3 - curr_state->accumulated_insns_num % 3;
6696 else if (ia64_safe_type (insn) == TYPE_L)
6697 curr_state->accumulated_insns_num++;
6699 if (ia64_safe_type (insn) == TYPE_B)
6700 curr_state->branch_deviation
6701 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6702 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6704 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6707 struct bundle_state *curr_state1;
6708 struct bundle_state *allocated_states_chain;
6710 curr_state1 = get_free_bundle_state ();
6711 dfa_state = curr_state1->dfa_state;
6712 allocated_states_chain = curr_state1->allocated_states_chain;
6713 *curr_state1 = *curr_state;
6714 curr_state1->dfa_state = dfa_state;
6715 curr_state1->allocated_states_chain = allocated_states_chain;
6716 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6718 curr_state = curr_state1;
6720 if (!try_issue_nops (curr_state,
6721 3 - curr_state->accumulated_insns_num % 3))
6723 curr_state->after_nops_num
6724 = 3 - curr_state->accumulated_insns_num % 3;
6725 curr_state->accumulated_insns_num
6726 += 3 - curr_state->accumulated_insns_num % 3;
6728 if (!insert_bundle_state (curr_state))
6729 free_bundle_state (curr_state);
6733 /* The following function returns position in the two window bundle
6737 get_max_pos (state_t state)
6739 if (cpu_unit_reservation_p (state, pos_6))
6741 else if (cpu_unit_reservation_p (state, pos_5))
6743 else if (cpu_unit_reservation_p (state, pos_4))
6745 else if (cpu_unit_reservation_p (state, pos_3))
6747 else if (cpu_unit_reservation_p (state, pos_2))
6749 else if (cpu_unit_reservation_p (state, pos_1))
6755 /* The function returns code of a possible template for given position
6756 and state. The function should be called only with 2 values of
6757 position equal to 3 or 6. We avoid generating F NOPs by putting
6758 templates containing F insns at the end of the template search
6759 because undocumented anomaly in McKinley derived cores which can
6760 cause stalls if an F-unit insn (including a NOP) is issued within a
6761 six-cycle window after reading certain application registers (such
6762 as ar.bsp). Furthermore, power-considerations also argue against
6763 the use of F-unit instructions unless they're really needed. */
6766 get_template (state_t state, int pos)
6771 if (cpu_unit_reservation_p (state, _0mmi_))
6773 else if (cpu_unit_reservation_p (state, _0mii_))
6775 else if (cpu_unit_reservation_p (state, _0mmb_))
6777 else if (cpu_unit_reservation_p (state, _0mib_))
6779 else if (cpu_unit_reservation_p (state, _0mbb_))
6781 else if (cpu_unit_reservation_p (state, _0bbb_))
6783 else if (cpu_unit_reservation_p (state, _0mmf_))
6785 else if (cpu_unit_reservation_p (state, _0mfi_))
6787 else if (cpu_unit_reservation_p (state, _0mfb_))
6789 else if (cpu_unit_reservation_p (state, _0mlx_))
6794 if (cpu_unit_reservation_p (state, _1mmi_))
6796 else if (cpu_unit_reservation_p (state, _1mii_))
6798 else if (cpu_unit_reservation_p (state, _1mmb_))
6800 else if (cpu_unit_reservation_p (state, _1mib_))
6802 else if (cpu_unit_reservation_p (state, _1mbb_))
6804 else if (cpu_unit_reservation_p (state, _1bbb_))
6806 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6808 else if (cpu_unit_reservation_p (state, _1mfi_))
6810 else if (cpu_unit_reservation_p (state, _1mfb_))
6812 else if (cpu_unit_reservation_p (state, _1mlx_))
6821 /* The following function returns an insn important for insn bundling
6822 followed by INSN and before TAIL. */
6825 get_next_important_insn (rtx insn, rtx tail)
6827 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6829 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6830 && GET_CODE (PATTERN (insn)) != USE
6831 && GET_CODE (PATTERN (insn)) != CLOBBER)
6836 /* The following function does insn bundling. Bundling means
6837 inserting templates and nop insns to fit insn groups into permitted
6838 templates. Instruction scheduling uses NDFA (non-deterministic
6839 finite automata) encoding informations about the templates and the
6840 inserted nops. Nondeterminism of the automata permits follows
6841 all possible insn sequences very fast.
6843 Unfortunately it is not possible to get information about inserting
6844 nop insns and used templates from the automata states. The
6845 automata only says that we can issue an insn possibly inserting
6846 some nops before it and using some template. Therefore insn
6847 bundling in this function is implemented by using DFA
6848 (deterministic finite automata). We follows all possible insn
6849 sequences by inserting 0-2 nops (that is what the NDFA describe for
6850 insn scheduling) before/after each insn being bundled. We know the
6851 start of simulated processor cycle from insn scheduling (insn
6852 starting a new cycle has TImode).
6854 Simple implementation of insn bundling would create enormous
6855 number of possible insn sequences satisfying information about new
6856 cycle ticks taken from the insn scheduling. To make the algorithm
6857 practical we use dynamic programming. Each decision (about
6858 inserting nops and implicitly about previous decisions) is described
6859 by structure bundle_state (see above). If we generate the same
6860 bundle state (key is automaton state after issuing the insns and
6861 nops for it), we reuse already generated one. As consequence we
6862 reject some decisions which cannot improve the solution and
6863 reduce memory for the algorithm.
6865 When we reach the end of EBB (extended basic block), we choose the
6866 best sequence and then, moving back in EBB, insert templates for
6867 the best alternative. The templates are taken from querying
6868 automaton state for each insn in chosen bundle states.
6870 So the algorithm makes two (forward and backward) passes through
6871 EBB. There is an additional forward pass through EBB for Itanium1
6872 processor. This pass inserts more nops to make dependency between
6873 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6876 bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
6878 struct bundle_state *curr_state, *next_state, *best_state;
6879 rtx insn, next_insn;
6881 int i, bundle_end_p, only_bundle_end_p, asm_p;
6882 int pos = 0, max_pos, template0, template1;
6885 enum attr_type type;
6888 /* Count insns in the EBB. */
6889 for (insn = NEXT_INSN (prev_head_insn);
6890 insn && insn != tail;
6891 insn = NEXT_INSN (insn))
6897 dfa_clean_insn_cache ();
6898 initiate_bundle_state_table ();
6899 index_to_bundle_states = xmalloc ((insn_num + 2)
6900 * sizeof (struct bundle_state *));
6901 /* First (forward) pass -- generation of bundle states. */
6902 curr_state = get_free_bundle_state ();
6903 curr_state->insn = NULL;
6904 curr_state->before_nops_num = 0;
6905 curr_state->after_nops_num = 0;
6906 curr_state->insn_num = 0;
6907 curr_state->cost = 0;
6908 curr_state->accumulated_insns_num = 0;
6909 curr_state->branch_deviation = 0;
6910 curr_state->next = NULL;
6911 curr_state->originator = NULL;
6912 state_reset (curr_state->dfa_state);
6913 index_to_bundle_states [0] = curr_state;
6915 /* Shift cycle mark if it is put on insn which could be ignored. */
6916 for (insn = NEXT_INSN (prev_head_insn);
6918 insn = NEXT_INSN (insn))
6920 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6921 || GET_CODE (PATTERN (insn)) == USE
6922 || GET_CODE (PATTERN (insn)) == CLOBBER)
6923 && GET_MODE (insn) == TImode)
6925 PUT_MODE (insn, VOIDmode);
6926 for (next_insn = NEXT_INSN (insn);
6928 next_insn = NEXT_INSN (next_insn))
6929 if (INSN_P (next_insn)
6930 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6931 && GET_CODE (PATTERN (next_insn)) != USE
6932 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6934 PUT_MODE (next_insn, TImode);
6938 /* Froward pass: generation of bundle states. */
6939 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6943 gcc_assert (INSN_P (insn)
6944 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6945 && GET_CODE (PATTERN (insn)) != USE
6946 && GET_CODE (PATTERN (insn)) != CLOBBER);
6947 type = ia64_safe_type (insn);
6948 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6950 index_to_bundle_states [insn_num] = NULL;
6951 for (curr_state = index_to_bundle_states [insn_num - 1];
6953 curr_state = next_state)
6955 pos = curr_state->accumulated_insns_num % 3;
6956 next_state = curr_state->next;
6957 /* We must fill up the current bundle in order to start a
6958 subsequent asm insn in a new bundle. Asm insn is always
6959 placed in a separate bundle. */
6961 = (next_insn != NULL_RTX
6962 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6963 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6964 /* We may fill up the current bundle if it is the cycle end
6965 without a group barrier. */
6967 = (only_bundle_end_p || next_insn == NULL_RTX
6968 || (GET_MODE (next_insn) == TImode
6969 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6970 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6972 /* We need to insert 2 nops for cases like M_MII. To
6973 guarantee issuing all insns on the same cycle for
6974 Itanium 1, we need to issue 2 nops after the first M
6975 insn (MnnMII where n is a nop insn). */
6976 || ((type == TYPE_M || type == TYPE_A)
6977 && ia64_tune == PROCESSOR_ITANIUM
6978 && !bundle_end_p && pos == 1))
6979 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6981 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6983 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6986 gcc_assert (index_to_bundle_states [insn_num]);
6987 for (curr_state = index_to_bundle_states [insn_num];
6989 curr_state = curr_state->next)
6990 if (verbose >= 2 && dump)
6992 /* This structure is taken from generated code of the
6993 pipeline hazard recognizer (see file insn-attrtab.c).
6994 Please don't forget to change the structure if a new
6995 automaton is added to .md file. */
6998 unsigned short one_automaton_state;
6999 unsigned short oneb_automaton_state;
7000 unsigned short two_automaton_state;
7001 unsigned short twob_automaton_state;
7006 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7007 curr_state->unique_num,
7008 (curr_state->originator == NULL
7009 ? -1 : curr_state->originator->unique_num),
7011 curr_state->before_nops_num, curr_state->after_nops_num,
7012 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7013 (ia64_tune == PROCESSOR_ITANIUM
7014 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7015 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7020 /* We should find a solution because the 2nd insn scheduling has
7022 gcc_assert (index_to_bundle_states [insn_num]);
7023 /* Find a state corresponding to the best insn sequence. */
7025 for (curr_state = index_to_bundle_states [insn_num];
7027 curr_state = curr_state->next)
7028 /* We are just looking at the states with fully filled up last
7029 bundle. The first we prefer insn sequences with minimal cost
7030 then with minimal inserted nops and finally with branch insns
7031 placed in the 3rd slots. */
7032 if (curr_state->accumulated_insns_num % 3 == 0
7033 && (best_state == NULL || best_state->cost > curr_state->cost
7034 || (best_state->cost == curr_state->cost
7035 && (curr_state->accumulated_insns_num
7036 < best_state->accumulated_insns_num
7037 || (curr_state->accumulated_insns_num
7038 == best_state->accumulated_insns_num
7039 && curr_state->branch_deviation
7040 < best_state->branch_deviation)))))
7041 best_state = curr_state;
7042 /* Second (backward) pass: adding nops and templates. */
7043 insn_num = best_state->before_nops_num;
7044 template0 = template1 = -1;
7045 for (curr_state = best_state;
7046 curr_state->originator != NULL;
7047 curr_state = curr_state->originator)
7049 insn = curr_state->insn;
7050 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
7051 || asm_noperands (PATTERN (insn)) >= 0);
7053 if (verbose >= 2 && dump)
7057 unsigned short one_automaton_state;
7058 unsigned short oneb_automaton_state;
7059 unsigned short two_automaton_state;
7060 unsigned short twob_automaton_state;
7065 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7066 curr_state->unique_num,
7067 (curr_state->originator == NULL
7068 ? -1 : curr_state->originator->unique_num),
7070 curr_state->before_nops_num, curr_state->after_nops_num,
7071 curr_state->accumulated_insns_num, curr_state->branch_deviation,
7072 (ia64_tune == PROCESSOR_ITANIUM
7073 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
7074 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
7077 /* Find the position in the current bundle window. The window can
7078 contain at most two bundles. Two bundle window means that
7079 the processor will make two bundle rotation. */
7080 max_pos = get_max_pos (curr_state->dfa_state);
7082 /* The following (negative template number) means that the
7083 processor did one bundle rotation. */
7084 || (max_pos == 3 && template0 < 0))
7086 /* We are at the end of the window -- find template(s) for
7090 template0 = get_template (curr_state->dfa_state, 3);
7093 template1 = get_template (curr_state->dfa_state, 3);
7094 template0 = get_template (curr_state->dfa_state, 6);
7097 if (max_pos > 3 && template1 < 0)
7098 /* It may happen when we have the stop inside a bundle. */
7100 gcc_assert (pos <= 3);
7101 template1 = get_template (curr_state->dfa_state, 3);
7105 /* Emit nops after the current insn. */
7106 for (i = 0; i < curr_state->after_nops_num; i++)
7109 emit_insn_after (nop, insn);
7111 gcc_assert (pos >= 0);
7114 /* We are at the start of a bundle: emit the template
7115 (it should be defined). */
7116 gcc_assert (template0 >= 0);
7117 b = gen_bundle_selector (GEN_INT (template0));
7118 ia64_emit_insn_before (b, nop);
7119 /* If we have two bundle window, we make one bundle
7120 rotation. Otherwise template0 will be undefined
7121 (negative value). */
7122 template0 = template1;
7126 /* Move the position backward in the window. Group barrier has
7127 no slot. Asm insn takes all bundle. */
7128 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7129 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7130 && asm_noperands (PATTERN (insn)) < 0)
7132 /* Long insn takes 2 slots. */
7133 if (ia64_safe_type (insn) == TYPE_L)
7135 gcc_assert (pos >= 0);
7137 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
7138 && GET_CODE (PATTERN (insn)) != ASM_INPUT
7139 && asm_noperands (PATTERN (insn)) < 0)
7141 /* The current insn is at the bundle start: emit the
7143 gcc_assert (template0 >= 0);
7144 b = gen_bundle_selector (GEN_INT (template0));
7145 ia64_emit_insn_before (b, insn);
7146 b = PREV_INSN (insn);
7148 /* See comment above in analogous place for emitting nops
7150 template0 = template1;
7153 /* Emit nops after the current insn. */
7154 for (i = 0; i < curr_state->before_nops_num; i++)
7157 ia64_emit_insn_before (nop, insn);
7158 nop = PREV_INSN (insn);
7161 gcc_assert (pos >= 0);
7164 /* See comment above in analogous place for emitting nops
7166 gcc_assert (template0 >= 0);
7167 b = gen_bundle_selector (GEN_INT (template0));
7168 ia64_emit_insn_before (b, insn);
7169 b = PREV_INSN (insn);
7171 template0 = template1;
7176 if (ia64_tune == PROCESSOR_ITANIUM)
7177 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7178 Itanium1 has a strange design, if the distance between an insn
7179 and dependent MM-insn is less 4 then we have a 6 additional
7180 cycles stall. So we make the distance equal to 4 cycles if it
7182 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
7186 gcc_assert (INSN_P (insn)
7187 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
7188 && GET_CODE (PATTERN (insn)) != USE
7189 && GET_CODE (PATTERN (insn)) != CLOBBER);
7190 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
7191 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
7192 /* We found a MM-insn which needs additional cycles. */
7198 /* Now we are searching for a template of the bundle in
7199 which the MM-insn is placed and the position of the
7200 insn in the bundle (0, 1, 2). Also we are searching
7201 for that there is a stop before the insn. */
7202 last = prev_active_insn (insn);
7203 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
7205 last = prev_active_insn (last);
7207 for (;; last = prev_active_insn (last))
7208 if (recog_memoized (last) == CODE_FOR_bundle_selector)
7210 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
7212 /* The insn is in MLX bundle. Change the template
7213 onto MFI because we will add nops before the
7214 insn. It simplifies subsequent code a lot. */
7216 = gen_bundle_selector (const2_rtx); /* -> MFI */
7219 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier
7220 && (ia64_safe_itanium_class (last)
7221 != ITANIUM_CLASS_IGNORE))
7223 /* Some check of correctness: the stop is not at the
7224 bundle start, there are no more 3 insns in the bundle,
7225 and the MM-insn is not at the start of bundle with
7227 gcc_assert ((!pred_stop_p || n)
7229 && (template0 != 9 || !n));
7230 /* Put nops after the insn in the bundle. */
7231 for (j = 3 - n; j > 0; j --)
7232 ia64_emit_insn_before (gen_nop (), insn);
7233 /* It takes into account that we will add more N nops
7234 before the insn lately -- please see code below. */
7235 add_cycles [INSN_UID (insn)]--;
7236 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
7237 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7240 add_cycles [INSN_UID (insn)]--;
7241 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
7243 /* Insert "MII;" template. */
7244 ia64_emit_insn_before (gen_bundle_selector (const0_rtx),
7246 ia64_emit_insn_before (gen_nop (), insn);
7247 ia64_emit_insn_before (gen_nop (), insn);
7250 /* To decrease code size, we use "MI;I;"
7252 ia64_emit_insn_before
7253 (gen_insn_group_barrier (GEN_INT (3)), insn);
7256 ia64_emit_insn_before (gen_nop (), insn);
7257 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7260 /* Put the MM-insn in the same slot of a bundle with the
7261 same template as the original one. */
7262 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
7264 /* To put the insn in the same slot, add necessary number
7266 for (j = n; j > 0; j --)
7267 ia64_emit_insn_before (gen_nop (), insn);
7268 /* Put the stop if the original bundle had it. */
7270 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7274 free (index_to_bundle_states);
7275 finish_bundle_state_table ();
7277 dfa_clean_insn_cache ();
7280 /* The following function is called at the end of scheduling BB or
7281 EBB. After reload, it inserts stop bits and does insn bundling. */
7284 ia64_sched_finish (FILE *dump, int sched_verbose)
7287 fprintf (dump, "// Finishing schedule.\n");
7288 if (!reload_completed)
7290 if (reload_completed)
7292 final_emit_insn_group_barriers (dump);
7293 bundling (dump, sched_verbose, current_sched_info->prev_head,
7294 current_sched_info->next_tail);
7295 if (sched_verbose && dump)
7296 fprintf (dump, "// finishing %d-%d\n",
7297 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
7298 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
7304 /* The following function inserts stop bits in scheduled BB or EBB. */
7307 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
7310 int need_barrier_p = 0;
7311 rtx prev_insn = NULL_RTX;
7313 init_insn_group_barriers ();
7315 for (insn = NEXT_INSN (current_sched_info->prev_head);
7316 insn != current_sched_info->next_tail;
7317 insn = NEXT_INSN (insn))
7319 if (GET_CODE (insn) == BARRIER)
7321 rtx last = prev_active_insn (insn);
7325 if (GET_CODE (last) == JUMP_INSN
7326 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
7327 last = prev_active_insn (last);
7328 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
7329 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
7331 init_insn_group_barriers ();
7333 prev_insn = NULL_RTX;
7335 else if (INSN_P (insn))
7337 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
7339 init_insn_group_barriers ();
7341 prev_insn = NULL_RTX;
7343 else if (need_barrier_p || group_barrier_needed (insn))
7345 if (TARGET_EARLY_STOP_BITS)
7350 last != current_sched_info->prev_head;
7351 last = PREV_INSN (last))
7352 if (INSN_P (last) && GET_MODE (last) == TImode
7353 && stops_p [INSN_UID (last)])
7355 if (last == current_sched_info->prev_head)
7357 last = prev_active_insn (last);
7359 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7360 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7362 init_insn_group_barriers ();
7363 for (last = NEXT_INSN (last);
7365 last = NEXT_INSN (last))
7367 group_barrier_needed (last);
7371 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7373 init_insn_group_barriers ();
7375 group_barrier_needed (insn);
7376 prev_insn = NULL_RTX;
7378 else if (recog_memoized (insn) >= 0)
7380 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7381 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7382 || asm_noperands (PATTERN (insn)) >= 0);
7389 /* If the following function returns TRUE, we will use the the DFA
7393 ia64_first_cycle_multipass_dfa_lookahead (void)
7395 return (reload_completed ? 6 : 4);
7398 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7401 ia64_init_dfa_pre_cycle_insn (void)
7403 if (temp_dfa_state == NULL)
7405 dfa_state_size = state_size ();
7406 temp_dfa_state = xmalloc (dfa_state_size);
7407 prev_cycle_state = xmalloc (dfa_state_size);
7409 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7410 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7411 recog_memoized (dfa_pre_cycle_insn);
7412 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7413 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7414 recog_memoized (dfa_stop_insn);
7417 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7418 used by the DFA insn scheduler. */
7421 ia64_dfa_pre_cycle_insn (void)
7423 return dfa_pre_cycle_insn;
7426 /* The following function returns TRUE if PRODUCER (of type ilog or
7427 ld) produces address for CONSUMER (of type st or stf). */
7430 ia64_st_address_bypass_p (rtx producer, rtx consumer)
7434 gcc_assert (producer && consumer);
7435 dest = ia64_single_set (producer);
7437 reg = SET_DEST (dest);
7439 if (GET_CODE (reg) == SUBREG)
7440 reg = SUBREG_REG (reg);
7441 gcc_assert (GET_CODE (reg) == REG);
7443 dest = ia64_single_set (consumer);
7445 mem = SET_DEST (dest);
7446 gcc_assert (mem && GET_CODE (mem) == MEM);
7447 return reg_mentioned_p (reg, mem);
7450 /* The following function returns TRUE if PRODUCER (of type ilog or
7451 ld) produces address for CONSUMER (of type ld or fld). */
7454 ia64_ld_address_bypass_p (rtx producer, rtx consumer)
7456 rtx dest, src, reg, mem;
7458 gcc_assert (producer && consumer);
7459 dest = ia64_single_set (producer);
7461 reg = SET_DEST (dest);
7463 if (GET_CODE (reg) == SUBREG)
7464 reg = SUBREG_REG (reg);
7465 gcc_assert (GET_CODE (reg) == REG);
7467 src = ia64_single_set (consumer);
7469 mem = SET_SRC (src);
7471 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7472 mem = XVECEXP (mem, 0, 0);
7473 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7474 mem = XEXP (mem, 0);
7476 /* Note that LO_SUM is used for GOT loads. */
7477 gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
7479 return reg_mentioned_p (reg, mem);
7482 /* The following function returns TRUE if INSN produces address for a
7483 load/store insn. We will place such insns into M slot because it
7484 decreases its latency time. */
7487 ia64_produce_address_p (rtx insn)
7493 /* Emit pseudo-ops for the assembler to describe predicate relations.
7494 At present this assumes that we only consider predicate pairs to
7495 be mutex, and that the assembler can deduce proper values from
7496 straight-line code. */
7499 emit_predicate_relation_info (void)
7503 FOR_EACH_BB_REVERSE (bb)
7506 rtx head = BB_HEAD (bb);
7508 /* We only need such notes at code labels. */
7509 if (GET_CODE (head) != CODE_LABEL)
7511 if (GET_CODE (NEXT_INSN (head)) == NOTE
7512 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7513 head = NEXT_INSN (head);
7515 /* Skip p0, which may be thought to be live due to (reg:DI p0)
7516 grabbing the entire block of predicate registers. */
7517 for (r = PR_REG (2); r < PR_REG (64); r += 2)
7518 if (REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, r))
7520 rtx p = gen_rtx_REG (BImode, r);
7521 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7522 if (head == BB_END (bb))
7528 /* Look for conditional calls that do not return, and protect predicate
7529 relations around them. Otherwise the assembler will assume the call
7530 returns, and complain about uses of call-clobbered predicates after
7532 FOR_EACH_BB_REVERSE (bb)
7534 rtx insn = BB_HEAD (bb);
7538 if (GET_CODE (insn) == CALL_INSN
7539 && GET_CODE (PATTERN (insn)) == COND_EXEC
7540 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7542 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7543 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7544 if (BB_HEAD (bb) == insn)
7546 if (BB_END (bb) == insn)
7550 if (insn == BB_END (bb))
7552 insn = NEXT_INSN (insn);
7557 /* Perform machine dependent operations on the rtl chain INSNS. */
7562 /* We are freeing block_for_insn in the toplev to keep compatibility
7563 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7564 compute_bb_for_insn ();
7566 /* If optimizing, we'll have split before scheduling. */
7568 split_all_insns (0);
7570 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7571 non-optimizing bootstrap. */
7572 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7574 if (ia64_flag_schedule_insns2)
7576 timevar_push (TV_SCHED2);
7577 ia64_final_schedule = 1;
7579 initiate_bundle_states ();
7580 ia64_nop = make_insn_raw (gen_nop ());
7581 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7582 recog_memoized (ia64_nop);
7583 clocks_length = get_max_uid () + 1;
7584 stops_p = xcalloc (1, clocks_length);
7585 if (ia64_tune == PROCESSOR_ITANIUM)
7587 clocks = xcalloc (clocks_length, sizeof (int));
7588 add_cycles = xcalloc (clocks_length, sizeof (int));
7590 if (ia64_tune == PROCESSOR_ITANIUM2)
7592 pos_1 = get_cpu_unit_code ("2_1");
7593 pos_2 = get_cpu_unit_code ("2_2");
7594 pos_3 = get_cpu_unit_code ("2_3");
7595 pos_4 = get_cpu_unit_code ("2_4");
7596 pos_5 = get_cpu_unit_code ("2_5");
7597 pos_6 = get_cpu_unit_code ("2_6");
7598 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7599 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7600 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7601 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7602 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7603 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7604 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7605 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7606 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7607 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7608 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7609 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7610 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7611 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7612 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7613 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7614 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7615 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7616 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7617 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7621 pos_1 = get_cpu_unit_code ("1_1");
7622 pos_2 = get_cpu_unit_code ("1_2");
7623 pos_3 = get_cpu_unit_code ("1_3");
7624 pos_4 = get_cpu_unit_code ("1_4");
7625 pos_5 = get_cpu_unit_code ("1_5");
7626 pos_6 = get_cpu_unit_code ("1_6");
7627 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7628 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7629 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7630 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7631 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7632 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7633 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7634 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7635 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7636 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7637 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7638 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7639 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7640 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7641 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7642 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7643 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7644 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7645 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7646 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7648 schedule_ebbs (dump_file);
7649 finish_bundle_states ();
7650 if (ia64_tune == PROCESSOR_ITANIUM)
7656 emit_insn_group_barriers (dump_file);
7658 ia64_final_schedule = 0;
7659 timevar_pop (TV_SCHED2);
7662 emit_all_insn_group_barriers (dump_file);
7664 /* A call must not be the last instruction in a function, so that the
7665 return address is still within the function, so that unwinding works
7666 properly. Note that IA-64 differs from dwarf2 on this point. */
7667 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7672 insn = get_last_insn ();
7673 if (! INSN_P (insn))
7674 insn = prev_active_insn (insn);
7675 /* Skip over insns that expand to nothing. */
7676 while (GET_CODE (insn) == INSN && get_attr_empty (insn) == EMPTY_YES)
7678 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7679 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7681 insn = prev_active_insn (insn);
7683 if (GET_CODE (insn) == CALL_INSN)
7686 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7687 emit_insn (gen_break_f ());
7688 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7692 emit_predicate_relation_info ();
7694 if (ia64_flag_var_tracking)
7696 timevar_push (TV_VAR_TRACKING);
7697 variable_tracking_main ();
7698 timevar_pop (TV_VAR_TRACKING);
7702 /* Return true if REGNO is used by the epilogue. */
7705 ia64_epilogue_uses (int regno)
7710 /* With a call to a function in another module, we will write a new
7711 value to "gp". After returning from such a call, we need to make
7712 sure the function restores the original gp-value, even if the
7713 function itself does not use the gp anymore. */
7714 return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
7716 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7717 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7718 /* For functions defined with the syscall_linkage attribute, all
7719 input registers are marked as live at all function exits. This
7720 prevents the register allocator from using the input registers,
7721 which in turn makes it possible to restart a system call after
7722 an interrupt without having to save/restore the input registers.
7723 This also prevents kernel data from leaking to application code. */
7724 return lookup_attribute ("syscall_linkage",
7725 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7728 /* Conditional return patterns can't represent the use of `b0' as
7729 the return address, so we force the value live this way. */
7733 /* Likewise for ar.pfs, which is used by br.ret. */
7741 /* Return true if REGNO is used by the frame unwinder. */
7744 ia64_eh_uses (int regno)
7746 if (! reload_completed)
7749 if (current_frame_info.reg_save_b0
7750 && regno == current_frame_info.reg_save_b0)
7752 if (current_frame_info.reg_save_pr
7753 && regno == current_frame_info.reg_save_pr)
7755 if (current_frame_info.reg_save_ar_pfs
7756 && regno == current_frame_info.reg_save_ar_pfs)
7758 if (current_frame_info.reg_save_ar_unat
7759 && regno == current_frame_info.reg_save_ar_unat)
7761 if (current_frame_info.reg_save_ar_lc
7762 && regno == current_frame_info.reg_save_ar_lc)
7768 /* Return true if this goes in small data/bss. */
7770 /* ??? We could also support own long data here. Generating movl/add/ld8
7771 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7772 code faster because there is one less load. This also includes incomplete
7773 types which can't go in sdata/sbss. */
7776 ia64_in_small_data_p (tree exp)
7778 if (TARGET_NO_SDATA)
7781 /* We want to merge strings, so we never consider them small data. */
7782 if (TREE_CODE (exp) == STRING_CST)
7785 /* Functions are never small data. */
7786 if (TREE_CODE (exp) == FUNCTION_DECL)
7789 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7791 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7793 if (strcmp (section, ".sdata") == 0
7794 || strncmp (section, ".sdata.", 7) == 0
7795 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
7796 || strcmp (section, ".sbss") == 0
7797 || strncmp (section, ".sbss.", 6) == 0
7798 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
7803 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7805 /* If this is an incomplete type with size 0, then we can't put it
7806 in sdata because it might be too big when completed. */
7807 if (size > 0 && size <= ia64_section_threshold)
7814 /* Output assembly directives for prologue regions. */
7816 /* The current basic block number. */
7818 static bool last_block;
7820 /* True if we need a copy_state command at the start of the next block. */
7822 static bool need_copy_state;
7824 /* The function emits unwind directives for the start of an epilogue. */
7827 process_epilogue (void)
7829 /* If this isn't the last block of the function, then we need to label the
7830 current state, and copy it back in at the start of the next block. */
7834 fprintf (asm_out_file, "\t.label_state %d\n",
7835 ++cfun->machine->state_num);
7836 need_copy_state = true;
7839 fprintf (asm_out_file, "\t.restore sp\n");
7842 /* This function processes a SET pattern looking for specific patterns
7843 which result in emitting an assembly directive required for unwinding. */
7846 process_set (FILE *asm_out_file, rtx pat)
7848 rtx src = SET_SRC (pat);
7849 rtx dest = SET_DEST (pat);
7850 int src_regno, dest_regno;
7852 /* Look for the ALLOC insn. */
7853 if (GET_CODE (src) == UNSPEC_VOLATILE
7854 && XINT (src, 1) == UNSPECV_ALLOC
7855 && GET_CODE (dest) == REG)
7857 dest_regno = REGNO (dest);
7859 /* If this is the final destination for ar.pfs, then this must
7860 be the alloc in the prologue. */
7861 if (dest_regno == current_frame_info.reg_save_ar_pfs)
7862 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7863 ia64_dbx_register_number (dest_regno));
7866 /* This must be an alloc before a sibcall. We must drop the
7867 old frame info. The easiest way to drop the old frame
7868 info is to ensure we had a ".restore sp" directive
7869 followed by a new prologue. If the procedure doesn't
7870 have a memory-stack frame, we'll issue a dummy ".restore
7872 if (current_frame_info.total_size == 0 && !frame_pointer_needed)
7873 /* if haven't done process_epilogue() yet, do it now */
7874 process_epilogue ();
7875 fprintf (asm_out_file, "\t.prologue\n");
7880 /* Look for SP = .... */
7881 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7883 if (GET_CODE (src) == PLUS)
7885 rtx op0 = XEXP (src, 0);
7886 rtx op1 = XEXP (src, 1);
7888 gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
7890 if (INTVAL (op1) < 0)
7891 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7894 process_epilogue ();
7898 gcc_assert (GET_CODE (src) == REG
7899 && REGNO (src) == HARD_FRAME_POINTER_REGNUM);
7900 process_epilogue ();
7906 /* Register move we need to look at. */
7907 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7909 src_regno = REGNO (src);
7910 dest_regno = REGNO (dest);
7915 /* Saving return address pointer. */
7916 gcc_assert (dest_regno == current_frame_info.reg_save_b0);
7917 fprintf (asm_out_file, "\t.save rp, r%d\n",
7918 ia64_dbx_register_number (dest_regno));
7922 gcc_assert (dest_regno == current_frame_info.reg_save_pr);
7923 fprintf (asm_out_file, "\t.save pr, r%d\n",
7924 ia64_dbx_register_number (dest_regno));
7927 case AR_UNAT_REGNUM:
7928 gcc_assert (dest_regno == current_frame_info.reg_save_ar_unat);
7929 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7930 ia64_dbx_register_number (dest_regno));
7934 gcc_assert (dest_regno == current_frame_info.reg_save_ar_lc);
7935 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7936 ia64_dbx_register_number (dest_regno));
7939 case STACK_POINTER_REGNUM:
7940 gcc_assert (dest_regno == HARD_FRAME_POINTER_REGNUM
7941 && frame_pointer_needed);
7942 fprintf (asm_out_file, "\t.vframe r%d\n",
7943 ia64_dbx_register_number (dest_regno));
7947 /* Everything else should indicate being stored to memory. */
7952 /* Memory store we need to look at. */
7953 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7959 if (GET_CODE (XEXP (dest, 0)) == REG)
7961 base = XEXP (dest, 0);
7966 gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
7967 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
7968 base = XEXP (XEXP (dest, 0), 0);
7969 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7972 if (base == hard_frame_pointer_rtx)
7974 saveop = ".savepsp";
7979 gcc_assert (base == stack_pointer_rtx);
7983 src_regno = REGNO (src);
7987 gcc_assert (!current_frame_info.reg_save_b0);
7988 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7992 gcc_assert (!current_frame_info.reg_save_pr);
7993 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7997 gcc_assert (!current_frame_info.reg_save_ar_lc);
7998 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
8002 gcc_assert (!current_frame_info.reg_save_ar_pfs);
8003 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
8006 case AR_UNAT_REGNUM:
8007 gcc_assert (!current_frame_info.reg_save_ar_unat);
8008 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
8015 fprintf (asm_out_file, "\t.save.g 0x%x\n",
8016 1 << (src_regno - GR_REG (4)));
8024 fprintf (asm_out_file, "\t.save.b 0x%x\n",
8025 1 << (src_regno - BR_REG (1)));
8032 fprintf (asm_out_file, "\t.save.f 0x%x\n",
8033 1 << (src_regno - FR_REG (2)));
8036 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
8037 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
8038 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
8039 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
8040 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
8041 1 << (src_regno - FR_REG (12)));
8053 /* This function looks at a single insn and emits any directives
8054 required to unwind this insn. */
8056 process_for_unwind_directive (FILE *asm_out_file, rtx insn)
8058 if (flag_unwind_tables
8059 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
8063 if (GET_CODE (insn) == NOTE
8064 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
8066 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
8068 /* Restore unwind state from immediately before the epilogue. */
8069 if (need_copy_state)
8071 fprintf (asm_out_file, "\t.body\n");
8072 fprintf (asm_out_file, "\t.copy_state %d\n",
8073 cfun->machine->state_num);
8074 need_copy_state = false;
8078 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
8081 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
8083 pat = XEXP (pat, 0);
8085 pat = PATTERN (insn);
8087 switch (GET_CODE (pat))
8090 process_set (asm_out_file, pat);
8096 int limit = XVECLEN (pat, 0);
8097 for (par_index = 0; par_index < limit; par_index++)
8099 rtx x = XVECEXP (pat, 0, par_index);
8100 if (GET_CODE (x) == SET)
8101 process_set (asm_out_file, x);
8116 IA64_BUILTIN_FLUSHRS
8120 ia64_init_builtins (void)
8125 /* The __fpreg type. */
8126 fpreg_type = make_node (REAL_TYPE);
8127 TYPE_PRECISION (fpreg_type) = 82;
8128 layout_type (fpreg_type);
8129 (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
8131 /* The __float80 type. */
8132 float80_type = make_node (REAL_TYPE);
8133 TYPE_PRECISION (float80_type) = 80;
8134 layout_type (float80_type);
8135 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
8137 /* The __float128 type. */
8140 tree float128_type = make_node (REAL_TYPE);
8141 TYPE_PRECISION (float128_type) = 128;
8142 layout_type (float128_type);
8143 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
8146 /* Under HPUX, this is a synonym for "long double". */
8147 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
8150 #define def_builtin(name, type, code) \
8151 lang_hooks.builtin_function ((name), (type), (code), BUILT_IN_MD, \
8154 def_builtin ("__builtin_ia64_bsp",
8155 build_function_type (ptr_type_node, void_list_node),
8158 def_builtin ("__builtin_ia64_flushrs",
8159 build_function_type (void_type_node, void_list_node),
8160 IA64_BUILTIN_FLUSHRS);
8166 ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8167 enum machine_mode mode ATTRIBUTE_UNUSED,
8168 int ignore ATTRIBUTE_UNUSED)
8170 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8171 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8175 case IA64_BUILTIN_BSP:
8176 if (! target || ! register_operand (target, DImode))
8177 target = gen_reg_rtx (DImode);
8178 emit_insn (gen_bsp_value (target));
8179 #ifdef POINTERS_EXTEND_UNSIGNED
8180 target = convert_memory_address (ptr_mode, target);
8184 case IA64_BUILTIN_FLUSHRS:
8185 emit_insn (gen_flushrs ());
8195 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8196 most significant bits of the stack slot. */
8199 ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
8201 /* Exception to normal case for structures/unions/etc. */
8203 if (type && AGGREGATE_TYPE_P (type)
8204 && int_size_in_bytes (type) < UNITS_PER_WORD)
8207 /* Fall back to the default. */
8208 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
8211 /* Linked list of all external functions that are to be emitted by GCC.
8212 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8213 order to avoid putting out names that are never really used. */
8215 struct extern_func_list GTY(())
8217 struct extern_func_list *next;
8221 static GTY(()) struct extern_func_list *extern_func_head;
8224 ia64_hpux_add_extern_decl (tree decl)
8226 struct extern_func_list *p = ggc_alloc (sizeof (struct extern_func_list));
8229 p->next = extern_func_head;
8230 extern_func_head = p;
8233 /* Print out the list of used global functions. */
8236 ia64_hpux_file_end (void)
8238 struct extern_func_list *p;
8240 for (p = extern_func_head; p; p = p->next)
8242 tree decl = p->decl;
8243 tree id = DECL_ASSEMBLER_NAME (decl);
8247 if (!TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (id))
8249 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8251 TREE_ASM_WRITTEN (decl) = 1;
8252 (*targetm.asm_out.globalize_label) (asm_out_file, name);
8253 fputs (TYPE_ASM_OP, asm_out_file);
8254 assemble_name (asm_out_file, name);
8255 fprintf (asm_out_file, "," TYPE_OPERAND_FMT "\n", "function");
8259 extern_func_head = 0;
8262 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8263 modes of word_mode and larger. Rename the TFmode libfuncs using the
8264 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
8265 backward compatibility. */
8268 ia64_init_libfuncs (void)
8270 set_optab_libfunc (sdiv_optab, SImode, "__divsi3");
8271 set_optab_libfunc (udiv_optab, SImode, "__udivsi3");
8272 set_optab_libfunc (smod_optab, SImode, "__modsi3");
8273 set_optab_libfunc (umod_optab, SImode, "__umodsi3");
8275 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
8276 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
8277 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
8278 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
8279 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
8281 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
8282 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
8283 set_conv_libfunc (sext_optab, TFmode, XFmode, "_U_Qfcnvff_f80_to_quad");
8284 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
8285 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
8286 set_conv_libfunc (trunc_optab, XFmode, TFmode, "_U_Qfcnvff_quad_to_f80");
8288 set_conv_libfunc (sfix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_sgl");
8289 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
8290 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxut_quad_to_sgl");
8291 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxut_quad_to_dbl");
8293 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
8294 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
8297 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8300 ia64_hpux_init_libfuncs (void)
8302 ia64_init_libfuncs ();
8304 set_optab_libfunc (smin_optab, TFmode, "_U_Qfmin");
8305 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
8306 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
8308 /* ia64_expand_compare uses this. */
8309 cmptf_libfunc = init_one_libfunc ("_U_Qfcmp");
8311 /* These should never be used. */
8312 set_optab_libfunc (eq_optab, TFmode, 0);
8313 set_optab_libfunc (ne_optab, TFmode, 0);
8314 set_optab_libfunc (gt_optab, TFmode, 0);
8315 set_optab_libfunc (ge_optab, TFmode, 0);
8316 set_optab_libfunc (lt_optab, TFmode, 0);
8317 set_optab_libfunc (le_optab, TFmode, 0);
8320 /* Rename the division and modulus functions in VMS. */
8323 ia64_vms_init_libfuncs (void)
8325 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
8326 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
8327 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
8328 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
8329 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
8330 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
8331 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
8332 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
8335 /* Rename the TFmode libfuncs available from soft-fp in glibc using
8336 the HPUX conventions. */
8339 ia64_sysv4_init_libfuncs (void)
8341 ia64_init_libfuncs ();
8343 /* These functions are not part of the HPUX TFmode interface. We
8344 use them instead of _U_Qfcmp, which doesn't work the way we
8346 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
8347 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
8348 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
8349 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
8350 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
8351 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
8353 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
8354 glibc doesn't have them. */
8357 /* Switch to the section to which we should output X. The only thing
8358 special we do here is to honor small data. */
8361 ia64_select_rtx_section (enum machine_mode mode, rtx x,
8362 unsigned HOST_WIDE_INT align)
8364 if (GET_MODE_SIZE (mode) > 0
8365 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8368 default_elf_select_rtx_section (mode, x, align);
8371 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8372 Pretend flag_pic is always set. */
8375 ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
8377 default_elf_select_section_1 (exp, reloc, align, true);
8381 ia64_rwreloc_unique_section (tree decl, int reloc)
8383 default_unique_section_1 (decl, reloc, true);
8387 ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
8388 unsigned HOST_WIDE_INT align)
8390 int save_pic = flag_pic;
8392 ia64_select_rtx_section (mode, x, align);
8393 flag_pic = save_pic;
8396 #ifndef TARGET_RWRELOC
8397 #define TARGET_RWRELOC flag_pic
8401 ia64_section_type_flags (tree decl, const char *name, int reloc)
8403 unsigned int flags = 0;
8405 if (strcmp (name, ".sdata") == 0
8406 || strncmp (name, ".sdata.", 7) == 0
8407 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
8408 || strncmp (name, ".sdata2.", 8) == 0
8409 || strncmp (name, ".gnu.linkonce.s2.", 17) == 0
8410 || strcmp (name, ".sbss") == 0
8411 || strncmp (name, ".sbss.", 6) == 0
8412 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
8413 flags = SECTION_SMALL;
8415 flags |= default_section_type_flags_1 (decl, name, reloc, TARGET_RWRELOC);
8419 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8420 structure type and that the address of that type should be passed
8421 in out0, rather than in r8. */
8424 ia64_struct_retval_addr_is_first_parm_p (tree fntype)
8426 tree ret_type = TREE_TYPE (fntype);
8428 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8429 as the structure return address parameter, if the return value
8430 type has a non-trivial copy constructor or destructor. It is not
8431 clear if this same convention should be used for other
8432 programming languages. Until G++ 3.4, we incorrectly used r8 for
8433 these return values. */
8434 return (abi_version_at_least (2)
8436 && TYPE_MODE (ret_type) == BLKmode
8437 && TREE_ADDRESSABLE (ret_type)
8438 && strcmp (lang_hooks.name, "GNU C++") == 0);
8441 /* Output the assembler code for a thunk function. THUNK_DECL is the
8442 declaration for the thunk function itself, FUNCTION is the decl for
8443 the target function. DELTA is an immediate constant offset to be
8444 added to THIS. If VCALL_OFFSET is nonzero, the word at
8445 *(*this + vcall_offset) should be added to THIS. */
8448 ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
8449 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8452 rtx this, insn, funexp;
8453 unsigned int this_parmno;
8454 unsigned int this_regno;
8456 reload_completed = 1;
8457 epilogue_completed = 1;
8459 reset_block_changes ();
8461 /* Set things up as ia64_expand_prologue might. */
8462 last_scratch_gr_reg = 15;
8464 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8465 current_frame_info.spill_cfa_off = -16;
8466 current_frame_info.n_input_regs = 1;
8467 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8469 /* Mark the end of the (empty) prologue. */
8470 emit_note (NOTE_INSN_PROLOGUE_END);
8472 /* Figure out whether "this" will be the first parameter (the
8473 typical case) or the second parameter (as happens when the
8474 virtual function returns certain class objects). */
8476 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk))
8478 this_regno = IN_REG (this_parmno);
8479 if (!TARGET_REG_NAMES)
8480 reg_names[this_regno] = ia64_reg_numbers[this_parmno];
8482 this = gen_rtx_REG (Pmode, this_regno);
8485 rtx tmp = gen_rtx_REG (ptr_mode, this_regno);
8486 REG_POINTER (tmp) = 1;
8487 if (delta && CONST_OK_FOR_I (delta))
8489 emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
8493 emit_insn (gen_ptr_extend (this, tmp));
8496 /* Apply the constant offset, if required. */
8499 rtx delta_rtx = GEN_INT (delta);
8501 if (!CONST_OK_FOR_I (delta))
8503 rtx tmp = gen_rtx_REG (Pmode, 2);
8504 emit_move_insn (tmp, delta_rtx);
8507 emit_insn (gen_adddi3 (this, this, delta_rtx));
8510 /* Apply the offset from the vtable, if required. */
8513 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8514 rtx tmp = gen_rtx_REG (Pmode, 2);
8518 rtx t = gen_rtx_REG (ptr_mode, 2);
8519 REG_POINTER (t) = 1;
8520 emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
8521 if (CONST_OK_FOR_I (vcall_offset))
8523 emit_insn (gen_ptr_extend_plus_imm (tmp, t,
8528 emit_insn (gen_ptr_extend (tmp, t));
8531 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8535 if (!CONST_OK_FOR_J (vcall_offset))
8537 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8538 emit_move_insn (tmp2, vcall_offset_rtx);
8539 vcall_offset_rtx = tmp2;
8541 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8545 emit_move_insn (gen_rtx_REG (ptr_mode, 2),
8546 gen_rtx_MEM (ptr_mode, tmp));
8548 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8550 emit_insn (gen_adddi3 (this, this, tmp));
8553 /* Generate a tail call to the target function. */
8554 if (! TREE_USED (function))
8556 assemble_external (function);
8557 TREE_USED (function) = 1;
8559 funexp = XEXP (DECL_RTL (function), 0);
8560 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8561 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8562 insn = get_last_insn ();
8563 SIBLING_CALL_P (insn) = 1;
8565 /* Code generation for calls relies on splitting. */
8566 reload_completed = 1;
8567 epilogue_completed = 1;
8568 try_split (PATTERN (insn), insn, 0);
8572 /* Run just enough of rest_of_compilation to get the insns emitted.
8573 There's not really enough bulk here to make other passes such as
8574 instruction scheduling worth while. Note that use_thunk calls
8575 assemble_start_function and assemble_end_function. */
8577 insn_locators_initialize ();
8578 emit_all_insn_group_barriers (NULL);
8579 insn = get_insns ();
8580 shorten_branches (insn);
8581 final_start_function (insn, file, 1);
8582 final (insn, file, 1);
8583 final_end_function ();
8585 reload_completed = 0;
8586 epilogue_completed = 0;
8590 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
8593 ia64_struct_value_rtx (tree fntype,
8594 int incoming ATTRIBUTE_UNUSED)
8596 if (fntype && ia64_struct_retval_addr_is_first_parm_p (fntype))
8598 return gen_rtx_REG (Pmode, GR_REG (8));
8602 ia64_scalar_mode_supported_p (enum machine_mode mode)
8628 ia64_vector_mode_supported_p (enum machine_mode mode)
8646 ia64_output_function_profiler (FILE *file, int labelno)
8649 fputs ("\t.prologue 4, r40\n", file);
8651 fputs ("\t.prologue\n\t.save ar.pfs, r40\n", file);
8652 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", file);
8654 if (NO_PROFILE_COUNTERS)
8655 fputs ("\tmov out3 = r0\n\t;;\n", file);
8659 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8661 if (TARGET_AUTO_PIC)
8662 fputs ("\tmovl out3 = @gprel(", file);
8664 fputs ("\taddl out3 = @ltoff(", file);
8665 assemble_name (file, buf);
8666 if (TARGET_AUTO_PIC)
8667 fputs (")\n\t;;\n", file);
8669 fputs ("), r1\n\t;;\n", file);
8672 fputs ("\t.save rp, r42\n", file);
8673 fputs ("\tmov out2 = b0\n", file);
8674 fputs ("\t.body\n", file);
8675 fputs ("\tmov out1 = r1\n", file);
8676 fputs ("\tbr.call.sptk.many b0 = _mcount\n\t;;\n", file);
8679 static GTY(()) rtx mcount_func_rtx;
8681 gen_mcount_func_rtx (void)
8683 if (!mcount_func_rtx)
8684 mcount_func_rtx = init_one_libfunc ("_mcount");
8685 return mcount_func_rtx;
8689 ia64_profile_hook (int labelno)
8693 if (NO_PROFILE_COUNTERS)
8698 const char *label_name;
8699 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8700 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
8701 label = gen_rtx_SYMBOL_REF (Pmode, label_name);
8702 SYMBOL_REF_FLAGS (label) = SYMBOL_FLAG_LOCAL;
8704 ip = gen_reg_rtx (Pmode);
8705 emit_insn (gen_ip_value (ip));
8706 emit_library_call (gen_mcount_func_rtx (), LCT_NORMAL,
8708 gen_rtx_REG (Pmode, BR_REG (0)), Pmode,
8713 /* Return the mangling of TYPE if it is an extended fundamental type. */
8716 ia64_mangle_fundamental_type (tree type)
8718 /* On HP-UX, "long double" is mangled as "e" so __float128 is
8720 if (!TARGET_HPUX && TYPE_MODE (type) == TFmode)
8722 /* On HP-UX, "e" is not available as a mangling of __float80 so use
8723 an extended mangling. Elsewhere, "e" is available since long
8724 double is 80 bits. */
8725 if (TYPE_MODE (type) == XFmode)
8726 return TARGET_HPUX ? "u9__float80" : "e";
8727 if (TYPE_MODE (type) == RFmode)
8732 /* Return the diagnostic message string if conversion from FROMTYPE to
8733 TOTYPE is not allowed, NULL otherwise. */
8735 ia64_invalid_conversion (tree fromtype, tree totype)
8737 /* Reject nontrivial conversion to or from __fpreg. */
8738 if (TYPE_MODE (fromtype) == RFmode
8739 && TYPE_MODE (totype) != RFmode
8740 && TYPE_MODE (totype) != VOIDmode)
8741 return N_("invalid conversion from %<__fpreg%>");
8742 if (TYPE_MODE (totype) == RFmode
8743 && TYPE_MODE (fromtype) != RFmode)
8744 return N_("invalid conversion to %<__fpreg%>");
8748 /* Return the diagnostic message string if the unary operation OP is
8749 not permitted on TYPE, NULL otherwise. */
8751 ia64_invalid_unary_op (int op, tree type)
8753 /* Reject operations on __fpreg other than unary + or &. */
8754 if (TYPE_MODE (type) == RFmode
8755 && op != CONVERT_EXPR
8757 return N_("invalid operation on %<__fpreg%>");
8761 /* Return the diagnostic message string if the binary operation OP is
8762 not permitted on TYPE1 and TYPE2, NULL otherwise. */
8764 ia64_invalid_binary_op (int op ATTRIBUTE_UNUSED, tree type1, tree type2)
8766 /* Reject operations on __fpreg. */
8767 if (TYPE_MODE (type1) == RFmode || TYPE_MODE (type2) == RFmode)
8768 return N_("invalid operation on %<__fpreg%>");
8772 #include "gt-ia64.h"