1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
3 Contributed by James E. Wilson <wilson@cygnus.com> and
4 David Mosberger <davidm@hpl.hp.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
43 #include "basic-block.h"
45 #include "sched-int.h"
48 #include "target-def.h"
51 #include "langhooks.h"
52 #include "cfglayout.h"
54 /* This is used for communication between ASM_OUTPUT_LABEL and
55 ASM_OUTPUT_LABELREF. */
56 int ia64_asm_output_label = 0;
58 /* Define the information needed to generate branch and scc insns. This is
59 stored from the compare operation. */
60 struct rtx_def * ia64_compare_op0;
61 struct rtx_def * ia64_compare_op1;
63 /* Register names for ia64_expand_prologue. */
64 static const char * const ia64_reg_numbers[96] =
65 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
66 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
67 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
68 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
69 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
70 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
71 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
72 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
73 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
74 "r104","r105","r106","r107","r108","r109","r110","r111",
75 "r112","r113","r114","r115","r116","r117","r118","r119",
76 "r120","r121","r122","r123","r124","r125","r126","r127"};
78 /* ??? These strings could be shared with REGISTER_NAMES. */
79 static const char * const ia64_input_reg_names[8] =
80 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
82 /* ??? These strings could be shared with REGISTER_NAMES. */
83 static const char * const ia64_local_reg_names[80] =
84 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
85 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
86 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
87 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
88 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
89 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
90 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
91 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
92 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
93 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
95 /* ??? These strings could be shared with REGISTER_NAMES. */
96 static const char * const ia64_output_reg_names[8] =
97 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
99 /* String used with the -mfixed-range= option. */
100 const char *ia64_fixed_range_string;
102 /* Determines whether we use adds, addl, or movl to generate our
103 TLS immediate offsets. */
104 int ia64_tls_size = 22;
106 /* String used with the -mtls-size= option. */
107 const char *ia64_tls_size_string;
109 /* Which cpu are we scheduling for. */
110 enum processor_type ia64_tune;
112 /* String used with the -tune= option. */
113 const char *ia64_tune_string;
115 /* Determines whether we run our final scheduling pass or not. We always
116 avoid the normal second scheduling pass. */
117 static int ia64_flag_schedule_insns2;
119 /* Variables which are this size or smaller are put in the sdata/sbss
122 unsigned int ia64_section_threshold;
124 /* The following variable is used by the DFA insn scheduler. The value is
125 TRUE if we do insn bundling instead of insn scheduling. */
128 /* Structure to be filled in by ia64_compute_frame_size with register
129 save masks and offsets for the current function. */
131 struct ia64_frame_info
133 HOST_WIDE_INT total_size; /* size of the stack frame, not including
134 the caller's scratch area. */
135 HOST_WIDE_INT spill_cfa_off; /* top of the reg spill area from the cfa. */
136 HOST_WIDE_INT spill_size; /* size of the gr/br/fr spill area. */
137 HOST_WIDE_INT extra_spill_size; /* size of spill area for others. */
138 HARD_REG_SET mask; /* mask of saved registers. */
139 unsigned int gr_used_mask; /* mask of registers in use as gr spill
140 registers or long-term scratches. */
141 int n_spilled; /* number of spilled registers. */
142 int reg_fp; /* register for fp. */
143 int reg_save_b0; /* save register for b0. */
144 int reg_save_pr; /* save register for prs. */
145 int reg_save_ar_pfs; /* save register for ar.pfs. */
146 int reg_save_ar_unat; /* save register for ar.unat. */
147 int reg_save_ar_lc; /* save register for ar.lc. */
148 int reg_save_gp; /* save register for gp. */
149 int n_input_regs; /* number of input registers used. */
150 int n_local_regs; /* number of local registers used. */
151 int n_output_regs; /* number of output registers used. */
152 int n_rotate_regs; /* number of rotating registers used. */
154 char need_regstk; /* true if a .regstk directive needed. */
155 char initialized; /* true if the data is finalized. */
158 /* Current frame information calculated by ia64_compute_frame_size. */
159 static struct ia64_frame_info current_frame_info;
161 static int ia64_use_dfa_pipeline_interface PARAMS ((void));
162 static int ia64_first_cycle_multipass_dfa_lookahead PARAMS ((void));
163 static void ia64_dependencies_evaluation_hook PARAMS ((rtx, rtx));
164 static void ia64_init_dfa_pre_cycle_insn PARAMS ((void));
165 static rtx ia64_dfa_pre_cycle_insn PARAMS ((void));
166 static int ia64_first_cycle_multipass_dfa_lookahead_guard PARAMS ((rtx));
167 static int ia64_dfa_new_cycle PARAMS ((FILE *, int, rtx, int, int, int *));
168 static rtx gen_tls_get_addr PARAMS ((void));
169 static rtx gen_thread_pointer PARAMS ((void));
170 static rtx ia64_expand_tls_address PARAMS ((enum tls_model, rtx, rtx));
171 static int find_gr_spill PARAMS ((int));
172 static int next_scratch_gr_reg PARAMS ((void));
173 static void mark_reg_gr_used_mask PARAMS ((rtx, void *));
174 static void ia64_compute_frame_size PARAMS ((HOST_WIDE_INT));
175 static void setup_spill_pointers PARAMS ((int, rtx, HOST_WIDE_INT));
176 static void finish_spill_pointers PARAMS ((void));
177 static rtx spill_restore_mem PARAMS ((rtx, HOST_WIDE_INT));
178 static void do_spill PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx));
179 static void do_restore PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT));
180 static rtx gen_movdi_x PARAMS ((rtx, rtx, rtx));
181 static rtx gen_fr_spill_x PARAMS ((rtx, rtx, rtx));
182 static rtx gen_fr_restore_x PARAMS ((rtx, rtx, rtx));
184 static enum machine_mode hfa_element_mode PARAMS ((tree, int));
185 static bool ia64_function_ok_for_sibcall PARAMS ((tree, tree));
186 static bool ia64_rtx_costs PARAMS ((rtx, int, int, int *));
187 static void fix_range PARAMS ((const char *));
188 static struct machine_function * ia64_init_machine_status PARAMS ((void));
189 static void emit_insn_group_barriers PARAMS ((FILE *));
190 static void emit_all_insn_group_barriers PARAMS ((FILE *));
191 static void final_emit_insn_group_barriers PARAMS ((FILE *));
192 static void emit_predicate_relation_info PARAMS ((void));
193 static void ia64_reorg PARAMS ((void));
194 static bool ia64_in_small_data_p PARAMS ((tree));
195 static void process_epilogue PARAMS ((void));
196 static int process_set PARAMS ((FILE *, rtx));
198 static rtx ia64_expand_fetch_and_op PARAMS ((optab, enum machine_mode,
200 static rtx ia64_expand_op_and_fetch PARAMS ((optab, enum machine_mode,
202 static rtx ia64_expand_compare_and_swap PARAMS ((enum machine_mode,
205 static rtx ia64_expand_lock_test_and_set PARAMS ((enum machine_mode,
207 static rtx ia64_expand_lock_release PARAMS ((enum machine_mode, tree, rtx));
208 static bool ia64_assemble_integer PARAMS ((rtx, unsigned int, int));
209 static void ia64_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
210 static void ia64_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
211 static void ia64_output_function_end_prologue PARAMS ((FILE *));
213 static int ia64_issue_rate PARAMS ((void));
214 static int ia64_adjust_cost PARAMS ((rtx, rtx, rtx, int));
215 static void ia64_sched_init PARAMS ((FILE *, int, int));
216 static void ia64_sched_finish PARAMS ((FILE *, int));
217 static int ia64_dfa_sched_reorder PARAMS ((FILE *, int, rtx *, int *,
219 static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
220 static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
221 static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
223 static struct bundle_state *get_free_bundle_state PARAMS ((void));
224 static void free_bundle_state PARAMS ((struct bundle_state *));
225 static void initiate_bundle_states PARAMS ((void));
226 static void finish_bundle_states PARAMS ((void));
227 static unsigned bundle_state_hash PARAMS ((const void *));
228 static int bundle_state_eq_p PARAMS ((const void *, const void *));
229 static int insert_bundle_state PARAMS ((struct bundle_state *));
230 static void initiate_bundle_state_table PARAMS ((void));
231 static void finish_bundle_state_table PARAMS ((void));
232 static int try_issue_nops PARAMS ((struct bundle_state *, int));
233 static int try_issue_insn PARAMS ((struct bundle_state *, rtx));
234 static void issue_nops_and_insn PARAMS ((struct bundle_state *, int,
236 static int get_max_pos PARAMS ((state_t));
237 static int get_template PARAMS ((state_t, int));
239 static rtx get_next_important_insn PARAMS ((rtx, rtx));
240 static void bundling PARAMS ((FILE *, int, rtx, rtx));
242 static void ia64_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
243 HOST_WIDE_INT, tree));
244 static void ia64_file_start PARAMS ((void));
246 static void ia64_select_rtx_section PARAMS ((enum machine_mode, rtx,
247 unsigned HOST_WIDE_INT));
248 static void ia64_rwreloc_select_section PARAMS ((tree, int,
249 unsigned HOST_WIDE_INT))
251 static void ia64_rwreloc_unique_section PARAMS ((tree, int))
253 static void ia64_rwreloc_select_rtx_section PARAMS ((enum machine_mode, rtx,
254 unsigned HOST_WIDE_INT))
256 static unsigned int ia64_rwreloc_section_type_flags
257 PARAMS ((tree, const char *, int))
260 static void ia64_hpux_add_extern_decl PARAMS ((const char *name))
262 static void ia64_hpux_file_end PARAMS ((void))
266 /* Table of valid machine attributes. */
267 static const struct attribute_spec ia64_attribute_table[] =
269 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
270 { "syscall_linkage", 0, 0, false, true, true, NULL },
271 { NULL, 0, 0, false, false, false, NULL }
274 /* Initialize the GCC target structure. */
275 #undef TARGET_ATTRIBUTE_TABLE
276 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
278 #undef TARGET_INIT_BUILTINS
279 #define TARGET_INIT_BUILTINS ia64_init_builtins
281 #undef TARGET_EXPAND_BUILTIN
282 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
284 #undef TARGET_ASM_BYTE_OP
285 #define TARGET_ASM_BYTE_OP "\tdata1\t"
286 #undef TARGET_ASM_ALIGNED_HI_OP
287 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
288 #undef TARGET_ASM_ALIGNED_SI_OP
289 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
290 #undef TARGET_ASM_ALIGNED_DI_OP
291 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
292 #undef TARGET_ASM_UNALIGNED_HI_OP
293 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
294 #undef TARGET_ASM_UNALIGNED_SI_OP
295 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
296 #undef TARGET_ASM_UNALIGNED_DI_OP
297 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
298 #undef TARGET_ASM_INTEGER
299 #define TARGET_ASM_INTEGER ia64_assemble_integer
301 #undef TARGET_ASM_FUNCTION_PROLOGUE
302 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
303 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
304 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
305 #undef TARGET_ASM_FUNCTION_EPILOGUE
306 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
308 #undef TARGET_IN_SMALL_DATA_P
309 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
311 #undef TARGET_SCHED_ADJUST_COST
312 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
313 #undef TARGET_SCHED_ISSUE_RATE
314 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
315 #undef TARGET_SCHED_VARIABLE_ISSUE
316 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
317 #undef TARGET_SCHED_INIT
318 #define TARGET_SCHED_INIT ia64_sched_init
319 #undef TARGET_SCHED_FINISH
320 #define TARGET_SCHED_FINISH ia64_sched_finish
321 #undef TARGET_SCHED_REORDER
322 #define TARGET_SCHED_REORDER ia64_sched_reorder
323 #undef TARGET_SCHED_REORDER2
324 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
326 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
327 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
329 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
330 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
332 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
333 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
335 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
336 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
337 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
338 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
340 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
341 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
342 ia64_first_cycle_multipass_dfa_lookahead_guard
344 #undef TARGET_SCHED_DFA_NEW_CYCLE
345 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
348 #undef TARGET_HAVE_TLS
349 #define TARGET_HAVE_TLS true
352 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
353 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
355 #undef TARGET_ASM_OUTPUT_MI_THUNK
356 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
357 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
358 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
360 #undef TARGET_ASM_FILE_START
361 #define TARGET_ASM_FILE_START ia64_file_start
363 #undef TARGET_RTX_COSTS
364 #define TARGET_RTX_COSTS ia64_rtx_costs
365 #undef TARGET_ADDRESS_COST
366 #define TARGET_ADDRESS_COST hook_int_rtx_0
368 #undef TARGET_MACHINE_DEPENDENT_REORG
369 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
371 struct gcc_target targetm = TARGET_INITIALIZER;
373 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
376 call_operand (op, mode)
378 enum machine_mode mode;
380 if (mode != GET_MODE (op) && mode != VOIDmode)
383 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG
384 || (GET_CODE (op) == SUBREG && GET_CODE (XEXP (op, 0)) == REG));
387 /* Return 1 if OP refers to a symbol in the sdata section. */
390 sdata_symbolic_operand (op, mode)
392 enum machine_mode mode ATTRIBUTE_UNUSED;
394 switch (GET_CODE (op))
397 if (GET_CODE (XEXP (op, 0)) != PLUS
398 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF)
400 op = XEXP (XEXP (op, 0), 0);
404 if (CONSTANT_POOL_ADDRESS_P (op))
405 return GET_MODE_SIZE (get_pool_mode (op)) <= ia64_section_threshold;
407 return SYMBOL_REF_LOCAL_P (op) && SYMBOL_REF_SMALL_P (op);
416 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
419 got_symbolic_operand (op, mode)
421 enum machine_mode mode ATTRIBUTE_UNUSED;
423 switch (GET_CODE (op))
427 if (GET_CODE (op) != PLUS)
429 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
432 if (GET_CODE (op) != CONST_INT)
437 /* Ok if we're not using GOT entries at all. */
438 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
441 /* "Ok" while emitting rtl, since otherwise we won't be provided
442 with the entire offset during emission, which makes it very
443 hard to split the offset into high and low parts. */
444 if (rtx_equal_function_value_matters)
447 /* Force the low 14 bits of the constant to zero so that we do not
448 use up so many GOT entries. */
449 return (INTVAL (op) & 0x3fff) == 0;
461 /* Return 1 if OP refers to a symbol. */
464 symbolic_operand (op, mode)
466 enum machine_mode mode ATTRIBUTE_UNUSED;
468 switch (GET_CODE (op))
481 /* Return tls_model if OP refers to a TLS symbol. */
484 tls_symbolic_operand (op, mode)
486 enum machine_mode mode ATTRIBUTE_UNUSED;
488 if (GET_CODE (op) != SYMBOL_REF)
490 return SYMBOL_REF_TLS_MODEL (op);
494 /* Return 1 if OP refers to a function. */
497 function_operand (op, mode)
499 enum machine_mode mode ATTRIBUTE_UNUSED;
501 if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
507 /* Return 1 if OP is setjmp or a similar function. */
509 /* ??? This is an unsatisfying solution. Should rethink. */
512 setjmp_operand (op, mode)
514 enum machine_mode mode ATTRIBUTE_UNUSED;
519 if (GET_CODE (op) != SYMBOL_REF)
524 /* The following code is borrowed from special_function_p in calls.c. */
526 /* Disregard prefix _, __ or __x. */
529 if (name[1] == '_' && name[2] == 'x')
531 else if (name[1] == '_')
541 && (! strcmp (name, "setjmp")
542 || ! strcmp (name, "setjmp_syscall")))
544 && ! strcmp (name, "sigsetjmp"))
546 && ! strcmp (name, "savectx")));
548 else if ((name[0] == 'q' && name[1] == 's'
549 && ! strcmp (name, "qsetjmp"))
550 || (name[0] == 'v' && name[1] == 'f'
551 && ! strcmp (name, "vfork")))
557 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
560 move_operand (op, mode)
562 enum machine_mode mode;
564 return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
567 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
570 gr_register_operand (op, mode)
572 enum machine_mode mode;
574 if (! register_operand (op, mode))
576 if (GET_CODE (op) == SUBREG)
577 op = SUBREG_REG (op);
578 if (GET_CODE (op) == REG)
580 unsigned int regno = REGNO (op);
581 if (regno < FIRST_PSEUDO_REGISTER)
582 return GENERAL_REGNO_P (regno);
587 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
590 fr_register_operand (op, mode)
592 enum machine_mode mode;
594 if (! register_operand (op, mode))
596 if (GET_CODE (op) == SUBREG)
597 op = SUBREG_REG (op);
598 if (GET_CODE (op) == REG)
600 unsigned int regno = REGNO (op);
601 if (regno < FIRST_PSEUDO_REGISTER)
602 return FR_REGNO_P (regno);
607 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
610 grfr_register_operand (op, mode)
612 enum machine_mode mode;
614 if (! register_operand (op, mode))
616 if (GET_CODE (op) == SUBREG)
617 op = SUBREG_REG (op);
618 if (GET_CODE (op) == REG)
620 unsigned int regno = REGNO (op);
621 if (regno < FIRST_PSEUDO_REGISTER)
622 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
627 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
630 gr_nonimmediate_operand (op, mode)
632 enum machine_mode mode;
634 if (! nonimmediate_operand (op, mode))
636 if (GET_CODE (op) == SUBREG)
637 op = SUBREG_REG (op);
638 if (GET_CODE (op) == REG)
640 unsigned int regno = REGNO (op);
641 if (regno < FIRST_PSEUDO_REGISTER)
642 return GENERAL_REGNO_P (regno);
647 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
650 fr_nonimmediate_operand (op, mode)
652 enum machine_mode mode;
654 if (! nonimmediate_operand (op, mode))
656 if (GET_CODE (op) == SUBREG)
657 op = SUBREG_REG (op);
658 if (GET_CODE (op) == REG)
660 unsigned int regno = REGNO (op);
661 if (regno < FIRST_PSEUDO_REGISTER)
662 return FR_REGNO_P (regno);
667 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
670 grfr_nonimmediate_operand (op, mode)
672 enum machine_mode mode;
674 if (! nonimmediate_operand (op, mode))
676 if (GET_CODE (op) == SUBREG)
677 op = SUBREG_REG (op);
678 if (GET_CODE (op) == REG)
680 unsigned int regno = REGNO (op);
681 if (regno < FIRST_PSEUDO_REGISTER)
682 return GENERAL_REGNO_P (regno) || FR_REGNO_P (regno);
687 /* Return 1 if OP is a GR register operand, or zero. */
690 gr_reg_or_0_operand (op, mode)
692 enum machine_mode mode;
694 return (op == const0_rtx || gr_register_operand (op, mode));
697 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
700 gr_reg_or_5bit_operand (op, mode)
702 enum machine_mode mode;
704 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
705 || GET_CODE (op) == CONSTANT_P_RTX
706 || gr_register_operand (op, mode));
709 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
712 gr_reg_or_6bit_operand (op, mode)
714 enum machine_mode mode;
716 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
717 || GET_CODE (op) == CONSTANT_P_RTX
718 || gr_register_operand (op, mode));
721 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
724 gr_reg_or_8bit_operand (op, mode)
726 enum machine_mode mode;
728 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
729 || GET_CODE (op) == CONSTANT_P_RTX
730 || gr_register_operand (op, mode));
733 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
736 grfr_reg_or_8bit_operand (op, mode)
738 enum machine_mode mode;
740 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
741 || GET_CODE (op) == CONSTANT_P_RTX
742 || grfr_register_operand (op, mode));
745 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
749 gr_reg_or_8bit_adjusted_operand (op, mode)
751 enum machine_mode mode;
753 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
754 || GET_CODE (op) == CONSTANT_P_RTX
755 || gr_register_operand (op, mode));
758 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
759 immediate and an 8 bit adjusted immediate operand. This is necessary
760 because when we emit a compare, we don't know what the condition will be,
761 so we need the union of the immediates accepted by GT and LT. */
764 gr_reg_or_8bit_and_adjusted_operand (op, mode)
766 enum machine_mode mode;
768 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
769 && CONST_OK_FOR_L (INTVAL (op)))
770 || GET_CODE (op) == CONSTANT_P_RTX
771 || gr_register_operand (op, mode));
774 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
777 gr_reg_or_14bit_operand (op, mode)
779 enum machine_mode mode;
781 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
782 || GET_CODE (op) == CONSTANT_P_RTX
783 || gr_register_operand (op, mode));
786 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
789 gr_reg_or_22bit_operand (op, mode)
791 enum machine_mode mode;
793 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
794 || GET_CODE (op) == CONSTANT_P_RTX
795 || gr_register_operand (op, mode));
798 /* Return 1 if OP is a 6 bit immediate operand. */
801 shift_count_operand (op, mode)
803 enum machine_mode mode ATTRIBUTE_UNUSED;
805 return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
806 || GET_CODE (op) == CONSTANT_P_RTX);
809 /* Return 1 if OP is a 5 bit immediate operand. */
812 shift_32bit_count_operand (op, mode)
814 enum machine_mode mode ATTRIBUTE_UNUSED;
816 return ((GET_CODE (op) == CONST_INT
817 && (INTVAL (op) >= 0 && INTVAL (op) < 32))
818 || GET_CODE (op) == CONSTANT_P_RTX);
821 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
824 shladd_operand (op, mode)
826 enum machine_mode mode ATTRIBUTE_UNUSED;
828 return (GET_CODE (op) == CONST_INT
829 && (INTVAL (op) == 2 || INTVAL (op) == 4
830 || INTVAL (op) == 8 || INTVAL (op) == 16));
833 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
836 fetchadd_operand (op, mode)
838 enum machine_mode mode ATTRIBUTE_UNUSED;
840 return (GET_CODE (op) == CONST_INT
841 && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
842 INTVAL (op) == -4 || INTVAL (op) == -1 ||
843 INTVAL (op) == 1 || INTVAL (op) == 4 ||
844 INTVAL (op) == 8 || INTVAL (op) == 16));
847 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
850 fr_reg_or_fp01_operand (op, mode)
852 enum machine_mode mode;
854 return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
855 || fr_register_operand (op, mode));
858 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
859 POST_MODIFY with a REG as displacement. */
862 destination_operand (op, mode)
864 enum machine_mode mode;
866 if (! nonimmediate_operand (op, mode))
868 if (GET_CODE (op) == MEM
869 && GET_CODE (XEXP (op, 0)) == POST_MODIFY
870 && GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) == REG)
875 /* Like memory_operand, but don't allow post-increments. */
878 not_postinc_memory_operand (op, mode)
880 enum machine_mode mode;
882 return (memory_operand (op, mode)
883 && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
886 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
887 signed immediate operand. */
890 normal_comparison_operator (op, mode)
892 enum machine_mode mode;
894 enum rtx_code code = GET_CODE (op);
895 return ((mode == VOIDmode || GET_MODE (op) == mode)
896 && (code == EQ || code == NE
897 || code == GT || code == LE || code == GTU || code == LEU));
900 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
901 signed immediate operand. */
904 adjusted_comparison_operator (op, mode)
906 enum machine_mode mode;
908 enum rtx_code code = GET_CODE (op);
909 return ((mode == VOIDmode || GET_MODE (op) == mode)
910 && (code == LT || code == GE || code == LTU || code == GEU));
913 /* Return 1 if this is a signed inequality operator. */
916 signed_inequality_operator (op, mode)
918 enum machine_mode mode;
920 enum rtx_code code = GET_CODE (op);
921 return ((mode == VOIDmode || GET_MODE (op) == mode)
922 && (code == GE || code == GT
923 || code == LE || code == LT));
926 /* Return 1 if this operator is valid for predication. */
929 predicate_operator (op, mode)
931 enum machine_mode mode;
933 enum rtx_code code = GET_CODE (op);
934 return ((GET_MODE (op) == mode || mode == VOIDmode)
935 && (code == EQ || code == NE));
938 /* Return 1 if this operator can be used in a conditional operation. */
941 condop_operator (op, mode)
943 enum machine_mode mode;
945 enum rtx_code code = GET_CODE (op);
946 return ((GET_MODE (op) == mode || mode == VOIDmode)
947 && (code == PLUS || code == MINUS || code == AND
948 || code == IOR || code == XOR));
951 /* Return 1 if this is the ar.lc register. */
954 ar_lc_reg_operand (op, mode)
956 enum machine_mode mode;
958 return (GET_MODE (op) == DImode
959 && (mode == DImode || mode == VOIDmode)
960 && GET_CODE (op) == REG
961 && REGNO (op) == AR_LC_REGNUM);
964 /* Return 1 if this is the ar.ccv register. */
967 ar_ccv_reg_operand (op, mode)
969 enum machine_mode mode;
971 return ((GET_MODE (op) == mode || mode == VOIDmode)
972 && GET_CODE (op) == REG
973 && REGNO (op) == AR_CCV_REGNUM);
976 /* Return 1 if this is the ar.pfs register. */
979 ar_pfs_reg_operand (op, mode)
981 enum machine_mode mode;
983 return ((GET_MODE (op) == mode || mode == VOIDmode)
984 && GET_CODE (op) == REG
985 && REGNO (op) == AR_PFS_REGNUM);
988 /* Like general_operand, but don't allow (mem (addressof)). */
991 general_tfmode_operand (op, mode)
993 enum machine_mode mode;
995 if (! general_operand (op, mode))
997 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1005 destination_tfmode_operand (op, mode)
1007 enum machine_mode mode;
1009 if (! destination_operand (op, mode))
1011 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == ADDRESSOF)
1019 tfreg_or_fp01_operand (op, mode)
1021 enum machine_mode mode;
1023 if (GET_CODE (op) == SUBREG)
1025 return fr_reg_or_fp01_operand (op, mode);
1028 /* Return 1 if OP is valid as a base register in a reg + offset address. */
1031 basereg_operand (op, mode)
1033 enum machine_mode mode;
1035 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
1036 checks from pa.c basereg_operand as well? Seems to be OK without them
1039 return (register_operand (op, mode) &&
1040 REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
1043 /* Return 1 if the operands of a move are ok. */
1046 ia64_move_ok (dst, src)
1049 /* If we're under init_recog_no_volatile, we'll not be able to use
1050 memory_operand. So check the code directly and don't worry about
1051 the validity of the underlying address, which should have been
1052 checked elsewhere anyway. */
1053 if (GET_CODE (dst) != MEM)
1055 if (GET_CODE (src) == MEM)
1057 if (register_operand (src, VOIDmode))
1060 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1061 if (INTEGRAL_MODE_P (GET_MODE (dst)))
1062 return src == const0_rtx;
1064 return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
1067 /* Return 0 if we are doing C++ code. This optimization fails with
1068 C++ because of GNAT c++/6685. */
1071 addp4_optimize_ok (op1, op2)
1075 if (!strcmp (lang_hooks.name, "GNU C++"))
1078 return (basereg_operand (op1, GET_MODE(op1)) !=
1079 basereg_operand (op2, GET_MODE(op2)));
1082 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1083 Return the length of the field, or <= 0 on failure. */
1086 ia64_depz_field_mask (rop, rshift)
1089 unsigned HOST_WIDE_INT op = INTVAL (rop);
1090 unsigned HOST_WIDE_INT shift = INTVAL (rshift);
1092 /* Get rid of the zero bits we're shifting in. */
1095 /* We must now have a solid block of 1's at bit 0. */
1096 return exact_log2 (op + 1);
1099 /* Expand a symbolic constant load. */
1102 ia64_expand_load_address (dest, src)
1105 if (tls_symbolic_operand (src, VOIDmode))
1107 if (GET_CODE (dest) != REG)
1110 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1111 having to pointer-extend the value afterward. Other forms of address
1112 computation below are also more natural to compute as 64-bit quantities.
1113 If we've been given an SImode destination register, change it. */
1114 if (GET_MODE (dest) != Pmode)
1115 dest = gen_rtx_REG (Pmode, REGNO (dest));
1117 if (TARGET_AUTO_PIC)
1119 emit_insn (gen_load_gprel64 (dest, src));
1122 else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
1124 emit_insn (gen_load_fptr (dest, src));
1127 else if (sdata_symbolic_operand (src, VOIDmode))
1129 emit_insn (gen_load_gprel (dest, src));
1133 if (GET_CODE (src) == CONST
1134 && GET_CODE (XEXP (src, 0)) == PLUS
1135 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
1136 && (INTVAL (XEXP (XEXP (src, 0), 1)) & 0x1fff) != 0)
1138 rtx sym = XEXP (XEXP (src, 0), 0);
1139 HOST_WIDE_INT ofs, hi, lo;
1141 /* Split the offset into a sign extended 14-bit low part
1142 and a complementary high part. */
1143 ofs = INTVAL (XEXP (XEXP (src, 0), 1));
1144 lo = ((ofs & 0x3fff) ^ 0x2000) - 0x2000;
1147 ia64_expand_load_address (dest, plus_constant (sym, hi));
1148 emit_insn (gen_adddi3 (dest, dest, GEN_INT (lo)));
1154 tmp = gen_rtx_HIGH (Pmode, src);
1155 tmp = gen_rtx_PLUS (Pmode, tmp, pic_offset_table_rtx);
1156 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1158 tmp = gen_rtx_LO_SUM (GET_MODE (dest), dest, src);
1159 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
1163 static GTY(()) rtx gen_tls_tga;
1168 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
1172 static GTY(()) rtx thread_pointer_rtx;
1174 gen_thread_pointer ()
1176 if (!thread_pointer_rtx)
1178 thread_pointer_rtx = gen_rtx_REG (Pmode, 13);
1179 RTX_UNCHANGING_P (thread_pointer_rtx) = 1;
1181 return thread_pointer_rtx;
1185 ia64_expand_tls_address (tls_kind, op0, op1)
1186 enum tls_model tls_kind;
1189 rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
1193 case TLS_MODEL_GLOBAL_DYNAMIC:
1196 tga_op1 = gen_reg_rtx (Pmode);
1197 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1198 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1199 RTX_UNCHANGING_P (tga_op1) = 1;
1201 tga_op2 = gen_reg_rtx (Pmode);
1202 emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
1203 tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
1204 RTX_UNCHANGING_P (tga_op2) = 1;
1206 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1207 LCT_CONST, Pmode, 2, tga_op1,
1208 Pmode, tga_op2, Pmode);
1210 insns = get_insns ();
1213 emit_libcall_block (insns, op0, tga_ret, op1);
1216 case TLS_MODEL_LOCAL_DYNAMIC:
1217 /* ??? This isn't the completely proper way to do local-dynamic
1218 If the call to __tls_get_addr is used only by a single symbol,
1219 then we should (somehow) move the dtprel to the second arg
1220 to avoid the extra add. */
1223 tga_op1 = gen_reg_rtx (Pmode);
1224 emit_insn (gen_load_ltoff_dtpmod (tga_op1, op1));
1225 tga_op1 = gen_rtx_MEM (Pmode, tga_op1);
1226 RTX_UNCHANGING_P (tga_op1) = 1;
1228 tga_op2 = const0_rtx;
1230 tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
1231 LCT_CONST, Pmode, 2, tga_op1,
1232 Pmode, tga_op2, Pmode);
1234 insns = get_insns ();
1237 tga_eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1239 tmp = gen_reg_rtx (Pmode);
1240 emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
1242 if (register_operand (op0, Pmode))
1245 tga_ret = gen_reg_rtx (Pmode);
1248 emit_insn (gen_load_dtprel (tga_ret, op1));
1249 emit_insn (gen_adddi3 (tga_ret, tmp, tga_ret));
1252 emit_insn (gen_add_dtprel (tga_ret, tmp, op1));
1254 return (tga_ret == op0 ? NULL_RTX : tga_ret);
1256 case TLS_MODEL_INITIAL_EXEC:
1257 tmp = gen_reg_rtx (Pmode);
1258 emit_insn (gen_load_ltoff_tprel (tmp, op1));
1259 tmp = gen_rtx_MEM (Pmode, tmp);
1260 RTX_UNCHANGING_P (tmp) = 1;
1261 tmp = force_reg (Pmode, tmp);
1263 if (register_operand (op0, Pmode))
1266 op1 = gen_reg_rtx (Pmode);
1267 emit_insn (gen_adddi3 (op1, tmp, gen_thread_pointer ()));
1269 return (op1 == op0 ? NULL_RTX : op1);
1271 case TLS_MODEL_LOCAL_EXEC:
1272 if (register_operand (op0, Pmode))
1275 tmp = gen_reg_rtx (Pmode);
1278 emit_insn (gen_load_tprel (tmp, op1));
1279 emit_insn (gen_adddi3 (tmp, gen_thread_pointer (), tmp));
1282 emit_insn (gen_add_tprel (tmp, gen_thread_pointer (), op1));
1284 return (tmp == op0 ? NULL_RTX : tmp);
1292 ia64_expand_move (op0, op1)
1295 enum machine_mode mode = GET_MODE (op0);
1297 if (!reload_in_progress && !reload_completed && !ia64_move_ok (op0, op1))
1298 op1 = force_reg (mode, op1);
1300 if ((mode == Pmode || mode == ptr_mode) && symbolic_operand (op1, VOIDmode))
1302 enum tls_model tls_kind;
1303 if ((tls_kind = tls_symbolic_operand (op1, VOIDmode)))
1304 return ia64_expand_tls_address (tls_kind, op0, op1);
1306 if (!TARGET_NO_PIC && reload_completed)
1308 ia64_expand_load_address (op0, op1);
1316 /* Split a move from OP1 to OP0 conditional on COND. */
1319 ia64_emit_cond_move (op0, op1, cond)
1322 rtx insn, first = get_last_insn ();
1324 emit_move_insn (op0, op1);
1326 for (insn = get_last_insn (); insn != first; insn = PREV_INSN (insn))
1328 PATTERN (insn) = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond),
1332 /* Split a post-reload TImode reference into two DImode components. */
1335 ia64_split_timode (out, in, scratch)
1339 switch (GET_CODE (in))
1342 out[0] = gen_rtx_REG (DImode, REGNO (in));
1343 out[1] = gen_rtx_REG (DImode, REGNO (in) + 1);
1348 rtx base = XEXP (in, 0);
1350 switch (GET_CODE (base))
1353 out[0] = adjust_address (in, DImode, 0);
1356 base = XEXP (base, 0);
1357 out[0] = adjust_address (in, DImode, 0);
1360 /* Since we're changing the mode, we need to change to POST_MODIFY
1361 as well to preserve the size of the increment. Either that or
1362 do the update in two steps, but we've already got this scratch
1363 register handy so let's use it. */
1365 base = XEXP (base, 0);
1367 = change_address (in, DImode,
1369 (Pmode, base, plus_constant (base, 16)));
1372 base = XEXP (base, 0);
1374 = change_address (in, DImode,
1376 (Pmode, base, plus_constant (base, -16)));
1382 if (scratch == NULL_RTX)
1384 out[1] = change_address (in, DImode, scratch);
1385 return gen_adddi3 (scratch, base, GEN_INT (8));
1390 split_double (in, &out[0], &out[1]);
1398 /* ??? Fixing GR->FR TFmode moves during reload is hard. You need to go
1399 through memory plus an extra GR scratch register. Except that you can
1400 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1401 SECONDARY_RELOAD_CLASS, but not both.
1403 We got into problems in the first place by allowing a construct like
1404 (subreg:TF (reg:TI)), which we got from a union containing a long double.
1405 This solution attempts to prevent this situation from occurring. When
1406 we see something like the above, we spill the inner register to memory. */
1409 spill_tfmode_operand (in, force)
1413 if (GET_CODE (in) == SUBREG
1414 && GET_MODE (SUBREG_REG (in)) == TImode
1415 && GET_CODE (SUBREG_REG (in)) == REG)
1417 rtx mem = gen_mem_addressof (SUBREG_REG (in), NULL_TREE, /*rescan=*/true);
1418 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1420 else if (force && GET_CODE (in) == REG)
1422 rtx mem = gen_mem_addressof (in, NULL_TREE, /*rescan=*/true);
1423 return gen_rtx_MEM (TFmode, copy_to_reg (XEXP (mem, 0)));
1425 else if (GET_CODE (in) == MEM
1426 && GET_CODE (XEXP (in, 0)) == ADDRESSOF)
1427 return change_address (in, TFmode, copy_to_reg (XEXP (in, 0)));
1432 /* Emit comparison instruction if necessary, returning the expression
1433 that holds the compare result in the proper mode. */
1436 ia64_expand_compare (code, mode)
1438 enum machine_mode mode;
1440 rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
1443 /* If we have a BImode input, then we already have a compare result, and
1444 do not need to emit another comparison. */
1445 if (GET_MODE (op0) == BImode)
1447 if ((code == NE || code == EQ) && op1 == const0_rtx)
1454 cmp = gen_reg_rtx (BImode);
1455 emit_insn (gen_rtx_SET (VOIDmode, cmp,
1456 gen_rtx_fmt_ee (code, BImode, op0, op1)));
1460 return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
1463 /* Emit the appropriate sequence for a call. */
1466 ia64_expand_call (retval, addr, nextarg, sibcall_p)
1469 rtx nextarg ATTRIBUTE_UNUSED;
1474 addr = XEXP (addr, 0);
1475 b0 = gen_rtx_REG (DImode, R_BR (0));
1477 /* ??? Should do this for functions known to bind local too. */
1478 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
1481 insn = gen_sibcall_nogp (addr);
1483 insn = gen_call_nogp (addr, b0);
1485 insn = gen_call_value_nogp (retval, addr, b0);
1486 insn = emit_call_insn (insn);
1491 insn = gen_sibcall_gp (addr);
1493 insn = gen_call_gp (addr, b0);
1495 insn = gen_call_value_gp (retval, addr, b0);
1496 insn = emit_call_insn (insn);
1498 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
1502 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), b0);
1510 if (current_frame_info.reg_save_gp)
1511 tmp = gen_rtx_REG (DImode, current_frame_info.reg_save_gp);
1514 HOST_WIDE_INT offset;
1516 offset = (current_frame_info.spill_cfa_off
1517 + current_frame_info.spill_size);
1518 if (frame_pointer_needed)
1520 tmp = hard_frame_pointer_rtx;
1525 tmp = stack_pointer_rtx;
1526 offset = current_frame_info.total_size - offset;
1529 if (CONST_OK_FOR_I (offset))
1530 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1531 tmp, GEN_INT (offset)));
1534 emit_move_insn (pic_offset_table_rtx, GEN_INT (offset));
1535 emit_insn (gen_adddi3 (pic_offset_table_rtx,
1536 pic_offset_table_rtx, tmp));
1539 tmp = gen_rtx_MEM (DImode, pic_offset_table_rtx);
1542 emit_move_insn (pic_offset_table_rtx, tmp);
1546 ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
1547 noreturn_p, sibcall_p)
1548 rtx retval, addr, retaddr, scratch_r, scratch_b;
1549 int noreturn_p, sibcall_p;
1552 bool is_desc = false;
1554 /* If we find we're calling through a register, then we're actually
1555 calling through a descriptor, so load up the values. */
1556 if (REG_P (addr) && GR_REGNO_P (REGNO (addr)))
1561 /* ??? We are currently constrained to *not* use peep2, because
1562 we can legitimiately change the global lifetime of the GP
1563 (in the form of killing where previously live). This is
1564 because a call through a descriptor doesn't use the previous
1565 value of the GP, while a direct call does, and we do not
1566 commit to either form until the split here.
1568 That said, this means that we lack precise life info for
1569 whether ADDR is dead after this call. This is not terribly
1570 important, since we can fix things up essentially for free
1571 with the POST_DEC below, but it's nice to not use it when we
1572 can immediately tell it's not necessary. */
1573 addr_dead_p = ((noreturn_p || sibcall_p
1574 || TEST_HARD_REG_BIT (regs_invalidated_by_call,
1576 && !FUNCTION_ARG_REGNO_P (REGNO (addr)));
1578 /* Load the code address into scratch_b. */
1579 tmp = gen_rtx_POST_INC (Pmode, addr);
1580 tmp = gen_rtx_MEM (Pmode, tmp);
1581 emit_move_insn (scratch_r, tmp);
1582 emit_move_insn (scratch_b, scratch_r);
1584 /* Load the GP address. If ADDR is not dead here, then we must
1585 revert the change made above via the POST_INCREMENT. */
1587 tmp = gen_rtx_POST_DEC (Pmode, addr);
1590 tmp = gen_rtx_MEM (Pmode, tmp);
1591 emit_move_insn (pic_offset_table_rtx, tmp);
1598 insn = gen_sibcall_nogp (addr);
1600 insn = gen_call_value_nogp (retval, addr, retaddr);
1602 insn = gen_call_nogp (addr, retaddr);
1603 emit_call_insn (insn);
1605 if ((!TARGET_CONST_GP || is_desc) && !noreturn_p && !sibcall_p)
1609 /* Begin the assembly file. */
1614 default_file_start ();
1615 emit_safe_across_calls ();
1619 emit_safe_across_calls ()
1621 unsigned int rs, re;
1628 while (rs < 64 && call_used_regs[PR_REG (rs)])
1632 for (re = rs + 1; re < 64 && ! call_used_regs[PR_REG (re)]; re++)
1636 fputs ("\t.pred.safe_across_calls ", asm_out_file);
1640 fputc (',', asm_out_file);
1642 fprintf (asm_out_file, "p%u", rs);
1644 fprintf (asm_out_file, "p%u-p%u", rs, re - 1);
1648 fputc ('\n', asm_out_file);
1651 /* Helper function for ia64_compute_frame_size: find an appropriate general
1652 register to spill some special register to. SPECIAL_SPILL_MASK contains
1653 bits in GR0 to GR31 that have already been allocated by this routine.
1654 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1657 find_gr_spill (try_locals)
1662 /* If this is a leaf function, first try an otherwise unused
1663 call-clobbered register. */
1664 if (current_function_is_leaf)
1666 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1667 if (! regs_ever_live[regno]
1668 && call_used_regs[regno]
1669 && ! fixed_regs[regno]
1670 && ! global_regs[regno]
1671 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1673 current_frame_info.gr_used_mask |= 1 << regno;
1680 regno = current_frame_info.n_local_regs;
1681 /* If there is a frame pointer, then we can't use loc79, because
1682 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1683 reg_name switching code in ia64_expand_prologue. */
1684 if (regno < (80 - frame_pointer_needed))
1686 current_frame_info.n_local_regs = regno + 1;
1687 return LOC_REG (0) + regno;
1691 /* Failed to find a general register to spill to. Must use stack. */
1695 /* In order to make for nice schedules, we try to allocate every temporary
1696 to a different register. We must of course stay away from call-saved,
1697 fixed, and global registers. We must also stay away from registers
1698 allocated in current_frame_info.gr_used_mask, since those include regs
1699 used all through the prologue.
1701 Any register allocated here must be used immediately. The idea is to
1702 aid scheduling, not to solve data flow problems. */
1704 static int last_scratch_gr_reg;
1707 next_scratch_gr_reg ()
1711 for (i = 0; i < 32; ++i)
1713 regno = (last_scratch_gr_reg + i + 1) & 31;
1714 if (call_used_regs[regno]
1715 && ! fixed_regs[regno]
1716 && ! global_regs[regno]
1717 && ((current_frame_info.gr_used_mask >> regno) & 1) == 0)
1719 last_scratch_gr_reg = regno;
1724 /* There must be _something_ available. */
1728 /* Helper function for ia64_compute_frame_size, called through
1729 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
1732 mark_reg_gr_used_mask (reg, data)
1734 void *data ATTRIBUTE_UNUSED;
1736 unsigned int regno = REGNO (reg);
1739 unsigned int i, n = HARD_REGNO_NREGS (regno, GET_MODE (reg));
1740 for (i = 0; i < n; ++i)
1741 current_frame_info.gr_used_mask |= 1 << (regno + i);
1745 /* Returns the number of bytes offset between the frame pointer and the stack
1746 pointer for the current function. SIZE is the number of bytes of space
1747 needed for local variables. */
1750 ia64_compute_frame_size (size)
1753 HOST_WIDE_INT total_size;
1754 HOST_WIDE_INT spill_size = 0;
1755 HOST_WIDE_INT extra_spill_size = 0;
1756 HOST_WIDE_INT pretend_args_size;
1759 int spilled_gr_p = 0;
1760 int spilled_fr_p = 0;
1764 if (current_frame_info.initialized)
1767 memset (¤t_frame_info, 0, sizeof current_frame_info);
1768 CLEAR_HARD_REG_SET (mask);
1770 /* Don't allocate scratches to the return register. */
1771 diddle_return_value (mark_reg_gr_used_mask, NULL);
1773 /* Don't allocate scratches to the EH scratch registers. */
1774 if (cfun->machine->ia64_eh_epilogue_sp)
1775 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_sp, NULL);
1776 if (cfun->machine->ia64_eh_epilogue_bsp)
1777 mark_reg_gr_used_mask (cfun->machine->ia64_eh_epilogue_bsp, NULL);
1779 /* Find the size of the register stack frame. We have only 80 local
1780 registers, because we reserve 8 for the inputs and 8 for the
1783 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
1784 since we'll be adjusting that down later. */
1785 regno = LOC_REG (78) + ! frame_pointer_needed;
1786 for (; regno >= LOC_REG (0); regno--)
1787 if (regs_ever_live[regno])
1789 current_frame_info.n_local_regs = regno - LOC_REG (0) + 1;
1791 /* For functions marked with the syscall_linkage attribute, we must mark
1792 all eight input registers as in use, so that locals aren't visible to
1795 if (cfun->machine->n_varargs > 0
1796 || lookup_attribute ("syscall_linkage",
1797 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
1798 current_frame_info.n_input_regs = 8;
1801 for (regno = IN_REG (7); regno >= IN_REG (0); regno--)
1802 if (regs_ever_live[regno])
1804 current_frame_info.n_input_regs = regno - IN_REG (0) + 1;
1807 for (regno = OUT_REG (7); regno >= OUT_REG (0); regno--)
1808 if (regs_ever_live[regno])
1810 i = regno - OUT_REG (0) + 1;
1812 /* When -p profiling, we need one output register for the mcount argument.
1813 Likewise for -a profiling for the bb_init_func argument. For -ax
1814 profiling, we need two output registers for the two bb_init_trace_func
1816 if (current_function_profile)
1818 current_frame_info.n_output_regs = i;
1820 /* ??? No rotating register support yet. */
1821 current_frame_info.n_rotate_regs = 0;
1823 /* Discover which registers need spilling, and how much room that
1824 will take. Begin with floating point and general registers,
1825 which will always wind up on the stack. */
1827 for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
1828 if (regs_ever_live[regno] && ! call_used_regs[regno])
1830 SET_HARD_REG_BIT (mask, regno);
1836 for (regno = GR_REG (1); regno <= GR_REG (31); regno++)
1837 if (regs_ever_live[regno] && ! call_used_regs[regno])
1839 SET_HARD_REG_BIT (mask, regno);
1845 for (regno = BR_REG (1); regno <= BR_REG (7); regno++)
1846 if (regs_ever_live[regno] && ! call_used_regs[regno])
1848 SET_HARD_REG_BIT (mask, regno);
1853 /* Now come all special registers that might get saved in other
1854 general registers. */
1856 if (frame_pointer_needed)
1858 current_frame_info.reg_fp = find_gr_spill (1);
1859 /* If we did not get a register, then we take LOC79. This is guaranteed
1860 to be free, even if regs_ever_live is already set, because this is
1861 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
1862 as we don't count loc79 above. */
1863 if (current_frame_info.reg_fp == 0)
1865 current_frame_info.reg_fp = LOC_REG (79);
1866 current_frame_info.n_local_regs++;
1870 if (! current_function_is_leaf)
1872 /* Emit a save of BR0 if we call other functions. Do this even
1873 if this function doesn't return, as EH depends on this to be
1874 able to unwind the stack. */
1875 SET_HARD_REG_BIT (mask, BR_REG (0));
1877 current_frame_info.reg_save_b0 = find_gr_spill (1);
1878 if (current_frame_info.reg_save_b0 == 0)
1884 /* Similarly for ar.pfs. */
1885 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1886 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1887 if (current_frame_info.reg_save_ar_pfs == 0)
1889 extra_spill_size += 8;
1893 /* Similarly for gp. Note that if we're calling setjmp, the stacked
1894 registers are clobbered, so we fall back to the stack. */
1895 current_frame_info.reg_save_gp
1896 = (current_function_calls_setjmp ? 0 : find_gr_spill (1));
1897 if (current_frame_info.reg_save_gp == 0)
1899 SET_HARD_REG_BIT (mask, GR_REG (1));
1906 if (regs_ever_live[BR_REG (0)] && ! call_used_regs[BR_REG (0)])
1908 SET_HARD_REG_BIT (mask, BR_REG (0));
1913 if (regs_ever_live[AR_PFS_REGNUM])
1915 SET_HARD_REG_BIT (mask, AR_PFS_REGNUM);
1916 current_frame_info.reg_save_ar_pfs = find_gr_spill (1);
1917 if (current_frame_info.reg_save_ar_pfs == 0)
1919 extra_spill_size += 8;
1925 /* Unwind descriptor hackery: things are most efficient if we allocate
1926 consecutive GR save registers for RP, PFS, FP in that order. However,
1927 it is absolutely critical that FP get the only hard register that's
1928 guaranteed to be free, so we allocated it first. If all three did
1929 happen to be allocated hard regs, and are consecutive, rearrange them
1930 into the preferred order now. */
1931 if (current_frame_info.reg_fp != 0
1932 && current_frame_info.reg_save_b0 == current_frame_info.reg_fp + 1
1933 && current_frame_info.reg_save_ar_pfs == current_frame_info.reg_fp + 2)
1935 current_frame_info.reg_save_b0 = current_frame_info.reg_fp;
1936 current_frame_info.reg_save_ar_pfs = current_frame_info.reg_fp + 1;
1937 current_frame_info.reg_fp = current_frame_info.reg_fp + 2;
1940 /* See if we need to store the predicate register block. */
1941 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1942 if (regs_ever_live[regno] && ! call_used_regs[regno])
1944 if (regno <= PR_REG (63))
1946 SET_HARD_REG_BIT (mask, PR_REG (0));
1947 current_frame_info.reg_save_pr = find_gr_spill (1);
1948 if (current_frame_info.reg_save_pr == 0)
1950 extra_spill_size += 8;
1954 /* ??? Mark them all as used so that register renaming and such
1955 are free to use them. */
1956 for (regno = PR_REG (0); regno <= PR_REG (63); regno++)
1957 regs_ever_live[regno] = 1;
1960 /* If we're forced to use st8.spill, we're forced to save and restore
1961 ar.unat as well. The check for existing liveness allows inline asm
1962 to touch ar.unat. */
1963 if (spilled_gr_p || cfun->machine->n_varargs
1964 || regs_ever_live[AR_UNAT_REGNUM])
1966 regs_ever_live[AR_UNAT_REGNUM] = 1;
1967 SET_HARD_REG_BIT (mask, AR_UNAT_REGNUM);
1968 current_frame_info.reg_save_ar_unat = find_gr_spill (spill_size == 0);
1969 if (current_frame_info.reg_save_ar_unat == 0)
1971 extra_spill_size += 8;
1976 if (regs_ever_live[AR_LC_REGNUM])
1978 SET_HARD_REG_BIT (mask, AR_LC_REGNUM);
1979 current_frame_info.reg_save_ar_lc = find_gr_spill (spill_size == 0);
1980 if (current_frame_info.reg_save_ar_lc == 0)
1982 extra_spill_size += 8;
1987 /* If we have an odd number of words of pretend arguments written to
1988 the stack, then the FR save area will be unaligned. We round the
1989 size of this area up to keep things 16 byte aligned. */
1991 pretend_args_size = IA64_STACK_ALIGN (current_function_pretend_args_size);
1993 pretend_args_size = current_function_pretend_args_size;
1995 total_size = (spill_size + extra_spill_size + size + pretend_args_size
1996 + current_function_outgoing_args_size);
1997 total_size = IA64_STACK_ALIGN (total_size);
1999 /* We always use the 16-byte scratch area provided by the caller, but
2000 if we are a leaf function, there's no one to which we need to provide
2002 if (current_function_is_leaf)
2003 total_size = MAX (0, total_size - 16);
2005 current_frame_info.total_size = total_size;
2006 current_frame_info.spill_cfa_off = pretend_args_size - 16;
2007 current_frame_info.spill_size = spill_size;
2008 current_frame_info.extra_spill_size = extra_spill_size;
2009 COPY_HARD_REG_SET (current_frame_info.mask, mask);
2010 current_frame_info.n_spilled = n_spilled;
2011 current_frame_info.initialized = reload_completed;
2014 /* Compute the initial difference between the specified pair of registers. */
2017 ia64_initial_elimination_offset (from, to)
2020 HOST_WIDE_INT offset;
2022 ia64_compute_frame_size (get_frame_size ());
2025 case FRAME_POINTER_REGNUM:
2026 if (to == HARD_FRAME_POINTER_REGNUM)
2028 if (current_function_is_leaf)
2029 offset = -current_frame_info.total_size;
2031 offset = -(current_frame_info.total_size
2032 - current_function_outgoing_args_size - 16);
2034 else if (to == STACK_POINTER_REGNUM)
2036 if (current_function_is_leaf)
2039 offset = 16 + current_function_outgoing_args_size;
2045 case ARG_POINTER_REGNUM:
2046 /* Arguments start above the 16 byte save area, unless stdarg
2047 in which case we store through the 16 byte save area. */
2048 if (to == HARD_FRAME_POINTER_REGNUM)
2049 offset = 16 - current_function_pretend_args_size;
2050 else if (to == STACK_POINTER_REGNUM)
2051 offset = (current_frame_info.total_size
2052 + 16 - current_function_pretend_args_size);
2057 case RETURN_ADDRESS_POINTER_REGNUM:
2068 /* If there are more than a trivial number of register spills, we use
2069 two interleaved iterators so that we can get two memory references
2072 In order to simplify things in the prologue and epilogue expanders,
2073 we use helper functions to fix up the memory references after the
2074 fact with the appropriate offsets to a POST_MODIFY memory mode.
2075 The following data structure tracks the state of the two iterators
2076 while insns are being emitted. */
2078 struct spill_fill_data
2080 rtx init_after; /* point at which to emit initializations */
2081 rtx init_reg[2]; /* initial base register */
2082 rtx iter_reg[2]; /* the iterator registers */
2083 rtx *prev_addr[2]; /* address of last memory use */
2084 rtx prev_insn[2]; /* the insn corresponding to prev_addr */
2085 HOST_WIDE_INT prev_off[2]; /* last offset */
2086 int n_iter; /* number of iterators in use */
2087 int next_iter; /* next iterator to use */
2088 unsigned int save_gr_used_mask;
2091 static struct spill_fill_data spill_fill_data;
2094 setup_spill_pointers (n_spills, init_reg, cfa_off)
2097 HOST_WIDE_INT cfa_off;
2101 spill_fill_data.init_after = get_last_insn ();
2102 spill_fill_data.init_reg[0] = init_reg;
2103 spill_fill_data.init_reg[1] = init_reg;
2104 spill_fill_data.prev_addr[0] = NULL;
2105 spill_fill_data.prev_addr[1] = NULL;
2106 spill_fill_data.prev_insn[0] = NULL;
2107 spill_fill_data.prev_insn[1] = NULL;
2108 spill_fill_data.prev_off[0] = cfa_off;
2109 spill_fill_data.prev_off[1] = cfa_off;
2110 spill_fill_data.next_iter = 0;
2111 spill_fill_data.save_gr_used_mask = current_frame_info.gr_used_mask;
2113 spill_fill_data.n_iter = 1 + (n_spills > 2);
2114 for (i = 0; i < spill_fill_data.n_iter; ++i)
2116 int regno = next_scratch_gr_reg ();
2117 spill_fill_data.iter_reg[i] = gen_rtx_REG (DImode, regno);
2118 current_frame_info.gr_used_mask |= 1 << regno;
2123 finish_spill_pointers ()
2125 current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
2129 spill_restore_mem (reg, cfa_off)
2131 HOST_WIDE_INT cfa_off;
2133 int iter = spill_fill_data.next_iter;
2134 HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
2135 rtx disp_rtx = GEN_INT (disp);
2138 if (spill_fill_data.prev_addr[iter])
2140 if (CONST_OK_FOR_N (disp))
2142 *spill_fill_data.prev_addr[iter]
2143 = gen_rtx_POST_MODIFY (DImode, spill_fill_data.iter_reg[iter],
2144 gen_rtx_PLUS (DImode,
2145 spill_fill_data.iter_reg[iter],
2147 REG_NOTES (spill_fill_data.prev_insn[iter])
2148 = gen_rtx_EXPR_LIST (REG_INC, spill_fill_data.iter_reg[iter],
2149 REG_NOTES (spill_fill_data.prev_insn[iter]));
2153 /* ??? Could use register post_modify for loads. */
2154 if (! CONST_OK_FOR_I (disp))
2156 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2157 emit_move_insn (tmp, disp_rtx);
2160 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2161 spill_fill_data.iter_reg[iter], disp_rtx));
2164 /* Micro-optimization: if we've created a frame pointer, it's at
2165 CFA 0, which may allow the real iterator to be initialized lower,
2166 slightly increasing parallelism. Also, if there are few saves
2167 it may eliminate the iterator entirely. */
2169 && spill_fill_data.init_reg[iter] == stack_pointer_rtx
2170 && frame_pointer_needed)
2172 mem = gen_rtx_MEM (GET_MODE (reg), hard_frame_pointer_rtx);
2173 set_mem_alias_set (mem, get_varargs_alias_set ());
2181 seq = gen_movdi (spill_fill_data.iter_reg[iter],
2182 spill_fill_data.init_reg[iter]);
2187 if (! CONST_OK_FOR_I (disp))
2189 rtx tmp = gen_rtx_REG (DImode, next_scratch_gr_reg ());
2190 emit_move_insn (tmp, disp_rtx);
2194 emit_insn (gen_adddi3 (spill_fill_data.iter_reg[iter],
2195 spill_fill_data.init_reg[iter],
2202 /* Careful for being the first insn in a sequence. */
2203 if (spill_fill_data.init_after)
2204 insn = emit_insn_after (seq, spill_fill_data.init_after);
2207 rtx first = get_insns ();
2209 insn = emit_insn_before (seq, first);
2211 insn = emit_insn (seq);
2213 spill_fill_data.init_after = insn;
2215 /* If DISP is 0, we may or may not have a further adjustment
2216 afterward. If we do, then the load/store insn may be modified
2217 to be a post-modify. If we don't, then this copy may be
2218 eliminated by copyprop_hardreg_forward, which makes this
2219 insn garbage, which runs afoul of the sanity check in
2220 propagate_one_insn. So mark this insn as legal to delete. */
2222 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
2226 mem = gen_rtx_MEM (GET_MODE (reg), spill_fill_data.iter_reg[iter]);
2228 /* ??? Not all of the spills are for varargs, but some of them are.
2229 The rest of the spills belong in an alias set of their own. But
2230 it doesn't actually hurt to include them here. */
2231 set_mem_alias_set (mem, get_varargs_alias_set ());
2233 spill_fill_data.prev_addr[iter] = &XEXP (mem, 0);
2234 spill_fill_data.prev_off[iter] = cfa_off;
2236 if (++iter >= spill_fill_data.n_iter)
2238 spill_fill_data.next_iter = iter;
2244 do_spill (move_fn, reg, cfa_off, frame_reg)
2245 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2247 HOST_WIDE_INT cfa_off;
2249 int iter = spill_fill_data.next_iter;
2252 mem = spill_restore_mem (reg, cfa_off);
2253 insn = emit_insn ((*move_fn) (mem, reg, GEN_INT (cfa_off)));
2254 spill_fill_data.prev_insn[iter] = insn;
2261 RTX_FRAME_RELATED_P (insn) = 1;
2263 /* Don't even pretend that the unwind code can intuit its way
2264 through a pair of interleaved post_modify iterators. Just
2265 provide the correct answer. */
2267 if (frame_pointer_needed)
2269 base = hard_frame_pointer_rtx;
2274 base = stack_pointer_rtx;
2275 off = current_frame_info.total_size - cfa_off;
2279 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2280 gen_rtx_SET (VOIDmode,
2281 gen_rtx_MEM (GET_MODE (reg),
2282 plus_constant (base, off)),
2289 do_restore (move_fn, reg, cfa_off)
2290 rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
2292 HOST_WIDE_INT cfa_off;
2294 int iter = spill_fill_data.next_iter;
2297 insn = emit_insn ((*move_fn) (reg, spill_restore_mem (reg, cfa_off),
2298 GEN_INT (cfa_off)));
2299 spill_fill_data.prev_insn[iter] = insn;
2302 /* Wrapper functions that discards the CONST_INT spill offset. These
2303 exist so that we can give gr_spill/gr_fill the offset they need and
2304 use a consistent function interface. */
2307 gen_movdi_x (dest, src, offset)
2309 rtx offset ATTRIBUTE_UNUSED;
2311 return gen_movdi (dest, src);
2315 gen_fr_spill_x (dest, src, offset)
2317 rtx offset ATTRIBUTE_UNUSED;
2319 return gen_fr_spill (dest, src);
2323 gen_fr_restore_x (dest, src, offset)
2325 rtx offset ATTRIBUTE_UNUSED;
2327 return gen_fr_restore (dest, src);
2330 /* Called after register allocation to add any instructions needed for the
2331 prologue. Using a prologue insn is favored compared to putting all of the
2332 instructions in output_function_prologue(), since it allows the scheduler
2333 to intermix instructions with the saves of the caller saved registers. In
2334 some cases, it might be necessary to emit a barrier instruction as the last
2335 insn to prevent such scheduling.
2337 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2338 so that the debug info generation code can handle them properly.
2340 The register save area is layed out like so:
2342 [ varargs spill area ]
2343 [ fr register spill area ]
2344 [ br register spill area ]
2345 [ ar register spill area ]
2346 [ pr register spill area ]
2347 [ gr register spill area ] */
2349 /* ??? Get inefficient code when the frame size is larger than can fit in an
2350 adds instruction. */
2353 ia64_expand_prologue ()
2355 rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
2356 int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
2359 ia64_compute_frame_size (get_frame_size ());
2360 last_scratch_gr_reg = 15;
2362 /* If there is no epilogue, then we don't need some prologue insns.
2363 We need to avoid emitting the dead prologue insns, because flow
2364 will complain about them. */
2369 for (e = EXIT_BLOCK_PTR->pred; e ; e = e->pred_next)
2370 if ((e->flags & EDGE_FAKE) == 0
2371 && (e->flags & EDGE_FALLTHRU) != 0)
2373 epilogue_p = (e != NULL);
2378 /* Set the local, input, and output register names. We need to do this
2379 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2380 half. If we use in/loc/out register names, then we get assembler errors
2381 in crtn.S because there is no alloc insn or regstk directive in there. */
2382 if (! TARGET_REG_NAMES)
2384 int inputs = current_frame_info.n_input_regs;
2385 int locals = current_frame_info.n_local_regs;
2386 int outputs = current_frame_info.n_output_regs;
2388 for (i = 0; i < inputs; i++)
2389 reg_names[IN_REG (i)] = ia64_reg_numbers[i];
2390 for (i = 0; i < locals; i++)
2391 reg_names[LOC_REG (i)] = ia64_reg_numbers[inputs + i];
2392 for (i = 0; i < outputs; i++)
2393 reg_names[OUT_REG (i)] = ia64_reg_numbers[inputs + locals + i];
2396 /* Set the frame pointer register name. The regnum is logically loc79,
2397 but of course we'll not have allocated that many locals. Rather than
2398 worrying about renumbering the existing rtxs, we adjust the name. */
2399 /* ??? This code means that we can never use one local register when
2400 there is a frame pointer. loc79 gets wasted in this case, as it is
2401 renamed to a register that will never be used. See also the try_locals
2402 code in find_gr_spill. */
2403 if (current_frame_info.reg_fp)
2405 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
2406 reg_names[HARD_FRAME_POINTER_REGNUM]
2407 = reg_names[current_frame_info.reg_fp];
2408 reg_names[current_frame_info.reg_fp] = tmp;
2411 /* Fix up the return address placeholder. */
2412 /* ??? We can fail if __builtin_return_address is used, and we didn't
2413 allocate a register in which to save b0. I can't think of a way to
2414 eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
2415 then be sure that I got the right one. Further, reload doesn't seem
2416 to care if an eliminable register isn't used, and "eliminates" it
2418 if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
2419 && current_frame_info.reg_save_b0 != 0)
2420 XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
2422 /* We don't need an alloc instruction if we've used no outputs or locals. */
2423 if (current_frame_info.n_local_regs == 0
2424 && current_frame_info.n_output_regs == 0
2425 && current_frame_info.n_input_regs <= current_function_args_info.int_regs
2426 && !TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2428 /* If there is no alloc, but there are input registers used, then we
2429 need a .regstk directive. */
2430 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
2431 ar_pfs_save_reg = NULL_RTX;
2435 current_frame_info.need_regstk = 0;
2437 if (current_frame_info.reg_save_ar_pfs)
2438 regno = current_frame_info.reg_save_ar_pfs;
2440 regno = next_scratch_gr_reg ();
2441 ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
2443 insn = emit_insn (gen_alloc (ar_pfs_save_reg,
2444 GEN_INT (current_frame_info.n_input_regs),
2445 GEN_INT (current_frame_info.n_local_regs),
2446 GEN_INT (current_frame_info.n_output_regs),
2447 GEN_INT (current_frame_info.n_rotate_regs)));
2448 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_pfs != 0);
2451 /* Set up frame pointer, stack pointer, and spill iterators. */
2453 n_varargs = cfun->machine->n_varargs;
2454 setup_spill_pointers (current_frame_info.n_spilled + n_varargs,
2455 stack_pointer_rtx, 0);
2457 if (frame_pointer_needed)
2459 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2460 RTX_FRAME_RELATED_P (insn) = 1;
2463 if (current_frame_info.total_size != 0)
2465 rtx frame_size_rtx = GEN_INT (- current_frame_info.total_size);
2468 if (CONST_OK_FOR_I (- current_frame_info.total_size))
2469 offset = frame_size_rtx;
2472 regno = next_scratch_gr_reg ();
2473 offset = gen_rtx_REG (DImode, regno);
2474 emit_move_insn (offset, frame_size_rtx);
2477 insn = emit_insn (gen_adddi3 (stack_pointer_rtx,
2478 stack_pointer_rtx, offset));
2480 if (! frame_pointer_needed)
2482 RTX_FRAME_RELATED_P (insn) = 1;
2483 if (GET_CODE (offset) != CONST_INT)
2486 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2487 gen_rtx_SET (VOIDmode,
2489 gen_rtx_PLUS (DImode,
2496 /* ??? At this point we must generate a magic insn that appears to
2497 modify the stack pointer, the frame pointer, and all spill
2498 iterators. This would allow the most scheduling freedom. For
2499 now, just hard stop. */
2500 emit_insn (gen_blockage ());
2503 /* Must copy out ar.unat before doing any integer spills. */
2504 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2506 if (current_frame_info.reg_save_ar_unat)
2508 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2511 alt_regno = next_scratch_gr_reg ();
2512 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2513 current_frame_info.gr_used_mask |= 1 << alt_regno;
2516 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2517 insn = emit_move_insn (ar_unat_save_reg, reg);
2518 RTX_FRAME_RELATED_P (insn) = (current_frame_info.reg_save_ar_unat != 0);
2520 /* Even if we're not going to generate an epilogue, we still
2521 need to save the register so that EH works. */
2522 if (! epilogue_p && current_frame_info.reg_save_ar_unat)
2523 emit_insn (gen_prologue_use (ar_unat_save_reg));
2526 ar_unat_save_reg = NULL_RTX;
2528 /* Spill all varargs registers. Do this before spilling any GR registers,
2529 since we want the UNAT bits for the GR registers to override the UNAT
2530 bits from varargs, which we don't care about. */
2533 for (regno = GR_ARG_FIRST + 7; n_varargs > 0; --n_varargs, --regno)
2535 reg = gen_rtx_REG (DImode, regno);
2536 do_spill (gen_gr_spill, reg, cfa_off += 8, NULL_RTX);
2539 /* Locate the bottom of the register save area. */
2540 cfa_off = (current_frame_info.spill_cfa_off
2541 + current_frame_info.spill_size
2542 + current_frame_info.extra_spill_size);
2544 /* Save the predicate register block either in a register or in memory. */
2545 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2547 reg = gen_rtx_REG (DImode, PR_REG (0));
2548 if (current_frame_info.reg_save_pr != 0)
2550 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2551 insn = emit_move_insn (alt_reg, reg);
2553 /* ??? Denote pr spill/fill by a DImode move that modifies all
2554 64 hard registers. */
2555 RTX_FRAME_RELATED_P (insn) = 1;
2557 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2558 gen_rtx_SET (VOIDmode, alt_reg, reg),
2561 /* Even if we're not going to generate an epilogue, we still
2562 need to save the register so that EH works. */
2564 emit_insn (gen_prologue_use (alt_reg));
2568 alt_regno = next_scratch_gr_reg ();
2569 alt_reg = gen_rtx_REG (DImode, alt_regno);
2570 insn = emit_move_insn (alt_reg, reg);
2571 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2576 /* Handle AR regs in numerical order. All of them get special handling. */
2577 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM)
2578 && current_frame_info.reg_save_ar_unat == 0)
2580 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2581 do_spill (gen_movdi_x, ar_unat_save_reg, cfa_off, reg);
2585 /* The alloc insn already copied ar.pfs into a general register. The
2586 only thing we have to do now is copy that register to a stack slot
2587 if we'd not allocated a local register for the job. */
2588 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM)
2589 && current_frame_info.reg_save_ar_pfs == 0)
2591 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2592 do_spill (gen_movdi_x, ar_pfs_save_reg, cfa_off, reg);
2596 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2598 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2599 if (current_frame_info.reg_save_ar_lc != 0)
2601 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2602 insn = emit_move_insn (alt_reg, reg);
2603 RTX_FRAME_RELATED_P (insn) = 1;
2605 /* Even if we're not going to generate an epilogue, we still
2606 need to save the register so that EH works. */
2608 emit_insn (gen_prologue_use (alt_reg));
2612 alt_regno = next_scratch_gr_reg ();
2613 alt_reg = gen_rtx_REG (DImode, alt_regno);
2614 emit_move_insn (alt_reg, reg);
2615 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2620 if (current_frame_info.reg_save_gp)
2622 insn = emit_move_insn (gen_rtx_REG (DImode,
2623 current_frame_info.reg_save_gp),
2624 pic_offset_table_rtx);
2625 /* We don't know for sure yet if this is actually needed, since
2626 we've not split the PIC call patterns. If all of the calls
2627 are indirect, and not followed by any uses of the gp, then
2628 this save is dead. Allow it to go away. */
2630 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, REG_NOTES (insn));
2633 /* We should now be at the base of the gr/br/fr spill area. */
2634 if (cfa_off != (current_frame_info.spill_cfa_off
2635 + current_frame_info.spill_size))
2638 /* Spill all general registers. */
2639 for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
2640 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2642 reg = gen_rtx_REG (DImode, regno);
2643 do_spill (gen_gr_spill, reg, cfa_off, reg);
2647 /* Handle BR0 specially -- it may be getting stored permanently in
2648 some GR register. */
2649 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2651 reg = gen_rtx_REG (DImode, BR_REG (0));
2652 if (current_frame_info.reg_save_b0 != 0)
2654 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2655 insn = emit_move_insn (alt_reg, reg);
2656 RTX_FRAME_RELATED_P (insn) = 1;
2658 /* Even if we're not going to generate an epilogue, we still
2659 need to save the register so that EH works. */
2661 emit_insn (gen_prologue_use (alt_reg));
2665 alt_regno = next_scratch_gr_reg ();
2666 alt_reg = gen_rtx_REG (DImode, alt_regno);
2667 emit_move_insn (alt_reg, reg);
2668 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2673 /* Spill the rest of the BR registers. */
2674 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2675 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2677 alt_regno = next_scratch_gr_reg ();
2678 alt_reg = gen_rtx_REG (DImode, alt_regno);
2679 reg = gen_rtx_REG (DImode, regno);
2680 emit_move_insn (alt_reg, reg);
2681 do_spill (gen_movdi_x, alt_reg, cfa_off, reg);
2685 /* Align the frame and spill all FR registers. */
2686 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2687 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2691 reg = gen_rtx_REG (TFmode, regno);
2692 do_spill (gen_fr_spill_x, reg, cfa_off, reg);
2696 if (cfa_off != current_frame_info.spill_cfa_off)
2699 finish_spill_pointers ();
2702 /* Called after register allocation to add any instructions needed for the
2703 epilogue. Using an epilogue insn is favored compared to putting all of the
2704 instructions in output_function_prologue(), since it allows the scheduler
2705 to intermix instructions with the saves of the caller saved registers. In
2706 some cases, it might be necessary to emit a barrier instruction as the last
2707 insn to prevent such scheduling. */
2710 ia64_expand_epilogue (sibcall_p)
2713 rtx insn, reg, alt_reg, ar_unat_save_reg;
2714 int regno, alt_regno, cfa_off;
2716 ia64_compute_frame_size (get_frame_size ());
2718 /* If there is a frame pointer, then we use it instead of the stack
2719 pointer, so that the stack pointer does not need to be valid when
2720 the epilogue starts. See EXIT_IGNORE_STACK. */
2721 if (frame_pointer_needed)
2722 setup_spill_pointers (current_frame_info.n_spilled,
2723 hard_frame_pointer_rtx, 0);
2725 setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
2726 current_frame_info.total_size);
2728 if (current_frame_info.total_size != 0)
2730 /* ??? At this point we must generate a magic insn that appears to
2731 modify the spill iterators and the frame pointer. This would
2732 allow the most scheduling freedom. For now, just hard stop. */
2733 emit_insn (gen_blockage ());
2736 /* Locate the bottom of the register save area. */
2737 cfa_off = (current_frame_info.spill_cfa_off
2738 + current_frame_info.spill_size
2739 + current_frame_info.extra_spill_size);
2741 /* Restore the predicate registers. */
2742 if (TEST_HARD_REG_BIT (current_frame_info.mask, PR_REG (0)))
2744 if (current_frame_info.reg_save_pr != 0)
2745 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_pr);
2748 alt_regno = next_scratch_gr_reg ();
2749 alt_reg = gen_rtx_REG (DImode, alt_regno);
2750 do_restore (gen_movdi_x, alt_reg, cfa_off);
2753 reg = gen_rtx_REG (DImode, PR_REG (0));
2754 emit_move_insn (reg, alt_reg);
2757 /* Restore the application registers. */
2759 /* Load the saved unat from the stack, but do not restore it until
2760 after the GRs have been restored. */
2761 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2763 if (current_frame_info.reg_save_ar_unat != 0)
2765 = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_unat);
2768 alt_regno = next_scratch_gr_reg ();
2769 ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);
2770 current_frame_info.gr_used_mask |= 1 << alt_regno;
2771 do_restore (gen_movdi_x, ar_unat_save_reg, cfa_off);
2776 ar_unat_save_reg = NULL_RTX;
2778 if (current_frame_info.reg_save_ar_pfs != 0)
2780 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
2781 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2782 emit_move_insn (reg, alt_reg);
2784 else if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_PFS_REGNUM))
2786 alt_regno = next_scratch_gr_reg ();
2787 alt_reg = gen_rtx_REG (DImode, alt_regno);
2788 do_restore (gen_movdi_x, alt_reg, cfa_off);
2790 reg = gen_rtx_REG (DImode, AR_PFS_REGNUM);
2791 emit_move_insn (reg, alt_reg);
2794 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_LC_REGNUM))
2796 if (current_frame_info.reg_save_ar_lc != 0)
2797 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_lc);
2800 alt_regno = next_scratch_gr_reg ();
2801 alt_reg = gen_rtx_REG (DImode, alt_regno);
2802 do_restore (gen_movdi_x, alt_reg, cfa_off);
2805 reg = gen_rtx_REG (DImode, AR_LC_REGNUM);
2806 emit_move_insn (reg, alt_reg);
2809 /* We should now be at the base of the gr/br/fr spill area. */
2810 if (cfa_off != (current_frame_info.spill_cfa_off
2811 + current_frame_info.spill_size))
2814 /* The GP may be stored on the stack in the prologue, but it's
2815 never restored in the epilogue. Skip the stack slot. */
2816 if (TEST_HARD_REG_BIT (current_frame_info.mask, GR_REG (1)))
2819 /* Restore all general registers. */
2820 for (regno = GR_REG (2); regno <= GR_REG (31); ++regno)
2821 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2823 reg = gen_rtx_REG (DImode, regno);
2824 do_restore (gen_gr_restore, reg, cfa_off);
2828 /* Restore the branch registers. Handle B0 specially, as it may
2829 have gotten stored in some GR register. */
2830 if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
2832 if (current_frame_info.reg_save_b0 != 0)
2833 alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
2836 alt_regno = next_scratch_gr_reg ();
2837 alt_reg = gen_rtx_REG (DImode, alt_regno);
2838 do_restore (gen_movdi_x, alt_reg, cfa_off);
2841 reg = gen_rtx_REG (DImode, BR_REG (0));
2842 emit_move_insn (reg, alt_reg);
2845 for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
2846 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2848 alt_regno = next_scratch_gr_reg ();
2849 alt_reg = gen_rtx_REG (DImode, alt_regno);
2850 do_restore (gen_movdi_x, alt_reg, cfa_off);
2852 reg = gen_rtx_REG (DImode, regno);
2853 emit_move_insn (reg, alt_reg);
2856 /* Restore floating point registers. */
2857 for (regno = FR_REG (2); regno <= FR_REG (127); ++regno)
2858 if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
2862 reg = gen_rtx_REG (TFmode, regno);
2863 do_restore (gen_fr_restore_x, reg, cfa_off);
2867 /* Restore ar.unat for real. */
2868 if (TEST_HARD_REG_BIT (current_frame_info.mask, AR_UNAT_REGNUM))
2870 reg = gen_rtx_REG (DImode, AR_UNAT_REGNUM);
2871 emit_move_insn (reg, ar_unat_save_reg);
2874 if (cfa_off != current_frame_info.spill_cfa_off)
2877 finish_spill_pointers ();
2879 if (current_frame_info.total_size || cfun->machine->ia64_eh_epilogue_sp)
2881 /* ??? At this point we must generate a magic insn that appears to
2882 modify the spill iterators, the stack pointer, and the frame
2883 pointer. This would allow the most scheduling freedom. For now,
2885 emit_insn (gen_blockage ());
2888 if (cfun->machine->ia64_eh_epilogue_sp)
2889 emit_move_insn (stack_pointer_rtx, cfun->machine->ia64_eh_epilogue_sp);
2890 else if (frame_pointer_needed)
2892 insn = emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
2893 RTX_FRAME_RELATED_P (insn) = 1;
2895 else if (current_frame_info.total_size)
2897 rtx offset, frame_size_rtx;
2899 frame_size_rtx = GEN_INT (current_frame_info.total_size);
2900 if (CONST_OK_FOR_I (current_frame_info.total_size))
2901 offset = frame_size_rtx;
2904 regno = next_scratch_gr_reg ();
2905 offset = gen_rtx_REG (DImode, regno);
2906 emit_move_insn (offset, frame_size_rtx);
2909 insn = emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
2912 RTX_FRAME_RELATED_P (insn) = 1;
2913 if (GET_CODE (offset) != CONST_INT)
2916 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2917 gen_rtx_SET (VOIDmode,
2919 gen_rtx_PLUS (DImode,
2926 if (cfun->machine->ia64_eh_epilogue_bsp)
2927 emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
2930 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
2933 int fp = GR_REG (2);
2934 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
2935 first available call clobbered register. If there was a frame_pointer
2936 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
2937 so we have to make sure we're using the string "r2" when emitting
2938 the register name for the assembler. */
2939 if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
2940 fp = HARD_FRAME_POINTER_REGNUM;
2942 /* We must emit an alloc to force the input registers to become output
2943 registers. Otherwise, if the callee tries to pass its parameters
2944 through to another call without an intervening alloc, then these
2946 /* ??? We don't need to preserve all input registers. We only need to
2947 preserve those input registers used as arguments to the sibling call.
2948 It is unclear how to compute that number here. */
2949 if (current_frame_info.n_input_regs != 0)
2950 emit_insn (gen_alloc (gen_rtx_REG (DImode, fp),
2951 GEN_INT (0), GEN_INT (0),
2952 GEN_INT (current_frame_info.n_input_regs),
2957 /* Return 1 if br.ret can do all the work required to return from a
2961 ia64_direct_return ()
2963 if (reload_completed && ! frame_pointer_needed)
2965 ia64_compute_frame_size (get_frame_size ());
2967 return (current_frame_info.total_size == 0
2968 && current_frame_info.n_spilled == 0
2969 && current_frame_info.reg_save_b0 == 0
2970 && current_frame_info.reg_save_pr == 0
2971 && current_frame_info.reg_save_ar_pfs == 0
2972 && current_frame_info.reg_save_ar_unat == 0
2973 && current_frame_info.reg_save_ar_lc == 0);
2979 ia64_hard_regno_rename_ok (from, to)
2983 /* Don't clobber any of the registers we reserved for the prologue. */
2984 if (to == current_frame_info.reg_fp
2985 || to == current_frame_info.reg_save_b0
2986 || to == current_frame_info.reg_save_pr
2987 || to == current_frame_info.reg_save_ar_pfs
2988 || to == current_frame_info.reg_save_ar_unat
2989 || to == current_frame_info.reg_save_ar_lc)
2992 if (from == current_frame_info.reg_fp
2993 || from == current_frame_info.reg_save_b0
2994 || from == current_frame_info.reg_save_pr
2995 || from == current_frame_info.reg_save_ar_pfs
2996 || from == current_frame_info.reg_save_ar_unat
2997 || from == current_frame_info.reg_save_ar_lc)
3000 /* Don't use output registers outside the register frame. */
3001 if (OUT_REGNO_P (to) && to >= OUT_REG (current_frame_info.n_output_regs))
3004 /* Retain even/oddness on predicate register pairs. */
3005 if (PR_REGNO_P (from) && PR_REGNO_P (to))
3006 return (from & 1) == (to & 1);
3011 /* Target hook for assembling integer objects. Handle word-sized
3012 aligned objects and detect the cases when @fptr is needed. */
3015 ia64_assemble_integer (x, size, aligned_p)
3020 if (size == (TARGET_ILP32 ? 4 : 8)
3022 && !(TARGET_NO_PIC || TARGET_AUTO_PIC)
3023 && GET_CODE (x) == SYMBOL_REF
3024 && SYMBOL_REF_FUNCTION_P (x))
3027 fputs ("\tdata4\t@fptr(", asm_out_file);
3029 fputs ("\tdata8\t@fptr(", asm_out_file);
3030 output_addr_const (asm_out_file, x);
3031 fputs (")\n", asm_out_file);
3034 return default_assemble_integer (x, size, aligned_p);
3037 /* Emit the function prologue. */
3040 ia64_output_function_prologue (file, size)
3042 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3044 int mask, grsave, grsave_prev;
3046 if (current_frame_info.need_regstk)
3047 fprintf (file, "\t.regstk %d, %d, %d, %d\n",
3048 current_frame_info.n_input_regs,
3049 current_frame_info.n_local_regs,
3050 current_frame_info.n_output_regs,
3051 current_frame_info.n_rotate_regs);
3053 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3056 /* Emit the .prologue directive. */
3059 grsave = grsave_prev = 0;
3060 if (current_frame_info.reg_save_b0 != 0)
3063 grsave = grsave_prev = current_frame_info.reg_save_b0;
3065 if (current_frame_info.reg_save_ar_pfs != 0
3066 && (grsave_prev == 0
3067 || current_frame_info.reg_save_ar_pfs == grsave_prev + 1))
3070 if (grsave_prev == 0)
3071 grsave = current_frame_info.reg_save_ar_pfs;
3072 grsave_prev = current_frame_info.reg_save_ar_pfs;
3074 if (current_frame_info.reg_fp != 0
3075 && (grsave_prev == 0
3076 || current_frame_info.reg_fp == grsave_prev + 1))
3079 if (grsave_prev == 0)
3080 grsave = HARD_FRAME_POINTER_REGNUM;
3081 grsave_prev = current_frame_info.reg_fp;
3083 if (current_frame_info.reg_save_pr != 0
3084 && (grsave_prev == 0
3085 || current_frame_info.reg_save_pr == grsave_prev + 1))
3088 if (grsave_prev == 0)
3089 grsave = current_frame_info.reg_save_pr;
3093 fprintf (file, "\t.prologue %d, %d\n", mask,
3094 ia64_dbx_register_number (grsave));
3096 fputs ("\t.prologue\n", file);
3098 /* Emit a .spill directive, if necessary, to relocate the base of
3099 the register spill area. */
3100 if (current_frame_info.spill_cfa_off != -16)
3101 fprintf (file, "\t.spill %ld\n",
3102 (long) (current_frame_info.spill_cfa_off
3103 + current_frame_info.spill_size));
3106 /* Emit the .body directive at the scheduled end of the prologue. */
3109 ia64_output_function_end_prologue (file)
3112 if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
3115 fputs ("\t.body\n", file);
3118 /* Emit the function epilogue. */
3121 ia64_output_function_epilogue (file, size)
3122 FILE *file ATTRIBUTE_UNUSED;
3123 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3127 /* Reset from the function's potential modifications. */
3128 XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
3130 if (current_frame_info.reg_fp)
3132 const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
3133 reg_names[HARD_FRAME_POINTER_REGNUM]
3134 = reg_names[current_frame_info.reg_fp];
3135 reg_names[current_frame_info.reg_fp] = tmp;
3137 if (! TARGET_REG_NAMES)
3139 for (i = 0; i < current_frame_info.n_input_regs; i++)
3140 reg_names[IN_REG (i)] = ia64_input_reg_names[i];
3141 for (i = 0; i < current_frame_info.n_local_regs; i++)
3142 reg_names[LOC_REG (i)] = ia64_local_reg_names[i];
3143 for (i = 0; i < current_frame_info.n_output_regs; i++)
3144 reg_names[OUT_REG (i)] = ia64_output_reg_names[i];
3147 current_frame_info.initialized = 0;
3151 ia64_dbx_register_number (regno)
3154 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3155 from its home at loc79 to something inside the register frame. We
3156 must perform the same renumbering here for the debug info. */
3157 if (current_frame_info.reg_fp)
3159 if (regno == HARD_FRAME_POINTER_REGNUM)
3160 regno = current_frame_info.reg_fp;
3161 else if (regno == current_frame_info.reg_fp)
3162 regno = HARD_FRAME_POINTER_REGNUM;
3165 if (IN_REGNO_P (regno))
3166 return 32 + regno - IN_REG (0);
3167 else if (LOC_REGNO_P (regno))
3168 return 32 + current_frame_info.n_input_regs + regno - LOC_REG (0);
3169 else if (OUT_REGNO_P (regno))
3170 return (32 + current_frame_info.n_input_regs
3171 + current_frame_info.n_local_regs + regno - OUT_REG (0));
3177 ia64_initialize_trampoline (addr, fnaddr, static_chain)
3178 rtx addr, fnaddr, static_chain;
3180 rtx addr_reg, eight = GEN_INT (8);
3182 /* Load up our iterator. */
3183 addr_reg = gen_reg_rtx (Pmode);
3184 emit_move_insn (addr_reg, addr);
3186 /* The first two words are the fake descriptor:
3187 __ia64_trampoline, ADDR+16. */
3188 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3189 gen_rtx_SYMBOL_REF (Pmode, "__ia64_trampoline"));
3190 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3192 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg),
3193 copy_to_reg (plus_constant (addr, 16)));
3194 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3196 /* The third word is the target descriptor. */
3197 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), fnaddr);
3198 emit_insn (gen_adddi3 (addr_reg, addr_reg, eight));
3200 /* The fourth word is the static chain. */
3201 emit_move_insn (gen_rtx_MEM (Pmode, addr_reg), static_chain);
3204 /* Do any needed setup for a variadic function. CUM has not been updated
3205 for the last named argument which has type TYPE and mode MODE.
3207 We generate the actual spill instructions during prologue generation. */
3210 ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
3211 CUMULATIVE_ARGS cum;
3215 int second_time ATTRIBUTE_UNUSED;
3217 /* Skip the current argument. */
3218 ia64_function_arg_advance (&cum, int_mode, type, 1);
3220 if (cum.words < MAX_ARGUMENT_SLOTS)
3222 int n = MAX_ARGUMENT_SLOTS - cum.words;
3223 *pretend_size = n * UNITS_PER_WORD;
3224 cfun->machine->n_varargs = n;
3228 /* Check whether TYPE is a homogeneous floating point aggregate. If
3229 it is, return the mode of the floating point type that appears
3230 in all leafs. If it is not, return VOIDmode.
3232 An aggregate is a homogeneous floating point aggregate is if all
3233 fields/elements in it have the same floating point type (e.g,
3234 SFmode). 128-bit quad-precision floats are excluded. */
3236 static enum machine_mode
3237 hfa_element_mode (type, nested)
3241 enum machine_mode element_mode = VOIDmode;
3242 enum machine_mode mode;
3243 enum tree_code code = TREE_CODE (type);
3244 int know_element_mode = 0;
3249 case VOID_TYPE: case INTEGER_TYPE: case ENUMERAL_TYPE:
3250 case BOOLEAN_TYPE: case CHAR_TYPE: case POINTER_TYPE:
3251 case OFFSET_TYPE: case REFERENCE_TYPE: case METHOD_TYPE:
3252 case FILE_TYPE: case SET_TYPE: case LANG_TYPE:
3256 /* Fortran complex types are supposed to be HFAs, so we need to handle
3257 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3260 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT
3261 && (TYPE_MODE (type) != TCmode || INTEL_EXTENDED_IEEE_FORMAT))
3262 return mode_for_size (GET_MODE_UNIT_SIZE (TYPE_MODE (type))
3263 * BITS_PER_UNIT, MODE_FLOAT, 0);
3268 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3269 mode if this is contained within an aggregate. */
3270 if (nested && (TYPE_MODE (type) != TFmode || INTEL_EXTENDED_IEEE_FORMAT))
3271 return TYPE_MODE (type);
3276 return hfa_element_mode (TREE_TYPE (type), 1);
3280 case QUAL_UNION_TYPE:
3281 for (t = TYPE_FIELDS (type); t; t = TREE_CHAIN (t))
3283 if (TREE_CODE (t) != FIELD_DECL)
3286 mode = hfa_element_mode (TREE_TYPE (t), 1);
3287 if (know_element_mode)
3289 if (mode != element_mode)
3292 else if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3296 know_element_mode = 1;
3297 element_mode = mode;
3300 return element_mode;
3303 /* If we reach here, we probably have some front-end specific type
3304 that the backend doesn't know about. This can happen via the
3305 aggregate_value_p call in init_function_start. All we can do is
3306 ignore unknown tree types. */
3313 /* Return rtx for register where argument is passed, or zero if it is passed
3316 /* ??? 128-bit quad-precision floats are always passed in general
3320 ia64_function_arg (cum, mode, type, named, incoming)
3321 CUMULATIVE_ARGS *cum;
3322 enum machine_mode mode;
3327 int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
3328 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3329 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3332 enum machine_mode hfa_mode = VOIDmode;
3334 /* Integer and float arguments larger than 8 bytes start at the next even
3335 boundary. Aggregates larger than 8 bytes start at the next even boundary
3336 if the aggregate has 16 byte alignment. Net effect is that types with
3337 alignment greater than 8 start at the next even boundary. */
3338 /* ??? The ABI does not specify how to handle aggregates with alignment from
3339 9 to 15 bytes, or greater than 16. We handle them all as if they had
3340 16 byte alignment. Such aggregates can occur only if gcc extensions are
3342 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3344 && (cum->words & 1))
3347 /* If all argument slots are used, then it must go on the stack. */
3348 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3351 /* Check for and handle homogeneous FP aggregates. */
3353 hfa_mode = hfa_element_mode (type, 0);
3355 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3356 and unprototyped hfas are passed specially. */
3357 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3361 int fp_regs = cum->fp_regs;
3362 int int_regs = cum->words + offset;
3363 int hfa_size = GET_MODE_SIZE (hfa_mode);
3367 /* If prototyped, pass it in FR regs then GR regs.
3368 If not prototyped, pass it in both FR and GR regs.
3370 If this is an SFmode aggregate, then it is possible to run out of
3371 FR regs while GR regs are still left. In that case, we pass the
3372 remaining part in the GR regs. */
3374 /* Fill the FP regs. We do this always. We stop if we reach the end
3375 of the argument, the last FP register, or the last argument slot. */
3377 byte_size = ((mode == BLKmode)
3378 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3379 args_byte_size = int_regs * UNITS_PER_WORD;
3381 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3382 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD)); i++)
3384 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3385 gen_rtx_REG (hfa_mode, (FR_ARG_FIRST
3389 args_byte_size += hfa_size;
3393 /* If no prototype, then the whole thing must go in GR regs. */
3394 if (! cum->prototype)
3396 /* If this is an SFmode aggregate, then we might have some left over
3397 that needs to go in GR regs. */
3398 else if (byte_size != offset)
3399 int_regs += offset / UNITS_PER_WORD;
3401 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3403 for (; offset < byte_size && int_regs < MAX_ARGUMENT_SLOTS; i++)
3405 enum machine_mode gr_mode = DImode;
3407 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3408 then this goes in a GR reg left adjusted/little endian, right
3409 adjusted/big endian. */
3410 /* ??? Currently this is handled wrong, because 4-byte hunks are
3411 always right adjusted/little endian. */
3414 /* If we have an even 4 byte hunk because the aggregate is a
3415 multiple of 4 bytes in size, then this goes in a GR reg right
3416 adjusted/little endian. */
3417 else if (byte_size - offset == 4)
3419 /* Complex floats need to have float mode. */
3420 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3423 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3424 gen_rtx_REG (gr_mode, (basereg
3427 offset += GET_MODE_SIZE (gr_mode);
3428 int_regs += GET_MODE_SIZE (gr_mode) <= UNITS_PER_WORD
3429 ? 1 : GET_MODE_SIZE (gr_mode) / UNITS_PER_WORD;
3432 /* If we ended up using just one location, just return that one loc. */
3434 return XEXP (loc[0], 0);
3436 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3439 /* Integral and aggregates go in general registers. If we have run out of
3440 FR registers, then FP values must also go in general registers. This can
3441 happen when we have a SFmode HFA. */
3442 else if (((mode == TFmode) && ! INTEL_EXTENDED_IEEE_FORMAT)
3443 || (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS))
3445 int byte_size = ((mode == BLKmode)
3446 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3447 if (BYTES_BIG_ENDIAN
3448 && (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
3449 && byte_size < UNITS_PER_WORD
3452 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3453 gen_rtx_REG (DImode,
3454 (basereg + cum->words
3457 return gen_rtx_PARALLEL (mode, gen_rtvec (1, gr_reg));
3460 return gen_rtx_REG (mode, basereg + cum->words + offset);
3464 /* If there is a prototype, then FP values go in a FR register when
3465 named, and in a GR register when unnamed. */
3466 else if (cum->prototype)
3469 return gen_rtx_REG (mode, basereg + cum->words + offset);
3471 return gen_rtx_REG (mode, FR_ARG_FIRST + cum->fp_regs);
3473 /* If there is no prototype, then FP values go in both FR and GR
3477 rtx fp_reg = gen_rtx_EXPR_LIST (VOIDmode,
3478 gen_rtx_REG (mode, (FR_ARG_FIRST
3481 rtx gr_reg = gen_rtx_EXPR_LIST (VOIDmode,
3483 (basereg + cum->words
3487 return gen_rtx_PARALLEL (mode, gen_rtvec (2, fp_reg, gr_reg));
3491 /* Return number of words, at the beginning of the argument, that must be
3492 put in registers. 0 is the argument is entirely in registers or entirely
3496 ia64_function_arg_partial_nregs (cum, mode, type, named)
3497 CUMULATIVE_ARGS *cum;
3498 enum machine_mode mode;
3500 int named ATTRIBUTE_UNUSED;
3502 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3503 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3507 /* Arguments with alignment larger than 8 bytes start at the next even
3509 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3511 && (cum->words & 1))
3514 /* If all argument slots are used, then it must go on the stack. */
3515 if (cum->words + offset >= MAX_ARGUMENT_SLOTS)
3518 /* It doesn't matter whether the argument goes in FR or GR regs. If
3519 it fits within the 8 argument slots, then it goes entirely in
3520 registers. If it extends past the last argument slot, then the rest
3521 goes on the stack. */
3523 if (words + cum->words + offset <= MAX_ARGUMENT_SLOTS)
3526 return MAX_ARGUMENT_SLOTS - cum->words - offset;
3529 /* Update CUM to point after this argument. This is patterned after
3530 ia64_function_arg. */
3533 ia64_function_arg_advance (cum, mode, type, named)
3534 CUMULATIVE_ARGS *cum;
3535 enum machine_mode mode;
3539 int words = (((mode == BLKmode ? int_size_in_bytes (type)
3540 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
3543 enum machine_mode hfa_mode = VOIDmode;
3545 /* If all arg slots are already full, then there is nothing to do. */
3546 if (cum->words >= MAX_ARGUMENT_SLOTS)
3549 /* Arguments with alignment larger than 8 bytes start at the next even
3551 if ((type ? (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3553 && (cum->words & 1))
3556 cum->words += words + offset;
3558 /* Check for and handle homogeneous FP aggregates. */
3560 hfa_mode = hfa_element_mode (type, 0);
3562 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3563 and unprototyped hfas are passed specially. */
3564 if (hfa_mode != VOIDmode && (! cum->prototype || named))
3566 int fp_regs = cum->fp_regs;
3567 /* This is the original value of cum->words + offset. */
3568 int int_regs = cum->words - words;
3569 int hfa_size = GET_MODE_SIZE (hfa_mode);
3573 /* If prototyped, pass it in FR regs then GR regs.
3574 If not prototyped, pass it in both FR and GR regs.
3576 If this is an SFmode aggregate, then it is possible to run out of
3577 FR regs while GR regs are still left. In that case, we pass the
3578 remaining part in the GR regs. */
3580 /* Fill the FP regs. We do this always. We stop if we reach the end
3581 of the argument, the last FP register, or the last argument slot. */
3583 byte_size = ((mode == BLKmode)
3584 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode));
3585 args_byte_size = int_regs * UNITS_PER_WORD;
3587 for (; (offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS
3588 && args_byte_size < (MAX_ARGUMENT_SLOTS * UNITS_PER_WORD));)
3591 args_byte_size += hfa_size;
3595 cum->fp_regs = fp_regs;
3598 /* Integral and aggregates go in general registers. If we have run out of
3599 FR registers, then FP values must also go in general registers. This can
3600 happen when we have a SFmode HFA. */
3601 else if (! FLOAT_MODE_P (mode) || cum->fp_regs == MAX_ARGUMENT_SLOTS)
3602 cum->int_regs = cum->words;
3604 /* If there is a prototype, then FP values go in a FR register when
3605 named, and in a GR register when unnamed. */
3606 else if (cum->prototype)
3609 cum->int_regs = cum->words;
3611 /* ??? Complex types should not reach here. */
3612 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3614 /* If there is no prototype, then FP values go in both FR and GR
3618 /* ??? Complex types should not reach here. */
3619 cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
3620 cum->int_regs = cum->words;
3624 /* Variable sized types are passed by reference. */
3625 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3628 ia64_function_arg_pass_by_reference (cum, mode, type, named)
3629 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
3630 enum machine_mode mode ATTRIBUTE_UNUSED;
3632 int named ATTRIBUTE_UNUSED;
3634 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3637 /* True if it is OK to do sibling call optimization for the specified
3638 call expression EXP. DECL will be the called function, or NULL if
3639 this is an indirect call. */
3641 ia64_function_ok_for_sibcall (decl, exp)
3643 tree exp ATTRIBUTE_UNUSED;
3645 /* Direct calls are always ok. */
3649 /* If TARGET_CONST_GP is in effect, then our caller expects us to
3650 return with our current GP. This means that we'll always have
3651 a GP reload after an indirect call. */
3652 return !ia64_epilogue_uses (R_GR (1));
3656 /* Implement va_arg. */
3659 ia64_va_arg (valist, type)
3664 /* Variable sized types are passed by reference. */
3665 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
3667 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
3668 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
3671 /* Arguments with alignment larger than 8 bytes start at the next even
3673 if (TYPE_ALIGN (type) > 8 * BITS_PER_UNIT)
3675 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
3676 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
3677 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
3678 build_int_2 (-2 * UNITS_PER_WORD, -1));
3679 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
3680 TREE_SIDE_EFFECTS (t) = 1;
3681 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3684 return std_expand_builtin_va_arg (valist, type);
3687 /* Return 1 if function return value returned in memory. Return 0 if it is
3691 ia64_return_in_memory (valtype)
3694 enum machine_mode mode;
3695 enum machine_mode hfa_mode;
3696 HOST_WIDE_INT byte_size;
3698 mode = TYPE_MODE (valtype);
3699 byte_size = GET_MODE_SIZE (mode);
3700 if (mode == BLKmode)
3702 byte_size = int_size_in_bytes (valtype);
3707 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
3709 hfa_mode = hfa_element_mode (valtype, 0);
3710 if (hfa_mode != VOIDmode)
3712 int hfa_size = GET_MODE_SIZE (hfa_mode);
3714 if (byte_size / hfa_size > MAX_ARGUMENT_SLOTS)
3719 else if (byte_size > UNITS_PER_WORD * MAX_INT_RETURN_SLOTS)
3725 /* Return rtx for register that holds the function return value. */
3728 ia64_function_value (valtype, func)
3730 tree func ATTRIBUTE_UNUSED;
3732 enum machine_mode mode;
3733 enum machine_mode hfa_mode;
3735 mode = TYPE_MODE (valtype);
3736 hfa_mode = hfa_element_mode (valtype, 0);
3738 if (hfa_mode != VOIDmode)
3746 hfa_size = GET_MODE_SIZE (hfa_mode);
3747 byte_size = ((mode == BLKmode)
3748 ? int_size_in_bytes (valtype) : GET_MODE_SIZE (mode));
3750 for (i = 0; offset < byte_size; i++)
3752 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3753 gen_rtx_REG (hfa_mode, FR_ARG_FIRST + i),
3759 return XEXP (loc[0], 0);
3761 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3763 else if (FLOAT_TYPE_P (valtype) &&
3764 ((mode != TFmode) || INTEL_EXTENDED_IEEE_FORMAT))
3765 return gen_rtx_REG (mode, FR_ARG_FIRST);
3768 if (BYTES_BIG_ENDIAN
3769 && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
3777 bytesize = int_size_in_bytes (valtype);
3778 for (i = 0; offset < bytesize; i++)
3780 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
3781 gen_rtx_REG (DImode,
3784 offset += UNITS_PER_WORD;
3786 return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
3789 return gen_rtx_REG (mode, GR_RET_FIRST);
3793 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3794 We need to emit DTP-relative relocations. */
3797 ia64_output_dwarf_dtprel (file, size, x)
3804 fputs ("\tdata8.ua\t@dtprel(", file);
3805 output_addr_const (file, x);
3809 /* Print a memory address as an operand to reference that memory location. */
3811 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
3812 also call this from ia64_print_operand for memory addresses. */
3815 ia64_print_operand_address (stream, address)
3816 FILE * stream ATTRIBUTE_UNUSED;
3817 rtx address ATTRIBUTE_UNUSED;
3821 /* Print an operand to an assembler instruction.
3822 C Swap and print a comparison operator.
3823 D Print an FP comparison operator.
3824 E Print 32 - constant, for SImode shifts as extract.
3825 e Print 64 - constant, for DImode rotates.
3826 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
3827 a floating point register emitted normally.
3828 I Invert a predicate register by adding 1.
3829 J Select the proper predicate register for a condition.
3830 j Select the inverse predicate register for a condition.
3831 O Append .acq for volatile load.
3832 P Postincrement of a MEM.
3833 Q Append .rel for volatile store.
3834 S Shift amount for shladd instruction.
3835 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
3836 for Intel assembler.
3837 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
3838 for Intel assembler.
3839 r Print register name, or constant 0 as r0. HP compatibility for
3842 ia64_print_operand (file, x, code)
3852 /* Handled below. */
3857 enum rtx_code c = swap_condition (GET_CODE (x));
3858 fputs (GET_RTX_NAME (c), file);
3863 switch (GET_CODE (x))
3875 str = GET_RTX_NAME (GET_CODE (x));
3882 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x));
3886 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - INTVAL (x));
3890 if (x == CONST0_RTX (GET_MODE (x)))
3891 str = reg_names [FR_REG (0)];
3892 else if (x == CONST1_RTX (GET_MODE (x)))
3893 str = reg_names [FR_REG (1)];
3894 else if (GET_CODE (x) == REG)
3895 str = reg_names [REGNO (x)];
3902 fputs (reg_names [REGNO (x) + 1], file);
3908 unsigned int regno = REGNO (XEXP (x, 0));
3909 if (GET_CODE (x) == EQ)
3913 fputs (reg_names [regno], file);
3918 if (MEM_VOLATILE_P (x))
3919 fputs(".acq", file);
3924 HOST_WIDE_INT value;
3926 switch (GET_CODE (XEXP (x, 0)))
3932 x = XEXP (XEXP (XEXP (x, 0), 1), 1);
3933 if (GET_CODE (x) == CONST_INT)
3935 else if (GET_CODE (x) == REG)
3937 fprintf (file, ", %s", reg_names[REGNO (x)]);
3945 value = GET_MODE_SIZE (GET_MODE (x));
3949 value = - (HOST_WIDE_INT) GET_MODE_SIZE (GET_MODE (x));
3953 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC, value);
3958 if (MEM_VOLATILE_P (x))
3959 fputs(".rel", file);
3963 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3967 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3969 fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
3975 if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
3977 const char *prefix = "0x";
3978 if (INTVAL (x) & 0x80000000)
3980 fprintf (file, "0xffffffff");
3983 fprintf (file, "%s%x", prefix, (int) INTVAL (x) & 0xffffffff);
3989 /* If this operand is the constant zero, write it as register zero.
3990 Any register, zero, or CONST_INT value is OK here. */
3991 if (GET_CODE (x) == REG)
3992 fputs (reg_names[REGNO (x)], file);
3993 else if (x == CONST0_RTX (GET_MODE (x)))
3995 else if (GET_CODE (x) == CONST_INT)
3996 output_addr_const (file, x);
3998 output_operand_lossage ("invalid %%r value");
4005 /* For conditional branches, returns or calls, substitute
4006 sptk, dptk, dpnt, or spnt for %s. */
4007 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
4010 int pred_val = INTVAL (XEXP (x, 0));
4012 /* Guess top and bottom 10% statically predicted. */
4013 if (pred_val < REG_BR_PROB_BASE / 50)
4015 else if (pred_val < REG_BR_PROB_BASE / 2)
4017 else if (pred_val < REG_BR_PROB_BASE / 100 * 98)
4022 else if (GET_CODE (current_output_insn) == CALL_INSN)
4027 fputs (which, file);
4032 x = current_insn_predicate;
4035 unsigned int regno = REGNO (XEXP (x, 0));
4036 if (GET_CODE (x) == EQ)
4038 fprintf (file, "(%s) ", reg_names [regno]);
4043 output_operand_lossage ("ia64_print_operand: unknown code");
4047 switch (GET_CODE (x))
4049 /* This happens for the spill/restore instructions. */
4054 /* ... fall through ... */
4057 fputs (reg_names [REGNO (x)], file);
4062 rtx addr = XEXP (x, 0);
4063 if (GET_RTX_CLASS (GET_CODE (addr)) == 'a')
4064 addr = XEXP (addr, 0);
4065 fprintf (file, "[%s]", reg_names [REGNO (addr)]);
4070 output_addr_const (file, x);
4077 /* Compute a (partial) cost for rtx X. Return true if the complete
4078 cost has been computed, and false if subexpressions should be
4079 scanned. In either case, *TOTAL contains the cost result. */
4080 /* ??? This is incomplete. */
4083 ia64_rtx_costs (x, code, outer_code, total)
4085 int code, outer_code;
4094 *total = CONST_OK_FOR_J (INTVAL (x)) ? 0 : COSTS_N_INSNS (1);
4097 if (CONST_OK_FOR_I (INTVAL (x)))
4099 else if (CONST_OK_FOR_J (INTVAL (x)))
4102 *total = COSTS_N_INSNS (1);
4105 if (CONST_OK_FOR_K (INTVAL (x)) || CONST_OK_FOR_L (INTVAL (x)))
4108 *total = COSTS_N_INSNS (1);
4113 *total = COSTS_N_INSNS (1);
4119 *total = COSTS_N_INSNS (3);
4123 /* For multiplies wider than HImode, we have to go to the FPU,
4124 which normally involves copies. Plus there's the latency
4125 of the multiply itself, and the latency of the instructions to
4126 transfer integer regs to FP regs. */
4127 /* ??? Check for FP mode. */
4128 if (GET_MODE_SIZE (GET_MODE (x)) > 2)
4129 *total = COSTS_N_INSNS (10);
4131 *total = COSTS_N_INSNS (2);
4139 *total = COSTS_N_INSNS (1);
4146 /* We make divide expensive, so that divide-by-constant will be
4147 optimized to a multiply. */
4148 *total = COSTS_N_INSNS (60);
4156 /* Calculate the cost of moving data from a register in class FROM to
4157 one in class TO, using MODE. */
4160 ia64_register_move_cost (mode, from, to)
4161 enum machine_mode mode;
4162 enum reg_class from, to;
4164 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4165 if (to == ADDL_REGS)
4167 if (from == ADDL_REGS)
4170 /* All costs are symmetric, so reduce cases by putting the
4171 lower number class as the destination. */
4174 enum reg_class tmp = to;
4175 to = from, from = tmp;
4178 /* Moving from FR<->GR in TFmode must be more expensive than 2,
4179 so that we get secondary memory reloads. Between FR_REGS,
4180 we have to make this at least as expensive as MEMORY_MOVE_COST
4181 to avoid spectacularly poor register class preferencing. */
4184 if (to != GR_REGS || from != GR_REGS)
4185 return MEMORY_MOVE_COST (mode, to, 0);
4193 /* Moving between PR registers takes two insns. */
4194 if (from == PR_REGS)
4196 /* Moving between PR and anything but GR is impossible. */
4197 if (from != GR_REGS)
4198 return MEMORY_MOVE_COST (mode, to, 0);
4202 /* Moving between BR and anything but GR is impossible. */
4203 if (from != GR_REGS && from != GR_AND_BR_REGS)
4204 return MEMORY_MOVE_COST (mode, to, 0);
4209 /* Moving between AR and anything but GR is impossible. */
4210 if (from != GR_REGS)
4211 return MEMORY_MOVE_COST (mode, to, 0);
4216 case GR_AND_FR_REGS:
4217 case GR_AND_BR_REGS:
4228 /* This function returns the register class required for a secondary
4229 register when copying between one of the registers in CLASS, and X,
4230 using MODE. A return value of NO_REGS means that no secondary register
4234 ia64_secondary_reload_class (class, mode, x)
4235 enum reg_class class;
4236 enum machine_mode mode ATTRIBUTE_UNUSED;
4241 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
4242 regno = true_regnum (x);
4249 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4250 interaction. We end up with two pseudos with overlapping lifetimes
4251 both of which are equiv to the same constant, and both which need
4252 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4253 changes depending on the path length, which means the qty_first_reg
4254 check in make_regs_eqv can give different answers at different times.
4255 At some point I'll probably need a reload_indi pattern to handle
4258 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4259 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4260 non-general registers for good measure. */
4261 if (regno >= 0 && ! GENERAL_REGNO_P (regno))
4264 /* This is needed if a pseudo used as a call_operand gets spilled to a
4266 if (GET_CODE (x) == MEM)
4271 /* Need to go through general registers to get to other class regs. */
4272 if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
4275 /* This can happen when a paradoxical subreg is an operand to the
4277 /* ??? This shouldn't be necessary after instruction scheduling is
4278 enabled, because paradoxical subregs are not accepted by
4279 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4280 stop the paradoxical subreg stupidity in the *_operand functions
4282 if (GET_CODE (x) == MEM
4283 && (GET_MODE (x) == SImode || GET_MODE (x) == HImode
4284 || GET_MODE (x) == QImode))
4287 /* This can happen because of the ior/and/etc patterns that accept FP
4288 registers as operands. If the third operand is a constant, then it
4289 needs to be reloaded into a FP register. */
4290 if (GET_CODE (x) == CONST_INT)
4293 /* This can happen because of register elimination in a muldi3 insn.
4294 E.g. `26107 * (unsigned long)&u'. */
4295 if (GET_CODE (x) == PLUS)
4300 /* ??? This happens if we cse/gcse a BImode value across a call,
4301 and the function has a nonlocal goto. This is because global
4302 does not allocate call crossing pseudos to hard registers when
4303 current_function_has_nonlocal_goto is true. This is relatively
4304 common for C++ programs that use exceptions. To reproduce,
4305 return NO_REGS and compile libstdc++. */
4306 if (GET_CODE (x) == MEM)
4309 /* This can happen when we take a BImode subreg of a DImode value,
4310 and that DImode value winds up in some non-GR register. */
4311 if (regno >= 0 && ! GENERAL_REGNO_P (regno) && ! PR_REGNO_P (regno))
4316 /* Since we have no offsettable memory addresses, we need a temporary
4317 to hold the address of the second word. */
4330 /* Emit text to declare externally defined variables and functions, because
4331 the Intel assembler does not support undefined externals. */
4334 ia64_asm_output_external (file, decl, name)
4339 int save_referenced;
4341 /* GNU as does not need anything here, but the HP linker does need
4342 something for external functions. */
4346 || TREE_CODE (decl) != FUNCTION_DECL
4347 || strstr(name, "__builtin_") == name))
4350 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4351 the linker when we do this, so we need to be careful not to do this for
4352 builtin functions which have no library equivalent. Unfortunately, we
4353 can't tell here whether or not a function will actually be called by
4354 expand_expr, so we pull in library functions even if we may not need
4356 if (! strcmp (name, "__builtin_next_arg")
4357 || ! strcmp (name, "alloca")
4358 || ! strcmp (name, "__builtin_constant_p")
4359 || ! strcmp (name, "__builtin_args_info"))
4363 ia64_hpux_add_extern_decl (name);
4366 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4368 save_referenced = TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl));
4369 if (TREE_CODE (decl) == FUNCTION_DECL)
4370 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
4371 (*targetm.asm_out.globalize_label) (file, name);
4372 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) = save_referenced;
4376 /* Parse the -mfixed-range= option string. */
4379 fix_range (const_str)
4380 const char *const_str;
4383 char *str, *dash, *comma;
4385 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4386 REG2 are either register names or register numbers. The effect
4387 of this option is to mark the registers in the range from REG1 to
4388 REG2 as ``fixed'' so they won't be used by the compiler. This is
4389 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4391 i = strlen (const_str);
4392 str = (char *) alloca (i + 1);
4393 memcpy (str, const_str, i + 1);
4397 dash = strchr (str, '-');
4400 warning ("value of -mfixed-range must have form REG1-REG2");
4405 comma = strchr (dash + 1, ',');
4409 first = decode_reg_name (str);
4412 warning ("unknown register name: %s", str);
4416 last = decode_reg_name (dash + 1);
4419 warning ("unknown register name: %s", dash + 1);
4427 warning ("%s-%s is an empty range", str, dash + 1);
4431 for (i = first; i <= last; ++i)
4432 fixed_regs[i] = call_used_regs[i] = 1;
4442 static struct machine_function *
4443 ia64_init_machine_status ()
4445 return ggc_alloc_cleared (sizeof (struct machine_function));
4448 /* Handle TARGET_OPTIONS switches. */
4451 ia64_override_options ()
4455 const char *const name; /* processor name or nickname. */
4456 const enum processor_type processor;
4458 const processor_alias_table[] =
4460 {"itanium", PROCESSOR_ITANIUM},
4461 {"itanium1", PROCESSOR_ITANIUM},
4462 {"merced", PROCESSOR_ITANIUM},
4463 {"itanium2", PROCESSOR_ITANIUM2},
4464 {"mckinley", PROCESSOR_ITANIUM2},
4467 int const pta_size = ARRAY_SIZE (processor_alias_table);
4470 if (TARGET_AUTO_PIC)
4471 target_flags |= MASK_CONST_GP;
4473 if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
4475 warning ("cannot optimize floating point division for both latency and throughput");
4476 target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
4479 if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
4481 warning ("cannot optimize integer division for both latency and throughput");
4482 target_flags &= ~MASK_INLINE_INT_DIV_THR;
4485 if (ia64_fixed_range_string)
4486 fix_range (ia64_fixed_range_string);
4488 if (ia64_tls_size_string)
4491 unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
4492 if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
4493 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
4495 ia64_tls_size = tmp;
4498 if (!ia64_tune_string)
4499 ia64_tune_string = "itanium2";
4501 for (i = 0; i < pta_size; i++)
4502 if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
4504 ia64_tune = processor_alias_table[i].processor;
4509 error ("bad value (%s) for -tune= switch", ia64_tune_string);
4511 ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
4512 flag_schedule_insns_after_reload = 0;
4514 ia64_section_threshold = g_switch_set ? g_switch_value : IA64_DEFAULT_GVALUE;
4516 init_machine_status = ia64_init_machine_status;
4518 /* Tell the compiler which flavor of TFmode we're using. */
4519 if (INTEL_EXTENDED_IEEE_FORMAT)
4520 real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
4523 static enum attr_itanium_class ia64_safe_itanium_class PARAMS((rtx));
4524 static enum attr_type ia64_safe_type PARAMS((rtx));
4526 static enum attr_itanium_class
4527 ia64_safe_itanium_class (insn)
4530 if (recog_memoized (insn) >= 0)
4531 return get_attr_itanium_class (insn);
4533 return ITANIUM_CLASS_UNKNOWN;
4536 static enum attr_type
4537 ia64_safe_type (insn)
4540 if (recog_memoized (insn) >= 0)
4541 return get_attr_type (insn);
4543 return TYPE_UNKNOWN;
4546 /* The following collection of routines emit instruction group stop bits as
4547 necessary to avoid dependencies. */
4549 /* Need to track some additional registers as far as serialization is
4550 concerned so we can properly handle br.call and br.ret. We could
4551 make these registers visible to gcc, but since these registers are
4552 never explicitly used in gcc generated code, it seems wasteful to
4553 do so (plus it would make the call and return patterns needlessly
4555 #define REG_GP (GR_REG (1))
4556 #define REG_RP (BR_REG (0))
4557 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4558 /* This is used for volatile asms which may require a stop bit immediately
4559 before and after them. */
4560 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4561 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4562 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4564 /* For each register, we keep track of how it has been written in the
4565 current instruction group.
4567 If a register is written unconditionally (no qualifying predicate),
4568 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4570 If a register is written if its qualifying predicate P is true, we
4571 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4572 may be written again by the complement of P (P^1) and when this happens,
4573 WRITE_COUNT gets set to 2.
4575 The result of this is that whenever an insn attempts to write a register
4576 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4578 If a predicate register is written by a floating-point insn, we set
4579 WRITTEN_BY_FP to true.
4581 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4582 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4584 struct reg_write_state
4586 unsigned int write_count : 2;
4587 unsigned int first_pred : 16;
4588 unsigned int written_by_fp : 1;
4589 unsigned int written_by_and : 1;
4590 unsigned int written_by_or : 1;
4593 /* Cumulative info for the current instruction group. */
4594 struct reg_write_state rws_sum[NUM_REGS];
4595 /* Info for the current instruction. This gets copied to rws_sum after a
4596 stop bit is emitted. */
4597 struct reg_write_state rws_insn[NUM_REGS];
4599 /* Indicates whether this is the first instruction after a stop bit,
4600 in which case we don't need another stop bit. Without this, we hit
4601 the abort in ia64_variable_issue when scheduling an alloc. */
4602 static int first_instruction;
4604 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4605 RTL for one instruction. */
4608 unsigned int is_write : 1; /* Is register being written? */
4609 unsigned int is_fp : 1; /* Is register used as part of an fp op? */
4610 unsigned int is_branch : 1; /* Is register used as part of a branch? */
4611 unsigned int is_and : 1; /* Is register used as part of and.orcm? */
4612 unsigned int is_or : 1; /* Is register used as part of or.andcm? */
4613 unsigned int is_sibcall : 1; /* Is this a sibling or normal call? */
4616 static void rws_update PARAMS ((struct reg_write_state *, int,
4617 struct reg_flags, int));
4618 static int rws_access_regno PARAMS ((int, struct reg_flags, int));
4619 static int rws_access_reg PARAMS ((rtx, struct reg_flags, int));
4620 static void update_set_flags PARAMS ((rtx, struct reg_flags *, int *, rtx *));
4621 static int set_src_needs_barrier PARAMS ((rtx, struct reg_flags, int, rtx));
4622 static int rtx_needs_barrier PARAMS ((rtx, struct reg_flags, int));
4623 static void init_insn_group_barriers PARAMS ((void));
4624 static int group_barrier_needed_p PARAMS ((rtx));
4625 static int safe_group_barrier_needed_p PARAMS ((rtx));
4627 /* Update *RWS for REGNO, which is being written by the current instruction,
4628 with predicate PRED, and associated register flags in FLAGS. */
4631 rws_update (rws, regno, flags, pred)
4632 struct reg_write_state *rws;
4634 struct reg_flags flags;
4638 rws[regno].write_count++;
4640 rws[regno].write_count = 2;
4641 rws[regno].written_by_fp |= flags.is_fp;
4642 /* ??? Not tracking and/or across differing predicates. */
4643 rws[regno].written_by_and = flags.is_and;
4644 rws[regno].written_by_or = flags.is_or;
4645 rws[regno].first_pred = pred;
4648 /* Handle an access to register REGNO of type FLAGS using predicate register
4649 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4650 a dependency with an earlier instruction in the same group. */
4653 rws_access_regno (regno, flags, pred)
4655 struct reg_flags flags;
4658 int need_barrier = 0;
4660 if (regno >= NUM_REGS)
4663 if (! PR_REGNO_P (regno))
4664 flags.is_and = flags.is_or = 0;
4670 /* One insn writes same reg multiple times? */
4671 if (rws_insn[regno].write_count > 0)
4674 /* Update info for current instruction. */
4675 rws_update (rws_insn, regno, flags, pred);
4676 write_count = rws_sum[regno].write_count;
4678 switch (write_count)
4681 /* The register has not been written yet. */
4682 rws_update (rws_sum, regno, flags, pred);
4686 /* The register has been written via a predicate. If this is
4687 not a complementary predicate, then we need a barrier. */
4688 /* ??? This assumes that P and P+1 are always complementary
4689 predicates for P even. */
4690 if (flags.is_and && rws_sum[regno].written_by_and)
4692 else if (flags.is_or && rws_sum[regno].written_by_or)
4694 else if ((rws_sum[regno].first_pred ^ 1) != pred)
4696 rws_update (rws_sum, regno, flags, pred);
4700 /* The register has been unconditionally written already. We
4702 if (flags.is_and && rws_sum[regno].written_by_and)
4704 else if (flags.is_or && rws_sum[regno].written_by_or)
4708 rws_sum[regno].written_by_and = flags.is_and;
4709 rws_sum[regno].written_by_or = flags.is_or;
4718 if (flags.is_branch)
4720 /* Branches have several RAW exceptions that allow to avoid
4723 if (REGNO_REG_CLASS (regno) == BR_REGS || regno == AR_PFS_REGNUM)
4724 /* RAW dependencies on branch regs are permissible as long
4725 as the writer is a non-branch instruction. Since we
4726 never generate code that uses a branch register written
4727 by a branch instruction, handling this case is
4731 if (REGNO_REG_CLASS (regno) == PR_REGS
4732 && ! rws_sum[regno].written_by_fp)
4733 /* The predicates of a branch are available within the
4734 same insn group as long as the predicate was written by
4735 something other than a floating-point instruction. */
4739 if (flags.is_and && rws_sum[regno].written_by_and)
4741 if (flags.is_or && rws_sum[regno].written_by_or)
4744 switch (rws_sum[regno].write_count)
4747 /* The register has not been written yet. */
4751 /* The register has been written via a predicate. If this is
4752 not a complementary predicate, then we need a barrier. */
4753 /* ??? This assumes that P and P+1 are always complementary
4754 predicates for P even. */
4755 if ((rws_sum[regno].first_pred ^ 1) != pred)
4760 /* The register has been unconditionally written already. We
4770 return need_barrier;
4774 rws_access_reg (reg, flags, pred)
4776 struct reg_flags flags;
4779 int regno = REGNO (reg);
4780 int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
4783 return rws_access_regno (regno, flags, pred);
4786 int need_barrier = 0;
4788 need_barrier |= rws_access_regno (regno + n, flags, pred);
4789 return need_barrier;
4793 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
4794 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
4797 update_set_flags (x, pflags, ppred, pcond)
4799 struct reg_flags *pflags;
4803 rtx src = SET_SRC (x);
4807 switch (GET_CODE (src))
4813 if (SET_DEST (x) == pc_rtx)
4814 /* X is a conditional branch. */
4818 int is_complemented = 0;
4820 /* X is a conditional move. */
4821 rtx cond = XEXP (src, 0);
4822 if (GET_CODE (cond) == EQ)
4823 is_complemented = 1;
4824 cond = XEXP (cond, 0);
4825 if (GET_CODE (cond) != REG
4826 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4829 if (XEXP (src, 1) == SET_DEST (x)
4830 || XEXP (src, 2) == SET_DEST (x))
4832 /* X is a conditional move that conditionally writes the
4835 /* We need another complement in this case. */
4836 if (XEXP (src, 1) == SET_DEST (x))
4837 is_complemented = ! is_complemented;
4839 *ppred = REGNO (cond);
4840 if (is_complemented)
4844 /* ??? If this is a conditional write to the dest, then this
4845 instruction does not actually read one source. This probably
4846 doesn't matter, because that source is also the dest. */
4847 /* ??? Multiple writes to predicate registers are allowed
4848 if they are all AND type compares, or if they are all OR
4849 type compares. We do not generate such instructions
4852 /* ... fall through ... */
4855 if (GET_RTX_CLASS (GET_CODE (src)) == '<'
4856 && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
4857 /* Set pflags->is_fp to 1 so that we know we're dealing
4858 with a floating point comparison when processing the
4859 destination of the SET. */
4862 /* Discover if this is a parallel comparison. We only handle
4863 and.orcm and or.andcm at present, since we must retain a
4864 strict inverse on the predicate pair. */
4865 else if (GET_CODE (src) == AND)
4867 else if (GET_CODE (src) == IOR)
4874 /* Subroutine of rtx_needs_barrier; this function determines whether the
4875 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
4876 are as in rtx_needs_barrier. COND is an rtx that holds the condition
4880 set_src_needs_barrier (x, flags, pred, cond)
4882 struct reg_flags flags;
4886 int need_barrier = 0;
4888 rtx src = SET_SRC (x);
4890 if (GET_CODE (src) == CALL)
4891 /* We don't need to worry about the result registers that
4892 get written by subroutine call. */
4893 return rtx_needs_barrier (src, flags, pred);
4894 else if (SET_DEST (x) == pc_rtx)
4896 /* X is a conditional branch. */
4897 /* ??? This seems redundant, as the caller sets this bit for
4899 flags.is_branch = 1;
4900 return rtx_needs_barrier (src, flags, pred);
4903 need_barrier = rtx_needs_barrier (src, flags, pred);
4905 /* This instruction unconditionally uses a predicate register. */
4907 need_barrier |= rws_access_reg (cond, flags, 0);
4910 if (GET_CODE (dst) == ZERO_EXTRACT)
4912 need_barrier |= rtx_needs_barrier (XEXP (dst, 1), flags, pred);
4913 need_barrier |= rtx_needs_barrier (XEXP (dst, 2), flags, pred);
4914 dst = XEXP (dst, 0);
4916 return need_barrier;
4919 /* Handle an access to rtx X of type FLAGS using predicate register PRED.
4920 Return 1 is this access creates a dependency with an earlier instruction
4921 in the same group. */
4924 rtx_needs_barrier (x, flags, pred)
4926 struct reg_flags flags;
4930 int is_complemented = 0;
4931 int need_barrier = 0;
4932 const char *format_ptr;
4933 struct reg_flags new_flags;
4941 switch (GET_CODE (x))
4944 update_set_flags (x, &new_flags, &pred, &cond);
4945 need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
4946 if (GET_CODE (SET_SRC (x)) != CALL)
4948 new_flags.is_write = 1;
4949 need_barrier |= rtx_needs_barrier (SET_DEST (x), new_flags, pred);
4954 new_flags.is_write = 0;
4955 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
4957 /* Avoid multiple register writes, in case this is a pattern with
4958 multiple CALL rtx. This avoids an abort in rws_access_reg. */
4959 if (! flags.is_sibcall && ! rws_insn[REG_AR_CFM].write_count)
4961 new_flags.is_write = 1;
4962 need_barrier |= rws_access_regno (REG_RP, new_flags, pred);
4963 need_barrier |= rws_access_regno (AR_PFS_REGNUM, new_flags, pred);
4964 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
4969 /* X is a predicated instruction. */
4971 cond = COND_EXEC_TEST (x);
4974 need_barrier = rtx_needs_barrier (cond, flags, 0);
4976 if (GET_CODE (cond) == EQ)
4977 is_complemented = 1;
4978 cond = XEXP (cond, 0);
4979 if (GET_CODE (cond) != REG
4980 && REGNO_REG_CLASS (REGNO (cond)) != PR_REGS)
4982 pred = REGNO (cond);
4983 if (is_complemented)
4986 need_barrier |= rtx_needs_barrier (COND_EXEC_CODE (x), flags, pred);
4987 return need_barrier;
4991 /* Clobber & use are for earlier compiler-phases only. */
4996 /* We always emit stop bits for traditional asms. We emit stop bits
4997 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
4998 if (GET_CODE (x) != ASM_OPERANDS
4999 || (MEM_VOLATILE_P (x) && TARGET_VOL_ASM_STOP))
5001 /* Avoid writing the register multiple times if we have multiple
5002 asm outputs. This avoids an abort in rws_access_reg. */
5003 if (! rws_insn[REG_VOLATILE].write_count)
5005 new_flags.is_write = 1;
5006 rws_access_regno (REG_VOLATILE, new_flags, pred);
5011 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5012 We can not just fall through here since then we would be confused
5013 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5014 traditional asms unlike their normal usage. */
5016 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; --i)
5017 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x, i), flags, pred))
5022 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5024 rtx pat = XVECEXP (x, 0, i);
5025 if (GET_CODE (pat) == SET)
5027 update_set_flags (pat, &new_flags, &pred, &cond);
5028 need_barrier |= set_src_needs_barrier (pat, new_flags, pred, cond);
5030 else if (GET_CODE (pat) == USE
5031 || GET_CODE (pat) == CALL
5032 || GET_CODE (pat) == ASM_OPERANDS)
5033 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5034 else if (GET_CODE (pat) != CLOBBER && GET_CODE (pat) != RETURN)
5037 for (i = XVECLEN (x, 0) - 1; i >= 0; --i)
5039 rtx pat = XVECEXP (x, 0, i);
5040 if (GET_CODE (pat) == SET)
5042 if (GET_CODE (SET_SRC (pat)) != CALL)
5044 new_flags.is_write = 1;
5045 need_barrier |= rtx_needs_barrier (SET_DEST (pat), new_flags,
5049 else if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == RETURN)
5050 need_barrier |= rtx_needs_barrier (pat, flags, pred);
5058 if (REGNO (x) == AR_UNAT_REGNUM)
5060 for (i = 0; i < 64; ++i)
5061 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + i, flags, pred);
5064 need_barrier = rws_access_reg (x, flags, pred);
5068 /* Find the regs used in memory address computation. */
5069 new_flags.is_write = 0;
5070 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5073 case CONST_INT: case CONST_DOUBLE:
5074 case SYMBOL_REF: case LABEL_REF: case CONST:
5077 /* Operators with side-effects. */
5078 case POST_INC: case POST_DEC:
5079 if (GET_CODE (XEXP (x, 0)) != REG)
5082 new_flags.is_write = 0;
5083 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5084 new_flags.is_write = 1;
5085 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5089 if (GET_CODE (XEXP (x, 0)) != REG)
5092 new_flags.is_write = 0;
5093 need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
5094 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5095 new_flags.is_write = 1;
5096 need_barrier |= rws_access_reg (XEXP (x, 0), new_flags, pred);
5099 /* Handle common unary and binary ops for efficiency. */
5100 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
5101 case MOD: case UDIV: case UMOD: case AND: case IOR:
5102 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
5103 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
5104 case NE: case EQ: case GE: case GT: case LE:
5105 case LT: case GEU: case GTU: case LEU: case LTU:
5106 need_barrier = rtx_needs_barrier (XEXP (x, 0), new_flags, pred);
5107 need_barrier |= rtx_needs_barrier (XEXP (x, 1), new_flags, pred);
5110 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
5111 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
5112 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
5113 case SQRT: case FFS: case POPCOUNT:
5114 need_barrier = rtx_needs_barrier (XEXP (x, 0), flags, pred);
5118 switch (XINT (x, 1))
5120 case UNSPEC_LTOFF_DTPMOD:
5121 case UNSPEC_LTOFF_DTPREL:
5123 case UNSPEC_LTOFF_TPREL:
5125 case UNSPEC_PRED_REL_MUTEX:
5126 case UNSPEC_PIC_CALL:
5128 case UNSPEC_FETCHADD_ACQ:
5129 case UNSPEC_BSP_VALUE:
5130 case UNSPEC_FLUSHRS:
5131 case UNSPEC_BUNDLE_SELECTOR:
5134 case UNSPEC_GR_SPILL:
5135 case UNSPEC_GR_RESTORE:
5137 HOST_WIDE_INT offset = INTVAL (XVECEXP (x, 0, 1));
5138 HOST_WIDE_INT bit = (offset >> 3) & 63;
5140 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5141 new_flags.is_write = (XINT (x, 1) == 1);
5142 need_barrier |= rws_access_regno (AR_UNAT_BIT_0 + bit,
5147 case UNSPEC_FR_SPILL:
5148 case UNSPEC_FR_RESTORE:
5149 case UNSPEC_GETF_EXP:
5151 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5154 case UNSPEC_FR_RECIP_APPROX:
5155 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 0), flags, pred);
5156 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5159 case UNSPEC_CMPXCHG_ACQ:
5160 need_barrier = rtx_needs_barrier (XVECEXP (x, 0, 1), flags, pred);
5161 need_barrier |= rtx_needs_barrier (XVECEXP (x, 0, 2), flags, pred);
5169 case UNSPEC_VOLATILE:
5170 switch (XINT (x, 1))
5173 /* Alloc must always be the first instruction of a group.
5174 We force this by always returning true. */
5175 /* ??? We might get better scheduling if we explicitly check for
5176 input/local/output register dependencies, and modify the
5177 scheduler so that alloc is always reordered to the start of
5178 the current group. We could then eliminate all of the
5179 first_instruction code. */
5180 rws_access_regno (AR_PFS_REGNUM, flags, pred);
5182 new_flags.is_write = 1;
5183 rws_access_regno (REG_AR_CFM, new_flags, pred);
5186 case UNSPECV_SET_BSP:
5190 case UNSPECV_BLOCKAGE:
5191 case UNSPECV_INSN_GROUP_BARRIER:
5193 case UNSPECV_PSAC_ALL:
5194 case UNSPECV_PSAC_NORMAL:
5203 new_flags.is_write = 0;
5204 need_barrier = rws_access_regno (REG_RP, flags, pred);
5205 need_barrier |= rws_access_regno (AR_PFS_REGNUM, flags, pred);
5207 new_flags.is_write = 1;
5208 need_barrier |= rws_access_regno (AR_EC_REGNUM, new_flags, pred);
5209 need_barrier |= rws_access_regno (REG_AR_CFM, new_flags, pred);
5213 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
5214 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5215 switch (format_ptr[i])
5217 case '0': /* unused field */
5218 case 'i': /* integer */
5219 case 'n': /* note */
5220 case 'w': /* wide integer */
5221 case 's': /* pointer to string */
5222 case 'S': /* optional pointer to string */
5226 if (rtx_needs_barrier (XEXP (x, i), flags, pred))
5231 for (j = XVECLEN (x, i) - 1; j >= 0; --j)
5232 if (rtx_needs_barrier (XVECEXP (x, i, j), flags, pred))
5241 return need_barrier;
5244 /* Clear out the state for group_barrier_needed_p at the start of a
5245 sequence of insns. */
5248 init_insn_group_barriers ()
5250 memset (rws_sum, 0, sizeof (rws_sum));
5251 first_instruction = 1;
5254 /* Given the current state, recorded by previous calls to this function,
5255 determine whether a group barrier (a stop bit) is necessary before INSN.
5256 Return nonzero if so. */
5259 group_barrier_needed_p (insn)
5263 int need_barrier = 0;
5264 struct reg_flags flags;
5266 memset (&flags, 0, sizeof (flags));
5267 switch (GET_CODE (insn))
5273 /* A barrier doesn't imply an instruction group boundary. */
5277 memset (rws_insn, 0, sizeof (rws_insn));
5281 flags.is_branch = 1;
5282 flags.is_sibcall = SIBLING_CALL_P (insn);
5283 memset (rws_insn, 0, sizeof (rws_insn));
5285 /* Don't bundle a call following another call. */
5286 if ((pat = prev_active_insn (insn))
5287 && GET_CODE (pat) == CALL_INSN)
5293 need_barrier = rtx_needs_barrier (PATTERN (insn), flags, 0);
5297 flags.is_branch = 1;
5299 /* Don't bundle a jump following a call. */
5300 if ((pat = prev_active_insn (insn))
5301 && GET_CODE (pat) == CALL_INSN)
5309 if (GET_CODE (PATTERN (insn)) == USE
5310 || GET_CODE (PATTERN (insn)) == CLOBBER)
5311 /* Don't care about USE and CLOBBER "insns"---those are used to
5312 indicate to the optimizer that it shouldn't get rid of
5313 certain operations. */
5316 pat = PATTERN (insn);
5318 /* Ug. Hack hacks hacked elsewhere. */
5319 switch (recog_memoized (insn))
5321 /* We play dependency tricks with the epilogue in order
5322 to get proper schedules. Undo this for dv analysis. */
5323 case CODE_FOR_epilogue_deallocate_stack:
5324 case CODE_FOR_prologue_allocate_stack:
5325 pat = XVECEXP (pat, 0, 0);
5328 /* The pattern we use for br.cloop confuses the code above.
5329 The second element of the vector is representative. */
5330 case CODE_FOR_doloop_end_internal:
5331 pat = XVECEXP (pat, 0, 1);
5334 /* Doesn't generate code. */
5335 case CODE_FOR_pred_rel_mutex:
5336 case CODE_FOR_prologue_use:
5343 memset (rws_insn, 0, sizeof (rws_insn));
5344 need_barrier = rtx_needs_barrier (pat, flags, 0);
5346 /* Check to see if the previous instruction was a volatile
5349 need_barrier = rws_access_regno (REG_VOLATILE, flags, 0);
5356 if (first_instruction && INSN_P (insn)
5357 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
5358 && GET_CODE (PATTERN (insn)) != USE
5359 && GET_CODE (PATTERN (insn)) != CLOBBER)
5362 first_instruction = 0;
5365 return need_barrier;
5368 /* Like group_barrier_needed_p, but do not clobber the current state. */
5371 safe_group_barrier_needed_p (insn)
5374 struct reg_write_state rws_saved[NUM_REGS];
5375 int saved_first_instruction;
5378 memcpy (rws_saved, rws_sum, NUM_REGS * sizeof *rws_saved);
5379 saved_first_instruction = first_instruction;
5381 t = group_barrier_needed_p (insn);
5383 memcpy (rws_sum, rws_saved, NUM_REGS * sizeof *rws_saved);
5384 first_instruction = saved_first_instruction;
5389 /* Scan the current function and insert stop bits as necessary to
5390 eliminate dependencies. This function assumes that a final
5391 instruction scheduling pass has been run which has already
5392 inserted most of the necessary stop bits. This function only
5393 inserts new ones at basic block boundaries, since these are
5394 invisible to the scheduler. */
5397 emit_insn_group_barriers (dump)
5402 int insns_since_last_label = 0;
5404 init_insn_group_barriers ();
5406 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5408 if (GET_CODE (insn) == CODE_LABEL)
5410 if (insns_since_last_label)
5412 insns_since_last_label = 0;
5414 else if (GET_CODE (insn) == NOTE
5415 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
5417 if (insns_since_last_label)
5419 insns_since_last_label = 0;
5421 else if (GET_CODE (insn) == INSN
5422 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
5423 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
5425 init_insn_group_barriers ();
5428 else if (INSN_P (insn))
5430 insns_since_last_label = 1;
5432 if (group_barrier_needed_p (insn))
5437 fprintf (dump, "Emitting stop before label %d\n",
5438 INSN_UID (last_label));
5439 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label);
5442 init_insn_group_barriers ();
5450 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5451 This function has to emit all necessary group barriers. */
5454 emit_all_insn_group_barriers (dump)
5455 FILE *dump ATTRIBUTE_UNUSED;
5459 init_insn_group_barriers ();
5461 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5463 if (GET_CODE (insn) == BARRIER)
5465 rtx last = prev_active_insn (insn);
5469 if (GET_CODE (last) == JUMP_INSN
5470 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
5471 last = prev_active_insn (last);
5472 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
5473 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
5475 init_insn_group_barriers ();
5477 else if (INSN_P (insn))
5479 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
5480 init_insn_group_barriers ();
5481 else if (group_barrier_needed_p (insn))
5483 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5484 init_insn_group_barriers ();
5485 group_barrier_needed_p (insn);
5492 static int errata_find_address_regs PARAMS ((rtx *, void *));
5493 static void errata_emit_nops PARAMS ((rtx));
5494 static void fixup_errata PARAMS ((void));
5496 /* This structure is used to track some details about the previous insns
5497 groups so we can determine if it may be necessary to insert NOPs to
5498 workaround hardware errata. */
5501 HARD_REG_SET p_reg_set;
5502 HARD_REG_SET gr_reg_conditionally_set;
5505 /* Index into the last_group array. */
5506 static int group_idx;
5508 /* Called through for_each_rtx; determines if a hard register that was
5509 conditionally set in the previous group is used as an address register.
5510 It ensures that for_each_rtx returns 1 in that case. */
5512 errata_find_address_regs (xp, data)
5514 void *data ATTRIBUTE_UNUSED;
5517 if (GET_CODE (x) != MEM)
5520 if (GET_CODE (x) == POST_MODIFY)
5522 if (GET_CODE (x) == REG)
5524 struct group *prev_group = last_group + (group_idx ^ 1);
5525 if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set,
5533 /* Called for each insn; this function keeps track of the state in
5534 last_group and emits additional NOPs if necessary to work around
5535 an Itanium A/B step erratum. */
5537 errata_emit_nops (insn)
5540 struct group *this_group = last_group + group_idx;
5541 struct group *prev_group = last_group + (group_idx ^ 1);
5542 rtx pat = PATTERN (insn);
5543 rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0;
5544 rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat;
5545 enum attr_type type;
5548 if (GET_CODE (real_pat) == USE
5549 || GET_CODE (real_pat) == CLOBBER
5550 || GET_CODE (real_pat) == ASM_INPUT
5551 || GET_CODE (real_pat) == ADDR_VEC
5552 || GET_CODE (real_pat) == ADDR_DIFF_VEC
5553 || asm_noperands (PATTERN (insn)) >= 0)
5556 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5559 if (GET_CODE (set) == PARALLEL)
5562 set = XVECEXP (real_pat, 0, 0);
5563 for (i = 1; i < XVECLEN (real_pat, 0); i++)
5564 if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE
5565 && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER)
5572 if (set && GET_CODE (set) != SET)
5575 type = get_attr_type (insn);
5578 && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set))))
5579 SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set)));
5581 if ((type == TYPE_M || type == TYPE_A) && cond && set
5582 && REG_P (SET_DEST (set))
5583 && GET_CODE (SET_SRC (set)) != PLUS
5584 && GET_CODE (SET_SRC (set)) != MINUS
5585 && (GET_CODE (SET_SRC (set)) != ASHIFT
5586 || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode))
5587 && (GET_CODE (SET_SRC (set)) != MEM
5588 || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY)
5589 && GENERAL_REGNO_P (REGNO (SET_DEST (set))))
5591 if (GET_RTX_CLASS (GET_CODE (cond)) != '<'
5592 || ! REG_P (XEXP (cond, 0)))
5595 if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0))))
5596 SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set)));
5598 if (for_each_rtx (&real_pat, errata_find_address_regs, NULL))
5600 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5601 emit_insn_before (gen_nop (), insn);
5602 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn);
5604 memset (last_group, 0, sizeof last_group);
5608 /* Emit extra nops if they are required to work around hardware errata. */
5615 if (! TARGET_B_STEP)
5619 memset (last_group, 0, sizeof last_group);
5621 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5626 if (ia64_safe_type (insn) == TYPE_S)
5629 memset (last_group + group_idx, 0, sizeof last_group[group_idx]);
5632 errata_emit_nops (insn);
5637 /* Instruction scheduling support. */
5639 #define NR_BUNDLES 10
5641 /* A list of names of all available bundles. */
5643 static const char *bundle_name [NR_BUNDLES] =
5649 #if NR_BUNDLES == 10
5659 /* Nonzero if we should insert stop bits into the schedule. */
5661 int ia64_final_schedule = 0;
5663 /* Codes of the corresponding quieryied units: */
5665 static int _0mii_, _0mmi_, _0mfi_, _0mmf_;
5666 static int _0bbb_, _0mbb_, _0mib_, _0mmb_, _0mfb_, _0mlx_;
5668 static int _1mii_, _1mmi_, _1mfi_, _1mmf_;
5669 static int _1bbb_, _1mbb_, _1mib_, _1mmb_, _1mfb_, _1mlx_;
5671 static int pos_1, pos_2, pos_3, pos_4, pos_5, pos_6;
5673 /* The following variable value is an insn group barrier. */
5675 static rtx dfa_stop_insn;
5677 /* The following variable value is the last issued insn. */
5679 static rtx last_scheduled_insn;
5681 /* The following variable value is size of the DFA state. */
5683 static size_t dfa_state_size;
5685 /* The following variable value is pointer to a DFA state used as
5686 temporary variable. */
5688 static state_t temp_dfa_state = NULL;
5690 /* The following variable value is DFA state after issuing the last
5693 static state_t prev_cycle_state = NULL;
5695 /* The following array element values are TRUE if the corresponding
5696 insn requires to add stop bits before it. */
5698 static char *stops_p;
5700 /* The following variable is used to set up the mentioned above array. */
5702 static int stop_before_p = 0;
5704 /* The following variable value is length of the arrays `clocks' and
5707 static int clocks_length;
5709 /* The following array element values are cycles on which the
5710 corresponding insn will be issued. The array is used only for
5715 /* The following array element values are numbers of cycles should be
5716 added to improve insn scheduling for MM_insns for Itanium1. */
5718 static int *add_cycles;
5720 static rtx ia64_single_set PARAMS ((rtx));
5721 static void ia64_emit_insn_before PARAMS ((rtx, rtx));
5723 /* Map a bundle number to its pseudo-op. */
5729 return bundle_name[b];
5733 /* Return the maximum number of instructions a cpu can issue. */
5741 /* Helper function - like single_set, but look inside COND_EXEC. */
5744 ia64_single_set (insn)
5747 rtx x = PATTERN (insn), ret;
5748 if (GET_CODE (x) == COND_EXEC)
5749 x = COND_EXEC_CODE (x);
5750 if (GET_CODE (x) == SET)
5753 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
5754 Although they are not classical single set, the second set is there just
5755 to protect it from moving past FP-relative stack accesses. */
5756 switch (recog_memoized (insn))
5758 case CODE_FOR_prologue_allocate_stack:
5759 case CODE_FOR_epilogue_deallocate_stack:
5760 ret = XVECEXP (x, 0, 0);
5764 ret = single_set_2 (insn, x);
5771 /* Adjust the cost of a scheduling dependency. Return the new cost of
5772 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5775 ia64_adjust_cost (insn, link, dep_insn, cost)
5776 rtx insn, link, dep_insn;
5779 enum attr_itanium_class dep_class;
5780 enum attr_itanium_class insn_class;
5782 if (REG_NOTE_KIND (link) != REG_DEP_OUTPUT)
5785 insn_class = ia64_safe_itanium_class (insn);
5786 dep_class = ia64_safe_itanium_class (dep_insn);
5787 if (dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF
5788 || insn_class == ITANIUM_CLASS_ST || insn_class == ITANIUM_CLASS_STF)
5794 /* Like emit_insn_before, but skip cycle_display notes.
5795 ??? When cycle display notes are implemented, update this. */
5798 ia64_emit_insn_before (insn, before)
5801 emit_insn_before (insn, before);
5804 /* The following function marks insns who produce addresses for load
5805 and store insns. Such insns will be placed into M slots because it
5806 decrease latency time for Itanium1 (see function
5807 `ia64_produce_address_p' and the DFA descriptions). */
5810 ia64_dependencies_evaluation_hook (head, tail)
5813 rtx insn, link, next, next_tail;
5815 next_tail = NEXT_INSN (tail);
5816 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5819 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
5821 && ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IALU)
5823 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
5825 next = XEXP (link, 0);
5826 if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_ST
5827 || ia64_safe_itanium_class (next) == ITANIUM_CLASS_STF)
5828 && ia64_st_address_bypass_p (insn, next))
5830 else if ((ia64_safe_itanium_class (next) == ITANIUM_CLASS_LD
5831 || ia64_safe_itanium_class (next)
5832 == ITANIUM_CLASS_FLD)
5833 && ia64_ld_address_bypass_p (insn, next))
5836 insn->call = link != 0;
5840 /* We're beginning a new block. Initialize data structures as necessary. */
5843 ia64_sched_init (dump, sched_verbose, max_ready)
5844 FILE *dump ATTRIBUTE_UNUSED;
5845 int sched_verbose ATTRIBUTE_UNUSED;
5846 int max_ready ATTRIBUTE_UNUSED;
5848 #ifdef ENABLE_CHECKING
5851 if (reload_completed)
5852 for (insn = NEXT_INSN (current_sched_info->prev_head);
5853 insn != current_sched_info->next_tail;
5854 insn = NEXT_INSN (insn))
5855 if (SCHED_GROUP_P (insn))
5858 last_scheduled_insn = NULL_RTX;
5859 init_insn_group_barriers ();
5862 /* We are about to being issuing insns for this clock cycle.
5863 Override the default sort algorithm to better slot instructions. */
5866 ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5867 clock_var, reorder_type)
5872 int clock_var ATTRIBUTE_UNUSED;
5876 int n_ready = *pn_ready;
5877 rtx *e_ready = ready + n_ready;
5881 fprintf (dump, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type);
5883 if (reorder_type == 0)
5885 /* First, move all USEs, CLOBBERs and other crud out of the way. */
5887 for (insnp = ready; insnp < e_ready; insnp++)
5888 if (insnp < e_ready)
5891 enum attr_type t = ia64_safe_type (insn);
5892 if (t == TYPE_UNKNOWN)
5894 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
5895 || asm_noperands (PATTERN (insn)) >= 0)
5897 rtx lowest = ready[n_asms];
5898 ready[n_asms] = insn;
5904 rtx highest = ready[n_ready - 1];
5905 ready[n_ready - 1] = insn;
5912 if (n_asms < n_ready)
5914 /* Some normal insns to process. Skip the asms. */
5918 else if (n_ready > 0)
5922 if (ia64_final_schedule)
5925 int nr_need_stop = 0;
5927 for (insnp = ready; insnp < e_ready; insnp++)
5928 if (safe_group_barrier_needed_p (*insnp))
5931 if (reorder_type == 1 && n_ready == nr_need_stop)
5933 if (reorder_type == 0)
5936 /* Move down everything that needs a stop bit, preserving
5938 while (insnp-- > ready + deleted)
5939 while (insnp >= ready + deleted)
5942 if (! safe_group_barrier_needed_p (insn))
5944 memmove (ready + 1, ready, (insnp - ready) * sizeof (rtx));
5955 /* We are about to being issuing insns for this clock cycle. Override
5956 the default sort algorithm to better slot instructions. */
5959 ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
5966 return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
5967 pn_ready, clock_var, 0);
5970 /* Like ia64_sched_reorder, but called after issuing each insn.
5971 Override the default sort algorithm to better slot instructions. */
5974 ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
5975 FILE *dump ATTRIBUTE_UNUSED;
5976 int sched_verbose ATTRIBUTE_UNUSED;
5981 if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
5982 clocks [INSN_UID (last_scheduled_insn)] = clock_var;
5983 return ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
5987 /* We are about to issue INSN. Return the number of insns left on the
5988 ready queue that can be issued this cycle. */
5991 ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
5992 FILE *dump ATTRIBUTE_UNUSED;
5993 int sched_verbose ATTRIBUTE_UNUSED;
5994 rtx insn ATTRIBUTE_UNUSED;
5995 int can_issue_more ATTRIBUTE_UNUSED;
5997 last_scheduled_insn = insn;
5998 memcpy (prev_cycle_state, curr_state, dfa_state_size);
5999 if (reload_completed)
6001 if (group_barrier_needed_p (insn))
6003 if (GET_CODE (insn) == CALL_INSN)
6004 init_insn_group_barriers ();
6005 stops_p [INSN_UID (insn)] = stop_before_p;
6011 /* We are choosing insn from the ready queue. Return nonzero if INSN
6015 ia64_first_cycle_multipass_dfa_lookahead_guard (insn)
6018 if (insn == NULL_RTX || !INSN_P (insn))
6020 return (!reload_completed
6021 || !safe_group_barrier_needed_p (insn));
6024 /* The following variable value is pseudo-insn used by the DFA insn
6025 scheduler to change the DFA state when the simulated clock is
6028 static rtx dfa_pre_cycle_insn;
6030 /* We are about to being issuing INSN. Return nonzero if we can not
6031 issue it on given cycle CLOCK and return zero if we should not sort
6032 the ready queue on the next clock start. */
6035 ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
6039 int last_clock, clock;
6042 int setup_clocks_p = FALSE;
6044 if (insn == NULL_RTX || !INSN_P (insn))
6046 if ((reload_completed && safe_group_barrier_needed_p (insn))
6047 || (last_scheduled_insn
6048 && (GET_CODE (last_scheduled_insn) == CALL_INSN
6049 || GET_CODE (PATTERN (last_scheduled_insn)) == ASM_INPUT
6050 || asm_noperands (PATTERN (last_scheduled_insn)) >= 0)))
6052 init_insn_group_barriers ();
6053 if (verbose && dump)
6054 fprintf (dump, "// Stop should be before %d%s\n", INSN_UID (insn),
6055 last_clock == clock ? " + cycle advance" : "");
6057 if (last_clock == clock)
6059 state_transition (curr_state, dfa_stop_insn);
6060 if (TARGET_EARLY_STOP_BITS)
6061 *sort_p = (last_scheduled_insn == NULL_RTX
6062 || GET_CODE (last_scheduled_insn) != CALL_INSN);
6067 else if (reload_completed)
6068 setup_clocks_p = TRUE;
6069 memcpy (curr_state, prev_cycle_state, dfa_state_size);
6070 state_transition (curr_state, dfa_stop_insn);
6071 state_transition (curr_state, dfa_pre_cycle_insn);
6072 state_transition (curr_state, NULL);
6074 else if (reload_completed)
6075 setup_clocks_p = TRUE;
6076 if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
6078 enum attr_itanium_class c = ia64_safe_itanium_class (insn);
6080 if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
6085 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6086 if (REG_NOTE_KIND (link) == 0)
6088 enum attr_itanium_class dep_class;
6089 rtx dep_insn = XEXP (link, 0);
6091 dep_class = ia64_safe_itanium_class (dep_insn);
6092 if ((dep_class == ITANIUM_CLASS_MMMUL
6093 || dep_class == ITANIUM_CLASS_MMSHF)
6094 && last_clock - clocks [INSN_UID (dep_insn)] < 4
6096 || last_clock - clocks [INSN_UID (dep_insn)] < d))
6097 d = last_clock - clocks [INSN_UID (dep_insn)];
6100 add_cycles [INSN_UID (insn)] = 3 - d;
6108 /* The following page contains abstract data `bundle states' which are
6109 used for bundling insns (inserting nops and template generation). */
6111 /* The following describes state of insn bundling. */
6115 /* Unique bundle state number to identify them in the debugging
6118 rtx insn; /* corresponding insn, NULL for the 1st and the last state */
6119 /* number nops before and after the insn */
6120 short before_nops_num, after_nops_num;
6121 int insn_num; /* insn number (0 - for initial state, 1 - for the 1st
6123 int cost; /* cost of the state in cycles */
6124 int accumulated_insns_num; /* number of all previous insns including
6125 nops. L is considered as 2 insns */
6126 int branch_deviation; /* deviation of previous branches from 3rd slots */
6127 struct bundle_state *next; /* next state with the same insn_num */
6128 struct bundle_state *originator; /* originator (previous insn state) */
6129 /* All bundle states are in the following chain. */
6130 struct bundle_state *allocated_states_chain;
6131 /* The DFA State after issuing the insn and the nops. */
6135 /* The following is map insn number to the corresponding bundle state. */
6137 static struct bundle_state **index_to_bundle_states;
6139 /* The unique number of next bundle state. */
6141 static int bundle_states_num;
6143 /* All allocated bundle states are in the following chain. */
6145 static struct bundle_state *allocated_bundle_states_chain;
6147 /* All allocated but not used bundle states are in the following
6150 static struct bundle_state *free_bundle_state_chain;
6153 /* The following function returns a free bundle state. */
6155 static struct bundle_state *
6156 get_free_bundle_state ()
6158 struct bundle_state *result;
6160 if (free_bundle_state_chain != NULL)
6162 result = free_bundle_state_chain;
6163 free_bundle_state_chain = result->next;
6167 result = xmalloc (sizeof (struct bundle_state));
6168 result->dfa_state = xmalloc (dfa_state_size);
6169 result->allocated_states_chain = allocated_bundle_states_chain;
6170 allocated_bundle_states_chain = result;
6172 result->unique_num = bundle_states_num++;
6177 /* The following function frees given bundle state. */
6180 free_bundle_state (state)
6181 struct bundle_state *state;
6183 state->next = free_bundle_state_chain;
6184 free_bundle_state_chain = state;
6187 /* Start work with abstract data `bundle states'. */
6190 initiate_bundle_states ()
6192 bundle_states_num = 0;
6193 free_bundle_state_chain = NULL;
6194 allocated_bundle_states_chain = NULL;
6197 /* Finish work with abstract data `bundle states'. */
6200 finish_bundle_states ()
6202 struct bundle_state *curr_state, *next_state;
6204 for (curr_state = allocated_bundle_states_chain;
6206 curr_state = next_state)
6208 next_state = curr_state->allocated_states_chain;
6209 free (curr_state->dfa_state);
6214 /* Hash table of the bundle states. The key is dfa_state and insn_num
6215 of the bundle states. */
6217 static htab_t bundle_state_table;
6219 /* The function returns hash of BUNDLE_STATE. */
6222 bundle_state_hash (bundle_state)
6223 const void *bundle_state;
6225 const struct bundle_state *state = (struct bundle_state *) bundle_state;
6228 for (result = i = 0; i < dfa_state_size; i++)
6229 result += (((unsigned char *) state->dfa_state) [i]
6230 << ((i % CHAR_BIT) * 3 + CHAR_BIT));
6231 return result + state->insn_num;
6234 /* The function returns nonzero if the bundle state keys are equal. */
6237 bundle_state_eq_p (bundle_state_1, bundle_state_2)
6238 const void *bundle_state_1;
6239 const void *bundle_state_2;
6241 const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
6242 const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
6244 return (state1->insn_num == state2->insn_num
6245 && memcmp (state1->dfa_state, state2->dfa_state,
6246 dfa_state_size) == 0);
6249 /* The function inserts the BUNDLE_STATE into the hash table. The
6250 function returns nonzero if the bundle has been inserted into the
6251 table. The table contains the best bundle state with given key. */
6254 insert_bundle_state (bundle_state)
6255 struct bundle_state *bundle_state;
6259 entry_ptr = htab_find_slot (bundle_state_table, bundle_state, 1);
6260 if (*entry_ptr == NULL)
6262 bundle_state->next = index_to_bundle_states [bundle_state->insn_num];
6263 index_to_bundle_states [bundle_state->insn_num] = bundle_state;
6264 *entry_ptr = (void *) bundle_state;
6267 else if (bundle_state->cost < ((struct bundle_state *) *entry_ptr)->cost
6268 || (bundle_state->cost == ((struct bundle_state *) *entry_ptr)->cost
6269 && (((struct bundle_state *)*entry_ptr)->accumulated_insns_num
6270 > bundle_state->accumulated_insns_num
6271 || (((struct bundle_state *)
6272 *entry_ptr)->accumulated_insns_num
6273 == bundle_state->accumulated_insns_num
6274 && ((struct bundle_state *)
6275 *entry_ptr)->branch_deviation
6276 > bundle_state->branch_deviation))))
6279 struct bundle_state temp;
6281 temp = *(struct bundle_state *) *entry_ptr;
6282 *(struct bundle_state *) *entry_ptr = *bundle_state;
6283 ((struct bundle_state *) *entry_ptr)->next = temp.next;
6284 *bundle_state = temp;
6289 /* Start work with the hash table. */
6292 initiate_bundle_state_table ()
6294 bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
6298 /* Finish work with the hash table. */
6301 finish_bundle_state_table ()
6303 htab_delete (bundle_state_table);
6308 /* The following variable is a insn `nop' used to check bundle states
6309 with different number of inserted nops. */
6311 static rtx ia64_nop;
6313 /* The following function tries to issue NOPS_NUM nops for the current
6314 state without advancing processor cycle. If it failed, the
6315 function returns FALSE and frees the current state. */
6318 try_issue_nops (curr_state, nops_num)
6319 struct bundle_state *curr_state;
6324 for (i = 0; i < nops_num; i++)
6325 if (state_transition (curr_state->dfa_state, ia64_nop) >= 0)
6327 free_bundle_state (curr_state);
6333 /* The following function tries to issue INSN for the current
6334 state without advancing processor cycle. If it failed, the
6335 function returns FALSE and frees the current state. */
6338 try_issue_insn (curr_state, insn)
6339 struct bundle_state *curr_state;
6342 if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
6344 free_bundle_state (curr_state);
6350 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6351 starting with ORIGINATOR without advancing processor cycle. If
6352 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6353 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6354 If it was successful, the function creates new bundle state and
6355 insert into the hash table and into `index_to_bundle_states'. */
6358 issue_nops_and_insn (originator, before_nops_num, insn, try_bundle_end_p,
6360 struct bundle_state *originator;
6361 int before_nops_num;
6363 int try_bundle_end_p, only_bundle_end_p;
6365 struct bundle_state *curr_state;
6367 curr_state = get_free_bundle_state ();
6368 memcpy (curr_state->dfa_state, originator->dfa_state, dfa_state_size);
6369 curr_state->insn = insn;
6370 curr_state->insn_num = originator->insn_num + 1;
6371 curr_state->cost = originator->cost;
6372 curr_state->originator = originator;
6373 curr_state->before_nops_num = before_nops_num;
6374 curr_state->after_nops_num = 0;
6375 curr_state->accumulated_insns_num
6376 = originator->accumulated_insns_num + before_nops_num;
6377 curr_state->branch_deviation = originator->branch_deviation;
6378 if (insn == NULL_RTX)
6380 else if (INSN_CODE (insn) == CODE_FOR_insn_group_barrier)
6382 if (GET_MODE (insn) == TImode)
6384 if (!try_issue_nops (curr_state, before_nops_num))
6386 if (!try_issue_insn (curr_state, insn))
6388 memcpy (temp_dfa_state, curr_state->dfa_state, dfa_state_size);
6389 if (state_transition (temp_dfa_state, dfa_pre_cycle_insn) >= 0
6390 && curr_state->accumulated_insns_num % 3 != 0)
6392 free_bundle_state (curr_state);
6396 else if (GET_MODE (insn) != TImode)
6398 if (!try_issue_nops (curr_state, before_nops_num))
6400 if (!try_issue_insn (curr_state, insn))
6402 curr_state->accumulated_insns_num++;
6403 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6404 || asm_noperands (PATTERN (insn)) >= 0)
6406 if (ia64_safe_type (insn) == TYPE_L)
6407 curr_state->accumulated_insns_num++;
6411 state_transition (curr_state->dfa_state, dfa_pre_cycle_insn);
6412 state_transition (curr_state->dfa_state, NULL);
6414 if (!try_issue_nops (curr_state, before_nops_num))
6416 if (!try_issue_insn (curr_state, insn))
6418 curr_state->accumulated_insns_num++;
6419 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6420 || asm_noperands (PATTERN (insn)) >= 0)
6422 /* Finish bundle containing asm insn. */
6423 curr_state->after_nops_num
6424 = 3 - curr_state->accumulated_insns_num % 3;
6425 curr_state->accumulated_insns_num
6426 += 3 - curr_state->accumulated_insns_num % 3;
6428 else if (ia64_safe_type (insn) == TYPE_L)
6429 curr_state->accumulated_insns_num++;
6431 if (ia64_safe_type (insn) == TYPE_B)
6432 curr_state->branch_deviation
6433 += 2 - (curr_state->accumulated_insns_num - 1) % 3;
6434 if (try_bundle_end_p && curr_state->accumulated_insns_num % 3 != 0)
6436 if (!only_bundle_end_p && insert_bundle_state (curr_state))
6439 struct bundle_state *curr_state1;
6440 struct bundle_state *allocated_states_chain;
6442 curr_state1 = get_free_bundle_state ();
6443 dfa_state = curr_state1->dfa_state;
6444 allocated_states_chain = curr_state1->allocated_states_chain;
6445 *curr_state1 = *curr_state;
6446 curr_state1->dfa_state = dfa_state;
6447 curr_state1->allocated_states_chain = allocated_states_chain;
6448 memcpy (curr_state1->dfa_state, curr_state->dfa_state,
6450 curr_state = curr_state1;
6452 if (!try_issue_nops (curr_state,
6453 3 - curr_state->accumulated_insns_num % 3))
6455 curr_state->after_nops_num
6456 = 3 - curr_state->accumulated_insns_num % 3;
6457 curr_state->accumulated_insns_num
6458 += 3 - curr_state->accumulated_insns_num % 3;
6460 if (!insert_bundle_state (curr_state))
6461 free_bundle_state (curr_state);
6465 /* The following function returns position in the two window bundle
6472 if (cpu_unit_reservation_p (state, pos_6))
6474 else if (cpu_unit_reservation_p (state, pos_5))
6476 else if (cpu_unit_reservation_p (state, pos_4))
6478 else if (cpu_unit_reservation_p (state, pos_3))
6480 else if (cpu_unit_reservation_p (state, pos_2))
6482 else if (cpu_unit_reservation_p (state, pos_1))
6488 /* The function returns code of a possible template for given position
6489 and state. The function should be called only with 2 values of
6490 position equal to 3 or 6. */
6493 get_template (state, pos)
6500 if (cpu_unit_reservation_p (state, _0mii_))
6502 else if (cpu_unit_reservation_p (state, _0mmi_))
6504 else if (cpu_unit_reservation_p (state, _0mfi_))
6506 else if (cpu_unit_reservation_p (state, _0mmf_))
6508 else if (cpu_unit_reservation_p (state, _0bbb_))
6510 else if (cpu_unit_reservation_p (state, _0mbb_))
6512 else if (cpu_unit_reservation_p (state, _0mib_))
6514 else if (cpu_unit_reservation_p (state, _0mmb_))
6516 else if (cpu_unit_reservation_p (state, _0mfb_))
6518 else if (cpu_unit_reservation_p (state, _0mlx_))
6523 if (cpu_unit_reservation_p (state, _1mii_))
6525 else if (cpu_unit_reservation_p (state, _1mmi_))
6527 else if (cpu_unit_reservation_p (state, _1mfi_))
6529 else if (_1mmf_ >= 0 && cpu_unit_reservation_p (state, _1mmf_))
6531 else if (cpu_unit_reservation_p (state, _1bbb_))
6533 else if (cpu_unit_reservation_p (state, _1mbb_))
6535 else if (cpu_unit_reservation_p (state, _1mib_))
6537 else if (cpu_unit_reservation_p (state, _1mmb_))
6539 else if (cpu_unit_reservation_p (state, _1mfb_))
6541 else if (cpu_unit_reservation_p (state, _1mlx_))
6550 /* The following function returns an insn important for insn bundling
6551 followed by INSN and before TAIL. */
6554 get_next_important_insn (insn, tail)
6557 for (; insn && insn != tail; insn = NEXT_INSN (insn))
6559 && ia64_safe_itanium_class (insn) != ITANIUM_CLASS_IGNORE
6560 && GET_CODE (PATTERN (insn)) != USE
6561 && GET_CODE (PATTERN (insn)) != CLOBBER)
6566 /* The following function does insn bundling. Bundling algorithm is
6567 based on dynamic programming. It tries to insert different number of
6568 nop insns before/after the real insns. At the end of EBB, it chooses the
6569 best alternative and then, moving back in EBB, inserts templates for
6570 the best alternative. The algorithm is directed by information
6571 (changes of simulated processor cycle) created by the 2nd insn
6575 bundling (dump, verbose, prev_head_insn, tail)
6578 rtx prev_head_insn, tail;
6580 struct bundle_state *curr_state, *next_state, *best_state;
6581 rtx insn, next_insn;
6583 int i, bundle_end_p, only_bundle_end_p, asm_p;
6584 int pos = 0, max_pos, template0, template1;
6587 enum attr_type type;
6590 for (insn = NEXT_INSN (prev_head_insn);
6591 insn && insn != tail;
6592 insn = NEXT_INSN (insn))
6598 dfa_clean_insn_cache ();
6599 initiate_bundle_state_table ();
6600 index_to_bundle_states = xmalloc ((insn_num + 2)
6601 * sizeof (struct bundle_state *));
6602 /* First (forward) pass -- generates states. */
6603 curr_state = get_free_bundle_state ();
6604 curr_state->insn = NULL;
6605 curr_state->before_nops_num = 0;
6606 curr_state->after_nops_num = 0;
6607 curr_state->insn_num = 0;
6608 curr_state->cost = 0;
6609 curr_state->accumulated_insns_num = 0;
6610 curr_state->branch_deviation = 0;
6611 curr_state->next = NULL;
6612 curr_state->originator = NULL;
6613 state_reset (curr_state->dfa_state);
6614 index_to_bundle_states [0] = curr_state;
6616 for (insn = NEXT_INSN (prev_head_insn);
6618 insn = NEXT_INSN (insn))
6620 && (ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6621 || GET_CODE (PATTERN (insn)) == USE
6622 || GET_CODE (PATTERN (insn)) == CLOBBER)
6623 && GET_MODE (insn) == TImode)
6625 PUT_MODE (insn, VOIDmode);
6626 for (next_insn = NEXT_INSN (insn);
6628 next_insn = NEXT_INSN (next_insn))
6629 if (INSN_P (next_insn)
6630 && ia64_safe_itanium_class (next_insn) != ITANIUM_CLASS_IGNORE
6631 && GET_CODE (PATTERN (next_insn)) != USE
6632 && GET_CODE (PATTERN (next_insn)) != CLOBBER)
6634 PUT_MODE (next_insn, TImode);
6638 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6643 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6644 || GET_CODE (PATTERN (insn)) == USE
6645 || GET_CODE (PATTERN (insn)) == CLOBBER)
6647 type = ia64_safe_type (insn);
6648 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6650 index_to_bundle_states [insn_num] = NULL;
6651 for (curr_state = index_to_bundle_states [insn_num - 1];
6653 curr_state = next_state)
6655 pos = curr_state->accumulated_insns_num % 3;
6656 next_state = curr_state->next;
6657 /* Finish the current bundle in order to start a subsequent
6658 asm insn in a new bundle. */
6660 = (next_insn != NULL_RTX
6661 && INSN_CODE (insn) == CODE_FOR_insn_group_barrier
6662 && ia64_safe_type (next_insn) == TYPE_UNKNOWN);
6664 = (only_bundle_end_p || next_insn == NULL_RTX
6665 || (GET_MODE (next_insn) == TImode
6666 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier));
6667 if (type == TYPE_F || type == TYPE_B || type == TYPE_L
6669 /* We need to insert 2 Nops for cases like M_MII. */
6670 || (type == TYPE_M && ia64_tune == PROCESSOR_ITANIUM
6671 && !bundle_end_p && pos == 1))
6672 issue_nops_and_insn (curr_state, 2, insn, bundle_end_p,
6674 issue_nops_and_insn (curr_state, 1, insn, bundle_end_p,
6676 issue_nops_and_insn (curr_state, 0, insn, bundle_end_p,
6679 if (index_to_bundle_states [insn_num] == NULL)
6681 for (curr_state = index_to_bundle_states [insn_num];
6683 curr_state = curr_state->next)
6684 if (verbose >= 2 && dump)
6688 unsigned short one_automaton_state;
6689 unsigned short oneb_automaton_state;
6690 unsigned short two_automaton_state;
6691 unsigned short twob_automaton_state;
6696 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6697 curr_state->unique_num,
6698 (curr_state->originator == NULL
6699 ? -1 : curr_state->originator->unique_num),
6701 curr_state->before_nops_num, curr_state->after_nops_num,
6702 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6703 (ia64_tune == PROCESSOR_ITANIUM
6704 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6705 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6709 if (index_to_bundle_states [insn_num] == NULL)
6711 /* Finding state with a minimal cost: */
6713 for (curr_state = index_to_bundle_states [insn_num];
6715 curr_state = curr_state->next)
6716 if (curr_state->accumulated_insns_num % 3 == 0
6717 && (best_state == NULL || best_state->cost > curr_state->cost
6718 || (best_state->cost == curr_state->cost
6719 && (curr_state->accumulated_insns_num
6720 < best_state->accumulated_insns_num
6721 || (curr_state->accumulated_insns_num
6722 == best_state->accumulated_insns_num
6723 && curr_state->branch_deviation
6724 < best_state->branch_deviation)))))
6725 best_state = curr_state;
6726 /* Second (backward) pass: adding nops and templates: */
6727 insn_num = best_state->before_nops_num;
6728 template0 = template1 = -1;
6729 for (curr_state = best_state;
6730 curr_state->originator != NULL;
6731 curr_state = curr_state->originator)
6733 insn = curr_state->insn;
6734 asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT
6735 || asm_noperands (PATTERN (insn)) >= 0);
6737 if (verbose >= 2 && dump)
6741 unsigned short one_automaton_state;
6742 unsigned short oneb_automaton_state;
6743 unsigned short two_automaton_state;
6744 unsigned short twob_automaton_state;
6749 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6750 curr_state->unique_num,
6751 (curr_state->originator == NULL
6752 ? -1 : curr_state->originator->unique_num),
6754 curr_state->before_nops_num, curr_state->after_nops_num,
6755 curr_state->accumulated_insns_num, curr_state->branch_deviation,
6756 (ia64_tune == PROCESSOR_ITANIUM
6757 ? ((struct DFA_chip *) curr_state->dfa_state)->oneb_automaton_state
6758 : ((struct DFA_chip *) curr_state->dfa_state)->twob_automaton_state),
6761 max_pos = get_max_pos (curr_state->dfa_state);
6762 if (max_pos == 6 || (max_pos == 3 && template0 < 0))
6766 template0 = get_template (curr_state->dfa_state, 3);
6769 template1 = get_template (curr_state->dfa_state, 3);
6770 template0 = get_template (curr_state->dfa_state, 6);
6773 if (max_pos > 3 && template1 < 0)
6777 template1 = get_template (curr_state->dfa_state, 3);
6781 for (i = 0; i < curr_state->after_nops_num; i++)
6784 emit_insn_after (nop, insn);
6792 b = gen_bundle_selector (GEN_INT (template0));
6793 ia64_emit_insn_before (b, nop);
6794 template0 = template1;
6798 if (INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6799 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6800 && asm_noperands (PATTERN (insn)) < 0)
6802 if (ia64_safe_type (insn) == TYPE_L)
6807 && INSN_CODE (insn) != CODE_FOR_insn_group_barrier
6808 && GET_CODE (PATTERN (insn)) != ASM_INPUT
6809 && asm_noperands (PATTERN (insn)) < 0)
6813 b = gen_bundle_selector (GEN_INT (template0));
6814 ia64_emit_insn_before (b, insn);
6815 b = PREV_INSN (insn);
6817 template0 = template1;
6820 for (i = 0; i < curr_state->before_nops_num; i++)
6823 ia64_emit_insn_before (nop, insn);
6824 nop = PREV_INSN (insn);
6833 b = gen_bundle_selector (GEN_INT (template0));
6834 ia64_emit_insn_before (b, insn);
6835 b = PREV_INSN (insn);
6837 template0 = template1;
6842 if (ia64_tune == PROCESSOR_ITANIUM)
6843 /* Insert additional cycles for MM-insns: */
6844 for (insn = get_next_important_insn (NEXT_INSN (prev_head_insn), tail);
6849 || ia64_safe_itanium_class (insn) == ITANIUM_CLASS_IGNORE
6850 || GET_CODE (PATTERN (insn)) == USE
6851 || GET_CODE (PATTERN (insn)) == CLOBBER)
6853 next_insn = get_next_important_insn (NEXT_INSN (insn), tail);
6854 if (INSN_UID (insn) < clocks_length && add_cycles [INSN_UID (insn)])
6860 last = prev_active_insn (insn);
6861 pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
6863 last = prev_active_insn (last);
6865 for (;; last = prev_active_insn (last))
6866 if (recog_memoized (last) == CODE_FOR_bundle_selector)
6868 template0 = XINT (XVECEXP (PATTERN (last), 0, 0), 0);
6871 = gen_bundle_selector (GEN_INT (2)); /* -> MFI */
6874 else if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6876 if ((pred_stop_p && n == 0) || n > 2
6877 || (template0 == 9 && n != 0))
6879 for (j = 3 - n; j > 0; j --)
6880 ia64_emit_insn_before (gen_nop (), insn);
6881 add_cycles [INSN_UID (insn)]--;
6882 if (!pred_stop_p || add_cycles [INSN_UID (insn)])
6883 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6886 add_cycles [INSN_UID (insn)]--;
6887 for (i = add_cycles [INSN_UID (insn)]; i > 0; i--)
6889 /* Insert .MII bundle. */
6890 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (0)),
6892 ia64_emit_insn_before (gen_nop (), insn);
6893 ia64_emit_insn_before (gen_nop (), insn);
6896 ia64_emit_insn_before
6897 (gen_insn_group_barrier (GEN_INT (3)), insn);
6900 ia64_emit_insn_before (gen_nop (), insn);
6901 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6904 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0)),
6906 for (j = n; j > 0; j --)
6907 ia64_emit_insn_before (gen_nop (), insn);
6909 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
6913 free (index_to_bundle_states);
6914 finish_bundle_state_table ();
6916 dfa_clean_insn_cache ();
6919 /* The following function is called at the end of scheduling BB or
6920 EBB. After reload, it inserts stop bits and does insn bundling. */
6923 ia64_sched_finish (dump, sched_verbose)
6928 fprintf (dump, "// Finishing schedule.\n");
6929 if (!reload_completed)
6931 if (reload_completed)
6933 final_emit_insn_group_barriers (dump);
6934 bundling (dump, sched_verbose, current_sched_info->prev_head,
6935 current_sched_info->next_tail);
6936 if (sched_verbose && dump)
6937 fprintf (dump, "// finishing %d-%d\n",
6938 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
6939 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
6945 /* The following function inserts stop bits in scheduled BB or EBB. */
6948 final_emit_insn_group_barriers (dump)
6949 FILE *dump ATTRIBUTE_UNUSED;
6952 int need_barrier_p = 0;
6953 rtx prev_insn = NULL_RTX;
6955 init_insn_group_barriers ();
6957 for (insn = NEXT_INSN (current_sched_info->prev_head);
6958 insn != current_sched_info->next_tail;
6959 insn = NEXT_INSN (insn))
6961 if (GET_CODE (insn) == BARRIER)
6963 rtx last = prev_active_insn (insn);
6967 if (GET_CODE (last) == JUMP_INSN
6968 && GET_CODE (PATTERN (last)) == ADDR_DIFF_VEC)
6969 last = prev_active_insn (last);
6970 if (recog_memoized (last) != CODE_FOR_insn_group_barrier)
6971 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last);
6973 init_insn_group_barriers ();
6975 prev_insn = NULL_RTX;
6977 else if (INSN_P (insn))
6979 if (recog_memoized (insn) == CODE_FOR_insn_group_barrier)
6981 init_insn_group_barriers ();
6983 prev_insn = NULL_RTX;
6985 else if (need_barrier_p || group_barrier_needed_p (insn))
6987 if (TARGET_EARLY_STOP_BITS)
6992 last != current_sched_info->prev_head;
6993 last = PREV_INSN (last))
6994 if (INSN_P (last) && GET_MODE (last) == TImode
6995 && stops_p [INSN_UID (last)])
6997 if (last == current_sched_info->prev_head)
6999 last = prev_active_insn (last);
7001 && recog_memoized (last) != CODE_FOR_insn_group_barrier)
7002 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7004 init_insn_group_barriers ();
7005 for (last = NEXT_INSN (last);
7007 last = NEXT_INSN (last))
7009 group_barrier_needed_p (last);
7013 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7015 init_insn_group_barriers ();
7017 group_barrier_needed_p (insn);
7018 prev_insn = NULL_RTX;
7020 else if (recog_memoized (insn) >= 0)
7022 need_barrier_p = (GET_CODE (insn) == CALL_INSN
7023 || GET_CODE (PATTERN (insn)) == ASM_INPUT
7024 || asm_noperands (PATTERN (insn)) >= 0);
7031 /* If the following function returns TRUE, we will use the the DFA
7035 ia64_use_dfa_pipeline_interface ()
7040 /* If the following function returns TRUE, we will use the the DFA
7044 ia64_first_cycle_multipass_dfa_lookahead ()
7046 return (reload_completed ? 6 : 4);
7049 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7052 ia64_init_dfa_pre_cycle_insn ()
7054 if (temp_dfa_state == NULL)
7056 dfa_state_size = state_size ();
7057 temp_dfa_state = xmalloc (dfa_state_size);
7058 prev_cycle_state = xmalloc (dfa_state_size);
7060 dfa_pre_cycle_insn = make_insn_raw (gen_pre_cycle ());
7061 PREV_INSN (dfa_pre_cycle_insn) = NEXT_INSN (dfa_pre_cycle_insn) = NULL_RTX;
7062 recog_memoized (dfa_pre_cycle_insn);
7063 dfa_stop_insn = make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7064 PREV_INSN (dfa_stop_insn) = NEXT_INSN (dfa_stop_insn) = NULL_RTX;
7065 recog_memoized (dfa_stop_insn);
7068 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7069 used by the DFA insn scheduler. */
7072 ia64_dfa_pre_cycle_insn ()
7074 return dfa_pre_cycle_insn;
7077 /* The following function returns TRUE if PRODUCER (of type ilog or
7078 ld) produces address for CONSUMER (of type st or stf). */
7081 ia64_st_address_bypass_p (producer, consumer)
7087 if (producer == NULL_RTX || consumer == NULL_RTX)
7089 dest = ia64_single_set (producer);
7090 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7091 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7093 if (GET_CODE (reg) == SUBREG)
7094 reg = SUBREG_REG (reg);
7095 dest = ia64_single_set (consumer);
7096 if (dest == NULL_RTX || (mem = SET_DEST (dest)) == NULL_RTX
7097 || GET_CODE (mem) != MEM)
7099 return reg_mentioned_p (reg, mem);
7102 /* The following function returns TRUE if PRODUCER (of type ilog or
7103 ld) produces address for CONSUMER (of type ld or fld). */
7106 ia64_ld_address_bypass_p (producer, consumer)
7110 rtx dest, src, reg, mem;
7112 if (producer == NULL_RTX || consumer == NULL_RTX)
7114 dest = ia64_single_set (producer);
7115 if (dest == NULL_RTX || (reg = SET_DEST (dest)) == NULL_RTX
7116 || (GET_CODE (reg) != REG && GET_CODE (reg) != SUBREG))
7118 if (GET_CODE (reg) == SUBREG)
7119 reg = SUBREG_REG (reg);
7120 src = ia64_single_set (consumer);
7121 if (src == NULL_RTX || (mem = SET_SRC (src)) == NULL_RTX)
7123 if (GET_CODE (mem) == UNSPEC && XVECLEN (mem, 0) > 0)
7124 mem = XVECEXP (mem, 0, 0);
7125 while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
7126 mem = XEXP (mem, 0);
7128 /* Note that LO_SUM is used for GOT loads. */
7129 if (GET_CODE (mem) != LO_SUM && GET_CODE (mem) != MEM)
7132 return reg_mentioned_p (reg, mem);
7135 /* The following function returns TRUE if INSN produces address for a
7136 load/store insn. We will place such insns into M slot because it
7137 decreases its latency time. */
7140 ia64_produce_address_p (insn)
7147 /* Emit pseudo-ops for the assembler to describe predicate relations.
7148 At present this assumes that we only consider predicate pairs to
7149 be mutex, and that the assembler can deduce proper values from
7150 straight-line code. */
7153 emit_predicate_relation_info ()
7157 FOR_EACH_BB_REVERSE (bb)
7160 rtx head = bb->head;
7162 /* We only need such notes at code labels. */
7163 if (GET_CODE (head) != CODE_LABEL)
7165 if (GET_CODE (NEXT_INSN (head)) == NOTE
7166 && NOTE_LINE_NUMBER (NEXT_INSN (head)) == NOTE_INSN_BASIC_BLOCK)
7167 head = NEXT_INSN (head);
7169 for (r = PR_REG (0); r < PR_REG (64); r += 2)
7170 if (REGNO_REG_SET_P (bb->global_live_at_start, r))
7172 rtx p = gen_rtx_REG (BImode, r);
7173 rtx n = emit_insn_after (gen_pred_rel_mutex (p), head);
7174 if (head == bb->end)
7180 /* Look for conditional calls that do not return, and protect predicate
7181 relations around them. Otherwise the assembler will assume the call
7182 returns, and complain about uses of call-clobbered predicates after
7184 FOR_EACH_BB_REVERSE (bb)
7186 rtx insn = bb->head;
7190 if (GET_CODE (insn) == CALL_INSN
7191 && GET_CODE (PATTERN (insn)) == COND_EXEC
7192 && find_reg_note (insn, REG_NORETURN, NULL_RTX))
7194 rtx b = emit_insn_before (gen_safe_across_calls_all (), insn);
7195 rtx a = emit_insn_after (gen_safe_across_calls_normal (), insn);
7196 if (bb->head == insn)
7198 if (bb->end == insn)
7202 if (insn == bb->end)
7204 insn = NEXT_INSN (insn);
7209 /* Perform machine dependent operations on the rtl chain INSNS. */
7214 /* We are freeing block_for_insn in the toplev to keep compatibility
7215 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7216 compute_bb_for_insn ();
7218 /* If optimizing, we'll have split before scheduling. */
7220 split_all_insns (0);
7222 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7223 non-optimizing bootstrap. */
7224 update_life_info (NULL, UPDATE_LIFE_GLOBAL_RM_NOTES, PROP_DEATH_NOTES);
7226 if (ia64_flag_schedule_insns2)
7228 timevar_push (TV_SCHED2);
7229 ia64_final_schedule = 1;
7231 initiate_bundle_states ();
7232 ia64_nop = make_insn_raw (gen_nop ());
7233 PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
7234 recog_memoized (ia64_nop);
7235 clocks_length = get_max_uid () + 1;
7236 stops_p = (char *) xmalloc (clocks_length);
7237 memset (stops_p, 0, clocks_length);
7238 if (ia64_tune == PROCESSOR_ITANIUM)
7240 clocks = (int *) xmalloc (clocks_length * sizeof (int));
7241 memset (clocks, 0, clocks_length * sizeof (int));
7242 add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
7243 memset (add_cycles, 0, clocks_length * sizeof (int));
7245 if (ia64_tune == PROCESSOR_ITANIUM2)
7247 pos_1 = get_cpu_unit_code ("2_1");
7248 pos_2 = get_cpu_unit_code ("2_2");
7249 pos_3 = get_cpu_unit_code ("2_3");
7250 pos_4 = get_cpu_unit_code ("2_4");
7251 pos_5 = get_cpu_unit_code ("2_5");
7252 pos_6 = get_cpu_unit_code ("2_6");
7253 _0mii_ = get_cpu_unit_code ("2b_0mii.");
7254 _0mmi_ = get_cpu_unit_code ("2b_0mmi.");
7255 _0mfi_ = get_cpu_unit_code ("2b_0mfi.");
7256 _0mmf_ = get_cpu_unit_code ("2b_0mmf.");
7257 _0bbb_ = get_cpu_unit_code ("2b_0bbb.");
7258 _0mbb_ = get_cpu_unit_code ("2b_0mbb.");
7259 _0mib_ = get_cpu_unit_code ("2b_0mib.");
7260 _0mmb_ = get_cpu_unit_code ("2b_0mmb.");
7261 _0mfb_ = get_cpu_unit_code ("2b_0mfb.");
7262 _0mlx_ = get_cpu_unit_code ("2b_0mlx.");
7263 _1mii_ = get_cpu_unit_code ("2b_1mii.");
7264 _1mmi_ = get_cpu_unit_code ("2b_1mmi.");
7265 _1mfi_ = get_cpu_unit_code ("2b_1mfi.");
7266 _1mmf_ = get_cpu_unit_code ("2b_1mmf.");
7267 _1bbb_ = get_cpu_unit_code ("2b_1bbb.");
7268 _1mbb_ = get_cpu_unit_code ("2b_1mbb.");
7269 _1mib_ = get_cpu_unit_code ("2b_1mib.");
7270 _1mmb_ = get_cpu_unit_code ("2b_1mmb.");
7271 _1mfb_ = get_cpu_unit_code ("2b_1mfb.");
7272 _1mlx_ = get_cpu_unit_code ("2b_1mlx.");
7276 pos_1 = get_cpu_unit_code ("1_1");
7277 pos_2 = get_cpu_unit_code ("1_2");
7278 pos_3 = get_cpu_unit_code ("1_3");
7279 pos_4 = get_cpu_unit_code ("1_4");
7280 pos_5 = get_cpu_unit_code ("1_5");
7281 pos_6 = get_cpu_unit_code ("1_6");
7282 _0mii_ = get_cpu_unit_code ("1b_0mii.");
7283 _0mmi_ = get_cpu_unit_code ("1b_0mmi.");
7284 _0mfi_ = get_cpu_unit_code ("1b_0mfi.");
7285 _0mmf_ = get_cpu_unit_code ("1b_0mmf.");
7286 _0bbb_ = get_cpu_unit_code ("1b_0bbb.");
7287 _0mbb_ = get_cpu_unit_code ("1b_0mbb.");
7288 _0mib_ = get_cpu_unit_code ("1b_0mib.");
7289 _0mmb_ = get_cpu_unit_code ("1b_0mmb.");
7290 _0mfb_ = get_cpu_unit_code ("1b_0mfb.");
7291 _0mlx_ = get_cpu_unit_code ("1b_0mlx.");
7292 _1mii_ = get_cpu_unit_code ("1b_1mii.");
7293 _1mmi_ = get_cpu_unit_code ("1b_1mmi.");
7294 _1mfi_ = get_cpu_unit_code ("1b_1mfi.");
7295 _1mmf_ = get_cpu_unit_code ("1b_1mmf.");
7296 _1bbb_ = get_cpu_unit_code ("1b_1bbb.");
7297 _1mbb_ = get_cpu_unit_code ("1b_1mbb.");
7298 _1mib_ = get_cpu_unit_code ("1b_1mib.");
7299 _1mmb_ = get_cpu_unit_code ("1b_1mmb.");
7300 _1mfb_ = get_cpu_unit_code ("1b_1mfb.");
7301 _1mlx_ = get_cpu_unit_code ("1b_1mlx.");
7303 schedule_ebbs (rtl_dump_file);
7304 finish_bundle_states ();
7305 if (ia64_tune == PROCESSOR_ITANIUM)
7311 emit_insn_group_barriers (rtl_dump_file);
7313 ia64_final_schedule = 0;
7314 timevar_pop (TV_SCHED2);
7317 emit_all_insn_group_barriers (rtl_dump_file);
7319 /* A call must not be the last instruction in a function, so that the
7320 return address is still within the function, so that unwinding works
7321 properly. Note that IA-64 differs from dwarf2 on this point. */
7322 if (flag_unwind_tables || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7327 insn = get_last_insn ();
7328 if (! INSN_P (insn))
7329 insn = prev_active_insn (insn);
7330 if (GET_CODE (insn) == INSN
7331 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
7332 && XINT (PATTERN (insn), 1) == UNSPECV_INSN_GROUP_BARRIER)
7335 insn = prev_active_insn (insn);
7337 if (GET_CODE (insn) == CALL_INSN)
7340 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7341 emit_insn (gen_break_f ());
7342 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7347 emit_predicate_relation_info ();
7350 /* Return true if REGNO is used by the epilogue. */
7353 ia64_epilogue_uses (regno)
7359 /* When a function makes a call through a function descriptor, we
7360 will write a (potentially) new value to "gp". After returning
7361 from such a call, we need to make sure the function restores the
7362 original gp-value, even if the function itself does not use the
7364 return (TARGET_CONST_GP && !(TARGET_AUTO_PIC || TARGET_NO_PIC));
7366 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7367 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7368 /* For functions defined with the syscall_linkage attribute, all
7369 input registers are marked as live at all function exits. This
7370 prevents the register allocator from using the input registers,
7371 which in turn makes it possible to restart a system call after
7372 an interrupt without having to save/restore the input registers.
7373 This also prevents kernel data from leaking to application code. */
7374 return lookup_attribute ("syscall_linkage",
7375 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))) != NULL;
7378 /* Conditional return patterns can't represent the use of `b0' as
7379 the return address, so we force the value live this way. */
7383 /* Likewise for ar.pfs, which is used by br.ret. */
7391 /* Return true if REGNO is used by the frame unwinder. */
7394 ia64_eh_uses (regno)
7397 if (! reload_completed)
7400 if (current_frame_info.reg_save_b0
7401 && regno == current_frame_info.reg_save_b0)
7403 if (current_frame_info.reg_save_pr
7404 && regno == current_frame_info.reg_save_pr)
7406 if (current_frame_info.reg_save_ar_pfs
7407 && regno == current_frame_info.reg_save_ar_pfs)
7409 if (current_frame_info.reg_save_ar_unat
7410 && regno == current_frame_info.reg_save_ar_unat)
7412 if (current_frame_info.reg_save_ar_lc
7413 && regno == current_frame_info.reg_save_ar_lc)
7419 /* Return true if this goes in small data/bss. */
7421 /* ??? We could also support own long data here. Generating movl/add/ld8
7422 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7423 code faster because there is one less load. This also includes incomplete
7424 types which can't go in sdata/sbss. */
7427 ia64_in_small_data_p (exp)
7430 if (TARGET_NO_SDATA)
7433 /* We want to merge strings, so we never consider them small data. */
7434 if (TREE_CODE (exp) == STRING_CST)
7437 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
7439 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
7440 if (strcmp (section, ".sdata") == 0
7441 || strcmp (section, ".sbss") == 0)
7446 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
7448 /* If this is an incomplete type with size 0, then we can't put it
7449 in sdata because it might be too big when completed. */
7450 if (size > 0 && size <= ia64_section_threshold)
7457 /* Output assembly directives for prologue regions. */
7459 /* The current basic block number. */
7461 static bool last_block;
7463 /* True if we need a copy_state command at the start of the next block. */
7465 static bool need_copy_state;
7467 /* The function emits unwind directives for the start of an epilogue. */
7472 /* If this isn't the last block of the function, then we need to label the
7473 current state, and copy it back in at the start of the next block. */
7477 fprintf (asm_out_file, "\t.label_state 1\n");
7478 need_copy_state = true;
7481 fprintf (asm_out_file, "\t.restore sp\n");
7484 /* This function processes a SET pattern looking for specific patterns
7485 which result in emitting an assembly directive required for unwinding. */
7488 process_set (asm_out_file, pat)
7492 rtx src = SET_SRC (pat);
7493 rtx dest = SET_DEST (pat);
7494 int src_regno, dest_regno;
7496 /* Look for the ALLOC insn. */
7497 if (GET_CODE (src) == UNSPEC_VOLATILE
7498 && XINT (src, 1) == UNSPECV_ALLOC
7499 && GET_CODE (dest) == REG)
7501 dest_regno = REGNO (dest);
7503 /* If this isn't the final destination for ar.pfs, the alloc
7504 shouldn't have been marked frame related. */
7505 if (dest_regno != current_frame_info.reg_save_ar_pfs)
7508 fprintf (asm_out_file, "\t.save ar.pfs, r%d\n",
7509 ia64_dbx_register_number (dest_regno));
7513 /* Look for SP = .... */
7514 if (GET_CODE (dest) == REG && REGNO (dest) == STACK_POINTER_REGNUM)
7516 if (GET_CODE (src) == PLUS)
7518 rtx op0 = XEXP (src, 0);
7519 rtx op1 = XEXP (src, 1);
7520 if (op0 == dest && GET_CODE (op1) == CONST_INT)
7522 if (INTVAL (op1) < 0)
7523 fprintf (asm_out_file, "\t.fframe "HOST_WIDE_INT_PRINT_DEC"\n",
7526 process_epilogue ();
7531 else if (GET_CODE (src) == REG
7532 && REGNO (src) == HARD_FRAME_POINTER_REGNUM)
7533 process_epilogue ();
7540 /* Register move we need to look at. */
7541 if (GET_CODE (dest) == REG && GET_CODE (src) == REG)
7543 src_regno = REGNO (src);
7544 dest_regno = REGNO (dest);
7549 /* Saving return address pointer. */
7550 if (dest_regno != current_frame_info.reg_save_b0)
7552 fprintf (asm_out_file, "\t.save rp, r%d\n",
7553 ia64_dbx_register_number (dest_regno));
7557 if (dest_regno != current_frame_info.reg_save_pr)
7559 fprintf (asm_out_file, "\t.save pr, r%d\n",
7560 ia64_dbx_register_number (dest_regno));
7563 case AR_UNAT_REGNUM:
7564 if (dest_regno != current_frame_info.reg_save_ar_unat)
7566 fprintf (asm_out_file, "\t.save ar.unat, r%d\n",
7567 ia64_dbx_register_number (dest_regno));
7571 if (dest_regno != current_frame_info.reg_save_ar_lc)
7573 fprintf (asm_out_file, "\t.save ar.lc, r%d\n",
7574 ia64_dbx_register_number (dest_regno));
7577 case STACK_POINTER_REGNUM:
7578 if (dest_regno != HARD_FRAME_POINTER_REGNUM
7579 || ! frame_pointer_needed)
7581 fprintf (asm_out_file, "\t.vframe r%d\n",
7582 ia64_dbx_register_number (dest_regno));
7586 /* Everything else should indicate being stored to memory. */
7591 /* Memory store we need to look at. */
7592 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
7598 if (GET_CODE (XEXP (dest, 0)) == REG)
7600 base = XEXP (dest, 0);
7603 else if (GET_CODE (XEXP (dest, 0)) == PLUS
7604 && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT)
7606 base = XEXP (XEXP (dest, 0), 0);
7607 off = INTVAL (XEXP (XEXP (dest, 0), 1));
7612 if (base == hard_frame_pointer_rtx)
7614 saveop = ".savepsp";
7617 else if (base == stack_pointer_rtx)
7622 src_regno = REGNO (src);
7626 if (current_frame_info.reg_save_b0 != 0)
7628 fprintf (asm_out_file, "\t%s rp, %ld\n", saveop, off);
7632 if (current_frame_info.reg_save_pr != 0)
7634 fprintf (asm_out_file, "\t%s pr, %ld\n", saveop, off);
7638 if (current_frame_info.reg_save_ar_lc != 0)
7640 fprintf (asm_out_file, "\t%s ar.lc, %ld\n", saveop, off);
7644 if (current_frame_info.reg_save_ar_pfs != 0)
7646 fprintf (asm_out_file, "\t%s ar.pfs, %ld\n", saveop, off);
7649 case AR_UNAT_REGNUM:
7650 if (current_frame_info.reg_save_ar_unat != 0)
7652 fprintf (asm_out_file, "\t%s ar.unat, %ld\n", saveop, off);
7659 fprintf (asm_out_file, "\t.save.g 0x%x\n",
7660 1 << (src_regno - GR_REG (4)));
7668 fprintf (asm_out_file, "\t.save.b 0x%x\n",
7669 1 << (src_regno - BR_REG (1)));
7676 fprintf (asm_out_file, "\t.save.f 0x%x\n",
7677 1 << (src_regno - FR_REG (2)));
7680 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
7681 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
7682 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
7683 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
7684 fprintf (asm_out_file, "\t.save.gf 0x0, 0x%x\n",
7685 1 << (src_regno - FR_REG (12)));
7697 /* This function looks at a single insn and emits any directives
7698 required to unwind this insn. */
7700 process_for_unwind_directive (asm_out_file, insn)
7704 if (flag_unwind_tables
7705 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
7709 if (GET_CODE (insn) == NOTE
7710 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_BASIC_BLOCK)
7712 last_block = NOTE_BASIC_BLOCK (insn)->next_bb == EXIT_BLOCK_PTR;
7714 /* Restore unwind state from immediately before the epilogue. */
7715 if (need_copy_state)
7717 fprintf (asm_out_file, "\t.body\n");
7718 fprintf (asm_out_file, "\t.copy_state 1\n");
7719 need_copy_state = false;
7723 if (GET_CODE (insn) == NOTE || ! RTX_FRAME_RELATED_P (insn))
7726 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
7728 pat = XEXP (pat, 0);
7730 pat = PATTERN (insn);
7732 switch (GET_CODE (pat))
7735 process_set (asm_out_file, pat);
7741 int limit = XVECLEN (pat, 0);
7742 for (par_index = 0; par_index < limit; par_index++)
7744 rtx x = XVECEXP (pat, 0, par_index);
7745 if (GET_CODE (x) == SET)
7746 process_set (asm_out_file, x);
7759 ia64_init_builtins ()
7761 tree psi_type_node = build_pointer_type (integer_type_node);
7762 tree pdi_type_node = build_pointer_type (long_integer_type_node);
7764 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
7765 tree si_ftype_psi_si_si
7766 = build_function_type_list (integer_type_node,
7767 psi_type_node, integer_type_node,
7768 integer_type_node, NULL_TREE);
7770 /* __sync_val_compare_and_swap_di */
7771 tree di_ftype_pdi_di_di
7772 = build_function_type_list (long_integer_type_node,
7773 pdi_type_node, long_integer_type_node,
7774 long_integer_type_node, NULL_TREE);
7775 /* __sync_bool_compare_and_swap_di */
7776 tree si_ftype_pdi_di_di
7777 = build_function_type_list (integer_type_node,
7778 pdi_type_node, long_integer_type_node,
7779 long_integer_type_node, NULL_TREE);
7780 /* __sync_synchronize */
7781 tree void_ftype_void
7782 = build_function_type (void_type_node, void_list_node);
7784 /* __sync_lock_test_and_set_si */
7785 tree si_ftype_psi_si
7786 = build_function_type_list (integer_type_node,
7787 psi_type_node, integer_type_node, NULL_TREE);
7789 /* __sync_lock_test_and_set_di */
7790 tree di_ftype_pdi_di
7791 = build_function_type_list (long_integer_type_node,
7792 pdi_type_node, long_integer_type_node,
7795 /* __sync_lock_release_si */
7797 = build_function_type_list (void_type_node, psi_type_node, NULL_TREE);
7799 /* __sync_lock_release_di */
7801 = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
7803 #define def_builtin(name, type, code) \
7804 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
7806 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si,
7807 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI);
7808 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di,
7809 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI);
7810 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si,
7811 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI);
7812 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di,
7813 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI);
7815 def_builtin ("__sync_synchronize", void_ftype_void,
7816 IA64_BUILTIN_SYNCHRONIZE);
7818 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si,
7819 IA64_BUILTIN_LOCK_TEST_AND_SET_SI);
7820 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di,
7821 IA64_BUILTIN_LOCK_TEST_AND_SET_DI);
7822 def_builtin ("__sync_lock_release_si", void_ftype_psi,
7823 IA64_BUILTIN_LOCK_RELEASE_SI);
7824 def_builtin ("__sync_lock_release_di", void_ftype_pdi,
7825 IA64_BUILTIN_LOCK_RELEASE_DI);
7827 def_builtin ("__builtin_ia64_bsp",
7828 build_function_type (ptr_type_node, void_list_node),
7831 def_builtin ("__builtin_ia64_flushrs",
7832 build_function_type (void_type_node, void_list_node),
7833 IA64_BUILTIN_FLUSHRS);
7835 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
7836 IA64_BUILTIN_FETCH_AND_ADD_SI);
7837 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si,
7838 IA64_BUILTIN_FETCH_AND_SUB_SI);
7839 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si,
7840 IA64_BUILTIN_FETCH_AND_OR_SI);
7841 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si,
7842 IA64_BUILTIN_FETCH_AND_AND_SI);
7843 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si,
7844 IA64_BUILTIN_FETCH_AND_XOR_SI);
7845 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si,
7846 IA64_BUILTIN_FETCH_AND_NAND_SI);
7848 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si,
7849 IA64_BUILTIN_ADD_AND_FETCH_SI);
7850 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si,
7851 IA64_BUILTIN_SUB_AND_FETCH_SI);
7852 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si,
7853 IA64_BUILTIN_OR_AND_FETCH_SI);
7854 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si,
7855 IA64_BUILTIN_AND_AND_FETCH_SI);
7856 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si,
7857 IA64_BUILTIN_XOR_AND_FETCH_SI);
7858 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si,
7859 IA64_BUILTIN_NAND_AND_FETCH_SI);
7861 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di,
7862 IA64_BUILTIN_FETCH_AND_ADD_DI);
7863 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di,
7864 IA64_BUILTIN_FETCH_AND_SUB_DI);
7865 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di,
7866 IA64_BUILTIN_FETCH_AND_OR_DI);
7867 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di,
7868 IA64_BUILTIN_FETCH_AND_AND_DI);
7869 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di,
7870 IA64_BUILTIN_FETCH_AND_XOR_DI);
7871 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di,
7872 IA64_BUILTIN_FETCH_AND_NAND_DI);
7874 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di,
7875 IA64_BUILTIN_ADD_AND_FETCH_DI);
7876 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di,
7877 IA64_BUILTIN_SUB_AND_FETCH_DI);
7878 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di,
7879 IA64_BUILTIN_OR_AND_FETCH_DI);
7880 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di,
7881 IA64_BUILTIN_AND_AND_FETCH_DI);
7882 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di,
7883 IA64_BUILTIN_XOR_AND_FETCH_DI);
7884 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di,
7885 IA64_BUILTIN_NAND_AND_FETCH_DI);
7890 /* Expand fetch_and_op intrinsics. The basic code sequence is:
7898 cmpxchgsz.acq tmp = [ptr], tmp
7899 } while (tmp != ret)
7903 ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
7905 enum machine_mode mode;
7909 rtx ret, label, tmp, ccv, insn, mem, value;
7912 arg0 = TREE_VALUE (arglist);
7913 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7914 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
7915 #ifdef POINTERS_EXTEND_UNSIGNED
7916 if (GET_MODE(mem) != Pmode)
7917 mem = convert_memory_address (Pmode, mem);
7919 value = expand_expr (arg1, NULL_RTX, mode, 0);
7921 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
7922 MEM_VOLATILE_P (mem) = 1;
7924 if (target && register_operand (target, mode))
7927 ret = gen_reg_rtx (mode);
7929 emit_insn (gen_mf ());
7931 /* Special case for fetchadd instructions. */
7932 if (binoptab == add_optab && fetchadd_operand (value, VOIDmode))
7935 insn = gen_fetchadd_acq_si (ret, mem, value);
7937 insn = gen_fetchadd_acq_di (ret, mem, value);
7942 tmp = gen_reg_rtx (mode);
7943 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
7944 emit_move_insn (tmp, mem);
7946 label = gen_label_rtx ();
7948 emit_move_insn (ret, tmp);
7949 emit_move_insn (ccv, tmp);
7951 /* Perform the specific operation. Special case NAND by noticing
7952 one_cmpl_optab instead. */
7953 if (binoptab == one_cmpl_optab)
7955 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
7956 binoptab = and_optab;
7958 tmp = expand_binop (mode, binoptab, tmp, value, tmp, 1, OPTAB_WIDEN);
7961 insn = gen_cmpxchg_acq_si (tmp, mem, tmp, ccv);
7963 insn = gen_cmpxchg_acq_di (tmp, mem, tmp, ccv);
7966 emit_cmp_and_jump_insns (tmp, ret, NE, 0, mode, 1, label);
7971 /* Expand op_and_fetch intrinsics. The basic code sequence is:
7978 ret = tmp <op> value;
7979 cmpxchgsz.acq tmp = [ptr], ret
7980 } while (tmp != old)
7984 ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
7986 enum machine_mode mode;
7990 rtx old, label, tmp, ret, ccv, insn, mem, value;
7993 arg0 = TREE_VALUE (arglist);
7994 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7995 mem = expand_expr (arg0, NULL_RTX, Pmode, 0);
7996 #ifdef POINTERS_EXTEND_UNSIGNED
7997 if (GET_MODE(mem) != Pmode)
7998 mem = convert_memory_address (Pmode, mem);
8001 value = expand_expr (arg1, NULL_RTX, mode, 0);
8003 mem = gen_rtx_MEM (mode, force_reg (Pmode, mem));
8004 MEM_VOLATILE_P (mem) = 1;
8006 if (target && ! register_operand (target, mode))
8009 emit_insn (gen_mf ());
8010 tmp = gen_reg_rtx (mode);
8011 old = gen_reg_rtx (mode);
8012 ccv = gen_rtx_REG (mode, AR_CCV_REGNUM);
8014 emit_move_insn (tmp, mem);
8016 label = gen_label_rtx ();
8018 emit_move_insn (old, tmp);
8019 emit_move_insn (ccv, tmp);
8021 /* Perform the specific operation. Special case NAND by noticing
8022 one_cmpl_optab instead. */
8023 if (binoptab == one_cmpl_optab)
8025 tmp = expand_unop (mode, binoptab, tmp, NULL, OPTAB_WIDEN);
8026 binoptab = and_optab;
8028 ret = expand_binop (mode, binoptab, tmp, value, target, 1, OPTAB_WIDEN);
8031 insn = gen_cmpxchg_acq_si (tmp, mem, ret, ccv);
8033 insn = gen_cmpxchg_acq_di (tmp, mem, ret, ccv);
8036 emit_cmp_and_jump_insns (tmp, old, NE, 0, mode, 1, label);
8041 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8045 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8048 For bool_ it's the same except return ret == oldval.
8052 ia64_expand_compare_and_swap (rmode, mode, boolp, arglist, target)
8053 enum machine_mode rmode;
8054 enum machine_mode mode;
8059 tree arg0, arg1, arg2;
8060 rtx mem, old, new, ccv, tmp, insn;
8062 arg0 = TREE_VALUE (arglist);
8063 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8064 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8065 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8066 old = expand_expr (arg1, NULL_RTX, mode, 0);
8067 new = expand_expr (arg2, NULL_RTX, mode, 0);
8069 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8070 MEM_VOLATILE_P (mem) = 1;
8072 if (! register_operand (old, mode))
8073 old = copy_to_mode_reg (mode, old);
8074 if (! register_operand (new, mode))
8075 new = copy_to_mode_reg (mode, new);
8077 if (! boolp && target && register_operand (target, mode))
8080 tmp = gen_reg_rtx (mode);
8082 ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
8084 emit_move_insn (ccv, old);
8087 rtx ccvtmp = gen_reg_rtx (DImode);
8088 emit_insn (gen_zero_extendsidi2 (ccvtmp, old));
8089 emit_move_insn (ccv, ccvtmp);
8091 emit_insn (gen_mf ());
8093 insn = gen_cmpxchg_acq_si (tmp, mem, new, ccv);
8095 insn = gen_cmpxchg_acq_di (tmp, mem, new, ccv);
8101 target = gen_reg_rtx (rmode);
8102 return emit_store_flag_force (target, EQ, tmp, old, mode, 1, 1);
8108 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8111 ia64_expand_lock_test_and_set (mode, arglist, target)
8112 enum machine_mode mode;
8117 rtx mem, new, ret, insn;
8119 arg0 = TREE_VALUE (arglist);
8120 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8121 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8122 new = expand_expr (arg1, NULL_RTX, mode, 0);
8124 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8125 MEM_VOLATILE_P (mem) = 1;
8126 if (! register_operand (new, mode))
8127 new = copy_to_mode_reg (mode, new);
8129 if (target && register_operand (target, mode))
8132 ret = gen_reg_rtx (mode);
8135 insn = gen_xchgsi (ret, mem, new);
8137 insn = gen_xchgdi (ret, mem, new);
8143 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8146 ia64_expand_lock_release (mode, arglist, target)
8147 enum machine_mode mode;
8149 rtx target ATTRIBUTE_UNUSED;
8154 arg0 = TREE_VALUE (arglist);
8155 mem = expand_expr (arg0, NULL_RTX, ptr_mode, 0);
8157 mem = gen_rtx_MEM (mode, force_reg (ptr_mode, mem));
8158 MEM_VOLATILE_P (mem) = 1;
8160 emit_move_insn (mem, const0_rtx);
8166 ia64_expand_builtin (exp, target, subtarget, mode, ignore)
8169 rtx subtarget ATTRIBUTE_UNUSED;
8170 enum machine_mode mode ATTRIBUTE_UNUSED;
8171 int ignore ATTRIBUTE_UNUSED;
8173 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8174 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8175 tree arglist = TREE_OPERAND (exp, 1);
8176 enum machine_mode rmode = VOIDmode;
8180 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8181 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8186 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8187 case IA64_BUILTIN_LOCK_RELEASE_SI:
8188 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8189 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8190 case IA64_BUILTIN_FETCH_AND_OR_SI:
8191 case IA64_BUILTIN_FETCH_AND_AND_SI:
8192 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8193 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8194 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8195 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8196 case IA64_BUILTIN_OR_AND_FETCH_SI:
8197 case IA64_BUILTIN_AND_AND_FETCH_SI:
8198 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8199 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8203 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8208 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8213 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8214 case IA64_BUILTIN_LOCK_RELEASE_DI:
8215 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8216 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8217 case IA64_BUILTIN_FETCH_AND_OR_DI:
8218 case IA64_BUILTIN_FETCH_AND_AND_DI:
8219 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8220 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8221 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8222 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8223 case IA64_BUILTIN_OR_AND_FETCH_DI:
8224 case IA64_BUILTIN_AND_AND_FETCH_DI:
8225 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8226 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8236 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI:
8237 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI:
8238 return ia64_expand_compare_and_swap (rmode, mode, 1, arglist,
8241 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI:
8242 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI:
8243 return ia64_expand_compare_and_swap (rmode, mode, 0, arglist,
8246 case IA64_BUILTIN_SYNCHRONIZE:
8247 emit_insn (gen_mf ());
8250 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI:
8251 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI:
8252 return ia64_expand_lock_test_and_set (mode, arglist, target);
8254 case IA64_BUILTIN_LOCK_RELEASE_SI:
8255 case IA64_BUILTIN_LOCK_RELEASE_DI:
8256 return ia64_expand_lock_release (mode, arglist, target);
8258 case IA64_BUILTIN_BSP:
8259 if (! target || ! register_operand (target, DImode))
8260 target = gen_reg_rtx (DImode);
8261 emit_insn (gen_bsp_value (target));
8262 #ifdef POINTERS_EXTEND_UNSIGNED
8263 target = convert_memory_address (ptr_mode, target);
8267 case IA64_BUILTIN_FLUSHRS:
8268 emit_insn (gen_flushrs ());
8271 case IA64_BUILTIN_FETCH_AND_ADD_SI:
8272 case IA64_BUILTIN_FETCH_AND_ADD_DI:
8273 return ia64_expand_fetch_and_op (add_optab, mode, arglist, target);
8275 case IA64_BUILTIN_FETCH_AND_SUB_SI:
8276 case IA64_BUILTIN_FETCH_AND_SUB_DI:
8277 return ia64_expand_fetch_and_op (sub_optab, mode, arglist, target);
8279 case IA64_BUILTIN_FETCH_AND_OR_SI:
8280 case IA64_BUILTIN_FETCH_AND_OR_DI:
8281 return ia64_expand_fetch_and_op (ior_optab, mode, arglist, target);
8283 case IA64_BUILTIN_FETCH_AND_AND_SI:
8284 case IA64_BUILTIN_FETCH_AND_AND_DI:
8285 return ia64_expand_fetch_and_op (and_optab, mode, arglist, target);
8287 case IA64_BUILTIN_FETCH_AND_XOR_SI:
8288 case IA64_BUILTIN_FETCH_AND_XOR_DI:
8289 return ia64_expand_fetch_and_op (xor_optab, mode, arglist, target);
8291 case IA64_BUILTIN_FETCH_AND_NAND_SI:
8292 case IA64_BUILTIN_FETCH_AND_NAND_DI:
8293 return ia64_expand_fetch_and_op (one_cmpl_optab, mode, arglist, target);
8295 case IA64_BUILTIN_ADD_AND_FETCH_SI:
8296 case IA64_BUILTIN_ADD_AND_FETCH_DI:
8297 return ia64_expand_op_and_fetch (add_optab, mode, arglist, target);
8299 case IA64_BUILTIN_SUB_AND_FETCH_SI:
8300 case IA64_BUILTIN_SUB_AND_FETCH_DI:
8301 return ia64_expand_op_and_fetch (sub_optab, mode, arglist, target);
8303 case IA64_BUILTIN_OR_AND_FETCH_SI:
8304 case IA64_BUILTIN_OR_AND_FETCH_DI:
8305 return ia64_expand_op_and_fetch (ior_optab, mode, arglist, target);
8307 case IA64_BUILTIN_AND_AND_FETCH_SI:
8308 case IA64_BUILTIN_AND_AND_FETCH_DI:
8309 return ia64_expand_op_and_fetch (and_optab, mode, arglist, target);
8311 case IA64_BUILTIN_XOR_AND_FETCH_SI:
8312 case IA64_BUILTIN_XOR_AND_FETCH_DI:
8313 return ia64_expand_op_and_fetch (xor_optab, mode, arglist, target);
8315 case IA64_BUILTIN_NAND_AND_FETCH_SI:
8316 case IA64_BUILTIN_NAND_AND_FETCH_DI:
8317 return ia64_expand_op_and_fetch (one_cmpl_optab, mode, arglist, target);
8326 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8327 most significant bits of the stack slot. */
8330 ia64_hpux_function_arg_padding (mode, type)
8331 enum machine_mode mode;
8334 /* Exception to normal case for structures/unions/etc. */
8336 if (type && AGGREGATE_TYPE_P (type)
8337 && int_size_in_bytes (type) < UNITS_PER_WORD)
8340 /* This is the standard FUNCTION_ARG_PADDING with !BYTES_BIG_ENDIAN
8341 hardwired to be true. */
8343 return((mode == BLKmode
8344 ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
8345 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
8346 : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
8347 ? downward : upward);
8350 /* Linked list of all external functions that are to be emitted by GCC.
8351 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8352 order to avoid putting out names that are never really used. */
8354 struct extern_func_list
8356 struct extern_func_list *next; /* next external */
8357 char *name; /* name of the external */
8358 } *extern_func_head = 0;
8361 ia64_hpux_add_extern_decl (name)
8364 struct extern_func_list *p;
8366 p = (struct extern_func_list *) xmalloc (sizeof (struct extern_func_list));
8367 p->name = xmalloc (strlen (name) + 1);
8368 strcpy(p->name, name);
8369 p->next = extern_func_head;
8370 extern_func_head = p;
8373 /* Print out the list of used global functions. */
8376 ia64_hpux_file_end ()
8378 while (extern_func_head)
8380 const char *real_name;
8383 real_name = (* targetm.strip_name_encoding) (extern_func_head->name);
8384 decl = maybe_get_identifier (real_name);
8387 || (! TREE_ASM_WRITTEN (decl) && TREE_SYMBOL_REFERENCED (decl)))
8390 TREE_ASM_WRITTEN (decl) = 1;
8391 (*targetm.asm_out.globalize_label) (asm_out_file,
8392 extern_func_head->name);
8393 fputs (TYPE_ASM_OP, asm_out_file);
8394 assemble_name (asm_out_file, extern_func_head->name);
8395 putc (',', asm_out_file);
8396 fprintf (asm_out_file, TYPE_OPERAND_FMT, "function");
8397 putc ('\n', asm_out_file);
8399 extern_func_head = extern_func_head->next;
8404 /* Switch to the section to which we should output X. The only thing
8405 special we do here is to honor small data. */
8408 ia64_select_rtx_section (mode, x, align)
8409 enum machine_mode mode;
8411 unsigned HOST_WIDE_INT align;
8413 if (GET_MODE_SIZE (mode) > 0
8414 && GET_MODE_SIZE (mode) <= ia64_section_threshold)
8417 default_elf_select_rtx_section (mode, x, align);
8420 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8421 Pretend flag_pic is always set. */
8424 ia64_rwreloc_select_section (exp, reloc, align)
8427 unsigned HOST_WIDE_INT align;
8429 default_elf_select_section_1 (exp, reloc, align, true);
8433 ia64_rwreloc_unique_section (decl, reloc)
8437 default_unique_section_1 (decl, reloc, true);
8441 ia64_rwreloc_select_rtx_section (mode, x, align)
8442 enum machine_mode mode;
8444 unsigned HOST_WIDE_INT align;
8446 int save_pic = flag_pic;
8448 ia64_select_rtx_section (mode, x, align);
8449 flag_pic = save_pic;
8453 ia64_rwreloc_section_type_flags (decl, name, reloc)
8458 return default_section_type_flags_1 (decl, name, reloc, true);
8462 /* Output the assembler code for a thunk function. THUNK_DECL is the
8463 declaration for the thunk function itself, FUNCTION is the decl for
8464 the target function. DELTA is an immediate constant offset to be
8465 added to THIS. If VCALL_OFFSET is nonzero, the word at
8466 *(*this + vcall_offset) should be added to THIS. */
8469 ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
8471 tree thunk ATTRIBUTE_UNUSED;
8472 HOST_WIDE_INT delta;
8473 HOST_WIDE_INT vcall_offset;
8476 rtx this, insn, funexp;
8478 reload_completed = 1;
8479 epilogue_completed = 1;
8482 /* Set things up as ia64_expand_prologue might. */
8483 last_scratch_gr_reg = 15;
8485 memset (¤t_frame_info, 0, sizeof (current_frame_info));
8486 current_frame_info.spill_cfa_off = -16;
8487 current_frame_info.n_input_regs = 1;
8488 current_frame_info.need_regstk = (TARGET_REG_NAMES != 0);
8490 if (!TARGET_REG_NAMES)
8491 reg_names[IN_REG (0)] = ia64_reg_numbers[0];
8493 /* Mark the end of the (empty) prologue. */
8494 emit_note (NOTE_INSN_PROLOGUE_END);
8496 this = gen_rtx_REG (Pmode, IN_REG (0));
8498 /* Apply the constant offset, if required. */
8501 rtx delta_rtx = GEN_INT (delta);
8503 if (!CONST_OK_FOR_I (delta))
8505 rtx tmp = gen_rtx_REG (Pmode, 2);
8506 emit_move_insn (tmp, delta_rtx);
8509 emit_insn (gen_adddi3 (this, this, delta_rtx));
8512 /* Apply the offset from the vtable, if required. */
8515 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
8516 rtx tmp = gen_rtx_REG (Pmode, 2);
8518 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
8520 if (!CONST_OK_FOR_J (vcall_offset))
8522 rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
8523 emit_move_insn (tmp2, vcall_offset_rtx);
8524 vcall_offset_rtx = tmp2;
8526 emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
8528 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
8530 emit_insn (gen_adddi3 (this, this, tmp));
8533 /* Generate a tail call to the target function. */
8534 if (! TREE_USED (function))
8536 assemble_external (function);
8537 TREE_USED (function) = 1;
8539 funexp = XEXP (DECL_RTL (function), 0);
8540 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8541 ia64_expand_call (NULL_RTX, funexp, NULL_RTX, 1);
8542 insn = get_last_insn ();
8543 SIBLING_CALL_P (insn) = 1;
8545 /* Code generation for calls relies on splitting. */
8546 reload_completed = 1;
8547 epilogue_completed = 1;
8548 try_split (PATTERN (insn), insn, 0);
8552 /* Run just enough of rest_of_compilation to get the insns emitted.
8553 There's not really enough bulk here to make other passes such as
8554 instruction scheduling worth while. Note that use_thunk calls
8555 assemble_start_function and assemble_end_function. */
8557 insn_locators_initialize ();
8558 emit_all_insn_group_barriers (NULL);
8559 insn = get_insns ();
8560 shorten_branches (insn);
8561 final_start_function (insn, file, 1);
8562 final (insn, file, 1, 0);
8563 final_end_function ();
8565 reload_completed = 0;
8566 epilogue_completed = 0;
8570 #include "gt-ia64.h"