1 ;;- Machine description for Intel 80960 chip for GNU C compiler
2 ;; Copyright (C) 1992, 1995, 1998 Free Software Foundation, Inc.
3 ;; Contributed by Steven McGeady, Intel Corp.
4 ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26 ;; There are very few (4) 'f' registers, they can't be loaded/stored from/to
27 ;; memory, and some instructions explicitly require them, so we get better
28 ;; code by discouraging pseudo-registers from being allocated to them.
29 ;; However, we do want to allow all patterns which can store to them to
30 ;; include them in their constraints, so we always use '*f' in a destination
31 ;; constraint except when 'f' is the only alternative.
33 ;; Insn attributes which describe the i960.
35 ;; Modscan is not used, since the compiler never emits any of these insns.
37 "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc"
38 (const_string "arith"))
40 ;; Length (in # of insns).
41 (define_attr "length" ""
42 (cond [(eq_attr "type" "load,fpload")
43 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
46 (eq_attr "type" "store,fpstore")
47 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
50 (eq_attr "type" "address")
54 (define_asm_attributes
55 [(set_attr "length" "1")
56 (set_attr "type" "multi")])
58 ;; (define_function_unit {name} {num-units} {n-users} {test}
59 ;; {ready-delay} {issue-delay} [{conflict-list}])
62 (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0)
63 (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0)
64 (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0)
65 (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0)
66 (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0)
68 ;; Memory with load-delay of 1 (i.e., 2 cycle load).
69 (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0)
71 ;; Floating point operations.
72 (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0)
73 (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0)
74 (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0)
75 (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0)
76 (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0)
77 (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0)
79 ;; Compare instructions.
80 ;; This controls RTL generation and register allocation.
82 ;; We generate RTL for comparisons and branches by having the cmpxx
83 ;; patterns store away the operands. Then, the scc and bcc patterns
84 ;; emit RTL for both the compare and the branch.
86 ;; We start with the DEFINE_EXPANDs, then DEFINE_INSNs to match
87 ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
88 ;; insns that actually require more than one machine instruction.
90 ;; Put cmpsi first because it is expected to be the most common.
92 (define_expand "cmpsi"
94 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
95 (match_operand:SI 1 "general_operand" "")))]
99 i960_compare_op0 = operands[0];
100 i960_compare_op1 = operands[1];
104 (define_expand "cmpdf"
106 (compare:CC (match_operand:DF 0 "register_operand" "r")
107 (match_operand:DF 1 "nonmemory_operand" "rGH")))]
111 i960_compare_op0 = operands[0];
112 i960_compare_op1 = operands[1];
116 (define_expand "cmpsf"
118 (compare:CC (match_operand:SF 0 "register_operand" "r")
119 (match_operand:SF 1 "nonmemory_operand" "rGH")))]
123 i960_compare_op0 = operands[0];
124 i960_compare_op1 = operands[1];
128 ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares.
132 (compare:CC (match_operand:SI 0 "register_operand" "d")
133 (match_operand:SI 1 "arith_operand" "dI")))]
136 [(set_attr "type" "compare")])
139 [(set (reg:CC_UNS 36)
140 (compare:CC_UNS (match_operand:SI 0 "register_operand" "d")
141 (match_operand:SI 1 "arith_operand" "dI")))]
144 [(set_attr "type" "compare")])
148 (compare:CC (match_operand:DF 0 "register_operand" "r")
149 (match_operand:DF 1 "nonmemory_operand" "rGH")))]
152 [(set_attr "type" "fpcc")])
156 (compare:CC (match_operand:SF 0 "register_operand" "r")
157 (match_operand:SF 1 "nonmemory_operand" "rGH")))]
160 [(set_attr "type" "fpcc")])
162 ;; Instruction definitions for branch-on-bit-set and clear insns.
167 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
169 (match_operand:SI 1 "arith_operand" "dI"))
171 (label_ref (match_operand 2 "" ""))
175 [(set_attr "type" "branch")])
180 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "d")
182 (match_operand:SI 1 "arith_operand" "dI"))
184 (label_ref (match_operand 2 "" ""))
188 [(set_attr "type" "branch")])
193 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
195 (match_operand:SI 1 "arith_operand" "dI"))
197 (label_ref (match_operand 2 "" ""))
201 [(set_attr "type" "branch")])
206 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
208 (match_operand:SI 1 "arith_operand" "dI"))
210 (label_ref (match_operand 2 "" ""))
214 [(set_attr "type" "branch")])
216 ;; ??? These will never match. The LOG_LINKs necessary to make these match
217 ;; are not created by flow. These remain as a reminder to make this work
222 (compare (match_operand:SI 0 "arith_operand" "d")
223 (match_operand:SI 1 "arith_operand" "+d")))
224 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
227 [(set_attr "type" "compare")])
230 [(set (reg:CC_UNS 36)
231 (compare (match_operand:SI 0 "arith_operand" "d")
232 (match_operand:SI 1 "arith_operand" "+d")))
233 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
236 [(set_attr "type" "compare")])
240 (compare (match_operand:SI 0 "arith_operand" "d")
241 (match_operand:SI 1 "arith_operand" "+d")))
242 (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
245 [(set_attr "type" "compare")])
248 [(set (reg:CC_UNS 36)
249 (compare (match_operand:SI 0 "arith_operand" "d")
250 (match_operand:SI 1 "arith_operand" "+d")))
251 (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
254 [(set_attr "type" "compare")])
256 ;; Templates to store result of condition.
257 ;; '1' is stored if condition is true.
258 ;; '0' is stored if condition is false.
259 ;; These should use predicate "general_operand", since
260 ;; gcc seems to be creating mem references which use these
264 [(set (match_operand:SI 0 "general_operand" "=d")
265 (eq:SI (match_dup 1) (const_int 0)))]
269 operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1);
273 [(set (match_operand:SI 0 "general_operand" "=d")
274 (ne:SI (match_dup 1) (const_int 0)))]
278 operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1);
282 [(set (match_operand:SI 0 "general_operand" "=d")
283 (gt:SI (match_dup 1) (const_int 0)))]
287 operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1);
290 (define_expand "sgtu"
291 [(set (match_operand:SI 0 "general_operand" "=d")
292 (gtu:SI (match_dup 1) (const_int 0)))]
296 operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1);
300 [(set (match_operand:SI 0 "general_operand" "=d")
301 (lt:SI (match_dup 1) (const_int 0)))]
305 operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1);
308 (define_expand "sltu"
309 [(set (match_operand:SI 0 "general_operand" "=d")
310 (ltu:SI (match_dup 1) (const_int 0)))]
314 operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1);
318 [(set (match_operand:SI 0 "general_operand" "=d")
319 (ge:SI (match_dup 1) (const_int 0)))]
323 operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1);
326 (define_expand "sgeu"
327 [(set (match_operand:SI 0 "general_operand" "=d")
328 (geu:SI (match_dup 1) (const_int 0)))]
332 operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1);
336 [(set (match_operand:SI 0 "general_operand" "=d")
337 (le:SI (match_dup 1) (const_int 0)))]
341 operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1);
344 (define_expand "sleu"
345 [(set (match_operand:SI 0 "general_operand" "=d")
346 (leu:SI (match_dup 1) (const_int 0)))]
350 operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1);
354 [(set (match_operand:SI 0 "general_operand" "=d")
355 (eq:SI (match_operand:SI 1 "register_operand" "d") (const_int 0)))]
358 [(set_attr "type" "alu2")])
361 [(set (match_operand:SI 0 "general_operand" "=d")
362 (match_operator:SI 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))]
365 [(set_attr "type" "compare")])
368 [(set (match_operand:SI 0 "general_operand" "=d")
369 (match_operator:SI 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))]
372 [(set_attr "type" "compare")])
374 ;; These control RTL generation for conditional jump insns
375 ;; and match them for register allocation.
379 (if_then_else (eq (match_dup 1)
381 (label_ref (match_operand 0 "" ""))
385 { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }")
389 (if_then_else (ne (match_dup 1)
391 (label_ref (match_operand 0 "" ""))
395 { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }")
399 (if_then_else (gt (match_dup 1)
401 (label_ref (match_operand 0 "" ""))
405 { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }")
407 (define_expand "bgtu"
409 (if_then_else (gtu (match_dup 1)
411 (label_ref (match_operand 0 "" ""))
415 { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }")
419 (if_then_else (lt (match_dup 1)
421 (label_ref (match_operand 0 "" ""))
425 { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }")
427 (define_expand "bltu"
429 (if_then_else (ltu (match_dup 1)
431 (label_ref (match_operand 0 "" ""))
435 { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }")
439 (if_then_else (ge (match_dup 1)
441 (label_ref (match_operand 0 "" ""))
445 { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }")
447 (define_expand "bgeu"
449 (if_then_else (geu (match_dup 1)
451 (label_ref (match_operand 0 "" ""))
455 { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }")
459 (if_then_else (le (match_dup 1)
461 (label_ref (match_operand 0 "" ""))
465 { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }")
467 (define_expand "bleu"
469 (if_then_else (leu (match_dup 1)
471 (label_ref (match_operand 0 "" ""))
475 { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }")
477 ;; Now the normal branch insns (forward and reverse).
481 (if_then_else (match_operator 0 "comparison_operator"
482 [(reg:CC 36) (const_int 0)])
483 (label_ref (match_operand 1 "" ""))
487 [(set_attr "type" "branch")])
491 (if_then_else (match_operator 0 "comparison_operator"
492 [(reg:CC 36) (const_int 0)])
494 (label_ref (match_operand 1 "" ""))))]
497 [(set_attr "type" "branch")])
501 (if_then_else (match_operator 0 "comparison_operator"
502 [(reg:CC_UNS 36) (const_int 0)])
503 (label_ref (match_operand 1 "" ""))
507 [(set_attr "type" "branch")])
511 (if_then_else (match_operator 0 "comparison_operator"
512 [(reg:CC_UNS 36) (const_int 0)])
514 (label_ref (match_operand 1 "" ""))))]
517 [(set_attr "type" "branch")])
522 (match_operator 0 "comparison_operator"
523 [(match_operand:SI 1 "arith_operand" "d")
524 (match_operand:SI 2 "arith_operand" "dI")])
525 (label_ref (match_operand 3 "" ""))
528 "cmp%S0%B0%R0%+ %2,%1,%l3"
529 [(set_attr "type" "branch")])
534 (match_operator 0 "comparison_operator"
535 [(match_operand:SI 1 "arith_operand" "d")
536 (match_operand:SI 2 "arith_operand" "dI")])
538 (label_ref (match_operand 3 "" ""))))]
540 "cmp%S0%B0%X0%+ %2,%1,%l3"
541 [(set_attr "type" "branch")])
543 ;; Now the trap instructions. The i960 appears to only have conditional
546 (define_insn ("trap")
547 [(trap_if (const_int 1) (const_int 0))]
549 "cmpo g0,g0 ; faulteq.t")
551 (define_expand "conditional_trap"
552 [(trap_if (match_operator 0 "comparison_operator"
553 [(match_dup 2) (const_int 0)])
554 (match_operand 1 "const_int_operand" "i"))]
558 operands[2] = gen_compare_reg (GET_CODE (operands[0]),
559 i960_compare_op0, i960_compare_op1);
563 [(trap_if (match_operator 0 "comparison_operator"
564 [(reg:CC 36) (const_int 0)])
565 (match_operand 1 "const_int_operand" "i"))]
570 [(trap_if (match_operator 0 "comparison_operator"
571 [(reg:CC_UNS 36) (const_int 0)])
572 (match_operand 1 "const_int_operand" "i"))]
576 ;; Normal move instructions.
577 ;; This code is based on the sparc machine description.
579 (define_expand "movsi"
580 [(set (match_operand:SI 0 "general_operand" "")
581 (match_operand:SI 1 "general_operand" ""))]
585 if (emit_move_sequence (operands, SImode))
589 ;; The store case can not be separate, because reload may convert a register
590 ;; to register move insn to a store (or load) insn without rerecognizing
593 ;; The i960 does not have any store constant to memory instruction. However,
594 ;; the calling convention is defined so that the arg pointer when it is not
595 ;; overwise being used is zero. Thus, we can handle store zero to memory
596 ;; by storing an unused arg pointer. The arg pointer will be unused if
597 ;; current_function_args_size is zero and this is not a stdarg/varargs
598 ;; function. This value of the former variable is not valid until after
599 ;; all rtl generation is complete, including function inlining (because a
600 ;; function that doesn't need an arg pointer may be inlined into a function
601 ;; that does need an arg pointer), so we must also check that
602 ;; rtx_equal_function_value_matters is zero.
605 [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
606 (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))]
607 "(current_function_args_size == 0
608 && current_function_varargs == 0
609 && current_function_stdarg == 0
610 && rtx_equal_function_value_matters == 0)
611 && (register_operand (operands[0], SImode)
612 || register_operand (operands[1], SImode)
613 || operands[1] == const0_rtx)"
616 switch (which_alternative)
619 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
621 if (GET_CODE (operands[1]) == REG)
622 return \"lda (%1),%0\";
624 return \"lda %1,%0\";
626 return \"mov %1,%0\";
628 return i960_output_ldconst (operands[0], operands[1]);
632 if (operands[1] == const0_rtx)
633 return \"st g14,%0\";
637 [(set_attr "type" "move,address,load,store")
638 (set_attr "length" "*,3,*,*")])
641 [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
642 (match_operand:SI 1 "general_operand" "dI,i,m,d"))]
643 "(current_function_args_size != 0
644 || current_function_varargs != 0
645 || current_function_stdarg != 0
646 || rtx_equal_function_value_matters != 0)
647 && (register_operand (operands[0], SImode)
648 || register_operand (operands[1], SImode))"
651 switch (which_alternative)
654 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
656 if (GET_CODE (operands[1]) == REG)
657 return \"lda (%1),%0\";
659 return \"lda %1,%0\";
661 return \"mov %1,%0\";
663 return i960_output_ldconst (operands[0], operands[1]);
670 [(set_attr "type" "move,address,load,store")
671 (set_attr "length" "*,3,*,*")])
673 (define_expand "movhi"
674 [(set (match_operand:HI 0 "general_operand" "")
675 (match_operand:HI 1 "general_operand" ""))]
679 if (emit_move_sequence (operands, HImode))
683 ;; Special pattern for zero stores to memory for functions which don't use
686 ;; The store case can not be separate. See above.
688 [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
689 (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))]
690 "(current_function_args_size == 0
691 && current_function_varargs == 0
692 && current_function_stdarg == 0
693 && rtx_equal_function_value_matters == 0)
694 && (register_operand (operands[0], HImode)
695 || register_operand (operands[1], HImode)
696 || operands[1] == const0_rtx)"
699 switch (which_alternative)
702 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
704 if (GET_CODE (operands[1]) == REG)
705 return \"lda (%1),%0\";
707 return \"lda %1,%0\";
709 return \"mov %1,%0\";
711 return i960_output_ldconst (operands[0], operands[1]);
713 return \"ldos %1,%0\";
715 if (operands[1] == const0_rtx)
716 return \"stos g14,%0\";
717 return \"stos %1,%0\";
720 [(set_attr "type" "move,misc,load,store")
721 (set_attr "length" "*,3,*,*")])
723 ;; The store case can not be separate. See above.
725 [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
726 (match_operand:HI 1 "general_operand" "dI,i,m,d"))]
727 "(current_function_args_size != 0
728 || current_function_varargs != 0
729 || current_function_stdarg != 0
730 || rtx_equal_function_value_matters != 0)
731 && (register_operand (operands[0], HImode)
732 || register_operand (operands[1], HImode))"
735 switch (which_alternative)
738 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
740 if (GET_CODE (operands[1]) == REG)
741 return \"lda (%1),%0\";
743 return \"lda %1,%0\";
745 return \"mov %1,%0\";
747 return i960_output_ldconst (operands[0], operands[1]);
749 return \"ldos %1,%0\";
751 return \"stos %1,%0\";
754 [(set_attr "type" "move,misc,load,store")
755 (set_attr "length" "*,3,*,*")])
757 (define_expand "movqi"
758 [(set (match_operand:QI 0 "general_operand" "")
759 (match_operand:QI 1 "general_operand" ""))]
763 if (emit_move_sequence (operands, QImode))
767 ;; The store case can not be separate. See comment above.
769 [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
770 (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))]
771 "(current_function_args_size == 0
772 && current_function_varargs == 0
773 && current_function_stdarg == 0
774 && rtx_equal_function_value_matters == 0)
775 && (register_operand (operands[0], QImode)
776 || register_operand (operands[1], QImode)
777 || operands[1] == const0_rtx)"
780 switch (which_alternative)
783 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
785 if (GET_CODE (operands[1]) == REG)
786 return \"lda (%1),%0\";
788 return \"lda %1,%0\";
790 return \"mov %1,%0\";
792 return i960_output_ldconst (operands[0], operands[1]);
794 return \"ldob %1,%0\";
796 if (operands[1] == const0_rtx)
797 return \"stob g14,%0\";
798 return \"stob %1,%0\";
801 [(set_attr "type" "move,misc,load,store")
802 (set_attr "length" "*,3,*,*")])
804 ;; The store case can not be separate. See comment above.
806 [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
807 (match_operand:QI 1 "general_operand" "dI,i,m,d"))]
808 "(current_function_args_size != 0
809 || current_function_varargs != 0
810 || current_function_stdarg != 0
811 || rtx_equal_function_value_matters != 0)
812 && (register_operand (operands[0], QImode)
813 || register_operand (operands[1], QImode))"
816 switch (which_alternative)
819 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
821 if (GET_CODE (operands[1]) == REG)
822 return \"lda (%1),%0\";
824 return \"lda %1,%0\";
826 return \"mov %1,%0\";
828 return i960_output_ldconst (operands[0], operands[1]);
830 return \"ldob %1,%0\";
832 return \"stob %1,%0\";
835 [(set_attr "type" "move,misc,load,store")
836 (set_attr "length" "*,3,*,*")])
838 (define_expand "movdi"
839 [(set (match_operand:DI 0 "general_operand" "")
840 (match_operand:DI 1 "general_operand" ""))]
844 if (emit_move_sequence (operands, DImode))
848 ;; The store case can not be separate. See comment above.
850 [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m,o")
851 (match_operand:DI 1 "general_operand" "d,I,i,m,d,J"))]
852 "(current_function_args_size == 0
853 && current_function_varargs == 0
854 && current_function_stdarg == 0
855 && rtx_equal_function_value_matters == 0)
856 && (register_operand (operands[0], DImode)
857 || register_operand (operands[1], DImode)
858 || operands[1] == const0_rtx)"
861 switch (which_alternative)
867 return i960_output_move_double (operands[0], operands[1]);
869 return i960_output_ldconst (operands[0], operands[1]);
871 return i960_output_move_double_zero (operands[0]);
874 [(set_attr "type" "move,move,load,load,store,store")])
876 ;; The store case can not be separate. See comment above.
878 [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m")
879 (match_operand:DI 1 "general_operand" "d,I,i,m,d"))]
880 "(current_function_args_size != 0
881 || current_function_varargs != 0
882 || current_function_stdarg != 0
883 || rtx_equal_function_value_matters != 0)
884 && (register_operand (operands[0], DImode)
885 || register_operand (operands[1], DImode))"
888 switch (which_alternative)
894 return i960_output_move_double (operands[0], operands[1]);
896 return i960_output_ldconst (operands[0], operands[1]);
899 [(set_attr "type" "move,move,load,load,store")])
901 (define_insn "*store_unaligned_di_reg"
902 [(set (match_operand:DI 0 "general_operand" "=d,m")
903 (match_operand:DI 1 "register_operand" "d,d"))
904 (clobber (match_scratch:SI 2 "=X,&d"))]
908 if (which_alternative == 0)
909 return i960_output_move_double (operands[0], operands[1]);
911 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
912 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
913 return \"lda %0,%2\;st %1,%3\;st %D1,%4\";
915 [(set_attr "type" "move,store")])
917 (define_expand "movti"
918 [(set (match_operand:TI 0 "general_operand" "")
919 (match_operand:TI 1 "general_operand" ""))]
923 if (emit_move_sequence (operands, TImode))
927 ;; The store case can not be separate. See comment above.
929 [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o")
930 (match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))]
931 "(current_function_args_size == 0
932 && current_function_varargs == 0
933 && current_function_stdarg == 0
934 && rtx_equal_function_value_matters == 0)
935 && (register_operand (operands[0], TImode)
936 || register_operand (operands[1], TImode)
937 || operands[1] == const0_rtx)"
940 switch (which_alternative)
946 return i960_output_move_quad (operands[0], operands[1]);
948 return i960_output_ldconst (operands[0], operands[1]);
950 return i960_output_move_quad_zero (operands[0]);
953 [(set_attr "type" "move,move,load,load,store,store")])
955 ;; The store case can not be separate. See comment above.
957 [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m")
958 (match_operand:TI 1 "general_operand" "d,I,i,m,d"))]
959 "(current_function_args_size != 0
960 || current_function_varargs != 0
961 || current_function_stdarg != 0
962 || rtx_equal_function_value_matters != 0)
963 && (register_operand (operands[0], TImode)
964 || register_operand (operands[1], TImode))"
967 switch (which_alternative)
973 return i960_output_move_quad (operands[0], operands[1]);
975 return i960_output_ldconst (operands[0], operands[1]);
978 [(set_attr "type" "move,move,load,load,store")])
980 (define_insn "*store_unaligned_ti_reg"
981 [(set (match_operand:TI 0 "general_operand" "=d,m")
982 (match_operand:TI 1 "register_operand" "d,d"))
983 (clobber (match_scratch:SI 2 "=X,&d"))]
987 if (which_alternative == 0)
988 return i960_output_move_quad (operands[0], operands[1]);
990 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
991 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
992 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
993 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
994 return \"lda %0,%2\;st %1,%3\;st %D1,%4\;st %E1,%5\;st %F1,%6\";
996 [(set_attr "type" "move,store")])
998 (define_expand "store_multiple"
999 [(set (match_operand:SI 0 "" "") ;;- dest
1000 (match_operand:SI 1 "" "")) ;;- src
1001 (use (match_operand:SI 2 "" ""))] ;;- nregs
1009 if (GET_CODE (operands[0]) != MEM
1010 || GET_CODE (operands[1]) != REG
1011 || GET_CODE (operands[2]) != CONST_INT)
1014 count = INTVAL (operands[2]);
1018 regno = REGNO (operands[1]);
1019 from = memory_address (SImode, XEXP (operands[0], 0));
1020 while (count >= 4 && ((regno & 3) == 0))
1022 emit_move_insn (change_address (operands[0], TImode, from),
1023 gen_rtx_REG (TImode, regno));
1026 from = memory_address (TImode, plus_constant (from, 16));
1028 while (count >= 2 && ((regno & 1) == 0))
1030 emit_move_insn (change_address (operands[0], DImode, from),
1031 gen_rtx_REG (DImode, regno));
1034 from = memory_address (DImode, plus_constant (from, 8));
1038 emit_move_insn (change_address (operands[0], SImode, from),
1039 gen_rtx_REG (SImode, regno));
1042 from = memory_address (SImode, plus_constant (from, 4));
1047 ;; Floating point move insns
1049 (define_expand "movdf"
1050 [(set (match_operand:DF 0 "general_operand" "")
1051 (match_operand:DF 1 "fpmove_src_operand" ""))]
1055 if (emit_move_sequence (operands, DFmode))
1060 [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o")
1061 (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
1062 "(current_function_args_size == 0
1063 && current_function_varargs == 0
1064 && current_function_stdarg == 0
1065 && rtx_equal_function_value_matters == 0)
1066 && (register_operand (operands[0], DFmode)
1067 || register_operand (operands[1], DFmode)
1068 || operands[1] == CONST0_RTX (DFmode))"
1071 switch (which_alternative)
1074 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1075 return \"movrl %1,%0\";
1077 return \"movl %1,%0\";
1079 return \"movrl %1,%0\";
1081 return i960_output_ldconst (operands[0], operands[1]);
1083 return \"ldl %1,%0\";
1085 return \"stl %1,%0\";
1087 operands[1] = adj_offsettable_operand (operands[0], 4);
1088 return \"st g14,%0\;st g14,%1\";
1091 [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
1094 [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m")
1095 (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1096 "(current_function_args_size != 0
1097 || current_function_varargs != 0
1098 || current_function_stdarg != 0
1099 || rtx_equal_function_value_matters != 0)
1100 && (register_operand (operands[0], DFmode)
1101 || register_operand (operands[1], DFmode))"
1104 switch (which_alternative)
1107 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1108 return \"movrl %1,%0\";
1110 return \"movl %1,%0\";
1112 return \"movrl %1,%0\";
1114 return i960_output_ldconst (operands[0], operands[1]);
1116 return \"ldl %1,%0\";
1118 return \"stl %1,%0\";
1121 [(set_attr "type" "move,move,load,fpload,fpstore")])
1123 (define_expand "movsf"
1124 [(set (match_operand:SF 0 "general_operand" "")
1125 (match_operand:SF 1 "fpmove_src_operand" ""))]
1129 if (emit_move_sequence (operands, SFmode))
1134 [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1135 (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
1136 "(current_function_args_size == 0
1137 && current_function_varargs == 0
1138 && current_function_stdarg == 0
1139 && rtx_equal_function_value_matters == 0)
1140 && (register_operand (operands[0], SFmode)
1141 || register_operand (operands[1], SFmode)
1142 || operands[1] == CONST0_RTX (SFmode))"
1145 switch (which_alternative)
1148 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1149 return \"movr %1,%0\";
1151 return \"mov %1,%0\";
1153 return \"movr %1,%0\";
1155 return i960_output_ldconst (operands[0], operands[1]);
1157 return \"ld %1,%0\";
1159 if (operands[1] == CONST0_RTX (SFmode))
1160 return \"st g14,%0\";
1161 return \"st %1,%0\";
1164 [(set_attr "type" "move,move,load,fpload,fpstore")])
1167 [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1168 (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1169 "(current_function_args_size != 0
1170 || current_function_varargs != 0
1171 || current_function_stdarg != 0
1172 || rtx_equal_function_value_matters != 0)
1173 && (register_operand (operands[0], SFmode)
1174 || register_operand (operands[1], SFmode))"
1177 switch (which_alternative)
1180 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1181 return \"movr %1,%0\";
1183 return \"mov %1,%0\";
1185 return \"movr %1,%0\";
1187 return i960_output_ldconst (operands[0], operands[1]);
1189 return \"ld %1,%0\";
1191 return \"st %1,%0\";
1194 [(set_attr "type" "move,move,load,fpload,fpstore")])
1196 ;; Mixed-mode moves with sign and zero-extension.
1198 ;; Note that the one starting from HImode comes before those for QImode
1199 ;; so that a constant operand will match HImode, not QImode.
1201 (define_expand "extendhisi2"
1202 [(set (match_operand:SI 0 "register_operand" "")
1204 (match_operand:HI 1 "nonimmediate_operand" "")))]
1208 if (GET_CODE (operand1) == REG
1209 || (GET_CODE (operand1) == SUBREG
1210 && GET_CODE (XEXP (operand1, 0)) == REG))
1212 rtx temp = gen_reg_rtx (SImode);
1213 rtx shift_16 = GEN_INT (16);
1214 int op1_subreg_word = 0;
1216 if (GET_CODE (operand1) == SUBREG)
1218 op1_subreg_word = SUBREG_WORD (operand1);
1219 operand1 = SUBREG_REG (operand1);
1221 if (GET_MODE (operand1) != SImode)
1222 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1224 emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1225 emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
1231 [(set (match_operand:SI 0 "register_operand" "=d")
1232 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1235 [(set_attr "type" "load")])
1237 (define_expand "extendqisi2"
1238 [(set (match_operand:SI 0 "register_operand" "")
1239 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1243 if (GET_CODE (operand1) == REG
1244 || (GET_CODE (operand1) == SUBREG
1245 && GET_CODE (XEXP (operand1, 0)) == REG))
1247 rtx temp = gen_reg_rtx (SImode);
1248 rtx shift_24 = GEN_INT (24);
1249 int op1_subreg_word = 0;
1251 if (GET_CODE (operand1) == SUBREG)
1253 op1_subreg_word = SUBREG_WORD (operand1);
1254 operand1 = SUBREG_REG (operand1);
1256 if (GET_MODE (operand1) != SImode)
1257 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1259 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1260 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1266 [(set (match_operand:SI 0 "register_operand" "=d")
1267 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1270 [(set_attr "type" "load")])
1272 (define_expand "extendqihi2"
1273 [(set (match_operand:HI 0 "register_operand" "")
1275 (match_operand:QI 1 "nonimmediate_operand" "")))]
1279 if (GET_CODE (operand1) == REG
1280 || (GET_CODE (operand1) == SUBREG
1281 && GET_CODE (XEXP (operand1, 0)) == REG))
1283 rtx temp = gen_reg_rtx (SImode);
1284 rtx shift_24 = GEN_INT (24);
1285 int op0_subreg_word = 0;
1286 int op1_subreg_word = 0;
1288 if (GET_CODE (operand1) == SUBREG)
1290 op1_subreg_word = SUBREG_WORD (operand1);
1291 operand1 = SUBREG_REG (operand1);
1293 if (GET_MODE (operand1) != SImode)
1294 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1296 if (GET_CODE (operand0) == SUBREG)
1298 op0_subreg_word = SUBREG_WORD (operand0);
1299 operand0 = SUBREG_REG (operand0);
1301 if (GET_MODE (operand0) != SImode)
1302 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_word);
1304 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1305 emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1311 [(set (match_operand:HI 0 "register_operand" "=d")
1312 (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1315 [(set_attr "type" "load")])
1317 (define_expand "zero_extendhisi2"
1318 [(set (match_operand:SI 0 "register_operand" "")
1320 (match_operand:HI 1 "nonimmediate_operand" "")))]
1324 if (GET_CODE (operand1) == REG
1325 || (GET_CODE (operand1) == SUBREG
1326 && GET_CODE (XEXP (operand1, 0)) == REG))
1328 rtx temp = gen_reg_rtx (SImode);
1329 rtx shift_16 = GEN_INT (16);
1330 int op1_subreg_word = 0;
1332 if (GET_CODE (operand1) == SUBREG)
1334 op1_subreg_word = SUBREG_WORD (operand1);
1335 operand1 = SUBREG_REG (operand1);
1337 if (GET_MODE (operand1) != SImode)
1338 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1340 emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1341 emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
1347 [(set (match_operand:SI 0 "register_operand" "=d")
1348 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1351 [(set_attr "type" "load")])
1353 ;; Using shifts here generates much better code than doing an `and 255'.
1354 ;; This is mainly because the `and' requires loading the constant separately,
1355 ;; the constant is likely to get optimized, and then the compiler can't
1356 ;; optimize the `and' because it doesn't know that one operand is a constant.
1358 (define_expand "zero_extendqisi2"
1359 [(set (match_operand:SI 0 "register_operand" "")
1360 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1364 if (GET_CODE (operand1) == REG
1365 || (GET_CODE (operand1) == SUBREG
1366 && GET_CODE (XEXP (operand1, 0)) == REG))
1368 rtx temp = gen_reg_rtx (SImode);
1369 rtx shift_24 = GEN_INT (24);
1370 int op1_subreg_word = 0;
1372 if (GET_CODE (operand1) == SUBREG)
1374 op1_subreg_word = SUBREG_WORD (operand1);
1375 operand1 = SUBREG_REG (operand1);
1377 if (GET_MODE (operand1) != SImode)
1378 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1380 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1381 emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1387 [(set (match_operand:SI 0 "register_operand" "=d")
1388 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1391 [(set_attr "type" "load")])
1393 (define_expand "zero_extendqihi2"
1394 [(set (match_operand:HI 0 "register_operand" "")
1396 (match_operand:QI 1 "nonimmediate_operand" "")))]
1400 if (GET_CODE (operand1) == REG
1401 || (GET_CODE (operand1) == SUBREG
1402 && GET_CODE (XEXP (operand1, 0)) == REG))
1404 rtx temp = gen_reg_rtx (SImode);
1405 rtx shift_24 = GEN_INT (24);
1406 int op0_subreg_word = 0;
1407 int op1_subreg_word = 0;
1409 if (GET_CODE (operand1) == SUBREG)
1411 op1_subreg_word = SUBREG_WORD (operand1);
1412 operand1 = SUBREG_REG (operand1);
1414 if (GET_MODE (operand1) != SImode)
1415 operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1417 if (GET_CODE (operand0) == SUBREG)
1419 op0_subreg_word = SUBREG_WORD (operand0);
1420 operand0 = SUBREG_REG (operand0);
1422 if (GET_MODE (operand0) != SImode)
1423 operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subreg_word);
1425 emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1426 emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1432 [(set (match_operand:HI 0 "register_operand" "=d")
1433 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1436 [(set_attr "type" "load")])
1438 ;; Conversions between float and double.
1440 (define_insn "extendsfdf2"
1441 [(set (match_operand:DF 0 "register_operand" "=*f,d")
1442 (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))]
1447 [(set_attr "type" "fpmove")])
1449 (define_insn "truncdfsf2"
1450 [(set (match_operand:SF 0 "register_operand" "=d")
1452 (match_operand:DF 1 "fp_arith_operand" "fGH")))]
1455 [(set_attr "type" "fpmove")])
1457 ;; Conversion between fixed point and floating point.
1459 (define_insn "floatsidf2"
1460 [(set (match_operand:DF 0 "register_operand" "=f")
1461 (float:DF (match_operand:SI 1 "register_operand" "d")))]
1464 [(set_attr "type" "fpcvt")])
1466 (define_insn "floatsisf2"
1467 [(set (match_operand:SF 0 "register_operand" "=d*f")
1468 (float:SF (match_operand:SI 1 "register_operand" "d")))]
1471 [(set_attr "type" "fpcvt")])
1473 ;; Convert a float to an actual integer.
1474 ;; Truncation is performed as part of the conversion.
1475 ;; The i960 requires conversion from DFmode to DImode to make
1476 ;; unsigned conversions work properly.
1478 (define_insn "fixuns_truncdfdi2"
1479 [(set (match_operand:DI 0 "register_operand" "=d")
1480 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1483 [(set_attr "type" "fpcvt")])
1485 (define_insn "fixuns_truncsfdi2"
1486 [(set (match_operand:DI 0 "register_operand" "=d")
1487 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))]
1490 [(set_attr "type" "fpcvt")])
1492 (define_insn "fix_truncdfsi2"
1493 [(set (match_operand:SI 0 "register_operand" "=d")
1494 (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1497 [(set_attr "type" "fpcvt")])
1499 (define_expand "fixuns_truncdfsi2"
1500 [(set (match_operand:SI 0 "register_operand" "")
1501 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))]
1505 rtx temp = gen_reg_rtx (DImode);
1506 emit_insn (gen_rtx_SET (VOIDmode, temp,
1507 gen_rtx_UNSIGNED_FIX (DImode,
1508 gen_rtx_FIX (DFmode,
1510 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1511 gen_rtx_SUBREG (SImode, temp, 0)));
1515 (define_insn "fix_truncsfsi2"
1516 [(set (match_operand:SI 0 "register_operand" "=d")
1517 (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))]
1520 [(set_attr "type" "fpcvt")])
1522 (define_expand "fixuns_truncsfsi2"
1523 [(set (match_operand:SI 0 "register_operand" "")
1524 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))]
1528 rtx temp = gen_reg_rtx (DImode);
1529 emit_insn (gen_rtx_SET (VOIDmode, temp,
1530 gen_rtx_UNSIGNED_FIX (DImode,
1531 gen_rtx_FIX (SFmode,
1533 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
1534 gen_rtx_SUBREG (SImode, temp, 0)));
1538 ;; Arithmetic instructions.
1540 (define_insn "subsi3"
1541 [(set (match_operand:SI 0 "register_operand" "=d")
1542 (minus:SI (match_operand:SI 1 "arith_operand" "dI")
1543 (match_operand:SI 2 "arith_operand" "dI")))]
1547 ;; Try to generate an lda instruction when it would be faster than an
1549 ;; Some assemblers apparently won't accept two addresses added together.
1551 ;; ??? The condition should be improved to reject the case of two
1552 ;; symbolic constants.
1555 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1556 (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn")
1557 (match_operand:SI 2 "arith32_operand" "dn,dn,i")))]
1558 "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))"
1561 if (GET_CODE (operands[1]) == CONST_INT)
1563 rtx tmp = operands[1];
1564 operands[1] = operands[2];
1567 if (GET_CODE (operands[2]) == CONST_INT
1568 && GET_CODE (operands[1]) == REG
1569 && i960_last_insn_type != I_TYPE_REG)
1571 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
1572 return \"subo %n2,%1,%0\";
1573 else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1574 return \"addo %1,%2,%0\";
1576 /* Non-canonical results (op1 == const, op2 != const) have been seen
1577 in reload output when both operands were symbols before reload, so
1578 we deal with it here. This may be a fault of the constraints above. */
1579 if (CONSTANT_P (operands[1]))
1581 if (CONSTANT_P (operands[2]))
1582 return \"lda %1+%2,%0\";
1584 return \"lda %1(%2),%0\";
1586 return \"lda %2(%1),%0\";
1589 (define_insn "addsi3"
1590 [(set (match_operand:SI 0 "register_operand" "=d")
1591 (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI")
1592 (match_operand:SI 2 "signed_arith_operand" "dIK")))]
1596 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1597 return \"subo %n2,%1,%0\";
1598 if (i960_bypass (insn, operands[1], operands[2], 0))
1599 return \"addo %2,%1,%0\";
1600 return \"addo %1,%2,%0\";
1603 (define_insn "mulsi3"
1604 [(set (match_operand:SI 0 "register_operand" "=d")
1605 (mult:SI (match_operand:SI 1 "arith_operand" "%dI")
1606 (match_operand:SI 2 "arith_operand" "dI")))]
1610 if (i960_bypass (insn, operands[1], operands[2], 0))
1611 return \"mulo %2,%1,%0\";
1612 return \"mulo %1,%2,%0\";
1614 [(set_attr "type" "mult")])
1616 (define_insn "umulsidi3"
1617 [(set (match_operand:DI 0 "register_operand" "=d")
1618 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1619 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1623 if (i960_bypass (insn, operands[1], operands[2], 0))
1624 return \"emul %2,%1,%0\";
1625 return \"emul %1,%2,%0\";
1627 [(set_attr "type" "mult")])
1630 [(set (match_operand:DI 0 "register_operand" "=d")
1631 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%d"))
1632 (match_operand:SI 2 "literal" "I")))]
1636 if (i960_bypass (insn, operands[1], operands[2], 0))
1637 return \"emul %2,%1,%0\";
1638 return \"emul %1,%2,%0\";
1640 [(set_attr "type" "mult")])
1642 ;; This goes after the move/add/sub/mul instructions
1643 ;; because those instructions are better when they apply.
1646 [(set (match_operand:SI 0 "register_operand" "=d")
1647 (match_operand:SI 1 "address_operand" "p"))]
1650 [(set_attr "type" "load")])
1652 ;; This will never be selected because of an "optimization" that GCC does.
1653 ;; It always converts divides by a power of 2 into a sequence of instructions
1654 ;; that does a right shift, and then corrects the result if it was negative.
1657 ;; [(set (match_operand:SI 0 "register_operand" "=d")
1658 ;; (div:SI (match_operand:SI 1 "arith_operand" "dI")
1659 ;; (match_operand:SI 2 "power2_operand" "nI")))]
1662 ;; operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1663 ;; return \"shrdi %2,%1,%0\";
1666 (define_insn "divsi3"
1667 [(set (match_operand:SI 0 "register_operand" "=d")
1668 (div:SI (match_operand:SI 1 "arith_operand" "dI")
1669 (match_operand:SI 2 "arith_operand" "dI")))]
1672 [(set_attr "type" "div")])
1674 (define_insn "udivsi3"
1675 [(set (match_operand:SI 0 "register_operand" "=d")
1676 (udiv:SI (match_operand:SI 1 "arith_operand" "dI")
1677 (match_operand:SI 2 "arith_operand" "dI")))]
1680 [(set_attr "type" "div")])
1682 ;; We must use `remi' not `modi' here, to ensure that `%' has the effects
1683 ;; specified by the ANSI C standard.
1685 (define_insn "modsi3"
1686 [(set (match_operand:SI 0 "register_operand" "=d")
1687 (mod:SI (match_operand:SI 1 "arith_operand" "dI")
1688 (match_operand:SI 2 "arith_operand" "dI")))]
1691 [(set_attr "type" "div")])
1693 (define_insn "umodsi3"
1694 [(set (match_operand:SI 0 "register_operand" "=d")
1695 (umod:SI (match_operand:SI 1 "arith_operand" "dI")
1696 (match_operand:SI 2 "arith_operand" "dI")))]
1699 [(set_attr "type" "div")])
1701 ;; And instructions (with complement also).
1703 (define_insn "andsi3"
1704 [(set (match_operand:SI 0 "register_operand" "=d")
1705 (and:SI (match_operand:SI 1 "register_operand" "%d")
1706 (match_operand:SI 2 "logic_operand" "dIM")))]
1710 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1711 return \"andnot %C2,%1,%0\";
1712 if (i960_bypass (insn, operands[1], operands[2], 0))
1713 return \"and %2,%1,%0\";
1714 return \"and %1,%2,%0\";
1718 [(set (match_operand:SI 0 "register_operand" "=d")
1719 (and:SI (match_operand:SI 1 "arith_operand" "dI")
1720 (match_operand:SI 2 "cmplpower2_operand" "n")))]
1724 operands[2] = GEN_INT (bitpos (~INTVAL (operands[2])));
1725 return \"clrbit %2,%1,%0\";
1729 [(set (match_operand:SI 0 "register_operand" "=d")
1730 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1731 (match_operand:SI 2 "logic_operand" "dIM")))]
1735 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1736 return \"nor %C2,%1,%0\";
1737 if (i960_bypass (insn, operands[1], operands[2], 0))
1738 return \"notand %2,%1,%0\";
1739 return \"andnot %1,%2,%0\";
1743 [(set (match_operand:SI 0 "register_operand" "=d")
1744 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
1745 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
1749 if (i960_bypass (insn, operands[1], operands[2], 0))
1750 return \"nand %2,%1,%0\";
1751 return \"nand %1,%2,%0\";
1754 (define_insn "iorsi3"
1755 [(set (match_operand:SI 0 "register_operand" "=d")
1756 (ior:SI (match_operand:SI 1 "register_operand" "%d")
1757 (match_operand:SI 2 "logic_operand" "dIM")))]
1761 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1762 return \"ornot %C2,%1,%0\";
1763 if (i960_bypass (insn, operands[1], operands[2], 0))
1764 return \"or %2,%1,%0\";
1765 return \"or %1,%2,%0\";
1769 [(set (match_operand:SI 0 "register_operand" "=d")
1770 (ior:SI (match_operand:SI 1 "register_operand" "d")
1771 (match_operand:SI 2 "power2_operand" "n")))]
1775 operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1776 return \"setbit %2,%1,%0\";
1780 [(set (match_operand:SI 0 "register_operand" "=d")
1781 (ior:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
1782 (match_operand:SI 2 "logic_operand" "dIM")))]
1786 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1787 return \"nand %C2,%1,%0\";
1788 if (i960_bypass (insn, operands[1], operands[2], 0))
1789 return \"notor %2,%1,%0\";
1790 return \"ornot %1,%2,%0\";
1794 [(set (match_operand:SI 0 "register_operand" "=d")
1795 (and:SI (not:SI (match_operand:SI 1 "register_operand" "%d"))
1796 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
1800 if (i960_bypass (insn, operands[1], operands[2], 0))
1801 return \"nor %2,%1,%0\";
1802 return \"nor %1,%2,%0\";
1805 (define_insn "xorsi3"
1806 [(set (match_operand:SI 0 "register_operand" "=d")
1807 (xor:SI (match_operand:SI 1 "register_operand" "%d")
1808 (match_operand:SI 2 "logic_operand" "dIM")))]
1812 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1813 return \"xnor %C2,%1,%0\";
1814 if (i960_bypass (insn, operands[1], operands[2], 0))
1815 return \"xor %2,%1,%0\";
1816 return \"xor %1,%2,%0\";
1820 [(set (match_operand:SI 0 "register_operand" "=d")
1821 (xor:SI (match_operand:SI 1 "arith_operand" "dI")
1822 (match_operand:SI 2 "power2_operand" "n")))]
1826 operands[2] = GEN_INT (bitpos (INTVAL (operands[2])));
1827 return \"notbit %2,%1,%0\";
1831 [(set (match_operand:SI 0 "register_operand" "=d")
1832 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%d")
1833 (match_operand:SI 2 "register_operand" "d"))))]
1837 if (i960_bypass (insn, operands[1], operands[2], 0))
1838 return \"xnor %2,%1,%0\";
1839 return \"xnor %2,%1,%0\";
1843 [(set (match_operand:SI 0 "register_operand" "=d")
1844 (ior:SI (ashift:SI (const_int 1)
1845 (match_operand:SI 1 "register_operand" "d"))
1846 (match_operand:SI 2 "arith_operand" "dI")))]
1850 ;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg)
1852 [(set (match_operand:SI 0 "register_operand" "=d")
1853 (and:SI (rotate:SI (const_int -2)
1854 (match_operand:SI 1 "register_operand" "d"))
1855 (match_operand:SI 2 "register_operand" "d")))]
1859 ;; The above pattern canonicalizes to this when both the input and output
1860 ;; are the same pseudo-register.
1862 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d")
1864 (match_operand:SI 1 "register_operand" "d"))
1870 [(set (match_operand:SI 0 "register_operand" "=d")
1871 (xor:SI (ashift:SI (const_int 1)
1872 (match_operand:SI 1 "register_operand" "d"))
1873 (match_operand:SI 2 "arith_operand" "dI")))]
1877 (define_insn "negsi2"
1878 [(set (match_operand:SI 0 "register_operand" "=d")
1879 (neg:SI (match_operand:SI 1 "arith_operand" "dI")))]
1882 [(set_attr "length" "1")])
1884 (define_insn "one_cmplsi2"
1885 [(set (match_operand:SI 0 "register_operand" "=d")
1886 (not:SI (match_operand:SI 1 "arith_operand" "dI")))]
1889 [(set_attr "length" "1")])
1891 ;; Floating point arithmetic instructions.
1893 (define_insn "adddf3"
1894 [(set (match_operand:DF 0 "register_operand" "=d*f")
1895 (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
1896 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1899 [(set_attr "type" "fpadd")])
1901 (define_insn "addsf3"
1902 [(set (match_operand:SF 0 "register_operand" "=d*f")
1903 (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
1904 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1907 [(set_attr "type" "fpadd")])
1910 (define_insn "subdf3"
1911 [(set (match_operand:DF 0 "register_operand" "=d*f")
1912 (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1913 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1916 [(set_attr "type" "fpadd")])
1918 (define_insn "subsf3"
1919 [(set (match_operand:SF 0 "register_operand" "=d*f")
1920 (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1921 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1924 [(set_attr "type" "fpadd")])
1927 (define_insn "muldf3"
1928 [(set (match_operand:DF 0 "register_operand" "=d*f")
1929 (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
1930 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1933 [(set_attr "type" "fpmul")])
1935 (define_insn "mulsf3"
1936 [(set (match_operand:SF 0 "register_operand" "=d*f")
1937 (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
1938 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1941 [(set_attr "type" "fpmul")])
1944 (define_insn "divdf3"
1945 [(set (match_operand:DF 0 "register_operand" "=d*f")
1946 (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1947 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1950 [(set_attr "type" "fpdiv")])
1952 (define_insn "divsf3"
1953 [(set (match_operand:SF 0 "register_operand" "=d*f")
1954 (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1955 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1958 [(set_attr "type" "fpdiv")])
1960 (define_insn "negdf2"
1961 [(set (match_operand:DF 0 "register_operand" "=d,d*f")
1962 (neg:DF (match_operand:DF 1 "register_operand" "d,r")))]
1966 if (which_alternative == 0)
1968 if (REGNO (operands[0]) == REGNO (operands[1]))
1969 return \"notbit 31,%D1,%D0\";
1970 return \"mov %1,%0\;notbit 31,%D1,%D0\";
1972 return \"subrl %1,0f0.0,%0\";
1974 [(set_attr "type" "fpadd")])
1976 (define_insn "negsf2"
1977 [(set (match_operand:SF 0 "register_operand" "=d,d*f")
1978 (neg:SF (match_operand:SF 1 "register_operand" "d,r")))]
1983 [(set_attr "type" "fpadd")])
1985 ;;; The abs patterns also work even if the target machine doesn't have
1986 ;;; floating point, because in that case dstreg and srcreg will always be
1989 (define_insn "absdf2"
1990 [(set (match_operand:DF 0 "register_operand" "=d*f")
1991 (abs:DF (match_operand:DF 1 "register_operand" "df")))]
1995 int dstreg = REGNO (operands[0]);
1996 int srcreg = REGNO (operands[1]);
2002 if (dstreg != srcreg)
2003 output_asm_insn (\"mov %1,%0\", operands);
2004 return \"clrbit 31,%D1,%D0\";
2006 /* Src is an fp reg. */
2007 return \"movrl %1,%0\;clrbit 31,%D1,%D0\";
2010 return \"cpysre %1,0f0.0,%0\";
2011 return \"movrl %1,%0\;cpysre %0,0f0.0,%0\";
2013 [(set_attr "type" "multi")])
2015 (define_insn "abssf2"
2016 [(set (match_operand:SF 0 "register_operand" "=d*f")
2017 (abs:SF (match_operand:SF 1 "register_operand" "df")))]
2021 int dstreg = REGNO (operands[0]);
2022 int srcreg = REGNO (operands[1]);
2024 if (dstreg < 32 && srcreg < 32)
2025 return \"clrbit 31,%1,%0\";
2027 if (dstreg >= 32 && srcreg >= 32)
2028 return \"cpysre %1,0f0.0,%0\";
2031 return \"movr %1,%0\;clrbit 31,%0,%0\";
2033 return \"movr %1,%0\;cpysre %0,0f0.0,%0\";
2035 [(set_attr "type" "multi")])
2037 ;; Tetra (16 byte) float support.
2039 (define_expand "cmpxf"
2041 (compare:CC (match_operand:XF 0 "register_operand" "")
2042 (match_operand:XF 1 "nonmemory_operand" "")))]
2046 i960_compare_op0 = operands[0];
2047 i960_compare_op1 = operands[1];
2053 (compare:CC (match_operand:XF 0 "register_operand" "f")
2054 (match_operand:XF 1 "nonmemory_operand" "fGH")))]
2057 [(set_attr "type" "fpcc")])
2059 (define_expand "movxf"
2060 [(set (match_operand:XF 0 "general_operand" "")
2061 (match_operand:XF 1 "fpmove_src_operand" ""))]
2065 if (emit_move_sequence (operands, XFmode))
2070 [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m")
2071 (match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
2072 "register_operand (operands[0], XFmode)
2073 || register_operand (operands[1], XFmode)"
2076 switch (which_alternative)
2079 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
2080 return \"movre %1,%0\";
2082 return \"movq %1,%0\";
2084 return \"movre %1,%0\";
2086 return i960_output_ldconst (operands[0], operands[1]);
2088 return \"ldt %1,%0\";
2090 return \"stt %1,%0\";
2093 [(set_attr "type" "move,move,load,fpload,fpstore")])
2095 (define_insn "extendsfxf2"
2096 [(set (match_operand:XF 0 "register_operand" "=f,d")
2098 (match_operand:SF 1 "register_operand" "d,f")))]
2103 [(set_attr "type" "fpmove")])
2105 (define_insn "extenddfxf2"
2106 [(set (match_operand:XF 0 "register_operand" "=f,d")
2108 (match_operand:DF 1 "register_operand" "d,f")))]
2113 [(set_attr "type" "fpmove")])
2115 (define_insn "truncxfdf2"
2116 [(set (match_operand:DF 0 "register_operand" "=d")
2118 (match_operand:XF 1 "register_operand" "f")))]
2121 [(set_attr "type" "fpmove")])
2123 (define_insn "truncxfsf2"
2124 [(set (match_operand:SF 0 "register_operand" "=d")
2126 (match_operand:XF 1 "register_operand" "f")))]
2129 [(set_attr "type" "fpmove")])
2131 (define_insn "floatsixf2"
2132 [(set (match_operand:XF 0 "register_operand" "=f")
2133 (float:XF (match_operand:SI 1 "register_operand" "d")))]
2136 [(set_attr "type" "fpcvt")])
2138 (define_insn "fix_truncxfsi2"
2139 [(set (match_operand:SI 0 "register_operand" "=d")
2140 (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
2143 [(set_attr "type" "fpcvt")])
2145 (define_insn "fixuns_truncxfsi2"
2146 [(set (match_operand:SI 0 "register_operand" "=d")
2147 (unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))]
2150 [(set_attr "type" "fpcvt")])
2152 (define_insn "addxf3"
2153 [(set (match_operand:XF 0 "register_operand" "=f")
2154 (plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
2155 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2158 [(set_attr "type" "fpadd")])
2160 (define_insn "subxf3"
2161 [(set (match_operand:XF 0 "register_operand" "=f")
2162 (minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
2163 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2166 [(set_attr "type" "fpadd")])
2168 (define_insn "mulxf3"
2169 [(set (match_operand:XF 0 "register_operand" "=f")
2170 (mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH")
2171 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2174 [(set_attr "type" "fpmul")])
2176 (define_insn "divxf3"
2177 [(set (match_operand:XF 0 "register_operand" "=f")
2178 (div:XF (match_operand:XF 1 "nonmemory_operand" "fGH")
2179 (match_operand:XF 2 "nonmemory_operand" "fGH")))]
2182 [(set_attr "type" "fpdiv")])
2184 (define_insn "negxf2"
2185 [(set (match_operand:XF 0 "register_operand" "=f")
2186 (neg:XF (match_operand:XF 1 "register_operand" "f")))]
2189 [(set_attr "type" "fpadd")])
2191 (define_insn "absxf2"
2192 [(set (match_operand:XF 0 "register_operand" "=f")
2193 (abs:XF (match_operand:XF 1 "register_operand" "f")))]
2195 "cpysre %1,0f0.0,%0"
2196 [(set_attr "type" "fpmove")])
2198 ;; Arithmetic shift instructions.
2200 ;; The shli instruction generates an overflow fault if the sign changes.
2201 ;; In the case of overflow, it does not give the natural result, it instead
2202 ;; gives the last shift value before the overflow. We can not use this
2203 ;; instruction because gcc thinks that arithmetic left shift and logical
2204 ;; left shift are identical, and sometimes canonicalizes the logical left
2205 ;; shift to an arithmetic left shift. Therefore we must always use the
2206 ;; logical left shift instruction.
2208 (define_insn "ashlsi3"
2209 [(set (match_operand:SI 0 "register_operand" "=d")
2210 (ashift:SI (match_operand:SI 1 "arith_operand" "dI")
2211 (match_operand:SI 2 "arith_operand" "dI")))]
2214 [(set_attr "type" "alu2")])
2216 (define_insn "ashrsi3"
2217 [(set (match_operand:SI 0 "register_operand" "=d")
2218 (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2219 (match_operand:SI 2 "arith_operand" "dI")))]
2222 [(set_attr "type" "alu2")])
2224 (define_insn "lshrsi3"
2225 [(set (match_operand:SI 0 "register_operand" "=d")
2226 (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2227 (match_operand:SI 2 "arith_operand" "dI")))]
2230 [(set_attr "type" "alu2")])
2232 ;; Unconditional and other jump instructions.
2236 (label_ref (match_operand 0 "" "")))]
2239 [(set_attr "type" "branch")])
2241 (define_insn "indirect_jump"
2242 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
2245 [(set_attr "type" "branch")])
2247 (define_insn "tablejump"
2248 [(set (pc) (match_operand:SI 0 "register_operand" "d"))
2249 (use (label_ref (match_operand 1 "" "")))]
2254 return \"bx %l1(%0)\";
2258 [(set_attr "type" "branch")])
2260 ;;- jump to subroutine
2262 (define_expand "call"
2263 [(call (match_operand:SI 0 "memory_operand" "m")
2264 (match_operand:SI 1 "immediate_operand" "i"))]
2268 emit_insn (gen_call_internal (operands[0], operands[1],
2269 virtual_outgoing_args_rtx));
2273 ;; We need a call saved register allocated for the match_scratch, so we use
2274 ;; 'l' because all local registers are call saved.
2276 ;; ??? I would prefer to use a match_scratch here, but match_scratch allocated
2277 ;; registers can't be used for spills. In a function with lots of calls,
2278 ;; local-alloc may allocate all local registers to a match_scratch, leaving
2279 ;; no local registers available for spills.
2281 (define_insn "call_internal"
2282 [(call (match_operand:SI 0 "memory_operand" "m")
2283 (match_operand:SI 1 "immediate_operand" "i"))
2284 (use (match_operand:SI 2 "address_operand" "p"))
2285 (clobber (reg:SI 19))]
2287 "* return i960_output_call_insn (operands[0], operands[1], operands[2],
2289 [(set_attr "type" "call")])
2291 (define_expand "call_value"
2292 [(set (match_operand 0 "register_operand" "=d")
2293 (call (match_operand:SI 1 "memory_operand" "m")
2294 (match_operand:SI 2 "immediate_operand" "i")))]
2298 emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
2299 virtual_outgoing_args_rtx));
2303 ;; We need a call saved register allocated for the match_scratch, so we use
2304 ;; 'l' because all local registers are call saved.
2306 (define_insn "call_value_internal"
2307 [(set (match_operand 0 "register_operand" "=d")
2308 (call (match_operand:SI 1 "memory_operand" "m")
2309 (match_operand:SI 2 "immediate_operand" "i")))
2310 (use (match_operand:SI 3 "address_operand" "p"))
2311 (clobber (reg:SI 19))]
2313 "* return i960_output_call_insn (operands[1], operands[2], operands[3],
2315 [(set_attr "type" "call")])
2317 (define_insn "return"
2320 "* return i960_output_ret_insn (insn);"
2321 [(set_attr "type" "branch")])
2323 ;; A return instruction. Used only by nonlocal_goto to change the
2324 ;; stack pointer, frame pointer, previous frame pointer and the return
2325 ;; instruction pointer.
2328 (unspec_volatile [(const_int 0)] 3)]
2331 [(set_attr "type" "branch")
2332 (set_attr "length" "1")])
2334 (define_expand "nonlocal_goto"
2335 [(match_operand:SI 0 "" "")
2336 (match_operand:SI 1 "general_operand" "")
2337 (match_operand:SI 2 "general_operand" "")
2338 (match_operand:SI 3 "general_operand" "")]
2342 rtx chain = operands[0];
2343 rtx handler = operands[1];
2344 rtx stack = operands[2];
2345 rtx label = operands[3];
2347 /* We must restore the stack pointer, frame pointer, previous frame
2348 pointer and the return instruction pointer. Since the ret
2349 instruction does all this for us with one instruction, we arrange
2350 everything so that ret will do everything we need done. */
2352 /* First, we must flush the register windows, so that we can modify
2353 the saved local registers on the stack directly and because we
2354 are going to change the previous frame pointer. */
2356 emit_insn (gen_flush_register_windows ());
2358 /* Load the static chain value for the containing fn into fp. This is needed
2359 because STACK refers to fp. */
2360 emit_move_insn (hard_frame_pointer_rtx, chain);
2362 /* Now move the adjusted value into the pfp register for the following return
2364 emit_move_insn (gen_rtx (REG, SImode, 16),
2365 plus_constant (hard_frame_pointer_rtx, -64));
2367 /* Next, we put the address that we want to transfer to, into the
2368 saved $rip value in the frame. Once we ret below, that value
2369 will be loaded into the pc (IP). */
2371 emit_move_insn (gen_rtx (MEM, SImode,
2372 plus_constant (hard_frame_pointer_rtx, -56)),
2375 /* Next, we put stack into the saved $sp value in the frame. */
2376 emit_move_insn (gen_rtx (MEM, SImode,
2377 plus_constant (hard_frame_pointer_rtx, -60)),
2380 /* And finally, we can now just ret to get all the values saved
2381 above into all the right registers, and also, all the local
2382 register that were in use in the function, are restored from
2383 their saved values (from the call instruction) on the stack
2384 because we are very careful to ret from the exact save area in
2385 use during the original call. */
2387 emit_insn (gen_ret ());
2392 ;; Special insn to flush register windows.
2393 (define_insn "flush_register_windows"
2394 [(unspec_volatile [(const_int 0)] 1)]
2397 [(set_attr "type" "misc")
2398 (set_attr "length" "1")])
2405 ;; Various peephole optimizations for multiple-word moves, loads, and stores.
2406 ;; Multiple register moves.
2410 [(set (match_operand:SI 0 "register_operand" "=r")
2411 (match_operand:SI 1 "register_operand" "r"))
2412 (set (match_operand:SI 2 "register_operand" "=r")
2413 (match_operand:SI 3 "register_operand" "r"))
2414 (set (match_operand:SI 4 "register_operand" "=r")
2415 (match_operand:SI 5 "register_operand" "r"))
2416 (set (match_operand:SI 6 "register_operand" "=r")
2417 (match_operand:SI 7 "register_operand" "r"))]
2418 "((REGNO (operands[0]) & 3) == 0)
2419 && ((REGNO (operands[1]) & 3) == 0)
2420 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2421 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2422 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2423 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2424 && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2425 && (REGNO (operands[1]) + 3 == REGNO (operands[7]))"
2430 [(set (match_operand:DI 0 "register_operand" "=r")
2431 (match_operand:DI 1 "register_operand" "r"))
2432 (set (match_operand:DI 2 "register_operand" "=r")
2433 (match_operand:DI 3 "register_operand" "r"))]
2434 "((REGNO (operands[0]) & 3) == 0)
2435 && ((REGNO (operands[1]) & 3) == 0)
2436 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2437 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2442 [(set (match_operand:DI 0 "register_operand" "=r")
2443 (match_operand:DI 1 "register_operand" "r"))
2444 (set (match_operand:SI 2 "register_operand" "=r")
2445 (match_operand:SI 3 "register_operand" "r"))
2446 (set (match_operand:SI 4 "register_operand" "=r")
2447 (match_operand:SI 5 "register_operand" "r"))]
2448 "((REGNO (operands[0]) & 3) == 0)
2449 && ((REGNO (operands[1]) & 3) == 0)
2450 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2451 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))
2452 && (REGNO (operands[0]) + 3 == REGNO (operands[4]))
2453 && (REGNO (operands[1]) + 3 == REGNO (operands[5]))"
2458 [(set (match_operand:SI 0 "register_operand" "=r")
2459 (match_operand:SI 1 "register_operand" "r"))
2460 (set (match_operand:SI 2 "register_operand" "=r")
2461 (match_operand:SI 3 "register_operand" "r"))
2462 (set (match_operand:DI 4 "register_operand" "=r")
2463 (match_operand:DI 5 "register_operand" "r"))]
2464 "((REGNO (operands[0]) & 3) == 0)
2465 && ((REGNO (operands[1]) & 3) == 0)
2466 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2467 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2468 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2469 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2474 [(set (match_operand:DI 0 "register_operand" "=r")
2475 (match_operand:DI 1 "register_operand" "r"))
2476 (set (match_operand:SI 2 "register_operand" "=r")
2477 (match_operand:SI 3 "register_operand" "r"))]
2478 "((REGNO (operands[0]) & 3) == 0)
2479 && ((REGNO (operands[1]) & 3) == 0)
2480 && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2481 && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2486 [(set (match_operand:SI 0 "register_operand" "=r")
2487 (match_operand:SI 1 "register_operand" "r"))
2488 (set (match_operand:SI 2 "register_operand" "=r")
2489 (match_operand:SI 3 "register_operand" "r"))
2490 (set (match_operand:SI 4 "register_operand" "=r")
2491 (match_operand:SI 5 "register_operand" "r"))]
2492 "((REGNO (operands[0]) & 3) == 0)
2493 && ((REGNO (operands[1]) & 3) == 0)
2494 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2495 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2496 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2497 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2502 [(set (match_operand:SI 0 "register_operand" "=r")
2503 (match_operand:SI 1 "register_operand" "r"))
2504 (set (match_operand:SI 2 "register_operand" "=r")
2505 (match_operand:SI 3 "register_operand" "r"))]
2506 "((REGNO (operands[0]) & 1) == 0)
2507 && ((REGNO (operands[1]) & 1) == 0)
2508 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2509 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))"
2512 ; Multiple register loads.
2516 [(set (match_operand:SI 0 "register_operand" "=r")
2517 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2518 (match_operand:SI 2 "immediate_operand" "n"))))
2519 (set (match_operand:SI 3 "register_operand" "=r")
2520 (mem:SI (plus:SI (match_dup 1)
2521 (match_operand:SI 4 "immediate_operand" "n"))))
2522 (set (match_operand:SI 5 "register_operand" "=r")
2523 (mem:SI (plus:SI (match_dup 1)
2524 (match_operand:SI 6 "immediate_operand" "n"))))
2525 (set (match_operand:SI 7 "register_operand" "=r")
2526 (mem:SI (plus:SI (match_dup 1)
2527 (match_operand:SI 8 "immediate_operand" "n"))))]
2528 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2529 && (REGNO (operands[1]) != REGNO (operands[0]))
2530 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2531 && (REGNO (operands[1]) != REGNO (operands[3]))
2532 && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2533 && (REGNO (operands[1]) != REGNO (operands[5]))
2534 && (REGNO (operands[0]) + 3 == REGNO (operands[7]))
2535 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2536 && (INTVAL (operands[2]) + 8 == INTVAL (operands[6]))
2537 && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))"
2542 [(set (match_operand:DF 0 "register_operand" "=d")
2543 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
2544 (match_operand:SI 2 "immediate_operand" "n"))))
2545 (set (match_operand:DF 3 "register_operand" "=d")
2546 (mem:DF (plus:SI (match_dup 1)
2547 (match_operand:SI 4 "immediate_operand" "n"))))]
2548 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2549 && (REGNO (operands[1]) != REGNO (operands[0]))
2550 && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2551 && (REGNO (operands[1]) != REGNO (operands[3]))
2552 && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2557 [(set (match_operand:DI 0 "register_operand" "=d")
2558 (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d")
2559 (match_operand:SI 2 "immediate_operand" "n"))))
2560 (set (match_operand:DI 3 "register_operand" "=d")
2561 (mem:DI (plus:SI (match_dup 1)
2562 (match_operand:SI 4 "immediate_operand" "n"))))]
2563 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2564 && (REGNO (operands[1]) != REGNO (operands[0]))
2565 && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2566 && (REGNO (operands[1]) != REGNO (operands[3]))
2567 && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2572 [(set (match_operand:SI 0 "register_operand" "=d")
2573 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2574 (set (match_operand:SI 2 "register_operand" "=d")
2575 (mem:SI (plus:SI (match_dup 1)
2576 (match_operand:SI 3 "immediate_operand" "n"))))
2577 (set (match_operand:SI 4 "register_operand" "=d")
2578 (mem:SI (plus:SI (match_dup 1)
2579 (match_operand:SI 5 "immediate_operand" "n"))))
2580 (set (match_operand:SI 6 "register_operand" "=d")
2581 (mem:SI (plus:SI (match_dup 1)
2582 (match_operand:SI 7 "immediate_operand" "n"))))]
2583 "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2584 && (REGNO (operands[1]) != REGNO (operands[0]))
2585 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2586 && (REGNO (operands[1]) != REGNO (operands[2]))
2587 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2588 && (REGNO (operands[1]) != REGNO (operands[4]))
2589 && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2590 && (INTVAL (operands[3]) == 4)
2591 && (INTVAL (operands[5]) == 8)
2592 && (INTVAL (operands[7]) == 12))"
2597 [(set (match_operand:SI 0 "register_operand" "=d")
2598 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2599 (match_operand:SI 2 "immediate_operand" "n"))))
2600 (set (match_operand:SI 3 "register_operand" "=d")
2601 (mem:SI (plus:SI (match_dup 1)
2602 (match_operand:SI 4 "immediate_operand" "n"))))
2603 (set (match_operand:SI 5 "register_operand" "=d")
2604 (mem:SI (plus:SI (match_dup 1)
2605 (match_operand:SI 6 "immediate_operand" "n"))))]
2606 "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2607 && (REGNO (operands[1]) != REGNO (operands[0]))
2608 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2609 && (REGNO (operands[1]) != REGNO (operands[3]))
2610 && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2611 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2612 && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))"
2617 [(set (match_operand:SI 0 "register_operand" "=d")
2618 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2619 (set (match_operand:SI 2 "register_operand" "=d")
2620 (mem:SI (plus:SI (match_dup 1)
2621 (match_operand:SI 3 "immediate_operand" "n"))))
2622 (set (match_operand:SI 4 "register_operand" "=d")
2623 (mem:SI (plus:SI (match_dup 1)
2624 (match_operand:SI 5 "immediate_operand" "n"))))]
2625 "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2626 && (REGNO (operands[1]) != REGNO (operands[0]))
2627 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2628 && (REGNO (operands[1]) != REGNO (operands[2]))
2629 && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2630 && (INTVAL (operands[3]) == 4)
2631 && (INTVAL (operands[5]) == 8))"
2636 [(set (match_operand:SI 0 "register_operand" "=d")
2637 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2638 (match_operand:SI 2 "immediate_operand" "n"))))
2639 (set (match_operand:SI 3 "register_operand" "=d")
2640 (mem:SI (plus:SI (match_dup 1)
2641 (match_operand:SI 4 "immediate_operand" "n"))))]
2642 "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0)
2643 && (REGNO (operands[1]) != REGNO (operands[0]))
2644 && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2645 && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))"
2650 [(set (match_operand:SI 0 "register_operand" "=d")
2651 (mem:SI (match_operand:SI 1 "register_operand" "d")))
2652 (set (match_operand:SI 2 "register_operand" "=d")
2653 (mem:SI (plus:SI (match_dup 1)
2654 (match_operand:SI 3 "immediate_operand" "n"))))]
2655 "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0)
2656 && (REGNO (operands[1]) != REGNO (operands[0]))
2657 && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2658 && (INTVAL (operands[3]) == 4))"
2661 ; Multiple register stores.
2665 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2666 (match_operand:SI 1 "immediate_operand" "n")))
2667 (match_operand:SI 2 "register_operand" "d"))
2668 (set (mem:SI (plus:SI (match_dup 0)
2669 (match_operand:SI 3 "immediate_operand" "n")))
2670 (match_operand:SI 4 "register_operand" "d"))
2671 (set (mem:SI (plus:SI (match_dup 0)
2672 (match_operand:SI 5 "immediate_operand" "n")))
2673 (match_operand:SI 6 "register_operand" "d"))
2674 (set (mem:SI (plus:SI (match_dup 0)
2675 (match_operand:SI 7 "immediate_operand" "n")))
2676 (match_operand:SI 8 "register_operand" "d"))]
2677 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2678 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2679 && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2680 && (REGNO (operands[2]) + 3 == REGNO (operands[8]))
2681 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2682 && (INTVAL (operands[1]) + 8 == INTVAL (operands[5]))
2683 && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))"
2688 [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d")
2689 (match_operand:SI 1 "immediate_operand" "n")))
2690 (match_operand:DF 2 "register_operand" "d"))
2691 (set (mem:DF (plus:SI (match_dup 0)
2692 (match_operand:SI 3 "immediate_operand" "n")))
2693 (match_operand:DF 4 "register_operand" "d"))]
2694 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2695 && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2696 && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2701 [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d")
2702 (match_operand:SI 1 "immediate_operand" "n")))
2703 (match_operand:DI 2 "register_operand" "d"))
2704 (set (mem:DI (plus:SI (match_dup 0)
2705 (match_operand:SI 3 "immediate_operand" "n")))
2706 (match_operand:DI 4 "register_operand" "d"))]
2707 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2708 && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2709 && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2714 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2715 (match_operand:SI 1 "register_operand" "d"))
2716 (set (mem:SI (plus:SI (match_dup 0)
2717 (match_operand:SI 2 "immediate_operand" "n")))
2718 (match_operand:SI 3 "register_operand" "d"))
2719 (set (mem:SI (plus:SI (match_dup 0)
2720 (match_operand:SI 4 "immediate_operand" "n")))
2721 (match_operand:SI 5 "register_operand" "d"))
2722 (set (mem:SI (plus:SI (match_dup 0)
2723 (match_operand:SI 6 "immediate_operand" "n")))
2724 (match_operand:SI 7 "register_operand" "d"))]
2725 "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2726 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2727 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2728 && (REGNO (operands[1]) + 3 == REGNO (operands[7]))
2729 && (INTVAL (operands[2]) == 4)
2730 && (INTVAL (operands[4]) == 8)
2731 && (INTVAL (operands[6]) == 12))"
2736 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2737 (match_operand:SI 1 "immediate_operand" "n")))
2738 (match_operand:SI 2 "register_operand" "d"))
2739 (set (mem:SI (plus:SI (match_dup 0)
2740 (match_operand:SI 3 "immediate_operand" "n")))
2741 (match_operand:SI 4 "register_operand" "d"))
2742 (set (mem:SI (plus:SI (match_dup 0)
2743 (match_operand:SI 5 "immediate_operand" "n")))
2744 (match_operand:SI 6 "register_operand" "d"))]
2745 "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2746 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2747 && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2748 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2749 && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))"
2754 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2755 (match_operand:SI 1 "register_operand" "d"))
2756 (set (mem:SI (plus:SI (match_dup 0)
2757 (match_operand:SI 2 "immediate_operand" "n")))
2758 (match_operand:SI 3 "register_operand" "d"))
2759 (set (mem:SI (plus:SI (match_dup 0)
2760 (match_operand:SI 4 "immediate_operand" "n")))
2761 (match_operand:SI 5 "register_operand" "d"))]
2762 "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2763 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2764 && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2765 && (INTVAL (operands[2]) == 4)
2766 && (INTVAL (operands[4]) == 8))"
2771 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2772 (match_operand:SI 1 "immediate_operand" "n")))
2773 (match_operand:SI 2 "register_operand" "d"))
2774 (set (mem:SI (plus:SI (match_dup 0)
2775 (match_operand:SI 3 "immediate_operand" "n")))
2776 (match_operand:SI 4 "register_operand" "d"))]
2777 "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0)
2778 && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2779 && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))"
2784 [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2785 (match_operand:SI 1 "register_operand" "d"))
2786 (set (mem:SI (plus:SI (match_dup 0)
2787 (match_operand:SI 2 "immediate_operand" "n")))
2788 (match_operand:SI 3 "register_operand" "d"))]
2789 "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0)
2790 && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2791 && (INTVAL (operands[2]) == 4))"