1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files may include this one and then override
26 many of the definitions that relate to assembler syntax. */
28 #define MULTILIB_DEFAULTS { "mnumerics" }
30 /* Names to predefine in the preprocessor for this target machine. */
31 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu=i960 -Amachine=i960"
33 /* Name to predefine in the preprocessor for processor variations.
34 -mic* options make characters signed by default. */
35 #define CPP_SPEC "%{mic*:-D__i960 -fsigned-char\
36 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
37 %{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
39 %{msa:-D__i960SA}%{msb:-D__i960SB}\
41 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
43 %{msoft-float:-D_SOFT_FLOAT}\
44 %{mka:-D__i960KA__ -D__i960_KA__}\
45 %{mkb:-D__i960KB__ -D__i960_KB__}\
46 %{msa:-D__i960SA__ -D__i960_SA__}\
47 %{msb:-D__i960SB__ -D__i960_SB__}\
48 %{mmc:-D__i960MC__ -D__i960_MC__}\
49 %{mca:-D__i960CA__ -D__i960_CA__}\
50 %{mcc:-D__i960CC__ -D__i960_CC__}\
51 %{mcf:-D__i960CF__ -D__i960_CF__}\
52 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
53 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}\
54 %{mlong-double-64:-D__LONG_DOUBLE_64__}"
56 /* Specs for the compiler, to handle processor variations.
57 If the user gives an explicit -gstabs or -gcoff option, then do not
58 try to add an implicit one, as this will fail.
59 -mic* options make characters signed by default. */
61 "%{mic*:-fsigned-char}\
62 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
63 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
64 %{mcoff:%{g*:-gcoff}}\
65 %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
67 /* Specs for the assembler, to handle processor variations.
68 For compatibility with Intel's gnu960 tool chain, pass -A options to
71 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
72 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
73 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
74 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
75 %{mlink-relax:-linkrelax}"
77 /* Specs for the linker, to handle processor variations.
78 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
81 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
82 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
83 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
84 %{mbout:-Fbout}%{mcoff:-Fcoff}\
85 %{mlink-relax:-relax}"
87 /* Specs for the libraries to link with, to handle processor variations.
88 Compatible with Intel's gnu960 tool chain. */
89 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
90 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
92 /* Defining the macro shows we can debug even without a frame pointer.
93 Actually, we can debug without FP. But defining the macro results in
94 that -O means FP elimination. Addressing through sp requires
95 negative offset and more one word addressing in the most cases
96 (offsets except for 0-4095 require one more word). Therefore we've
97 not defined the macro. */
98 /*#define CAN_DEBUG_WITHOUT_FP*/
100 /* Do leaf procedure and tail call optimizations for -O2 and higher. */
101 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
105 target_flags |= TARGET_FLAG_LEAFPROC; \
106 target_flags |= TARGET_FLAG_TAILCALL; \
110 /* Print subsidiary information on the compiler version in use. */
111 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
113 /* Generate DBX debugging information. */
114 #define DBX_DEBUGGING_INFO 1
116 /* Generate SDB style debugging information. */
117 #define SDB_DEBUGGING_INFO 1
118 #define EXTENDED_SDB_BASIC_TYPES
120 /* Generate DBX_DEBUGGING_INFO by default. */
121 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
123 /* Redefine this to print in hex. No value adjustment is necessary
125 #define PUT_SDB_TYPE(A) \
126 fprintf (asm_out_file, "\t.type\t0x%x;", A)
128 /* Handle pragmas for compatibility with Intel's compilers. */
130 extern int i960_maxbitalignment;
131 extern int i960_last_maxbitalignment;
133 #define REGISTER_TARGET_PRAGMAS() do { \
134 c_register_pragma (0, "align", i960_pr_align); \
135 c_register_pragma (0, "noalign", i960_pr_noalign); \
138 /* Run-time compilation parameters selecting different hardware subsets. */
140 /* 960 architecture with floating-point. */
141 #define TARGET_FLAG_NUMERICS 0x01
142 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
144 /* 960 architecture with memory management. */
145 /* ??? Not used currently. */
146 #define TARGET_FLAG_PROTECTED 0x02
147 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
149 /* The following three are mainly used to provide a little sanity checking
150 against the -mARCH flags given. The Jx series, for the purposes of
151 gcc, is a Kx with a data cache. */
153 /* Nonzero if we should generate code for the KA and similar processors.
154 No FPU, no microcode instructions. */
155 #define TARGET_FLAG_K_SERIES 0x04
156 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
158 /* Nonzero if we should generate code for the MC processor.
159 Not really different from KB for our purposes. */
160 #define TARGET_FLAG_MC 0x08
161 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
163 /* Nonzero if we should generate code for the CA processor.
164 Enables different optimization strategies. */
165 #define TARGET_FLAG_C_SERIES 0x10
166 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
168 /* Nonzero if we should generate leaf-procedures when we find them.
169 You may not want to do this because leaf-proc entries are
170 slower when not entered via BAL - this would be true when
171 a linker not supporting the optimization is used. */
172 #define TARGET_FLAG_LEAFPROC 0x20
173 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
175 /* Nonzero if we should perform tail-call optimizations when we find them.
176 You may not want to do this because the detection of cases where
177 this is not valid is not totally complete. */
178 #define TARGET_FLAG_TAILCALL 0x40
179 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
181 /* Nonzero if use of a complex addressing mode is a win on this implementation.
182 Complex addressing modes are probably not worthwhile on the K-series,
183 but they definitely are on the C-series. */
184 #define TARGET_FLAG_COMPLEX_ADDR 0x80
185 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
187 /* Align code to 8 byte boundaries for faster fetching. */
188 #define TARGET_FLAG_CODE_ALIGN 0x100
189 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
191 /* Append branch prediction suffixes to branch opcodes. */
192 /* ??? Not used currently. */
193 #define TARGET_FLAG_BRANCH_PREDICT 0x200
194 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
196 /* Forces prototype and return promotions. */
197 /* ??? This does not work. */
198 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
199 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
201 /* For compatibility with iC960 v3.0. */
202 #define TARGET_FLAG_IC_COMPAT3_0 0x800
203 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
205 /* For compatibility with iC960 v2.0. */
206 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
207 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
209 /* If no unaligned accesses are to be permitted. */
210 #define TARGET_FLAG_STRICT_ALIGN 0x2000
211 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
213 /* For compatibility with iC960 assembler. */
214 #define TARGET_FLAG_ASM_COMPAT 0x4000
215 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
217 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
218 alignment rules. Also, turns on STRICT_ALIGNMENT. */
219 #define TARGET_FLAG_OLD_ALIGN 0x8000
220 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
222 /* Nonzero if long doubles are to be 64 bits. Useful for soft-float targets
223 if 80 bit long double support is missing. */
224 #define TARGET_FLAG_LONG_DOUBLE_64 0x10000
225 #define TARGET_LONG_DOUBLE_64 (target_flags & TARGET_FLAG_LONG_DOUBLE_64)
227 extern int target_flags;
229 /* Macro to define tables used to set the flags.
230 This is a list in braces of pairs in braces,
231 each pair being { "NAME", VALUE }
232 where VALUE is the bits to set or minus the bits to clear.
233 An empty string NAME is used to identify the default VALUE. */
235 /* ??? Not all ten of these architecture variations actually exist, but I
236 am not sure which are real and which aren't. */
238 #define TARGET_SWITCHES \
239 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
240 N_("Generate SA code")}, \
241 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
242 TARGET_FLAG_COMPLEX_ADDR), \
243 N_("Generate SB code")}, \
244 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
245 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
246 N_("Generate SC code")}, */ \
247 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
248 N_("Generate KA code")}, \
249 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
250 TARGET_FLAG_COMPLEX_ADDR), \
251 N_("Generate KB code")}, \
252 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
253 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
254 N_("Generate KC code")}, */ \
255 {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
256 N_("Generate JA code")}, \
257 {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
258 N_("Generate JD code")}, \
259 {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
260 TARGET_FLAG_COMPLEX_ADDR), \
261 N_("Generate JF code")}, \
262 {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
263 N_("generate RP code")}, \
264 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
265 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
266 N_("Generate MC code")}, \
267 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
268 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
269 N_("Generate CA code")}, \
270 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
271 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
272 N_("Generate CB code")}, \
273 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
274 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
275 TARGET_FLAG_CODE_ALIGN), \
276 N_("Generate CC code")}, */ \
277 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
278 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
279 N_("Generate CF code")}, \
280 {"numerics", (TARGET_FLAG_NUMERICS), \
281 N_("Use hardware floating point instructions")}, \
282 {"soft-float", -(TARGET_FLAG_NUMERICS), \
283 N_("Use software floating point")}, \
284 {"leaf-procedures", TARGET_FLAG_LEAFPROC, \
285 N_("Use alternate leaf function entries")}, \
286 {"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
287 N_("Do not use alternate leaf function entries")}, \
288 {"tail-call", TARGET_FLAG_TAILCALL, \
289 N_("Perform tail call optimization")}, \
290 {"no-tail-call", -(TARGET_FLAG_TAILCALL), \
291 N_("Do not perform tail call optimization")}, \
292 {"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
293 N_("Use complex addressing modes")}, \
294 {"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
295 N_("Do not use complex addressing modes")}, \
296 {"code-align", TARGET_FLAG_CODE_ALIGN, \
297 N_("Align code to 8 byte boundary")}, \
298 {"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
299 N_("Do not align code to 8 byte boundary")}, \
300 /* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
301 N_("Force use of prototypes")}, \
302 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
303 N_("Do not force use of prototypes")}, */ \
304 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
305 N_("Enable compatibility with iC960 v2.0")}, \
306 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
307 N_("Enable compatibility with iC960 v2.0")}, \
308 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
309 N_("Enable compatibility with iC960 v3.0")}, \
310 {"asm-compat", TARGET_FLAG_ASM_COMPAT, \
311 N_("Enable compatibility with ic960 assembler")}, \
312 {"intel-asm", TARGET_FLAG_ASM_COMPAT, \
313 N_("Enable compatibility with ic960 assembler")}, \
314 {"strict-align", TARGET_FLAG_STRICT_ALIGN, \
315 N_("Do not permit unaligned accesses")}, \
316 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
317 N_("Permit unaligned accesses")}, \
318 {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
319 N_("Layout types like Intel's v1.3 gcc")}, \
320 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
321 N_("Do not layout types like Intel's v1.3 gcc")}, \
322 {"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
323 N_("Use 64 bit long doubles")}, \
325 N_("Enable linker relaxation")}, \
326 {"no-link-relax", 0, \
327 N_("Do not enable linker relaxation")}, \
329 { "", TARGET_DEFAULT, \
332 /* This are meant to be redefined in the host dependent files */
333 #define SUBTARGET_SWITCHES
335 /* Override conflicting target switch options.
336 Doesn't actually detect if more than one -mARCH option is given, but
337 does handle the case of two blatantly conflicting -mARCH options. */
338 #define OVERRIDE_OPTIONS i960_initialize ()
340 /* Don't enable anything by default. The user is expected to supply a -mARCH
341 option. If none is given, then -mka is added by CC1_SPEC. */
342 #define TARGET_DEFAULT 0
344 /* Target machine storage layout. */
346 /* Define this if most significant bit is lowest numbered
347 in instructions that operate on numbered bit-fields. */
348 #define BITS_BIG_ENDIAN 0
350 /* Define this if most significant byte of a word is the lowest numbered.
351 The i960 case be either big endian or little endian. We only support
352 little endian, which is the most common. */
353 #define BYTES_BIG_ENDIAN 0
355 /* Define this if most significant word of a multiword number is lowest
357 #define WORDS_BIG_ENDIAN 0
359 /* Bitfields cannot cross word boundaries. */
360 #define BITFIELD_NBYTES_LIMITED 1
362 /* Width of a word, in units (bytes). */
363 #define UNITS_PER_WORD 4
365 /* Width in bits of a long double. */
366 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 128)
367 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
369 /* Define this to set long double type size to use in libgcc2.c, which can
370 not depend on target_flags. */
371 #if defined(__LONG_DOUBLE_64__)
372 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
374 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
377 /* Allocation boundary (in *bits*) for storing pointers in memory. */
378 #define POINTER_BOUNDARY 32
380 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
381 #define PARM_BOUNDARY 32
383 /* Boundary (in *bits*) on which stack pointer should be aligned. */
384 #define STACK_BOUNDARY 128
386 /* Allocation boundary (in *bits*) for the code of a function. */
387 #define FUNCTION_BOUNDARY 128
389 /* Alignment of field after `int : 0' in a structure. */
390 #define EMPTY_FIELD_BOUNDARY 32
392 /* This makes zero-length anonymous fields lay the next field
393 at a word boundary. It also makes the whole struct have
394 at least word alignment if there are any bitfields at all. */
395 #define PCC_BITFIELD_TYPE_MATTERS 1
397 /* Every structure's size must be a multiple of this. */
398 #define STRUCTURE_SIZE_BOUNDARY 8
400 /* No data type wants to be aligned rounder than this.
401 Extended precision floats gets 4-word alignment. */
402 #define BIGGEST_ALIGNMENT 128
404 /* Define this if move instructions will actually fail to work
405 when given unaligned data.
406 80960 will work even with unaligned data, but it is slow. */
407 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
409 /* Specify alignment for string literals (which might be higher than the
410 base type's minimal alignment requirement. This allows strings to be
411 aligned on word boundaries, and optimizes calls to the str* and mem*
412 library functions. */
413 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
414 (TREE_CODE (EXP) == STRING_CST \
415 && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
416 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
419 /* Macros to determine size of aggregates (structures and unions
420 in C). Normally, these may be defined to simply return the maximum
421 alignment and simple rounded-up size, but on some machines (like
422 the i960), the total size of a structure is based on a non-trivial
425 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
426 i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE)
428 /* Standard register usage. */
430 /* Number of actual hardware registers.
431 The hardware registers are assigned numbers for the compiler
432 from 0 to just below FIRST_PSEUDO_REGISTER.
433 All registers that the compiler knows about must be given numbers,
434 even those that are not normally considered general registers.
436 Registers 0-15 are the global registers (g0-g15).
437 Registers 16-31 are the local registers (r0-r15).
438 Register 32-35 are the fp registers (fp0-fp3).
439 Register 36 is the condition code register.
440 Register 37 is unused. */
442 #define FIRST_PSEUDO_REGISTER 38
444 /* 1 for registers that have pervasive standard uses and are not available
445 for the register allocator. On 80960, this includes the frame pointer
446 (g15), the previous FP (r0), the stack pointer (r1), the return
447 instruction pointer (r2), and the argument pointer (g14). */
448 #define FIXED_REGISTERS \
449 {0, 0, 0, 0, 0, 0, 0, 0, \
450 0, 0, 0, 0, 0, 0, 1, 1, \
451 1, 1, 1, 0, 0, 0, 0, 0, \
452 0, 0, 0, 0, 0, 0, 0, 0, \
455 /* 1 for registers not available across function calls.
456 These must include the FIXED_REGISTERS and also any
457 registers that can be used without being saved.
458 The latter must include the registers where values are returned
459 and the register where structure-value addresses are passed.
460 Aside from that, you can include as many other registers as you like. */
462 /* On the 80960, note that:
463 g0..g3 are used for return values,
464 g0..g7 may always be used for parameters,
465 g8..g11 may be used for parameters, but are preserved if they aren't,
466 g12 is the static chain if needed, otherwise is preserved
467 g13 is the struct return ptr if used, or temp, but may be trashed,
468 g14 is the leaf return ptr or the arg block ptr otherwise zero,
469 must be reset to zero before returning if it was used,
470 g15 is the frame pointer,
471 r0 is the previous FP,
472 r1 is the stack pointer,
473 r2 is the return instruction pointer,
474 r3-r15 are always available,
475 r3 is clobbered by calls in functions that use the arg pointer
476 r4-r11 may be clobbered by the mcount call when profiling
477 r4-r15 if otherwise unused may be used for preserving global registers
478 fp0..fp3 are never available. */
479 #define CALL_USED_REGISTERS \
480 {1, 1, 1, 1, 1, 1, 1, 1, \
481 0, 0, 0, 0, 0, 1, 1, 1, \
482 1, 1, 1, 0, 0, 0, 0, 0, \
483 0, 0, 0, 0, 0, 0, 0, 0, \
486 /* If no fp unit, make all of the fp registers fixed so that they can't
488 #define CONDITIONAL_REGISTER_USAGE \
489 if (! TARGET_NUMERICS) { \
490 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
493 /* Return number of consecutive hard regs needed starting at reg REGNO
494 to hold something of mode MODE.
495 This is ordinarily the length in words of a value of mode MODE
496 but can be less for certain modes in special long registers.
498 On 80960, ordinary registers hold 32 bits worth, but can be ganged
499 together to hold double or extended precision floating point numbers,
500 and the floating point registers hold any size floating point number */
501 #define HARD_REGNO_NREGS(REGNO, MODE) \
503 ? (((MODE) == VOIDmode) \
504 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
505 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
507 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
508 On 80960, the cpu registers can hold any mode but the float registers
509 can only hold SFmode, DFmode, or TFmode. */
510 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
512 /* Value is 1 if it is a good idea to tie two pseudo registers
513 when one has mode MODE1 and one has mode MODE2.
514 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
515 for any hard reg, then this must be 0 for correct output. */
517 #define MODES_TIEABLE_P(MODE1, MODE2) \
518 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
520 /* Specify the registers used for certain standard purposes.
521 The values of these macros are register numbers. */
523 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
524 /* #define PC_REGNUM */
526 /* Register to use for pushing function arguments. */
527 #define STACK_POINTER_REGNUM 17
529 /* Actual top-of-stack address is same as
530 the contents of the stack pointer register. */
531 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
533 /* Base register for access to local variables of the function. */
534 #define FRAME_POINTER_REGNUM 15
536 /* Value should be nonzero if functions must have frame pointers.
537 Zero means the frame pointer need not be set up (and parms
538 may be accessed via the stack pointer) in functions that seem suitable.
539 This is computed in `reload', in reload1.c. */
540 /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
541 fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
542 caused this to fail. */
543 /* ??? Must check current_function_has_nonlocal_goto, otherwise frame pointer
544 elimination messes up nonlocal goto sequences. I think this works for other
545 targets because they use indirect jumps for the return which disables fp
547 #define FRAME_POINTER_REQUIRED \
548 (! leaf_function_p () || current_function_has_nonlocal_goto)
550 /* Definitions for register eliminations.
552 This is an array of structures. Each structure initializes one pair
553 of eliminable registers. The "from" register number is given first,
554 followed by "to". Eliminations of the same "from" register are listed
555 in order of preference.. */
557 #define ELIMINABLE_REGS {{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
559 /* Given FROM and TO register numbers, say whether this elimination is allowed.
560 Frame pointer elimination is automatically handled. */
561 #define CAN_ELIMINATE(FROM, TO) 1
563 /* Define the offset between two registers, one to be eliminated, and
564 the other its replacement, at the start of a routine.
566 Since the stack grows upward on the i960, this must be a negative number.
567 This includes the 64 byte hardware register save area and the size of
570 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
571 do { (OFFSET) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
573 /* Base register for access to arguments of the function. */
574 #define ARG_POINTER_REGNUM 14
576 /* Register in which static-chain is passed to a function.
577 On i960, we use g12. We can't use any local register, because we need
578 a register that can be set before a call or before a jump. */
579 #define STATIC_CHAIN_REGNUM 12
581 /* Functions which return large structures get the address
582 to place the wanted value at in g13. */
584 #define STRUCT_VALUE_REGNUM 13
586 /* The order in which to allocate registers. */
588 #define REG_ALLOC_ORDER \
589 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
590 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
591 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
592 11, 12, /* g11, g12 */ \
593 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
594 /* We can't actually allocate these. */ \
595 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
597 /* Define the classes of registers for register constraints in the
598 machine description. Also define ranges of constants.
600 One of the classes must always be named ALL_REGS and include all hard regs.
601 If there is more than one class, another class must be named NO_REGS
602 and contain no registers.
604 The name GENERAL_REGS must be the name of a class (or an alias for
605 another name such as ALL_REGS). This is the class of registers
606 that is allowed by "g" or "r" in a register constraint.
607 Also, registers outside this class are allocated only when
608 instructions express preferences for them.
610 The classes must be numbered in nondecreasing order; that is,
611 a larger-numbered class must never be contained completely
612 in a smaller-numbered class.
614 For any two classes, it is very desirable that there be another
615 class that represents their union. */
617 /* The 80960 has four kinds of registers, global, local, floating point,
618 and condition code. The cc register is never allocated, so no class
619 needs to be defined for it. */
621 enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
622 FP_REGS, ALL_REGS, LIM_REG_CLASSES };
624 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
626 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
628 #define N_REG_CLASSES (int) LIM_REG_CLASSES
630 /* Give names of register classes as strings for dump file. */
632 #define REG_CLASS_NAMES \
633 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
634 "FP_REGS", "ALL_REGS" }
636 /* Define which registers fit in which classes.
637 This is an initializer for a vector of HARD_REG_SET
638 of length N_REG_CLASSES. */
640 #define REG_CLASS_CONTENTS \
641 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
643 /* The same information, inverted:
644 Return the class number of the smallest class containing
645 reg number REGNO. This could be a conditional expression
646 or could index an array. */
648 #define REGNO_REG_CLASS(REGNO) \
649 ((REGNO) < 16 ? GLOBAL_REGS \
650 : (REGNO) < 32 ? LOCAL_REGS \
651 : (REGNO) < 36 ? FP_REGS \
654 /* The class value for index registers, and the one for base regs.
655 There is currently no difference between base and index registers on the
656 i960, but this distinction may one day be useful. */
657 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
658 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
660 /* Get reg_class from a letter such as appears in the machine description.
661 'f' is a floating point register (fp0..fp3)
662 'l' is a local register (r0-r15)
663 'b' is a global register (g0-g15)
664 'd' is any local or global register
665 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
666 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
667 the same thing, since 'r' may include the fp registers. */
668 #define REG_CLASS_FROM_LETTER(C) \
669 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
670 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
672 /* The letters I, J, K, L and M in a register constraint string
673 can be used to stand for particular ranges of immediate operands.
674 This macro defines what the ranges are.
675 C is the letter, and VALUE is a constant value.
676 Return 1 if VALUE is in the range specified by C.
679 'I' is used for literal values 0..31
683 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
684 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
685 : (C) == 'J' ? ((VALUE) == 0) \
686 : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \
687 : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \
690 /* Similar, but for floating constants, and defining letters G and H.
691 Here VALUE is the CONST_DOUBLE rtx itself.
692 For the 80960, G is 0.0 and H is 1.0. */
694 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
695 ((TARGET_NUMERICS) && \
696 (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
697 || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
699 /* Given an rtx X being reloaded into a reg required to be
700 in class CLASS, return the class of reg to actually use.
701 In general this is just CLASS; but on some machines
702 in some cases it is preferable to use a more restrictive class. */
704 /* On 960, can't load constant into floating-point reg except
707 Any hard reg is ok as a src operand of a reload insn. */
709 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
710 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
712 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
713 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
714 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
716 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
718 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
719 secondary_reload_class (CLASS, MODE, IN)
721 /* Return the maximum number of consecutive registers
722 needed to represent mode MODE in a register of class CLASS. */
723 /* On 80960, this is the size of MODE in words,
724 except in the FP regs, where a single reg is always enough. */
725 #define CLASS_MAX_NREGS(CLASS, MODE) \
726 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
728 /* Stack layout; function entry, exit and calling. */
730 /* Define this if pushing a word on the stack
731 makes the stack pointer a smaller address. */
732 /* #define STACK_GROWS_DOWNWARD */
734 /* Define this if the nominal address of the stack frame
735 is at the high-address end of the local variables;
736 that is, each additional local variable allocated
737 goes at a more negative offset in the frame. */
738 /* #define FRAME_GROWS_DOWNWARD */
740 /* Offset within stack frame to start allocating local variables at.
741 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
742 first local allocated. Otherwise, it is the offset to the BEGINNING
743 of the first local allocated.
745 The i960 has a 64 byte register save area, plus possibly some extra
746 bytes allocated for varargs functions. */
747 #define STARTING_FRAME_OFFSET 64
749 /* If we generate an insn to push BYTES bytes,
750 this says how many the stack pointer really advances by.
751 On 80960, don't define this because there are no push insns. */
752 /* #define PUSH_ROUNDING(BYTES) BYTES */
754 /* Offset of first parameter from the argument pointer register value. */
755 #define FIRST_PARM_OFFSET(FNDECL) 0
757 /* When a parameter is passed in a register, no stack space is
758 allocated for it. However, when args are passed in the
759 stack, space is allocated for every register parameter. */
760 #define MAYBE_REG_PARM_STACK_SPACE 48
761 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
762 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
763 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
764 #define OUTGOING_REG_PARM_STACK_SPACE
766 /* Keep the stack pointer constant throughout the function. */
767 #define ACCUMULATE_OUTGOING_ARGS 1
769 /* Value is 1 if returning from a function call automatically
770 pops the arguments described by the number-of-args field in the call.
771 FUNDECL is the declaration node of the function (as a tree),
772 FUNTYPE is the data type of the function (as a tree),
773 or for a library call it is an identifier node for the subroutine name. */
775 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
777 /* Define how to find the value returned by a library function
778 assuming the value has mode MODE. */
780 #define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), 0)
782 /* 1 if N is a possible register number for a function value
783 as seen by the caller.
784 On 80960, returns are in g0..g3 */
786 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
788 /* 1 if N is a possible register number for function argument passing.
789 On 80960, parameters are passed in g0..g11 */
791 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
793 /* Perform any needed actions needed for a function that is receiving a
794 variable number of arguments.
798 MODE and TYPE are the mode and type of the current parameter.
800 PRETEND_SIZE is a variable that should be set to the amount of stack
801 that must be pushed by the prolog to pretend that our caller pushed
804 Normally, this macro will push all remaining incoming registers on the
805 stack and set PRETEND_SIZE to the length of the registers pushed. */
807 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
808 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
810 /* Define the `__builtin_va_list' type for the ABI. */
811 #define BUILD_VA_LIST_TYPE(VALIST) \
812 (VALIST) = i960_build_va_list ()
814 /* Implement `va_start' for varargs and stdarg. */
815 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
816 i960_va_start (valist, nextarg)
818 /* Implement `va_arg'. */
819 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
820 i960_va_arg (valist, type)
822 /* Define a data type for recording info about an argument list
823 during the scan of that argument list. This data type should
824 hold all necessary information about the function itself
825 and about the args processed so far, enough to enable macros
826 such as FUNCTION_ARG to determine where the next arg should go.
828 On 80960, this is two integers, which count the number of register
829 parameters and the number of stack parameters seen so far. */
831 struct cum_args { int ca_nregparms; int ca_nstackparms; };
833 #define CUMULATIVE_ARGS struct cum_args
835 /* Define the number of registers that can hold parameters.
836 This macro is used only in macro definitions below and/or i960.c. */
837 #define NPARM_REGS 12
839 /* Define how to round to the next parameter boundary.
840 This macro is used only in macro definitions below and/or i960.c. */
841 #define ROUND_PARM(X, MULTIPLE_OF) \
842 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
844 /* Initialize a variable CUM of type CUMULATIVE_ARGS
845 for a call to a function whose data type is FNTYPE.
846 For a library call, FNTYPE is 0.
848 On 80960, the offset always starts at 0; the first parm reg is g0. */
850 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
851 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
853 /* Update the data in CUM to advance over an argument
854 of mode MODE and data type TYPE.
855 CUM should be advanced to align with the data type accessed and
856 also the size of that data type in # of regs.
857 (TYPE is null for libcalls where that information may not be available.) */
859 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
860 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
862 /* Indicate the alignment boundary for an argument of the specified mode and
864 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
866 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
868 : TYPE_ALIGN (TYPE)) \
869 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
871 : GET_MODE_ALIGNMENT (MODE)))
873 /* Determine where to put an argument to a function.
874 Value is zero to push the argument on the stack,
875 or a hard register in which to store the argument.
877 MODE is the argument's machine mode.
878 TYPE is the data type of the argument (as a tree).
879 This is null for libcalls where that information may
881 CUM is a variable of type CUMULATIVE_ARGS which gives info about
882 the preceding args and about the function being called.
883 NAMED is nonzero if this argument is a named parameter
884 (otherwise it is an extra parameter matching an ellipsis). */
886 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
887 i960_function_arg(&CUM, MODE, TYPE, NAMED)
889 /* Define how to find the value returned by a function.
890 VALTYPE is the data type of the value (as a tree).
891 If the precise function being called is known, FUNC is its FUNCTION_DECL;
892 otherwise, FUNC is 0. */
894 #define FUNCTION_VALUE(TYPE, FUNC) \
895 gen_rtx_REG (TYPE_MODE (TYPE), 0)
897 /* Force aggregates and objects larger than 16 bytes to be returned in memory,
898 since we only have 4 registers available for return values. */
900 #define RETURN_IN_MEMORY(TYPE) \
901 (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
903 /* Don't default to pcc-struct-return, because we have already specified
904 exactly how to return structures in the RETURN_IN_MEMORY macro. */
905 #define DEFAULT_PCC_STRUCT_RETURN 0
907 /* For an arg passed partly in registers and partly in memory,
908 this is the number of registers used.
909 This never happens on 80960. */
911 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
913 /* Output the label for a function definition.
914 This handles leaf functions and a few other things for the i960. */
916 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
917 i960_function_name_declare (FILE, NAME, DECL)
919 /* Output assembler code to FILE to increment profiler label # LABELNO
920 for profiling a function entry. */
922 #define FUNCTION_PROFILER(FILE, LABELNO) \
923 output_function_profiler ((FILE), (LABELNO));
925 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
926 the stack pointer does not matter. The value is tested only in
927 functions that have frame pointers.
928 No definition is equivalent to always zero. */
930 #define EXIT_IGNORE_STACK 1
932 /* Addressing modes, and classification of registers for them. */
934 /* Macros to check register numbers against specific register classes. */
936 /* These assume that REGNO is a hard or pseudo reg number.
937 They give nonzero only if REGNO is a hard reg of the suitable class
938 or a pseudo reg currently allocated to a suitable hard reg.
939 Since they use reg_renumber, they are safe only once reg_renumber
940 has been allocated, which happens in local-alloc.c. */
942 #define REGNO_OK_FOR_INDEX_P(REGNO) \
943 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
944 #define REGNO_OK_FOR_BASE_P(REGNO) \
945 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
946 #define REGNO_OK_FOR_FP_P(REGNO) \
947 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
949 /* Now macros that check whether X is a register and also,
950 strictly, whether it is in a specified class.
952 These macros are specific to the 960, and may be used only
953 in code for printing assembler insns and in conditions for
954 define_optimization. */
956 /* 1 if X is an fp register. */
958 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
960 /* Maximum number of registers that can appear in a valid memory address. */
961 #define MAX_REGS_PER_ADDRESS 2
963 #define CONSTANT_ADDRESS_P(X) \
964 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
965 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
966 || GET_CODE (X) == HIGH)
968 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
969 is a legitimate general operand.
970 It is given that X satisfies CONSTANT_P.
972 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
974 ??? This probably should be defined to 1. */
976 #define LEGITIMATE_CONSTANT_P(X) \
977 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
979 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
980 and check its validity for a certain class.
981 We have two alternate definitions for each of them.
982 The usual definition accepts all pseudo regs; the other rejects
983 them unless they have been allocated suitable hard regs.
984 The symbol REG_OK_STRICT causes the latter definition to be used.
986 Most source files want to accept pseudo regs in the hope that
987 they will get allocated to the class that the insn wants them to be in.
988 Source files for reload pass need to be strict.
989 After reload, it makes no difference, since pseudo regs have
990 been eliminated by then. */
992 #ifndef REG_OK_STRICT
994 /* Nonzero if X is a hard reg that can be used as an index
995 or if it is a pseudo reg. */
996 #define REG_OK_FOR_INDEX_P(X) \
997 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
998 /* Nonzero if X is a hard reg that can be used as a base reg
999 or if it is a pseudo reg. */
1000 #define REG_OK_FOR_BASE_P(X) \
1001 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1003 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1004 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1008 /* Nonzero if X is a hard reg that can be used as an index. */
1009 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1010 /* Nonzero if X is a hard reg that can be used as a base reg. */
1011 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1015 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1016 that is a valid memory address for an instruction.
1017 The MODE argument is the machine mode for the MEM expression
1018 that wants to use this address.
1020 On 80960, legitimate addresses are:
1022 disp (12 or 32 bit) ld foo,r0
1023 base + index ld (g0)[g1*1],r0
1024 base + displ ld 0xf00(g0),r0
1025 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1026 index*scale + base ld (g0)[g1*4],r0
1027 index*scale + displ ld 0xf00[g1*4],r0
1028 index*scale ld [g1*4],r0
1029 index + base + displ ld 0xf00(g0)[g1*1],r0
1031 In each case, scale can be 1, 2, 4, 8, or 16. */
1033 /* Returns 1 if the scale factor of an index term is valid. */
1034 #define SCALE_TERM_P(X) \
1035 (GET_CODE (X) == CONST_INT \
1036 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1037 || INTVAL(X) == 8 || INTVAL (X) == 16))
1040 #ifdef REG_OK_STRICT
1041 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1042 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1044 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1045 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1048 /* Try machine-dependent ways of modifying an illegitimate address
1049 to be legitimate. If we find one, return the new, valid address.
1050 This macro is used in only one place: `memory_address' in explow.c.
1052 OLDX is the address as it was before break_out_memory_refs was called.
1053 In some cases it is useful to look at this to decide what needs to be done.
1055 MODE and WIN are passed so that this macro can use
1056 GO_IF_LEGITIMATE_ADDRESS.
1058 It is always safe for this macro to do nothing. It exists to recognize
1059 opportunities to optimize the output. */
1061 /* On 80960, convert non-canonical addresses to canonical form. */
1063 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1064 { rtx orig_x = (X); \
1065 (X) = legitimize_address (X, OLDX, MODE); \
1066 if ((X) != orig_x && memory_address_p (MODE, X)) \
1069 /* Go to LABEL if ADDR (a legitimate address expression)
1070 has an effect that depends on the machine mode it is used for.
1071 On the 960 this is never true. */
1073 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1075 /* Specify the machine mode that this machine uses
1076 for the index in the tablejump instruction. */
1077 #define CASE_VECTOR_MODE SImode
1079 /* Define as C expression which evaluates to nonzero if the tablejump
1080 instruction expects the table to contain offsets from the address of the
1082 Do not define this if the table should contain absolute addresses. */
1083 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1085 /* Define this as 1 if `char' should by default be signed; else as 0. */
1086 #define DEFAULT_SIGNED_CHAR 0
1088 /* Max number of bytes we can move from memory to memory
1089 in one reasonably fast instruction. */
1092 /* Define if operations between registers always perform the operation
1093 on the full register even if a narrower mode is specified. */
1094 #define WORD_REGISTER_OPERATIONS
1096 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1097 will either zero-extend or sign-extend. The value of this macro should
1098 be the code that says which one of the two operations is implicitly
1099 done, NIL if none. */
1100 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1102 /* Nonzero if access to memory by bytes is no faster than for words.
1103 Value changed to 1 after reports of poor bit-field code with g++.
1104 Indications are that code is usually as good, sometimes better. */
1106 #define SLOW_BYTE_ACCESS 1
1108 /* We assume that the store-condition-codes instructions store 0 for false
1109 and some other value for true. This is the value stored for true. */
1111 #define STORE_FLAG_VALUE 1
1113 /* Define this to be nonzero if shift instructions ignore all but the low-order
1115 #define SHIFT_COUNT_TRUNCATED 0
1117 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1118 is done just by pretending it is already truncated. */
1119 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1121 /* Specify the machine mode that pointers have.
1122 After generation of rtl, the compiler makes no further distinction
1123 between pointers and any other objects of this machine mode. */
1124 #define Pmode SImode
1126 /* Specify the widest mode that BLKmode objects can be promoted to */
1127 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1129 /* These global variables are used to pass information between
1130 cc setter and cc user at insn emit time. */
1132 extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
1134 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1135 return the mode to be used for the comparison. For floating-point, CCFPmode
1136 should be used. CC_NOOVmode should be used when the first operand is a
1137 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1139 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1141 /* A function address in a call instruction is a byte address
1142 (for indexing purposes) so give the MEM rtx a byte's mode. */
1143 #define FUNCTION_MODE SImode
1145 /* Define this if addresses of constant functions
1146 shouldn't be put through pseudo regs where they can be cse'd.
1147 Desirable on machines where ordinary constants are expensive
1148 but a CALL with constant address is cheap. */
1149 #define NO_FUNCTION_CSE
1151 /* Use memcpy, etc. instead of bcopy. */
1154 #define TARGET_MEM_FUNCTIONS 1
1157 /* Control the assembler format that we output. */
1159 /* Output at beginning of assembler file. */
1161 #define ASM_FILE_START(file)
1163 /* Output to assembler file text saying following lines
1164 may contain character constants, extra white space, comments, etc. */
1166 #define ASM_APP_ON ""
1168 /* Output to assembler file text saying following lines
1169 no longer contain unusual constructs. */
1171 #define ASM_APP_OFF ""
1173 /* Output before read-only data. */
1175 #define TEXT_SECTION_ASM_OP "\t.text"
1177 /* Output before writable data. */
1179 #define DATA_SECTION_ASM_OP "\t.data"
1181 /* How to refer to registers in assembler output.
1182 This sequence is indexed by compiler's hard-register-number (see above). */
1184 #define REGISTER_NAMES { \
1185 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1186 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1187 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1188 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1189 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1191 /* How to renumber registers for dbx and gdb.
1192 In the 960 encoding, g0..g15 are registers 16..31. */
1194 #define DBX_REGISTER_NUMBER(REGNO) \
1195 (((REGNO) < 16) ? (REGNO) + 16 \
1196 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1198 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1199 #define DBX_CONTIN_LENGTH 1500
1201 /* This is how to output a note to DBX telling it the line number
1202 to which the following sequence of instructions corresponds. */
1204 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1205 { if (write_symbols == SDB_DEBUG) { \
1206 fprintf ((FILE), "\t.ln %d\n", \
1207 (sdb_begin_function_line \
1208 ? (LINE) - sdb_begin_function_line : 1)); \
1209 } else if (write_symbols == DBX_DEBUG) { \
1210 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1213 /* Globalizing directive for a label. */
1214 #define GLOBAL_ASM_OP "\t.globl "
1216 /* The prefix to add to user-visible assembler symbols. */
1218 #define USER_LABEL_PREFIX "_"
1220 /* This is how to store into the string LABEL
1221 the symbol_ref name of an internal numbered label where
1222 PREFIX is the class of label and NUM is the number within the class.
1223 This is suitable for output with `assemble_name'. */
1225 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1226 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1228 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1229 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1231 /* This is how to output an insn to pop a register from the stack.
1232 It need not be very fast code. */
1234 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1235 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1237 /* This is how to output an element of a case-vector that is absolute. */
1239 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1240 fprintf (FILE, "\t.word L%d\n", VALUE)
1242 /* This is how to output an element of a case-vector that is relative. */
1244 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1245 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1247 /* This is how to output an assembler line that says to advance the
1248 location counter to a multiple of 2**LOG bytes. */
1250 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1251 fprintf (FILE, "\t.align %d\n", (LOG))
1253 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1254 fprintf (FILE, "\t.space %d\n", (int)(SIZE))
1256 /* This says how to output an assembler line
1257 to define a global common symbol. */
1259 /* For common objects, output unpadded size... gld960 & lnk960 both
1260 have code to align each common object at link time. Also, if size
1261 is 0, treat this as a declaration, not a definition - i.e.,
1262 do nothing at all. */
1264 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1265 { if ((SIZE) != 0) \
1267 fputs (".globl ", (FILE)), \
1268 assemble_name ((FILE), (NAME)), \
1269 fputs ("\n.comm ", (FILE)), \
1270 assemble_name ((FILE), (NAME)), \
1271 fprintf ((FILE), ",%d\n", (int)(SIZE)); \
1275 /* This says how to output an assembler line to define a local common symbol.
1276 Output unpadded size, with request to linker to align as requested.
1277 0 size should not be possible here. */
1279 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1280 ( fputs (".bss\t", (FILE)), \
1281 assemble_name ((FILE), (NAME)), \
1282 fprintf ((FILE), ",%d,%d\n", (int)(SIZE), \
1283 (floor_log2 ((ALIGN) / BITS_PER_UNIT))))
1285 /* A C statement (sans semicolon) to output to the stdio stream
1286 FILE the assembler definition of uninitialized global DECL named
1287 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1288 Try to use asm_output_aligned_bss to implement this macro. */
1290 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1292 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1295 /* Output text for an #ident directive. */
1296 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1298 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1300 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
1303 /* Print operand X (an rtx) in assembler syntax to file FILE.
1304 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1305 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1307 #define PRINT_OPERAND(FILE, X, CODE) \
1308 i960_print_operand (FILE, X, CODE);
1310 /* Print a memory address as an operand to reference that memory location. */
1312 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1313 i960_print_operand_addr (FILE, ADDR)
1315 /* Determine which codes are valid without a following integer. These must
1316 not be alphabetic (the characters are chosen so that
1317 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
1320 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '+')
1322 /* Output assembler code for a block containing the constant parts
1323 of a trampoline, leaving space for the variable parts. */
1325 /* On the i960, the trampoline contains three instructions:
1326 ldconst _function, r4
1327 ldconst static addr, g12
1330 #define TRAMPOLINE_TEMPLATE(FILE) \
1332 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8C203000)); \
1333 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \
1334 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x8CE03000)); \
1335 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x00000000)); \
1336 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x84212000)); \
1339 /* Length in units of the trampoline for entering a nested function. */
1341 #define TRAMPOLINE_SIZE 20
1343 /* Emit RTL insns to initialize the variable parts of a trampoline.
1344 FNADDR is an RTX for the address of the function's pure code.
1345 CXT is an RTX for the static chain value for the function. */
1347 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1349 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 4)), FNADDR); \
1350 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \
1353 /* Generate RTL to flush the register windows so as to make arbitrary frames
1355 #define SETUP_FRAME_ADDRESSES() \
1356 emit_insn (gen_flush_register_windows ())
1358 #define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx
1361 /* Promote char and short arguments to ints, when want compatibility with
1362 the iC960 compilers. */
1364 /* ??? In order for this to work, all users would need to be changed
1365 to test the value of the macro at run time. */
1366 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1367 /* ??? This does not exist. */
1368 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1371 /* Instruction type definitions. Used to alternate instructions types for
1372 better performance on the C series chips. */
1374 enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
1376 /* Holds the insn type of the last insn output to the assembly file. */
1378 extern enum insn_types i960_last_insn_type;
1380 /* Parse opcodes, and set the insn last insn type based on them. */
1382 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1384 /* Table listing what rtl codes each predicate in i960.c will accept. */
1386 #define PREDICATE_CODES \
1387 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1388 LABEL_REF, SUBREG, REG, MEM}}, \
1389 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1390 {"logic_operand", {SUBREG, REG, CONST_INT}}, \
1391 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1392 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1393 {"literal", {CONST_INT}}, \
1394 {"fp_literal_one", {CONST_DOUBLE}}, \
1395 {"fp_literal_double", {CONST_DOUBLE}}, \
1396 {"fp_literal", {CONST_DOUBLE}}, \
1397 {"signed_literal", {CONST_INT}}, \
1398 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1399 {"eq_or_neq", {EQ, NE}}, \
1400 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1401 CONST_DOUBLE, CONST}}, \
1402 {"power2_operand", {CONST_INT}}, \
1403 {"cmplpower2_operand", {CONST_INT}},
1405 /* Defined in reload.c, and used in insn-recog.c. */
1407 extern int rtx_equal_function_value_matters;