1 /* Definitions of target machine for GNU compiler, for Intel 80960
2 Copyright (C) 1992, 1993, 1995, 1996, 1998 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files may include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Names to predefine in the preprocessor for this target machine. */
28 #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
30 /* Name to predefine in the preprocessor for processor variations. */
31 #define CPP_SPEC "%{mic*:-D__i960\
32 %{mka:-D__i960KA}%{mkb:-D__i960KB}\
33 %{mja:-D__i960JA}%{mjd:-D__i960JD}%{mjf:-D__i960JF}\
35 %{msa:-D__i960SA}%{msb:-D__i960SB}\
37 %{mca:-D__i960CA}%{mcc:-D__i960CC}\
39 %{mka:-D__i960KA__ -D__i960_KA__}\
40 %{mkb:-D__i960KB__ -D__i960_KB__}\
41 %{msa:-D__i960SA__ -D__i960_SA__}\
42 %{msb:-D__i960SB__ -D__i960_SB__}\
43 %{mmc:-D__i960MC__ -D__i960_MC__}\
44 %{mca:-D__i960CA__ -D__i960_CA__}\
45 %{mcc:-D__i960CC__ -D__i960_CC__}\
46 %{mcf:-D__i960CF__ -D__i960_CF__}\
47 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
48 %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
50 /* -mic* options make characters signed by default. */
51 /* Use #if rather than ?: because MIPS C compiler rejects ?: in
53 #if DEFAULT_SIGNED_CHAR
54 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
56 #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
59 /* Specs for the compiler, to handle processor variations.
60 If the user gives an explicit -gstabs or -gcoff option, then do not
61 try to add an implicit one, as this will fail. */
63 "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-mka}}}}}}}}}}}}\
64 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
65 %{mcoff:%{g*:-gcoff}}\
66 %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"
68 /* Specs for the assembler, to handle processor variations.
69 For compatibility with Intel's gnu960 tool chain, pass -A options to
72 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
73 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
74 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
75 %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:%{!mja:%{!mjd:%{!mjf:%{!mrp:-AKB}}}}}}}}}}}}\
76 %{mlink-relax:-linkrelax}"
78 /* Specs for the linker, to handle processor variations.
79 For compatibility with Intel's gnu960 tool chain, pass -F and -A options
82 "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
83 %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
84 %{mja:-AJX}%{mjd:-AJX}%{mjf:-AJX}%{mrp:-AJX}\
85 %{mbout:-Fbout}%{mcoff:-Fcoff}\
86 %{mlink-relax:-relax}"
88 /* Specs for the libraries to link with, to handle processor variations.
89 Compatible with Intel's gnu960 tool chain. */
90 #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
91 %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
93 /* Show we can debug even without a frame pointer. */
94 #define CAN_DEBUG_WITHOUT_FP
96 /* Do leaf procedure and tail call optimizations for -O2 and higher. */
97 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
101 target_flags |= TARGET_FLAG_LEAFPROC; \
102 target_flags |= TARGET_FLAG_TAILCALL; \
106 /* Print subsidiary information on the compiler version in use. */
107 #define TARGET_VERSION fprintf (stderr," (intel 80960)");
109 /* Generate DBX debugging information. */
110 #define DBX_DEBUGGING_INFO
112 /* Generate SDB style debugging information. */
113 #define SDB_DEBUGGING_INFO
114 #define EXTENDED_SDB_BASIC_TYPES
116 /* Generate DBX_DEBUGGING_INFO by default. */
117 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
119 /* Redefine this to print in hex. No value adjustment is necessary
121 #define PUT_SDB_TYPE(A) \
122 fprintf (asm_out_file, "\t.type\t0x%x;", A)
124 /* Handle pragmas for compatibility with Intel's compilers. */
125 #define HANDLE_PRAGMA(GET, UNGET, NAME) process_pragma (GET, UNGET, NAME)
126 extern int process_pragma ();
128 /* Run-time compilation parameters selecting different hardware subsets. */
130 /* 960 architecture with floating-point. */
131 #define TARGET_FLAG_NUMERICS 0x01
132 #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
134 /* 960 architecture with memory management. */
135 /* ??? Not used currently. */
136 #define TARGET_FLAG_PROTECTED 0x02
137 #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
139 /* The following three are mainly used to provide a little sanity checking
140 against the -mARCH flags given. The Jx series, for the purposes of
141 gcc, is a Kx with a data cache. */
143 /* Nonzero if we should generate code for the KA and similar processors.
144 No FPU, no microcode instructions. */
145 #define TARGET_FLAG_K_SERIES 0x04
146 #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
148 /* Nonzero if we should generate code for the MC processor.
149 Not really different from KB for our purposes. */
150 #define TARGET_FLAG_MC 0x08
151 #define TARGET_MC (target_flags & TARGET_FLAG_MC)
153 /* Nonzero if we should generate code for the CA processor.
154 Enables different optimization strategies. */
155 #define TARGET_FLAG_C_SERIES 0x10
156 #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
158 /* Nonzero if we should generate leaf-procedures when we find them.
159 You may not want to do this because leaf-proc entries are
160 slower when not entered via BAL - this would be true when
161 a linker not supporting the optimization is used. */
162 #define TARGET_FLAG_LEAFPROC 0x20
163 #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
165 /* Nonzero if we should perform tail-call optimizations when we find them.
166 You may not want to do this because the detection of cases where
167 this is not valid is not totally complete. */
168 #define TARGET_FLAG_TAILCALL 0x40
169 #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
171 /* Nonzero if use of a complex addressing mode is a win on this implementation.
172 Complex addressing modes are probably not worthwhile on the K-series,
173 but they definitely are on the C-series. */
174 #define TARGET_FLAG_COMPLEX_ADDR 0x80
175 #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
177 /* Align code to 8 byte boundaries for faster fetching. */
178 #define TARGET_FLAG_CODE_ALIGN 0x100
179 #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
181 /* Append branch prediction suffixes to branch opcodes. */
182 /* ??? Not used currently. */
183 #define TARGET_FLAG_BRANCH_PREDICT 0x200
184 #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
186 /* Forces prototype and return promotions. */
187 /* ??? This does not work. */
188 #define TARGET_FLAG_CLEAN_LINKAGE 0x400
189 #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
191 /* For compatibility with iC960 v3.0. */
192 #define TARGET_FLAG_IC_COMPAT3_0 0x800
193 #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
195 /* For compatibility with iC960 v2.0. */
196 #define TARGET_FLAG_IC_COMPAT2_0 0x1000
197 #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
199 /* If no unaligned accesses are to be permitted. */
200 #define TARGET_FLAG_STRICT_ALIGN 0x2000
201 #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
203 /* For compatibility with iC960 assembler. */
204 #define TARGET_FLAG_ASM_COMPAT 0x4000
205 #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
207 /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
208 alignment rules. Also, turns on STRICT_ALIGNMENT. */
209 #define TARGET_FLAG_OLD_ALIGN 0x8000
210 #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
212 extern int target_flags;
214 /* Macro to define tables used to set the flags.
215 This is a list in braces of pairs in braces,
216 each pair being { "NAME", VALUE }
217 where VALUE is the bits to set or minus the bits to clear.
218 An empty string NAME is used to identify the default VALUE. */
220 /* ??? Not all ten of these architecture variations actually exist, but I
221 am not sure which are real and which aren't. */
223 #define TARGET_SWITCHES \
224 { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
225 {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
226 TARGET_FLAG_COMPLEX_ADDR)},\
227 /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
228 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
229 {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
230 {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
231 TARGET_FLAG_COMPLEX_ADDR)},\
232 /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
233 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
234 {"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
235 {"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
236 {"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
237 TARGET_FLAG_COMPLEX_ADDR)},\
238 {"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
239 {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
240 TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
241 {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
242 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
243 /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
244 TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
245 {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
246 TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
247 TARGET_FLAG_CODE_ALIGN)}, */ \
248 {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
249 TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
250 {"numerics", (TARGET_FLAG_NUMERICS)}, \
251 {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
252 {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
253 {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
254 {"tail-call",TARGET_FLAG_TAILCALL}, \
255 {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
256 {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
257 {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
258 {"code-align",TARGET_FLAG_CODE_ALIGN}, \
259 {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
260 {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
261 {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
262 {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
263 {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
264 {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
265 {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
266 {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
267 {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
268 {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
269 {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
270 {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
272 {"no-link-relax", 0}, \
274 { "", TARGET_DEFAULT}}
276 /* This are meant to be redefined in the host dependent files */
277 #define SUBTARGET_SWITCHES
279 /* Override conflicting target switch options.
280 Doesn't actually detect if more than one -mARCH option is given, but
281 does handle the case of two blatantly conflicting -mARCH options. */
282 #define OVERRIDE_OPTIONS \
284 if (TARGET_K_SERIES && TARGET_C_SERIES) \
286 warning ("conflicting architectures defined - using C series", 0); \
287 target_flags &= ~TARGET_FLAG_K_SERIES; \
289 if (TARGET_K_SERIES && TARGET_MC) \
291 warning ("conflicting architectures defined - using K series", 0); \
292 target_flags &= ~TARGET_FLAG_MC; \
294 if (TARGET_C_SERIES && TARGET_MC) \
296 warning ("conflicting architectures defined - using C series", 0);\
297 target_flags &= ~TARGET_FLAG_MC; \
299 if (TARGET_IC_COMPAT3_0) \
301 flag_short_enums = 1; \
302 flag_signed_char = 1; \
303 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
304 if (TARGET_IC_COMPAT2_0) \
306 warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
307 target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
310 if (TARGET_IC_COMPAT2_0) \
312 flag_signed_char = 1; \
313 target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
315 i960_initialize (); \
318 /* Don't enable anything by default. The user is expected to supply a -mARCH
319 option. If none is given, then -mka is added by CC1_SPEC. */
320 #define TARGET_DEFAULT 0
322 /* Target machine storage layout. */
324 /* Define for cross-compilation from a host with a different float format
325 or endianness, as well as to support 80 bit long doubles on the i960. */
326 #define REAL_ARITHMETIC
328 /* Define this if most significant bit is lowest numbered
329 in instructions that operate on numbered bit-fields. */
330 #define BITS_BIG_ENDIAN 0
332 /* Define this if most significant byte of a word is the lowest numbered.
333 The i960 case be either big endian or little endian. We only support
334 little endian, which is the most common. */
335 #define BYTES_BIG_ENDIAN 0
337 /* Define this if most significant word of a multiword number is lowest
339 #define WORDS_BIG_ENDIAN 0
341 /* Number of bits in an addressable storage unit. */
342 #define BITS_PER_UNIT 8
344 /* Bitfields cannot cross word boundaries. */
345 #define BITFIELD_NBYTES_LIMITED 1
347 /* Width in bits of a "word", which is the contents of a machine register.
348 Note that this is not necessarily the width of data type `int';
349 if using 16-bit ints on a 68000, this would still be 32.
350 But on a machine with 16-bit registers, this would be 16. */
351 #define BITS_PER_WORD 32
353 /* Width of a word, in units (bytes). */
354 #define UNITS_PER_WORD 4
356 /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
357 #define POINTER_SIZE 32
359 /* Width in bits of a long double. Identical to double for now. */
360 #define LONG_DOUBLE_TYPE_SIZE 64
362 /* Allocation boundary (in *bits*) for storing pointers in memory. */
363 #define POINTER_BOUNDARY 32
365 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
366 #define PARM_BOUNDARY 32
368 /* Boundary (in *bits*) on which stack pointer should be aligned. */
369 #define STACK_BOUNDARY 128
371 /* Allocation boundary (in *bits*) for the code of a function. */
372 #define FUNCTION_BOUNDARY 128
374 /* Alignment of field after `int : 0' in a structure. */
375 #define EMPTY_FIELD_BOUNDARY 32
377 /* This makes zero-length anonymous fields lay the next field
378 at a word boundary. It also makes the whole struct have
379 at least word alignment if there are any bitfields at all. */
380 #define PCC_BITFIELD_TYPE_MATTERS 1
382 /* Every structure's size must be a multiple of this. */
383 #define STRUCTURE_SIZE_BOUNDARY 8
385 /* No data type wants to be aligned rounder than this.
386 Extended precision floats gets 4-word alignment. */
387 #define BIGGEST_ALIGNMENT 128
389 /* Define this if move instructions will actually fail to work
390 when given unaligned data.
391 80960 will work even with unaligned data, but it is slow. */
392 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
394 /* Specify alignment for string literals (which might be higher than the
395 base type's minimal alignment requirement. This allows strings to be
396 aligned on word boundaries, and optimizes calls to the str* and mem*
397 library functions. */
398 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
399 (TREE_CODE (EXP) == STRING_CST \
400 && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
401 ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
404 /* Make XFmode floating point quantities be 128 bit aligned. */
405 #define DATA_ALIGNMENT(TYPE, ALIGN) \
406 (TREE_CODE (TYPE) == ARRAY_TYPE \
407 && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \
408 && (ALIGN) < 128 ? 128 : (ALIGN))
410 /* Macros to determine size of aggregates (structures and unions
411 in C). Normally, these may be defined to simply return the maximum
412 alignment and simple rounded-up size, but on some machines (like
413 the i960), the total size of a structure is based on a non-trivial
416 #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
417 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
418 ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \
419 : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \
420 && TREE_CODE (TYPE) == RECORD_TYPE) \
421 ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \
422 : MAX ((COMPUTED), (SPECIFIED))))
424 #define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \
425 ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \
426 ? build_int_2 (128, 0) : round_up (COMPUTED, SPECIFIED))
428 /* Standard register usage. */
430 /* Number of actual hardware registers.
431 The hardware registers are assigned numbers for the compiler
432 from 0 to just below FIRST_PSEUDO_REGISTER.
433 All registers that the compiler knows about must be given numbers,
434 even those that are not normally considered general registers.
436 Registers 0-15 are the global registers (g0-g15).
437 Registers 16-31 are the local registers (r0-r15).
438 Register 32-35 are the fp registers (fp0-fp3).
439 Register 36 is the condition code register.
440 Register 37 is unused. */
442 #define FIRST_PSEUDO_REGISTER 38
444 /* 1 for registers that have pervasive standard uses and are not available
445 for the register allocator. On 80960, this includes the frame pointer
446 (g15), the previous FP (r0), the stack pointer (r1), the return
447 instruction pointer (r2), and the argument pointer (g14). */
448 #define FIXED_REGISTERS \
449 {0, 0, 0, 0, 0, 0, 0, 0, \
450 0, 0, 0, 0, 0, 0, 1, 1, \
451 1, 1, 1, 0, 0, 0, 0, 0, \
452 0, 0, 0, 0, 0, 0, 0, 0, \
455 /* 1 for registers not available across function calls.
456 These must include the FIXED_REGISTERS and also any
457 registers that can be used without being saved.
458 The latter must include the registers where values are returned
459 and the register where structure-value addresses are passed.
460 Aside from that, you can include as many other registers as you like. */
462 /* On the 80960, note that:
463 g0..g3 are used for return values,
464 g0..g7 may always be used for parameters,
465 g8..g11 may be used for parameters, but are preserved if they aren't,
466 g12 is always preserved, but otherwise unused,
467 g13 is the struct return ptr if used, or temp, but may be trashed,
468 g14 is the leaf return ptr or the arg block ptr otherwise zero,
469 must be reset to zero before returning if it was used,
470 g15 is the frame pointer,
471 r0 is the previous FP,
472 r1 is the stack pointer,
473 r2 is the return instruction pointer,
474 r3-r15 are always available,
475 r3 is clobbered by calls in functions that use the arg pointer
476 r4-r11 may be clobbered by the mcount call when profiling
477 r4-r15 if otherwise unused may be used for preserving global registers
478 fp0..fp3 are never available. */
479 #define CALL_USED_REGISTERS \
480 {1, 1, 1, 1, 1, 1, 1, 1, \
481 0, 0, 0, 0, 0, 1, 1, 1, \
482 1, 1, 1, 0, 0, 0, 0, 0, \
483 0, 0, 0, 0, 0, 0, 0, 0, \
486 /* If no fp unit, make all of the fp registers fixed so that they can't
488 #define CONDITIONAL_REGISTER_USAGE \
489 if (! TARGET_NUMERICS) { \
490 fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
493 /* Return number of consecutive hard regs needed starting at reg REGNO
494 to hold something of mode MODE.
495 This is ordinarily the length in words of a value of mode MODE
496 but can be less for certain modes in special long registers.
498 On 80960, ordinary registers hold 32 bits worth, but can be ganged
499 together to hold double or extended precision floating point numbers,
500 and the floating point registers hold any size floating point number */
501 #define HARD_REGNO_NREGS(REGNO, MODE) \
503 ? (((MODE) == VOIDmode) \
504 ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
505 : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
507 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
508 On 80960, the cpu registers can hold any mode but the float registers
509 can only hold SFmode, DFmode, or XFmode. */
510 extern int hard_regno_mode_ok ();
511 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE))
513 /* Value is 1 if it is a good idea to tie two pseudo registers
514 when one has mode MODE1 and one has mode MODE2.
515 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
516 for any hard reg, then this must be 0 for correct output. */
518 #define MODES_TIEABLE_P(MODE1, MODE2) \
519 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
521 /* Specify the registers used for certain standard purposes.
522 The values of these macros are register numbers. */
524 /* 80960 pc isn't overloaded on a register that the compiler knows about. */
525 /* #define PC_REGNUM */
527 /* Register to use for pushing function arguments. */
528 #define STACK_POINTER_REGNUM 17
530 /* Actual top-of-stack address is same as
531 the contents of the stack pointer register. */
532 #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
534 /* Base register for access to local variables of the function. */
535 #define FRAME_POINTER_REGNUM 15
537 /* Value should be nonzero if functions must have frame pointers.
538 Zero means the frame pointer need not be set up (and parms
539 may be accessed via the stack pointer) in functions that seem suitable.
540 This is computed in `reload', in reload1.c. */
541 /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
542 fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
543 caused this to fail. */
544 #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
546 /* C statement to store the difference between the frame pointer
547 and the stack pointer values immediately after the function prologue.
549 Since the stack grows upward on the i960, this must be a negative number.
550 This includes the 64 byte hardware register save area and the size of
553 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
554 do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
556 /* Base register for access to arguments of the function. */
557 #define ARG_POINTER_REGNUM 14
559 /* Register in which static-chain is passed to a function.
560 On i960, we use r3. */
561 #define STATIC_CHAIN_REGNUM 19
563 /* Functions which return large structures get the address
564 to place the wanted value at in g13. */
566 #define STRUCT_VALUE_REGNUM 13
568 /* The order in which to allocate registers. */
570 #define REG_ALLOC_ORDER \
571 { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
572 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
573 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
574 11, 12, /* g11, g12 */ \
575 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
576 /* We can't actually allocate these. */ \
577 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
579 /* Define the classes of registers for register constraints in the
580 machine description. Also define ranges of constants.
582 One of the classes must always be named ALL_REGS and include all hard regs.
583 If there is more than one class, another class must be named NO_REGS
584 and contain no registers.
586 The name GENERAL_REGS must be the name of a class (or an alias for
587 another name such as ALL_REGS). This is the class of registers
588 that is allowed by "g" or "r" in a register constraint.
589 Also, registers outside this class are allocated only when
590 instructions express preferences for them.
592 The classes must be numbered in nondecreasing order; that is,
593 a larger-numbered class must never be contained completely
594 in a smaller-numbered class.
596 For any two classes, it is very desirable that there be another
597 class that represents their union. */
599 /* The 80960 has four kinds of registers, global, local, floating point,
600 and condition code. The cc register is never allocated, so no class
601 needs to be defined for it. */
603 enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
604 FP_REGS, ALL_REGS, LIM_REG_CLASSES };
606 /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
608 #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
610 #define N_REG_CLASSES (int) LIM_REG_CLASSES
612 /* Give names of register classes as strings for dump file. */
614 #define REG_CLASS_NAMES \
615 { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
616 "FP_REGS", "ALL_REGS" }
618 /* Define which registers fit in which classes.
619 This is an initializer for a vector of HARD_REG_SET
620 of length N_REG_CLASSES. */
622 #define REG_CLASS_CONTENTS \
623 { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
625 /* The same information, inverted:
626 Return the class number of the smallest class containing
627 reg number REGNO. This could be a conditional expression
628 or could index an array. */
630 #define REGNO_REG_CLASS(REGNO) \
631 ((REGNO) < 16 ? GLOBAL_REGS \
632 : (REGNO) < 32 ? LOCAL_REGS \
633 : (REGNO) < 36 ? FP_REGS \
636 /* The class value for index registers, and the one for base regs.
637 There is currently no difference between base and index registers on the
638 i960, but this distinction may one day be useful. */
639 #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
640 #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
642 /* Get reg_class from a letter such as appears in the machine description.
643 'f' is a floating point register (fp0..fp3)
644 'l' is a local register (r0-r15)
645 'b' is a global register (g0-g15)
646 'd' is any local or global register
647 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
648 /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
649 the same thing, since 'r' may include the fp registers. */
650 #define REG_CLASS_FROM_LETTER(C) \
651 (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
652 (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
654 /* The letters I, J, K, L and M in a register constraint string
655 can be used to stand for particular ranges of immediate operands.
656 This macro defines what the ranges are.
657 C is the letter, and VALUE is a constant value.
658 Return 1 if VALUE is in the range specified by C.
661 'I' is used for literal values 0..31
665 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
666 ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
667 : (C) == 'J' ? ((VALUE) == 0) \
668 : (C) == 'K' ? ((VALUE) >= -31 && (VALUE) <= 0) \
669 : (C) == 'M' ? ((VALUE) >= -32 && (VALUE) <= 0) \
672 /* Similar, but for floating constants, and defining letters G and H.
673 Here VALUE is the CONST_DOUBLE rtx itself.
674 For the 80960, G is 0.0 and H is 1.0. */
676 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
677 ((TARGET_NUMERICS) && \
678 (((C) == 'G' && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
679 || ((C) == 'H' && ((VALUE) == CONST1_RTX (GET_MODE (VALUE))))))
681 /* Given an rtx X being reloaded into a reg required to be
682 in class CLASS, return the class of reg to actually use.
683 In general this is just CLASS; but on some machines
684 in some cases it is preferable to use a more restrictive class. */
686 /* On 960, can't load constant into floating-point reg except
689 Any hard reg is ok as a src operand of a reload insn. */
691 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
692 (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
694 : ((CLASS) == FP_REGS && CONSTANT_P (X) \
695 && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
696 && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
698 : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
700 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
701 secondary_reload_class (CLASS, MODE, IN)
703 /* Return the maximum number of consecutive registers
704 needed to represent mode MODE in a register of class CLASS. */
705 /* On 80960, this is the size of MODE in words,
706 except in the FP regs, where a single reg is always enough. */
707 #define CLASS_MAX_NREGS(CLASS, MODE) \
708 ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
710 /* Stack layout; function entry, exit and calling. */
712 /* Define this if pushing a word on the stack
713 makes the stack pointer a smaller address. */
714 /* #define STACK_GROWS_DOWNWARD */
716 /* Define this if the nominal address of the stack frame
717 is at the high-address end of the local variables;
718 that is, each additional local variable allocated
719 goes at a more negative offset in the frame. */
720 /* #define FRAME_GROWS_DOWNWARD */
722 /* Offset within stack frame to start allocating local variables at.
723 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
724 first local allocated. Otherwise, it is the offset to the BEGINNING
725 of the first local allocated.
727 The i960 has a 64 byte register save area, plus possibly some extra
728 bytes allocated for varargs functions. */
729 #define STARTING_FRAME_OFFSET 64
731 /* If we generate an insn to push BYTES bytes,
732 this says how many the stack pointer really advances by.
733 On 80960, don't define this because there are no push insns. */
734 /* #define PUSH_ROUNDING(BYTES) BYTES */
736 /* Offset of first parameter from the argument pointer register value. */
737 #define FIRST_PARM_OFFSET(FNDECL) 0
739 /* When a parameter is passed in a register, no stack space is
740 allocated for it. However, when args are passed in the
741 stack, space is allocated for every register parameter. */
742 #define MAYBE_REG_PARM_STACK_SPACE 48
743 #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
744 i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
745 #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
746 #define OUTGOING_REG_PARM_STACK_SPACE
748 /* Keep the stack pointer constant throughout the function. */
749 #define ACCUMULATE_OUTGOING_ARGS
751 /* Value is 1 if returning from a function call automatically
752 pops the arguments described by the number-of-args field in the call.
753 FUNDECL is the declaration node of the function (as a tree),
754 FUNTYPE is the data type of the function (as a tree),
755 or for a library call it is an identifier node for the subroutine name. */
757 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
759 /* Define how to find the value returned by a library function
760 assuming the value has mode MODE. */
762 #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
764 /* 1 if N is a possible register number for a function value
765 as seen by the caller.
766 On 80960, returns are in g0..g3 */
768 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
770 /* 1 if N is a possible register number for function argument passing.
771 On 80960, parameters are passed in g0..g11 */
773 #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
775 /* Perform any needed actions needed for a function that is receiving a
776 variable number of arguments.
780 MODE and TYPE are the mode and type of the current parameter.
782 PRETEND_SIZE is a variable that should be set to the amount of stack
783 that must be pushed by the prolog to pretend that our caller pushed
786 Normally, this macro will push all remaining incoming registers on the
787 stack and set PRETEND_SIZE to the length of the registers pushed. */
789 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
790 i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
792 /* Define a data type for recording info about an argument list
793 during the scan of that argument list. This data type should
794 hold all necessary information about the function itself
795 and about the args processed so far, enough to enable macros
796 such as FUNCTION_ARG to determine where the next arg should go.
798 On 80960, this is two integers, which count the number of register
799 parameters and the number of stack parameters seen so far. */
801 struct cum_args { int ca_nregparms; int ca_nstackparms; };
803 #define CUMULATIVE_ARGS struct cum_args
805 /* Define the number of registers that can hold parameters.
806 This macro is used only in macro definitions below and/or i960.c. */
807 #define NPARM_REGS 12
809 /* Define how to round to the next parameter boundary.
810 This macro is used only in macro definitions below and/or i960.c. */
811 #define ROUND_PARM(X, MULTIPLE_OF) \
812 ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
814 /* Initialize a variable CUM of type CUMULATIVE_ARGS
815 for a call to a function whose data type is FNTYPE.
816 For a library call, FNTYPE is 0.
818 On 80960, the offset always starts at 0; the first parm reg is g0. */
820 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
821 ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
823 /* Update the data in CUM to advance over an argument
824 of mode MODE and data type TYPE.
825 CUM should be advanced to align with the data type accessed and
826 also the size of that data type in # of regs.
827 (TYPE is null for libcalls where that information may not be available.) */
829 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
830 i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
832 /* Indicate the alignment boundary for an argument of the specified mode and
834 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
836 ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
838 : TYPE_ALIGN (TYPE)) \
839 : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
841 : GET_MODE_ALIGNMENT (MODE)))
843 /* Determine where to put an argument to a function.
844 Value is zero to push the argument on the stack,
845 or a hard register in which to store the argument.
847 MODE is the argument's machine mode.
848 TYPE is the data type of the argument (as a tree).
849 This is null for libcalls where that information may
851 CUM is a variable of type CUMULATIVE_ARGS which gives info about
852 the preceding args and about the function being called.
853 NAMED is nonzero if this argument is a named parameter
854 (otherwise it is an extra parameter matching an ellipsis). */
856 extern struct rtx_def *i960_function_arg ();
857 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
858 i960_function_arg(&CUM, MODE, TYPE, NAMED)
860 /* Define how to find the value returned by a function.
861 VALTYPE is the data type of the value (as a tree).
862 If the precise function being called is known, FUNC is its FUNCTION_DECL;
863 otherwise, FUNC is 0. */
865 #define FUNCTION_VALUE(TYPE, FUNC) \
866 gen_rtx (REG, TYPE_MODE (TYPE), 0)
868 /* Force aggregates and objects larger than 16 bytes to be returned in memory,
869 since we only have 4 registers available for return values. */
871 #define RETURN_IN_MEMORY(TYPE) \
872 (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
874 /* Don't default to pcc-struct-return, because we have already specified
875 exactly how to return structures in the RETURN_IN_MEMORY macro. */
876 #define DEFAULT_PCC_STRUCT_RETURN 0
878 /* For an arg passed partly in registers and partly in memory,
879 this is the number of registers used.
880 This never happens on 80960. */
882 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
884 /* Output the label for a function definition.
885 This handles leaf functions and a few other things for the i960. */
887 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
888 i960_function_name_declare (FILE, NAME, DECL)
890 /* This macro generates the assembly code for function entry.
891 FILE is a stdio stream to output the code to.
892 SIZE is an int: how many units of temporary storage to allocate.
893 Refer to the array `regs_ever_live' to determine which registers
894 to save; `regs_ever_live[I]' is nonzero if register number I
895 is ever used in the function. This macro is responsible for
896 knowing which registers should not be saved even if used. */
898 #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
900 /* Output assembler code to FILE to increment profiler label # LABELNO
901 for profiling a function entry. */
903 #define FUNCTION_PROFILER(FILE, LABELNO) \
904 output_function_profiler ((FILE), (LABELNO));
906 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
907 the stack pointer does not matter. The value is tested only in
908 functions that have frame pointers.
909 No definition is equivalent to always zero. */
911 #define EXIT_IGNORE_STACK 1
913 /* This macro generates the assembly code for function exit,
914 on machines that need it. If FUNCTION_EPILOGUE is not defined
915 then individual return instructions are generated for each
916 return statement. Args are same as for FUNCTION_PROLOGUE.
918 The function epilogue should not depend on the current stack pointer!
919 It should use the frame pointer only. This is mandatory because
920 of alloca; we also take advantage of it to omit stack adjustments
923 #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
925 /* Addressing modes, and classification of registers for them. */
927 /* #define HAVE_POST_INCREMENT 0 */
928 /* #define HAVE_POST_DECREMENT 0 */
930 /* #define HAVE_PRE_DECREMENT 0 */
931 /* #define HAVE_PRE_INCREMENT 0 */
933 /* Macros to check register numbers against specific register classes. */
935 /* These assume that REGNO is a hard or pseudo reg number.
936 They give nonzero only if REGNO is a hard reg of the suitable class
937 or a pseudo reg currently allocated to a suitable hard reg.
938 Since they use reg_renumber, they are safe only once reg_renumber
939 has been allocated, which happens in local-alloc.c. */
941 #define REGNO_OK_FOR_INDEX_P(REGNO) \
942 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
943 #define REGNO_OK_FOR_BASE_P(REGNO) \
944 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
945 #define REGNO_OK_FOR_FP_P(REGNO) \
946 ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
948 /* Now macros that check whether X is a register and also,
949 strictly, whether it is in a specified class.
951 These macros are specific to the 960, and may be used only
952 in code for printing assembler insns and in conditions for
953 define_optimization. */
955 /* 1 if X is an fp register. */
957 #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
959 /* Maximum number of registers that can appear in a valid memory address. */
960 #define MAX_REGS_PER_ADDRESS 2
962 #define CONSTANT_ADDRESS_P(X) \
963 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
964 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
965 || GET_CODE (X) == HIGH)
967 /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
968 is a legitimate general operand.
969 It is given that X satisfies CONSTANT_P.
971 Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0.
973 ??? This probably should be defined to 1. */
975 #define LEGITIMATE_CONSTANT_P(X) \
976 ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), GET_MODE (X)))
978 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
979 and check its validity for a certain class.
980 We have two alternate definitions for each of them.
981 The usual definition accepts all pseudo regs; the other rejects
982 them unless they have been allocated suitable hard regs.
983 The symbol REG_OK_STRICT causes the latter definition to be used.
985 Most source files want to accept pseudo regs in the hope that
986 they will get allocated to the class that the insn wants them to be in.
987 Source files for reload pass need to be strict.
988 After reload, it makes no difference, since pseudo regs have
989 been eliminated by then. */
991 #ifndef REG_OK_STRICT
993 /* Nonzero if X is a hard reg that can be used as an index
994 or if it is a pseudo reg. */
995 #define REG_OK_FOR_INDEX_P(X) \
996 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
997 /* Nonzero if X is a hard reg that can be used as a base reg
998 or if it is a pseudo reg. */
999 #define REG_OK_FOR_BASE_P(X) \
1000 (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1002 #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1003 #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1007 /* Nonzero if X is a hard reg that can be used as an index. */
1008 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1009 /* Nonzero if X is a hard reg that can be used as a base reg. */
1010 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1014 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1015 that is a valid memory address for an instruction.
1016 The MODE argument is the machine mode for the MEM expression
1017 that wants to use this address.
1019 On 80960, legitimate addresses are:
1021 disp (12 or 32 bit) ld foo,r0
1022 base + index ld (g0)[g1*1],r0
1023 base + displ ld 0xf00(g0),r0
1024 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1025 index*scale + base ld (g0)[g1*4],r0
1026 index*scale + displ ld 0xf00[g1*4],r0
1027 index*scale ld [g1*4],r0
1028 index + base + displ ld 0xf00(g0)[g1*1],r0
1030 In each case, scale can be 1, 2, 4, 8, or 16. */
1032 /* Returns 1 if the scale factor of an index term is valid. */
1033 #define SCALE_TERM_P(X) \
1034 (GET_CODE (X) == CONST_INT \
1035 && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1036 || INTVAL(X) == 8 || INTVAL (X) == 16))
1039 #ifdef REG_OK_STRICT
1040 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1041 { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1043 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1044 { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1047 /* Try machine-dependent ways of modifying an illegitimate address
1048 to be legitimate. If we find one, return the new, valid address.
1049 This macro is used in only one place: `memory_address' in explow.c.
1051 OLDX is the address as it was before break_out_memory_refs was called.
1052 In some cases it is useful to look at this to decide what needs to be done.
1054 MODE and WIN are passed so that this macro can use
1055 GO_IF_LEGITIMATE_ADDRESS.
1057 It is always safe for this macro to do nothing. It exists to recognize
1058 opportunities to optimize the output. */
1060 /* On 80960, convert non-canonical addresses to canonical form. */
1062 extern struct rtx_def *legitimize_address ();
1063 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1064 { rtx orig_x = (X); \
1065 (X) = legitimize_address (X, OLDX, MODE); \
1066 if ((X) != orig_x && memory_address_p (MODE, X)) \
1069 /* Go to LABEL if ADDR (a legitimate address expression)
1070 has an effect that depends on the machine mode it is used for.
1071 On the 960 this is never true. */
1073 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1075 /* Specify the machine mode that this machine uses
1076 for the index in the tablejump instruction. */
1077 #define CASE_VECTOR_MODE SImode
1079 /* Define as C expression which evaluates to nonzero if the tablejump
1080 instruction expects the table to contain offsets from the address of the
1082 Do not define this if the table should contain absolute addresses. */
1083 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1085 /* Specify the tree operation to be used to convert reals to integers. */
1086 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1088 /* This is the kind of divide that is easiest to do in the general case. */
1089 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1091 /* Define this as 1 if `char' should by default be signed; else as 0. */
1092 #define DEFAULT_SIGNED_CHAR 0
1094 /* Allow and ignore #sccs directives. */
1095 #define SCCS_DIRECTIVE
1097 /* Max number of bytes we can move from memory to memory
1098 in one reasonably fast instruction. */
1101 /* Define if operations between registers always perform the operation
1102 on the full register even if a narrower mode is specified. */
1103 #define WORD_REGISTER_OPERATIONS
1105 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1106 will either zero-extend or sign-extend. The value of this macro should
1107 be the code that says which one of the two operations is implicitly
1108 done, NIL if none. */
1109 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1111 /* Nonzero if access to memory by bytes is no faster than for words.
1112 Value changed to 1 after reports of poor bitfield code with g++.
1113 Indications are that code is usually as good, sometimes better. */
1115 #define SLOW_BYTE_ACCESS 1
1117 /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
1118 change in SLOW_BYTE_ACCESS would have changed it to 4. */
1120 #define BOOL_TYPE_SIZE CHAR_TYPE_SIZE
1122 /* We assume that the store-condition-codes instructions store 0 for false
1123 and some other value for true. This is the value stored for true. */
1125 #define STORE_FLAG_VALUE 1
1127 /* Define this to be nonzero if shift instructions ignore all but the low-order
1129 #define SHIFT_COUNT_TRUNCATED 0
1131 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1132 is done just by pretending it is already truncated. */
1133 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1135 /* Specify the machine mode that pointers have.
1136 After generation of rtl, the compiler makes no further distinction
1137 between pointers and any other objects of this machine mode. */
1138 #define Pmode SImode
1140 /* Specify the widest mode that BLKmode objects can be promoted to */
1141 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1143 /* These global variables are used to pass information between
1144 cc setter and cc user at insn emit time. */
1146 extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
1148 /* Define the function that build the compare insn for scc and bcc. */
1150 extern struct rtx_def *gen_compare_reg ();
1152 /* Add any extra modes needed to represent the condition code.
1154 Also, signed and unsigned comparisons are distinguished, as
1155 are operations which are compatible with chkbit insns. */
1156 #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1158 /* Define the names for the modes specified above. */
1159 #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1161 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1162 return the mode to be used for the comparison. For floating-point, CCFPmode
1163 should be used. CC_NOOVmode should be used when the first operand is a
1164 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1166 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1168 /* A function address in a call instruction is a byte address
1169 (for indexing purposes) so give the MEM rtx a byte's mode. */
1170 #define FUNCTION_MODE SImode
1172 /* Define this if addresses of constant functions
1173 shouldn't be put through pseudo regs where they can be cse'd.
1174 Desirable on machines where ordinary constants are expensive
1175 but a CALL with constant address is cheap. */
1176 #define NO_FUNCTION_CSE
1178 /* Use memcpy, etc. instead of bcopy. */
1181 #define TARGET_MEM_FUNCTIONS 1
1184 /* Compute the cost of computing a constant rtl expression RTX
1185 whose rtx-code is CODE. The body of this macro is a portion
1186 of a switch statement. If the code is computed here,
1187 return it with a return statement. Otherwise, break from the switch. */
1189 /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1190 that can be non-ldconst operands in rare cases are cost 1. Other constants
1191 have higher costs. */
1193 /* Must check for OUTER_CODE of SET for power2_operand, because
1194 reload_cse_move2add calls us with OUTER_CODE of PLUS to decide when
1195 to replace set with add. */
1197 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1199 if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1200 || (OUTER_CODE == SET && power2_operand (RTX, VOIDmode))) \
1202 else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1207 return (TARGET_C_SERIES ? 6 : 8); \
1208 case CONST_DOUBLE: \
1209 if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1210 || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1214 /* The i960 offers addressing modes which are "as cheap as a register".
1215 See i960.c (or gcc.texinfo) for details. */
1217 #define ADDRESS_COST(RTX) \
1218 (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1220 /* Control the assembler format that we output. */
1222 /* Output at beginning of assembler file. */
1224 #define ASM_FILE_START(file)
1226 /* Output to assembler file text saying following lines
1227 may contain character constants, extra white space, comments, etc. */
1229 #define ASM_APP_ON ""
1231 /* Output to assembler file text saying following lines
1232 no longer contain unusual constructs. */
1234 #define ASM_APP_OFF ""
1236 /* Output before read-only data. */
1238 #define TEXT_SECTION_ASM_OP ".text"
1240 /* Output before writable data. */
1242 #define DATA_SECTION_ASM_OP ".data"
1244 /* How to refer to registers in assembler output.
1245 This sequence is indexed by compiler's hard-register-number (see above). */
1247 #define REGISTER_NAMES { \
1248 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1249 "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1250 "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1252 "fp0","fp1","fp2", "fp3", "cc", "fake" }
1254 /* How to renumber registers for dbx and gdb.
1255 In the 960 encoding, g0..g15 are registers 16..31. */
1257 #define DBX_REGISTER_NUMBER(REGNO) \
1258 (((REGNO) < 16) ? (REGNO) + 16 \
1259 : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1261 /* Don't emit dbx records longer than this. This is an arbitrary value. */
1262 #define DBX_CONTIN_LENGTH 1500
1264 /* This is how to output a note to DBX telling it the line number
1265 to which the following sequence of instructions corresponds. */
1267 #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1268 { if (write_symbols == SDB_DEBUG) { \
1269 fprintf ((FILE), "\t.ln %d\n", \
1270 (sdb_begin_function_line \
1271 ? (LINE) - sdb_begin_function_line : 1)); \
1272 } else if (write_symbols == DBX_DEBUG) { \
1273 fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1276 /* This is how to output the definition of a user-level label named NAME,
1277 such as the label on a static function or variable NAME. */
1279 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1280 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1282 /* This is how to output a command to make the user-level label named NAME
1283 defined for reference from other files. */
1285 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1286 { fputs ("\t.globl ", FILE); \
1287 assemble_name (FILE, NAME); \
1288 fputs ("\n", FILE); }
1290 /* The prefix to add to user-visible assembler symbols. */
1292 #define USER_LABEL_PREFIX "_"
1294 /* This is how to output an internal numbered label where
1295 PREFIX is the class of label and NUM is the number within the class. */
1297 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1298 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1300 /* This is how to store into the string LABEL
1301 the symbol_ref name of an internal numbered label where
1302 PREFIX is the class of label and NUM is the number within the class.
1303 This is suitable for output with `assemble_name'. */
1305 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1306 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1308 /* This is how to output an assembler line defining a `long double'
1311 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) i960_output_long_double(FILE, VALUE)
1313 /* This is how to output an assembler line defining a `double' constant. */
1315 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1317 /* This is how to output an assembler line defining a `float' constant. */
1319 #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1321 /* This is how to output an assembler line defining an `int' constant. */
1323 #define ASM_OUTPUT_INT(FILE,VALUE) \
1324 ( fprintf (FILE, "\t.word "), \
1325 output_addr_const (FILE, (VALUE)), \
1326 fprintf (FILE, "\n"))
1328 /* Likewise for `char' and `short' constants. */
1330 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1331 ( fprintf (FILE, "\t.short "), \
1332 output_addr_const (FILE, (VALUE)), \
1333 fprintf (FILE, "\n"))
1335 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1336 ( fprintf (FILE, "\t.byte "), \
1337 output_addr_const (FILE, (VALUE)), \
1338 fprintf (FILE, "\n"))
1340 /* This is how to output an assembler line for a numeric constant byte. */
1342 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1343 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1345 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1346 fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1348 /* This is how to output an insn to pop a register from the stack.
1349 It need not be very fast code. */
1351 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1352 fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1354 /* This is how to output an element of a case-vector that is absolute. */
1356 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1357 fprintf (FILE, "\t.word L%d\n", VALUE)
1359 /* This is how to output an element of a case-vector that is relative. */
1361 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1362 fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1364 /* This is how to output an assembler line that says to advance the
1365 location counter to a multiple of 2**LOG bytes. */
1367 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1368 fprintf (FILE, "\t.align %d\n", (LOG))
1370 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1371 fprintf (FILE, "\t.space %d\n", (SIZE))
1373 /* This says how to output an assembler line
1374 to define a global common symbol. */
1376 /* For common objects, output unpadded size... gld960 & lnk960 both
1377 have code to align each common object at link time. Also, if size
1378 is 0, treat this as a declaration, not a definition - i.e.,
1379 do nothing at all. */
1381 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1382 { if ((SIZE) != 0) \
1384 fputs (".globl ", (FILE)), \
1385 assemble_name ((FILE), (NAME)), \
1386 fputs ("\n.comm ", (FILE)), \
1387 assemble_name ((FILE), (NAME)), \
1388 fprintf ((FILE), ",%d\n", (SIZE)); \
1392 /* This says how to output an assembler line to define a local common symbol.
1393 Output unpadded size, with request to linker to align as requested.
1394 0 size should not be possible here. */
1396 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1397 ( fputs (".bss\t", (FILE)), \
1398 assemble_name ((FILE), (NAME)), \
1399 fprintf ((FILE), ",%d,%d\n", (SIZE), \
1400 (floor_log2 ((ALIGN) / BITS_PER_UNIT))))
1402 /* A C statement (sans semicolon) to output to the stdio stream
1403 FILE the assembler definition of uninitialized global DECL named
1404 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1405 Try to use asm_output_aligned_bss to implement this macro. */
1407 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1409 fputs (".globl ", (FILE)); \
1410 assemble_name ((FILE), (NAME)); \
1411 fputs ("\n", (FILE)); \
1412 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1415 /* Output text for an #ident directive. */
1416 #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1418 /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1420 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (TARGET_CODE_ALIGN ? 3 : 0)
1422 /* Store in OUTPUT a string (made with alloca) containing
1423 an assembler-name for a local static variable named NAME.
1424 LABELNO is an integer which is different for each call. */
1426 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1427 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1428 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1430 /* Define the parentheses used to group arithmetic operations
1431 in assembler code. */
1433 #define ASM_OPEN_PAREN "("
1434 #define ASM_CLOSE_PAREN ")"
1436 /* Define results of standard character escape sequences. */
1437 #define TARGET_BELL 007
1438 #define TARGET_BS 010
1439 #define TARGET_TAB 011
1440 #define TARGET_NEWLINE 012
1441 #define TARGET_VT 013
1442 #define TARGET_FF 014
1443 #define TARGET_CR 015
1445 /* Output assembler code to FILE to initialize this source file's
1446 basic block profiling info, if that has not already been done. */
1448 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1449 { fprintf (FILE, "\tld LPBX0,g12\n"); \
1450 fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1451 fprintf (FILE, "\tlda LPBX0,g12\n"); \
1452 fprintf (FILE, "\tcall ___bb_init_func\n"); \
1453 fprintf (FILE, "LPY%d:\n",LABELNO); }
1455 /* Output assembler code to FILE to increment the entry-count for
1456 the BLOCKNO'th basic block in this source file. */
1458 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1459 { int blockn = (BLOCKNO); \
1460 fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1461 fprintf (FILE, "\taddo g12,1,g12\n"); \
1462 fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1464 /* Print operand X (an rtx) in assembler syntax to file FILE.
1465 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1466 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1468 #define PRINT_OPERAND(FILE, X, CODE) \
1469 i960_print_operand (FILE, X, CODE);
1471 /* Print a memory address as an operand to reference that memory location. */
1473 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1474 i960_print_operand_addr (FILE, ADDR)
1476 /* Output assembler code for a block containing the constant parts
1477 of a trampoline, leaving space for the variable parts. */
1479 /* On the i960, the trampoline contains three instructions:
1480 ldconst _function, r4
1481 ldconst static addr, r3
1484 #define TRAMPOLINE_TEMPLATE(FILE) \
1486 ASM_OUTPUT_INT (FILE, GEN_INT (0x8C203000)); \
1487 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1488 ASM_OUTPUT_INT (FILE, GEN_INT (0x8C183000)); \
1489 ASM_OUTPUT_INT (FILE, GEN_INT (0x00000000)); \
1490 ASM_OUTPUT_INT (FILE, GEN_INT (0x84212000)); \
1493 /* Length in units of the trampoline for entering a nested function. */
1495 #define TRAMPOLINE_SIZE 20
1497 /* Emit RTL insns to initialize the variable parts of a trampoline.
1498 FNADDR is an RTX for the address of the function's pure code.
1499 CXT is an RTX for the static chain value for the function. */
1501 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1503 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1505 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1509 /* Generate RTL to flush the register windows so as to make arbitrary frames
1511 #define SETUP_FRAME_ADDRESSES() \
1512 emit_insn (gen_flush_register_windows ())
1514 #define BUILTIN_SETJMP_FRAME_VALUE hard_frame_pointer_rtx
1517 /* Promote char and short arguments to ints, when want compatibility with
1518 the iC960 compilers. */
1520 /* ??? In order for this to work, all users would need to be changed
1521 to test the value of the macro at run time. */
1522 #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1523 /* ??? This does not exist. */
1524 #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1527 /* Instruction type definitions. Used to alternate instructions types for
1528 better performance on the C series chips. */
1530 enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
1532 /* Holds the insn type of the last insn output to the assembly file. */
1534 extern enum insn_types i960_last_insn_type;
1536 /* Parse opcodes, and set the insn last insn type based on them. */
1538 #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1540 /* Table listing what rtl codes each predicate in i960.c will accept. */
1542 #define PREDICATE_CODES \
1543 {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1544 LABEL_REF, SUBREG, REG, MEM}}, \
1545 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1546 {"logic_operand", {SUBREG, REG, CONST_INT}}, \
1547 {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1548 {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1549 {"literal", {CONST_INT}}, \
1550 {"fp_literal_one", {CONST_DOUBLE}}, \
1551 {"fp_literal_double", {CONST_DOUBLE}}, \
1552 {"fp_literal", {CONST_DOUBLE}}, \
1553 {"signed_literal", {CONST_INT}}, \
1554 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1555 {"eq_or_neq", {EQ, NE}}, \
1556 {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1557 CONST_DOUBLE, CONST}}, \
1558 {"power2_operand", {CONST_INT}}, \
1559 {"cmplpower2_operand", {CONST_INT}},
1561 /* Define functions in i960.c and used in insn-output.c. */
1563 extern char *i960_output_ldconst ();
1564 extern char *i960_output_call_insn ();
1565 extern char *i960_output_ret_insn ();
1566 extern char *i960_output_move_double ();
1567 extern char *i960_output_move_quad ();
1569 /* Defined in reload.c, and used in insn-recog.c. */
1571 extern int rtx_equal_function_value_matters;
1573 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1574 Used for C++ multiple inheritance. */
1575 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
1578 if (d < 0 && d > -32) \
1579 fprintf (FILE, "\tsubo %d,g0,g0\n", -d); \
1580 else if (d > 0 && d < 32) \
1581 fprintf (FILE, "\taddo %d,g0,g0\n", d); \
1584 fprintf (FILE, "\tldconst %d,r5\n", d); \
1585 fprintf (FILE, "\taddo r5,g0,g0\n"); \
1587 fprintf (FILE, "\tbx "); \
1588 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
1589 fprintf (FILE, "\n"); \