1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0, i960_compare_op1;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment;
53 static int i960_last_maxbitalignment;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label = 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (finput)
99 while (c == ' ' || c == '\t')
103 && getc (finput) == 'l'
104 && getc (finput) == 'i'
105 && getc (finput) == 'g'
106 && getc (finput) == 'n'
107 && ((c = getc (finput)) == ' ' || c == '\t' || c == '\n'))
113 while (c == ' ' || c == '\t')
117 while (c >= '0' && c <= '9')
119 if (s < buf + sizeof buf - 1)
129 /* Return to last alignment. */
130 align = i960_last_maxbitalignment / 8;
137 i960_last_maxbitalignment = i960_maxbitalignment;
138 i960_maxbitalignment = align * 8;
142 /* Silently ignore bad values. */
146 /* NOTE: ic960 R3.0 pragma align definition:
148 #pragma align [(size)] | (identifier=size[,...])
149 #pragma noalign [(identifier)[,...]]
151 (all parens are optional)
153 - size is [1,2,4,8,16]
154 - noalign means size==1
155 - applies only to component elements of a struct (and union?)
156 - identifier applies to structure tag (only)
157 - missing identifier means next struct
159 - alignment rules for bitfields need more investigation */
162 /* Should be pragma 'far' or equivalent for callx/balx here. */
167 /* Initialize variables before compiling any files. */
172 if (TARGET_IC_COMPAT2_0)
174 i960_maxbitalignment = 8;
175 i960_last_maxbitalignment = 128;
179 i960_maxbitalignment = 128;
180 i960_last_maxbitalignment = 8;
184 /* Return true if OP can be used as the source of an fp move insn. */
187 fpmove_src_operand (op, mode)
189 enum machine_mode mode;
191 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
195 /* Return true if OP is a register or zero. */
198 reg_or_zero_operand (op, mode)
200 enum machine_mode mode;
202 return register_operand (op, mode) || op == const0_rtx;
206 /* Return truth value of whether OP can be used as an operands in a three
207 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
210 arith_operand (op, mode)
212 enum machine_mode mode;
214 return (register_operand (op, mode) || literal (op, mode));
217 /* Return true if OP is a register or a valid floating point literal. */
220 fp_arith_operand (op, mode)
222 enum machine_mode mode;
224 return (register_operand (op, mode) || fp_literal (op, mode));
227 /* Return true is OP is a register or a valid signed integer literal. */
230 signed_arith_operand (op, mode)
232 enum machine_mode mode;
234 return (register_operand (op, mode) || signed_literal (op, mode));
237 /* Return truth value of whether OP is a integer which fits the
238 range constraining immediate operands in three-address insns. */
243 enum machine_mode mode;
245 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
248 /* Return true if OP is a float constant of 1. */
251 fp_literal_one (op, mode)
253 enum machine_mode mode;
255 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
258 /* Return true if OP is a float constant of 0. */
261 fp_literal_zero (op, mode)
263 enum machine_mode mode;
265 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
268 /* Return true if OP is a valid floating point literal. */
273 enum machine_mode mode;
275 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
278 /* Return true if OP is a valid signed immediate constant. */
281 signed_literal(op, mode)
283 enum machine_mode mode;
285 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
288 /* Return truth value of statement that OP is a symbolic memory
289 operand of mode MODE. */
292 symbolic_memory_operand (op, mode)
294 enum machine_mode mode;
296 if (GET_CODE (op) == SUBREG)
297 op = SUBREG_REG (op);
298 if (GET_CODE (op) != MEM)
301 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
302 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
305 /* Return truth value of whether OP is EQ or NE. */
310 enum machine_mode mode;
312 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
315 /* OP is an integer register or a constant. */
318 arith32_operand (op, mode)
320 enum machine_mode mode;
322 if (register_operand (op, mode))
324 return (CONSTANT_P (op));
327 /* Return true if OP is an integer constant which is a power of 2. */
330 power2_operand (op,mode)
332 enum machine_mode mode;
334 if (GET_CODE (op) != CONST_INT)
337 return exact_log2 (INTVAL (op)) >= 0;
340 /* Return true if OP is an integer constant which is the complement of a
344 cmplpower2_operand (op, mode)
346 enum machine_mode mode;
348 if (GET_CODE (op) != CONST_INT)
351 return exact_log2 (~ INTVAL (op)) >= 0;
354 /* If VAL has only one bit set, return the index of that bit. Otherwise
363 for (i = 0; val != 0; i++, val >>= 1)
375 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
376 The return value indicates how many consecutive non-zero bits exist
377 if this is a mask. This is the same as the next function, except that
378 it does not indicate what the start and stop bit positions are. */
384 register int start, end, i;
387 for (i = 0; val != 0; val >>= 1, i++)
397 /* Still looking for the first bit. */
401 /* We've seen the start of a bit sequence, and now a zero. There
402 must be more one bits, otherwise we would have exited the loop.
403 Therefore, it is not a mask. */
408 /* The bit string has ones from START to END bit positions only. */
409 return end - start + 1;
412 /* If VAL is a mask, then return nonzero, with S set to the starting bit
413 position and E set to the ending bit position of the mask. The return
414 value indicates how many consecutive bits exist in the mask. This is
415 the same as the previous function, except that it also indicates the
416 start and end bit positions of the mask. */
423 register int start, end, i;
427 for (i = 0; val != 0; val >>= 1, i++)
438 /* Still looking for the first bit. */
442 /* We've seen the start of a bit sequence, and now a zero. There
443 must be more one bits, otherwise we would have exited the loop.
444 Therefor, it is not a mask. */
453 /* The bit string has ones from START to END bit positions only. */
456 return ((start < 0) ? 0 : end - start + 1);
459 /* Return the machine mode to use for a comparison. */
462 select_cc_mode (op, x)
466 if (op == GTU || op == LTU || op == GEU || op == LEU)
471 /* X and Y are two things to compare using CODE. Emit the compare insn and
472 return the rtx for register 36 in the proper mode. */
475 gen_compare_reg (code, x, y)
480 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
481 enum machine_mode mode
482 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
486 if (! arith_operand (x, mode))
487 x = force_reg (SImode, x);
488 if (! arith_operand (y, mode))
489 y = force_reg (SImode, y);
492 cc_reg = gen_rtx (REG, ccmode, 36);
493 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
494 gen_rtx (COMPARE, ccmode, x, y)));
499 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
500 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
501 are 4. Indexed addresses are cost 6. */
503 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
506 i960_address_cost (x)
510 /* Handled before calling here. */
511 if (GET_CODE (x) == REG)
514 if (GET_CODE (x) == PLUS)
516 rtx base = XEXP (x, 0);
517 rtx offset = XEXP (x, 1);
519 if (GET_CODE (base) == SUBREG)
520 base = SUBREG_REG (base);
521 if (GET_CODE (offset) == SUBREG)
522 offset = SUBREG_REG (offset);
524 if (GET_CODE (base) == REG)
526 if (GET_CODE (offset) == REG)
528 if (GET_CODE (offset) == CONST_INT)
530 if ((unsigned)INTVAL (offset) < 2047)
534 if (CONSTANT_P (offset))
537 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
540 /* This is an invalid address. The return value doesn't matter, but
541 for convenience we make this more expensive than anything else. */
544 if (GET_CODE (x) == MULT)
547 /* Symbol_refs and other unrecognized addresses are cost 4. */
551 /* Emit insns to move operands[1] into operands[0].
553 Return 1 if we have written out everything that needs to be done to
554 do the move. Otherwise, return 0 and the caller will emit the move
558 emit_move_sequence (operands, mode)
560 enum machine_mode mode;
562 register rtx operand0 = operands[0];
563 register rtx operand1 = operands[1];
565 /* We can only store registers to memory. */
567 if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG)
568 operands[1] = force_reg (mode, operand1);
573 /* Emit insns to load a constant. Uses several strategies to try to use
574 as few insns as possible. */
577 i960_output_ldconst (dst, src)
578 register rtx dst, src;
581 register unsigned rsrc2;
582 enum machine_mode mode = GET_MODE (dst);
584 union { long l[2]; double d; } x;
586 operands[0] = operands[2] = dst;
587 operands[1] = operands[3] = src;
589 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
590 must be a ldconst insn. */
592 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
594 output_asm_insn ("ldconst %1,%0", operands);
597 else if (mode == DFmode)
601 if (fp_literal_zero (src, DFmode))
604 split_double (src, &first, &second);
606 output_asm_insn ("# ldconst %1,%0",operands);
608 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
610 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
612 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
613 operands[1] = second;
614 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
618 else if (mode == TImode)
620 /* ??? This is currently not handled at all. */
623 /* Note: lowest order word goes in lowest numbered reg. */
624 rsrc1 = INTVAL (src);
625 if (rsrc1 >= 0 && rsrc1 < 32)
628 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
629 /* Go pick up the low-order word. */
631 else if (mode == DImode)
633 rtx upperhalf, lowerhalf, xoperands[2];
636 if (GET_CODE (src) == CONST_DOUBLE)
638 upperhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (src));
639 lowerhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (src));
641 else if (GET_CODE (src) == CONST_INT)
644 upperhalf = INTVAL (src) < 0 ? constm1_rtx : const0_rtx;
649 /* Note: lowest order word goes in lowest numbered reg. */
650 /* Numbers from 0 to 31 can be handled with a single insn. */
651 rsrc1 = INTVAL (lowerhalf);
652 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
655 /* Output the upper half with a recursive call. */
656 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
657 xoperands[1] = upperhalf;
658 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
660 /* The lower word is emitted as normally. */
662 else if (mode == SFmode)
667 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
668 REAL_VALUE_TO_TARGET_SINGLE (d, value);
670 output_asm_insn ("# ldconst %1,%0",operands);
671 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
672 operands[1] = gen_rtx (CONST_INT, VOIDmode, value);
673 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
679 rsrc1 = INTVAL (src);
685 else if (mode == HImode)
694 /* ldconst 0..31,X -> mov 0..31,X */
697 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
702 /* ldconst 32..63,X -> add 31,nn,X */
705 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
707 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31);
708 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
714 /* ldconst -1..-31 -> sub 0,0..31,X */
717 /* return 'sub -(%1),0,%0' */
718 operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1);
719 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
723 /* ldconst -32 -> not 31,X */
726 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1);
727 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
732 /* If const is a single bit. */
733 if (bitpos (rsrc1) >= 0)
735 operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1));
736 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
740 /* If const is a bit string of less than 6 bits (1..31 shifted). */
745 if (bitstr (rsrc1, &s, &e) < 6)
747 rsrc2 = ((unsigned int) rsrc1) >> s;
748 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2);
749 operands[2] = gen_rtx (CONST_INT, VOIDmode, s);
750 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
755 /* Unimplemented cases:
756 const is in range 0..31 but rotated around end of word:
757 ror 31,3,g0 -> ldconst 0xe0000003,g0
759 and any 2 instruction cases that might be worthwhile */
761 output_asm_insn ("ldconst %1,%0", operands);
765 /* Determine if there is an opportunity for a bypass optimization.
766 Bypass succeeds on the 960K* if the destination of the previous
767 instruction is the second operand of the current instruction.
768 Bypass always succeeds on the C*.
770 Return 1 if the pattern should interchange the operands.
772 CMPBR_FLAG is true if this is for a compare-and-branch insn.
773 OP1 and OP2 are the two source operands of a 3 operand insn. */
776 i960_bypass (insn, op1, op2, cmpbr_flag)
777 register rtx insn, op1, op2;
780 register rtx prev_insn, prev_dest;
785 /* Can't do this if op1 isn't a register. */
789 /* Can't do this for a compare-and-branch if both ops aren't regs. */
790 if (cmpbr_flag && ! REG_P (op2))
793 prev_insn = prev_real_insn (insn);
795 if (prev_insn && GET_CODE (prev_insn) == INSN
796 && GET_CODE (PATTERN (prev_insn)) == SET)
798 prev_dest = SET_DEST (PATTERN (prev_insn));
799 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
800 || (GET_CODE (prev_dest) == SUBREG
801 && GET_CODE (SUBREG_REG (prev_dest)) == REG
802 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
808 /* Output the code which declares the function name. This also handles
809 leaf routines, which have special requirements, and initializes some
813 i960_function_name_declare (file, name, fndecl)
822 /* Increment global return label. */
826 /* Compute whether tail calls and leaf routine optimizations can be performed
827 for this function. */
839 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
840 argblock, because argblock uses g14 implicitly. */
842 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
848 /* See if caller passes in an address to return value. */
850 if (aggregate_value_p (DECL_RESULT (fndecl)))
856 /* Can not use tail calls or make this a leaf routine if there is a non
859 if (get_frame_size () != 0)
862 /* I don't understand this condition, and do not think that it is correct.
863 Apparently this is just checking whether the frame pointer is used, and
864 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
867 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
868 if (GET_CODE (insn) == INSN
869 && reg_mentioned_p (frame_pointer_rtx, insn))
875 /* Check for CALL insns. Can not be a leaf routine if there are any. */
878 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
879 if (GET_CODE (insn) == CALL_INSN)
885 /* Can not be a leaf routine if any non-call clobbered registers are
886 used in this function. */
889 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
890 if (regs_ever_live[i]
891 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
893 /* Global registers. */
894 if (i < 16 && i > 7 && i != 13)
896 /* Local registers. */
901 /* Now choose a leaf return register, if we can find one, and if it is
902 OK for this to be a leaf routine. */
904 i960_leaf_ret_reg = -1;
906 if (optimize && leaf_proc_ok)
908 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
909 if (regs_ever_live[i] == 0)
911 i960_leaf_ret_reg = i;
912 regs_ever_live[i] = 1;
917 /* Do this after choosing the leaf return register, so it will be listed
918 if one was chosen. */
920 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
921 fprintf (file, "\t# Registers used: ");
923 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
925 if (regs_ever_live[i])
927 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
929 if (i > 15 && j == 0)
931 fprintf (file,"\n\t#\t\t ");
937 fprintf (file, "\n");
939 if (i960_leaf_ret_reg >= 0)
941 /* Make it a leaf procedure. */
943 if (TREE_PUBLIC (fndecl))
944 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
946 fprintf (file, "\t.leafproc\t");
947 assemble_name (file, name);
948 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
949 ASM_OUTPUT_LABEL (file, name);
950 fprintf (file, "\tlda LR%d,g14\n", ret_label);
951 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
952 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
956 fprintf (file, "\tlda 0,g14\n");
957 i960_last_insn_type = I_TYPE_MEM;
961 fprintf (file, "\tmov 0,g14\n");
962 i960_last_insn_type = I_TYPE_REG;
967 ASM_OUTPUT_LABEL (file, name);
968 i960_last_insn_type = I_TYPE_CTRL;
972 /* Compute and return the frame size. */
975 compute_frame_size (size)
979 int outgoing_args_size = current_function_outgoing_args_size;
981 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
982 as size is concerned. */
983 actual_fsize = (size + 15) & -16;
984 actual_fsize += (outgoing_args_size + 15) & -16;
989 /* Output code for the function prologue. */
992 i960_function_prologue (file, size)
996 register int i, j, nr;
999 int actual_fsize, offset;
1001 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1003 int regs[FIRST_PSEUDO_REGISTER];
1005 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1006 if (regs_ever_live[i]
1007 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1010 /* Count global registers that need saving. */
1017 epilogue_string[0] = '\0';
1019 if (profile_flag || profile_block_flag)
1021 /* When profiling, we may use registers 20 to 27 to save arguments, so
1022 they can't be used here for saving globals. J is the number of
1023 argument registers the mcount call will save. */
1024 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1027 for (i = 20; i <= j + 20; i++)
1031 /* First look for local registers to save globals in. */
1032 for (i = 0; i < 16; i++)
1037 /* Start at r4, not r3. */
1038 for (j = 20; j < 32; j++)
1045 regs_ever_live[j] = 1;
1047 if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0
1048 && regs[i+1] != 0 && regs[j+1] == 0)
1053 regs_ever_live[j+1] = 1;
1055 if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0
1056 && regs[i+2] != 0 && regs[j+2] == 0)
1061 regs_ever_live[j+2] = 1;
1063 if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0)
1068 regs_ever_live[j+3] = 1;
1071 fprintf (file, "\tmov%s %s,%s\n",
1074 (nr == 2) ? "l" : ""),
1075 reg_names[i], reg_names[j]);
1076 sprintf (tmpstr, "\tmov%s %s,%s\n",
1079 (nr == 2) ? "l" : ""),
1080 reg_names[j], reg_names[i]);
1081 strcat (epilogue_string, tmpstr);
1089 /* N_iregs is now the number of global registers that haven't been saved
1092 rsize = (n_iregs * 4);
1093 actual_fsize = compute_frame_size (size) + rsize;
1095 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1096 size up to the nearest multiple of 16. I don't know whether this is
1097 necessary, or even desirable.
1099 The frame pointer must be aligned, but the call instruction takes care of
1100 that. If we leave the stack pointer unaligned, we may save a little on
1101 dynamic stack allocation. And we don't lose, at least according to the
1103 actual_fsize = (actual_fsize + 15) & ~0xF;
1106 /* Allocate space for register save and locals. */
1107 if (actual_fsize > 0)
1109 if (actual_fsize < 32)
1110 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1112 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1115 /* Take hardware register save area created by the call instruction
1116 into account, but store them before the argument block area. */
1117 offset = 64 + actual_fsize - compute_frame_size (0) - rsize;
1118 /* Save registers on stack if needed. */
1119 for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
1126 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1129 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1133 if (nr == 3 && regs[i+3] == -1)
1136 fprintf (file,"\tst%s %s,%d(fp)\n",
1139 (nr == 2) ? "l" : ""),
1140 reg_names[i], offset);
1141 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1144 (nr == 2) ? "l" : ""),
1145 offset, reg_names[i]);
1146 strcat (epilogue_string, tmpstr);
1152 if (actual_fsize == 0 && size == 0 && rsize == 0)
1155 fprintf (file, "\t#Prologue stats:\n");
1156 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1159 fprintf (file, "\t# Local Variable Size: %d bytes\n", size);
1161 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1163 fprintf (file, "\t#End Prologue#\n");
1166 /* Output code for the function profiler. */
1169 output_function_profiler (file, labelno)
1173 /* The last used parameter register. */
1175 int i, j, increment;
1176 int varargs_stdarg_function
1177 = VARARGS_STDARG_FUNCTION (current_function_decl);
1179 /* Figure out the last used parameter register. The proper thing to do
1180 is to walk incoming args of the function. A function might have live
1181 parameter registers even if it has no incoming args. Note that we
1182 don't have to save parameter registers g8 to g11 because they are
1185 /* See also output_function_prologue, which tries to use local registers
1186 for preserved call-saved global registers. */
1188 for (last_parm_reg = 7;
1189 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1193 /* Save parameter registers in regs r4 (20) to r11 (27). */
1195 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1197 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1199 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1201 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1206 fprintf (file, "\tmov%s g%d,r%d\n",
1207 (increment == 4 ? "q" : increment == 3 ? "t"
1208 : increment == 2 ? "l": ""), i, j);
1211 /* If this function uses the arg pointer, then save it in r3 and then
1214 if (current_function_args_size != 0 || varargs_stdarg_function)
1215 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1217 /* Load location address into g0 and call mcount. */
1219 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1221 /* If this function uses the arg pointer, restore it. */
1223 if (current_function_args_size != 0 || varargs_stdarg_function)
1224 fprintf (file, "\tmov r3,g14\n");
1226 /* Restore parameter registers. */
1228 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1230 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1232 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1234 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1239 fprintf (file, "\tmov%s r%d,g%d\n",
1240 (increment == 4 ? "q" : increment == 3 ? "t"
1241 : increment == 2 ? "l": ""), j, i);
1245 /* Output code for the function epilogue. */
1248 i960_function_epilogue (file, size)
1252 if (i960_leaf_ret_reg >= 0)
1254 fprintf (file, "LR%d: ret\n", ret_label);
1258 if (*epilogue_string == 0)
1262 /* Emit a return insn, but only if control can fall through to here. */
1264 tmp = get_last_insn ();
1267 if (GET_CODE (tmp) == BARRIER)
1269 if (GET_CODE (tmp) == CODE_LABEL)
1271 if (GET_CODE (tmp) == JUMP_INSN)
1273 if (GET_CODE (PATTERN (tmp)) == RETURN)
1277 if (GET_CODE (tmp) == NOTE)
1279 tmp = PREV_INSN (tmp);
1284 fprintf (file, "LR%d: ret\n", ret_label);
1288 fprintf (file, "LR%d:\n", ret_label);
1290 fprintf (file, "\t#EPILOGUE#\n");
1292 /* Output the string created by the prologue which will restore all
1293 registers saved by the prologue. */
1295 if (epilogue_string[0] != '\0')
1296 fprintf (file, "%s", epilogue_string);
1298 /* Must clear g14 on return. */
1300 if (current_function_args_size != 0
1301 || VARARGS_STDARG_FUNCTION (current_function_decl))
1302 fprintf (file, "\tmov 0,g14\n");
1304 fprintf (file, "\tret\n");
1305 fprintf (file, "\t#End Epilogue#\n");
1308 /* Output code for a call insn. */
1311 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1312 register rtx target, argsize_rtx, arg_pointer, insn;
1314 int argsize = INTVAL (argsize_rtx);
1315 rtx nexti = next_real_insn (insn);
1317 int varargs_stdarg_function
1318 = VARARGS_STDARG_FUNCTION (current_function_decl);
1320 operands[0] = target;
1321 operands[1] = arg_pointer;
1323 if (current_function_args_size != 0 || varargs_stdarg_function)
1324 output_asm_insn ("mov g14,r3", operands);
1327 output_asm_insn ("lda %a1,g14", operands);
1328 else if (current_function_args_size != 0 || varargs_stdarg_function)
1329 output_asm_insn ("mov 0,g14", operands);
1331 /* The code used to assume that calls to SYMBOL_REFs could not be more
1332 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1333 feature is now implemented by relaxing in the GNU linker. It can convert
1334 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1336 /* Nexti could be zero if the called routine is volatile. */
1337 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1338 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1340 /* Delete following return insn. */
1341 if (nexti && no_labels_between_p (insn, nexti))
1342 delete_insn (nexti);
1343 output_asm_insn ("bx %0", operands);
1344 return "# notreached";
1347 output_asm_insn ("callx %0", operands);
1349 if (current_function_args_size != 0 || varargs_stdarg_function)
1350 output_asm_insn ("mov r3,g14", operands);
1355 /* Output code for a return insn. */
1358 i960_output_ret_insn (insn)
1361 static char lbuf[20];
1363 if (*epilogue_string != 0)
1365 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1368 sprintf (lbuf, "b LR%d", ret_label);
1372 if (current_function_args_size != 0
1373 || VARARGS_STDARG_FUNCTION (current_function_decl))
1374 output_asm_insn ("mov 0,g14", 0);
1376 if (i960_leaf_ret_reg >= 0)
1378 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1385 /* Return a character string representing the branch prediction
1386 opcode to be tacked on an instruction. This must at least
1387 return a null string. */
1390 i960_br_predict_opcode (lab_ref, insn)
1393 if (TARGET_BRANCH_PREDICT)
1395 unsigned long label_uid;
1397 if (GET_CODE (lab_ref) == CODE_LABEL)
1398 label_uid = INSN_UID (lab_ref);
1399 else if (GET_CODE (lab_ref) == LABEL_REF)
1400 label_uid = INSN_UID (XEXP (lab_ref, 0));
1404 /* If not optimizing, then the insn_addresses array will not be
1405 valid. In this case, always return ".t" since most branches
1406 are taken. If optimizing, return .t for backward branches
1407 and .f for forward branches. */
1409 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1418 /* Print the operand represented by rtx X formatted by code CODE. */
1421 i960_print_operand (file, x, code)
1426 enum rtx_code rtxcode = GET_CODE (x);
1433 /* Second reg of a double. */
1434 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1438 fprintf (file, "%s", reg_names[REGNO (x)]);
1446 else if (rtxcode == MEM)
1448 output_address (XEXP (x, 0));
1451 else if (rtxcode == CONST_INT)
1453 if (INTVAL (x) > 9999 || INTVAL (x) < -999)
1454 fprintf (file, "0x%x", INTVAL (x));
1456 fprintf (file, "%d", INTVAL (x));
1459 else if (rtxcode == CONST_DOUBLE)
1463 if (x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1465 fprintf (file, "0f0.0");
1468 else if (x == CONST1_RTX (DFmode) || x == CONST1_RTX (SFmode))
1470 fprintf (file, "0f1.0");
1474 /* This better be a comment. */
1475 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1476 fprintf (file, "%#g", d);
1483 /* Branch or jump, depending on assembler. */
1484 if (TARGET_ASM_COMPAT)
1491 /* Sign of condition. */
1492 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1493 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1495 else if ((rtxcode == GT) || (rtxcode == LT)
1496 || (rtxcode == GE) || (rtxcode == LE))
1503 /* Inverted condition. */
1504 rtxcode = reverse_condition (rtxcode);
1508 /* Inverted condition w/ reversed operands. */
1509 rtxcode = reverse_condition (rtxcode);
1513 /* Reversed operand condition. */
1514 rtxcode = swap_condition (rtxcode);
1518 /* Normal condition. */
1520 if (rtxcode == EQ) { fputs ("e", file); return; }
1521 else if (rtxcode == NE) { fputs ("ne", file); return; }
1522 else if (rtxcode == GT) { fputs ("g", file); return; }
1523 else if (rtxcode == GTU) { fputs ("g", file); return; }
1524 else if (rtxcode == LT) { fputs ("l", file); return; }
1525 else if (rtxcode == LTU) { fputs ("l", file); return; }
1526 else if (rtxcode == GE) { fputs ("ge", file); return; }
1527 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1528 else if (rtxcode == LE) { fputs ("le", file); return; }
1529 else if (rtxcode == LEU) { fputs ("le", file); return; }
1534 output_addr_const (file, x);
1544 /* Print a memory address as an operand to reference that memory location.
1546 This is exactly the same as legitimate_address_p, except that it the prints
1547 addresses instead of recognizing them. */
1550 i960_print_operand_addr (file, addr)
1562 if (GET_CODE (addr) == REG)
1564 else if (CONSTANT_P (addr))
1566 else if (GET_CODE (addr) == PLUS)
1570 op0 = XEXP (addr, 0);
1571 op1 = XEXP (addr, 1);
1573 if (GET_CODE (op0) == REG)
1576 if (GET_CODE (op1) == REG)
1578 else if (CONSTANT_P (op1))
1583 else if (GET_CODE (op0) == PLUS)
1585 if (GET_CODE (XEXP (op0, 0)) == MULT)
1587 ireg = XEXP (XEXP (op0, 0), 0);
1588 scale = XEXP (XEXP (op0, 0), 1);
1589 if (GET_CODE (XEXP (op0, 1)) == REG)
1591 breg = XEXP (op0, 1);
1597 else if (GET_CODE (XEXP (op0, 0)) == REG)
1599 breg = XEXP (op0, 0);
1600 if (GET_CODE (XEXP (op0, 1)) == REG)
1602 ireg = XEXP (op0, 1);
1611 else if (GET_CODE (op0) == MULT)
1613 ireg = XEXP (op0, 0);
1614 scale = XEXP (op0, 1);
1615 if (GET_CODE (op1) == REG)
1617 else if (CONSTANT_P (op1))
1625 else if (GET_CODE (addr) == MULT)
1627 ireg = XEXP (addr, 0);
1628 scale = XEXP (addr, 1);
1634 output_addr_const (file, offset);
1636 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1638 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1641 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1642 that is a valid memory address for an instruction.
1643 The MODE argument is the machine mode for the MEM expression
1644 that wants to use this address.
1646 On 80960, legitimate addresses are:
1648 disp (12 or 32 bit) ld foo,r0
1649 base + index ld (g0)[g1*1],r0
1650 base + displ ld 0xf00(g0),r0
1651 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1652 index*scale + base ld (g0)[g1*4],r0
1653 index*scale + displ ld 0xf00[g1*4],r0
1654 index*scale ld [g1*4],r0
1655 index + base + displ ld 0xf00(g0)[g1*1],r0
1657 In each case, scale can be 1, 2, 4, 8, or 16. */
1659 /* This is exactly the same as i960_print_operand_addr, except that
1660 it recognizes addresses instead of printing them.
1662 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1663 convert common non-canonical forms to canonical form so that they will
1666 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1667 where a register is valid. */
1669 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1670 ((GET_CODE (X) == REG \
1671 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1672 || (GET_CODE (X) == SUBREG \
1673 && GET_CODE (SUBREG_REG (X)) == REG \
1674 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1675 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1677 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1678 ((GET_CODE (X) == REG \
1679 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1680 || (GET_CODE (X) == SUBREG \
1681 && GET_CODE (SUBREG_REG (X)) == REG \
1682 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1683 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1686 legitimate_address_p (mode, addr, strict)
1687 enum machine_mode mode;
1691 if (RTX_OK_FOR_BASE_P (addr, strict))
1693 else if (CONSTANT_P (addr))
1695 else if (GET_CODE (addr) == PLUS)
1699 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1702 op0 = XEXP (addr, 0);
1703 op1 = XEXP (addr, 1);
1705 if (RTX_OK_FOR_BASE_P (op0, strict))
1707 if (RTX_OK_FOR_INDEX_P (op1, strict))
1709 else if (CONSTANT_P (op1))
1714 else if (GET_CODE (op0) == PLUS)
1716 if (GET_CODE (XEXP (op0, 0)) == MULT)
1718 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
1719 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
1722 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
1723 && CONSTANT_P (op1))
1728 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
1730 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
1731 && CONSTANT_P (op1))
1739 else if (GET_CODE (op0) == MULT)
1741 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
1742 && SCALE_TERM_P (XEXP (op0, 1))))
1745 if (RTX_OK_FOR_BASE_P (op1, strict))
1747 else if (CONSTANT_P (op1))
1755 else if (GET_CODE (addr) == MULT)
1757 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1760 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
1761 && SCALE_TERM_P (XEXP (addr, 1)));
1767 /* Try machine-dependent ways of modifying an illegitimate address
1768 to be legitimate. If we find one, return the new, valid address.
1769 This macro is used in only one place: `memory_address' in explow.c.
1771 This converts some non-canonical addresses to canonical form so they
1772 can be recognized. */
1775 legitimize_address (x, oldx, mode)
1778 enum machine_mode mode;
1780 if (GET_CODE (x) == SYMBOL_REF)
1783 x = copy_to_reg (x);
1786 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1789 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1790 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1791 created by virtual register instantiation, register elimination, and
1792 similar optimizations. */
1793 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1794 && GET_CODE (XEXP (x, 1)) == PLUS)
1795 x = gen_rtx (PLUS, Pmode,
1796 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
1797 XEXP (XEXP (x, 1), 1));
1799 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1800 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1801 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
1802 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1803 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
1804 && CONSTANT_P (XEXP (x, 1)))
1806 rtx constant, other;
1808 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1810 constant = XEXP (x, 1);
1811 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
1813 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
1815 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
1816 other = XEXP (x, 1);
1822 x = gen_rtx (PLUS, Pmode,
1823 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
1824 XEXP (XEXP (XEXP (x, 0), 1), 0)),
1825 plus_constant (other, INTVAL (constant)));
1832 /* Return the most stringent alignment that we are willing to consider
1833 objects of size SIZE and known alignment ALIGN as having. */
1836 i960_alignment (size, align)
1842 if (! TARGET_STRICT_ALIGN)
1843 if (TARGET_IC_COMPAT2_0 || align >= 4)
1845 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1854 /* Modes for condition codes. */
1856 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1858 /* Modes for single-word (and smaller) quantities. */
1861 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1862 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1864 /* Modes for double-word (and smaller) quantities. */
1867 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1869 /* Modes for quad-word quantities. */
1870 #define T_MODES (~C_MODES)
1872 /* Modes for single-float quantities. */
1873 #define SF_MODES ((1 << (int) SFmode))
1875 /* Modes for double-float quantities. */
1876 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1878 /* Modes for quad-float quantities. */
1879 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1881 unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
1882 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1883 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1884 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1885 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1887 TF_MODES, TF_MODES, TF_MODES, TF_MODES, C_MODES};
1890 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1891 advantage of machine specific facts, such as knowing that the frame pointer
1892 is always 16 byte aligned. */
1895 i960_expr_alignment (x, size)
1904 switch (GET_CODE(x))
1909 if ((align & 0xf) == 0)
1911 else if ((align & 0x7) == 0)
1913 else if ((align & 0x3) == 0)
1915 else if ((align & 0x1) == 0)
1922 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
1923 i960_expr_alignment (XEXP (x, 1), size));
1927 /* If this is a valid program, objects are guaranteed to be
1928 correctly aligned for whatever size the reference actually is. */
1929 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1933 if (REGNO (x) == FRAME_POINTER_REGNUM)
1938 align = i960_expr_alignment (XEXP (x, 0));
1940 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1942 align = align << INTVAL (XEXP (x, 1));
1943 align = MIN (align, 16);
1948 align = (i960_expr_alignment (XEXP (x, 0), size) *
1949 i960_expr_alignment (XEXP (x, 1), size));
1951 align = MIN (align, 16);
1958 /* Return true if it is possible to reference both BASE and OFFSET, which
1959 have alignment at least as great as 4 byte, as if they had alignment valid
1960 for an object of size SIZE. */
1963 i960_improve_align (base, offset, size)
1970 /* We have at least a word reference to the object, so we know it has to
1971 be aligned at least to 4 bytes. */
1973 i = MIN (i960_expr_alignment (base, 4),
1974 i960_expr_alignment (offset, 4));
1978 /* We know the size of the request. If strict align is not enabled, we
1979 can guess that the alignment is OK for the requested size. */
1981 if (! TARGET_STRICT_ALIGN)
1982 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
1988 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1989 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1992 i960_si_ti (base, offset)
1996 return i960_improve_align (base, offset, 16);
1999 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2000 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2003 i960_si_di (base, offset)
2007 return i960_improve_align (base, offset, 8);
2010 /* Return raw values of size and alignment (in words) for the data
2011 type being accessed. These values will be rounded by the caller. */
2014 i960_arg_size_and_align (mode, type, size_out, align_out)
2015 enum machine_mode mode;
2022 /* Use formal alignment requirements of type being passed, except make
2023 it at least a word. If we don't have a type, this is a library call,
2024 and the parm has to be of scalar type. In this case, consider its
2025 formal alignment requirement to be its size in words. */
2027 if (mode == BLKmode)
2028 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2029 else if (mode == VOIDmode)
2031 /* End of parm list. */
2032 assert (type != 0 && TYPE_MODE (type) == VOIDmode);
2036 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2040 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2041 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2049 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2050 Any arg that is bigger than 4 words is placed on the stack and all
2051 subsequent arguments are placed on the stack.
2053 Additionally, parameters with an alignment requirement stronger than
2054 a word must be be aligned appropriately. */
2056 /* Update CUM to advance past an argument described by MODE and TYPE. */
2059 i960_function_arg_advance (cum, mode, type, named)
2060 CUMULATIVE_ARGS *cum;
2061 enum machine_mode mode;
2067 i960_arg_size_and_align (mode, type, &size, &align);
2069 if (size > 4 || cum->ca_nstackparms != 0
2070 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2071 || MUST_PASS_IN_STACK (mode, type))
2072 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2074 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2077 /* Return the register that the argument described by MODE and TYPE is
2078 passed in, or else return 0 if it is passed on the stack. */
2081 i960_function_arg (cum, mode, type, named)
2082 CUMULATIVE_ARGS *cum;
2083 enum machine_mode mode;
2090 i960_arg_size_and_align (mode, type, &size, &align);
2092 if (size > 4 || cum->ca_nstackparms != 0
2093 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2094 || MUST_PASS_IN_STACK (mode, type))
2096 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2101 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2102 ret = gen_rtx (REG, mode, cum->ca_nregparms);
2108 /* Floating-point support. */
2111 i960_output_double (file, value)
2115 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
2117 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
2119 fprintf (file, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
2120 value_long[0], value, value_long[1]);
2122 if (REAL_VALUE_ISINF (value))
2124 fprintf (file, "\t.word 0\n");
2125 fprintf (file, "\t.word 0x7ff00000 # Infinity\n");
2128 fprintf (file, "\t.double 0d%.17e\n", (value));
2133 i960_output_float (file, value)
2137 #ifdef REAL_VALUE_TO_TARGET_SINGLE
2139 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
2141 fprintf (file, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
2143 if (REAL_VALUE_ISINF (value))
2144 fprintf (file, "\t.word 0x7f800000 # Infinity\n");
2146 fprintf (file, "\t.float 0f%.12e\n", (value));
2150 /* Return the number of bits that an object of size N bytes is aligned to. */
2153 i960_object_bytes_bitalign (n)
2157 else if (n > 4) n = 64;
2158 else if (n > 2) n = 32;
2159 else if (n > 1) n = 16;
2165 /* Compute the alignment for an aggregate type TSIZE.
2166 Alignment is MAX (greatest member alignment,
2167 MIN (pragma align, structure size alignment)). */
2170 i960_round_align (align, tsize)
2176 if (TREE_CODE (tsize) != INTEGER_CST)
2179 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2181 /* Handle #pragma align. */
2182 if (new_align > i960_maxbitalignment)
2183 new_align = i960_maxbitalignment;
2185 if (align < new_align)
2191 /* Do any needed setup for a varargs function. For the i960, we must
2192 create a register parameter block if one doesn't exist, and then copy
2193 all register parameters to memory. */
2196 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2197 CUMULATIVE_ARGS *cum;
2198 enum machine_mode mode;
2203 if (cum->ca_nregparms < NPARM_REGS)
2205 int first_reg_offset = cum->ca_nregparms;
2209 rtx label = gen_label_rtx ();
2212 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2213 and we need to allocate a chunk to save the registers (if any
2214 arguments were passed on the stack the caller would allocate the
2215 48 bytes as well). We must allocate all 48 bytes (12*4) because
2216 arg_pointer_rtx is saved at the front, the anonymous args are
2217 saved at the end. */
2218 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2219 emit_jump_insn (gen_bne (label));
2220 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
2221 stack_pointer_rtx));
2222 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
2223 memory_address (SImode,
2224 plus_constant (stack_pointer_rtx,
2228 /* Any anonymous args passed in regs? */
2229 if (first_reg_offset + 1 < NPARM_REGS)
2232 regblock = gen_rtx (MEM, BLKmode,
2233 plus_constant (arg_pointer_rtx,
2234 (first_reg_offset + 1) * 4));
2235 move_block_from_reg (first_reg_offset + 1, regblock,
2236 NPARM_REGS - first_reg_offset - 1,
2237 ((NPARM_REGS - first_reg_offset - 1)
2244 /* Calculate the final size of the reg parm stack space for the current
2245 function, based on how many bytes would be allocated on the stack. */
2248 i960_final_reg_parm_stack_space (const_size, var_size)
2252 if (var_size || const_size > 48)
2258 /* Calculate the size of the reg parm stack space. This is a bit complicated
2262 i960_reg_parm_stack_space (fndecl)
2265 /* In this case, we are called from emit_library_call, and we don't need
2266 to pretend we have more space for parameters than what's apparent. */
2270 /* In this case, we are called from locate_and_pad_parms when we're
2271 not IN_REGS, so we have an arg block. */
2272 if (fndecl != current_function_decl)
2275 /* Otherwise, we have an arg block if the current function has more than
2276 48 bytes of parameters. */
2277 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2283 /* Return the register class of a scratch register needed to copy IN into
2284 or out of a register in CLASS in MODE. If it can be done directly,
2285 NO_REGS is returned. */
2288 secondary_reload_class (class, mode, in)
2289 enum reg_class class;
2290 enum machine_mode mode;
2295 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2296 regno = true_regnum (in);
2298 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2299 LOCAL_OR_GLOBAL_REGS into anything. */
2300 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2301 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2304 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2305 if (class == FP_REGS
2306 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2307 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2310 return LOCAL_OR_GLOBAL_REGS;
2313 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2314 function unit it executed on. */
2316 /* ??? This would make more sense as an attribute. */
2319 i960_scan_opcode (p)
2331 /* Ret is not actually of type REG, but it won't matter, because no
2332 insn will ever follow it. */
2335 i960_last_insn_type = I_TYPE_REG;
2339 if (p[1] == 'x' || p[3] == 'x')
2340 i960_last_insn_type = I_TYPE_MEM;
2341 i960_last_insn_type = I_TYPE_CTRL;
2346 i960_last_insn_type = I_TYPE_CTRL;
2353 i960_last_insn_type = I_TYPE_MEM;
2355 i960_last_insn_type = I_TYPE_CTRL;
2357 else if (p[1] == 'm')
2360 i960_last_insn_type = I_TYPE_REG;
2361 else if (p[4] == 'b' || p[4] == 'j')
2362 i960_last_insn_type = I_TYPE_CTRL;
2364 i960_last_insn_type = I_TYPE_REG;
2367 i960_last_insn_type = I_TYPE_REG;
2371 i960_last_insn_type = I_TYPE_MEM;
2376 i960_last_insn_type = I_TYPE_MEM;
2378 i960_last_insn_type = I_TYPE_REG;