1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0, i960_compare_op1;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment;
53 static int i960_last_maxbitalignment;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label = 0;
79 /* Handle pragmas for compatibility with Intel's compilers. */
81 /* ??? This is incomplete, since it does not handle all pragmas that the
82 intel compilers understand. Also, it needs to be rewritten to accept
83 a stream instead of a string for GCC 2. */
92 if ((i = sscanf (str, " align %d", &align)) == 1)
95 case 0: /* Return to last alignment. */
96 align = i960_last_maxbitalignment / 8;
98 case 16: /* Byte alignments. */
103 i960_last_maxbitalignment = i960_maxbitalignment;
104 i960_maxbitalignment = align * 8;
107 default: /* Unknown, silently ignore. */
111 /* NOTE: ic960 R3.0 pragma align definition:
113 #pragma align [(size)] | (identifier=size[,...])
114 #pragma noalign [(identifier)[,...]]
116 (all parens are optional)
118 - size is [1,2,4,8,16]
119 - noalign means size==1
120 - applies only to component elements of a struct (and union?)
121 - identifier applies to structure tag (only)
122 - missing identifier means next struct
124 - alignment rules for bitfields need more investigation */
126 /* Should be pragma 'far' or equivalent for callx/balx here. */
130 /* Initialize variables before compiling any files. */
135 if (TARGET_IC_COMPAT2_0)
137 i960_maxbitalignment = 8;
138 i960_last_maxbitalignment = 128;
142 i960_maxbitalignment = 128;
143 i960_last_maxbitalignment = 8;
147 /* Return true if OP can be used as the source of an fp move insn. */
150 fpmove_src_operand (op, mode)
152 enum machine_mode mode;
154 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
158 /* Return true if OP is a register or zero. */
161 reg_or_zero_operand (op, mode)
163 enum machine_mode mode;
165 return register_operand (op, mode) || op == const0_rtx;
169 /* Return truth value of whether OP can be used as an operands in a three
170 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
173 arith_operand (op, mode)
175 enum machine_mode mode;
177 return (register_operand (op, mode) || literal (op, mode));
180 /* Return true if OP is a register or a valid floating point literal. */
183 fp_arith_operand (op, mode)
185 enum machine_mode mode;
187 return (register_operand (op, mode) || fp_literal (op, mode));
190 /* Return true is OP is a register or a valid signed integer literal. */
193 signed_arith_operand (op, mode)
195 enum machine_mode mode;
197 return (register_operand (op, mode) || signed_literal (op, mode));
200 /* Return truth value of whether OP is a integer which fits the
201 range constraining immediate operands in three-address insns. */
206 enum machine_mode mode;
208 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
211 /* Return true if OP is a float constant of 1. */
214 fp_literal_one (op, mode)
216 enum machine_mode mode;
218 return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op))
219 && (op == CONST1_RTX (mode)));
222 /* Return true if OP is a float constant of 0. */
225 fp_literal_zero (op, mode)
227 enum machine_mode mode;
229 return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op))
230 && (op == CONST0_RTX (mode)));
233 /* Return true if OP is a valid floating point literal. */
238 enum machine_mode mode;
240 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
243 /* Return true if OP is a valid signed immediate constant. */
246 signed_literal(op, mode)
248 enum machine_mode mode;
250 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
253 /* Return truth value of statement that OP is a symbolic memory
254 operand of mode MODE. */
257 symbolic_memory_operand (op, mode)
259 enum machine_mode mode;
261 if (GET_CODE (op) == SUBREG)
262 op = SUBREG_REG (op);
263 if (GET_CODE (op) != MEM)
266 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
267 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
270 /* Return truth value of whether OP is EQ or NE. */
275 enum machine_mode mode;
277 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
280 /* OP is an integer register or a constant. */
283 arith32_operand (op, mode)
285 enum machine_mode mode;
287 if (register_operand (op, mode))
289 return (CONSTANT_P (op));
292 /* Return true if OP is an integer constant which is a power of 2. */
295 power2_operand (op,mode)
297 enum machine_mode mode;
299 if (GET_CODE(op) != CONST_INT)
302 return exact_log2 (INTVAL (op)) >= 0;
305 /* If VAL has only one bit set, return the index of that bit. Otherwise
314 for (i = 0; val != 0; i++, val >>= 1)
326 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
327 The return value indicates how many consecutive non-zero bits exist
328 if this is a mask. This is the same as the next function, except that
329 it does not indicate what the start and stop bit positions are. */
335 register int start, end, i;
338 for (i = 0; val != 0; val >>= 1, i++)
348 /* Still looking for the first bit. */
352 /* We've seen the start of a bit sequence, and now a zero. There
353 must be more one bits, otherwise we would have exited the loop.
354 Therefore, it is not a mask. */
359 /* The bit string has ones from START to END bit positions only. */
360 return end - start + 1;
363 /* If VAL is a mask, then return nonzero, with S set to the starting bit
364 position and E set to the ending bit position of the mask. The return
365 value indicates how many consecutive bits exist in the mask. This is
366 the same as the previous function, except that it also indicates the
367 start and end bit positions of the mask. */
374 register int start, end, i;
378 for (i = 0; val != 0; val >>= 1, i++)
389 /* Still looking for the first bit. */
393 /* We've seen the start of a bit sequence, and now a zero. There
394 must be more one bits, otherwise we would have exited the loop.
395 Therefor, it is not a mask. */
404 /* The bit string has ones from START to END bit positions only. */
407 return ((start < 0) ? 0 : end - start + 1);
410 /* Return the machine mode to use for a comparison. */
413 select_cc_mode (op, x)
417 if (op == GTU || op == LTU || op == GEU || op == LEU)
422 /* X and Y are two things to compare using CODE. Emit the compare insn and
423 return the rtx for register 36 in the proper mode. */
426 gen_compare_reg (code, x, y)
431 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
432 enum machine_mode mode
433 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
437 if (! arith_operand (x, mode))
438 x = force_reg (SImode, x);
439 if (! arith_operand (y, mode))
440 y = force_reg (SImode, y);
443 cc_reg = gen_rtx (REG, ccmode, 36);
444 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
445 gen_rtx (COMPARE, ccmode, x, y)));
450 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
451 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
452 are 4. Indexed addresses are cost 6. */
454 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
457 i960_address_cost (x)
461 /* Handled before calling here. */
462 if (GET_CODE (x) == REG)
465 if (GET_CODE (x) == PLUS)
467 rtx base = XEXP (x, 0);
468 rtx offset = XEXP (x, 1);
470 if (GET_CODE (base) == SUBREG)
471 base = SUBREG_REG (base);
472 if (GET_CODE (offset) == SUBREG)
473 offset = SUBREG_REG (offset);
475 if (GET_CODE (base) == REG)
477 if (GET_CODE (offset) == REG)
479 if (GET_CODE (offset) == CONST_INT)
481 if ((unsigned)INTVAL (offset) < 2047)
485 if (CONSTANT_P (offset))
488 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
491 /* This is an invalid address. The return value doesn't matter, but
492 for convenience we make this more expensive than anything else. */
495 if (GET_CODE (x) == MULT)
498 /* Symbol_refs and other unrecognized addresses are cost 4. */
502 /* Emit insns to move operands[1] into operands[0].
504 Return 1 if we have written out everything that needs to be done to
505 do the move. Otherwise, return 0 and the caller will emit the move
509 emit_move_sequence (operands, mode)
511 enum machine_mode mode;
513 register rtx operand0 = operands[0];
514 register rtx operand1 = operands[1];
516 /* We can only store registers to memory. */
518 if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG)
519 operands[1] = force_reg (mode, operand1);
524 /* Emit insns to load a constant. Uses several strategies to try to use
525 as few insns as possible. */
528 i960_output_ldconst (dst, src)
529 register rtx dst, src;
532 register unsigned rsrc2;
533 enum machine_mode mode = GET_MODE (dst);
535 union { long l[2]; double d; } x;
537 operands[0] = operands[2] = dst;
538 operands[1] = operands[3] = src;
540 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
541 must be a ldconst insn. */
543 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
545 output_asm_insn ("ldconst %1,%0", operands);
548 else if (mode == DFmode)
552 if (fp_literal_zero (src, VOIDmode))
555 return "movrl %1,%0";
560 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
561 split_double (src, &first, &second);
563 output_asm_insn ("# ldconst %1,%0",operands);
565 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
567 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
569 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
570 operands[1] = second;
571 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
575 if (fp_literal_one (src, VOIDmode))
576 return "movrl 0f1.0,%0";
577 fatal ("inline double constants not supported on this host");
580 else if (mode == TImode)
582 /* ??? This is currently not handled at all. */
585 /* Note: lowest order word goes in lowest numbered reg. */
586 rsrc1 = INTVAL (src);
587 if (rsrc1 >= 0 && rsrc1 < 32)
590 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
591 /* Go pick up the low-order word. */
593 else if (mode == DImode)
595 rtx upperhalf, lowerhalf, xoperands[2];
598 if (GET_CODE (src) == CONST_DOUBLE)
600 upperhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (src));
601 lowerhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (src));
603 else if (GET_CODE (src) == CONST_INT)
606 upperhalf = INTVAL (src) < 0 ? constm1_rtx : const0_rtx;
611 /* Note: lowest order word goes in lowest numbered reg. */
612 /* Numbers from 0 to 31 can be handled with a single insn. */
613 rsrc1 = INTVAL (lowerhalf);
614 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
617 /* Output the upper half with a recursive call. */
618 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
619 xoperands[1] = upperhalf;
620 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
622 /* The lower word is emitted as normally. */
624 else if (mode == SFmode)
626 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
630 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
631 REAL_VALUE_TO_TARGET_SINGLE (d, value);
633 output_asm_insn ("# ldconst %1,%0",operands);
634 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
635 operands[1] = gen_rtx (CONST_INT, VOIDmode, value);
636 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
639 if (fp_literal_zero (src, VOIDmode))
640 return "movr 0f0.0,%0";
641 if (fp_literal_one (src, VOIDmode))
642 return "movr 0f1.0,%0";
643 fatal ("inline float constants not supported on this host");
649 rsrc1 = INTVAL (src);
655 else if (mode == HImode)
664 /* ldconst 0..31,X -> mov 0..31,X */
667 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
672 /* ldconst 32..63,X -> add 31,nn,X */
675 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
677 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31);
678 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
684 /* ldconst -1..-31 -> sub 0,0..31,X */
687 /* return 'sub -(%1),0,%0' */
688 operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1);
689 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
693 /* ldconst -32 -> not 31,X */
696 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1);
697 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
702 /* If const is a single bit. */
703 if (bitpos (rsrc1) >= 0)
705 operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1));
706 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
710 /* If const is a bit string of less than 6 bits (1..31 shifted). */
715 if (bitstr (rsrc1, &s, &e) < 6)
717 rsrc2 = ((unsigned int) rsrc1) >> s;
718 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2);
719 operands[2] = gen_rtx (CONST_INT, VOIDmode, s);
720 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
725 /* Unimplemented cases:
726 const is in range 0..31 but rotated around end of word:
727 ror 31,3,g0 -> ldconst 0xe0000003,g0
729 and any 2 instruction cases that might be worthwhile */
731 output_asm_insn ("ldconst %1,%0", operands);
735 /* Determine if there is an opportunity for a bypass optimization.
736 Bypass succeeds on the 960K* if the destination of the previous
737 instruction is the second operand of the current instruction.
738 Bypass always succeeds on the C*.
740 Return 1 if the pattern should interchange the operands.
742 CMPBR_FLAG is true if this is for a compare-and-branch insn.
743 OP1 and OP2 are the two source operands of a 3 operand insn. */
746 i960_bypass (insn, op1, op2, cmpbr_flag)
747 register rtx insn, op1, op2;
750 register rtx prev_insn, prev_dest;
755 /* Can't do this if op1 isn't a register. */
759 /* Can't do this for a compare-and-branch if both ops aren't regs. */
760 if (cmpbr_flag && ! REG_P (op2))
763 prev_insn = prev_real_insn (insn);
765 if (prev_insn && GET_CODE (prev_insn) == INSN
766 && GET_CODE (PATTERN (prev_insn)) == SET)
768 prev_dest = SET_DEST (PATTERN (prev_insn));
769 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
770 || (GET_CODE (prev_dest) == SUBREG
771 && GET_CODE (SUBREG_REG (prev_dest)) == REG
772 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
778 /* Output the code which declares the function name. This also handles
779 leaf routines, which have special requirements, and initializes some
783 i960_function_name_declare (file, name, fndecl)
792 /* Increment global return label. */
796 /* Compute whether tail calls and leaf routine optimizations can be performed
797 for this function. */
809 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
810 argblock, because argblock uses g14 implicitly. */
812 if (current_function_args_size != 0)
818 /* See if caller passes in an address to return value. */
820 if (aggregate_value_p (DECL_RESULT (fndecl)))
826 /* Can not use tail calls or make this a leaf routine if there is a non
829 if (get_frame_size () != 0)
832 /* I don't understand this condition, and do not think that it is correct.
833 Apparently this is just checking whether the frame pointer is used, and
834 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
837 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
838 if (GET_CODE (insn) == INSN
839 && reg_mentioned_p (frame_pointer_rtx, insn))
845 /* Check for CALL insns. Can not be a leaf routine if there are any. */
848 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
849 if (GET_CODE (insn) == CALL_INSN)
855 /* Can not be a leaf routine if any non-call clobbered registers are
856 used in this function. */
859 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
860 if (regs_ever_live[i]
861 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
863 /* Global registers. */
864 if (i < 16 && i > 7 && i != 13)
866 /* Local registers. */
871 /* Now choose a leaf return register, if we can find one, and if it is
872 OK for this to be a leaf routine. */
874 i960_leaf_ret_reg = -1;
876 if (optimize && leaf_proc_ok)
878 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
879 if (regs_ever_live[i] == 0)
881 i960_leaf_ret_reg = i;
882 regs_ever_live[i] = 1;
887 /* Do this after choosing the leaf return register, so it will be listed
888 if one was chosen. */
890 fprintf (file, "\t# Function '%s'\n", name);
891 fprintf (file, "\t# Registers used: ");
893 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
895 if (regs_ever_live[i])
897 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
899 if (i > 15 && j == 0)
901 fprintf (file,"\n\t#\t\t ");
907 fprintf (file, "\n");
909 if (i960_leaf_ret_reg >= 0)
911 /* Make it a leaf procedure. */
913 if (TREE_PUBLIC (fndecl))
914 fprintf (file,"\t.globl %s.lf\n", name);
916 fprintf (file, "\t.leafproc\t_%s,%s.lf\n", name, name);
917 fprintf (file, "_%s:\n", name);
918 fprintf (file, "\tlda LR%d,g14\n", ret_label);
919 fprintf (file, "%s.lf:\n", name);
920 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
924 fprintf (file, "\tlda 0,g14\n");
925 i960_last_insn_type = I_TYPE_MEM;
929 fprintf (file, "\tmov 0,g14\n");
930 i960_last_insn_type = I_TYPE_REG;
935 ASM_OUTPUT_LABEL (file, name);
936 i960_last_insn_type = I_TYPE_CTRL;
940 /* Compute and return the frame size. */
943 compute_frame_size (size)
947 int outgoing_args_size
948 = current_function_outgoing_args_size + current_function_pretend_args_size;
950 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
951 as size is concerned. */
952 actual_fsize = (size + 15) & -16;
953 actual_fsize += (outgoing_args_size + 15) & -16;
958 /* Output code for the function prologue. */
961 i960_function_prologue (file, size)
965 register int i, j, nr;
968 int actual_fsize, offset;
970 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
972 int regs[FIRST_PSEUDO_REGISTER];
974 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
975 if (regs_ever_live[i]
976 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
979 /* Count global registers that need saving. */
986 epilogue_string[0] = '\0';
988 /* First look for local registers to save globals in. */
989 for (i = 0; i < 16; i++)
994 /* Start at r4, not r3. */
995 for (j = 20; j < 32; j++)
1002 regs_ever_live[j] = 1;
1004 if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0
1005 && regs[i+1] != 0 && regs[j+1] == 0)
1010 regs_ever_live[j+1] = 1;
1012 if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0
1013 && regs[i+2] != 0 && regs[j+2] == 0)
1018 regs_ever_live[j+2] = 1;
1020 if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0)
1025 regs_ever_live[j+3] = 1;
1028 fprintf (file, "\tmov%s %s,%s\n",
1031 (nr == 2) ? "l" : ""),
1032 reg_names[i], reg_names[j]);
1033 sprintf (tmpstr, "\tmov%s %s,%s\n",
1036 (nr == 2) ? "l" : ""),
1037 reg_names[j], reg_names[i]);
1038 strcat (epilogue_string, tmpstr);
1046 /* N_iregs is now the number of global registers that haven't been saved
1049 rsize = (n_iregs * 4);
1050 actual_fsize = compute_frame_size (size) + rsize;
1052 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1053 size up to the nearest multiple of 16. I don't know whether this is
1054 necessary, or even desirable.
1056 The frame pointer must be aligned, but the call instruction takes care of
1057 that. If we leave the stack pointer unaligned, we may save a little on
1058 dynamic stack allocation. And we don't lose, at least according to the
1060 actual_fsize = (actual_fsize + 15) & ~0xF;
1063 /* Allocate space for register save and locals. */
1064 if (actual_fsize > 0)
1066 if (actual_fsize < 32)
1067 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1069 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1072 /* Take hardware register save area created by the call instruction
1074 offset = compute_frame_size (size) + 64;
1075 /* Save registers on stack if needed. */
1076 for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
1083 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1086 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1090 if (nr == 3 && regs[i+3] == -1)
1093 fprintf (file,"\tst%s %s,%d(fp)\n",
1096 (nr == 2) ? "l" : ""),
1097 reg_names[i], offset);
1098 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1101 (nr == 2) ? "l" : ""),
1102 offset, reg_names[i]);
1103 strcat (epilogue_string, tmpstr);
1109 if (actual_fsize == 0 && size == 0 && rsize == 0)
1112 fprintf (file, "\t#Prologue stats:\n");
1113 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1116 fprintf (file, "\t# Local Variable Size: %d bytes\n", size);
1118 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1120 fprintf (file, "\t#End Prologue#\n");
1123 /* Output code for the function epilogue. */
1126 i960_function_epilogue (file, size)
1130 if (i960_leaf_ret_reg >= 0)
1132 fprintf (file, "LR%d: ret\n", ret_label);
1136 if (*epilogue_string == 0)
1140 /* Emit a return insn, but only if control can fall through to here. */
1142 tmp = get_last_insn ();
1145 if (GET_CODE (tmp) == BARRIER)
1147 if (GET_CODE (tmp) == CODE_LABEL)
1149 if (GET_CODE (tmp) == JUMP_INSN)
1151 if (GET_CODE (PATTERN (tmp)) == RETURN)
1155 if (GET_CODE (tmp) == NOTE)
1157 tmp = PREV_INSN (tmp);
1162 fprintf (file, "LR%d: ret\n", ret_label);
1166 fprintf (file, "LR%d:\n", ret_label);
1168 fprintf (file, "\t#EPILOGUE#\n");
1170 /* Output the string created by the prologue which will restore all
1171 registers saved by the prologue. */
1173 if (epilogue_string[0] != '\0')
1174 fprintf (file, "%s", epilogue_string);
1176 /* Must clear g14 on return. */
1178 if (current_function_args_size != 0)
1179 fprintf (file, "\tmov 0,g14\n");
1181 fprintf (file, "\tret\n");
1182 fprintf (file, "\t#End Epilogue#\n");
1185 /* Output code for a call insn. */
1188 i960_output_call_insn (target, argsize_rtx, arg_pointer, scratch_reg, insn)
1189 register rtx target, argsize_rtx, arg_pointer, scratch_reg, insn;
1191 int argsize = INTVAL (argsize_rtx);
1192 rtx nexti = next_real_insn (insn);
1195 operands[0] = target;
1196 operands[1] = arg_pointer;
1197 operands[2] = scratch_reg;
1199 if (current_function_args_size != 0)
1200 output_asm_insn ("mov g14,%2", operands);
1203 output_asm_insn ("lda %a1,g14", operands);
1204 else if (current_function_args_size != 0)
1205 output_asm_insn ("mov 0,g14", operands);
1207 /* The code used to assume that calls to SYMBOL_REFs could not be more
1208 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1209 feature is now implemented by relaxing in the GNU linker. It can convert
1210 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1212 /* Nexti could be zero if the called routine is volatile. */
1213 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1214 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1216 /* Delete following return insn. */
1217 if (nexti && no_labels_between_p (insn, nexti))
1218 delete_insn (nexti);
1219 output_asm_insn ("bx %0", operands);
1220 return "# notreached";
1223 output_asm_insn ("callx %0", operands);
1225 if (current_function_args_size != 0)
1226 output_asm_insn ("mov %2,g14", operands);
1231 /* Output code for a return insn. */
1234 i960_output_ret_insn (insn)
1237 static char lbuf[20];
1239 if (*epilogue_string != 0)
1241 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1244 sprintf (lbuf, "b LR%d", ret_label);
1248 if (current_function_args_size != 0)
1249 output_asm_insn ("mov 0,g14", 0);
1251 if (i960_leaf_ret_reg >= 0)
1253 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1260 /* Return a character string representing the branch prediction
1261 opcode to be tacked on an instruction. This must at least
1262 return a null string. */
1265 i960_br_predict_opcode (lab_ref, insn)
1268 if (TARGET_BRANCH_PREDICT)
1270 unsigned long label_uid;
1272 if (GET_CODE (lab_ref) == CODE_LABEL)
1273 label_uid = INSN_UID (lab_ref);
1274 else if (GET_CODE (lab_ref) == LABEL_REF)
1275 label_uid = INSN_UID (XEXP (lab_ref, 0));
1279 /* If not optimizing, then the insn_addresses array will not be
1280 valid. In this case, always return ".t" since most branches
1281 are taken. If optimizing, return .t for backward branches
1282 and .f for forward branches. */
1284 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1293 /* Print the operand represented by rtx X formatted by code CODE. */
1296 i960_print_operand (file, x, code)
1301 enum rtx_code rtxcode = GET_CODE (x);
1308 /* Second reg of a double. */
1309 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1313 fprintf (file, "%s", reg_names[REGNO (x)]);
1321 else if (rtxcode == MEM)
1323 output_address (XEXP (x, 0));
1326 else if (rtxcode == CONST_INT)
1328 if (INTVAL (x) > 9999 || INTVAL (x) < -999)
1329 fprintf (file, "0x%x", INTVAL (x));
1331 fprintf (file, "%d", INTVAL (x));
1334 else if (rtxcode == CONST_DOUBLE)
1338 if (x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1340 fprintf (file, "0f0.0");
1343 else if (x == CONST1_RTX (DFmode) || x == CONST1_RTX (SFmode))
1345 fprintf (file, "0f1.0");
1349 /* This better be a comment. */
1350 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1351 fprintf (file, "%#g", d);
1358 /* Branch or jump, depending on assembler. */
1359 if (TARGET_ASM_COMPAT)
1366 /* Sign of condition. */
1367 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1368 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1370 else if ((rtxcode == GT) || (rtxcode == LT)
1371 || (rtxcode == GE) || (rtxcode == LE))
1378 /* Inverted condition. */
1379 rtxcode = reverse_condition (rtxcode);
1383 /* Inverted condition w/ reversed operands. */
1384 rtxcode = reverse_condition (rtxcode);
1388 /* Reversed operand condition. */
1389 rtxcode = swap_condition (rtxcode);
1393 /* Normal condition. */
1395 if (rtxcode == EQ) { fputs ("e", file); return; }
1396 else if (rtxcode == NE) { fputs ("ne", file); return; }
1397 else if (rtxcode == GT) { fputs ("g", file); return; }
1398 else if (rtxcode == GTU) { fputs ("g", file); return; }
1399 else if (rtxcode == LT) { fputs ("l", file); return; }
1400 else if (rtxcode == LTU) { fputs ("l", file); return; }
1401 else if (rtxcode == GE) { fputs ("ge", file); return; }
1402 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1403 else if (rtxcode == LE) { fputs ("le", file); return; }
1404 else if (rtxcode == LEU) { fputs ("le", file); return; }
1409 output_addr_const (file, x);
1419 /* Print a memory address as an operand to reference that memory location.
1421 This is exactly the same as legitimate_address_p, except that it the prints
1422 addresses instead of recognizing them. */
1425 i960_print_operand_addr (file, addr)
1437 if (GET_CODE (addr) == REG)
1439 else if (CONSTANT_P (addr))
1441 else if (GET_CODE (addr) == PLUS)
1445 op0 = XEXP (addr, 0);
1446 op1 = XEXP (addr, 1);
1448 if (GET_CODE (op0) == REG)
1451 if (GET_CODE (op1) == REG)
1453 else if (CONSTANT_P (op1))
1458 else if (GET_CODE (op0) == PLUS)
1460 if (GET_CODE (XEXP (op0, 0)) == MULT)
1462 ireg = XEXP (XEXP (op0, 0), 0);
1463 scale = XEXP (XEXP (op0, 0), 1);
1464 if (GET_CODE (XEXP (op0, 1)) == REG)
1466 breg = XEXP (op0, 1);
1472 else if (GET_CODE (XEXP (op0, 0)) == REG)
1474 breg = XEXP (op0, 0);
1475 if (GET_CODE (XEXP (op0, 1)) == REG)
1477 ireg = XEXP (op0, 1);
1486 else if (GET_CODE (op0) == MULT)
1488 ireg = XEXP (op0, 0);
1489 scale = XEXP (op0, 1);
1490 if (GET_CODE (op1) == REG)
1492 else if (CONSTANT_P (op1))
1500 else if (GET_CODE (addr) == MULT)
1502 breg = XEXP (addr, 0);
1503 scale = XEXP (addr, 1);
1509 output_addr_const (file, offset);
1511 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1513 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1516 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1517 that is a valid memory address for an instruction.
1518 The MODE argument is the machine mode for the MEM expression
1519 that wants to use this address.
1521 On 80960, legitimate addresses are:
1523 disp (12 or 32 bit) ld foo,r0
1524 base + index ld (g0)[g1*1],r0
1525 base + displ ld 0xf00(g0),r0
1526 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1527 index*scale + base ld (g0)[g1*4],r0
1528 index*scale + displ ld 0xf00[g1*4],r0
1529 index*scale ld [g1*4],r0
1530 index + base + displ ld 0xf00(g0)[g1*1],r0
1532 In each case, scale can be 1, 2, 4, 8, or 16. */
1534 /* This is exactly the same as i960_print_operand_addr, except that
1535 it recognizes addresses instead of printing them.
1537 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1538 convert common non-canonical forms to canonical form so that they will
1542 legitimate_address_p (mode, addr, strict)
1543 enum machine_mode mode;
1547 if (GET_CODE (addr) == REG)
1548 return (strict ? REG_OK_FOR_BASE_P_STRICT (addr)
1549 : REG_OK_FOR_BASE_P (addr));
1550 else if (CONSTANT_P (addr))
1552 else if (GET_CODE (addr) == PLUS)
1556 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1559 op0 = XEXP (addr, 0);
1560 op1 = XEXP (addr, 1);
1562 if (GET_CODE (op0) == REG)
1564 if (! (strict ? REG_OK_FOR_BASE_P_STRICT (op0)
1565 : REG_OK_FOR_BASE_P (op0)))
1568 if (GET_CODE (op1) == REG)
1569 return (strict ? REG_OK_FOR_INDEX_P_STRICT (op1)
1570 : REG_OK_FOR_INDEX_P (op1));
1571 else if (CONSTANT_P (op1))
1576 else if (GET_CODE (op0) == PLUS)
1578 if (GET_CODE (XEXP (op0, 0)) == MULT)
1580 if (! (GET_CODE (XEXP (XEXP (op0, 0), 0)) == REG
1581 && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (XEXP (op0, 0), 0))
1582 : REG_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0)))
1583 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
1586 if (GET_CODE (XEXP (op0, 1)) == REG)
1587 return ((strict ? REG_OK_FOR_BASE_P_STRICT (XEXP (op0, 1))
1588 : REG_OK_FOR_BASE_P (XEXP (op0, 1)))
1589 && CONSTANT_P (op1));
1593 else if (GET_CODE (XEXP (op0, 0)) == REG)
1595 if (! (strict ? REG_OK_FOR_BASE_P_STRICT (XEXP (op0, 0))
1596 : REG_OK_FOR_BASE_P (XEXP (op0, 0))))
1599 if (GET_CODE (XEXP (op0, 1)) == REG)
1600 return ((strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0, 1))
1601 : REG_OK_FOR_INDEX_P (XEXP (op0, 1)))
1602 && CONSTANT_P (op1));
1609 else if (GET_CODE (op0) == MULT)
1611 if (! (GET_CODE (XEXP (op0, 0)) == REG
1612 && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (op0, 0))
1613 : REG_OK_FOR_INDEX_P (XEXP (op0, 0)))
1614 && SCALE_TERM_P (XEXP (op0, 1))))
1617 if (GET_CODE (op1) == REG)
1618 return (strict ? REG_OK_FOR_BASE_P_STRICT (op1)
1619 : REG_OK_FOR_BASE_P (op1));
1620 else if (CONSTANT_P (op1))
1628 else if (GET_CODE (addr) == MULT)
1630 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1633 return (GET_CODE (XEXP (addr, 0)) == REG
1634 && (strict ? REG_OK_FOR_INDEX_P_STRICT (XEXP (addr, 0))
1635 : REG_OK_FOR_INDEX_P (XEXP (addr, 0)))
1636 && SCALE_TERM_P (XEXP (addr, 1)));
1642 /* Try machine-dependent ways of modifying an illegitimate address
1643 to be legitimate. If we find one, return the new, valid address.
1644 This macro is used in only one place: `memory_address' in explow.c.
1646 This converts some non-canonical addresses to canonical form so they
1647 can be recognized. */
1650 legitimize_address (x, oldx, mode)
1653 enum machine_mode mode;
1655 if (GET_CODE (x) == SYMBOL_REF)
1658 x = copy_to_reg (x);
1661 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1664 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1665 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1666 created by virtual register instantiation, register elimination, and
1667 similar optimizations. */
1668 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1669 && GET_CODE (XEXP (x, 1)) == PLUS)
1670 x = gen_rtx (PLUS, Pmode,
1671 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
1672 XEXP (XEXP (x, 1), 1));
1674 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1675 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1676 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
1677 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1678 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
1679 && CONSTANT_P (XEXP (x, 1)))
1681 rtx constant, other;
1683 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1685 constant = XEXP (x, 1);
1686 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
1688 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
1690 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
1691 other = XEXP (x, 1);
1697 x = gen_rtx (PLUS, Pmode,
1698 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
1699 XEXP (XEXP (XEXP (x, 0), 1), 0)),
1700 plus_constant (other, INTVAL (constant)));
1707 /* Return the most stringent alignment that we are willing to consider
1708 objects of size SIZE and known alignment ALIGN as having. */
1711 i960_alignment (size, align)
1717 if (! TARGET_STRICT_ALIGN)
1718 if (TARGET_IC_COMPAT2_0 || align >= 4)
1720 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1729 /* Modes for condition codes. */
1731 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1733 /* Modes for single-word (and smaller) quantities. */
1736 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1737 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1739 /* Modes for double-word (and smaller) quantities. */
1742 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1744 /* Modes for quad-word quantities. */
1745 #define T_MODES (~C_MODES)
1747 /* Modes for single-float quantities. */
1748 #define SF_MODES ((1 << (int) SFmode))
1750 /* Modes for double-float quantities. */
1751 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1753 /* Modes for quad-float quantities. */
1754 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1756 unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
1757 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1758 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1759 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1760 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1762 TF_MODES, TF_MODES, TF_MODES, TF_MODES, C_MODES};
1765 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1766 advantage of machine specific facts, such as knowing that the frame pointer
1767 is always 16 byte aligned. */
1770 i960_expr_alignment (x, size)
1779 switch (GET_CODE(x))
1784 if ((align & 0xf) == 0)
1786 else if ((align & 0x7) == 0)
1788 else if ((align & 0x3) == 0)
1790 else if ((align & 0x1) == 0)
1797 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
1798 i960_expr_alignment (XEXP (x, 1), size));
1802 /* If this is a valid program, objects are guaranteed to be
1803 correctly aligned for whatever size the reference actually is. */
1804 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1808 if (REGNO (x) == FRAME_POINTER_REGNUM)
1814 align = i960_expr_alignment (XEXP (x, 0));
1816 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1818 align = align << INTVAL (XEXP (x, 1));
1819 align = MIN (align, 16);
1824 align = (i960_expr_alignment (XEXP (x, 0), size) *
1825 i960_expr_alignment (XEXP (x, 1), size));
1827 align = MIN (align, 16);
1834 /* Return true if it is possible to reference both BASE and OFFSET, which
1835 have alignment at least as great as 4 byte, as if they had alignment valid
1836 for an object of size SIZE. */
1839 i960_improve_align (base, offset, size)
1846 /* We have at least a word reference to the object, so we know it has to
1847 be aligned at least to 4 bytes. */
1849 i = MIN (i960_expr_alignment (base, 4),
1850 i960_expr_alignment (offset, 4));
1854 /* We know the size of the request. If strict align is not enabled, we
1855 can guess that the alignment is OK for the requested size. */
1857 if (! TARGET_STRICT_ALIGN)
1858 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
1864 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1865 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1868 i960_si_ti (base, offset)
1872 return i960_improve_align (base, offset, 16);
1875 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1876 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1879 i960_si_di (base, offset)
1883 return i960_improve_align (base, offset, 8);
1886 /* Return raw values of size and alignment (in words) for the data
1887 type being accessed. These values will be rounded by the caller. */
1890 i960_arg_size_and_align (mode, type, size_out, align_out)
1891 enum machine_mode mode;
1898 /* Use formal alignment requirements of type being passed, except make
1899 it at least a word. If we don't have a type, this is a library call,
1900 and the parm has to be of scalar type. In this case, consider its
1901 formal alignment requirement to be its size in words. */
1903 if (mode == BLKmode)
1904 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1905 else if (mode == VOIDmode)
1907 /* End of parm list. */
1908 assert (type != 0 && TYPE_MODE (type) == VOIDmode);
1912 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1916 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
1917 align = TYPE_ALIGN (type) / BITS_PER_WORD;
1925 /* On the 80960 the first 12 args are in registers and the rest are pushed.
1926 Any arg that is bigger than 4 words is placed on the stack and all
1927 subsequent arguments are placed on the stack.
1929 Additionally, parameters with an alignment requirement stronger than
1930 a word must be be aligned appropriately. */
1932 /* Update CUM to advance past an argument described by MODE and TYPE. */
1935 i960_function_arg_advance (cum, mode, type, named)
1936 CUMULATIVE_ARGS *cum;
1937 enum machine_mode mode;
1943 i960_arg_size_and_align (mode, type, &size, &align);
1945 if (named == 0 || size > 4 || cum->ca_nstackparms != 0
1946 || (size + ROUND (cum->ca_nregparms, align)) > NPARM_REGS
1947 || MUST_PASS_IN_STACK (mode, type))
1948 cum->ca_nstackparms = ROUND (cum->ca_nstackparms, align) + size;
1950 cum->ca_nregparms = ROUND (cum->ca_nregparms, align) + size;
1953 /* Return the register that the argument described by MODE and TYPE is
1954 passed in, or else return 0 if it is passed on the stack. */
1957 i960_function_arg (cum, mode, type, named)
1958 CUMULATIVE_ARGS *cum;
1959 enum machine_mode mode;
1966 i960_arg_size_and_align (mode, type, &size, &align);
1968 if (named == 0 || size > 4 || cum->ca_nstackparms != 0
1969 || (size + ROUND (cum->ca_nregparms, align)) > NPARM_REGS
1970 || MUST_PASS_IN_STACK (mode, type))
1972 cum->ca_nstackparms = ROUND (cum->ca_nstackparms, align);
1977 cum->ca_nregparms = ROUND (cum->ca_nregparms, align);
1978 ret = gen_rtx (REG, mode, cum->ca_nregparms);
1984 /* Floating-point support. */
1987 i960_output_double (file, value)
1991 if (REAL_VALUE_ISINF (value))
1993 fprintf (file, "\t.word 0\n");
1994 fprintf (file, "\t.word 0x7ff00000 # Infinity\n");
1997 fprintf (file, "\t.double 0d%.17e\n", (value));
2001 i960_output_float (file, value)
2005 if (REAL_VALUE_ISINF (value))
2006 fprintf (file, "\t.word 0x7f800000 # Infinity\n");
2008 fprintf (file, "\t.float 0f%.12e\n", (value));
2011 /* Return the number of bits that an object of size N bytes is aligned to. */
2014 i960_object_bytes_bitalign (n)
2018 else if (n > 4) n = 64;
2019 else if (n > 2) n = 32;
2020 else if (n > 1) n = 16;
2026 /* Compute the size of an aggregate type TSIZE. */
2029 i960_round_size (tsize)
2032 int size, byte_size, align;
2034 if (TREE_CODE (tsize) != INTEGER_CST)
2037 size = TREE_INT_CST_LOW (tsize);
2038 byte_size = (size + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
2039 align = i960_object_bytes_bitalign (byte_size);
2041 /* Handle #pragma align. */
2042 if (align > i960_maxbitalignment)
2043 align = i960_maxbitalignment;
2046 size = ((size / align) + 1) * align;
2048 return size_int (size);
2051 /* Compute the alignment for an aggregate type TSIZE. */
2054 i960_round_align (align, tsize)
2060 if (TREE_CODE (tsize) != INTEGER_CST)
2063 byte_size = (TREE_INT_CST_LOW (tsize) + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
2064 align = i960_object_bytes_bitalign (byte_size);
2068 /* Do any needed setup for a varargs function. For the i960, we must
2069 create a register parameter block if one doesn't exist, and then copy
2070 all register parameters to memory. */
2073 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2074 CUMULATIVE_ARGS *cum;
2075 enum machine_mode mode;
2080 if (cum->ca_nregparms < NPARM_REGS)
2082 int first_reg_offset = cum->ca_nregparms;
2084 if (first_reg_offset > NPARM_REGS)
2085 first_reg_offset = NPARM_REGS;
2087 if (! (no_rtl) && first_reg_offset != NPARM_REGS)
2089 rtx label = gen_label_rtx ();
2090 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2091 emit_jump_insn (gen_bne (label));
2092 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
2093 stack_pointer_rtx));
2094 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
2095 memory_address (SImode,
2096 plus_constant (stack_pointer_rtx,
2101 gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx),
2102 NPARM_REGS - first_reg_offset);
2104 *pretend_size = (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD;
2108 /* Calculate the final size of the reg parm stack space for the current
2109 function, based on how many bytes would be allocated on the stack. */
2112 i960_final_reg_parm_stack_space (const_size, var_size)
2116 if (var_size || const_size > 48)
2122 /* Calculate the size of the reg parm stack space. This is a bit complicated
2126 i960_reg_parm_stack_space (fndecl)
2129 /* In this case, we are called from emit_library_call, and we don't need
2130 to pretend we have more space for parameters than what's apparent. */
2134 /* In this case, we are called from locate_and_pad_parms when we're
2135 not IN_REGS, so we have an arg block. */
2136 if (fndecl != current_function_decl)
2139 /* Otherwise, we have an arg block if the current function has more than
2140 48 bytes of parameters. */
2141 if (current_function_args_size != 0)
2147 /* Return the register class of a scratch register needed to copy IN into
2148 or out of a register in CLASS in MODE. If it can be done directly,
2149 NO_REGS is returned. */
2152 secondary_reload_class (class, mode, in)
2153 enum reg_class class;
2154 enum machine_mode mode;
2159 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2160 regno = true_regnum (in);
2162 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2163 LOCAL_OR_GLOBAL_REGS into anything. */
2164 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2165 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2168 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2169 if (class == FP_REGS
2170 && ((regno >= 0 && regno <= FIRST_PSEUDO_REGISTER)
2171 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2174 return LOCAL_OR_GLOBAL_REGS;
2177 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2178 function unit it executed on. */
2180 /* ??? This would make more sense as an attribute. */
2183 i960_scan_opcode (p)
2195 /* Ret is not actually of type REG, but it won't matter, because no
2196 insn will ever follow it. */
2199 i960_last_insn_type = I_TYPE_REG;
2203 if (p[1] == 'x' || p[3] == 'x')
2204 i960_last_insn_type = I_TYPE_MEM;
2205 i960_last_insn_type = I_TYPE_CTRL;
2210 i960_last_insn_type = I_TYPE_CTRL;
2217 i960_last_insn_type = I_TYPE_MEM;
2219 i960_last_insn_type = I_TYPE_CTRL;
2221 else if (p[1] == 'm')
2224 i960_last_insn_type = I_TYPE_REG;
2225 else if (p[4] == 'b' || p[4] == 'j')
2226 i960_last_insn_type = I_TYPE_CTRL;
2228 i960_last_insn_type = I_TYPE_REG;
2231 i960_last_insn_type = I_TYPE_REG;
2235 i960_last_insn_type = I_TYPE_MEM;
2240 i960_last_insn_type = I_TYPE_MEM;
2242 i960_last_insn_type = I_TYPE_REG;