1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
45 /* Save the operands last given to a compare for use when we
46 generate a scc or bcc insn. */
48 rtx i960_compare_op0, i960_compare_op1;
50 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
53 static int i960_maxbitalignment;
54 static int i960_last_maxbitalignment;
56 /* Used to implement switching between MEM and ALU insn types, for better
57 C series performance. */
59 enum insn_types i960_last_insn_type;
61 /* The leaf-procedure return register. Set only if this is a leaf routine. */
63 static int i960_leaf_ret_reg;
65 /* True if replacing tail calls with jumps is OK. */
67 static int tail_call_ok;
69 /* A string containing a list of insns to emit in the epilogue so as to
70 restore all registers saved by the prologue. Created by the prologue
71 code as it saves registers away. */
73 char epilogue_string[1000];
75 /* A unique number (per function) for return labels. */
77 static int ret_label = 0;
79 /* This is true if FNDECL is either a varargs or a stdarg function.
80 This is used to help identify functions that use an argument block. */
82 #define VARARGS_STDARG_FUNCTION(FNDECL) \
83 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
84 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
85 || current_function_varargs)
87 /* Handle pragmas for compatibility with Intel's compilers. */
89 /* ??? This is incomplete, since it does not handle all pragmas that the
90 intel compilers understand. */
93 process_pragma (finput, c)
99 while (c == ' ' || c == '\t')
103 && getc (finput) == 'l'
104 && getc (finput) == 'i'
105 && getc (finput) == 'g'
106 && getc (finput) == 'n'
107 && ((c = getc (finput)) == ' ' || c == '\t' || c == '\n'))
113 while (c == ' ' || c == '\t')
117 while (c >= '0' && c <= '9')
119 if (s < buf + sizeof buf - 1)
129 /* Return to last alignment. */
130 align = i960_last_maxbitalignment / 8;
137 i960_last_maxbitalignment = i960_maxbitalignment;
138 i960_maxbitalignment = align * 8;
142 /* Silently ignore bad values. */
146 /* NOTE: ic960 R3.0 pragma align definition:
148 #pragma align [(size)] | (identifier=size[,...])
149 #pragma noalign [(identifier)[,...]]
151 (all parens are optional)
153 - size is [1,2,4,8,16]
154 - noalign means size==1
155 - applies only to component elements of a struct (and union?)
156 - identifier applies to structure tag (only)
157 - missing identifier means next struct
159 - alignment rules for bitfields need more investigation */
162 /* Should be pragma 'far' or equivalent for callx/balx here. */
164 while (c != '\n' && c != EOF)
169 /* Initialize variables before compiling any files. */
174 if (TARGET_IC_COMPAT2_0)
176 i960_maxbitalignment = 8;
177 i960_last_maxbitalignment = 128;
181 i960_maxbitalignment = 128;
182 i960_last_maxbitalignment = 8;
186 /* Return true if OP can be used as the source of an fp move insn. */
189 fpmove_src_operand (op, mode)
191 enum machine_mode mode;
193 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
197 /* Return true if OP is a register or zero. */
200 reg_or_zero_operand (op, mode)
202 enum machine_mode mode;
204 return register_operand (op, mode) || op == const0_rtx;
208 /* Return truth value of whether OP can be used as an operands in a three
209 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
212 arith_operand (op, mode)
214 enum machine_mode mode;
216 return (register_operand (op, mode) || literal (op, mode));
219 /* Return truth value of whether OP can be used as an operands in a three
220 address logic insn, possibly complementing OP, of mode MODE. */
223 logic_operand (op, mode)
225 enum machine_mode mode;
227 return (register_operand (op, mode)
228 || (GET_CODE (op) == CONST_INT
229 && INTVAL(op) >= -32 && INTVAL(op) < 32));
232 /* Return true if OP is a register or a valid floating point literal. */
235 fp_arith_operand (op, mode)
237 enum machine_mode mode;
239 return (register_operand (op, mode) || fp_literal (op, mode));
242 /* Return true is OP is a register or a valid signed integer literal. */
245 signed_arith_operand (op, mode)
247 enum machine_mode mode;
249 return (register_operand (op, mode) || signed_literal (op, mode));
252 /* Return truth value of whether OP is a integer which fits the
253 range constraining immediate operands in three-address insns. */
258 enum machine_mode mode;
260 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
263 /* Return true if OP is a float constant of 1. */
266 fp_literal_one (op, mode)
268 enum machine_mode mode;
270 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
273 /* Return true if OP is a float constant of 0. */
276 fp_literal_zero (op, mode)
278 enum machine_mode mode;
280 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
283 /* Return true if OP is a valid floating point literal. */
288 enum machine_mode mode;
290 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
293 /* Return true if OP is a valid signed immediate constant. */
296 signed_literal(op, mode)
298 enum machine_mode mode;
300 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
303 /* Return truth value of statement that OP is a symbolic memory
304 operand of mode MODE. */
307 symbolic_memory_operand (op, mode)
309 enum machine_mode mode;
311 if (GET_CODE (op) == SUBREG)
312 op = SUBREG_REG (op);
313 if (GET_CODE (op) != MEM)
316 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
317 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
320 /* Return truth value of whether OP is EQ or NE. */
325 enum machine_mode mode;
327 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
330 /* OP is an integer register or a constant. */
333 arith32_operand (op, mode)
335 enum machine_mode mode;
337 if (register_operand (op, mode))
339 return (CONSTANT_P (op));
342 /* Return true if OP is an integer constant which is a power of 2. */
345 power2_operand (op,mode)
347 enum machine_mode mode;
349 if (GET_CODE (op) != CONST_INT)
352 return exact_log2 (INTVAL (op)) >= 0;
355 /* Return true if OP is an integer constant which is the complement of a
359 cmplpower2_operand (op, mode)
361 enum machine_mode mode;
363 if (GET_CODE (op) != CONST_INT)
366 return exact_log2 (~ INTVAL (op)) >= 0;
369 /* If VAL has only one bit set, return the index of that bit. Otherwise
378 for (i = 0; val != 0; i++, val >>= 1)
390 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
391 The return value indicates how many consecutive non-zero bits exist
392 if this is a mask. This is the same as the next function, except that
393 it does not indicate what the start and stop bit positions are. */
399 register int start, end, i;
402 for (i = 0; val != 0; val >>= 1, i++)
412 /* Still looking for the first bit. */
416 /* We've seen the start of a bit sequence, and now a zero. There
417 must be more one bits, otherwise we would have exited the loop.
418 Therefore, it is not a mask. */
423 /* The bit string has ones from START to END bit positions only. */
424 return end - start + 1;
427 /* If VAL is a mask, then return nonzero, with S set to the starting bit
428 position and E set to the ending bit position of the mask. The return
429 value indicates how many consecutive bits exist in the mask. This is
430 the same as the previous function, except that it also indicates the
431 start and end bit positions of the mask. */
438 register int start, end, i;
442 for (i = 0; val != 0; val >>= 1, i++)
453 /* Still looking for the first bit. */
457 /* We've seen the start of a bit sequence, and now a zero. There
458 must be more one bits, otherwise we would have exited the loop.
459 Therefor, it is not a mask. */
468 /* The bit string has ones from START to END bit positions only. */
471 return ((start < 0) ? 0 : end - start + 1);
474 /* Return the machine mode to use for a comparison. */
477 select_cc_mode (op, x)
481 if (op == GTU || op == LTU || op == GEU || op == LEU)
486 /* X and Y are two things to compare using CODE. Emit the compare insn and
487 return the rtx for register 36 in the proper mode. */
490 gen_compare_reg (code, x, y)
495 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
496 enum machine_mode mode
497 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
501 if (! arith_operand (x, mode))
502 x = force_reg (SImode, x);
503 if (! arith_operand (y, mode))
504 y = force_reg (SImode, y);
507 cc_reg = gen_rtx (REG, ccmode, 36);
508 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
509 gen_rtx (COMPARE, ccmode, x, y)));
514 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
515 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
516 are 4. Indexed addresses are cost 6. */
518 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
521 i960_address_cost (x)
525 /* Handled before calling here. */
526 if (GET_CODE (x) == REG)
529 if (GET_CODE (x) == PLUS)
531 rtx base = XEXP (x, 0);
532 rtx offset = XEXP (x, 1);
534 if (GET_CODE (base) == SUBREG)
535 base = SUBREG_REG (base);
536 if (GET_CODE (offset) == SUBREG)
537 offset = SUBREG_REG (offset);
539 if (GET_CODE (base) == REG)
541 if (GET_CODE (offset) == REG)
543 if (GET_CODE (offset) == CONST_INT)
545 if ((unsigned)INTVAL (offset) < 2047)
549 if (CONSTANT_P (offset))
552 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
555 /* This is an invalid address. The return value doesn't matter, but
556 for convenience we make this more expensive than anything else. */
559 if (GET_CODE (x) == MULT)
562 /* Symbol_refs and other unrecognized addresses are cost 4. */
566 /* Emit insns to move operands[1] into operands[0].
568 Return 1 if we have written out everything that needs to be done to
569 do the move. Otherwise, return 0 and the caller will emit the move
573 emit_move_sequence (operands, mode)
575 enum machine_mode mode;
577 /* We can only store registers to memory. */
579 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
580 operands[1] = force_reg (mode, operands[1]);
582 /* Storing multi-word values in unaligned hard registers to memory may
583 require a scratch since we have to store them a register at a time and
584 adding 4 to the memory address may not yield a valid insn. */
585 /* ??? We don't always need the scratch, but that would complicate things.
587 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
588 && GET_CODE (operands[0]) == MEM
589 && GET_CODE (operands[1]) == REG
590 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
591 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
593 emit_insn (gen_rtx (PARALLEL, VOIDmode,
595 gen_rtx (SET, VOIDmode,
596 operands[0], operands[1]),
597 gen_rtx (CLOBBER, VOIDmode,
598 gen_rtx (SCRATCH, Pmode)))));
605 /* Output assembler to move a double word value. */
608 i960_output_move_double (dst, src)
613 if (GET_CODE (dst) == REG
614 && GET_CODE (src) == REG)
616 if ((REGNO (src) & 1)
617 || (REGNO (dst) & 1))
619 /* We normally copy the low-numbered register first. However, if
620 the second source register is the same as the first destination
621 register, we must copy in the opposite order. */
622 if (REGNO (src) + 1 == REGNO (dst))
623 return "mov %D1,%D0\n\tmov %1,%0";
625 return "mov %1,%0\n\tmov %D1,%D0";
630 else if (GET_CODE (dst) == REG
631 && GET_CODE (src) == CONST_INT
632 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
635 return "mov %1,%0\n\tmov 0,%D0";
639 else if (GET_CODE (dst) == REG
640 && GET_CODE (src) == MEM)
644 /* One can optimize a few cases here, but you have to be
645 careful of clobbering registers used in the address and
649 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 1);
650 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
651 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
652 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
658 else if (GET_CODE (dst) == MEM
659 && GET_CODE (src) == REG)
663 /* This is handled by emit_move_sequence so we shouldn't get here. */
672 /* Output assembler to move a quad word value. */
675 i960_output_move_quad (dst, src)
680 if (GET_CODE (dst) == REG
681 && GET_CODE (src) == REG)
683 if ((REGNO (src) & 3)
684 || (REGNO (dst) & 3))
686 /* We normally copy starting with the low numbered register.
687 However, if there is an overlap such that the first dest reg
688 is <= the last source reg but not < the first source reg, we
689 must copy in the opposite order. */
690 if (REGNO (dst) <= REGNO (src) + 3
691 && REGNO (dst) >= REGNO (src))
692 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
694 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
699 else if (GET_CODE (dst) == REG
700 && GET_CODE (src) == CONST_INT
701 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
704 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
708 else if (GET_CODE (dst) == REG
709 && GET_CODE (src) == MEM)
713 /* One can optimize a few cases here, but you have to be
714 careful of clobbering registers used in the address and
718 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 3);
719 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
720 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
721 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
722 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
723 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
729 else if (GET_CODE (dst) == MEM
730 && GET_CODE (src) == REG)
734 /* This is handled by emit_move_sequence so we shouldn't get here. */
743 /* Emit insns to load a constant to non-floating point registers.
744 Uses several strategies to try to use as few insns as possible. */
747 i960_output_ldconst (dst, src)
748 register rtx dst, src;
751 register unsigned rsrc2;
752 enum machine_mode mode = GET_MODE (dst);
755 operands[0] = operands[2] = dst;
756 operands[1] = operands[3] = src;
758 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
759 must be a ldconst insn. */
761 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
763 output_asm_insn ("ldconst %1,%0", operands);
766 else if (mode == XFmode)
772 if (fp_literal_zero (src, XFmode))
775 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
776 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
778 output_asm_insn ("# ldconst %1,%0",operands);
780 for (i = 0; i < 3; i++)
782 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + i);
783 operands[1] = GEN_INT (value_long[i]);
784 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
790 else if (mode == DFmode)
794 if (fp_literal_zero (src, DFmode))
797 split_double (src, &first, &second);
799 output_asm_insn ("# ldconst %1,%0",operands);
801 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
803 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
805 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
806 operands[1] = second;
807 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
811 else if (mode == SFmode)
816 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
817 REAL_VALUE_TO_TARGET_SINGLE (d, value);
819 output_asm_insn ("# ldconst %1,%0",operands);
820 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
821 operands[1] = gen_rtx (CONST_INT, VOIDmode, value);
822 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
826 else if (mode == TImode)
828 /* ??? This is currently not handled at all. */
831 /* Note: lowest order word goes in lowest numbered reg. */
832 rsrc1 = INTVAL (src);
833 if (rsrc1 >= 0 && rsrc1 < 32)
836 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
837 /* Go pick up the low-order word. */
839 else if (mode == DImode)
841 rtx upperhalf, lowerhalf, xoperands[2];
843 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
844 split_double (src, &lowerhalf, &upperhalf);
849 /* Note: lowest order word goes in lowest numbered reg. */
850 /* Numbers from 0 to 31 can be handled with a single insn. */
851 rsrc1 = INTVAL (lowerhalf);
852 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
855 /* Output the upper half with a recursive call. */
856 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
857 xoperands[1] = upperhalf;
858 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
860 /* The lower word is emitted as normally. */
864 rsrc1 = INTVAL (src);
870 else if (mode == HImode)
879 /* ldconst 0..31,X -> mov 0..31,X */
882 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
887 /* ldconst 32..63,X -> add 31,nn,X */
890 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
892 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31);
893 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
899 /* ldconst -1..-31 -> sub 0,0..31,X */
902 /* return 'sub -(%1),0,%0' */
903 operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1);
904 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
908 /* ldconst -32 -> not 31,X */
911 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1);
912 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
917 /* If const is a single bit. */
918 if (bitpos (rsrc1) >= 0)
920 operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1));
921 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
925 /* If const is a bit string of less than 6 bits (1..31 shifted). */
930 if (bitstr (rsrc1, &s, &e) < 6)
932 rsrc2 = ((unsigned int) rsrc1) >> s;
933 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2);
934 operands[2] = gen_rtx (CONST_INT, VOIDmode, s);
935 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
940 /* Unimplemented cases:
941 const is in range 0..31 but rotated around end of word:
942 ror 31,3,g0 -> ldconst 0xe0000003,g0
944 and any 2 instruction cases that might be worthwhile */
946 output_asm_insn ("ldconst %1,%0", operands);
950 /* Determine if there is an opportunity for a bypass optimization.
951 Bypass succeeds on the 960K* if the destination of the previous
952 instruction is the second operand of the current instruction.
953 Bypass always succeeds on the C*.
955 Return 1 if the pattern should interchange the operands.
957 CMPBR_FLAG is true if this is for a compare-and-branch insn.
958 OP1 and OP2 are the two source operands of a 3 operand insn. */
961 i960_bypass (insn, op1, op2, cmpbr_flag)
962 register rtx insn, op1, op2;
965 register rtx prev_insn, prev_dest;
970 /* Can't do this if op1 isn't a register. */
974 /* Can't do this for a compare-and-branch if both ops aren't regs. */
975 if (cmpbr_flag && ! REG_P (op2))
978 prev_insn = prev_real_insn (insn);
980 if (prev_insn && GET_CODE (prev_insn) == INSN
981 && GET_CODE (PATTERN (prev_insn)) == SET)
983 prev_dest = SET_DEST (PATTERN (prev_insn));
984 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
985 || (GET_CODE (prev_dest) == SUBREG
986 && GET_CODE (SUBREG_REG (prev_dest)) == REG
987 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
993 /* Output the code which declares the function name. This also handles
994 leaf routines, which have special requirements, and initializes some
998 i960_function_name_declare (file, name, fndecl)
1007 /* Increment global return label. */
1011 /* Compute whether tail calls and leaf routine optimizations can be performed
1012 for this function. */
1014 if (TARGET_TAILCALL)
1019 if (TARGET_LEAFPROC)
1024 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1025 argblock, because argblock uses g14 implicitly. */
1027 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
1033 /* See if caller passes in an address to return value. */
1035 if (aggregate_value_p (DECL_RESULT (fndecl)))
1041 /* Can not use tail calls or make this a leaf routine if there is a non
1044 if (get_frame_size () != 0)
1047 /* I don't understand this condition, and do not think that it is correct.
1048 Apparently this is just checking whether the frame pointer is used, and
1049 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1052 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1053 if (GET_CODE (insn) == INSN
1054 && reg_mentioned_p (frame_pointer_rtx, insn))
1060 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1063 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1064 if (GET_CODE (insn) == CALL_INSN)
1070 /* Can not be a leaf routine if any non-call clobbered registers are
1071 used in this function. */
1074 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1075 if (regs_ever_live[i]
1076 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1078 /* Global registers. */
1079 if (i < 16 && i > 7 && i != 13)
1081 /* Local registers. */
1086 /* Now choose a leaf return register, if we can find one, and if it is
1087 OK for this to be a leaf routine. */
1089 i960_leaf_ret_reg = -1;
1091 if (optimize && leaf_proc_ok)
1093 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
1094 if (regs_ever_live[i] == 0)
1096 i960_leaf_ret_reg = i;
1097 regs_ever_live[i] = 1;
1102 /* Do this after choosing the leaf return register, so it will be listed
1103 if one was chosen. */
1105 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
1106 fprintf (file, "\t# Registers used: ");
1108 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1110 if (regs_ever_live[i])
1112 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
1114 if (i > 15 && j == 0)
1116 fprintf (file,"\n\t#\t\t ");
1122 fprintf (file, "\n");
1124 if (i960_leaf_ret_reg >= 0)
1126 /* Make it a leaf procedure. */
1128 if (TREE_PUBLIC (fndecl))
1129 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
1131 fprintf (file, "\t.leafproc\t");
1132 assemble_name (file, name);
1133 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
1134 ASM_OUTPUT_LABEL (file, name);
1135 fprintf (file, "\tlda LR%d,g14\n", ret_label);
1136 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
1137 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
1139 if (TARGET_C_SERIES)
1141 fprintf (file, "\tlda 0,g14\n");
1142 i960_last_insn_type = I_TYPE_MEM;
1146 fprintf (file, "\tmov 0,g14\n");
1147 i960_last_insn_type = I_TYPE_REG;
1152 ASM_OUTPUT_LABEL (file, name);
1153 i960_last_insn_type = I_TYPE_CTRL;
1157 /* Compute and return the frame size. */
1160 compute_frame_size (size)
1164 int outgoing_args_size = current_function_outgoing_args_size;
1166 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1167 as size is concerned. */
1168 actual_fsize = (size + 15) & -16;
1169 actual_fsize += (outgoing_args_size + 15) & -16;
1171 return actual_fsize;
1174 /* Output code for the function prologue. */
1177 i960_function_prologue (file, size)
1181 register int i, j, nr;
1184 int actual_fsize, offset;
1186 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1188 int regs[FIRST_PSEUDO_REGISTER];
1190 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1191 if (regs_ever_live[i]
1192 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1195 /* Count global registers that need saving. */
1202 epilogue_string[0] = '\0';
1204 if (profile_flag || profile_block_flag)
1206 /* When profiling, we may use registers 20 to 27 to save arguments, so
1207 they can't be used here for saving globals. J is the number of
1208 argument registers the mcount call will save. */
1209 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1212 for (i = 20; i <= j + 20; i++)
1216 /* First look for local registers to save globals in. */
1217 for (i = 0; i < 16; i++)
1222 /* Start at r4, not r3. */
1223 for (j = 20; j < 32; j++)
1230 regs_ever_live[j] = 1;
1232 if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0
1233 && regs[i+1] != 0 && regs[j+1] == 0)
1238 regs_ever_live[j+1] = 1;
1240 if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0
1241 && regs[i+2] != 0 && regs[j+2] == 0)
1246 regs_ever_live[j+2] = 1;
1248 if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0)
1253 regs_ever_live[j+3] = 1;
1256 fprintf (file, "\tmov%s %s,%s\n",
1259 (nr == 2) ? "l" : ""),
1260 reg_names[i], reg_names[j]);
1261 sprintf (tmpstr, "\tmov%s %s,%s\n",
1264 (nr == 2) ? "l" : ""),
1265 reg_names[j], reg_names[i]);
1266 strcat (epilogue_string, tmpstr);
1274 /* N_iregs is now the number of global registers that haven't been saved
1277 rsize = (n_iregs * 4);
1278 actual_fsize = compute_frame_size (size) + rsize;
1280 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1281 size up to the nearest multiple of 16. I don't know whether this is
1282 necessary, or even desirable.
1284 The frame pointer must be aligned, but the call instruction takes care of
1285 that. If we leave the stack pointer unaligned, we may save a little on
1286 dynamic stack allocation. And we don't lose, at least according to the
1288 actual_fsize = (actual_fsize + 15) & ~0xF;
1291 /* Allocate space for register save and locals. */
1292 if (actual_fsize > 0)
1294 if (actual_fsize < 32)
1295 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1297 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1300 /* Take hardware register save area created by the call instruction
1301 into account, but store them before the argument block area. */
1302 offset = 64 + actual_fsize - compute_frame_size (0) - rsize;
1303 /* Save registers on stack if needed. */
1304 for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
1311 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1314 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1318 if (nr == 3 && regs[i+3] == -1)
1321 fprintf (file,"\tst%s %s,%d(fp)\n",
1324 (nr == 2) ? "l" : ""),
1325 reg_names[i], offset);
1326 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1329 (nr == 2) ? "l" : ""),
1330 offset, reg_names[i]);
1331 strcat (epilogue_string, tmpstr);
1337 if (actual_fsize == 0 && size == 0 && rsize == 0)
1340 fprintf (file, "\t#Prologue stats:\n");
1341 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1344 fprintf (file, "\t# Local Variable Size: %d bytes\n", size);
1346 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1348 fprintf (file, "\t#End Prologue#\n");
1351 /* Output code for the function profiler. */
1354 output_function_profiler (file, labelno)
1358 /* The last used parameter register. */
1360 int i, j, increment;
1361 int varargs_stdarg_function
1362 = VARARGS_STDARG_FUNCTION (current_function_decl);
1364 /* Figure out the last used parameter register. The proper thing to do
1365 is to walk incoming args of the function. A function might have live
1366 parameter registers even if it has no incoming args. Note that we
1367 don't have to save parameter registers g8 to g11 because they are
1370 /* See also output_function_prologue, which tries to use local registers
1371 for preserved call-saved global registers. */
1373 for (last_parm_reg = 7;
1374 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1378 /* Save parameter registers in regs r4 (20) to r11 (27). */
1380 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1382 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1384 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1386 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1391 fprintf (file, "\tmov%s g%d,r%d\n",
1392 (increment == 4 ? "q" : increment == 3 ? "t"
1393 : increment == 2 ? "l": ""), i, j);
1396 /* If this function uses the arg pointer, then save it in r3 and then
1399 if (current_function_args_size != 0 || varargs_stdarg_function)
1400 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1402 /* Load location address into g0 and call mcount. */
1404 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1406 /* If this function uses the arg pointer, restore it. */
1408 if (current_function_args_size != 0 || varargs_stdarg_function)
1409 fprintf (file, "\tmov r3,g14\n");
1411 /* Restore parameter registers. */
1413 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1415 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1417 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1419 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1424 fprintf (file, "\tmov%s r%d,g%d\n",
1425 (increment == 4 ? "q" : increment == 3 ? "t"
1426 : increment == 2 ? "l": ""), j, i);
1430 /* Output code for the function epilogue. */
1433 i960_function_epilogue (file, size)
1437 if (i960_leaf_ret_reg >= 0)
1439 fprintf (file, "LR%d: ret\n", ret_label);
1443 if (*epilogue_string == 0)
1447 /* Emit a return insn, but only if control can fall through to here. */
1449 tmp = get_last_insn ();
1452 if (GET_CODE (tmp) == BARRIER)
1454 if (GET_CODE (tmp) == CODE_LABEL)
1456 if (GET_CODE (tmp) == JUMP_INSN)
1458 if (GET_CODE (PATTERN (tmp)) == RETURN)
1462 if (GET_CODE (tmp) == NOTE)
1464 tmp = PREV_INSN (tmp);
1469 fprintf (file, "LR%d: ret\n", ret_label);
1473 fprintf (file, "LR%d:\n", ret_label);
1475 fprintf (file, "\t#EPILOGUE#\n");
1477 /* Output the string created by the prologue which will restore all
1478 registers saved by the prologue. */
1480 if (epilogue_string[0] != '\0')
1481 fprintf (file, "%s", epilogue_string);
1483 /* Must clear g14 on return if this function set it.
1484 Only varargs/stdarg functions modify g14. */
1486 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1487 fprintf (file, "\tmov 0,g14\n");
1489 fprintf (file, "\tret\n");
1490 fprintf (file, "\t#End Epilogue#\n");
1493 /* Output code for a call insn. */
1496 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1497 register rtx target, argsize_rtx, arg_pointer, insn;
1499 int argsize = INTVAL (argsize_rtx);
1500 rtx nexti = next_real_insn (insn);
1502 int varargs_stdarg_function
1503 = VARARGS_STDARG_FUNCTION (current_function_decl);
1505 operands[0] = target;
1506 operands[1] = arg_pointer;
1508 if (current_function_args_size != 0 || varargs_stdarg_function)
1509 output_asm_insn ("mov g14,r3", operands);
1512 output_asm_insn ("lda %a1,g14", operands);
1513 else if (current_function_args_size != 0 || varargs_stdarg_function)
1514 output_asm_insn ("mov 0,g14", operands);
1516 /* The code used to assume that calls to SYMBOL_REFs could not be more
1517 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1518 feature is now implemented by relaxing in the GNU linker. It can convert
1519 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1521 /* Nexti could be zero if the called routine is volatile. */
1522 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1523 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1525 /* Delete following return insn. */
1526 if (nexti && no_labels_between_p (insn, nexti))
1527 delete_insn (nexti);
1528 output_asm_insn ("bx %0", operands);
1529 return "# notreached";
1532 output_asm_insn ("callx %0", operands);
1534 /* If the caller sets g14 to the address of the argblock, then the caller
1535 must clear it after the return. */
1537 if (current_function_args_size != 0 || varargs_stdarg_function)
1538 output_asm_insn ("mov r3,g14", operands);
1539 else if (argsize > 48)
1540 output_asm_insn ("mov 0,g14", operands);
1545 /* Output code for a return insn. */
1548 i960_output_ret_insn (insn)
1551 static char lbuf[20];
1553 if (*epilogue_string != 0)
1555 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1558 sprintf (lbuf, "b LR%d", ret_label);
1562 /* Must clear g14 on return if this function set it.
1563 Only varargs/stdarg functions modify g14. */
1565 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1566 output_asm_insn ("mov 0,g14", 0);
1568 if (i960_leaf_ret_reg >= 0)
1570 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1577 /* Return a character string representing the branch prediction
1578 opcode to be tacked on an instruction. This must at least
1579 return a null string. */
1582 i960_br_predict_opcode (lab_ref, insn)
1585 if (TARGET_BRANCH_PREDICT)
1587 unsigned long label_uid;
1589 if (GET_CODE (lab_ref) == CODE_LABEL)
1590 label_uid = INSN_UID (lab_ref);
1591 else if (GET_CODE (lab_ref) == LABEL_REF)
1592 label_uid = INSN_UID (XEXP (lab_ref, 0));
1596 /* If not optimizing, then the insn_addresses array will not be
1597 valid. In this case, always return ".t" since most branches
1598 are taken. If optimizing, return .t for backward branches
1599 and .f for forward branches. */
1601 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1610 /* Print the operand represented by rtx X formatted by code CODE. */
1613 i960_print_operand (file, x, code)
1618 enum rtx_code rtxcode = GET_CODE (x);
1625 /* Second reg of a double or quad. */
1626 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1630 /* Third reg of a quad. */
1631 fprintf (file, "%s", reg_names[REGNO (x)+2]);
1635 /* Fourth reg of a quad. */
1636 fprintf (file, "%s", reg_names[REGNO (x)+3]);
1640 fprintf (file, "%s", reg_names[REGNO (x)]);
1648 else if (rtxcode == MEM)
1650 output_address (XEXP (x, 0));
1653 else if (rtxcode == CONST_INT)
1655 HOST_WIDE_INT val = INTVAL (x);
1658 if (val > 9999 || val < -999)
1659 fprintf (file, "0x%x", val);
1661 fprintf (file, "%d", val);
1664 else if (rtxcode == CONST_DOUBLE)
1669 if (x == CONST0_RTX (GET_MODE (x)))
1671 fprintf (file, "0f0.0");
1674 else if (x == CONST1_RTX (GET_MODE (x)))
1676 fprintf (file, "0f1.0");
1680 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1681 REAL_VALUE_TO_DECIMAL (d, "%#g", dstr);
1682 fprintf (file, "0f%s", dstr);
1689 /* Branch or jump, depending on assembler. */
1690 if (TARGET_ASM_COMPAT)
1697 /* Sign of condition. */
1698 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1699 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1701 else if ((rtxcode == GT) || (rtxcode == LT)
1702 || (rtxcode == GE) || (rtxcode == LE))
1709 /* Inverted condition. */
1710 rtxcode = reverse_condition (rtxcode);
1714 /* Inverted condition w/ reversed operands. */
1715 rtxcode = reverse_condition (rtxcode);
1719 /* Reversed operand condition. */
1720 rtxcode = swap_condition (rtxcode);
1724 /* Normal condition. */
1726 if (rtxcode == EQ) { fputs ("e", file); return; }
1727 else if (rtxcode == NE) { fputs ("ne", file); return; }
1728 else if (rtxcode == GT) { fputs ("g", file); return; }
1729 else if (rtxcode == GTU) { fputs ("g", file); return; }
1730 else if (rtxcode == LT) { fputs ("l", file); return; }
1731 else if (rtxcode == LTU) { fputs ("l", file); return; }
1732 else if (rtxcode == GE) { fputs ("ge", file); return; }
1733 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1734 else if (rtxcode == LE) { fputs ("le", file); return; }
1735 else if (rtxcode == LEU) { fputs ("le", file); return; }
1740 output_addr_const (file, x);
1750 /* Print a memory address as an operand to reference that memory location.
1752 This is exactly the same as legitimate_address_p, except that it the prints
1753 addresses instead of recognizing them. */
1756 i960_print_operand_addr (file, addr)
1768 if (GET_CODE (addr) == REG)
1770 else if (CONSTANT_P (addr))
1772 else if (GET_CODE (addr) == PLUS)
1776 op0 = XEXP (addr, 0);
1777 op1 = XEXP (addr, 1);
1779 if (GET_CODE (op0) == REG)
1782 if (GET_CODE (op1) == REG)
1784 else if (CONSTANT_P (op1))
1789 else if (GET_CODE (op0) == PLUS)
1791 if (GET_CODE (XEXP (op0, 0)) == MULT)
1793 ireg = XEXP (XEXP (op0, 0), 0);
1794 scale = XEXP (XEXP (op0, 0), 1);
1795 if (GET_CODE (XEXP (op0, 1)) == REG)
1797 breg = XEXP (op0, 1);
1803 else if (GET_CODE (XEXP (op0, 0)) == REG)
1805 breg = XEXP (op0, 0);
1806 if (GET_CODE (XEXP (op0, 1)) == REG)
1808 ireg = XEXP (op0, 1);
1817 else if (GET_CODE (op0) == MULT)
1819 ireg = XEXP (op0, 0);
1820 scale = XEXP (op0, 1);
1821 if (GET_CODE (op1) == REG)
1823 else if (CONSTANT_P (op1))
1831 else if (GET_CODE (addr) == MULT)
1833 ireg = XEXP (addr, 0);
1834 scale = XEXP (addr, 1);
1840 output_addr_const (file, offset);
1842 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1844 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1847 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1848 that is a valid memory address for an instruction.
1849 The MODE argument is the machine mode for the MEM expression
1850 that wants to use this address.
1852 On 80960, legitimate addresses are:
1854 disp (12 or 32 bit) ld foo,r0
1855 base + index ld (g0)[g1*1],r0
1856 base + displ ld 0xf00(g0),r0
1857 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1858 index*scale + base ld (g0)[g1*4],r0
1859 index*scale + displ ld 0xf00[g1*4],r0
1860 index*scale ld [g1*4],r0
1861 index + base + displ ld 0xf00(g0)[g1*1],r0
1863 In each case, scale can be 1, 2, 4, 8, or 16. */
1865 /* This is exactly the same as i960_print_operand_addr, except that
1866 it recognizes addresses instead of printing them.
1868 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1869 convert common non-canonical forms to canonical form so that they will
1872 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1873 where a register is valid. */
1875 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1876 ((GET_CODE (X) == REG \
1877 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1878 || (GET_CODE (X) == SUBREG \
1879 && GET_CODE (SUBREG_REG (X)) == REG \
1880 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1881 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1883 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1884 ((GET_CODE (X) == REG \
1885 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1886 || (GET_CODE (X) == SUBREG \
1887 && GET_CODE (SUBREG_REG (X)) == REG \
1888 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1889 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1892 legitimate_address_p (mode, addr, strict)
1893 enum machine_mode mode;
1897 if (RTX_OK_FOR_BASE_P (addr, strict))
1899 else if (CONSTANT_P (addr))
1901 else if (GET_CODE (addr) == PLUS)
1905 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1908 op0 = XEXP (addr, 0);
1909 op1 = XEXP (addr, 1);
1911 if (RTX_OK_FOR_BASE_P (op0, strict))
1913 if (RTX_OK_FOR_INDEX_P (op1, strict))
1915 else if (CONSTANT_P (op1))
1920 else if (GET_CODE (op0) == PLUS)
1922 if (GET_CODE (XEXP (op0, 0)) == MULT)
1924 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
1925 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
1928 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
1929 && CONSTANT_P (op1))
1934 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
1936 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
1937 && CONSTANT_P (op1))
1945 else if (GET_CODE (op0) == MULT)
1947 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
1948 && SCALE_TERM_P (XEXP (op0, 1))))
1951 if (RTX_OK_FOR_BASE_P (op1, strict))
1953 else if (CONSTANT_P (op1))
1961 else if (GET_CODE (addr) == MULT)
1963 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1966 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
1967 && SCALE_TERM_P (XEXP (addr, 1)));
1973 /* Try machine-dependent ways of modifying an illegitimate address
1974 to be legitimate. If we find one, return the new, valid address.
1975 This macro is used in only one place: `memory_address' in explow.c.
1977 This converts some non-canonical addresses to canonical form so they
1978 can be recognized. */
1981 legitimize_address (x, oldx, mode)
1984 enum machine_mode mode;
1986 if (GET_CODE (x) == SYMBOL_REF)
1989 x = copy_to_reg (x);
1992 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1995 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1996 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1997 created by virtual register instantiation, register elimination, and
1998 similar optimizations. */
1999 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
2000 && GET_CODE (XEXP (x, 1)) == PLUS)
2001 x = gen_rtx (PLUS, Pmode,
2002 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2003 XEXP (XEXP (x, 1), 1));
2005 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2006 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2007 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2008 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2009 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2010 && CONSTANT_P (XEXP (x, 1)))
2012 rtx constant, other;
2014 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2016 constant = XEXP (x, 1);
2017 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2019 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2021 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2022 other = XEXP (x, 1);
2028 x = gen_rtx (PLUS, Pmode,
2029 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2030 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2031 plus_constant (other, INTVAL (constant)));
2038 /* Return the most stringent alignment that we are willing to consider
2039 objects of size SIZE and known alignment ALIGN as having. */
2042 i960_alignment (size, align)
2048 if (! TARGET_STRICT_ALIGN)
2049 if (TARGET_IC_COMPAT2_0 || align >= 4)
2051 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2060 /* Modes for condition codes. */
2062 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
2064 /* Modes for single-word (and smaller) quantities. */
2067 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
2068 | (1 << (int) DFmode) | (1 << (int) XFmode)))
2070 /* Modes for double-word (and smaller) quantities. */
2073 & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
2075 /* Modes for quad-word quantities. */
2076 #define T_MODES (~C_MODES)
2078 /* Modes for single-float quantities. */
2079 #define SF_MODES ((1 << (int) SFmode))
2081 /* Modes for double-float quantities. */
2082 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
2084 /* Modes for quad-float quantities. */
2085 #define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
2087 unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
2088 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2089 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2090 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2091 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
2093 XF_MODES, XF_MODES, XF_MODES, XF_MODES, C_MODES};
2096 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2097 advantage of machine specific facts, such as knowing that the frame pointer
2098 is always 16 byte aligned. */
2101 i960_expr_alignment (x, size)
2110 switch (GET_CODE(x))
2115 if ((align & 0xf) == 0)
2117 else if ((align & 0x7) == 0)
2119 else if ((align & 0x3) == 0)
2121 else if ((align & 0x1) == 0)
2128 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
2129 i960_expr_alignment (XEXP (x, 1), size));
2133 /* If this is a valid program, objects are guaranteed to be
2134 correctly aligned for whatever size the reference actually is. */
2135 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2139 if (REGNO (x) == FRAME_POINTER_REGNUM)
2144 align = i960_expr_alignment (XEXP (x, 0));
2146 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2148 align = align << INTVAL (XEXP (x, 1));
2149 align = MIN (align, 16);
2154 align = (i960_expr_alignment (XEXP (x, 0), size) *
2155 i960_expr_alignment (XEXP (x, 1), size));
2157 align = MIN (align, 16);
2164 /* Return true if it is possible to reference both BASE and OFFSET, which
2165 have alignment at least as great as 4 byte, as if they had alignment valid
2166 for an object of size SIZE. */
2169 i960_improve_align (base, offset, size)
2176 /* We have at least a word reference to the object, so we know it has to
2177 be aligned at least to 4 bytes. */
2179 i = MIN (i960_expr_alignment (base, 4),
2180 i960_expr_alignment (offset, 4));
2184 /* We know the size of the request. If strict align is not enabled, we
2185 can guess that the alignment is OK for the requested size. */
2187 if (! TARGET_STRICT_ALIGN)
2188 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
2194 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2195 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2198 i960_si_ti (base, offset)
2202 return i960_improve_align (base, offset, 16);
2205 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2206 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2209 i960_si_di (base, offset)
2213 return i960_improve_align (base, offset, 8);
2216 /* Return raw values of size and alignment (in words) for the data
2217 type being accessed. These values will be rounded by the caller. */
2220 i960_arg_size_and_align (mode, type, size_out, align_out)
2221 enum machine_mode mode;
2228 /* Use formal alignment requirements of type being passed, except make
2229 it at least a word. If we don't have a type, this is a library call,
2230 and the parm has to be of scalar type. In this case, consider its
2231 formal alignment requirement to be its size in words. */
2233 if (mode == BLKmode)
2234 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2235 else if (mode == VOIDmode)
2237 /* End of parm list. */
2238 assert (type != 0 && TYPE_MODE (type) == VOIDmode);
2242 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2246 /* ??? This is a hack to properly correct the alignment of XFmode
2247 values without affecting anything else. */
2253 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2254 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2262 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2263 Any arg that is bigger than 4 words is placed on the stack and all
2264 subsequent arguments are placed on the stack.
2266 Additionally, parameters with an alignment requirement stronger than
2267 a word must be aligned appropriately. Note that this means that a
2268 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2269 passed in an odd/even register pair. */
2271 /* Update CUM to advance past an argument described by MODE and TYPE. */
2274 i960_function_arg_advance (cum, mode, type, named)
2275 CUMULATIVE_ARGS *cum;
2276 enum machine_mode mode;
2282 i960_arg_size_and_align (mode, type, &size, &align);
2284 if (size > 4 || cum->ca_nstackparms != 0
2285 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2286 || MUST_PASS_IN_STACK (mode, type))
2288 /* Indicate that all the registers are in use, even if all are not,
2289 so va_start will compute the right value. */
2290 cum->ca_nregparms = NPARM_REGS;
2291 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2294 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2297 /* Return the register that the argument described by MODE and TYPE is
2298 passed in, or else return 0 if it is passed on the stack. */
2301 i960_function_arg (cum, mode, type, named)
2302 CUMULATIVE_ARGS *cum;
2303 enum machine_mode mode;
2310 i960_arg_size_and_align (mode, type, &size, &align);
2312 if (size > 4 || cum->ca_nstackparms != 0
2313 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2314 || MUST_PASS_IN_STACK (mode, type))
2316 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2321 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2322 ret = gen_rtx (REG, mode, cum->ca_nregparms);
2328 /* Floating-point support. */
2331 i960_output_long_double (file, value)
2333 REAL_VALUE_TYPE value;
2338 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
2339 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2342 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2343 value_long[0], dstr, value_long[1], value_long[2]);
2344 fprintf (file, "\t.word\t0x0\n");
2348 i960_output_double (file, value)
2350 REAL_VALUE_TYPE value;
2355 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
2356 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2358 fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2359 value_long[0], dstr, value_long[1]);
2363 i960_output_float (file, value)
2365 REAL_VALUE_TYPE value;
2370 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
2371 REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr);
2373 fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr);
2376 /* Return the number of bits that an object of size N bytes is aligned to. */
2379 i960_object_bytes_bitalign (n)
2383 else if (n > 4) n = 64;
2384 else if (n > 2) n = 32;
2385 else if (n > 1) n = 16;
2391 /* Compute the alignment for an aggregate type TSIZE.
2392 Alignment is MAX (greatest member alignment,
2393 MIN (pragma align, structure size alignment)). */
2396 i960_round_align (align, tsize)
2402 if (TREE_CODE (tsize) != INTEGER_CST)
2405 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2407 /* Handle #pragma align. */
2408 if (new_align > i960_maxbitalignment)
2409 new_align = i960_maxbitalignment;
2411 if (align < new_align)
2417 /* Do any needed setup for a varargs function. For the i960, we must
2418 create a register parameter block if one doesn't exist, and then copy
2419 all register parameters to memory. */
2422 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2423 CUMULATIVE_ARGS *cum;
2424 enum machine_mode mode;
2429 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2430 int first_reg = cum->ca_nregparms;
2432 /* Copy only unnamed register arguments to memory. If there are
2433 any stack parms, there are no unnamed arguments in registers, and
2434 an argument block was already allocated by the caller.
2435 Remember that any arg bigger than 4 words is passed on the stack as
2436 are all subsequent args.
2438 If there are no stack arguments but there are exactly NPARM_REGS
2439 registers, either there were no extra arguments or the caller
2440 allocated an argument block. */
2442 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
2444 rtx label = gen_label_rtx ();
2447 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2448 and we need to allocate a chunk to save the registers (if any
2449 arguments were passed on the stack the caller would allocate the
2450 48 bytes as well). We must allocate all 48 bytes (12*4) because
2451 va_start assumes it. */
2452 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2453 emit_jump_insn (gen_bne (label));
2454 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
2455 stack_pointer_rtx));
2456 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
2457 memory_address (SImode,
2458 plus_constant (stack_pointer_rtx,
2462 /* ??? Note that we unnecessarily store one extra register for stdarg
2463 fns. We could optimize this, but it's kept as for now. */
2464 regblock = gen_rtx (MEM, BLKmode,
2465 plus_constant (arg_pointer_rtx,
2467 move_block_from_reg (first_reg, regblock,
2468 NPARM_REGS - first_reg,
2469 (NPARM_REGS - first_reg) * UNITS_PER_WORD);
2473 /* Calculate the final size of the reg parm stack space for the current
2474 function, based on how many bytes would be allocated on the stack. */
2477 i960_final_reg_parm_stack_space (const_size, var_size)
2481 if (var_size || const_size > 48)
2487 /* Calculate the size of the reg parm stack space. This is a bit complicated
2491 i960_reg_parm_stack_space (fndecl)
2494 /* In this case, we are called from emit_library_call, and we don't need
2495 to pretend we have more space for parameters than what's apparent. */
2499 /* In this case, we are called from locate_and_pad_parms when we're
2500 not IN_REGS, so we have an arg block. */
2501 if (fndecl != current_function_decl)
2504 /* Otherwise, we have an arg block if the current function has more than
2505 48 bytes of parameters. */
2506 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2512 /* Return the register class of a scratch register needed to copy IN into
2513 or out of a register in CLASS in MODE. If it can be done directly,
2514 NO_REGS is returned. */
2517 secondary_reload_class (class, mode, in)
2518 enum reg_class class;
2519 enum machine_mode mode;
2524 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2525 regno = true_regnum (in);
2527 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2528 LOCAL_OR_GLOBAL_REGS into anything. */
2529 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2530 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2533 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2534 if (class == FP_REGS
2535 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2536 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2539 return LOCAL_OR_GLOBAL_REGS;
2542 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2543 function unit it executed on. */
2545 /* ??? This would make more sense as an attribute. */
2548 i960_scan_opcode (p)
2560 /* Ret is not actually of type REG, but it won't matter, because no
2561 insn will ever follow it. */
2564 i960_last_insn_type = I_TYPE_REG;
2568 if (p[1] == 'x' || p[3] == 'x')
2569 i960_last_insn_type = I_TYPE_MEM;
2570 i960_last_insn_type = I_TYPE_CTRL;
2575 i960_last_insn_type = I_TYPE_CTRL;
2582 i960_last_insn_type = I_TYPE_MEM;
2584 i960_last_insn_type = I_TYPE_CTRL;
2586 else if (p[1] == 'm')
2589 i960_last_insn_type = I_TYPE_REG;
2590 else if (p[4] == 'b' || p[4] == 'j')
2591 i960_last_insn_type = I_TYPE_CTRL;
2593 i960_last_insn_type = I_TYPE_REG;
2596 i960_last_insn_type = I_TYPE_REG;
2600 i960_last_insn_type = I_TYPE_MEM;
2605 i960_last_insn_type = I_TYPE_MEM;
2607 i960_last_insn_type = I_TYPE_REG;