1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0, i960_compare_op1;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment;
53 static int i960_last_maxbitalignment;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label = 0;
78 /* This is true if FNDECL is either a varargs or a stdarg function.
79 This is used to help identify functions that use an argument block. */
81 #define VARARGS_STDARG_FUNCTION(FNDECL) \
82 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
83 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
84 || current_function_varargs)
86 /* Handle pragmas for compatibility with Intel's compilers. */
88 /* ??? This is incomplete, since it does not handle all pragmas that the
89 intel compilers understand. */
92 process_pragma (p_getc, p_ungetc, pname)
93 int (* p_getc) PROTO ((void));
94 void (* p_ungetc) PROTO ((int));
103 /* Should be pragma 'far' or equivalent for callx/balx here. */
104 if (strcmp (pname, "align") != 0)
111 while (c == ' ' || c == '\t');
116 while (c >= '0' && c <= '9')
118 if (s < buf + sizeof buf - 1)
125 /* We had to read a non-numerical character to get out of the
126 while loop---often a newline. So, we have to put it back to
127 make sure we continue to parse everything properly. */
136 /* Return to last alignment. */
137 align = i960_last_maxbitalignment / 8;
144 i960_last_maxbitalignment = i960_maxbitalignment;
145 i960_maxbitalignment = align * 8;
149 /* Silently ignore bad values. */
153 /* NOTE: ic960 R3.0 pragma align definition:
155 #pragma align [(size)] | (identifier=size[,...])
156 #pragma noalign [(identifier)[,...]]
158 (all parens are optional)
160 - size is [1,2,4,8,16]
161 - noalign means size==1
162 - applies only to component elements of a struct (and union?)
163 - identifier applies to structure tag (only)
164 - missing identifier means next struct
166 - alignment rules for bitfields need more investigation */
171 /* Initialize variables before compiling any files. */
176 if (TARGET_IC_COMPAT2_0)
178 i960_maxbitalignment = 8;
179 i960_last_maxbitalignment = 128;
183 i960_maxbitalignment = 128;
184 i960_last_maxbitalignment = 8;
188 /* Return true if OP can be used as the source of an fp move insn. */
191 fpmove_src_operand (op, mode)
193 enum machine_mode mode;
195 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
199 /* Return true if OP is a register or zero. */
202 reg_or_zero_operand (op, mode)
204 enum machine_mode mode;
206 return register_operand (op, mode) || op == const0_rtx;
210 /* Return truth value of whether OP can be used as an operands in a three
211 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
214 arith_operand (op, mode)
216 enum machine_mode mode;
218 return (register_operand (op, mode) || literal (op, mode));
221 /* Return truth value of whether OP can be used as an operands in a three
222 address logic insn, possibly complementing OP, of mode MODE. */
225 logic_operand (op, mode)
227 enum machine_mode mode;
229 return (register_operand (op, mode)
230 || (GET_CODE (op) == CONST_INT
231 && INTVAL(op) >= -32 && INTVAL(op) < 32));
234 /* Return true if OP is a register or a valid floating point literal. */
237 fp_arith_operand (op, mode)
239 enum machine_mode mode;
241 return (register_operand (op, mode) || fp_literal (op, mode));
244 /* Return true is OP is a register or a valid signed integer literal. */
247 signed_arith_operand (op, mode)
249 enum machine_mode mode;
251 return (register_operand (op, mode) || signed_literal (op, mode));
254 /* Return truth value of whether OP is a integer which fits the
255 range constraining immediate operands in three-address insns. */
260 enum machine_mode mode;
262 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
265 /* Return true if OP is a float constant of 1. */
268 fp_literal_one (op, mode)
270 enum machine_mode mode;
272 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
275 /* Return true if OP is a float constant of 0. */
278 fp_literal_zero (op, mode)
280 enum machine_mode mode;
282 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
285 /* Return true if OP is a valid floating point literal. */
290 enum machine_mode mode;
292 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
295 /* Return true if OP is a valid signed immediate constant. */
298 signed_literal(op, mode)
300 enum machine_mode mode;
302 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
305 /* Return truth value of statement that OP is a symbolic memory
306 operand of mode MODE. */
309 symbolic_memory_operand (op, mode)
311 enum machine_mode mode;
313 if (GET_CODE (op) == SUBREG)
314 op = SUBREG_REG (op);
315 if (GET_CODE (op) != MEM)
318 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
319 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
322 /* Return truth value of whether OP is EQ or NE. */
327 enum machine_mode mode;
329 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
332 /* OP is an integer register or a constant. */
335 arith32_operand (op, mode)
337 enum machine_mode mode;
339 if (register_operand (op, mode))
341 return (CONSTANT_P (op));
344 /* Return true if OP is an integer constant which is a power of 2. */
347 power2_operand (op,mode)
349 enum machine_mode mode;
351 if (GET_CODE (op) != CONST_INT)
354 return exact_log2 (INTVAL (op)) >= 0;
357 /* Return true if OP is an integer constant which is the complement of a
361 cmplpower2_operand (op, mode)
363 enum machine_mode mode;
365 if (GET_CODE (op) != CONST_INT)
368 return exact_log2 (~ INTVAL (op)) >= 0;
371 /* If VAL has only one bit set, return the index of that bit. Otherwise
380 for (i = 0; val != 0; i++, val >>= 1)
392 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
393 The return value indicates how many consecutive non-zero bits exist
394 if this is a mask. This is the same as the next function, except that
395 it does not indicate what the start and stop bit positions are. */
401 register int start, end, i;
404 for (i = 0; val != 0; val >>= 1, i++)
414 /* Still looking for the first bit. */
418 /* We've seen the start of a bit sequence, and now a zero. There
419 must be more one bits, otherwise we would have exited the loop.
420 Therefore, it is not a mask. */
425 /* The bit string has ones from START to END bit positions only. */
426 return end - start + 1;
429 /* If VAL is a mask, then return nonzero, with S set to the starting bit
430 position and E set to the ending bit position of the mask. The return
431 value indicates how many consecutive bits exist in the mask. This is
432 the same as the previous function, except that it also indicates the
433 start and end bit positions of the mask. */
440 register int start, end, i;
444 for (i = 0; val != 0; val >>= 1, i++)
455 /* Still looking for the first bit. */
459 /* We've seen the start of a bit sequence, and now a zero. There
460 must be more one bits, otherwise we would have exited the loop.
461 Therefor, it is not a mask. */
470 /* The bit string has ones from START to END bit positions only. */
473 return ((start < 0) ? 0 : end - start + 1);
476 /* Return the machine mode to use for a comparison. */
479 select_cc_mode (op, x)
483 if (op == GTU || op == LTU || op == GEU || op == LEU)
488 /* X and Y are two things to compare using CODE. Emit the compare insn and
489 return the rtx for register 36 in the proper mode. */
492 gen_compare_reg (code, x, y)
497 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
498 enum machine_mode mode
499 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
503 if (! arith_operand (x, mode))
504 x = force_reg (SImode, x);
505 if (! arith_operand (y, mode))
506 y = force_reg (SImode, y);
509 cc_reg = gen_rtx (REG, ccmode, 36);
510 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
511 gen_rtx (COMPARE, ccmode, x, y)));
516 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
517 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
518 are 4. Indexed addresses are cost 6. */
520 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
523 i960_address_cost (x)
527 /* Handled before calling here. */
528 if (GET_CODE (x) == REG)
531 /* This is a MEMA operand -- it's free. */
532 if (GET_CODE (x) == CONST_INT
534 && INTVAL (x) < 4096)
537 if (GET_CODE (x) == PLUS)
539 rtx base = XEXP (x, 0);
540 rtx offset = XEXP (x, 1);
542 if (GET_CODE (base) == SUBREG)
543 base = SUBREG_REG (base);
544 if (GET_CODE (offset) == SUBREG)
545 offset = SUBREG_REG (offset);
547 if (GET_CODE (base) == REG)
549 if (GET_CODE (offset) == REG)
551 if (GET_CODE (offset) == CONST_INT)
553 if ((unsigned)INTVAL (offset) < 2047)
557 if (CONSTANT_P (offset))
560 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
563 /* This is an invalid address. The return value doesn't matter, but
564 for convenience we make this more expensive than anything else. */
567 if (GET_CODE (x) == MULT)
570 /* Symbol_refs and other unrecognized addresses are cost 4. */
574 /* Emit insns to move operands[1] into operands[0].
576 Return 1 if we have written out everything that needs to be done to
577 do the move. Otherwise, return 0 and the caller will emit the move
581 emit_move_sequence (operands, mode)
583 enum machine_mode mode;
585 /* We can only store registers to memory. */
587 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
588 operands[1] = force_reg (mode, operands[1]);
590 /* Storing multi-word values in unaligned hard registers to memory may
591 require a scratch since we have to store them a register at a time and
592 adding 4 to the memory address may not yield a valid insn. */
593 /* ??? We don't always need the scratch, but that would complicate things.
595 /* ??? We must also handle stores to pseudos here, because the pseudo may be
596 replaced with a MEM later. This would be cleaner if we didn't have
597 a separate pattern for unaligned DImode/TImode stores. */
598 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
599 && (GET_CODE (operands[0]) == MEM
600 || (GET_CODE (operands[0]) == REG
601 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
602 && GET_CODE (operands[1]) == REG
603 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
604 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
606 emit_insn (gen_rtx (PARALLEL, VOIDmode,
608 gen_rtx (SET, VOIDmode,
609 operands[0], operands[1]),
610 gen_rtx (CLOBBER, VOIDmode,
611 gen_rtx (SCRATCH, Pmode)))));
618 /* Output assembler to move a double word value. */
621 i960_output_move_double (dst, src)
626 if (GET_CODE (dst) == REG
627 && GET_CODE (src) == REG)
629 if ((REGNO (src) & 1)
630 || (REGNO (dst) & 1))
632 /* We normally copy the low-numbered register first. However, if
633 the second source register is the same as the first destination
634 register, we must copy in the opposite order. */
635 if (REGNO (src) + 1 == REGNO (dst))
636 return "mov %D1,%D0\n\tmov %1,%0";
638 return "mov %1,%0\n\tmov %D1,%D0";
643 else if (GET_CODE (dst) == REG
644 && GET_CODE (src) == CONST_INT
645 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
648 return "mov %1,%0\n\tmov 0,%D0";
652 else if (GET_CODE (dst) == REG
653 && GET_CODE (src) == MEM)
657 /* One can optimize a few cases here, but you have to be
658 careful of clobbering registers used in the address and
662 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 1);
663 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
664 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
665 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
671 else if (GET_CODE (dst) == MEM
672 && GET_CODE (src) == REG)
676 /* This is handled by emit_move_sequence so we shouldn't get here. */
685 /* Output assembler to move a quad word value. */
688 i960_output_move_quad (dst, src)
693 if (GET_CODE (dst) == REG
694 && GET_CODE (src) == REG)
696 if ((REGNO (src) & 3)
697 || (REGNO (dst) & 3))
699 /* We normally copy starting with the low numbered register.
700 However, if there is an overlap such that the first dest reg
701 is <= the last source reg but not < the first source reg, we
702 must copy in the opposite order. */
703 if (REGNO (dst) <= REGNO (src) + 3
704 && REGNO (dst) >= REGNO (src))
705 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
707 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
712 else if (GET_CODE (dst) == REG
713 && GET_CODE (src) == CONST_INT
714 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
717 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
721 else if (GET_CODE (dst) == REG
722 && GET_CODE (src) == MEM)
726 /* One can optimize a few cases here, but you have to be
727 careful of clobbering registers used in the address and
731 operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 3);
732 operands[3] = gen_rtx (MEM, word_mode, operands[2]);
733 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
734 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
735 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
736 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
742 else if (GET_CODE (dst) == MEM
743 && GET_CODE (src) == REG)
747 /* This is handled by emit_move_sequence so we shouldn't get here. */
756 /* Emit insns to load a constant to non-floating point registers.
757 Uses several strategies to try to use as few insns as possible. */
760 i960_output_ldconst (dst, src)
761 register rtx dst, src;
764 register unsigned rsrc2;
765 enum machine_mode mode = GET_MODE (dst);
768 operands[0] = operands[2] = dst;
769 operands[1] = operands[3] = src;
771 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
772 must be a ldconst insn. */
774 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
776 output_asm_insn ("ldconst %1,%0", operands);
779 else if (mode == XFmode)
785 if (fp_literal_zero (src, XFmode))
788 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
789 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
791 output_asm_insn ("# ldconst %1,%0",operands);
793 for (i = 0; i < 3; i++)
795 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + i);
796 operands[1] = GEN_INT (value_long[i]);
797 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
803 else if (mode == DFmode)
807 if (fp_literal_zero (src, DFmode))
810 split_double (src, &first, &second);
812 output_asm_insn ("# ldconst %1,%0",operands);
814 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
816 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
818 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
819 operands[1] = second;
820 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
824 else if (mode == SFmode)
829 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
830 REAL_VALUE_TO_TARGET_SINGLE (d, value);
832 output_asm_insn ("# ldconst %1,%0",operands);
833 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
834 operands[1] = GEN_INT (value);
835 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
839 else if (mode == TImode)
841 /* ??? This is currently not handled at all. */
844 /* Note: lowest order word goes in lowest numbered reg. */
845 rsrc1 = INTVAL (src);
846 if (rsrc1 >= 0 && rsrc1 < 32)
849 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
850 /* Go pick up the low-order word. */
852 else if (mode == DImode)
854 rtx upperhalf, lowerhalf, xoperands[2];
856 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
857 split_double (src, &lowerhalf, &upperhalf);
862 /* Note: lowest order word goes in lowest numbered reg. */
863 /* Numbers from 0 to 31 can be handled with a single insn. */
864 rsrc1 = INTVAL (lowerhalf);
865 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
868 /* Output the upper half with a recursive call. */
869 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
870 xoperands[1] = upperhalf;
871 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
873 /* The lower word is emitted as normally. */
877 rsrc1 = INTVAL (src);
883 else if (mode == HImode)
892 /* ldconst 0..31,X -> mov 0..31,X */
895 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
900 /* ldconst 32..63,X -> add 31,nn,X */
903 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
905 operands[1] = GEN_INT (rsrc1 - 31);
906 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
912 /* ldconst -1..-31 -> sub 0,0..31,X */
915 /* return 'sub -(%1),0,%0' */
916 operands[1] = GEN_INT (- rsrc1);
917 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
921 /* ldconst -32 -> not 31,X */
924 operands[1] = GEN_INT (~rsrc1);
925 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
930 /* If const is a single bit. */
931 if (bitpos (rsrc1) >= 0)
933 operands[1] = GEN_INT (bitpos (rsrc1));
934 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
938 /* If const is a bit string of less than 6 bits (1..31 shifted). */
943 if (bitstr (rsrc1, &s, &e) < 6)
945 rsrc2 = ((unsigned int) rsrc1) >> s;
946 operands[1] = GEN_INT (rsrc2);
947 operands[2] = GEN_INT (s);
948 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
953 /* Unimplemented cases:
954 const is in range 0..31 but rotated around end of word:
955 ror 31,3,g0 -> ldconst 0xe0000003,g0
957 and any 2 instruction cases that might be worthwhile */
959 output_asm_insn ("ldconst %1,%0", operands);
963 /* Determine if there is an opportunity for a bypass optimization.
964 Bypass succeeds on the 960K* if the destination of the previous
965 instruction is the second operand of the current instruction.
966 Bypass always succeeds on the C*.
968 Return 1 if the pattern should interchange the operands.
970 CMPBR_FLAG is true if this is for a compare-and-branch insn.
971 OP1 and OP2 are the two source operands of a 3 operand insn. */
974 i960_bypass (insn, op1, op2, cmpbr_flag)
975 register rtx insn, op1, op2;
978 register rtx prev_insn, prev_dest;
983 /* Can't do this if op1 isn't a register. */
987 /* Can't do this for a compare-and-branch if both ops aren't regs. */
988 if (cmpbr_flag && ! REG_P (op2))
991 prev_insn = prev_real_insn (insn);
993 if (prev_insn && GET_CODE (prev_insn) == INSN
994 && GET_CODE (PATTERN (prev_insn)) == SET)
996 prev_dest = SET_DEST (PATTERN (prev_insn));
997 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
998 || (GET_CODE (prev_dest) == SUBREG
999 && GET_CODE (SUBREG_REG (prev_dest)) == REG
1000 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
1006 /* Output the code which declares the function name. This also handles
1007 leaf routines, which have special requirements, and initializes some
1008 global variables. */
1011 i960_function_name_declare (file, name, fndecl)
1020 /* Increment global return label. */
1024 /* Compute whether tail calls and leaf routine optimizations can be performed
1025 for this function. */
1027 if (TARGET_TAILCALL)
1032 if (TARGET_LEAFPROC)
1037 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1038 argblock, because argblock uses g14 implicitly. */
1040 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
1046 /* See if caller passes in an address to return value. */
1048 if (aggregate_value_p (DECL_RESULT (fndecl)))
1054 /* Can not use tail calls or make this a leaf routine if there is a non
1057 if (get_frame_size () != 0)
1060 /* I don't understand this condition, and do not think that it is correct.
1061 Apparently this is just checking whether the frame pointer is used, and
1062 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1065 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1066 if (GET_CODE (insn) == INSN
1067 && reg_mentioned_p (frame_pointer_rtx, insn))
1073 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1076 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1077 if (GET_CODE (insn) == CALL_INSN)
1083 /* Can not be a leaf routine if any non-call clobbered registers are
1084 used in this function. */
1087 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (regs_ever_live[i]
1089 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1091 /* Global registers. */
1092 if (i < 16 && i > 7 && i != 13)
1094 /* Local registers. */
1099 /* Now choose a leaf return register, if we can find one, and if it is
1100 OK for this to be a leaf routine. */
1102 i960_leaf_ret_reg = -1;
1104 if (optimize && leaf_proc_ok)
1106 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
1107 if (regs_ever_live[i] == 0)
1109 i960_leaf_ret_reg = i;
1110 regs_ever_live[i] = 1;
1115 /* Do this after choosing the leaf return register, so it will be listed
1116 if one was chosen. */
1118 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
1119 fprintf (file, "\t# Registers used: ");
1121 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1123 if (regs_ever_live[i])
1125 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
1127 if (i > 15 && j == 0)
1129 fprintf (file,"\n\t#\t\t ");
1135 fprintf (file, "\n");
1137 if (i960_leaf_ret_reg >= 0)
1139 /* Make it a leaf procedure. */
1141 if (TREE_PUBLIC (fndecl))
1142 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
1144 fprintf (file, "\t.leafproc\t");
1145 assemble_name (file, name);
1146 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
1147 ASM_OUTPUT_LABEL (file, name);
1148 fprintf (file, "\tlda LR%d,g14\n", ret_label);
1149 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
1150 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
1152 if (TARGET_C_SERIES)
1154 fprintf (file, "\tlda 0,g14\n");
1155 i960_last_insn_type = I_TYPE_MEM;
1159 fprintf (file, "\tmov 0,g14\n");
1160 i960_last_insn_type = I_TYPE_REG;
1165 ASM_OUTPUT_LABEL (file, name);
1166 i960_last_insn_type = I_TYPE_CTRL;
1170 /* Compute and return the frame size. */
1173 compute_frame_size (size)
1177 int outgoing_args_size = current_function_outgoing_args_size;
1179 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1180 as size is concerned. */
1181 actual_fsize = (size + 15) & -16;
1182 actual_fsize += (outgoing_args_size + 15) & -16;
1184 return actual_fsize;
1187 /* Here register group is range of registers which can be moved by
1188 one i960 instruction. */
1196 /* The following functions forms the biggest as possible register
1197 groups with registers in STATE. REGS contain states of the
1198 registers in range [start, finish_reg). The function returns the
1199 number of groups formed. */
1201 i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
1206 struct reg_group *reg_groups;
1211 for (i = start_reg; i < finish_reg; )
1213 if (regs [i] != state)
1218 else if (i % 2 != 0 || regs [i + 1] != state)
1219 reg_groups [nw].length = 1;
1220 else if (i % 4 != 0 || regs [i + 2] != state)
1221 reg_groups [nw].length = 2;
1222 else if (regs [i + 3] != state)
1223 reg_groups [nw].length = 3;
1225 reg_groups [nw].length = 4;
1226 reg_groups [nw].start_reg = i;
1227 i += reg_groups [nw].length;
1233 /* We sort register winodws in descending order by length. */
1235 i960_reg_group_compare (group1, group2)
1239 struct reg_group *w1 = group1;
1240 struct reg_group *w2 = group2;
1242 if (w1->length > w2->length)
1244 else if (w1->length < w2->length)
1250 /* Split the first register group in REG_GROUPS on subgroups one of
1251 which will contain SUBGROUP_LENGTH registers. The function
1252 returns new number of winodws. */
1254 i960_split_reg_group (reg_groups, nw, subgroup_length)
1255 struct reg_group *reg_groups;
1257 int subgroup_length;
1259 if (subgroup_length < reg_groups->length - subgroup_length)
1260 /* This guarantees correct alignments of the two subgroups for
1261 i960 (see spliting for the group length 2, 3, 4). More
1262 generalized algorithm would require splitting the group more
1264 subgroup_length = reg_groups->length - subgroup_length;
1265 /* More generalized algorithm would require to try merging
1266 subgroups here. But in case i960 it always results in failure
1267 because of register group alignment. */
1268 reg_groups[nw].length = reg_groups->length - subgroup_length;
1269 reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
1271 reg_groups->length = subgroup_length;
1272 qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare);
1276 /* Output code for the function prologue. */
1279 i960_function_prologue (file, size)
1283 register int i, j, nr;
1286 int actual_fsize, offset;
1288 struct reg_group *g, *l;
1290 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1292 int regs[FIRST_PSEUDO_REGISTER];
1293 /* All global registers (which must be saved) divided by groups. */
1294 struct reg_group global_reg_groups [16];
1295 /* All local registers (which are available) divided by groups. */
1296 struct reg_group local_reg_groups [16];
1299 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1300 if (regs_ever_live[i]
1301 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1304 /* Count global registers that need saving. */
1311 epilogue_string[0] = '\0';
1313 if (profile_flag || profile_block_flag)
1315 /* When profiling, we may use registers 20 to 27 to save arguments, so
1316 they can't be used here for saving globals. J is the number of
1317 argument registers the mcount call will save. */
1318 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1321 for (i = 20; i <= j + 20; i++)
1325 gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups);
1326 lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups);
1327 qsort (global_reg_groups, gnw, sizeof (struct reg_group),
1328 i960_reg_group_compare);
1329 qsort (local_reg_groups, lnw, sizeof (struct reg_group),
1330 i960_reg_group_compare);
1331 for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;)
1333 if (g->length == l->length)
1335 fprintf (file, "\tmov%s %s,%s\n",
1336 ((g->length == 4) ? "q" :
1337 (g->length == 3) ? "t" :
1338 (g->length == 2) ? "l" : ""),
1339 reg_names[g->start_reg], reg_names[l->start_reg]);
1340 sprintf (tmpstr, "\tmov%s %s,%s\n",
1341 ((g->length == 4) ? "q" :
1342 (g->length == 3) ? "t" :
1343 (g->length == 2) ? "l" : ""),
1344 reg_names[l->start_reg], reg_names[g->start_reg]);
1345 strcat (epilogue_string, tmpstr);
1346 n_iregs -= g->length;
1347 for (i = 0; i < g->length; i++)
1349 regs [i + g->start_reg] = 1;
1350 regs [i + l->start_reg] = -1;
1351 regs_ever_live [i + l->start_reg] = 1;
1358 else if (g->length > l->length)
1359 gnw = i960_split_reg_group (g, gnw, l->length);
1361 lnw = i960_split_reg_group (l, lnw, g->length);
1364 /* N_iregs is now the number of global registers that haven't been saved
1367 rsize = (n_iregs * 4);
1368 actual_fsize = compute_frame_size (size) + rsize;
1370 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1371 size up to the nearest multiple of 16. I don't know whether this is
1372 necessary, or even desirable.
1374 The frame pointer must be aligned, but the call instruction takes care of
1375 that. If we leave the stack pointer unaligned, we may save a little on
1376 dynamic stack allocation. And we don't lose, at least according to the
1378 actual_fsize = (actual_fsize + 15) & ~0xF;
1381 /* Allocate space for register save and locals. */
1382 if (actual_fsize > 0)
1384 if (actual_fsize < 32)
1385 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1387 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1390 /* Take hardware register save area created by the call instruction
1391 into account, but store them before the argument block area. */
1392 offset = 64 + actual_fsize - compute_frame_size (0) - rsize;
1393 /* Save registers on stack if needed. */
1394 /* ??? Is it worth to use the same algorithm as one for saving
1395 global registers in local registers? */
1396 for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
1403 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1406 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1410 if (nr == 3 && regs[i+3] == -1)
1413 fprintf (file,"\tst%s %s,%d(fp)\n",
1416 (nr == 2) ? "l" : ""),
1417 reg_names[i], offset);
1418 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1421 (nr == 2) ? "l" : ""),
1422 offset, reg_names[i]);
1423 strcat (epilogue_string, tmpstr);
1429 if (actual_fsize == 0 && size == 0 && rsize == 0)
1432 fprintf (file, "\t#Prologue stats:\n");
1433 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1436 fprintf (file, "\t# Local Variable Size: %d bytes\n", size);
1438 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1440 fprintf (file, "\t#End Prologue#\n");
1443 /* Output code for the function profiler. */
1446 output_function_profiler (file, labelno)
1450 /* The last used parameter register. */
1452 int i, j, increment;
1453 int varargs_stdarg_function
1454 = VARARGS_STDARG_FUNCTION (current_function_decl);
1456 /* Figure out the last used parameter register. The proper thing to do
1457 is to walk incoming args of the function. A function might have live
1458 parameter registers even if it has no incoming args. Note that we
1459 don't have to save parameter registers g8 to g11 because they are
1462 /* See also output_function_prologue, which tries to use local registers
1463 for preserved call-saved global registers. */
1465 for (last_parm_reg = 7;
1466 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1470 /* Save parameter registers in regs r4 (20) to r11 (27). */
1472 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1474 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1476 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1478 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1483 fprintf (file, "\tmov%s g%d,r%d\n",
1484 (increment == 4 ? "q" : increment == 3 ? "t"
1485 : increment == 2 ? "l": ""), i, j);
1488 /* If this function uses the arg pointer, then save it in r3 and then
1491 if (current_function_args_size != 0 || varargs_stdarg_function)
1492 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1494 /* Load location address into g0 and call mcount. */
1496 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1498 /* If this function uses the arg pointer, restore it. */
1500 if (current_function_args_size != 0 || varargs_stdarg_function)
1501 fprintf (file, "\tmov r3,g14\n");
1503 /* Restore parameter registers. */
1505 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1507 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1509 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1511 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1516 fprintf (file, "\tmov%s r%d,g%d\n",
1517 (increment == 4 ? "q" : increment == 3 ? "t"
1518 : increment == 2 ? "l": ""), j, i);
1522 /* Output code for the function epilogue. */
1525 i960_function_epilogue (file, size)
1529 if (i960_leaf_ret_reg >= 0)
1531 fprintf (file, "LR%d: ret\n", ret_label);
1535 if (*epilogue_string == 0)
1539 /* Emit a return insn, but only if control can fall through to here. */
1541 tmp = get_last_insn ();
1544 if (GET_CODE (tmp) == BARRIER)
1546 if (GET_CODE (tmp) == CODE_LABEL)
1548 if (GET_CODE (tmp) == JUMP_INSN)
1550 if (GET_CODE (PATTERN (tmp)) == RETURN)
1554 if (GET_CODE (tmp) == NOTE)
1556 tmp = PREV_INSN (tmp);
1561 fprintf (file, "LR%d: ret\n", ret_label);
1565 fprintf (file, "LR%d:\n", ret_label);
1567 fprintf (file, "\t#EPILOGUE#\n");
1569 /* Output the string created by the prologue which will restore all
1570 registers saved by the prologue. */
1572 if (epilogue_string[0] != '\0')
1573 fprintf (file, "%s", epilogue_string);
1575 /* Must clear g14 on return if this function set it.
1576 Only varargs/stdarg functions modify g14. */
1578 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1579 fprintf (file, "\tmov 0,g14\n");
1581 fprintf (file, "\tret\n");
1582 fprintf (file, "\t#End Epilogue#\n");
1585 /* Output code for a call insn. */
1588 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1589 register rtx target, argsize_rtx, arg_pointer, insn;
1591 int argsize = INTVAL (argsize_rtx);
1592 rtx nexti = next_real_insn (insn);
1594 int varargs_stdarg_function
1595 = VARARGS_STDARG_FUNCTION (current_function_decl);
1597 operands[0] = target;
1598 operands[1] = arg_pointer;
1600 if (current_function_args_size != 0 || varargs_stdarg_function)
1601 output_asm_insn ("mov g14,r3", operands);
1604 output_asm_insn ("lda %a1,g14", operands);
1605 else if (current_function_args_size != 0 || varargs_stdarg_function)
1606 output_asm_insn ("mov 0,g14", operands);
1608 /* The code used to assume that calls to SYMBOL_REFs could not be more
1609 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1610 feature is now implemented by relaxing in the GNU linker. It can convert
1611 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1613 /* Nexti could be zero if the called routine is volatile. */
1614 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1615 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1617 /* Delete following return insn. */
1618 if (nexti && no_labels_between_p (insn, nexti))
1619 delete_insn (nexti);
1620 output_asm_insn ("bx %0", operands);
1621 return "# notreached";
1624 output_asm_insn ("callx %0", operands);
1626 /* If the caller sets g14 to the address of the argblock, then the caller
1627 must clear it after the return. */
1629 if (current_function_args_size != 0 || varargs_stdarg_function)
1630 output_asm_insn ("mov r3,g14", operands);
1631 else if (argsize > 48)
1632 output_asm_insn ("mov 0,g14", operands);
1637 /* Output code for a return insn. */
1640 i960_output_ret_insn (insn)
1643 static char lbuf[20];
1645 if (*epilogue_string != 0)
1647 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1650 sprintf (lbuf, "b LR%d", ret_label);
1654 /* Must clear g14 on return if this function set it.
1655 Only varargs/stdarg functions modify g14. */
1657 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1658 output_asm_insn ("mov 0,g14", 0);
1660 if (i960_leaf_ret_reg >= 0)
1662 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1669 /* Return a character string representing the branch prediction
1670 opcode to be tacked on an instruction. This must at least
1671 return a null string. */
1674 i960_br_predict_opcode (lab_ref, insn)
1677 if (TARGET_BRANCH_PREDICT)
1679 unsigned long label_uid;
1681 if (GET_CODE (lab_ref) == CODE_LABEL)
1682 label_uid = INSN_UID (lab_ref);
1683 else if (GET_CODE (lab_ref) == LABEL_REF)
1684 label_uid = INSN_UID (XEXP (lab_ref, 0));
1688 /* If not optimizing, then the insn_addresses array will not be
1689 valid. In this case, always return ".t" since most branches
1690 are taken. If optimizing, return .t for backward branches
1691 and .f for forward branches. */
1693 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1702 /* Print the operand represented by rtx X formatted by code CODE. */
1705 i960_print_operand (file, x, code)
1710 enum rtx_code rtxcode = GET_CODE (x);
1717 /* Second reg of a double or quad. */
1718 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1722 /* Third reg of a quad. */
1723 fprintf (file, "%s", reg_names[REGNO (x)+2]);
1727 /* Fourth reg of a quad. */
1728 fprintf (file, "%s", reg_names[REGNO (x)+3]);
1732 fprintf (file, "%s", reg_names[REGNO (x)]);
1740 else if (rtxcode == MEM)
1742 output_address (XEXP (x, 0));
1745 else if (rtxcode == CONST_INT)
1747 HOST_WIDE_INT val = INTVAL (x);
1750 if (val > 9999 || val < -999)
1751 fprintf (file, "0x%x", val);
1753 fprintf (file, "%d", val);
1756 else if (rtxcode == CONST_DOUBLE)
1761 if (x == CONST0_RTX (GET_MODE (x)))
1763 fprintf (file, "0f0.0");
1766 else if (x == CONST1_RTX (GET_MODE (x)))
1768 fprintf (file, "0f1.0");
1772 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1773 REAL_VALUE_TO_DECIMAL (d, "%#g", dstr);
1774 fprintf (file, "0f%s", dstr);
1781 /* Branch or jump, depending on assembler. */
1782 if (TARGET_ASM_COMPAT)
1789 /* Sign of condition. */
1790 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1791 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1793 else if ((rtxcode == GT) || (rtxcode == LT)
1794 || (rtxcode == GE) || (rtxcode == LE))
1801 /* Inverted condition. */
1802 rtxcode = reverse_condition (rtxcode);
1806 /* Inverted condition w/ reversed operands. */
1807 rtxcode = reverse_condition (rtxcode);
1811 /* Reversed operand condition. */
1812 rtxcode = swap_condition (rtxcode);
1816 /* Normal condition. */
1818 if (rtxcode == EQ) { fputs ("e", file); return; }
1819 else if (rtxcode == NE) { fputs ("ne", file); return; }
1820 else if (rtxcode == GT) { fputs ("g", file); return; }
1821 else if (rtxcode == GTU) { fputs ("g", file); return; }
1822 else if (rtxcode == LT) { fputs ("l", file); return; }
1823 else if (rtxcode == LTU) { fputs ("l", file); return; }
1824 else if (rtxcode == GE) { fputs ("ge", file); return; }
1825 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1826 else if (rtxcode == LE) { fputs ("le", file); return; }
1827 else if (rtxcode == LEU) { fputs ("le", file); return; }
1832 output_addr_const (file, x);
1842 /* Print a memory address as an operand to reference that memory location.
1844 This is exactly the same as legitimate_address_p, except that it the prints
1845 addresses instead of recognizing them. */
1848 i960_print_operand_addr (file, addr)
1860 if (GET_CODE (addr) == REG)
1862 else if (CONSTANT_P (addr))
1864 else if (GET_CODE (addr) == PLUS)
1868 op0 = XEXP (addr, 0);
1869 op1 = XEXP (addr, 1);
1871 if (GET_CODE (op0) == REG)
1874 if (GET_CODE (op1) == REG)
1876 else if (CONSTANT_P (op1))
1881 else if (GET_CODE (op0) == PLUS)
1883 if (GET_CODE (XEXP (op0, 0)) == MULT)
1885 ireg = XEXP (XEXP (op0, 0), 0);
1886 scale = XEXP (XEXP (op0, 0), 1);
1887 if (GET_CODE (XEXP (op0, 1)) == REG)
1889 breg = XEXP (op0, 1);
1895 else if (GET_CODE (XEXP (op0, 0)) == REG)
1897 breg = XEXP (op0, 0);
1898 if (GET_CODE (XEXP (op0, 1)) == REG)
1900 ireg = XEXP (op0, 1);
1909 else if (GET_CODE (op0) == MULT)
1911 ireg = XEXP (op0, 0);
1912 scale = XEXP (op0, 1);
1913 if (GET_CODE (op1) == REG)
1915 else if (CONSTANT_P (op1))
1923 else if (GET_CODE (addr) == MULT)
1925 ireg = XEXP (addr, 0);
1926 scale = XEXP (addr, 1);
1932 output_addr_const (file, offset);
1934 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1936 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1939 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1940 that is a valid memory address for an instruction.
1941 The MODE argument is the machine mode for the MEM expression
1942 that wants to use this address.
1944 On 80960, legitimate addresses are:
1946 disp (12 or 32 bit) ld foo,r0
1947 base + index ld (g0)[g1*1],r0
1948 base + displ ld 0xf00(g0),r0
1949 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1950 index*scale + base ld (g0)[g1*4],r0
1951 index*scale + displ ld 0xf00[g1*4],r0
1952 index*scale ld [g1*4],r0
1953 index + base + displ ld 0xf00(g0)[g1*1],r0
1955 In each case, scale can be 1, 2, 4, 8, or 16. */
1957 /* This is exactly the same as i960_print_operand_addr, except that
1958 it recognizes addresses instead of printing them.
1960 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1961 convert common non-canonical forms to canonical form so that they will
1964 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1965 where a register is valid. */
1967 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1968 ((GET_CODE (X) == REG \
1969 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1970 || (GET_CODE (X) == SUBREG \
1971 && GET_CODE (SUBREG_REG (X)) == REG \
1972 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1973 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1975 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1976 ((GET_CODE (X) == REG \
1977 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1978 || (GET_CODE (X) == SUBREG \
1979 && GET_CODE (SUBREG_REG (X)) == REG \
1980 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1981 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1984 legitimate_address_p (mode, addr, strict)
1985 enum machine_mode mode;
1989 if (RTX_OK_FOR_BASE_P (addr, strict))
1991 else if (CONSTANT_P (addr))
1993 else if (GET_CODE (addr) == PLUS)
1997 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2000 op0 = XEXP (addr, 0);
2001 op1 = XEXP (addr, 1);
2003 if (RTX_OK_FOR_BASE_P (op0, strict))
2005 if (RTX_OK_FOR_INDEX_P (op1, strict))
2007 else if (CONSTANT_P (op1))
2012 else if (GET_CODE (op0) == PLUS)
2014 if (GET_CODE (XEXP (op0, 0)) == MULT)
2016 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
2017 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
2020 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
2021 && CONSTANT_P (op1))
2026 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
2028 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
2029 && CONSTANT_P (op1))
2037 else if (GET_CODE (op0) == MULT)
2039 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
2040 && SCALE_TERM_P (XEXP (op0, 1))))
2043 if (RTX_OK_FOR_BASE_P (op1, strict))
2045 else if (CONSTANT_P (op1))
2053 else if (GET_CODE (addr) == MULT)
2055 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2058 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
2059 && SCALE_TERM_P (XEXP (addr, 1)));
2065 /* Try machine-dependent ways of modifying an illegitimate address
2066 to be legitimate. If we find one, return the new, valid address.
2067 This macro is used in only one place: `memory_address' in explow.c.
2069 This converts some non-canonical addresses to canonical form so they
2070 can be recognized. */
2073 legitimize_address (x, oldx, mode)
2076 enum machine_mode mode;
2078 if (GET_CODE (x) == SYMBOL_REF)
2081 x = copy_to_reg (x);
2084 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2087 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2088 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2089 created by virtual register instantiation, register elimination, and
2090 similar optimizations. */
2091 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
2092 && GET_CODE (XEXP (x, 1)) == PLUS)
2093 x = gen_rtx (PLUS, Pmode,
2094 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2095 XEXP (XEXP (x, 1), 1));
2097 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2098 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2099 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2100 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2101 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2102 && CONSTANT_P (XEXP (x, 1)))
2104 rtx constant, other;
2106 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2108 constant = XEXP (x, 1);
2109 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2111 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2113 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2114 other = XEXP (x, 1);
2120 x = gen_rtx (PLUS, Pmode,
2121 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
2122 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2123 plus_constant (other, INTVAL (constant)));
2130 /* Return the most stringent alignment that we are willing to consider
2131 objects of size SIZE and known alignment ALIGN as having. */
2134 i960_alignment (size, align)
2140 if (! TARGET_STRICT_ALIGN)
2141 if (TARGET_IC_COMPAT2_0 || align >= 4)
2143 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2154 hard_regno_mode_ok (regno, mode)
2156 enum machine_mode mode;
2162 case CCmode: case CC_UNSmode: case CC_CHKmode:
2165 case DImode: case DFmode:
2166 return (regno & 1) == 0;
2168 case TImode: case XFmode:
2169 return (regno & 3) == 0;
2175 else if (regno >= 32 && regno < 36)
2179 case SFmode: case DFmode: case XFmode:
2180 case SCmode: case DCmode:
2187 else if (regno == 36)
2191 case CCmode: case CC_UNSmode: case CC_CHKmode:
2198 else if (regno == 37)
2205 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2206 advantage of machine specific facts, such as knowing that the frame pointer
2207 is always 16 byte aligned. */
2210 i960_expr_alignment (x, size)
2219 switch (GET_CODE(x))
2224 if ((align & 0xf) == 0)
2226 else if ((align & 0x7) == 0)
2228 else if ((align & 0x3) == 0)
2230 else if ((align & 0x1) == 0)
2237 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
2238 i960_expr_alignment (XEXP (x, 1), size));
2242 /* If this is a valid program, objects are guaranteed to be
2243 correctly aligned for whatever size the reference actually is. */
2244 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2248 if (REGNO (x) == FRAME_POINTER_REGNUM)
2253 align = i960_expr_alignment (XEXP (x, 0));
2255 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2257 align = align << INTVAL (XEXP (x, 1));
2258 align = MIN (align, 16);
2263 align = (i960_expr_alignment (XEXP (x, 0), size) *
2264 i960_expr_alignment (XEXP (x, 1), size));
2266 align = MIN (align, 16);
2273 /* Return true if it is possible to reference both BASE and OFFSET, which
2274 have alignment at least as great as 4 byte, as if they had alignment valid
2275 for an object of size SIZE. */
2278 i960_improve_align (base, offset, size)
2285 /* We have at least a word reference to the object, so we know it has to
2286 be aligned at least to 4 bytes. */
2288 i = MIN (i960_expr_alignment (base, 4),
2289 i960_expr_alignment (offset, 4));
2293 /* We know the size of the request. If strict align is not enabled, we
2294 can guess that the alignment is OK for the requested size. */
2296 if (! TARGET_STRICT_ALIGN)
2297 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
2303 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2304 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2307 i960_si_ti (base, offset)
2311 return i960_improve_align (base, offset, 16);
2314 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2315 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2318 i960_si_di (base, offset)
2322 return i960_improve_align (base, offset, 8);
2325 /* Return raw values of size and alignment (in words) for the data
2326 type being accessed. These values will be rounded by the caller. */
2329 i960_arg_size_and_align (mode, type, size_out, align_out)
2330 enum machine_mode mode;
2337 /* Use formal alignment requirements of type being passed, except make
2338 it at least a word. If we don't have a type, this is a library call,
2339 and the parm has to be of scalar type. In this case, consider its
2340 formal alignment requirement to be its size in words. */
2342 if (mode == BLKmode)
2343 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2344 else if (mode == VOIDmode)
2346 /* End of parm list. */
2347 if (type == 0 || TYPE_MODE (type) != VOIDmode)
2352 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2356 /* ??? This is a hack to properly correct the alignment of XFmode
2357 values without affecting anything else. */
2363 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2364 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2372 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2373 Any arg that is bigger than 4 words is placed on the stack and all
2374 subsequent arguments are placed on the stack.
2376 Additionally, parameters with an alignment requirement stronger than
2377 a word must be aligned appropriately. Note that this means that a
2378 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2379 passed in an odd/even register pair. */
2381 /* Update CUM to advance past an argument described by MODE and TYPE. */
2384 i960_function_arg_advance (cum, mode, type, named)
2385 CUMULATIVE_ARGS *cum;
2386 enum machine_mode mode;
2392 i960_arg_size_and_align (mode, type, &size, &align);
2394 if (size > 4 || cum->ca_nstackparms != 0
2395 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2396 || MUST_PASS_IN_STACK (mode, type))
2398 /* Indicate that all the registers are in use, even if all are not,
2399 so va_start will compute the right value. */
2400 cum->ca_nregparms = NPARM_REGS;
2401 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2404 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2407 /* Return the register that the argument described by MODE and TYPE is
2408 passed in, or else return 0 if it is passed on the stack. */
2411 i960_function_arg (cum, mode, type, named)
2412 CUMULATIVE_ARGS *cum;
2413 enum machine_mode mode;
2420 i960_arg_size_and_align (mode, type, &size, &align);
2422 if (size > 4 || cum->ca_nstackparms != 0
2423 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2424 || MUST_PASS_IN_STACK (mode, type))
2426 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2431 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2432 ret = gen_rtx (REG, mode, cum->ca_nregparms);
2438 /* Floating-point support. */
2441 i960_output_long_double (file, value)
2443 REAL_VALUE_TYPE value;
2448 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
2449 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2452 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2453 value_long[0], dstr, value_long[1], value_long[2]);
2454 fprintf (file, "\t.word\t0x0\n");
2458 i960_output_double (file, value)
2460 REAL_VALUE_TYPE value;
2465 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
2466 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2468 fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2469 value_long[0], dstr, value_long[1]);
2473 i960_output_float (file, value)
2475 REAL_VALUE_TYPE value;
2480 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
2481 REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr);
2483 fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr);
2486 /* Return the number of bits that an object of size N bytes is aligned to. */
2489 i960_object_bytes_bitalign (n)
2493 else if (n > 4) n = 64;
2494 else if (n > 2) n = 32;
2495 else if (n > 1) n = 16;
2501 /* Compute the alignment for an aggregate type TSIZE.
2502 Alignment is MAX (greatest member alignment,
2503 MIN (pragma align, structure size alignment)). */
2506 i960_round_align (align, tsize)
2512 if (TREE_CODE (tsize) != INTEGER_CST)
2515 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2517 /* Handle #pragma align. */
2518 if (new_align > i960_maxbitalignment)
2519 new_align = i960_maxbitalignment;
2521 if (align < new_align)
2527 /* Do any needed setup for a varargs function. For the i960, we must
2528 create a register parameter block if one doesn't exist, and then copy
2529 all register parameters to memory. */
2532 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2533 CUMULATIVE_ARGS *cum;
2534 enum machine_mode mode;
2539 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2540 int first_reg = cum->ca_nregparms;
2542 /* Copy only unnamed register arguments to memory. If there are
2543 any stack parms, there are no unnamed arguments in registers, and
2544 an argument block was already allocated by the caller.
2545 Remember that any arg bigger than 4 words is passed on the stack as
2546 are all subsequent args.
2548 If there are no stack arguments but there are exactly NPARM_REGS
2549 registers, either there were no extra arguments or the caller
2550 allocated an argument block. */
2552 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
2554 rtx label = gen_label_rtx ();
2557 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2558 and we need to allocate a chunk to save the registers (if any
2559 arguments were passed on the stack the caller would allocate the
2560 48 bytes as well). We must allocate all 48 bytes (12*4) because
2561 va_start assumes it. */
2562 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2563 emit_jump_insn (gen_bne (label));
2564 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
2565 stack_pointer_rtx));
2566 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
2567 memory_address (SImode,
2568 plus_constant (stack_pointer_rtx,
2572 /* ??? Note that we unnecessarily store one extra register for stdarg
2573 fns. We could optimize this, but it's kept as for now. */
2574 regblock = gen_rtx (MEM, BLKmode,
2575 plus_constant (arg_pointer_rtx,
2577 move_block_from_reg (first_reg, regblock,
2578 NPARM_REGS - first_reg,
2579 (NPARM_REGS - first_reg) * UNITS_PER_WORD);
2583 /* Calculate the final size of the reg parm stack space for the current
2584 function, based on how many bytes would be allocated on the stack. */
2587 i960_final_reg_parm_stack_space (const_size, var_size)
2591 if (var_size || const_size > 48)
2597 /* Calculate the size of the reg parm stack space. This is a bit complicated
2601 i960_reg_parm_stack_space (fndecl)
2604 /* In this case, we are called from emit_library_call, and we don't need
2605 to pretend we have more space for parameters than what's apparent. */
2609 /* In this case, we are called from locate_and_pad_parms when we're
2610 not IN_REGS, so we have an arg block. */
2611 if (fndecl != current_function_decl)
2614 /* Otherwise, we have an arg block if the current function has more than
2615 48 bytes of parameters. */
2616 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2622 /* Return the register class of a scratch register needed to copy IN into
2623 or out of a register in CLASS in MODE. If it can be done directly,
2624 NO_REGS is returned. */
2627 secondary_reload_class (class, mode, in)
2628 enum reg_class class;
2629 enum machine_mode mode;
2634 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2635 regno = true_regnum (in);
2637 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2638 LOCAL_OR_GLOBAL_REGS into anything. */
2639 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2640 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2643 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2644 if (class == FP_REGS
2645 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2646 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2649 return LOCAL_OR_GLOBAL_REGS;
2652 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2653 function unit it executed on. */
2655 /* ??? This would make more sense as an attribute. */
2658 i960_scan_opcode (p)
2670 /* Ret is not actually of type REG, but it won't matter, because no
2671 insn will ever follow it. */
2674 i960_last_insn_type = I_TYPE_REG;
2678 if (p[1] == 'x' || p[3] == 'x')
2679 i960_last_insn_type = I_TYPE_MEM;
2680 i960_last_insn_type = I_TYPE_CTRL;
2685 i960_last_insn_type = I_TYPE_CTRL;
2692 i960_last_insn_type = I_TYPE_MEM;
2694 i960_last_insn_type = I_TYPE_CTRL;
2696 else if (p[1] == 'm')
2699 i960_last_insn_type = I_TYPE_REG;
2700 else if (p[4] == 'b' || p[4] == 'j')
2701 i960_last_insn_type = I_TYPE_CTRL;
2703 i960_last_insn_type = I_TYPE_REG;
2706 i960_last_insn_type = I_TYPE_REG;
2710 i960_last_insn_type = I_TYPE_MEM;
2715 i960_last_insn_type = I_TYPE_MEM;
2717 i960_last_insn_type = I_TYPE_REG;