1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
38 #include "insn-codes.h"
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
49 rtx i960_compare_op0, i960_compare_op1;
51 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
54 static int i960_maxbitalignment;
55 static int i960_last_maxbitalignment;
57 /* Used to implement switching between MEM and ALU insn types, for better
58 C series performance. */
60 enum insn_types i960_last_insn_type;
62 /* The leaf-procedure return register. Set only if this is a leaf routine. */
64 static int i960_leaf_ret_reg;
66 /* True if replacing tail calls with jumps is OK. */
68 static int tail_call_ok;
70 /* A string containing a list of insns to emit in the epilogue so as to
71 restore all registers saved by the prologue. Created by the prologue
72 code as it saves registers away. */
74 char epilogue_string[1000];
76 /* A unique number (per function) for return labels. */
78 static int ret_label = 0;
80 /* This is true if FNDECL is either a varargs or a stdarg function.
81 This is used to help identify functions that use an argument block. */
83 #define VARARGS_STDARG_FUNCTION(FNDECL) \
84 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
85 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
86 || current_function_varargs)
88 /* Handle pragmas for compatibility with Intel's compilers. */
90 /* ??? This is incomplete, since it does not handle all pragmas that the
91 intel compilers understand. */
94 process_pragma (p_getc, p_ungetc, pname)
95 int (* p_getc) PROTO ((void));
96 void (* p_ungetc) PROTO ((int));
105 /* Should be pragma 'far' or equivalent for callx/balx here. */
106 if (strcmp (pname, "align") != 0)
113 while (c == ' ' || c == '\t');
118 while (c >= '0' && c <= '9')
120 if (s < buf + sizeof buf - 1)
127 /* We had to read a non-numerical character to get out of the
128 while loop---often a newline. So, we have to put it back to
129 make sure we continue to parse everything properly. */
138 /* Return to last alignment. */
139 align = i960_last_maxbitalignment / 8;
146 i960_last_maxbitalignment = i960_maxbitalignment;
147 i960_maxbitalignment = align * 8;
151 /* Silently ignore bad values. */
155 /* NOTE: ic960 R3.0 pragma align definition:
157 #pragma align [(size)] | (identifier=size[,...])
158 #pragma noalign [(identifier)[,...]]
160 (all parens are optional)
162 - size is [1,2,4,8,16]
163 - noalign means size==1
164 - applies only to component elements of a struct (and union?)
165 - identifier applies to structure tag (only)
166 - missing identifier means next struct
168 - alignment rules for bitfields need more investigation */
173 /* Initialize variables before compiling any files. */
178 if (TARGET_IC_COMPAT2_0)
180 i960_maxbitalignment = 8;
181 i960_last_maxbitalignment = 128;
185 i960_maxbitalignment = 128;
186 i960_last_maxbitalignment = 8;
190 /* Return true if OP can be used as the source of an fp move insn. */
193 fpmove_src_operand (op, mode)
195 enum machine_mode mode;
197 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
201 /* Return true if OP is a register or zero. */
204 reg_or_zero_operand (op, mode)
206 enum machine_mode mode;
208 return register_operand (op, mode) || op == const0_rtx;
212 /* Return truth value of whether OP can be used as an operands in a three
213 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
216 arith_operand (op, mode)
218 enum machine_mode mode;
220 return (register_operand (op, mode) || literal (op, mode));
223 /* Return truth value of whether OP can be used as an operands in a three
224 address logic insn, possibly complementing OP, of mode MODE. */
227 logic_operand (op, mode)
229 enum machine_mode mode;
231 return (register_operand (op, mode)
232 || (GET_CODE (op) == CONST_INT
233 && INTVAL(op) >= -32 && INTVAL(op) < 32));
236 /* Return true if OP is a register or a valid floating point literal. */
239 fp_arith_operand (op, mode)
241 enum machine_mode mode;
243 return (register_operand (op, mode) || fp_literal (op, mode));
246 /* Return true is OP is a register or a valid signed integer literal. */
249 signed_arith_operand (op, mode)
251 enum machine_mode mode;
253 return (register_operand (op, mode) || signed_literal (op, mode));
256 /* Return truth value of whether OP is a integer which fits the
257 range constraining immediate operands in three-address insns. */
262 enum machine_mode mode;
264 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
267 /* Return true if OP is a float constant of 1. */
270 fp_literal_one (op, mode)
272 enum machine_mode mode;
274 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
277 /* Return true if OP is a float constant of 0. */
280 fp_literal_zero (op, mode)
282 enum machine_mode mode;
284 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
287 /* Return true if OP is a valid floating point literal. */
292 enum machine_mode mode;
294 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
297 /* Return true if OP is a valid signed immediate constant. */
300 signed_literal(op, mode)
302 enum machine_mode mode;
304 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
307 /* Return truth value of statement that OP is a symbolic memory
308 operand of mode MODE. */
311 symbolic_memory_operand (op, mode)
313 enum machine_mode mode;
315 if (GET_CODE (op) == SUBREG)
316 op = SUBREG_REG (op);
317 if (GET_CODE (op) != MEM)
320 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
321 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
324 /* Return truth value of whether OP is EQ or NE. */
329 enum machine_mode mode;
331 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
334 /* OP is an integer register or a constant. */
337 arith32_operand (op, mode)
339 enum machine_mode mode;
341 if (register_operand (op, mode))
343 return (CONSTANT_P (op));
346 /* Return true if OP is an integer constant which is a power of 2. */
349 power2_operand (op,mode)
351 enum machine_mode mode;
353 if (GET_CODE (op) != CONST_INT)
356 return exact_log2 (INTVAL (op)) >= 0;
359 /* Return true if OP is an integer constant which is the complement of a
363 cmplpower2_operand (op, mode)
365 enum machine_mode mode;
367 if (GET_CODE (op) != CONST_INT)
370 return exact_log2 (~ INTVAL (op)) >= 0;
373 /* If VAL has only one bit set, return the index of that bit. Otherwise
382 for (i = 0; val != 0; i++, val >>= 1)
394 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
395 The return value indicates how many consecutive non-zero bits exist
396 if this is a mask. This is the same as the next function, except that
397 it does not indicate what the start and stop bit positions are. */
403 register int start, end, i;
406 for (i = 0; val != 0; val >>= 1, i++)
416 /* Still looking for the first bit. */
420 /* We've seen the start of a bit sequence, and now a zero. There
421 must be more one bits, otherwise we would have exited the loop.
422 Therefore, it is not a mask. */
427 /* The bit string has ones from START to END bit positions only. */
428 return end - start + 1;
431 /* If VAL is a mask, then return nonzero, with S set to the starting bit
432 position and E set to the ending bit position of the mask. The return
433 value indicates how many consecutive bits exist in the mask. This is
434 the same as the previous function, except that it also indicates the
435 start and end bit positions of the mask. */
442 register int start, end, i;
446 for (i = 0; val != 0; val >>= 1, i++)
457 /* Still looking for the first bit. */
461 /* We've seen the start of a bit sequence, and now a zero. There
462 must be more one bits, otherwise we would have exited the loop.
463 Therefor, it is not a mask. */
472 /* The bit string has ones from START to END bit positions only. */
475 return ((start < 0) ? 0 : end - start + 1);
478 /* Return the machine mode to use for a comparison. */
481 select_cc_mode (op, x)
485 if (op == GTU || op == LTU || op == GEU || op == LEU)
490 /* X and Y are two things to compare using CODE. Emit the compare insn and
491 return the rtx for register 36 in the proper mode. */
494 gen_compare_reg (code, x, y)
499 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
500 enum machine_mode mode
501 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
505 if (! arith_operand (x, mode))
506 x = force_reg (SImode, x);
507 if (! arith_operand (y, mode))
508 y = force_reg (SImode, y);
511 cc_reg = gen_rtx_REG (ccmode, 36);
512 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
513 gen_rtx_COMPARE (ccmode, x, y)));
518 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
519 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
520 are 4. Indexed addresses are cost 6. */
522 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
525 i960_address_cost (x)
529 /* Handled before calling here. */
530 if (GET_CODE (x) == REG)
533 /* This is a MEMA operand -- it's free. */
534 if (GET_CODE (x) == CONST_INT
536 && INTVAL (x) < 4096)
539 if (GET_CODE (x) == PLUS)
541 rtx base = XEXP (x, 0);
542 rtx offset = XEXP (x, 1);
544 if (GET_CODE (base) == SUBREG)
545 base = SUBREG_REG (base);
546 if (GET_CODE (offset) == SUBREG)
547 offset = SUBREG_REG (offset);
549 if (GET_CODE (base) == REG)
551 if (GET_CODE (offset) == REG)
553 if (GET_CODE (offset) == CONST_INT)
555 if ((unsigned)INTVAL (offset) < 2047)
559 if (CONSTANT_P (offset))
562 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
565 /* This is an invalid address. The return value doesn't matter, but
566 for convenience we make this more expensive than anything else. */
569 if (GET_CODE (x) == MULT)
572 /* Symbol_refs and other unrecognized addresses are cost 4. */
576 /* Emit insns to move operands[1] into operands[0].
578 Return 1 if we have written out everything that needs to be done to
579 do the move. Otherwise, return 0 and the caller will emit the move
583 emit_move_sequence (operands, mode)
585 enum machine_mode mode;
587 /* We can only store registers to memory. */
589 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG
590 && (operands[1] != const0_rtx || current_function_args_size
591 || current_function_varargs || current_function_stdarg
592 || rtx_equal_function_value_matters))
593 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
594 operands[1] = force_reg (mode, operands[1]);
596 /* Storing multi-word values in unaligned hard registers to memory may
597 require a scratch since we have to store them a register at a time and
598 adding 4 to the memory address may not yield a valid insn. */
599 /* ??? We don't always need the scratch, but that would complicate things.
601 /* ??? We must also handle stores to pseudos here, because the pseudo may be
602 replaced with a MEM later. This would be cleaner if we didn't have
603 a separate pattern for unaligned DImode/TImode stores. */
604 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
605 && (GET_CODE (operands[0]) == MEM
606 || (GET_CODE (operands[0]) == REG
607 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
608 && GET_CODE (operands[1]) == REG
609 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
610 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
612 emit_insn (gen_rtx_PARALLEL
615 gen_rtx_SET (VOIDmode, operands[0], operands[1]),
616 gen_rtx_CLOBBER (VOIDmode,
617 gen_rtx_SCRATCH (Pmode)))));
624 /* Output assembler to move a double word value. */
627 i960_output_move_double (dst, src)
632 if (GET_CODE (dst) == REG
633 && GET_CODE (src) == REG)
635 if ((REGNO (src) & 1)
636 || (REGNO (dst) & 1))
638 /* We normally copy the low-numbered register first. However, if
639 the second source register is the same as the first destination
640 register, we must copy in the opposite order. */
641 if (REGNO (src) + 1 == REGNO (dst))
642 return "mov %D1,%D0\n\tmov %1,%0";
644 return "mov %1,%0\n\tmov %D1,%D0";
649 else if (GET_CODE (dst) == REG
650 && GET_CODE (src) == CONST_INT
651 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
654 return "mov %1,%0\n\tmov 0,%D0";
658 else if (GET_CODE (dst) == REG
659 && GET_CODE (src) == MEM)
663 /* One can optimize a few cases here, but you have to be
664 careful of clobbering registers used in the address and
668 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 1);
669 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
670 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
671 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
677 else if (GET_CODE (dst) == MEM
678 && GET_CODE (src) == REG)
683 operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
684 if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
687 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands);
696 /* Output assembler to move a double word zero. */
699 i960_output_move_double_zero (dst)
706 operands[1] = adj_offsettable_operand (dst, 4);
707 output_asm_insn ("st g14,%0\n\tst g14,%1", operands);
712 /* Output assembler to move a quad word value. */
715 i960_output_move_quad (dst, src)
720 if (GET_CODE (dst) == REG
721 && GET_CODE (src) == REG)
723 if ((REGNO (src) & 3)
724 || (REGNO (dst) & 3))
726 /* We normally copy starting with the low numbered register.
727 However, if there is an overlap such that the first dest reg
728 is <= the last source reg but not < the first source reg, we
729 must copy in the opposite order. */
730 if (REGNO (dst) <= REGNO (src) + 3
731 && REGNO (dst) >= REGNO (src))
732 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
734 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
739 else if (GET_CODE (dst) == REG
740 && GET_CODE (src) == CONST_INT
741 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
744 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
748 else if (GET_CODE (dst) == REG
749 && GET_CODE (src) == MEM)
753 /* One can optimize a few cases here, but you have to be
754 careful of clobbering registers used in the address and
758 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 3);
759 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
760 operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
761 operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
762 operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
763 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
769 else if (GET_CODE (dst) == MEM
770 && GET_CODE (src) == REG)
775 operands[1] = adj_offsettable_operand (dst, UNITS_PER_WORD);
776 operands[2] = adj_offsettable_operand (dst, 2*UNITS_PER_WORD);
777 operands[3] = adj_offsettable_operand (dst, 3*UNITS_PER_WORD);
778 if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
781 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands);
790 /* Output assembler to move a quad word zero. */
793 i960_output_move_quad_zero (dst)
800 operands[1] = adj_offsettable_operand (dst, 4);
801 operands[2] = adj_offsettable_operand (dst, 8);
802 operands[3] = adj_offsettable_operand (dst, 12);
803 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands);
809 /* Emit insns to load a constant to non-floating point registers.
810 Uses several strategies to try to use as few insns as possible. */
813 i960_output_ldconst (dst, src)
814 register rtx dst, src;
817 register unsigned rsrc2;
818 enum machine_mode mode = GET_MODE (dst);
821 operands[0] = operands[2] = dst;
822 operands[1] = operands[3] = src;
824 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
825 must be a ldconst insn. */
827 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
829 output_asm_insn ("ldconst %1,%0", operands);
832 else if (mode == XFmode)
838 if (fp_literal_zero (src, XFmode))
841 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
842 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
844 output_asm_insn ("# ldconst %1,%0",operands);
846 for (i = 0; i < 3; i++)
848 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + i);
849 operands[1] = GEN_INT (value_long[i]);
850 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
856 else if (mode == DFmode)
860 if (fp_literal_zero (src, DFmode))
863 split_double (src, &first, &second);
865 output_asm_insn ("# ldconst %1,%0",operands);
867 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
869 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
871 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
872 operands[1] = second;
873 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
877 else if (mode == SFmode)
882 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
883 REAL_VALUE_TO_TARGET_SINGLE (d, value);
885 output_asm_insn ("# ldconst %1,%0",operands);
886 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
887 operands[1] = GEN_INT (value);
888 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
892 else if (mode == TImode)
894 /* ??? This is currently not handled at all. */
897 /* Note: lowest order word goes in lowest numbered reg. */
898 rsrc1 = INTVAL (src);
899 if (rsrc1 >= 0 && rsrc1 < 32)
902 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
903 /* Go pick up the low-order word. */
905 else if (mode == DImode)
907 rtx upperhalf, lowerhalf, xoperands[2];
909 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
910 split_double (src, &lowerhalf, &upperhalf);
915 /* Note: lowest order word goes in lowest numbered reg. */
916 /* Numbers from 0 to 31 can be handled with a single insn. */
917 rsrc1 = INTVAL (lowerhalf);
918 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
921 /* Output the upper half with a recursive call. */
922 xoperands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
923 xoperands[1] = upperhalf;
924 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
926 /* The lower word is emitted as normally. */
930 rsrc1 = INTVAL (src);
936 else if (mode == HImode)
945 /* ldconst 0..31,X -> mov 0..31,X */
948 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
953 /* ldconst 32..63,X -> add 31,nn,X */
956 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
958 operands[1] = GEN_INT (rsrc1 - 31);
959 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
965 /* ldconst -1..-31 -> sub 0,0..31,X */
968 /* return 'sub -(%1),0,%0' */
969 operands[1] = GEN_INT (- rsrc1);
970 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
974 /* ldconst -32 -> not 31,X */
977 operands[1] = GEN_INT (~rsrc1);
978 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
983 /* If const is a single bit. */
984 if (bitpos (rsrc1) >= 0)
986 operands[1] = GEN_INT (bitpos (rsrc1));
987 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
991 /* If const is a bit string of less than 6 bits (1..31 shifted). */
996 if (bitstr (rsrc1, &s, &e) < 6)
998 rsrc2 = ((unsigned int) rsrc1) >> s;
999 operands[1] = GEN_INT (rsrc2);
1000 operands[2] = GEN_INT (s);
1001 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
1006 /* Unimplemented cases:
1007 const is in range 0..31 but rotated around end of word:
1008 ror 31,3,g0 -> ldconst 0xe0000003,g0
1010 and any 2 instruction cases that might be worthwhile */
1012 output_asm_insn ("ldconst %1,%0", operands);
1016 /* Determine if there is an opportunity for a bypass optimization.
1017 Bypass succeeds on the 960K* if the destination of the previous
1018 instruction is the second operand of the current instruction.
1019 Bypass always succeeds on the C*.
1021 Return 1 if the pattern should interchange the operands.
1023 CMPBR_FLAG is true if this is for a compare-and-branch insn.
1024 OP1 and OP2 are the two source operands of a 3 operand insn. */
1027 i960_bypass (insn, op1, op2, cmpbr_flag)
1028 register rtx insn, op1, op2;
1031 register rtx prev_insn, prev_dest;
1033 if (TARGET_C_SERIES)
1036 /* Can't do this if op1 isn't a register. */
1040 /* Can't do this for a compare-and-branch if both ops aren't regs. */
1041 if (cmpbr_flag && ! REG_P (op2))
1044 prev_insn = prev_real_insn (insn);
1046 if (prev_insn && GET_CODE (prev_insn) == INSN
1047 && GET_CODE (PATTERN (prev_insn)) == SET)
1049 prev_dest = SET_DEST (PATTERN (prev_insn));
1050 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
1051 || (GET_CODE (prev_dest) == SUBREG
1052 && GET_CODE (SUBREG_REG (prev_dest)) == REG
1053 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
1059 /* Output the code which declares the function name. This also handles
1060 leaf routines, which have special requirements, and initializes some
1061 global variables. */
1064 i960_function_name_declare (file, name, fndecl)
1073 /* Increment global return label. */
1077 /* Compute whether tail calls and leaf routine optimizations can be performed
1078 for this function. */
1080 if (TARGET_TAILCALL)
1085 if (TARGET_LEAFPROC)
1090 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1091 argblock, because argblock uses g14 implicitly. */
1093 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
1099 /* See if caller passes in an address to return value. */
1101 if (aggregate_value_p (DECL_RESULT (fndecl)))
1107 /* Can not use tail calls or make this a leaf routine if there is a non
1110 if (get_frame_size () != 0)
1113 /* I don't understand this condition, and do not think that it is correct.
1114 Apparently this is just checking whether the frame pointer is used, and
1115 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1118 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1119 if (GET_CODE (insn) == INSN
1120 && reg_mentioned_p (frame_pointer_rtx, insn))
1126 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1129 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1130 if (GET_CODE (insn) == CALL_INSN)
1136 /* Can not be a leaf routine if any non-call clobbered registers are
1137 used in this function. */
1140 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1141 if (regs_ever_live[i]
1142 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1144 /* Global registers. */
1145 if (i < 16 && i > 7 && i != 13)
1147 /* Local registers. */
1152 /* Now choose a leaf return register, if we can find one, and if it is
1153 OK for this to be a leaf routine. */
1155 i960_leaf_ret_reg = -1;
1157 if (optimize && leaf_proc_ok)
1159 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
1160 if (regs_ever_live[i] == 0)
1162 i960_leaf_ret_reg = i;
1163 regs_ever_live[i] = 1;
1168 /* Do this after choosing the leaf return register, so it will be listed
1169 if one was chosen. */
1171 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
1172 fprintf (file, "\t# Registers used: ");
1174 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1176 if (regs_ever_live[i])
1178 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
1180 if (i > 15 && j == 0)
1182 fprintf (file,"\n\t#\t\t ");
1188 fprintf (file, "\n");
1190 if (i960_leaf_ret_reg >= 0)
1192 /* Make it a leaf procedure. */
1194 if (TREE_PUBLIC (fndecl))
1195 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
1197 fprintf (file, "\t.leafproc\t");
1198 assemble_name (file, name);
1199 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
1200 ASM_OUTPUT_LABEL (file, name);
1201 fprintf (file, "\tlda Li960R%d,g14\n", ret_label);
1202 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
1203 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
1205 if (TARGET_C_SERIES)
1207 fprintf (file, "\tlda 0,g14\n");
1208 i960_last_insn_type = I_TYPE_MEM;
1212 fprintf (file, "\tmov 0,g14\n");
1213 i960_last_insn_type = I_TYPE_REG;
1218 ASM_OUTPUT_LABEL (file, name);
1219 i960_last_insn_type = I_TYPE_CTRL;
1223 /* Compute and return the frame size. */
1226 compute_frame_size (size)
1230 int outgoing_args_size = current_function_outgoing_args_size;
1232 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1233 as size is concerned. */
1234 actual_fsize = (size + 15) & -16;
1235 actual_fsize += (outgoing_args_size + 15) & -16;
1237 return actual_fsize;
1240 /* Here register group is range of registers which can be moved by
1241 one i960 instruction. */
1249 /* The following functions forms the biggest as possible register
1250 groups with registers in STATE. REGS contain states of the
1251 registers in range [start, finish_reg). The function returns the
1252 number of groups formed. */
1254 i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
1259 struct reg_group *reg_groups;
1264 for (i = start_reg; i < finish_reg; )
1266 if (regs [i] != state)
1271 else if (i % 2 != 0 || regs [i + 1] != state)
1272 reg_groups [nw].length = 1;
1273 else if (i % 4 != 0 || regs [i + 2] != state)
1274 reg_groups [nw].length = 2;
1275 else if (regs [i + 3] != state)
1276 reg_groups [nw].length = 3;
1278 reg_groups [nw].length = 4;
1279 reg_groups [nw].start_reg = i;
1280 i += reg_groups [nw].length;
1286 /* We sort register winodws in descending order by length. */
1288 i960_reg_group_compare (group1, group2)
1292 struct reg_group *w1 = group1;
1293 struct reg_group *w2 = group2;
1295 if (w1->length > w2->length)
1297 else if (w1->length < w2->length)
1303 /* Split the first register group in REG_GROUPS on subgroups one of
1304 which will contain SUBGROUP_LENGTH registers. The function
1305 returns new number of winodws. */
1307 i960_split_reg_group (reg_groups, nw, subgroup_length)
1308 struct reg_group *reg_groups;
1310 int subgroup_length;
1312 if (subgroup_length < reg_groups->length - subgroup_length)
1313 /* This guarantees correct alignments of the two subgroups for
1314 i960 (see spliting for the group length 2, 3, 4). More
1315 generalized algorithm would require splitting the group more
1317 subgroup_length = reg_groups->length - subgroup_length;
1318 /* More generalized algorithm would require to try merging
1319 subgroups here. But in case i960 it always results in failure
1320 because of register group alignment. */
1321 reg_groups[nw].length = reg_groups->length - subgroup_length;
1322 reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
1324 reg_groups->length = subgroup_length;
1325 qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare);
1329 /* Output code for the function prologue. */
1332 i960_function_prologue (file, size)
1336 register int i, j, nr;
1337 int n_saved_regs = 0;
1338 int n_remaining_saved_regs;
1340 int actual_fsize, offset;
1342 struct reg_group *g, *l;
1344 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1346 int regs[FIRST_PSEUDO_REGISTER];
1347 /* All global registers (which must be saved) divided by groups. */
1348 struct reg_group global_reg_groups [16];
1349 /* All local registers (which are available) divided by groups. */
1350 struct reg_group local_reg_groups [16];
1353 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1354 if (regs_ever_live[i]
1355 && ((! call_used_regs[i]) || (i > 7 && i < 12))
1356 /* No need to save the static chain pointer. */
1357 && ! (i == STATIC_CHAIN_REGNUM && current_function_needs_context))
1360 /* Count global registers that need saving. */
1367 n_remaining_saved_regs = n_saved_regs;
1369 epilogue_string[0] = '\0';
1371 if (profile_flag || profile_block_flag)
1373 /* When profiling, we may use registers 20 to 27 to save arguments, so
1374 they can't be used here for saving globals. J is the number of
1375 argument registers the mcount call will save. */
1376 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1379 for (i = 20; i <= j + 20; i++)
1383 gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups);
1384 lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups);
1385 qsort (global_reg_groups, gnw, sizeof (struct reg_group),
1386 i960_reg_group_compare);
1387 qsort (local_reg_groups, lnw, sizeof (struct reg_group),
1388 i960_reg_group_compare);
1389 for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;)
1391 if (g->length == l->length)
1393 fprintf (file, "\tmov%s %s,%s\n",
1394 ((g->length == 4) ? "q" :
1395 (g->length == 3) ? "t" :
1396 (g->length == 2) ? "l" : ""),
1397 reg_names[g->start_reg], reg_names[l->start_reg]);
1398 sprintf (tmpstr, "\tmov%s %s,%s\n",
1399 ((g->length == 4) ? "q" :
1400 (g->length == 3) ? "t" :
1401 (g->length == 2) ? "l" : ""),
1402 reg_names[l->start_reg], reg_names[g->start_reg]);
1403 strcat (epilogue_string, tmpstr);
1404 n_remaining_saved_regs -= g->length;
1405 for (i = 0; i < g->length; i++)
1407 regs [i + g->start_reg] = 1;
1408 regs [i + l->start_reg] = -1;
1409 regs_ever_live [i + l->start_reg] = 1;
1416 else if (g->length > l->length)
1417 gnw = i960_split_reg_group (g, gnw, l->length);
1419 lnw = i960_split_reg_group (l, lnw, g->length);
1422 actual_fsize = compute_frame_size (size);
1424 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1425 size up to the nearest multiple of 16. I don't know whether this is
1426 necessary, or even desirable.
1428 The frame pointer must be aligned, but the call instruction takes care of
1429 that. If we leave the stack pointer unaligned, we may save a little on
1430 dynamic stack allocation. And we don't lose, at least according to the
1432 actual_fsize = (actual_fsize + 15) & ~0xF;
1435 /* Check stack limit if necessary. */
1436 if (current_function_limit_stack)
1438 rtx min_stack = stack_limit_rtx;
1439 if (actual_fsize != 0)
1440 min_stack = plus_constant (stack_limit_rtx, -actual_fsize);
1442 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1443 into an arith_operand. Use register 20 as the temporary. */
1444 if (legitimate_address_p (Pmode, min_stack, 1)
1445 && !arith_operand (min_stack, Pmode))
1447 rtx tmp = gen_rtx_MEM (Pmode, min_stack);
1448 fputs ("\tlda\t", file);
1449 i960_print_operand (file, tmp, 0);
1450 fputs (",r4\n", file);
1451 min_stack = gen_rtx_REG (Pmode, 20);
1453 if (arith_operand (min_stack, Pmode))
1455 fputs ("\tcmpo\tsp,", file);
1456 i960_print_operand (file, min_stack, 0);
1457 fputs ("\n\tfaultge.f\n", file);
1460 warning ("stack limit expression is not supported");
1463 /* Allocate space for register save and locals. */
1464 if (actual_fsize > 0)
1466 if (actual_fsize < 32)
1467 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1469 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1472 /* Take hardware register save area created by the call instruction
1473 into account, but store them before the argument block area. */
1474 lvar_size = actual_fsize - compute_frame_size (0) - n_saved_regs * 4;
1475 offset = STARTING_FRAME_OFFSET + lvar_size;
1476 /* Save registers on stack if needed. */
1477 /* ??? Is it worth to use the same algorithm as one for saving
1478 global registers in local registers? */
1479 for (i = 0, j = n_remaining_saved_regs; j > 0 && i < 16; i++)
1486 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1489 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1493 if (nr == 3 && regs[i+3] == -1)
1496 fprintf (file,"\tst%s %s,%d(fp)\n",
1499 (nr == 2) ? "l" : ""),
1500 reg_names[i], offset);
1501 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1504 (nr == 2) ? "l" : ""),
1505 offset, reg_names[i]);
1506 strcat (epilogue_string, tmpstr);
1512 if (actual_fsize == 0)
1515 fprintf (file, "\t#Prologue stats:\n");
1516 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1519 fprintf (file, "\t# Local Variable Size: %d bytes\n", lvar_size);
1521 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1522 n_saved_regs, n_saved_regs * 4);
1523 fprintf (file, "\t#End Prologue#\n");
1526 /* Output code for the function profiler. */
1529 output_function_profiler (file, labelno)
1533 /* The last used parameter register. */
1535 int i, j, increment;
1536 int varargs_stdarg_function
1537 = VARARGS_STDARG_FUNCTION (current_function_decl);
1539 /* Figure out the last used parameter register. The proper thing to do
1540 is to walk incoming args of the function. A function might have live
1541 parameter registers even if it has no incoming args. Note that we
1542 don't have to save parameter registers g8 to g11 because they are
1545 /* See also output_function_prologue, which tries to use local registers
1546 for preserved call-saved global registers. */
1548 for (last_parm_reg = 7;
1549 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1553 /* Save parameter registers in regs r4 (20) to r11 (27). */
1555 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1557 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1559 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1561 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1566 fprintf (file, "\tmov%s g%d,r%d\n",
1567 (increment == 4 ? "q" : increment == 3 ? "t"
1568 : increment == 2 ? "l": ""), i, j);
1571 /* If this function uses the arg pointer, then save it in r3 and then
1574 if (current_function_args_size != 0 || varargs_stdarg_function)
1575 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1577 /* Load location address into g0 and call mcount. */
1579 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1581 /* If this function uses the arg pointer, restore it. */
1583 if (current_function_args_size != 0 || varargs_stdarg_function)
1584 fprintf (file, "\tmov r3,g14\n");
1586 /* Restore parameter registers. */
1588 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1590 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1592 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1594 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1599 fprintf (file, "\tmov%s r%d,g%d\n",
1600 (increment == 4 ? "q" : increment == 3 ? "t"
1601 : increment == 2 ? "l": ""), j, i);
1605 /* Output code for the function epilogue. */
1608 i960_function_epilogue (file, size)
1612 if (i960_leaf_ret_reg >= 0)
1614 fprintf (file, "Li960R%d: ret\n", ret_label);
1618 if (*epilogue_string == 0)
1622 /* Emit a return insn, but only if control can fall through to here. */
1624 tmp = get_last_insn ();
1627 if (GET_CODE (tmp) == BARRIER)
1629 if (GET_CODE (tmp) == CODE_LABEL)
1631 if (GET_CODE (tmp) == JUMP_INSN)
1633 if (GET_CODE (PATTERN (tmp)) == RETURN)
1637 if (GET_CODE (tmp) == NOTE)
1639 tmp = PREV_INSN (tmp);
1644 fprintf (file, "Li960R%d: ret\n", ret_label);
1648 fprintf (file, "Li960R%d:\n", ret_label);
1650 fprintf (file, "\t#EPILOGUE#\n");
1652 /* Output the string created by the prologue which will restore all
1653 registers saved by the prologue. */
1655 if (epilogue_string[0] != '\0')
1656 fprintf (file, "%s", epilogue_string);
1658 /* Must clear g14 on return if this function set it.
1659 Only varargs/stdarg functions modify g14. */
1661 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1662 fprintf (file, "\tmov 0,g14\n");
1664 fprintf (file, "\tret\n");
1665 fprintf (file, "\t#End Epilogue#\n");
1668 /* Output code for a call insn. */
1671 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1672 register rtx target, argsize_rtx, arg_pointer, insn;
1674 int argsize = INTVAL (argsize_rtx);
1675 rtx nexti = next_real_insn (insn);
1677 int varargs_stdarg_function
1678 = VARARGS_STDARG_FUNCTION (current_function_decl);
1680 operands[0] = target;
1681 operands[1] = arg_pointer;
1683 if (current_function_args_size != 0 || varargs_stdarg_function)
1684 output_asm_insn ("mov g14,r3", operands);
1687 output_asm_insn ("lda %a1,g14", operands);
1688 else if (current_function_args_size != 0 || varargs_stdarg_function)
1689 output_asm_insn ("mov 0,g14", operands);
1691 /* The code used to assume that calls to SYMBOL_REFs could not be more
1692 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1693 feature is now implemented by relaxing in the GNU linker. It can convert
1694 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1696 /* Nexti could be zero if the called routine is volatile. */
1697 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1698 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1700 /* Delete following return insn. */
1701 if (nexti && no_labels_between_p (insn, nexti))
1702 delete_insn (nexti);
1703 output_asm_insn ("bx %0", operands);
1704 return "# notreached";
1707 output_asm_insn ("callx %0", operands);
1709 /* If the caller sets g14 to the address of the argblock, then the caller
1710 must clear it after the return. */
1712 if (current_function_args_size != 0 || varargs_stdarg_function)
1713 output_asm_insn ("mov r3,g14", operands);
1714 else if (argsize > 48)
1715 output_asm_insn ("mov 0,g14", operands);
1720 /* Output code for a return insn. */
1723 i960_output_ret_insn (insn)
1726 static char lbuf[20];
1728 if (*epilogue_string != 0)
1730 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1733 sprintf (lbuf, "b Li960R%d", ret_label);
1737 /* Must clear g14 on return if this function set it.
1738 Only varargs/stdarg functions modify g14. */
1740 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1741 output_asm_insn ("mov 0,g14", 0);
1743 if (i960_leaf_ret_reg >= 0)
1745 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1752 /* Return a character string representing the branch prediction
1753 opcode to be tacked on an instruction. This must at least
1754 return a null string. */
1757 i960_br_predict_opcode (lab_ref, insn)
1760 if (TARGET_BRANCH_PREDICT)
1762 unsigned long label_uid;
1764 if (GET_CODE (lab_ref) == CODE_LABEL)
1765 label_uid = INSN_UID (lab_ref);
1766 else if (GET_CODE (lab_ref) == LABEL_REF)
1767 label_uid = INSN_UID (XEXP (lab_ref, 0));
1771 /* If not optimizing, then the insn_addresses array will not be
1772 valid. In this case, always return ".t" since most branches
1773 are taken. If optimizing, return .t for backward branches
1774 and .f for forward branches. */
1776 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1785 /* Print the operand represented by rtx X formatted by code CODE. */
1788 i960_print_operand (file, x, code)
1793 enum rtx_code rtxcode = GET_CODE (x);
1800 /* Second reg of a double or quad. */
1801 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1805 /* Third reg of a quad. */
1806 fprintf (file, "%s", reg_names[REGNO (x)+2]);
1810 /* Fourth reg of a quad. */
1811 fprintf (file, "%s", reg_names[REGNO (x)+3]);
1815 fprintf (file, "%s", reg_names[REGNO (x)]);
1823 else if (rtxcode == MEM)
1825 output_address (XEXP (x, 0));
1828 else if (rtxcode == CONST_INT)
1830 HOST_WIDE_INT val = INTVAL (x);
1833 if (val > 9999 || val < -999)
1834 fprintf (file, "0x%x", val);
1836 fprintf (file, "%d", val);
1839 else if (rtxcode == CONST_DOUBLE)
1844 if (x == CONST0_RTX (GET_MODE (x)))
1846 fprintf (file, "0f0.0");
1849 else if (x == CONST1_RTX (GET_MODE (x)))
1851 fprintf (file, "0f1.0");
1855 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1856 REAL_VALUE_TO_DECIMAL (d, "%#g", dstr);
1857 fprintf (file, "0f%s", dstr);
1864 /* Branch or jump, depending on assembler. */
1865 if (TARGET_ASM_COMPAT)
1872 /* Sign of condition. */
1873 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1874 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1876 else if ((rtxcode == GT) || (rtxcode == LT)
1877 || (rtxcode == GE) || (rtxcode == LE))
1884 /* Inverted condition. */
1885 rtxcode = reverse_condition (rtxcode);
1889 /* Inverted condition w/ reversed operands. */
1890 rtxcode = reverse_condition (rtxcode);
1894 /* Reversed operand condition. */
1895 rtxcode = swap_condition (rtxcode);
1899 /* Normal condition. */
1901 if (rtxcode == EQ) { fputs ("e", file); return; }
1902 else if (rtxcode == NE) { fputs ("ne", file); return; }
1903 else if (rtxcode == GT) { fputs ("g", file); return; }
1904 else if (rtxcode == GTU) { fputs ("g", file); return; }
1905 else if (rtxcode == LT) { fputs ("l", file); return; }
1906 else if (rtxcode == LTU) { fputs ("l", file); return; }
1907 else if (rtxcode == GE) { fputs ("ge", file); return; }
1908 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1909 else if (rtxcode == LE) { fputs ("le", file); return; }
1910 else if (rtxcode == LEU) { fputs ("le", file); return; }
1915 output_addr_const (file, x);
1925 /* Print a memory address as an operand to reference that memory location.
1927 This is exactly the same as legitimate_address_p, except that it the prints
1928 addresses instead of recognizing them. */
1931 i960_print_operand_addr (file, addr)
1943 if (GET_CODE (addr) == REG)
1945 else if (CONSTANT_P (addr))
1947 else if (GET_CODE (addr) == PLUS)
1951 op0 = XEXP (addr, 0);
1952 op1 = XEXP (addr, 1);
1954 if (GET_CODE (op0) == REG)
1957 if (GET_CODE (op1) == REG)
1959 else if (CONSTANT_P (op1))
1964 else if (GET_CODE (op0) == PLUS)
1966 if (GET_CODE (XEXP (op0, 0)) == MULT)
1968 ireg = XEXP (XEXP (op0, 0), 0);
1969 scale = XEXP (XEXP (op0, 0), 1);
1970 if (GET_CODE (XEXP (op0, 1)) == REG)
1972 breg = XEXP (op0, 1);
1978 else if (GET_CODE (XEXP (op0, 0)) == REG)
1980 breg = XEXP (op0, 0);
1981 if (GET_CODE (XEXP (op0, 1)) == REG)
1983 ireg = XEXP (op0, 1);
1992 else if (GET_CODE (op0) == MULT)
1994 ireg = XEXP (op0, 0);
1995 scale = XEXP (op0, 1);
1996 if (GET_CODE (op1) == REG)
1998 else if (CONSTANT_P (op1))
2006 else if (GET_CODE (addr) == MULT)
2008 ireg = XEXP (addr, 0);
2009 scale = XEXP (addr, 1);
2015 output_addr_const (file, offset);
2017 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
2019 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
2022 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2023 that is a valid memory address for an instruction.
2024 The MODE argument is the machine mode for the MEM expression
2025 that wants to use this address.
2027 On 80960, legitimate addresses are:
2029 disp (12 or 32 bit) ld foo,r0
2030 base + index ld (g0)[g1*1],r0
2031 base + displ ld 0xf00(g0),r0
2032 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
2033 index*scale + base ld (g0)[g1*4],r0
2034 index*scale + displ ld 0xf00[g1*4],r0
2035 index*scale ld [g1*4],r0
2036 index + base + displ ld 0xf00(g0)[g1*1],r0
2038 In each case, scale can be 1, 2, 4, 8, or 16. */
2040 /* This is exactly the same as i960_print_operand_addr, except that
2041 it recognizes addresses instead of printing them.
2043 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
2044 convert common non-canonical forms to canonical form so that they will
2047 /* These two macros allow us to accept either a REG or a SUBREG anyplace
2048 where a register is valid. */
2050 #define RTX_OK_FOR_BASE_P(X, STRICT) \
2051 ((GET_CODE (X) == REG \
2052 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
2053 || (GET_CODE (X) == SUBREG \
2054 && GET_CODE (SUBREG_REG (X)) == REG \
2055 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
2056 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
2058 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
2059 ((GET_CODE (X) == REG \
2060 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
2061 || (GET_CODE (X) == SUBREG \
2062 && GET_CODE (SUBREG_REG (X)) == REG \
2063 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
2064 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
2067 legitimate_address_p (mode, addr, strict)
2068 enum machine_mode mode;
2072 if (RTX_OK_FOR_BASE_P (addr, strict))
2074 else if (CONSTANT_P (addr))
2076 else if (GET_CODE (addr) == PLUS)
2080 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2083 op0 = XEXP (addr, 0);
2084 op1 = XEXP (addr, 1);
2086 if (RTX_OK_FOR_BASE_P (op0, strict))
2088 if (RTX_OK_FOR_INDEX_P (op1, strict))
2090 else if (CONSTANT_P (op1))
2095 else if (GET_CODE (op0) == PLUS)
2097 if (GET_CODE (XEXP (op0, 0)) == MULT)
2099 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
2100 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
2103 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
2104 && CONSTANT_P (op1))
2109 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
2111 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
2112 && CONSTANT_P (op1))
2120 else if (GET_CODE (op0) == MULT)
2122 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
2123 && SCALE_TERM_P (XEXP (op0, 1))))
2126 if (RTX_OK_FOR_BASE_P (op1, strict))
2128 else if (CONSTANT_P (op1))
2136 else if (GET_CODE (addr) == MULT)
2138 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2141 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
2142 && SCALE_TERM_P (XEXP (addr, 1)));
2148 /* Try machine-dependent ways of modifying an illegitimate address
2149 to be legitimate. If we find one, return the new, valid address.
2150 This macro is used in only one place: `memory_address' in explow.c.
2152 This converts some non-canonical addresses to canonical form so they
2153 can be recognized. */
2156 legitimize_address (x, oldx, mode)
2159 enum machine_mode mode;
2161 if (GET_CODE (x) == SYMBOL_REF)
2164 x = copy_to_reg (x);
2167 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2170 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2171 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2172 created by virtual register instantiation, register elimination, and
2173 similar optimizations. */
2174 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
2175 && GET_CODE (XEXP (x, 1)) == PLUS)
2176 x = gen_rtx_PLUS (Pmode,
2177 gen_rtx_PLUS (Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2178 XEXP (XEXP (x, 1), 1));
2180 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2181 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2182 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2183 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2184 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2185 && CONSTANT_P (XEXP (x, 1)))
2187 rtx constant, other;
2189 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2191 constant = XEXP (x, 1);
2192 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2194 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2196 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2197 other = XEXP (x, 1);
2203 x = gen_rtx_PLUS (Pmode,
2204 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
2205 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2206 plus_constant (other, INTVAL (constant)));
2213 /* Return the most stringent alignment that we are willing to consider
2214 objects of size SIZE and known alignment ALIGN as having. */
2217 i960_alignment (size, align)
2223 if (! TARGET_STRICT_ALIGN)
2224 if (TARGET_IC_COMPAT2_0 || align >= 4)
2226 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2237 hard_regno_mode_ok (regno, mode)
2239 enum machine_mode mode;
2245 case CCmode: case CC_UNSmode: case CC_CHKmode:
2248 case DImode: case DFmode:
2249 return (regno & 1) == 0;
2251 case TImode: case XFmode:
2252 return (regno & 3) == 0;
2258 else if (regno >= 32 && regno < 36)
2262 case SFmode: case DFmode: case XFmode:
2263 case SCmode: case DCmode:
2270 else if (regno == 36)
2274 case CCmode: case CC_UNSmode: case CC_CHKmode:
2281 else if (regno == 37)
2288 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2289 advantage of machine specific facts, such as knowing that the frame pointer
2290 is always 16 byte aligned. */
2293 i960_expr_alignment (x, size)
2302 switch (GET_CODE(x))
2307 if ((align & 0xf) == 0)
2309 else if ((align & 0x7) == 0)
2311 else if ((align & 0x3) == 0)
2313 else if ((align & 0x1) == 0)
2320 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
2321 i960_expr_alignment (XEXP (x, 1), size));
2325 /* If this is a valid program, objects are guaranteed to be
2326 correctly aligned for whatever size the reference actually is. */
2327 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2331 if (REGNO (x) == FRAME_POINTER_REGNUM)
2336 align = i960_expr_alignment (XEXP (x, 0));
2338 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2340 align = align << INTVAL (XEXP (x, 1));
2341 align = MIN (align, 16);
2346 align = (i960_expr_alignment (XEXP (x, 0), size) *
2347 i960_expr_alignment (XEXP (x, 1), size));
2349 align = MIN (align, 16);
2356 /* Return true if it is possible to reference both BASE and OFFSET, which
2357 have alignment at least as great as 4 byte, as if they had alignment valid
2358 for an object of size SIZE. */
2361 i960_improve_align (base, offset, size)
2368 /* We have at least a word reference to the object, so we know it has to
2369 be aligned at least to 4 bytes. */
2371 i = MIN (i960_expr_alignment (base, 4),
2372 i960_expr_alignment (offset, 4));
2376 /* We know the size of the request. If strict align is not enabled, we
2377 can guess that the alignment is OK for the requested size. */
2379 if (! TARGET_STRICT_ALIGN)
2380 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
2386 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2387 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2390 i960_si_ti (base, offset)
2394 return i960_improve_align (base, offset, 16);
2397 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2398 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2401 i960_si_di (base, offset)
2405 return i960_improve_align (base, offset, 8);
2408 /* Return raw values of size and alignment (in words) for the data
2409 type being accessed. These values will be rounded by the caller. */
2412 i960_arg_size_and_align (mode, type, size_out, align_out)
2413 enum machine_mode mode;
2420 /* Use formal alignment requirements of type being passed, except make
2421 it at least a word. If we don't have a type, this is a library call,
2422 and the parm has to be of scalar type. In this case, consider its
2423 formal alignment requirement to be its size in words. */
2425 if (mode == BLKmode)
2426 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2427 else if (mode == VOIDmode)
2429 /* End of parm list. */
2430 if (type == 0 || TYPE_MODE (type) != VOIDmode)
2435 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2439 /* ??? This is a hack to properly correct the alignment of XFmode
2440 values without affecting anything else. */
2446 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2447 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2455 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2456 Any arg that is bigger than 4 words is placed on the stack and all
2457 subsequent arguments are placed on the stack.
2459 Additionally, parameters with an alignment requirement stronger than
2460 a word must be aligned appropriately. Note that this means that a
2461 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2462 passed in an odd/even register pair. */
2464 /* Update CUM to advance past an argument described by MODE and TYPE. */
2467 i960_function_arg_advance (cum, mode, type, named)
2468 CUMULATIVE_ARGS *cum;
2469 enum machine_mode mode;
2475 i960_arg_size_and_align (mode, type, &size, &align);
2477 if (size > 4 || cum->ca_nstackparms != 0
2478 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2479 || MUST_PASS_IN_STACK (mode, type))
2481 /* Indicate that all the registers are in use, even if all are not,
2482 so va_start will compute the right value. */
2483 cum->ca_nregparms = NPARM_REGS;
2484 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2487 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2490 /* Return the register that the argument described by MODE and TYPE is
2491 passed in, or else return 0 if it is passed on the stack. */
2494 i960_function_arg (cum, mode, type, named)
2495 CUMULATIVE_ARGS *cum;
2496 enum machine_mode mode;
2503 i960_arg_size_and_align (mode, type, &size, &align);
2505 if (size > 4 || cum->ca_nstackparms != 0
2506 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2507 || MUST_PASS_IN_STACK (mode, type))
2509 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2514 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2515 ret = gen_rtx_REG (mode, cum->ca_nregparms);
2521 /* Floating-point support. */
2524 i960_output_long_double (file, value)
2526 REAL_VALUE_TYPE value;
2531 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
2532 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2535 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2536 value_long[0], dstr, value_long[1], value_long[2]);
2537 fprintf (file, "\t.word\t0x0\n");
2541 i960_output_double (file, value)
2543 REAL_VALUE_TYPE value;
2548 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
2549 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2551 fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2552 value_long[0], dstr, value_long[1]);
2556 i960_output_float (file, value)
2558 REAL_VALUE_TYPE value;
2563 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
2564 REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr);
2566 fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr);
2569 /* Return the number of bits that an object of size N bytes is aligned to. */
2572 i960_object_bytes_bitalign (n)
2576 else if (n > 4) n = 64;
2577 else if (n > 2) n = 32;
2578 else if (n > 1) n = 16;
2584 /* Compute the alignment for an aggregate type TSIZE.
2585 Alignment is MAX (greatest member alignment,
2586 MIN (pragma align, structure size alignment)). */
2589 i960_round_align (align, tsize)
2595 if (TREE_CODE (tsize) != INTEGER_CST)
2598 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2600 /* Handle #pragma align. */
2601 if (new_align > i960_maxbitalignment)
2602 new_align = i960_maxbitalignment;
2604 if (align < new_align)
2610 /* Do any needed setup for a varargs function. For the i960, we must
2611 create a register parameter block if one doesn't exist, and then copy
2612 all register parameters to memory. */
2615 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2616 CUMULATIVE_ARGS *cum;
2617 enum machine_mode mode;
2622 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2623 int first_reg = cum->ca_nregparms;
2625 /* Copy only unnamed register arguments to memory. If there are
2626 any stack parms, there are no unnamed arguments in registers, and
2627 an argument block was already allocated by the caller.
2628 Remember that any arg bigger than 4 words is passed on the stack as
2629 are all subsequent args.
2631 If there are no stack arguments but there are exactly NPARM_REGS
2632 registers, either there were no extra arguments or the caller
2633 allocated an argument block. */
2635 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
2637 rtx label = gen_label_rtx ();
2640 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2641 and we need to allocate a chunk to save the registers (if any
2642 arguments were passed on the stack the caller would allocate the
2643 48 bytes as well). We must allocate all 48 bytes (12*4) because
2644 va_start assumes it. */
2645 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2646 emit_jump_insn (gen_bne (label));
2647 emit_insn (gen_rtx_SET (VOIDmode, arg_pointer_rtx,
2648 stack_pointer_rtx));
2649 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2650 memory_address (SImode,
2651 plus_constant (stack_pointer_rtx,
2655 /* ??? Note that we unnecessarily store one extra register for stdarg
2656 fns. We could optimize this, but it's kept as for now. */
2657 regblock = gen_rtx_MEM (BLKmode,
2658 plus_constant (arg_pointer_rtx,
2660 MEM_ALIAS_SET (regblock) = get_varargs_alias_set ();
2661 move_block_from_reg (first_reg, regblock,
2662 NPARM_REGS - first_reg,
2663 (NPARM_REGS - first_reg) * UNITS_PER_WORD);
2667 /* Define the `__builtin_va_list' type for the ABI. */
2670 i960_build_va_list ()
2672 return build_array_type (unsigned_type_node,
2673 build_index_type (size_one_node));
2676 /* Implement `va_start' for varargs and stdarg. */
2679 i960_va_start (stdarg_p, valist, nextarg)
2680 int stdarg_p ATTRIBUTE_UNUSED;
2682 rtx nextarg ATTRIBUTE_UNUSED;
2684 tree s, t, base, num;
2686 /* The array type always decays to a pointer before we get here, so we
2687 can't use ARRAY_REF. */
2688 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2689 num = build1 (INDIRECT_REF, unsigned_type_node,
2690 build (PLUS_EXPR, unsigned_type_node, valist,
2691 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2693 s = make_tree (unsigned_type_node, arg_pointer_rtx);
2694 t = build (MODIFY_EXPR, unsigned_type_node, base, s);
2695 TREE_SIDE_EFFECTS (t) = 1;
2696 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2698 s = build_int_2 ((current_function_args_info.ca_nregparms
2699 + current_function_args_info.ca_nstackparms) * 4, 0);
2700 t = build (MODIFY_EXPR, unsigned_type_node, num, s);
2701 TREE_SIDE_EFFECTS (t) = 1;
2702 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2705 /* Implement `va_arg'. */
2708 i960_va_arg (valist, type)
2711 HOST_WIDE_INT siz, ali;
2712 tree base, num, pad, next, this, t1, t2, int48;
2715 /* The array type always decays to a pointer before we get here, so we
2716 can't use ARRAY_REF. */
2717 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2718 num = build1 (INDIRECT_REF, unsigned_type_node,
2719 build (PLUS_EXPR, unsigned_type_node, valist,
2720 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2722 /* Round up sizeof(type) to a word. */
2723 siz = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
2725 /* Round up alignment to a word. */
2726 ali = TYPE_ALIGN (type);
2727 if (ali < BITS_PER_WORD)
2728 ali = BITS_PER_WORD;
2729 ali /= BITS_PER_UNIT;
2731 /* Align NUM appropriate for the argument. */
2732 pad = fold (build (PLUS_EXPR, unsigned_type_node, num,
2733 build_int_2 (ali - 1, 0)));
2734 pad = fold (build (BIT_AND_EXPR, unsigned_type_node, pad,
2735 build_int_2 (-ali, -1)));
2736 pad = save_expr (pad);
2738 /* Increment VPAD past this argument. */
2739 next = fold (build (PLUS_EXPR, unsigned_type_node, pad,
2740 build_int_2 (siz, 0)));
2741 next = save_expr (next);
2743 /* Find the offset for the current argument. Mind peculiar overflow
2744 from registers to stack. */
2745 int48 = build_int_2 (48, 0);
2747 t2 = integer_one_node;
2749 t2 = fold (build (GT_EXPR, integer_type_node, next, int48));
2750 t1 = fold (build (LE_EXPR, integer_type_node, num, int48));
2751 t1 = fold (build (TRUTH_AND_EXPR, integer_type_node, t1, t2));
2752 this = fold (build (COND_EXPR, unsigned_type_node, t1, int48, pad));
2754 /* Find the address for the current argument. */
2755 t1 = fold (build (PLUS_EXPR, unsigned_type_node, base, this));
2756 t1 = build1 (NOP_EXPR, ptr_type_node, t1);
2757 addr_rtx = expand_expr (t1, NULL_RTX, Pmode, EXPAND_NORMAL);
2759 /* Increment NUM. */
2760 t1 = build (MODIFY_EXPR, unsigned_type_node, num, next);
2761 TREE_SIDE_EFFECTS (t1) = 1;
2762 expand_expr (t1, const0_rtx, VOIDmode, EXPAND_NORMAL);
2767 /* Calculate the final size of the reg parm stack space for the current
2768 function, based on how many bytes would be allocated on the stack. */
2771 i960_final_reg_parm_stack_space (const_size, var_size)
2775 if (var_size || const_size > 48)
2781 /* Calculate the size of the reg parm stack space. This is a bit complicated
2785 i960_reg_parm_stack_space (fndecl)
2788 /* In this case, we are called from emit_library_call, and we don't need
2789 to pretend we have more space for parameters than what's apparent. */
2793 /* In this case, we are called from locate_and_pad_parms when we're
2794 not IN_REGS, so we have an arg block. */
2795 if (fndecl != current_function_decl)
2798 /* Otherwise, we have an arg block if the current function has more than
2799 48 bytes of parameters. */
2800 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2806 /* Return the register class of a scratch register needed to copy IN into
2807 or out of a register in CLASS in MODE. If it can be done directly,
2808 NO_REGS is returned. */
2811 secondary_reload_class (class, mode, in)
2812 enum reg_class class;
2813 enum machine_mode mode;
2818 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2819 regno = true_regnum (in);
2821 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2822 LOCAL_OR_GLOBAL_REGS into anything. */
2823 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2824 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2827 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2828 if (class == FP_REGS
2829 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2830 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2833 return LOCAL_OR_GLOBAL_REGS;
2836 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2837 function unit it executed on. */
2839 /* ??? This would make more sense as an attribute. */
2842 i960_scan_opcode (p)
2854 /* Ret is not actually of type REG, but it won't matter, because no
2855 insn will ever follow it. */
2858 i960_last_insn_type = I_TYPE_REG;
2862 if (p[1] == 'x' || p[3] == 'x')
2863 i960_last_insn_type = I_TYPE_MEM;
2864 i960_last_insn_type = I_TYPE_CTRL;
2869 i960_last_insn_type = I_TYPE_CTRL;
2876 i960_last_insn_type = I_TYPE_MEM;
2878 i960_last_insn_type = I_TYPE_CTRL;
2880 else if (p[1] == 'm')
2883 i960_last_insn_type = I_TYPE_REG;
2884 else if (p[4] == 'b' || p[4] == 'j')
2885 i960_last_insn_type = I_TYPE_CTRL;
2887 i960_last_insn_type = I_TYPE_REG;
2890 i960_last_insn_type = I_TYPE_REG;
2894 i960_last_insn_type = I_TYPE_MEM;
2899 i960_last_insn_type = I_TYPE_MEM;
2901 i960_last_insn_type = I_TYPE_REG;