1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Steven McGeady, Intel Corp.
4 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 #include "insn-codes.h"
44 /* Save the operands last given to a compare for use when we
45 generate a scc or bcc insn. */
47 rtx i960_compare_op0, i960_compare_op1;
49 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
52 static int i960_maxbitalignment;
53 static int i960_last_maxbitalignment;
55 /* Used to implement switching between MEM and ALU insn types, for better
56 C series performance. */
58 enum insn_types i960_last_insn_type;
60 /* The leaf-procedure return register. Set only if this is a leaf routine. */
62 static int i960_leaf_ret_reg;
64 /* True if replacing tail calls with jumps is OK. */
66 static int tail_call_ok;
68 /* A string containing a list of insns to emit in the epilogue so as to
69 restore all registers saved by the prologue. Created by the prologue
70 code as it saves registers away. */
72 char epilogue_string[1000];
74 /* A unique number (per function) for return labels. */
76 static int ret_label = 0;
79 /* Handle pragmas for compatibility with Intel's compilers. */
81 /* ??? This is incomplete, since it does not handle all pragmas that the
82 intel compilers understand. Also, it needs to be rewritten to accept
83 a stream instead of a string for GCC 2. */
92 if ((i = sscanf (str, " align %d", &align)) == 1)
95 case 0: /* Return to last alignment. */
96 align = i960_last_maxbitalignment / 8;
98 case 16: /* Byte alignments. */
103 i960_last_maxbitalignment = i960_maxbitalignment;
104 i960_maxbitalignment = align * 8;
107 default: /* Unknown, silently ignore. */
111 /* NOTE: ic960 R3.0 pragma align definition:
113 #pragma align [(size)] | (identifier=size[,...])
114 #pragma noalign [(identifier)[,...]]
116 (all parens are optional)
118 - size is [1,2,4,8,16]
119 - noalign means size==1
120 - applies only to component elements of a struct (and union?)
121 - identifier applies to structure tag (only)
122 - missing identifier means next struct
124 - alignment rules for bitfields need more investigation */
126 /* Should be pragma 'far' or equivalent for callx/balx here. */
130 /* Initialize variables before compiling any files. */
135 if (TARGET_IC_COMPAT2_0)
137 i960_maxbitalignment = 8;
138 i960_last_maxbitalignment = 128;
142 i960_maxbitalignment = 128;
143 i960_last_maxbitalignment = 8;
147 /* Return true if OP can be used as the source of an fp move insn. */
150 fpmove_src_operand (op, mode)
152 enum machine_mode mode;
154 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
158 /* Return true if OP is a register or zero. */
161 reg_or_zero_operand (op, mode)
163 enum machine_mode mode;
165 return register_operand (op, mode) || op == const0_rtx;
169 /* Return truth value of whether OP can be used as an operands in a three
170 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
173 arith_operand (op, mode)
175 enum machine_mode mode;
177 return (register_operand (op, mode) || literal (op, mode));
180 /* Return true if OP is a register or a valid floating point literal. */
183 fp_arith_operand (op, mode)
185 enum machine_mode mode;
187 return (register_operand (op, mode) || fp_literal (op, mode));
190 /* Return true is OP is a register or a valid signed integer literal. */
193 signed_arith_operand (op, mode)
195 enum machine_mode mode;
197 return (register_operand (op, mode) || signed_literal (op, mode));
200 /* Return truth value of whether OP is a integer which fits the
201 range constraining immediate operands in three-address insns. */
206 enum machine_mode mode;
208 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
211 /* Return true if OP is a float constant of 1. */
214 fp_literal_one (op, mode)
216 enum machine_mode mode;
218 return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op))
219 && (op == CONST1_RTX (mode)));
222 /* Return true if OP is a float constant of 0. */
225 fp_literal_zero (op, mode)
227 enum machine_mode mode;
229 return (TARGET_NUMERICS && (mode == VOIDmode || mode == GET_MODE (op))
230 && (op == CONST0_RTX (mode)));
233 /* Return true if OP is a valid floating point literal. */
238 enum machine_mode mode;
240 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
243 /* Return true if OP is a valid signed immediate constant. */
246 signed_literal(op, mode)
248 enum machine_mode mode;
250 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
253 /* Return truth value of statement that OP is a symbolic memory
254 operand of mode MODE. */
257 symbolic_memory_operand (op, mode)
259 enum machine_mode mode;
261 if (GET_CODE (op) == SUBREG)
262 op = SUBREG_REG (op);
263 if (GET_CODE (op) != MEM)
266 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
267 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
270 /* Return truth value of whether OP is EQ or NE. */
275 enum machine_mode mode;
277 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
280 /* OP is an integer register or a constant. */
283 arith32_operand (op, mode)
285 enum machine_mode mode;
287 if (register_operand (op, mode))
289 return (CONSTANT_P (op));
292 /* Return true if OP is an integer constant which is a power of 2. */
295 power2_operand (op,mode)
297 enum machine_mode mode;
299 if (GET_CODE (op) != CONST_INT)
302 return exact_log2 (INTVAL (op)) >= 0;
305 /* Return true if OP is an integer constant which is the complement of a
309 cmplpower2_operand (op, mode)
311 enum machine_mode mode;
313 if (GET_CODE (op) != CONST_INT)
316 return exact_log2 (~ INTVAL (op)) >= 0;
319 /* If VAL has only one bit set, return the index of that bit. Otherwise
328 for (i = 0; val != 0; i++, val >>= 1)
340 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
341 The return value indicates how many consecutive non-zero bits exist
342 if this is a mask. This is the same as the next function, except that
343 it does not indicate what the start and stop bit positions are. */
349 register int start, end, i;
352 for (i = 0; val != 0; val >>= 1, i++)
362 /* Still looking for the first bit. */
366 /* We've seen the start of a bit sequence, and now a zero. There
367 must be more one bits, otherwise we would have exited the loop.
368 Therefore, it is not a mask. */
373 /* The bit string has ones from START to END bit positions only. */
374 return end - start + 1;
377 /* If VAL is a mask, then return nonzero, with S set to the starting bit
378 position and E set to the ending bit position of the mask. The return
379 value indicates how many consecutive bits exist in the mask. This is
380 the same as the previous function, except that it also indicates the
381 start and end bit positions of the mask. */
388 register int start, end, i;
392 for (i = 0; val != 0; val >>= 1, i++)
403 /* Still looking for the first bit. */
407 /* We've seen the start of a bit sequence, and now a zero. There
408 must be more one bits, otherwise we would have exited the loop.
409 Therefor, it is not a mask. */
418 /* The bit string has ones from START to END bit positions only. */
421 return ((start < 0) ? 0 : end - start + 1);
424 /* Return the machine mode to use for a comparison. */
427 select_cc_mode (op, x)
431 if (op == GTU || op == LTU || op == GEU || op == LEU)
436 /* X and Y are two things to compare using CODE. Emit the compare insn and
437 return the rtx for register 36 in the proper mode. */
440 gen_compare_reg (code, x, y)
445 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
446 enum machine_mode mode
447 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
451 if (! arith_operand (x, mode))
452 x = force_reg (SImode, x);
453 if (! arith_operand (y, mode))
454 y = force_reg (SImode, y);
457 cc_reg = gen_rtx (REG, ccmode, 36);
458 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
459 gen_rtx (COMPARE, ccmode, x, y)));
464 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
465 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
466 are 4. Indexed addresses are cost 6. */
468 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
471 i960_address_cost (x)
475 /* Handled before calling here. */
476 if (GET_CODE (x) == REG)
479 if (GET_CODE (x) == PLUS)
481 rtx base = XEXP (x, 0);
482 rtx offset = XEXP (x, 1);
484 if (GET_CODE (base) == SUBREG)
485 base = SUBREG_REG (base);
486 if (GET_CODE (offset) == SUBREG)
487 offset = SUBREG_REG (offset);
489 if (GET_CODE (base) == REG)
491 if (GET_CODE (offset) == REG)
493 if (GET_CODE (offset) == CONST_INT)
495 if ((unsigned)INTVAL (offset) < 2047)
499 if (CONSTANT_P (offset))
502 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
505 /* This is an invalid address. The return value doesn't matter, but
506 for convenience we make this more expensive than anything else. */
509 if (GET_CODE (x) == MULT)
512 /* Symbol_refs and other unrecognized addresses are cost 4. */
516 /* Emit insns to move operands[1] into operands[0].
518 Return 1 if we have written out everything that needs to be done to
519 do the move. Otherwise, return 0 and the caller will emit the move
523 emit_move_sequence (operands, mode)
525 enum machine_mode mode;
527 register rtx operand0 = operands[0];
528 register rtx operand1 = operands[1];
530 /* We can only store registers to memory. */
532 if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG)
533 operands[1] = force_reg (mode, operand1);
538 /* Emit insns to load a constant. Uses several strategies to try to use
539 as few insns as possible. */
542 i960_output_ldconst (dst, src)
543 register rtx dst, src;
546 register unsigned rsrc2;
547 enum machine_mode mode = GET_MODE (dst);
549 union { long l[2]; double d; } x;
551 operands[0] = operands[2] = dst;
552 operands[1] = operands[3] = src;
554 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
555 must be a ldconst insn. */
557 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
559 output_asm_insn ("ldconst %1,%0", operands);
562 else if (mode == DFmode)
566 if (fp_literal_zero (src, VOIDmode))
569 return "movrl %1,%0";
574 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
575 split_double (src, &first, &second);
577 output_asm_insn ("# ldconst %1,%0",operands);
579 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
581 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
583 operands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
584 operands[1] = second;
585 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
589 if (fp_literal_one (src, VOIDmode))
590 return "movrl 0f1.0,%0";
591 fatal ("inline double constants not supported on this host");
594 else if (mode == TImode)
596 /* ??? This is currently not handled at all. */
599 /* Note: lowest order word goes in lowest numbered reg. */
600 rsrc1 = INTVAL (src);
601 if (rsrc1 >= 0 && rsrc1 < 32)
604 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
605 /* Go pick up the low-order word. */
607 else if (mode == DImode)
609 rtx upperhalf, lowerhalf, xoperands[2];
612 if (GET_CODE (src) == CONST_DOUBLE)
614 upperhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (src));
615 lowerhalf = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (src));
617 else if (GET_CODE (src) == CONST_INT)
620 upperhalf = INTVAL (src) < 0 ? constm1_rtx : const0_rtx;
625 /* Note: lowest order word goes in lowest numbered reg. */
626 /* Numbers from 0 to 31 can be handled with a single insn. */
627 rsrc1 = INTVAL (lowerhalf);
628 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
631 /* Output the upper half with a recursive call. */
632 xoperands[0] = gen_rtx (REG, SImode, REGNO (dst) + 1);
633 xoperands[1] = upperhalf;
634 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
636 /* The lower word is emitted as normally. */
638 else if (mode == SFmode)
640 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT
644 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
645 REAL_VALUE_TO_TARGET_SINGLE (d, value);
647 output_asm_insn ("# ldconst %1,%0",operands);
648 operands[0] = gen_rtx (REG, SImode, REGNO (dst));
649 operands[1] = gen_rtx (CONST_INT, VOIDmode, value);
650 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
653 if (fp_literal_zero (src, VOIDmode))
654 return "movr 0f0.0,%0";
655 if (fp_literal_one (src, VOIDmode))
656 return "movr 0f1.0,%0";
657 fatal ("inline float constants not supported on this host");
663 rsrc1 = INTVAL (src);
669 else if (mode == HImode)
678 /* ldconst 0..31,X -> mov 0..31,X */
681 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
686 /* ldconst 32..63,X -> add 31,nn,X */
689 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
691 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31);
692 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
698 /* ldconst -1..-31 -> sub 0,0..31,X */
701 /* return 'sub -(%1),0,%0' */
702 operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1);
703 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
707 /* ldconst -32 -> not 31,X */
710 operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1);
711 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
716 /* If const is a single bit. */
717 if (bitpos (rsrc1) >= 0)
719 operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1));
720 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
724 /* If const is a bit string of less than 6 bits (1..31 shifted). */
729 if (bitstr (rsrc1, &s, &e) < 6)
731 rsrc2 = ((unsigned int) rsrc1) >> s;
732 operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2);
733 operands[2] = gen_rtx (CONST_INT, VOIDmode, s);
734 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
739 /* Unimplemented cases:
740 const is in range 0..31 but rotated around end of word:
741 ror 31,3,g0 -> ldconst 0xe0000003,g0
743 and any 2 instruction cases that might be worthwhile */
745 output_asm_insn ("ldconst %1,%0", operands);
749 /* Determine if there is an opportunity for a bypass optimization.
750 Bypass succeeds on the 960K* if the destination of the previous
751 instruction is the second operand of the current instruction.
752 Bypass always succeeds on the C*.
754 Return 1 if the pattern should interchange the operands.
756 CMPBR_FLAG is true if this is for a compare-and-branch insn.
757 OP1 and OP2 are the two source operands of a 3 operand insn. */
760 i960_bypass (insn, op1, op2, cmpbr_flag)
761 register rtx insn, op1, op2;
764 register rtx prev_insn, prev_dest;
769 /* Can't do this if op1 isn't a register. */
773 /* Can't do this for a compare-and-branch if both ops aren't regs. */
774 if (cmpbr_flag && ! REG_P (op2))
777 prev_insn = prev_real_insn (insn);
779 if (prev_insn && GET_CODE (prev_insn) == INSN
780 && GET_CODE (PATTERN (prev_insn)) == SET)
782 prev_dest = SET_DEST (PATTERN (prev_insn));
783 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
784 || (GET_CODE (prev_dest) == SUBREG
785 && GET_CODE (SUBREG_REG (prev_dest)) == REG
786 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
792 /* Output the code which declares the function name. This also handles
793 leaf routines, which have special requirements, and initializes some
797 i960_function_name_declare (file, name, fndecl)
806 /* Increment global return label. */
810 /* Compute whether tail calls and leaf routine optimizations can be performed
811 for this function. */
823 /* Even if nobody uses extra parms, can't have leafroc or tail calls if
824 argblock, because argblock uses g14 implicitly. */
826 if (current_function_args_size != 0)
832 /* See if caller passes in an address to return value. */
834 if (aggregate_value_p (DECL_RESULT (fndecl)))
840 /* Can not use tail calls or make this a leaf routine if there is a non
843 if (get_frame_size () != 0)
846 /* I don't understand this condition, and do not think that it is correct.
847 Apparently this is just checking whether the frame pointer is used, and
848 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
851 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
852 if (GET_CODE (insn) == INSN
853 && reg_mentioned_p (frame_pointer_rtx, insn))
859 /* Check for CALL insns. Can not be a leaf routine if there are any. */
862 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
863 if (GET_CODE (insn) == CALL_INSN)
869 /* Can not be a leaf routine if any non-call clobbered registers are
870 used in this function. */
873 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
874 if (regs_ever_live[i]
875 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
877 /* Global registers. */
878 if (i < 16 && i > 7 && i != 13)
880 /* Local registers. */
885 /* Now choose a leaf return register, if we can find one, and if it is
886 OK for this to be a leaf routine. */
888 i960_leaf_ret_reg = -1;
890 if (optimize && leaf_proc_ok)
892 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
893 if (regs_ever_live[i] == 0)
895 i960_leaf_ret_reg = i;
896 regs_ever_live[i] = 1;
901 /* Do this after choosing the leaf return register, so it will be listed
902 if one was chosen. */
904 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
905 fprintf (file, "\t# Registers used: ");
907 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
909 if (regs_ever_live[i])
911 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
913 if (i > 15 && j == 0)
915 fprintf (file,"\n\t#\t\t ");
921 fprintf (file, "\n");
923 if (i960_leaf_ret_reg >= 0)
925 /* Make it a leaf procedure. */
927 if (TREE_PUBLIC (fndecl))
928 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
930 fprintf (file, "\t.leafproc\t");
931 assemble_name (file, name);
932 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
933 ASM_OUTPUT_LABEL (file, name);
934 fprintf (file, "\tlda LR%d,g14\n", ret_label);
935 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
936 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
940 fprintf (file, "\tlda 0,g14\n");
941 i960_last_insn_type = I_TYPE_MEM;
945 fprintf (file, "\tmov 0,g14\n");
946 i960_last_insn_type = I_TYPE_REG;
951 ASM_OUTPUT_LABEL (file, name);
952 i960_last_insn_type = I_TYPE_CTRL;
956 /* Compute and return the frame size. */
959 compute_frame_size (size)
963 int outgoing_args_size
964 = current_function_outgoing_args_size + current_function_pretend_args_size;
966 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
967 as size is concerned. */
968 actual_fsize = (size + 15) & -16;
969 actual_fsize += (outgoing_args_size + 15) & -16;
974 /* Output code for the function prologue. */
977 i960_function_prologue (file, size)
981 register int i, j, nr;
984 int actual_fsize, offset;
986 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
988 int regs[FIRST_PSEUDO_REGISTER];
990 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
991 if (regs_ever_live[i]
992 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
995 /* Count global registers that need saving. */
1002 epilogue_string[0] = '\0';
1004 if (profile_flag || profile_block_flag)
1006 /* When profiling, we may use registers 20 to 27 to save arguments, so
1007 they can't be used here for saving globals. J is the number of
1008 argument registers the mcount call will save. */
1009 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1012 for (i = 20; i <= j + 20; i++)
1016 /* First look for local registers to save globals in. */
1017 for (i = 0; i < 16; i++)
1022 /* Start at r4, not r3. */
1023 for (j = 20; j < 32; j++)
1030 regs_ever_live[j] = 1;
1032 if (i <= 14 && i % 2 == 0 && j <= 30 && j % 2 == 0
1033 && regs[i+1] != 0 && regs[j+1] == 0)
1038 regs_ever_live[j+1] = 1;
1040 if (nr == 2 && i <= 12 && i % 4 == 0 && j <= 28 && j % 4 == 0
1041 && regs[i+2] != 0 && regs[j+2] == 0)
1046 regs_ever_live[j+2] = 1;
1048 if (nr == 3 && regs[i+3] != 0 && regs[j+3] == 0)
1053 regs_ever_live[j+3] = 1;
1056 fprintf (file, "\tmov%s %s,%s\n",
1059 (nr == 2) ? "l" : ""),
1060 reg_names[i], reg_names[j]);
1061 sprintf (tmpstr, "\tmov%s %s,%s\n",
1064 (nr == 2) ? "l" : ""),
1065 reg_names[j], reg_names[i]);
1066 strcat (epilogue_string, tmpstr);
1074 /* N_iregs is now the number of global registers that haven't been saved
1077 rsize = (n_iregs * 4);
1078 actual_fsize = compute_frame_size (size) + rsize;
1080 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1081 size up to the nearest multiple of 16. I don't know whether this is
1082 necessary, or even desirable.
1084 The frame pointer must be aligned, but the call instruction takes care of
1085 that. If we leave the stack pointer unaligned, we may save a little on
1086 dynamic stack allocation. And we don't lose, at least according to the
1088 actual_fsize = (actual_fsize + 15) & ~0xF;
1091 /* Allocate space for register save and locals. */
1092 if (actual_fsize > 0)
1094 if (actual_fsize < 32)
1095 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1097 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1100 /* Take hardware register save area created by the call instruction
1101 into account, but store them before the argument block area. */
1102 offset = 64 + actual_fsize - compute_frame_size (0) - rsize;
1103 /* Save registers on stack if needed. */
1104 for (i = 0, j = n_iregs; j > 0 && i < 16; i++)
1111 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1114 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1118 if (nr == 3 && regs[i+3] == -1)
1121 fprintf (file,"\tst%s %s,%d(fp)\n",
1124 (nr == 2) ? "l" : ""),
1125 reg_names[i], offset);
1126 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1129 (nr == 2) ? "l" : ""),
1130 offset, reg_names[i]);
1131 strcat (epilogue_string, tmpstr);
1137 if (actual_fsize == 0 && size == 0 && rsize == 0)
1140 fprintf (file, "\t#Prologue stats:\n");
1141 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1144 fprintf (file, "\t# Local Variable Size: %d bytes\n", size);
1146 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1148 fprintf (file, "\t#End Prologue#\n");
1151 /* Output code for the function profiler. */
1154 output_function_profiler (file, labelno)
1158 /* The last used parameter register. */
1160 int i, j, increment;
1162 /* Figure out the last used parameter register. The proper thing to do
1163 is to walk incoming args of the function. A function might have live
1164 parameter registers even if it has no incoming args. Note that we
1165 don't have to save parameter registers g8 to g11 because they are
1168 /* See also output_function_prologue, which tries to use local registers
1169 for preserved call-saved global registers. */
1171 for (last_parm_reg = 7;
1172 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1176 /* Save parameter registers in regs r4 (20) to r11 (27). */
1178 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1180 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1182 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1184 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1189 fprintf (file, "\tmov%s g%d,r%d\n",
1190 (increment == 4 ? "q" : increment == 3 ? "t"
1191 : increment == 2 ? "l": ""), i, j);
1194 /* If this function uses the arg pointer, then save it in r3 and then
1197 if (current_function_args_size != 0)
1198 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1200 /* Load location address into g0 and call mcount. */
1202 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1204 /* If this function uses the arg pointer, restore it. */
1206 if (current_function_args_size != 0)
1207 fprintf (file, "\tmov r3,g14\n");
1209 /* Restore parameter registers. */
1211 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1213 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1215 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1217 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1222 fprintf (file, "\tmov%s r%d,g%d\n",
1223 (increment == 4 ? "q" : increment == 3 ? "t"
1224 : increment == 2 ? "l": ""), j, i);
1228 /* Output code for the function epilogue. */
1231 i960_function_epilogue (file, size)
1235 if (i960_leaf_ret_reg >= 0)
1237 fprintf (file, "LR%d: ret\n", ret_label);
1241 if (*epilogue_string == 0)
1245 /* Emit a return insn, but only if control can fall through to here. */
1247 tmp = get_last_insn ();
1250 if (GET_CODE (tmp) == BARRIER)
1252 if (GET_CODE (tmp) == CODE_LABEL)
1254 if (GET_CODE (tmp) == JUMP_INSN)
1256 if (GET_CODE (PATTERN (tmp)) == RETURN)
1260 if (GET_CODE (tmp) == NOTE)
1262 tmp = PREV_INSN (tmp);
1267 fprintf (file, "LR%d: ret\n", ret_label);
1271 fprintf (file, "LR%d:\n", ret_label);
1273 fprintf (file, "\t#EPILOGUE#\n");
1275 /* Output the string created by the prologue which will restore all
1276 registers saved by the prologue. */
1278 if (epilogue_string[0] != '\0')
1279 fprintf (file, "%s", epilogue_string);
1281 /* Must clear g14 on return. */
1283 if (current_function_args_size != 0)
1284 fprintf (file, "\tmov 0,g14\n");
1286 fprintf (file, "\tret\n");
1287 fprintf (file, "\t#End Epilogue#\n");
1290 /* Output code for a call insn. */
1293 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1294 register rtx target, argsize_rtx, arg_pointer, insn;
1296 int argsize = INTVAL (argsize_rtx);
1297 rtx nexti = next_real_insn (insn);
1300 operands[0] = target;
1301 operands[1] = arg_pointer;
1303 if (current_function_args_size != 0)
1304 output_asm_insn ("mov g14,r3", operands);
1307 output_asm_insn ("lda %a1,g14", operands);
1308 else if (current_function_args_size != 0)
1309 output_asm_insn ("mov 0,g14", operands);
1311 /* The code used to assume that calls to SYMBOL_REFs could not be more
1312 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1313 feature is now implemented by relaxing in the GNU linker. It can convert
1314 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1316 /* Nexti could be zero if the called routine is volatile. */
1317 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1318 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1320 /* Delete following return insn. */
1321 if (nexti && no_labels_between_p (insn, nexti))
1322 delete_insn (nexti);
1323 output_asm_insn ("bx %0", operands);
1324 return "# notreached";
1327 output_asm_insn ("callx %0", operands);
1329 if (current_function_args_size != 0)
1330 output_asm_insn ("mov r3,g14", operands);
1335 /* Output code for a return insn. */
1338 i960_output_ret_insn (insn)
1341 static char lbuf[20];
1343 if (*epilogue_string != 0)
1345 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1348 sprintf (lbuf, "b LR%d", ret_label);
1352 if (current_function_args_size != 0)
1353 output_asm_insn ("mov 0,g14", 0);
1355 if (i960_leaf_ret_reg >= 0)
1357 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1364 /* Return a character string representing the branch prediction
1365 opcode to be tacked on an instruction. This must at least
1366 return a null string. */
1369 i960_br_predict_opcode (lab_ref, insn)
1372 if (TARGET_BRANCH_PREDICT)
1374 unsigned long label_uid;
1376 if (GET_CODE (lab_ref) == CODE_LABEL)
1377 label_uid = INSN_UID (lab_ref);
1378 else if (GET_CODE (lab_ref) == LABEL_REF)
1379 label_uid = INSN_UID (XEXP (lab_ref, 0));
1383 /* If not optimizing, then the insn_addresses array will not be
1384 valid. In this case, always return ".t" since most branches
1385 are taken. If optimizing, return .t for backward branches
1386 and .f for forward branches. */
1388 || insn_addresses[label_uid] < insn_addresses[INSN_UID (insn)])
1397 /* Print the operand represented by rtx X formatted by code CODE. */
1400 i960_print_operand (file, x, code)
1405 enum rtx_code rtxcode = GET_CODE (x);
1412 /* Second reg of a double. */
1413 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1417 fprintf (file, "%s", reg_names[REGNO (x)]);
1425 else if (rtxcode == MEM)
1427 output_address (XEXP (x, 0));
1430 else if (rtxcode == CONST_INT)
1432 if (INTVAL (x) > 9999 || INTVAL (x) < -999)
1433 fprintf (file, "0x%x", INTVAL (x));
1435 fprintf (file, "%d", INTVAL (x));
1438 else if (rtxcode == CONST_DOUBLE)
1442 if (x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1444 fprintf (file, "0f0.0");
1447 else if (x == CONST1_RTX (DFmode) || x == CONST1_RTX (SFmode))
1449 fprintf (file, "0f1.0");
1453 /* This better be a comment. */
1454 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1455 fprintf (file, "%#g", d);
1462 /* Branch or jump, depending on assembler. */
1463 if (TARGET_ASM_COMPAT)
1470 /* Sign of condition. */
1471 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1472 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1474 else if ((rtxcode == GT) || (rtxcode == LT)
1475 || (rtxcode == GE) || (rtxcode == LE))
1482 /* Inverted condition. */
1483 rtxcode = reverse_condition (rtxcode);
1487 /* Inverted condition w/ reversed operands. */
1488 rtxcode = reverse_condition (rtxcode);
1492 /* Reversed operand condition. */
1493 rtxcode = swap_condition (rtxcode);
1497 /* Normal condition. */
1499 if (rtxcode == EQ) { fputs ("e", file); return; }
1500 else if (rtxcode == NE) { fputs ("ne", file); return; }
1501 else if (rtxcode == GT) { fputs ("g", file); return; }
1502 else if (rtxcode == GTU) { fputs ("g", file); return; }
1503 else if (rtxcode == LT) { fputs ("l", file); return; }
1504 else if (rtxcode == LTU) { fputs ("l", file); return; }
1505 else if (rtxcode == GE) { fputs ("ge", file); return; }
1506 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1507 else if (rtxcode == LE) { fputs ("le", file); return; }
1508 else if (rtxcode == LEU) { fputs ("le", file); return; }
1513 output_addr_const (file, x);
1523 /* Print a memory address as an operand to reference that memory location.
1525 This is exactly the same as legitimate_address_p, except that it the prints
1526 addresses instead of recognizing them. */
1529 i960_print_operand_addr (file, addr)
1541 if (GET_CODE (addr) == REG)
1543 else if (CONSTANT_P (addr))
1545 else if (GET_CODE (addr) == PLUS)
1549 op0 = XEXP (addr, 0);
1550 op1 = XEXP (addr, 1);
1552 if (GET_CODE (op0) == REG)
1555 if (GET_CODE (op1) == REG)
1557 else if (CONSTANT_P (op1))
1562 else if (GET_CODE (op0) == PLUS)
1564 if (GET_CODE (XEXP (op0, 0)) == MULT)
1566 ireg = XEXP (XEXP (op0, 0), 0);
1567 scale = XEXP (XEXP (op0, 0), 1);
1568 if (GET_CODE (XEXP (op0, 1)) == REG)
1570 breg = XEXP (op0, 1);
1576 else if (GET_CODE (XEXP (op0, 0)) == REG)
1578 breg = XEXP (op0, 0);
1579 if (GET_CODE (XEXP (op0, 1)) == REG)
1581 ireg = XEXP (op0, 1);
1590 else if (GET_CODE (op0) == MULT)
1592 ireg = XEXP (op0, 0);
1593 scale = XEXP (op0, 1);
1594 if (GET_CODE (op1) == REG)
1596 else if (CONSTANT_P (op1))
1604 else if (GET_CODE (addr) == MULT)
1606 ireg = XEXP (addr, 0);
1607 scale = XEXP (addr, 1);
1613 output_addr_const (file, offset);
1615 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1617 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1620 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1621 that is a valid memory address for an instruction.
1622 The MODE argument is the machine mode for the MEM expression
1623 that wants to use this address.
1625 On 80960, legitimate addresses are:
1627 disp (12 or 32 bit) ld foo,r0
1628 base + index ld (g0)[g1*1],r0
1629 base + displ ld 0xf00(g0),r0
1630 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1631 index*scale + base ld (g0)[g1*4],r0
1632 index*scale + displ ld 0xf00[g1*4],r0
1633 index*scale ld [g1*4],r0
1634 index + base + displ ld 0xf00(g0)[g1*1],r0
1636 In each case, scale can be 1, 2, 4, 8, or 16. */
1638 /* This is exactly the same as i960_print_operand_addr, except that
1639 it recognizes addresses instead of printing them.
1641 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1642 convert common non-canonical forms to canonical form so that they will
1645 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1646 where a register is valid. */
1648 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1649 ((GET_CODE (X) == REG \
1650 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1651 || (GET_CODE (X) == SUBREG \
1652 && GET_CODE (SUBREG_REG (X)) == REG \
1653 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1654 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1656 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1657 ((GET_CODE (X) == REG \
1658 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1659 || (GET_CODE (X) == SUBREG \
1660 && GET_CODE (SUBREG_REG (X)) == REG \
1661 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1662 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1665 legitimate_address_p (mode, addr, strict)
1666 enum machine_mode mode;
1670 if (RTX_OK_FOR_BASE_P (addr, strict))
1672 else if (CONSTANT_P (addr))
1674 else if (GET_CODE (addr) == PLUS)
1678 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1681 op0 = XEXP (addr, 0);
1682 op1 = XEXP (addr, 1);
1684 if (RTX_OK_FOR_BASE_P (op0, strict))
1686 if (RTX_OK_FOR_INDEX_P (op1, strict))
1688 else if (CONSTANT_P (op1))
1693 else if (GET_CODE (op0) == PLUS)
1695 if (GET_CODE (XEXP (op0, 0)) == MULT)
1697 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
1698 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
1701 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
1702 && CONSTANT_P (op1))
1707 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
1709 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
1710 && CONSTANT_P (op1))
1718 else if (GET_CODE (op0) == MULT)
1720 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
1721 && SCALE_TERM_P (XEXP (op0, 1))))
1724 if (RTX_OK_FOR_BASE_P (op1, strict))
1726 else if (CONSTANT_P (op1))
1734 else if (GET_CODE (addr) == MULT)
1736 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1739 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
1740 && SCALE_TERM_P (XEXP (addr, 1)));
1746 /* Try machine-dependent ways of modifying an illegitimate address
1747 to be legitimate. If we find one, return the new, valid address.
1748 This macro is used in only one place: `memory_address' in explow.c.
1750 This converts some non-canonical addresses to canonical form so they
1751 can be recognized. */
1754 legitimize_address (x, oldx, mode)
1757 enum machine_mode mode;
1759 if (GET_CODE (x) == SYMBOL_REF)
1762 x = copy_to_reg (x);
1765 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1768 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
1769 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
1770 created by virtual register instantiation, register elimination, and
1771 similar optimizations. */
1772 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1773 && GET_CODE (XEXP (x, 1)) == PLUS)
1774 x = gen_rtx (PLUS, Pmode,
1775 gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
1776 XEXP (XEXP (x, 1), 1));
1778 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
1779 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
1780 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
1781 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1782 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
1783 && CONSTANT_P (XEXP (x, 1)))
1785 rtx constant, other;
1787 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1789 constant = XEXP (x, 1);
1790 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
1792 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
1794 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
1795 other = XEXP (x, 1);
1801 x = gen_rtx (PLUS, Pmode,
1802 gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0),
1803 XEXP (XEXP (XEXP (x, 0), 1), 0)),
1804 plus_constant (other, INTVAL (constant)));
1811 /* Return the most stringent alignment that we are willing to consider
1812 objects of size SIZE and known alignment ALIGN as having. */
1815 i960_alignment (size, align)
1821 if (! TARGET_STRICT_ALIGN)
1822 if (TARGET_IC_COMPAT2_0 || align >= 4)
1824 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1833 /* Modes for condition codes. */
1835 ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
1837 /* Modes for single-word (and smaller) quantities. */
1840 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1841 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1843 /* Modes for double-word (and smaller) quantities. */
1846 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1848 /* Modes for quad-word quantities. */
1849 #define T_MODES (~C_MODES)
1851 /* Modes for single-float quantities. */
1852 #define SF_MODES ((1 << (int) SFmode))
1854 /* Modes for double-float quantities. */
1855 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1857 /* Modes for quad-float quantities. */
1858 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1860 unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
1861 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1862 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1863 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1864 T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1866 TF_MODES, TF_MODES, TF_MODES, TF_MODES, C_MODES};
1869 /* Return the minimum alignment of an expression rtx X in bytes. This takes
1870 advantage of machine specific facts, such as knowing that the frame pointer
1871 is always 16 byte aligned. */
1874 i960_expr_alignment (x, size)
1883 switch (GET_CODE(x))
1888 if ((align & 0xf) == 0)
1890 else if ((align & 0x7) == 0)
1892 else if ((align & 0x3) == 0)
1894 else if ((align & 0x1) == 0)
1901 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
1902 i960_expr_alignment (XEXP (x, 1), size));
1906 /* If this is a valid program, objects are guaranteed to be
1907 correctly aligned for whatever size the reference actually is. */
1908 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
1912 if (REGNO (x) == FRAME_POINTER_REGNUM)
1918 align = i960_expr_alignment (XEXP (x, 0));
1920 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
1922 align = align << INTVAL (XEXP (x, 1));
1923 align = MIN (align, 16);
1928 align = (i960_expr_alignment (XEXP (x, 0), size) *
1929 i960_expr_alignment (XEXP (x, 1), size));
1931 align = MIN (align, 16);
1938 /* Return true if it is possible to reference both BASE and OFFSET, which
1939 have alignment at least as great as 4 byte, as if they had alignment valid
1940 for an object of size SIZE. */
1943 i960_improve_align (base, offset, size)
1950 /* We have at least a word reference to the object, so we know it has to
1951 be aligned at least to 4 bytes. */
1953 i = MIN (i960_expr_alignment (base, 4),
1954 i960_expr_alignment (offset, 4));
1958 /* We know the size of the request. If strict align is not enabled, we
1959 can guess that the alignment is OK for the requested size. */
1961 if (! TARGET_STRICT_ALIGN)
1962 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
1968 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1969 (SImode) alignment as if they had 16 byte (TImode) alignment. */
1972 i960_si_ti (base, offset)
1976 return i960_improve_align (base, offset, 16);
1979 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
1980 (SImode) alignment as if they had 8 byte (DImode) alignment. */
1983 i960_si_di (base, offset)
1987 return i960_improve_align (base, offset, 8);
1990 /* Return raw values of size and alignment (in words) for the data
1991 type being accessed. These values will be rounded by the caller. */
1994 i960_arg_size_and_align (mode, type, size_out, align_out)
1995 enum machine_mode mode;
2002 /* Use formal alignment requirements of type being passed, except make
2003 it at least a word. If we don't have a type, this is a library call,
2004 and the parm has to be of scalar type. In this case, consider its
2005 formal alignment requirement to be its size in words. */
2007 if (mode == BLKmode)
2008 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2009 else if (mode == VOIDmode)
2011 /* End of parm list. */
2012 assert (type != 0 && TYPE_MODE (type) == VOIDmode);
2016 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2020 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2021 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2029 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2030 Any arg that is bigger than 4 words is placed on the stack and all
2031 subsequent arguments are placed on the stack.
2033 Additionally, parameters with an alignment requirement stronger than
2034 a word must be be aligned appropriately. */
2036 /* Update CUM to advance past an argument described by MODE and TYPE. */
2039 i960_function_arg_advance (cum, mode, type, named)
2040 CUMULATIVE_ARGS *cum;
2041 enum machine_mode mode;
2047 i960_arg_size_and_align (mode, type, &size, &align);
2049 if (named == 0 || size > 4 || cum->ca_nstackparms != 0
2050 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2051 || MUST_PASS_IN_STACK (mode, type))
2052 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2054 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2057 /* Return the register that the argument described by MODE and TYPE is
2058 passed in, or else return 0 if it is passed on the stack. */
2061 i960_function_arg (cum, mode, type, named)
2062 CUMULATIVE_ARGS *cum;
2063 enum machine_mode mode;
2070 i960_arg_size_and_align (mode, type, &size, &align);
2072 if (named == 0 || size > 4 || cum->ca_nstackparms != 0
2073 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2074 || MUST_PASS_IN_STACK (mode, type))
2076 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2081 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2082 ret = gen_rtx (REG, mode, cum->ca_nregparms);
2088 /* Floating-point support. */
2091 i960_output_double (file, value)
2095 if (REAL_VALUE_ISINF (value))
2097 fprintf (file, "\t.word 0\n");
2098 fprintf (file, "\t.word 0x7ff00000 # Infinity\n");
2101 fprintf (file, "\t.double 0d%.17e\n", (value));
2105 i960_output_float (file, value)
2109 if (REAL_VALUE_ISINF (value))
2110 fprintf (file, "\t.word 0x7f800000 # Infinity\n");
2112 fprintf (file, "\t.float 0f%.12e\n", (value));
2115 /* Return the number of bits that an object of size N bytes is aligned to. */
2118 i960_object_bytes_bitalign (n)
2122 else if (n > 4) n = 64;
2123 else if (n > 2) n = 32;
2124 else if (n > 1) n = 16;
2130 /* Compute the size of an aggregate type TSIZE. */
2133 i960_round_size (tsize)
2136 int size, byte_size, align;
2138 if (TREE_CODE (tsize) != INTEGER_CST)
2141 size = TREE_INT_CST_LOW (tsize);
2142 byte_size = (size + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
2143 align = i960_object_bytes_bitalign (byte_size);
2145 /* Handle #pragma align. */
2146 if (align > i960_maxbitalignment)
2147 align = i960_maxbitalignment;
2150 size = ((size / align) + 1) * align;
2152 return size_int (size);
2155 /* Compute the alignment for an aggregate type TSIZE. */
2158 i960_round_align (align, tsize)
2164 if (TREE_CODE (tsize) != INTEGER_CST)
2167 byte_size = (TREE_INT_CST_LOW (tsize) + BITS_PER_UNIT - 1) / BITS_PER_UNIT;
2168 align = i960_object_bytes_bitalign (byte_size);
2172 /* Do any needed setup for a varargs function. For the i960, we must
2173 create a register parameter block if one doesn't exist, and then copy
2174 all register parameters to memory. */
2177 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2178 CUMULATIVE_ARGS *cum;
2179 enum machine_mode mode;
2184 if (cum->ca_nregparms < NPARM_REGS)
2186 int first_reg_offset = cum->ca_nregparms;
2188 if (first_reg_offset > NPARM_REGS)
2189 first_reg_offset = NPARM_REGS;
2191 if (! (no_rtl) && first_reg_offset != NPARM_REGS)
2193 rtx label = gen_label_rtx ();
2194 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2195 emit_jump_insn (gen_bne (label));
2196 emit_insn (gen_rtx (SET, VOIDmode, arg_pointer_rtx,
2197 stack_pointer_rtx));
2198 emit_insn (gen_rtx (SET, VOIDmode, stack_pointer_rtx,
2199 memory_address (SImode,
2200 plus_constant (stack_pointer_rtx,
2205 gen_rtx (MEM, BLKmode, virtual_incoming_args_rtx),
2206 NPARM_REGS - first_reg_offset,
2207 (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD);
2209 *pretend_size = (NPARM_REGS - first_reg_offset) * UNITS_PER_WORD;
2213 /* Calculate the final size of the reg parm stack space for the current
2214 function, based on how many bytes would be allocated on the stack. */
2217 i960_final_reg_parm_stack_space (const_size, var_size)
2221 if (var_size || const_size > 48)
2227 /* Calculate the size of the reg parm stack space. This is a bit complicated
2231 i960_reg_parm_stack_space (fndecl)
2234 /* In this case, we are called from emit_library_call, and we don't need
2235 to pretend we have more space for parameters than what's apparent. */
2239 /* In this case, we are called from locate_and_pad_parms when we're
2240 not IN_REGS, so we have an arg block. */
2241 if (fndecl != current_function_decl)
2244 /* Otherwise, we have an arg block if the current function has more than
2245 48 bytes of parameters. */
2246 if (current_function_args_size != 0)
2252 /* Return the register class of a scratch register needed to copy IN into
2253 or out of a register in CLASS in MODE. If it can be done directly,
2254 NO_REGS is returned. */
2257 secondary_reload_class (class, mode, in)
2258 enum reg_class class;
2259 enum machine_mode mode;
2264 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2265 regno = true_regnum (in);
2267 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2268 LOCAL_OR_GLOBAL_REGS into anything. */
2269 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2270 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2273 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2274 if (class == FP_REGS
2275 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2276 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2279 return LOCAL_OR_GLOBAL_REGS;
2282 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2283 function unit it executed on. */
2285 /* ??? This would make more sense as an attribute. */
2288 i960_scan_opcode (p)
2300 /* Ret is not actually of type REG, but it won't matter, because no
2301 insn will ever follow it. */
2304 i960_last_insn_type = I_TYPE_REG;
2308 if (p[1] == 'x' || p[3] == 'x')
2309 i960_last_insn_type = I_TYPE_MEM;
2310 i960_last_insn_type = I_TYPE_CTRL;
2315 i960_last_insn_type = I_TYPE_CTRL;
2322 i960_last_insn_type = I_TYPE_MEM;
2324 i960_last_insn_type = I_TYPE_CTRL;
2326 else if (p[1] == 'm')
2329 i960_last_insn_type = I_TYPE_REG;
2330 else if (p[4] == 'b' || p[4] == 'j')
2331 i960_last_insn_type = I_TYPE_CTRL;
2333 i960_last_insn_type = I_TYPE_REG;
2336 i960_last_insn_type = I_TYPE_REG;
2340 i960_last_insn_type = I_TYPE_MEM;
2345 i960_last_insn_type = I_TYPE_MEM;
2347 i960_last_insn_type = I_TYPE_REG;