1 /* Definitions of target machine for GNU compiler, for Intel 860.
2 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
4 Written by Richard Stallman (rms@ai.mit.edu).
6 Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater to
7 the whims of the System V Release 4 assembler.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions that relate to assembler syntax. */
30 /* Names to predefine in the preprocessor for this target machine. */
32 #define CPP_PREDEFINES "-Di860 -Dunix"
34 /* Print subsidiary information on the compiler version in use. */
35 #define TARGET_VERSION fprintf (stderr, " (i860)");
37 /* Run-time compilation parameters selecting different hardware subsets
40 On the i860, we have one: TARGET_XP. This option allows gcc to generate
41 additional instructions available only on the newer i860 XP (but not on
45 extern int target_flags;
47 /* Nonzero if we should generate code to use the fpu. */
48 #define TARGET_XP (target_flags & 1)
50 /* Macro to define tables used to set the flags.
51 This is a list in braces of pairs in braces,
52 each pair being { "NAME", VALUE }
53 where VALUE is the bits to set or minus the bits to clear.
54 An empty string NAME is used to identify the default VALUE. */
56 #define TARGET_SWITCHES \
60 { "", TARGET_DEFAULT}}
62 #define TARGET_DEFAULT 0
64 /* target machine storage layout */
66 /* Define this if most significant bit is lowest numbered
67 in instructions that operate on numbered bit-fields.
68 This is a moot question on the i860 due to the lack of bit-field insns. */
69 #define BITS_BIG_ENDIAN 0
71 /* Define this if most significant byte of a word is the lowest numbered. */
72 /* That is not true on i860 in the mode we will use. */
73 #define BYTES_BIG_ENDIAN 0
75 /* Define this if most significant word of a multiword number is the lowest
77 /* For the i860 this goes with BYTES_BIG_ENDIAN. */
78 #define WORDS_BIG_ENDIAN 0
80 /* number of bits in an addressable storage unit */
81 #define BITS_PER_UNIT 8
83 /* Width in bits of a "word", which is the contents of a machine register.
84 Note that this is not necessarily the width of data type `int';
85 if using 16-bit ints on a 68000, this would still be 32.
86 But on a machine with 16-bit registers, this would be 16. */
87 #define BITS_PER_WORD 32
89 /* Width of a word, in units (bytes). */
90 #define UNITS_PER_WORD 4
92 /* Width in bits of a pointer.
93 See also the macro `Pmode' defined below. */
94 #define POINTER_SIZE 32
96 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
97 #define PARM_BOUNDARY 32
99 /* Boundary (in *bits*) on which stack pointer should be aligned. */
100 #define STACK_BOUNDARY 128
102 /* Allocation boundary (in *bits*) for the code of a function. */
103 #define FUNCTION_BOUNDARY 64
105 /* Alignment of field after `int : 0' in a structure. */
106 #define EMPTY_FIELD_BOUNDARY 32
108 /* Every structure's size must be a multiple of this. */
109 #define STRUCTURE_SIZE_BOUNDARY 8
111 /* Minimum size in bits of the largest boundary to which any
112 and all fundamental data types supported by the hardware
113 might need to be aligned. No data type wants to be aligned
114 rounder than this. The i860 supports 128-bit (long double)
115 floating point quantities, and the System V Release 4 i860
116 ABI requires these to be aligned to 16-byte (128-bit)
118 #define BIGGEST_ALIGNMENT 128
120 /* Set this nonzero if move instructions will actually fail to work
121 when given unaligned data. */
122 #define STRICT_ALIGNMENT 1
124 /* If bit field type is int, dont let it cross an int,
125 and give entire struct the alignment of an int. */
126 #define PCC_BITFIELD_TYPE_MATTERS 1
128 /* Standard register usage. */
130 /* Number of actual hardware registers.
131 The hardware registers are assigned numbers for the compiler
132 from 0 to just below FIRST_PSEUDO_REGISTER.
133 All registers that the compiler knows about must be given numbers,
134 even those that are not normally considered general registers.
136 i860 has 32 fullword registers and 32 floating point registers. */
138 #define FIRST_PSEUDO_REGISTER 64
140 /* 1 for registers that have pervasive standard uses
141 and are not available for the register allocator.
142 On the i860, this includes the always-0 registers
143 and fp, sp, arg pointer, and the return address.
144 Also r31, used for special purposes for constant addresses. */
145 #define FIXED_REGISTERS \
146 {1, 1, 1, 1, 0, 0, 0, 0, \
147 0, 0, 0, 0, 0, 0, 0, 0, \
148 0, 0, 0, 0, 0, 0, 0, 0, \
149 0, 0, 0, 0, 0, 0, 0, 1, \
150 1, 1, 0, 0, 0, 0, 0, 0, \
151 0, 0, 0, 0, 0, 0, 0, 0, \
152 0, 0, 0, 0, 0, 0, 0, 0, \
153 0, 0, 0, 0, 0, 0, 0, 0}
155 /* 1 for registers not available across function calls.
156 These must include the FIXED_REGISTERS and also any
157 registers that can be used without being saved.
158 On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */
159 #define CALL_USED_REGISTERS \
160 {1, 1, 1, 1, 0, 0, 0, 0, \
161 0, 0, 0, 0, 0, 0, 0, 0, \
162 1, 1, 1, 1, 1, 1, 1, 1, \
163 1, 1, 1, 1, 1, 1, 1, 1, \
164 1, 1, 0, 0, 0, 0, 0, 0, \
165 1, 1, 1, 1, 1, 1, 1, 1, \
166 1, 1, 1, 1, 1, 1, 1, 1, \
167 1, 1, 1, 1, 1, 1, 1, 1}
169 /* Try to get a non-preserved register before trying to get one we will
170 have to preserve. Try to get an FP register only *after* trying to
171 get a general register, because it is relatively expensive to move
172 into or out of an FP register. */
174 #define REG_ALLOC_ORDER \
175 {31, 30, 29, 28, 27, 26, 25, 24, \
176 23, 22, 21, 20, 19, 18, 17, 16, \
177 15, 14, 13, 12, 11, 10, 9, 8, \
178 7, 6, 5, 4, 3, 2, 1, 0, \
179 63, 62, 61, 60, 59, 58, 57, 56, \
180 55, 54, 53, 52, 51, 50, 49, 48, \
181 47, 46, 45, 44, 43, 42, 41, 40, \
182 39, 38, 37, 36, 35, 34, 33, 32}
184 /* Return number of consecutive hard regs needed starting at reg REGNO
185 to hold something of mode MODE.
186 This is ordinarily the length in words of a value of mode MODE
187 but can be less for certain modes in special long registers.
189 On the i860, all registers hold 32 bits worth. */
190 #define HARD_REGNO_NREGS(REGNO, MODE) \
191 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
193 #define REGNO_MODE_ALIGNED(REGNO, MODE) \
194 (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
196 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
198 On the i860, we allow anything to go into any registers, but we require
199 any sort of value going into the FP registers to be properly aligned
200 (based on its size) within the FP register set.
202 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
204 || ((MODE) == VOIDmode) \
205 || REGNO_MODE_ALIGNED (REGNO, MODE))
207 /* Value is 1 if it is a good idea to tie two pseudo registers
208 when one has mode MODE1 and one has mode MODE2.
209 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
210 for any hard reg, then this must be 0 for correct output. */
211 /* I think that is not always true; alignment restrictions for doubles
212 should not prevent tying them with singles. So try allowing that.
213 On the other hand, don't let fixed and floating be tied;
214 this restriction is not necessary, but may make better code. */
215 #define MODES_TIEABLE_P(MODE1, MODE2) \
216 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
217 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
218 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
219 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
221 /* Specify the registers used for certain standard purposes.
222 The values of these macros are register numbers. */
224 /* i860 pc isn't overloaded on a register that the compiler knows about. */
225 /* #define PC_REGNUM */
227 /* Register to use for pushing function arguments. */
228 #define STACK_POINTER_REGNUM 2
230 /* Base register for access to local variables of the function. */
231 #define FRAME_POINTER_REGNUM 3
233 /* Value should be nonzero if functions must have frame pointers.
234 Zero means the frame pointer need not be set up (and parms
235 may be accessed via the stack pointer) in functions that seem suitable.
236 This is computed in `reload', in reload1.c. */
237 #define FRAME_POINTER_REQUIRED 1
239 /* Base register for access to arguments of the function. */
240 #define ARG_POINTER_REGNUM 28
242 /* Register in which static-chain is passed to a function. */
243 #define STATIC_CHAIN_REGNUM 29
245 /* Register in which address to store a structure value
246 is passed to a function. */
247 #define STRUCT_VALUE_REGNUM 16
249 /* Register to use when a source of a floating-point zero is needed. */
252 /* Define the classes of registers for register constraints in the
253 machine description. Also define ranges of constants.
255 One of the classes must always be named ALL_REGS and include all hard regs.
256 If there is more than one class, another class must be named NO_REGS
257 and contain no registers.
259 The name GENERAL_REGS must be the name of a class (or an alias for
260 another name such as ALL_REGS). This is the class of registers
261 that is allowed by "g" or "r" in a register constraint.
262 Also, registers outside this class are allocated only when
263 instructions express preferences for them.
265 The classes must be numbered in nondecreasing order; that is,
266 a larger-numbered class must never be contained completely
267 in a smaller-numbered class.
269 For any two classes, it is very desirable that there be another
270 class that represents their union. */
272 /* The i860 has two kinds of registers, hence four classes. */
274 enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
276 #define N_REG_CLASSES (int) LIM_REG_CLASSES
278 /* Give names of register classes as strings for dump file. */
280 #define REG_CLASS_NAMES \
281 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
283 /* Define which registers fit in which classes.
284 This is an initializer for a vector of HARD_REG_SET
285 of length N_REG_CLASSES. */
287 #define REG_CLASS_CONTENTS \
288 {{0, 0}, {0xffffffff, 0}, \
289 {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
291 /* The same information, inverted:
292 Return the class number of the smallest class containing
293 reg number REGNO. This could be a conditional expression
294 or could index an array. */
296 #define REGNO_REG_CLASS(REGNO) \
297 ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
299 /* The class value for index registers, and the one for base regs. */
300 #define INDEX_REG_CLASS GENERAL_REGS
301 #define BASE_REG_CLASS GENERAL_REGS
303 /* Get reg_class from a letter such as appears in the machine description. */
305 #define REG_CLASS_FROM_LETTER(C) \
306 ((C) == 'f' ? FP_REGS : NO_REGS)
308 /* The letters I, J, K, L and M in a register constraint string
309 can be used to stand for particular ranges of immediate operands.
310 This macro defines what the ranges are.
311 C is the letter, and VALUE is a constant value.
312 Return 1 if VALUE is in the range specified by C.
314 For the i860, `I' is used for the range of constants
315 an add/subtract insn can actually contain.
316 But not including -0x8000, since we need
317 to negate the constant sometimes.
318 `J' is used for the range which is just zero (since that is R0).
319 `K' is used for the range allowed in bte.
320 `L' is used for the range allowed in logical insns. */
322 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
324 #define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
326 #define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
328 #define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
330 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
331 ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \
332 : (C) == 'J' ? (VALUE) == 0 \
333 : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \
334 : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \
337 /* Return non-zero if the given VALUE is acceptable for the
338 constraint letter C. For the i860, constraint letter 'G'
339 permits only a floating-point zero value. */
340 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
341 ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \
342 && CONST_DOUBLE_HIGH ((VALUE)) == 0)
344 /* Given an rtx X being reloaded into a reg required to be
345 in class CLASS, return the class of reg to actually use.
346 In general this is just CLASS; but on some machines
347 in some cases it is preferable to use a more restrictive class.
349 If we are trying to put an integer constant into some register, prefer an
350 integer register to an FP register. If we are trying to put a
351 non-zero floating-point constant into some register, use an integer
352 register if the constant is SFmode and GENERAL_REGS is one of our options.
353 Otherwise, put the constant intoo memory. */
355 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
356 ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \
357 : (GET_CODE (X) == CONST_DOUBLE \
358 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
359 && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \
360 ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \
361 : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \
365 /* Return the register class of a scratch register needed to copy IN into
366 a register in CLASS in MODE. If it can be done directly, NO_REGS is
369 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
370 ((CLASS) == FP_REGS && GET_CODE (IN) == CONST_INT ? GENERAL_REGS : NO_REGS)
372 /* Return the maximum number of consecutive registers
373 needed to represent mode MODE in a register of class CLASS. */
374 /* On the i860, this is the size of MODE in words. */
375 #define CLASS_MAX_NREGS(CLASS, MODE) \
376 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
378 /* Stack layout; function entry, exit and calling. */
380 /* Define this if pushing a word on the stack
381 makes the stack pointer a smaller address. */
382 #define STACK_GROWS_DOWNWARD
384 /* Define this if the nominal address of the stack frame
385 is at the high-address end of the local variables;
386 that is, each additional local variable allocated
387 goes at a more negative offset in the frame. */
388 #define FRAME_GROWS_DOWNWARD
390 /* Offset within stack frame to start allocating local variables at.
391 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
392 first local allocated. Otherwise, it is the offset to the BEGINNING
393 of the first local allocated. */
394 #define STARTING_FRAME_OFFSET 0
396 /* If we generate an insn to push BYTES bytes,
397 this says how many the stack pointer really advances by.
398 On the i860, don't define this because there are no push insns. */
399 /* #define PUSH_ROUNDING(BYTES) */
401 /* Offset of first parameter from the argument pointer register value. */
402 #define FIRST_PARM_OFFSET(FNDECL) 0
404 /* Value is the number of bytes of arguments automatically
405 popped when returning from a subroutine call.
406 FUNTYPE is the data type of the function (as a tree),
407 or for a library call it is an identifier node for the subroutine name.
408 SIZE is the number of bytes of arguments passed on the stack. */
410 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
412 /* Define how to find the value returned by a function.
413 VALTYPE is the data type of the value (as a tree).
414 If the precise function being called is known, FUNC is its FUNCTION_DECL;
415 otherwise, FUNC is 0. */
417 /* On the i860, the value register depends on the mode. */
419 #define FUNCTION_VALUE(VALTYPE, FUNC) \
420 gen_rtx (REG, TYPE_MODE (VALTYPE), \
421 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
424 /* Define how to find the value returned by a library function
425 assuming the value has mode MODE. */
427 #define LIBCALL_VALUE(MODE) \
428 gen_rtx (REG, MODE, \
429 (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
432 /* 1 if N is a possible register number for a function value
433 as seen by the caller. */
435 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
437 /* 1 if N is a possible register number for function argument passing.
438 On the i860, these are r16-r27 and f8-f15. */
440 #define FUNCTION_ARG_REGNO_P(N) \
441 (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
443 /* Define a data type for recording info about an argument list
444 during the scan of that argument list. This data type should
445 hold all necessary information about the function itself
446 and about the args processed so far, enough to enable macros
447 such as FUNCTION_ARG to determine where the next arg should go.
449 On the i860, we must count separately the number of general registers used
450 and the number of float registers used. */
452 struct cumulative_args { int ints, floats; };
453 #define CUMULATIVE_ARGS struct cumulative_args
455 /* Initialize a variable CUM of type CUMULATIVE_ARGS
456 for a call to a function whose data type is FNTYPE.
457 For a library call, FNTYPE is 0.
459 On the i860, the general-reg offset normally starts at 0,
460 but starts at 4 bytes
461 when the function gets a structure-value-address as an
462 invisible first argument. */
464 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
465 ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p ((FNTYPE)) \
469 /* Machine-specific subroutines of the following macros. */
470 #define CEILING(X,Y) (((X) + (Y) - 1) / (Y))
471 #define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y))
473 /* Update the data in CUM to advance over an argument
474 of mode MODE and data type TYPE.
475 (TYPE is null for libcalls where that information may not be available.)
476 Floats, and doubleword ints, are returned in f regs;
477 other ints, in r regs.
478 Aggregates, even short ones, are passed in memory. */
480 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
481 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
482 || TREE_CODE ((TYPE)) == UNION_TYPE) \
484 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
485 ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \
486 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
487 : GET_MODE_CLASS ((MODE)) == MODE_INT \
488 ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
489 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
492 /* Determine where to put an argument to a function.
493 Value is zero to push the argument on the stack,
494 or a hard register in which to store the argument.
496 MODE is the argument's machine mode.
497 TYPE is the data type of the argument (as a tree).
498 This is null for libcalls where that information may
500 CUM is a variable of type CUMULATIVE_ARGS which gives info about
501 the preceding args and about the function being called.
502 NAMED is nonzero if this argument is a named parameter
503 (otherwise it is an extra parameter matching an ellipsis). */
505 /* On the i860, the first 12 words of integer arguments go in r16-r27,
506 and the first 8 words of floating arguments go in f8-f15.
507 DImode values are treated as floats. */
509 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
510 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
511 || TREE_CODE ((TYPE)) == UNION_TYPE) \
513 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
514 ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
515 ? gen_rtx (REG, (MODE), \
516 40+(ROUNDUP ((CUM).floats, \
517 GET_MODE_SIZE ((MODE))) \
520 : GET_MODE_CLASS ((MODE)) == MODE_INT \
521 ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
522 ? gen_rtx (REG, (MODE), \
523 16+(ROUNDUP ((CUM).ints, \
524 GET_MODE_SIZE ((MODE))) \
529 /* For an arg passed partly in registers and partly in memory,
530 this is the number of registers used.
531 For args passed entirely in registers or entirely in memory, zero. */
533 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
535 /* If defined, a C expression that gives the alignment boundary, in
536 bits, of an argument with the specified mode and type. If it is
537 not defined, `PARM_BOUNDARY' is used for all arguments. */
539 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
541 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
543 : TYPE_ALIGN(TYPE)) \
544 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
546 : GET_MODE_ALIGNMENT(MODE)))
548 /* This macro generates the assembly code for function entry.
550 FILE is a stdio stream to output the code to.
551 SIZE is an int: how many units of temporary storage to allocate.
554 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE))
556 /* Output a no-op just before the beginning of the function,
557 to ensure that there does not appear to be a delayed branch there.
558 Such a thing would confuse interrupt recovery. */
559 #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
560 fprintf (FILE, "\tnop\n")
562 /* Output assembler code to FILE to increment profiler label # LABELNO
563 for profiling a function entry. */
565 #define FUNCTION_PROFILER(FILE, LABELNO) \
568 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
569 the stack pointer does not matter. The value is tested only in
570 functions that have frame pointers.
571 No definition is equivalent to always zero. */
573 #define EXIT_IGNORE_STACK 1
575 /* This macro generates the assembly code for function exit.
577 FILE is a stdio stream to output the code to.
578 SIZE is an int: how many units of temporary storage to allocate.
580 The function epilogue should not depend on the current stack pointer!
581 It should use the frame pointer only. This is mandatory because
582 of alloca; we also take advantage of it to omit stack adjustments
586 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE))
588 /* Store in the variable DEPTH the initial difference between the
589 frame pointer reg contents and the stack pointer reg contents,
590 as of the start of the function body. This depends on the layout
591 of the fixed parts of the stack frame and on how registers are saved.
593 On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
594 macro doesn't matter. But it must be defined. */
596 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
597 do { (DEPTH) = 0; } while (0)
599 /* Output assembler code for a block containing the constant parts
600 of a trampoline, leaving space for the variable parts. */
602 /* On the i860, the trampoline contains five instructions:
603 orh #TOP_OF_FUNCTION,r0,r31
604 or #BOTTOM_OF_FUNCTION,r31,r31
605 orh #TOP_OF_STATIC,r0,r29
607 or #BOTTOM_OF_STATIC,r29,r29 */
608 #define TRAMPOLINE_TEMPLATE(FILE) \
610 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1f0000)); \
611 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7ff0000)); \
612 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1d0000)); \
613 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4000f800)); \
614 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7bd0000)); \
617 /* Length in units of the trampoline for entering a nested function. */
619 #define TRAMPOLINE_SIZE 20
621 /* Emit RTL insns to initialize the variable parts of a trampoline.
622 FNADDR is an RTX for the address of the function's pure code.
623 CXT is an RTX for the static chain value for the function.
625 Store hi function at +0, low function at +4,
626 hi static at +8, low static at +16 */
628 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
630 rtx low_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
631 size_int (16), 0, 0); \
632 rtx low_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
633 size_int (16), 0, 0); \
634 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)), \
635 gen_rtx (SUBREG, HImode, CXT)); \
636 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)), \
637 gen_rtx (SUBREG, HImode, FNADDR)); \
638 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)), \
639 gen_rtx (SUBREG, HImode, low_cxt)); \
640 emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)), \
641 gen_rtx (SUBREG, HImode, low_fn)); \
644 /* Addressing modes, and classification of registers for them. */
646 /* #define HAVE_POST_INCREMENT */
647 /* #define HAVE_POST_DECREMENT */
649 /* #define HAVE_PRE_DECREMENT */
650 /* #define HAVE_PRE_INCREMENT */
652 /* Macros to check register numbers against specific register classes. */
654 /* These assume that REGNO is a hard or pseudo reg number.
655 They give nonzero only if REGNO is a hard reg of the suitable class
656 or a pseudo reg currently allocated to a suitable hard reg.
657 Since they use reg_renumber, they are safe only once reg_renumber
658 has been allocated, which happens in local-alloc.c. */
660 #define REGNO_OK_FOR_INDEX_P(REGNO) \
661 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
662 #define REGNO_OK_FOR_BASE_P(REGNO) \
663 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
664 #define REGNO_OK_FOR_FP_P(REGNO) \
665 (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
667 /* Now macros that check whether X is a register and also,
668 strictly, whether it is in a specified class.
670 These macros are specific to the i860, and may be used only
671 in code for printing assembler insns and in conditions for
672 define_optimization. */
674 /* 1 if X is an fp register. */
676 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
678 /* Maximum number of registers that can appear in a valid memory address. */
680 #define MAX_REGS_PER_ADDRESS 2
682 /* Recognize any constant value that is a valid address. */
684 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
686 /* Nonzero if the constant value X is a legitimate general operand.
687 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
689 On the Sparc, this is anything but a CONST_DOUBLE.
690 Let's try permitting CONST_DOUBLEs and see what happens. */
692 #define LEGITIMATE_CONSTANT_P(X) 1
694 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
695 and check its validity for a certain class.
696 We have two alternate definitions for each of them.
697 The usual definition accepts all pseudo regs; the other rejects
698 them unless they have been allocated suitable hard regs.
699 The symbol REG_OK_STRICT causes the latter definition to be used.
701 Most source files want to accept pseudo regs in the hope that
702 they will get allocated to the class that the insn wants them to be in.
703 Source files for reload pass need to be strict.
704 After reload, it makes no difference, since pseudo regs have
705 been eliminated by then. */
707 #ifndef REG_OK_STRICT
709 /* Nonzero if X is a hard reg that can be used as an index
710 or if it is a pseudo reg. */
711 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
712 /* Nonzero if X is a hard reg that can be used as a base reg
713 or if it is a pseudo reg. */
714 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
718 /* Nonzero if X is a hard reg that can be used as an index. */
719 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
720 /* Nonzero if X is a hard reg that can be used as a base reg. */
721 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
725 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
726 that is a valid memory address for an instruction.
727 The MODE argument is the machine mode for the MEM expression
728 that wants to use this address.
730 On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
731 But we can treat a SYMBOL_REF as legitimate if it is part of this
732 function's constant-pool, because such addresses can actually
733 be output as REG+SMALLINT.
735 The displacement in an address must be a multiple of the alignment.
737 Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
738 a legitimate address, regardless. Because the only insns which can use
739 memory are load or store insns, the added hair in the machine description
740 is not that bad. It should also speed up the compiler by halving the number
741 of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */
743 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
744 { if (GET_CODE (X) == REG) \
745 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
746 else if (GET_CODE (X) == PLUS) \
748 if (GET_CODE (XEXP (X, 0)) == REG \
749 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
751 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
752 && INTVAL (XEXP (X, 1)) >= -0x8000 \
753 && INTVAL (XEXP (X, 1)) < 0x8000 \
754 && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
757 else if (GET_CODE (XEXP (X, 1)) == REG \
758 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
760 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
761 && INTVAL (XEXP (X, 0)) >= -0x8000 \
762 && INTVAL (XEXP (X, 0)) < 0x8000 \
763 && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
767 else if (CONSTANT_ADDRESS_P (X)) \
771 /* Try machine-dependent ways of modifying an illegitimate address
772 to be legitimate. If we find one, return the new, valid address.
773 This macro is used in only one place: `memory_address' in explow.c.
775 OLDX is the address as it was before break_out_memory_refs was called.
776 In some cases it is useful to look at this to decide what needs to be done.
778 MODE and WIN are passed so that this macro can use
779 GO_IF_LEGITIMATE_ADDRESS.
781 It is always safe for this macro to do nothing. It exists to recognize
782 opportunities to optimize the output. */
784 /* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
785 Also change a symbolic constant to a REG,
786 though that may not be necessary. */
788 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
789 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
790 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
791 force_operand (XEXP (X, 0), 0)); \
792 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
793 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
794 force_operand (XEXP (X, 1), 0)); \
795 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
796 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
797 force_operand (XEXP (X, 0), 0)); \
798 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
799 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
800 force_operand (XEXP (X, 1), 0)); \
801 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
802 && GET_CODE (XEXP (X, 0)) != CONST_INT) \
803 (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
804 copy_to_mode_reg (SImode, XEXP (X, 0))); \
805 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
806 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
807 (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
808 copy_to_mode_reg (SImode, XEXP (X, 1))); \
809 if (GET_CODE (x) == SYMBOL_REF) \
810 (X) = copy_to_reg (X); \
811 if (GET_CODE (x) == CONST) \
812 (X) = copy_to_reg (X); \
813 if (memory_address_p (MODE, X)) \
816 /* Go to LABEL if ADDR (a legitimate address expression)
817 has an effect that depends on the machine mode it is used for.
818 On the i860 this is never true.
819 There are some addresses that are invalid in wide modes
820 but valid for narrower modes, but they shouldn't affect
821 the places that use this macro. */
823 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
825 /* Specify the machine mode that this machine uses
826 for the index in the tablejump instruction. */
827 #define CASE_VECTOR_MODE SImode
829 /* Define this if the tablejump instruction expects the table
830 to contain offsets from the address of the table.
831 Do not define this if the table should contain absolute addresses. */
832 /* #define CASE_VECTOR_PC_RELATIVE */
834 /* Specify the tree operation to be used to convert reals to integers. */
835 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
837 /* This is the kind of divide that is easiest to do in the general case. */
838 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
840 /* Must pass floats to libgcc functions as doubles. */
841 #define LIBGCC_NEEDS_DOUBLE 1
843 #define DIVSI3_LIBCALL "*.div"
844 #define UDIVSI3_LIBCALL "*.udiv"
845 #define REMSI3_LIBCALL "*.rem"
846 #define UREMSI3_LIBCALL "*.urem"
848 /* Define this as 1 if `char' should by default be signed; else as 0. */
849 #define DEFAULT_SIGNED_CHAR 1
851 /* Max number of bytes we can move from memory to memory
852 in one reasonably fast instruction. */
855 /* Nonzero if access to memory by bytes is slow and undesirable. */
856 #define SLOW_BYTE_ACCESS 0
858 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
859 is done just by pretending it is already truncated. */
860 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
862 /* Value is 1 if it generates better code to perform an unsigned comparison
863 on the given literal integer value in the given mode when we are only
864 looking for an equal/non-equal result. */
865 /* For the i860, if the immediate value has its high-order 27 bits zero,
866 then we want to engineer an unsigned comparison for EQ/NE because
867 such values can fit in the 5-bit immediate field of a bte or btne
868 instruction (which gets zero extended before comparing). For all
869 other immediate values on the i860, we will use signed compares
870 because that avoids the need for doing explicit xor's to zero_extend
871 the non-constant operand in cases where it was (mem:QI ...) or a
872 (mem:HI ...) which always gets automatically sign-extended by the
873 hardware upon loading. */
875 #define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \
876 (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
878 /* Specify the machine mode that pointers have.
879 After generation of rtl, the compiler makes no further distinction
880 between pointers and any other objects of this machine mode. */
883 /* A function address in a call instruction
884 is a byte address (for indexing purposes)
885 so give the MEM rtx a byte's mode. */
886 #define FUNCTION_MODE SImode
888 /* Define this if addresses of constant functions
889 shouldn't be put through pseudo regs where they can be cse'd.
890 Desirable on machines where ordinary constants are expensive
891 but a CALL with constant address is cheap. */
892 #define NO_FUNCTION_CSE
894 /* Compute the cost of computing a constant rtl expression RTX
895 whose rtx-code is CODE. The body of this macro is a portion
896 of a switch statement. If the code is computed here,
897 return it with a return statement. Otherwise, break from the switch. */
899 #define CONST_COSTS(RTX,CODE) \
901 if (INTVAL (RTX) == 0) \
903 if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
911 /* Specify the cost of a branch insn; roughly the number of extra insns that
912 should be added to avoid a branch.
914 Set this to 3 on the i860 since branches may often take three cycles. */
916 #define BRANCH_COST 3
918 /* Tell final.c how to eliminate redundant test instructions. */
920 /* Here we define machine-dependent flags and fields in cc_status
921 (see `conditions.h'). */
923 /* This holds the value sourcing h%r31. We keep this info
924 around so that mem/mem ops, such as increment and decrement,
925 etc, can be performed reasonably. */
926 #define CC_STATUS_MDEP rtx
928 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
930 #define CC_NEGATED 01000
932 /* We use this macro in those places in the i860.md file where we would
933 normally just do a CC_STATUS_INIT (for other machines). This macro
934 differs from CC_STATUS_INIT in that it doesn't mess with the special
935 bits or fields which describe what is currently in the special r31
936 scratch register, but it does clear out everything that actually
937 relates to the condition code bit of the i860. */
939 #define CC_STATUS_PARTIAL_INIT \
940 (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \
941 cc_status.value1 = 0, \
942 cc_status.value2 = 0)
944 /* Nonzero if we know the value of h%r31. */
945 #define CC_KNOW_HI_R31 0100000
947 /* Nonzero if h%r31 is actually ha%something, rather than h%something. */
948 #define CC_HI_R31_ADJ 0200000
950 /* Store in cc_status the expressions
951 that the condition codes will describe
952 after execution of an instruction whose pattern is EXP.
953 Do not alter them if the instruction would not alter the cc's. */
955 /* On the i860, only compare insns set a useful condition code. */
957 #define NOTICE_UPDATE_CC(EXP, INSN) \
958 { cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \
959 cc_status.value1 = 0; cc_status.value2 = 0; }
961 /* Control the assembler format that we output. */
963 /* Assembler pseudos to introduce constants of various size. */
965 #define ASM_BYTE_OP "\t.byte"
966 #define ASM_SHORT "\t.short"
967 #define ASM_LONG "\t.long"
968 #define ASM_DOUBLE "\t.double"
970 /* Output at beginning of assembler file. */
971 /* The .file command should always begin the output. */
973 #define ASM_FILE_START(FILE)
975 #define ASM_FILE_START(FILE) \
976 do { output_file_directive ((FILE), main_input_filename); \
977 if (optimize) ASM_FILE_START_1 (FILE); \
981 #define ASM_FILE_START_1(FILE)
983 /* Output to assembler file text saying following lines
984 may contain character constants, extra white space, comments, etc. */
986 #define ASM_APP_ON ""
988 /* Output to assembler file text saying following lines
989 no longer contain unusual constructs. */
991 #define ASM_APP_OFF ""
993 /* Output before read-only data. */
995 #define TEXT_SECTION_ASM_OP ".text"
997 /* Output before writable data. */
999 #define DATA_SECTION_ASM_OP ".data"
1001 /* How to refer to registers in assembler output.
1002 This sequence is indexed by compiler's hard-register-number (see above). */
1004 #define REGISTER_NAMES \
1005 {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \
1006 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1007 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1009 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1010 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1011 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1014 /* How to renumber registers for dbx and gdb. */
1016 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1018 /* This is how to output the definition of a user-level label named NAME,
1019 such as the label on a static function or variable NAME. */
1021 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1022 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1024 /* This is how to output a command to make the user-level label named NAME
1025 defined for reference from other files. */
1027 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1028 do { fputs (".globl ", FILE); \
1029 assemble_name (FILE, NAME); \
1030 fputs ("\n", FILE); \
1033 /* This is how to output a reference to a user-level label named NAME.
1034 `assemble_name' uses this.
1036 This definition is overridden in i860v4.h because under System V
1037 Release 4, user-level symbols are *not* prefixed with underscores in
1038 the generated assembly code. */
1040 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1041 fprintf (FILE, "_%s", NAME)
1043 /* This is how to output an internal numbered label where
1044 PREFIX is the class of label and NUM is the number within the class. */
1046 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1047 fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1049 /* This is how to output an internal numbered label which
1050 labels a jump table. */
1052 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,JUMPTABLE) \
1053 fprintf (FILE, "\t.align\t4\n.%s%d:\n", PREFIX, NUM)
1055 /* Output at the end of a jump table. */
1057 #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
1058 fprintf (FILE, ".text\n")
1060 /* This is how to store into the string LABEL
1061 the symbol_ref name of an internal numbered label where
1062 PREFIX is the class of label and NUM is the number within the class.
1063 This is suitable for output with `assemble_name'. */
1065 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1066 sprintf (LABEL, "*.%s%d", PREFIX, NUM)
1068 /* This is how to output an assembler line defining a `double' constant. */
1070 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1071 fprintf (FILE, "\t.double %.20e\n", (VALUE))
1073 /* This is how to output an assembler line defining a `float' constant. */
1075 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1076 fprintf (FILE, "\t.float %.12e\n", (VALUE))
1078 /* This is how to output an assembler line defining an `int' constant. */
1080 #define ASM_OUTPUT_INT(FILE,VALUE) \
1081 ( fprintf (FILE, "\t.long "), \
1082 output_addr_const (FILE, (VALUE)), \
1083 fprintf (FILE, "\n"))
1085 /* Likewise for `char' and `short' constants. */
1087 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1088 ( fprintf (FILE, "\t.short "), \
1089 output_addr_const (FILE, (VALUE)), \
1090 fprintf (FILE, "\n"))
1092 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1093 ( fprintf (FILE, "\t.byte "), \
1094 output_addr_const (FILE, (VALUE)), \
1095 fprintf (FILE, "\n"))
1097 /* This is how to output an assembler line for a numeric constant byte. */
1099 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1100 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1102 /* This is how to output code to push a register on the stack.
1103 It need not be very fast code. */
1105 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1106 fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \
1107 i860_reg_prefix, i860_reg_prefix, \
1108 ((REGNO) < 32 ? "" : "f"), \
1109 i860_reg_prefix, reg_names[REGNO], \
1112 /* This is how to output an insn to pop a register from the stack.
1113 It need not be very fast code. */
1115 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1116 fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \
1117 ((REGNO) < 32 ? "" : "f"), \
1119 i860_reg_prefix, reg_names[REGNO], \
1120 i860_reg_prefix, i860_reg_prefix)
1122 /* This is how to output an element of a case-vector that is absolute. */
1124 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1125 fprintf (FILE, "\t.long .L%d\n", VALUE)
1127 /* This is how to output an element of a case-vector that is relative.
1128 (The i860 does not use such vectors,
1129 but we must define this macro anyway.) */
1131 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1132 fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
1134 /* This is how to output an assembler line
1135 that says to advance the location counter
1136 to a multiple of 2**LOG bytes. */
1138 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1140 fprintf (FILE, "\t.align %d\n", 1 << (LOG))
1142 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1143 fprintf (FILE, "\t.blkb %u\n", (SIZE))
1145 /* This says how to output an assembler line
1146 to define a global common symbol. */
1148 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1149 ( fputs (".comm ", (FILE)), \
1150 assemble_name ((FILE), (NAME)), \
1151 fprintf ((FILE), ",%u\n", (ROUNDED)))
1153 /* This says how to output an assembler line
1154 to define a local common symbol. */
1156 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1157 ( fputs (".lcomm ", (FILE)), \
1158 assemble_name ((FILE), (NAME)), \
1159 fprintf ((FILE), ",%u\n", (ROUNDED)))
1161 /* Store in OUTPUT a string (made with alloca) containing
1162 an assembler-name for a local static variable named NAME.
1163 LABELNO is an integer which is different for each call. */
1165 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1166 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1167 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1169 /* Define the parentheses used to group arithmetic operations
1170 in assembler code. */
1172 #define ASM_OPEN_PAREN "("
1173 #define ASM_CLOSE_PAREN ")"
1175 /* Define results of standard character escape sequences. */
1176 #define TARGET_BELL 007
1177 #define TARGET_BS 010
1178 #define TARGET_TAB 011
1179 #define TARGET_NEWLINE 012
1180 #define TARGET_VT 013
1181 #define TARGET_FF 014
1182 #define TARGET_CR 015
1184 /* Print operand X (an rtx) in assembler syntax to file FILE.
1185 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1186 For `%' followed by punctuation, CODE is the punctuation and X is null.
1188 In the following comments, the term "constant address" is used frequently.
1189 For an exact definition of what constitutes a "constant address" see the
1190 output_addr_const routine in final.c
1192 On the i860, the following target-specific special codes are recognized:
1194 `r' The operand can be anything, but if is is an immediate zero
1195 value (either integer or floating point) then it will be
1196 represented as `r0' or as `f0' (respectively).
1198 `m' The operand is a memory ref (to a constant address) but print
1199 its address as a constant.
1201 `L' The operand is a numeric constant, a constant address, or
1202 a memory ref to a constant address. Print the correct
1203 notation to yield the low part of the given value or
1204 address or the low part of the address of the referred
1207 `H' The operand is a numeric constant, a constant address, or
1208 a memory ref to a constant address. Print the correct
1209 notation to yield the high part of the given value or
1210 address or the high part of the address of the referred
1213 `h' The operand is a numeric constant, a constant address, or
1214 a memory ref to a constant address. Either print the
1215 correct notation to yield the plain high part of the
1216 given value or address (or the plain high part of the
1217 address of the memory object) or else print the correct
1218 notation to yield the "adjusted" high part of the given
1219 address (or of the address of the referred to memory object).
1221 The choice of what to print depends upon whether the address
1222 in question is relocatable or not. If it is relocatable,
1223 print the notation to get the adjusted high part. Otherwise
1224 just print the notation to get the plain high part. Note
1225 that "adjusted" high parts are generally used *only* when
1226 the next following instruction uses the low part of the
1227 address as an offset, as in `offset(reg)'.
1229 `R' The operand is a floating-pointer register. Print the
1230 name of the next following (32-bit) floating-point register.
1231 (This is used when moving a value into just the most
1232 significant part of a floating-point register pair.)
1234 `?' (takes no operand) Substitute the value of i860_reg_prefix
1235 at this point. The value of i860_reg_prefix is typically
1236 a null string for most i860 targets, but for System V
1237 Release 4 the i860 assembler syntax requires that all
1238 names of registers be prefixed with a percent-sign, so
1239 for SVR4, the value of i860_reg_prefix is initialized to
1243 extern char *i860_reg_prefix;
1244 extern unsigned long sfmode_constant_to_ulong ();
1246 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
1248 /* The following macro definition is overridden in i860v4.h
1249 because the svr4 i860 assembler required a different syntax
1250 for getting parts of constant/relocatable values. */
1252 #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
1253 do { fprintf (FILE, "%s%%", PART_CODE); \
1254 output_address (X); \
1257 #define OPERAND_LOW_PART "l"
1258 #define OPERAND_HIGH_PART "h"
1259 /* NOTE: All documentation available for the i860 sez that you must
1260 use "ha" to get the relocated high part of a relocatable, but
1261 reality sez different. */
1262 #define OPERAND_HIGH_ADJ_PART "ha"
1264 #define PRINT_OPERAND(FILE, X, CODE) \
1265 { if ((CODE) == '?') \
1266 fprintf (FILE, "%s", i860_reg_prefix); \
1267 else if (CODE == 'R') \
1268 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \
1269 else if (GET_CODE (X) == REG) \
1270 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \
1271 else if ((CODE) == 'm') \
1272 output_address (XEXP (X, 0)); \
1273 else if ((CODE) == 'L') \
1274 if (GET_CODE (X) == MEM) \
1275 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
1277 PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
1278 else if ((CODE) == 'H') \
1279 if (GET_CODE (X) == MEM) \
1280 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
1282 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
1283 else if ((CODE) == 'h') \
1284 if (GET_CODE (X) == MEM) \
1285 PRINT_OPERAND_PART (FILE, XEXP (X, 0), \
1286 const_int_operand (XEXP (X, 0)) \
1287 ? OPERAND_HIGH_PART \
1288 : OPERAND_HIGH_ADJ_PART); \
1290 PRINT_OPERAND_PART (FILE, X, \
1291 const_int_operand (X) \
1292 ? OPERAND_HIGH_PART \
1293 : OPERAND_HIGH_ADJ_PART); \
1294 else if (GET_CODE (X) == MEM) \
1295 output_address (XEXP (X, 0)); \
1296 else if ((CODE) == 'r' && (X) == const0_rtx) \
1297 fprintf (FILE, "%sr0", i860_reg_prefix); \
1298 else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
1299 fprintf (FILE, "%sf0", i860_reg_prefix); \
1300 else if (GET_CODE (X) == CONST_DOUBLE) \
1301 fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X)); \
1303 output_addr_const (FILE, X); }
1305 /* Print a memory address as an operand to reference that memory location. */
1307 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1308 { register rtx base, index = 0; \
1310 register rtx addr = ADDR; \
1311 if (GET_CODE (addr) == REG) \
1313 fprintf (FILE, "0(%s%s)", \
1314 i860_reg_prefix, reg_names[REGNO (addr)]); \
1316 else if (GET_CODE (addr) == CONST_DOUBLE \
1317 && GET_MODE (addr) == SFmode) \
1318 fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr)); \
1319 else if (GET_CODE (addr) == PLUS) \
1321 if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1322 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1323 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \
1324 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1325 else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1326 && (GET_CODE (XEXP (addr, 0)) == REG)) \
1327 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \
1328 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
1329 else if ((GET_CODE (XEXP (addr, 0)) == REG) \
1330 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1331 fprintf (FILE, "%s%s(%s%s)", \
1332 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \
1333 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1335 output_addr_const (FILE, addr); \
1339 output_addr_const (FILE, addr); \
1343 /* The following #defines are used when compiling the routines in
1344 libgcc1.c. Since the i860 calling conventions require single
1345 precision floats to be passed in the floating-point registers
1346 (rather than in the general registers) we have to build the
1347 libgcc1.c routines in such a way that they know the actual types
1348 of their formal arguments and the actual types of their return
1349 values. Otherwise, gcc will generate calls to the libgcc1.c
1350 routines, passing arguments in the floating-point registers,
1351 but the libgcc1.c routines will expect their arguments on the
1352 stack (where the i860 calling conventions require structs &
1353 unions to be passed). */
1355 #define FLOAT_TYPE_VALUE float
1356 #define INTIFY(FLOATVAL) (FLOATVAL)
1357 #define FLOATIFY(INTVAL) (INTVAL)
1358 #define FLOAT_ARG_TYPE float
1361 /* Optionally define this if you have added predicates to
1362 `MACHINE.c'. This macro is called within an initializer of an
1363 array of structures. The first field in the structure is the
1364 name of a predicate and the second field is an array of rtl
1365 codes. For each predicate, list all rtl codes that can be in
1366 expressions matched by the predicate. The list should have a
1367 trailing comma. Here is an example of two entries in the list
1368 for a typical RISC machine:
1370 #define PREDICATE_CODES \
1371 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
1372 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
1374 Defining this macro does not affect the generated code (however,
1375 incorrect definitions that omit an rtl code that may be matched
1376 by the predicate can cause the compiler to malfunction).
1377 Instead, it allows the table built by `genrecog' to be more
1378 compact and efficient, thus speeding up the compiler. The most
1379 important predicates to include in the list specified by this
1380 macro are thoses used in the most insn patterns.
1382 Note that for the i860 we have one more predicate, i.e.
1383 `single_insn_src_operand', however this is used only
1384 infrequently, so we don't put in the PREDICATE_CODES list.
1387 #define PREDICATE_CODES \
1388 {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
1389 {"arith_operand", {REG, SUBREG, CONST_INT}}, \
1390 {"logic_operand", {REG, SUBREG, CONST_INT}}, \
1391 {"shift_operand", {REG, SUBREG, CONST_INT}}, \
1392 {"compare_operand", {REG, SUBREG, CONST_INT}}, \
1393 {"arith_const_operand", {CONST_INT}}, \
1394 {"logic_const_operand", {CONST_INT}}, \
1395 {"bte_operand", {REG, SUBREG, CONST_INT}}, \
1396 {"indexed_operand", {MEM}}, \
1397 {"load_operand", {MEM}},
1399 /* Define the information needed to generate branch insns. This is stored
1400 from the compare operation. Note that we can't use "rtx" here since it
1401 hasn't been defined! */
1403 extern struct rtx_def *i860_compare_op0, *i860_compare_op1;
1405 /* Declare things which are defined in i860.c but called from
1408 extern unsigned long sfmode_constant_to_ulong ();
1409 extern char *output_load ();
1410 extern char *output_store ();
1411 extern char *output_move_double ();
1412 extern char *output_fp_move_double ();
1413 extern char *output_block_move ();
1414 extern char *output_delay_insn ();
1415 extern char *output_delayed_branch ();
1416 extern void output_load_address ();