1 /* Subroutines for insn-output.c for Intel 860
2 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
5 Written by Richard Stallman (rms@ai.mit.edu).
7 Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater
8 to the whims of the System V Release 4 assembler.
10 This file is part of GNU CC.
12 GNU CC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GNU CC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GNU CC; see the file COPYING. If not, write to
24 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-flags.h"
38 #include "insn-attr.h"
42 static rtx find_addr_reg ();
44 #ifndef I860_REG_PREFIX
45 #define I860_REG_PREFIX ""
48 char *i860_reg_prefix = I860_REG_PREFIX;
50 /* Save information from a "cmpxx" operation until the branch is emitted. */
52 rtx i860_compare_op0, i860_compare_op1;
54 /* Return non-zero if this pattern, can be evaluated safely, even if it
57 safe_insn_src_p (op, mode)
59 enum machine_mode mode;
61 /* Just experimenting. */
63 /* No floating point src is safe if it contains an arithmetic
64 operation, since that operation may trap. */
65 switch (GET_CODE (op))
77 return CONSTANT_ADDRESS_P (XEXP (op, 0));
79 /* We never need to negate or complement constants. */
81 return (mode != SFmode && mode != DFmode);
98 return (mode != SFmode && mode != DFmode);
106 if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
107 || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
116 /* Return 1 if REG is clobbered in IN.
117 Return 2 if REG is used in IN.
118 Return 3 if REG is both used and clobbered in IN.
119 Return 0 if neither. */
122 reg_clobbered_p (reg, in)
126 register enum rtx_code code;
131 code = GET_CODE (in);
133 if (code == SET || code == CLOBBER)
135 rtx dest = SET_DEST (in);
139 while (GET_CODE (dest) == STRICT_LOW_PART
140 || GET_CODE (dest) == SUBREG
141 || GET_CODE (dest) == SIGN_EXTRACT
142 || GET_CODE (dest) == ZERO_EXTRACT)
143 dest = XEXP (dest, 0);
147 else if (GET_CODE (dest) == REG
148 && refers_to_regno_p (REGNO (reg),
149 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
153 /* Anything that sets just part of the register
154 is considered using as well as setting it.
155 But note that a straight SUBREG of a single-word value
156 clobbers the entire value. */
157 if (dest != SET_DEST (in)
158 && ! (GET_CODE (SET_DEST (in)) == SUBREG
159 || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
166 used = refers_to_regno_p (REGNO (reg),
167 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
170 used = refers_to_regno_p (REGNO (reg),
171 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
175 return set + used * 2;
178 if (refers_to_regno_p (REGNO (reg),
179 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
185 /* Return non-zero if OP can be written to without screwing up
186 GCC's model of what's going on. It is assumed that this operand
187 appears in the dest position of a SET insn in a conditional
188 branch's delay slot. AFTER is the label to start looking from. */
190 operand_clobbered_before_used_after (op, after)
194 /* Just experimenting. */
195 if (GET_CODE (op) == CC0)
197 if (GET_CODE (op) == REG)
201 if (op == stack_pointer_rtx)
204 /* Scan forward from the label, to see if the value of OP
205 is clobbered before the first use. */
207 for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
209 if (GET_CODE (insn) == NOTE)
211 if (GET_CODE (insn) == INSN
212 || GET_CODE (insn) == JUMP_INSN
213 || GET_CODE (insn) == CALL_INSN)
215 switch (reg_clobbered_p (op, PATTERN (insn)))
225 /* If we reach another label without clobbering OP,
226 then we cannot safely write it here. */
227 else if (GET_CODE (insn) == CODE_LABEL)
229 if (GET_CODE (insn) == JUMP_INSN)
231 if (condjump_p (insn))
233 /* This is a jump insn which has already
234 been mangled. We can't tell what it does. */
235 if (GET_CODE (PATTERN (insn)) == PARALLEL)
237 if (! JUMP_LABEL (insn))
239 /* Keep following jumps. */
240 insn = JUMP_LABEL (insn);
246 /* In both of these cases, the first insn executed
247 for this op will be a orh whatever%h,%?r0,%?r31,
248 which is tolerable. */
249 if (GET_CODE (op) == MEM)
250 return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
255 /* Return non-zero if this pattern, as a source to a "SET",
256 is known to yield an instruction of unit size. */
258 single_insn_src_p (op, mode)
260 enum machine_mode mode;
262 switch (GET_CODE (op))
265 /* This is not always a single insn src, technically,
266 but output_delayed_branch knows how to deal with it. */
271 /* This is not a single insn src, technically,
272 but output_delayed_branch knows how to deal with it. */
281 /* We never need to negate or complement constants. */
283 return (mode != DFmode);
290 /* Detect cases that require multiple instructions. */
291 if (CONSTANT_P (XEXP (op, 1))
292 && !(GET_CODE (XEXP (op, 1)) == CONST_INT
293 && SMALL_INT (XEXP (op, 1))))
305 /* Not doing floating point, since they probably
306 take longer than the branch slot they might fill. */
307 return (mode != SFmode && mode != DFmode);
310 if (GET_CODE (XEXP (op, 1)) == NOT)
312 rtx arg = XEXP (XEXP (op, 1), 0);
314 && !(GET_CODE (arg) == CONST_INT
316 || INTVAL (arg) & 0xffff == 0)))
321 /* Both small and round numbers take one instruction;
323 if (CONSTANT_P (XEXP (op, 1))
324 && !(GET_CODE (XEXP (op, 1)) == CONST_INT
325 && (SMALL_INT (XEXP (op, 1))
326 || INTVAL (XEXP (op, 1)) & 0xffff == 0)))
336 if (SUBREG_WORD (op) != 0)
338 return single_insn_src_p (SUBREG_REG (op), mode);
340 /* Not doing floating point, since they probably
341 take longer than the branch slot they might fill. */
355 /* Return non-zero only if OP is a register of mode MODE,
358 reg_or_0_operand (op, mode)
360 enum machine_mode mode;
362 return (op == const0_rtx || register_operand (op, mode)
363 || op == CONST0_RTX (mode));
366 /* Return truth value of whether OP can be used as an operands in a three
367 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
370 arith_operand (op, mode)
372 enum machine_mode mode;
374 return (register_operand (op, mode)
375 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
378 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
381 logic_operand (op, mode)
383 enum machine_mode mode;
385 return (register_operand (op, mode)
386 || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
389 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
392 shift_operand (op, mode)
394 enum machine_mode mode;
396 return (register_operand (op, mode)
397 || (GET_CODE (op) == CONST_INT));
400 /* Return 1 if OP is a valid first operand for either a logical insn
401 or an add insn of mode MODE. */
404 compare_operand (op, mode)
406 enum machine_mode mode;
408 return (register_operand (op, mode)
409 || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
412 /* Return truth value of whether OP can be used as the 5-bit immediate
413 operand of a bte or btne insn. */
416 bte_operand (op, mode)
418 enum machine_mode mode;
420 return (register_operand (op, mode)
421 || (GET_CODE (op) == CONST_INT
422 && (unsigned) INTVAL (op) < 0x20));
425 /* Return 1 if OP is an indexed memory reference of mode MODE. */
428 indexed_operand (op, mode)
430 enum machine_mode mode;
432 return (GET_CODE (op) == MEM && GET_MODE (op) == mode
433 && GET_CODE (XEXP (op, 0)) == PLUS
434 && GET_MODE (XEXP (op, 0)) == SImode
435 && register_operand (XEXP (XEXP (op, 0), 0), SImode)
436 && register_operand (XEXP (XEXP (op, 0), 1), SImode));
439 /* Return 1 if OP is a suitable source operand for a load insn
443 load_operand (op, mode)
445 enum machine_mode mode;
447 return (memory_operand (op, mode) || indexed_operand (op, mode));
450 /* Return truth value of whether OP is a integer which fits the
451 range constraining immediate operands in add/subtract insns. */
456 enum machine_mode mode;
458 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
461 /* Return truth value of whether OP is a integer which fits the
462 range constraining immediate operands in logic insns. */
467 enum machine_mode mode;
469 return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
472 /* Return the best assembler insn template
473 for moving operands[1] into operands[0] as a fullword. */
476 singlemove_string (operands)
479 if (GET_CODE (operands[0]) == MEM)
481 if (GET_CODE (operands[1]) != MEM)
482 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
484 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
485 && (cc_prev_status.flags & CC_HI_R31_ADJ)
486 && cc_prev_status.mdep == XEXP (operands[0], 0)))
489 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
491 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
492 cc_status.mdep = XEXP (operands[0], 0);
493 return "st.l %r1,%L0(%?r31)";
496 return "st.l %r1,%0";
503 cc_status.flags &= ~CC_F0_IS_0;
504 xoperands[0] = gen_rtx (REG, SFmode, 32);
505 xoperands[1] = operands[1];
506 output_asm_insn (singlemove_string (xoperands), xoperands);
507 xoperands[1] = xoperands[0];
508 xoperands[0] = operands[0];
509 output_asm_insn (singlemove_string (xoperands), xoperands);
514 if (GET_CODE (operands[1]) == MEM)
516 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
518 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
519 && (cc_prev_status.flags & CC_HI_R31_ADJ)
520 && cc_prev_status.mdep == XEXP (operands[1], 0)))
523 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
525 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
526 cc_status.mdep = XEXP (operands[1], 0);
527 return "ld.l %L1(%?r31),%0";
529 return "ld.l %m1,%0";
531 if (GET_CODE (operands[1]) == CONST_INT)
533 if (operands[1] == const0_rtx)
534 return "mov %?r0,%0";
535 if((INTVAL (operands[1]) & 0xffff0000) == 0)
536 return "or %L1,%?r0,%0";
537 if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
538 return "adds %1,%?r0,%0";
539 if((INTVAL (operands[1]) & 0x0000ffff) == 0)
540 return "orh %H1,%?r0,%0";
545 /* Output assembler code to perform a doubleword move insn
546 with operands OPERANDS. */
549 output_move_double (operands)
552 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
554 rtx addreg0 = 0, addreg1 = 0;
556 /* First classify both operands. */
558 if (REG_P (operands[0]))
560 else if (offsettable_memref_p (operands[0]))
562 else if (GET_CODE (operands[0]) == MEM)
567 if (REG_P (operands[1]))
569 else if (CONSTANT_P (operands[1]))
571 else if (offsettable_memref_p (operands[1]))
573 else if (GET_CODE (operands[1]) == MEM)
578 /* Check for the cases that the operand constraints are not
579 supposed to allow to happen. Abort if we get one,
580 because generating code for these cases is painful. */
582 if (optype0 == RNDOP || optype1 == RNDOP)
585 /* If an operand is an unoffsettable memory ref, find a register
586 we can increment temporarily to make it refer to the second word. */
588 if (optype0 == MEMOP)
589 addreg0 = find_addr_reg (XEXP (operands[0], 0));
591 if (optype1 == MEMOP)
592 addreg1 = find_addr_reg (XEXP (operands[1], 0));
594 /* ??? Perhaps in some cases move double words
595 if there is a spare pair of floating regs. */
597 /* Ok, we can do one word at a time.
598 Normally we do the low-numbered word first,
599 but if either operand is autodecrementing then we
600 do the high-numbered word first.
602 In either case, set up in LATEHALF the operands to use
603 for the high-numbered word and in some cases alter the
604 operands in OPERANDS to be suitable for the low-numbered word. */
606 if (optype0 == REGOP)
607 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
608 else if (optype0 == OFFSOP)
609 latehalf[0] = adj_offsettable_operand (operands[0], 4);
611 latehalf[0] = operands[0];
613 if (optype1 == REGOP)
614 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
615 else if (optype1 == OFFSOP)
616 latehalf[1] = adj_offsettable_operand (operands[1], 4);
617 else if (optype1 == CNSTOP)
619 if (GET_CODE (operands[1]) == CONST_DOUBLE)
620 split_double (operands[1], &operands[1], &latehalf[1]);
621 else if (CONSTANT_P (operands[1]))
622 latehalf[1] = const0_rtx;
625 latehalf[1] = operands[1];
627 /* If the first move would clobber the source of the second one,
628 do them in the other order.
630 RMS says "This happens only for registers;
631 such overlap can't happen in memory unless the user explicitly
632 sets it up, and that is an undefined circumstance."
634 but it happens on the sparc when loading parameter registers,
635 so I am going to define that circumstance, and make it work
638 if (optype0 == REGOP && optype1 == REGOP
639 && REGNO (operands[0]) == REGNO (latehalf[1]))
641 CC_STATUS_PARTIAL_INIT;
642 /* Make any unoffsettable addresses point at high-numbered word. */
644 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
646 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
649 output_asm_insn (singlemove_string (latehalf), latehalf);
651 /* Undo the adds we just did. */
653 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
655 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
657 /* Do low-numbered word. */
658 return singlemove_string (operands);
660 else if (optype0 == REGOP && optype1 != REGOP
661 && reg_overlap_mentioned_p (operands[0], operands[1]))
663 /* Do the late half first. */
664 output_asm_insn (singlemove_string (latehalf), latehalf);
666 return singlemove_string (operands);
669 /* Normal case: do the two words, low-numbered first. */
671 output_asm_insn (singlemove_string (operands), operands);
673 CC_STATUS_PARTIAL_INIT;
674 /* Make any unoffsettable addresses point at high-numbered word. */
676 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
678 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
681 output_asm_insn (singlemove_string (latehalf), latehalf);
683 /* Undo the adds we just did. */
685 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
687 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
693 output_fp_move_double (operands)
696 /* If the source operand is any sort of zero, use f0 instead. */
698 if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
699 operands[1] = gen_rtx (REG, DFmode, F0_REGNUM);
701 if (FP_REG_P (operands[0]))
703 if (FP_REG_P (operands[1]))
704 return "fmov.dd %1,%0";
705 if (GET_CODE (operands[1]) == REG)
707 output_asm_insn ("ixfr %1,%0", operands);
708 operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
709 operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
712 if (operands[1] == CONST0_RTX (DFmode))
713 return "fmov.dd f0,%0";
714 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
716 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
717 && (cc_prev_status.flags & CC_HI_R31_ADJ)
718 && cc_prev_status.mdep == XEXP (operands[1], 0)))
721 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
723 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
724 cc_status.mdep = XEXP (operands[1], 0);
725 return "fld.d %L1(%?r31),%0";
727 return "fld.d %1,%0";
729 else if (FP_REG_P (operands[1]))
731 if (GET_CODE (operands[0]) == REG)
733 output_asm_insn ("fxfr %1,%0", operands);
734 operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
735 operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
738 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
740 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
741 && (cc_prev_status.flags & CC_HI_R31_ADJ)
742 && cc_prev_status.mdep == XEXP (operands[0], 0)))
745 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
747 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
748 cc_status.mdep = XEXP (operands[0], 0);
749 return "fst.d %1,%L0(%?r31)";
751 return "fst.d %1,%0";
759 /* Return a REG that occurs in ADDR with coefficient 1.
760 ADDR can be effectively incremented by incrementing REG. */
766 while (GET_CODE (addr) == PLUS)
768 if (GET_CODE (XEXP (addr, 0)) == REG)
769 addr = XEXP (addr, 0);
770 else if (GET_CODE (XEXP (addr, 1)) == REG)
771 addr = XEXP (addr, 1);
772 else if (CONSTANT_P (XEXP (addr, 0)))
773 addr = XEXP (addr, 1);
774 else if (CONSTANT_P (XEXP (addr, 1)))
775 addr = XEXP (addr, 0);
779 if (GET_CODE (addr) == REG)
786 /* Return a template for a load instruction with mode MODE and
787 arguments from the string ARGS.
789 This string is in static storage. */
792 load_opcode (mode, args, reg)
793 enum machine_mode mode;
829 sprintf (buf, "%s %s", opcode, args);
833 /* Return a template for a store instruction with mode MODE and
834 arguments from the string ARGS.
836 This string is in static storage. */
839 store_opcode (mode, args, reg)
840 enum machine_mode mode;
876 sprintf (buf, "%s %s", opcode, args);
880 /* Output a store-in-memory whose operands are OPERANDS[0,1].
881 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
883 This function returns a template for an insn.
884 This is in static storage.
886 It may also output some insns directly.
887 It may alter the values of operands[0] and operands[1]. */
890 output_store (operands)
893 enum machine_mode mode = GET_MODE (operands[0]);
894 rtx address = XEXP (operands[0], 0);
897 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
898 cc_status.mdep = address;
900 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
901 && (cc_prev_status.flags & CC_HI_R31_ADJ)
902 && address == cc_prev_status.mdep))
905 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
906 cc_prev_status.mdep = address;
909 /* Store zero in two parts when appropriate. */
910 if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
911 return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
913 /* Code below isn't smart enough to move a doubleword in two parts,
914 so use output_move_double to do that in the cases that require it. */
915 if ((mode == DImode || mode == DFmode)
916 && ! FP_REG_P (operands[1]))
917 return output_move_double (operands);
919 return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
922 /* Output a load-from-memory whose operands are OPERANDS[0,1].
923 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
925 This function returns a template for an insn.
926 This is in static storage.
928 It may also output some insns directly.
929 It may alter the values of operands[0] and operands[1]. */
932 output_load (operands)
935 enum machine_mode mode = GET_MODE (operands[0]);
936 rtx address = XEXP (operands[1], 0);
938 /* We don't bother trying to see if we know %hi(address).
939 This is because we are doing a load, and if we know the
940 %hi value, we probably also know that value in memory. */
941 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
942 cc_status.mdep = address;
944 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
945 && (cc_prev_status.flags & CC_HI_R31_ADJ)
946 && address == cc_prev_status.mdep
947 && cc_prev_status.mdep == cc_status.mdep))
950 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
951 cc_prev_status.mdep = address;
954 /* Code below isn't smart enough to move a doubleword in two parts,
955 so use output_move_double to do that in the cases that require it. */
956 if ((mode == DImode || mode == DFmode)
957 && ! FP_REG_P (operands[0]))
958 return output_move_double (operands);
960 return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
964 /* Load the address specified by OPERANDS[3] into the register
965 specified by OPERANDS[0].
967 OPERANDS[3] may be the result of a sum, hence it could either be:
972 (3) REG + REG + CONST_INT
973 (4) REG + REG (special case of 3).
975 Note that (3) is not a legitimate address.
976 All cases are handled here. */
979 output_load_address (operands)
984 if (CONSTANT_P (operands[3]))
986 output_asm_insn ("mov %3,%0", operands);
990 if (REG_P (operands[3]))
992 if (REGNO (operands[0]) != REGNO (operands[3]))
993 output_asm_insn ("shl %?r0,%3,%0", operands);
997 if (GET_CODE (operands[3]) != PLUS)
1000 base = XEXP (operands[3], 0);
1001 offset = XEXP (operands[3], 1);
1003 if (GET_CODE (base) == CONST_INT)
1010 if (GET_CODE (offset) != CONST_INT)
1012 /* Operand is (PLUS (REG) (REG)). */
1014 offset = const0_rtx;
1020 operands[7] = offset;
1021 CC_STATUS_PARTIAL_INIT;
1022 if (SMALL_INT (offset))
1023 output_asm_insn ("adds %7,%6,%0", operands);
1025 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
1027 else if (GET_CODE (base) == PLUS)
1029 operands[6] = XEXP (base, 0);
1030 operands[7] = XEXP (base, 1);
1031 operands[8] = offset;
1033 CC_STATUS_PARTIAL_INIT;
1034 if (SMALL_INT (offset))
1035 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
1037 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
1044 /* Output code to place a size count SIZE in register REG.
1045 Because block moves are pipelined, we don't include the
1046 first element in the transfer of SIZE to REG.
1047 For this, we subtract ALIGN. (Actually, I think it is not
1048 right to subtract on this machine, so right now we don't.) */
1051 output_size_for_block_move (size, reg, align)
1052 rtx size, reg, align;
1057 xoperands[1] = size;
1058 xoperands[2] = align;
1061 cc_status.flags &= ~ CC_KNOW_HI_R31;
1062 output_asm_insn (singlemove_string (xoperands), xoperands);
1064 if (GET_CODE (size) == REG)
1065 output_asm_insn ("sub %2,%1,%0", xoperands);
1069 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
1070 cc_status.flags &= ~ CC_KNOW_HI_R31;
1071 output_asm_insn ("mov %1,%0", xoperands);
1076 /* Emit code to perform a block move.
1078 OPERANDS[0] is the destination.
1079 OPERANDS[1] is the source.
1080 OPERANDS[2] is the size.
1081 OPERANDS[3] is the known safe alignment.
1082 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1085 output_block_move (operands)
1088 /* A vector for our computed operands. Note that load_output_address
1089 makes use of (and can clobber) up to the 8th element of this vector. */
1092 static int movstrsi_label = 0;
1094 rtx temp1 = operands[4];
1095 rtx alignrtx = operands[3];
1096 int align = INTVAL (alignrtx);
1099 xoperands[0] = operands[0];
1100 xoperands[1] = operands[1];
1101 xoperands[2] = temp1;
1103 /* We can't move more than four bytes at a time
1104 because we have only one register to move them through. */
1108 alignrtx = gen_rtx (CONST_INT, VOIDmode, 4);
1111 /* Recognize special cases of block moves. These occur
1112 when GNU C++ is forced to treat something as BLKmode
1113 to keep it in memory, when its mode could be represented
1114 with something smaller.
1116 We cannot do this for global variables, since we don't know
1117 what pages they don't cross. Sigh. */
1118 if (GET_CODE (operands[2]) == CONST_INT
1119 && ! CONSTANT_ADDRESS_P (operands[0])
1120 && ! CONSTANT_ADDRESS_P (operands[1]))
1122 int size = INTVAL (operands[2]);
1123 rtx op0 = xoperands[0];
1124 rtx op1 = xoperands[1];
1126 if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
1128 if (memory_address_p (SImode, plus_constant (op0, size))
1129 && memory_address_p (SImode, plus_constant (op1, size)))
1131 cc_status.flags &= ~CC_KNOW_HI_R31;
1132 for (i = (size>>2)-1; i >= 0; i--)
1134 xoperands[0] = plus_constant (op0, i * 4);
1135 xoperands[1] = plus_constant (op1, i * 4);
1136 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1142 else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
1144 if (memory_address_p (HImode, plus_constant (op0, size))
1145 && memory_address_p (HImode, plus_constant (op1, size)))
1147 cc_status.flags &= ~CC_KNOW_HI_R31;
1148 for (i = (size>>1)-1; i >= 0; i--)
1150 xoperands[0] = plus_constant (op0, i * 2);
1151 xoperands[1] = plus_constant (op1, i * 2);
1152 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1158 else if (size <= 16)
1160 if (memory_address_p (QImode, plus_constant (op0, size))
1161 && memory_address_p (QImode, plus_constant (op1, size)))
1163 cc_status.flags &= ~CC_KNOW_HI_R31;
1164 for (i = size-1; i >= 0; i--)
1166 xoperands[0] = plus_constant (op0, i);
1167 xoperands[1] = plus_constant (op1, i);
1168 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1176 /* Since we clobber untold things, nix the condition codes. */
1179 /* This is the size of the transfer.
1180 Either use the register which already contains the size,
1181 or use a free register (used by no operands). */
1182 output_size_for_block_move (operands[2], operands[4], alignrtx);
1185 /* Also emit code to decrement the size value by ALIGN. */
1186 zoperands[0] = operands[0];
1187 zoperands[3] = plus_constant (operands[0], align);
1188 output_load_address (zoperands);
1191 /* Generate number for unique label. */
1193 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1195 /* Calculate the size of the chunks we will be trying to move first. */
1198 if ((align & 3) == 0)
1200 else if ((align & 1) == 0)
1206 /* Copy the increment (negative) to a register for bla insn. */
1208 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, - chunk_size);
1209 xoperands[5] = operands[5];
1210 output_asm_insn ("adds %4,%?r0,%5", xoperands);
1212 /* Predecrement the loop counter. This happens again also in the `bla'
1213 instruction which precedes the loop, but we need to have it done
1214 two times before we enter the loop because of the bizarre semantics
1215 of the bla instruction. */
1217 output_asm_insn ("adds %5,%2,%2", xoperands);
1219 /* Check for the case where the original count was less than or equal to
1220 zero. Avoid going through the loop at all if the original count was
1221 indeed less than or equal to zero. Note that we treat the count as
1222 if it were a signed 32-bit quantity here, rather than an unsigned one,
1223 even though we really shouldn't. We have to do this because of the
1224 semantics of the `ble' instruction, which assume that the count is
1225 a signed 32-bit value. Anyway, in practice it won't matter because
1226 nobody is going to try to do a memcpy() of more than half of the
1227 entire address space (i.e. 2 gigabytes) anyway. */
1229 output_asm_insn ("bc .Le%3", xoperands);
1231 /* Make available a register which is a temporary. */
1233 xoperands[6] = operands[6];
1235 /* Now the actual loop.
1236 In xoperands, elements 1 and 0 are the input and output vectors.
1237 Element 2 is the loop index. Element 5 is the increment. */
1239 output_asm_insn ("subs %1,%5,%1", xoperands);
1240 output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
1241 output_asm_insn ("adds %0,%2,%6", xoperands);
1242 output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */
1243 output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */
1244 output_asm_insn ("adds %5,%6,%6", xoperands);
1246 /* NOTE: The code here which is supposed to handle the cases where the
1247 sources and destinations are known to start on a 4 or 2 byte boundary
1248 are currently broken. They fail to do anything about the overflow
1249 bytes which might still need to be copied even after we have copied
1250 some number of words or halfwords. Thus, for now we use the lowest
1251 common denominator, i.e. the code which just copies some number of
1252 totally unaligned individual bytes. (See the calculation of
1253 chunk_size above. */
1255 if (chunk_size == 4)
1257 output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
1258 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1259 output_asm_insn ("st.l %?r31,8(%6)", xoperands);
1261 else if (chunk_size == 2)
1263 output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
1264 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1265 output_asm_insn ("st.s %?r31,4(%6)", xoperands);
1267 else /* chunk_size == 1 */
1269 output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
1270 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1271 output_asm_insn ("st.b %?r31,2(%6)", xoperands);
1273 output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */
1278 /* Output a delayed branch insn with the delay insn in its
1279 branch slot. The delayed branch insn template is in TEMPLATE,
1280 with operands OPERANDS. The insn in its delay slot is INSN.
1282 As a special case, since we know that all memory transfers are via
1283 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1284 reference around the branch as
1288 ld/st l%x(%?r31),...
1290 As another special case, we handle loading (SYMBOL_REF ...) and
1291 other large constants around branches as well:
1300 output_delayed_branch (template, operands, insn)
1305 rtx src = XVECEXP (PATTERN (insn), 0, 1);
1306 rtx dest = XVECEXP (PATTERN (insn), 0, 0);
1308 /* See if we are doing some branch together with setting some register
1309 to some 32-bit value which does (or may) have some of the high-order
1310 16 bits set. If so, we need to set the register in two stages. One
1311 stage must be done before the branch, and the other one can be done
1312 in the delay slot. */
1314 if ( (GET_CODE (src) == CONST_INT
1315 && ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0)
1316 || (GET_CODE (src) == SYMBOL_REF)
1317 || (GET_CODE (src) == LABEL_REF)
1318 || (GET_CODE (src) == CONST))
1321 xoperands[0] = dest;
1324 CC_STATUS_PARTIAL_INIT;
1325 /* Output the `orh' insn. */
1326 output_asm_insn ("orh %H1,%?r0,%0", xoperands);
1328 /* Output the branch instruction next. */
1329 output_asm_insn (template, operands);
1331 /* Now output the `or' insn. */
1332 output_asm_insn ("or %L1,%0,%0", xoperands);
1334 else if ((GET_CODE (src) == MEM
1335 && CONSTANT_ADDRESS_P (XEXP (src, 0)))
1336 || (GET_CODE (dest) == MEM
1337 && CONSTANT_ADDRESS_P (XEXP (dest, 0))))
1340 char *split_template;
1341 xoperands[0] = dest;
1344 /* Output the `orh' insn. */
1345 if (GET_CODE (src) == MEM)
1347 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1348 && (cc_prev_status.flags & CC_HI_R31_ADJ)
1349 && cc_prev_status.mdep == XEXP (operands[1], 0)))
1352 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands);
1354 split_template = load_opcode (GET_MODE (dest),
1355 "%L1(%?r31),%0", dest);
1359 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1360 && (cc_prev_status.flags & CC_HI_R31_ADJ)
1361 && cc_prev_status.mdep == XEXP (operands[0], 0)))
1364 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands);
1366 split_template = store_opcode (GET_MODE (dest),
1367 "%r1,%L0(%?r31)", src);
1370 /* Output the branch instruction next. */
1371 output_asm_insn (template, operands);
1373 /* Now output the load or store.
1374 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1375 output_asm_insn (split_template, xoperands);
1379 int insn_code_number;
1380 rtx pat = gen_rtx (SET, VOIDmode, dest, src);
1381 rtx delay_insn = gen_rtx (INSN, VOIDmode, 0, 0, 0, pat, -1, 0, 0);
1384 /* Output the branch instruction first. */
1385 output_asm_insn (template, operands);
1387 /* Now recognize the insn which we put in its delay slot.
1388 We must do this after outputting the branch insn,
1389 since operands may just be a pointer to `recog_operand'. */
1390 INSN_CODE (delay_insn) = insn_code_number = recog (pat, delay_insn);
1391 if (insn_code_number == -1)
1394 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1396 if (GET_CODE (recog_operand[i]) == SUBREG)
1397 recog_operand[i] = alter_subreg (recog_operand[i]);
1400 insn_extract (delay_insn);
1401 if (! constrain_operands (insn_code_number, 1))
1402 fatal_insn_not_found (delay_insn);
1404 template = insn_template[insn_code_number];
1406 template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1407 output_asm_insn (template, recog_operand);
1413 /* Output a newly constructed insn DELAY_INSN. */
1415 output_delay_insn (delay_insn)
1419 int insn_code_number;
1422 /* Now recognize the insn which we put in its delay slot.
1423 We must do this after outputting the branch insn,
1424 since operands may just be a pointer to `recog_operand'. */
1425 insn_code_number = recog_memoized (delay_insn);
1426 if (insn_code_number == -1)
1429 /* Extract the operands of this delay insn. */
1430 INSN_CODE (delay_insn) = insn_code_number;
1431 insn_extract (delay_insn);
1433 /* It is possible that this insn has not been properly scanned by final
1434 yet. If this insn's operands don't appear in the peephole's
1435 actual operands, then they won't be fixed up by final, so we
1436 make sure they get fixed up here. -- This is a kludge. */
1437 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1439 if (GET_CODE (recog_operand[i]) == SUBREG)
1440 recog_operand[i] = alter_subreg (recog_operand[i]);
1443 #ifdef REGISTER_CONSTRAINTS
1444 if (! constrain_operands (insn_code_number))
1448 cc_prev_status = cc_status;
1450 /* Update `cc_status' for this instruction.
1451 The instruction's output routine may change it further.
1452 If the output routine for a jump insn needs to depend
1453 on the cc status, it should look at cc_prev_status. */
1455 NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn);
1457 /* Now get the template for what this insn would
1458 have been, without the branch. */
1460 template = insn_template[insn_code_number];
1462 template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1463 output_asm_insn (template, recog_operand);
1467 /* Special routine to convert an SFmode value represented as a
1468 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1469 We convert the value from a double precision floating-point
1470 value to single precision first, and thence to a bit-wise
1471 equivalent unsigned long value. This routine is used when
1472 generating an immediate move of an SFmode value directly
1473 into a general register because the svr4 assembler doesn't
1474 grok floating literals in instruction operand contexts. */
1477 sfmode_constant_to_ulong (x)
1481 union { float f; unsigned long i; } u2;
1483 if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
1486 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1487 error IEEE emulation needed
1489 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1494 /* This function generates the assembly code for function entry.
1495 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1497 ASM_FILE is a stdio stream to output the code to.
1498 SIZE is an int: how many units of temporary storage to allocate.
1500 Refer to the array `regs_ever_live' to determine which registers
1501 to save; `regs_ever_live[I]' is nonzero if register number I
1502 is ever used in the function. This macro is responsible for
1503 knowing which registers should not be saved even if used.
1505 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1506 between the new `fp' value and the new `sp' value after the
1507 prologue is done. `frame_upper_bytes' is the count of bytes
1508 that will lie between the new `fp' and the *old* `sp' value
1509 after the new `fp' is setup (in the prologue). The upper
1510 part of each frame always includes at least 2 words (8 bytes)
1511 to hold the saved frame pointer and the saved return address.
1513 The svr4 ABI for the i860 now requires that the values of the
1514 stack pointer and frame pointer registers be kept aligned to
1515 16-byte boundaries at all times. We obey that restriction here.
1517 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1518 exactly where the "preserved" registers should be saved. The native
1519 svr4 C compiler I now have doesn't help to clarify the requirements
1520 very much because it is plainly out-of-date and non-ABI-compliant
1521 (in at least one important way, i.e. how it generates function
1524 The native svr4 C compiler saves the "preserved" registers (i.e.
1525 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1526 offsets from the frame pointer).
1528 Previous versions of GCC also saved the "preserved" registers in the
1529 "negative" part of the frame, but they saved them using positive
1530 offsets from the (adjusted) stack pointer (after it had been adjusted
1531 to allocate space for the new frame). That's just plain wrong
1532 because if the current function calls alloca(), the stack pointer
1533 will get moved, and it will be impossible to restore the registers
1534 properly again after that.
1536 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1537 by copying their values either into various "preserved" registers or
1538 into stack slots in the lower part of the current frame (as seemed
1539 appropriate, depending upon subsequent usage of these values).
1541 Here we want to save the preserved registers at some offset from the
1542 frame pointer register so as to avoid any possible problems arising
1543 from calls to alloca(). We can either save them at small positive
1544 offsets from the frame pointer, or at small negative offsets from
1545 the frame pointer. If we save them at small negative offsets from
1546 the frame pointer (i.e. in the lower part of the frame) then we
1547 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1548 many bytes of space we plan to use in the lower part of the frame
1549 for this purpose. Since other parts of the compiler reference the
1550 value of STARTING_FRAME_OFFSET long before final() calls this function,
1551 we would have to go ahead and assume the worst-case storage requirements
1552 for saving all of the "preserved" registers (and use that number, i.e.
1553 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1554 the lower part of the frame. That could potentially be very wasteful,
1555 and that wastefulness could really hamper people compiling for embedded
1556 i860 targets with very tight limits on stack space. Thus, we choose
1557 here to save the preserved registers in the upper part of the
1558 frame, so that we can decide at the very last minute how much (or how
1559 little) space we must allocate for this purpose.
1561 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1562 registers must always be saved so that the saved values of registers
1563 with higher numbers are at higher addresses. We obey that restriction
1566 There are two somewhat different ways that you can generate prologues
1567 here... i.e. pedantically ABI-compliant, and the "other" way. The
1568 "other" way is more consistent with what is currently generated by the
1569 "native" svr4 C compiler for the i860. That's important if you want
1570 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1571 The SVR4 SDB for the i860 insists on having function prologues be
1574 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1575 in the i860svr4.h file. (By default this is *not* defined).
1577 The differences between the ABI-compliant and non-ABI-compliant prologues
1578 are that (a) the ABI version seems to require the use of *signed*
1579 (rather than unsigned) adds and subtracts, and (b) the ordering of
1580 the various steps (e.g. saving preserved registers, saving the
1581 return address, setting up the new frame pointer value) is different.
1583 For strict ABI compliance, it seems to be the case that the very last
1584 thing that is supposed to happen in the prologue is getting the frame
1585 pointer set to its new value (but only after everything else has
1586 already been properly setup). We do that here, but only if the symbol
1587 I860_STRICT_ABI_PROLOGUES is defined.
1590 #ifndef STACK_ALIGNMENT
1591 #define STACK_ALIGNMENT 16
1594 extern char call_used_regs[];
1595 extern int leaf_function_p ();
1597 char *current_function_original_name;
1599 static int must_preserve_r1;
1600 static unsigned must_preserve_bytes;
1603 function_prologue (asm_file, local_bytes)
1604 register FILE *asm_file;
1605 register unsigned local_bytes;
1607 register unsigned frame_lower_bytes;
1608 register unsigned frame_upper_bytes;
1609 register unsigned total_fsize;
1610 register unsigned preserved_reg_bytes = 0;
1611 register unsigned i;
1612 register unsigned preserved_so_far = 0;
1614 must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
1615 must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
1617 /* Count registers that need preserving. Ignore r0. It never needs
1620 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1622 if (regs_ever_live[i] && ! call_used_regs[i])
1623 preserved_reg_bytes += 4;
1626 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1628 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1630 /* The upper part of each frame will contain the saved fp,
1631 the saved r1, and stack slots for all of the other "preserved"
1632 registers that we find we will need to save & restore. */
1634 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1636 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1639 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1641 total_fsize = frame_upper_bytes + frame_lower_bytes;
1643 #ifndef I860_STRICT_ABI_PROLOGUES
1645 /* There are two kinds of function prologues.
1646 You use the "small" version if the total frame size is
1647 small enough so that it can fit into an immediate 16-bit
1648 value in one instruction. Otherwise, you use the "large"
1649 version of the function prologue. */
1651 if (total_fsize > 0x7fff)
1653 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1654 but the native C compiler on svr4 uses `addu'. */
1656 fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1657 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1659 /* Save the old frame pointer. */
1661 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1662 i860_reg_prefix, i860_reg_prefix);
1664 /* Setup the new frame pointer. The ABI sez to do this after
1665 preserving registers (using adds), but that's not what the
1666 native C compiler on svr4 does. */
1668 fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
1669 i860_reg_prefix, i860_reg_prefix);
1671 /* Get the value of frame_lower_bytes into r31. */
1673 fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1674 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1675 fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1676 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1678 /* Now re-adjust the stack pointer using the value in r31.
1679 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1681 fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
1682 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1684 /* Preserve registers. The ABI sez to do this before setting
1685 up the new frame pointer, but that's not what the native
1686 C compiler on svr4 does. */
1688 for (i = 1; i < 32; i++)
1689 if (regs_ever_live[i] && ! call_used_regs[i])
1690 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1691 i860_reg_prefix, reg_names[i],
1692 must_preserve_bytes + (4 * preserved_so_far++),
1695 for (i = 32; i < 64; i++)
1696 if (regs_ever_live[i] && ! call_used_regs[i])
1697 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1698 i860_reg_prefix, reg_names[i],
1699 must_preserve_bytes + (4 * preserved_so_far++),
1702 /* Save the return address. */
1704 if (must_preserve_r1)
1705 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1706 i860_reg_prefix, i860_reg_prefix);
1710 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1711 but the native C compiler on svr4 uses `addu'. */
1713 fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1714 total_fsize, i860_reg_prefix, i860_reg_prefix);
1716 /* Save the old frame pointer. */
1718 fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1719 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1721 /* Setup the new frame pointer. The ABI sez to do this after
1722 preserving registers and after saving the return address,
1723 (and its saz to do this using adds), but that's not what the
1724 native C compiler on svr4 does. */
1726 fprintf (asm_file, "\taddu %d,%ssp,%sfp\n",
1727 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1729 /* Preserve registers. The ABI sez to do this before setting
1730 up the new frame pointer, but that's not what the native
1731 compiler on svr4 does. */
1733 for (i = 1; i < 32; i++)
1734 if (regs_ever_live[i] && ! call_used_regs[i])
1735 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1736 i860_reg_prefix, reg_names[i],
1737 must_preserve_bytes + (4 * preserved_so_far++),
1740 for (i = 32; i < 64; i++)
1741 if (regs_ever_live[i] && ! call_used_regs[i])
1742 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1743 i860_reg_prefix, reg_names[i],
1744 must_preserve_bytes + (4 * preserved_so_far++),
1747 /* Save the return address. The ABI sez to do this earlier,
1748 and also via an offset from %sp, but the native C compiler
1749 on svr4 does it later (i.e. now) and uses an offset from
1752 if (must_preserve_r1)
1753 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1754 i860_reg_prefix, i860_reg_prefix);
1757 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1759 /* There are two kinds of function prologues.
1760 You use the "small" version if the total frame size is
1761 small enough so that it can fit into an immediate 16-bit
1762 value in one instruction. Otherwise, you use the "large"
1763 version of the function prologue. */
1765 if (total_fsize > 0x7fff)
1767 /* Adjust the stack pointer (thereby allocating a new frame). */
1769 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1770 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1772 /* Save the caller's frame pointer. */
1774 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1775 i860_reg_prefix, i860_reg_prefix);
1777 /* Save return address. */
1779 if (must_preserve_r1)
1780 fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
1781 i860_reg_prefix, i860_reg_prefix);
1783 /* Get the value of frame_lower_bytes into r31 for later use. */
1785 fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1786 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1787 fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1788 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1790 /* Now re-adjust the stack pointer using the value in r31. */
1792 fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
1793 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1795 /* Pre-compute value to be used as the new frame pointer. */
1797 fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
1798 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1800 /* Preserve registers. */
1802 for (i = 1; i < 32; i++)
1803 if (regs_ever_live[i] && ! call_used_regs[i])
1804 fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
1805 i860_reg_prefix, reg_names[i],
1806 must_preserve_bytes + (4 * preserved_so_far++),
1809 for (i = 32; i < 64; i++)
1810 if (regs_ever_live[i] && ! call_used_regs[i])
1811 fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
1812 i860_reg_prefix, reg_names[i],
1813 must_preserve_bytes + (4 * preserved_so_far++),
1816 /* Actually set the new value of the frame pointer. */
1818 fprintf (asm_file, "\tmov %sr31,%sfp\n",
1819 i860_reg_prefix, i860_reg_prefix);
1823 /* Adjust the stack pointer. */
1825 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1826 total_fsize, i860_reg_prefix, i860_reg_prefix);
1828 /* Save the caller's frame pointer. */
1830 fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1831 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1833 /* Save the return address. */
1835 if (must_preserve_r1)
1836 fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
1837 i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
1839 /* Preserve registers. */
1841 for (i = 1; i < 32; i++)
1842 if (regs_ever_live[i] && ! call_used_regs[i])
1843 fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
1844 i860_reg_prefix, reg_names[i],
1845 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1848 for (i = 32; i < 64; i++)
1849 if (regs_ever_live[i] && ! call_used_regs[i])
1850 fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
1851 i860_reg_prefix, reg_names[i],
1852 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1855 /* Setup the new frame pointer. */
1857 fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
1858 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1860 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1862 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1863 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
1864 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1867 /* This function generates the assembly code for function exit.
1868 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1870 ASM_FILE is a stdio stream to output the code to.
1871 SIZE is an int: how many units of temporary storage to allocate.
1873 The function epilogue should not depend on the current stack pointer!
1874 It should use the frame pointer only. This is mandatory because
1875 of alloca; we also take advantage of it to omit stack adjustments
1878 Note that when we go to restore the preserved register values we must
1879 not try to address their slots by using offsets from the stack pointer.
1880 That's because the stack pointer may have been moved during the function
1881 execution due to a call to alloca(). Rather, we must restore all
1882 preserved registers via offsets from the frame pointer value.
1884 Note also that when the current frame is being "popped" (by adjusting
1885 the value of the stack pointer) on function exit, we must (for the
1886 sake of alloca) set the new value of the stack pointer based upon
1887 the current value of the frame pointer. We can't just add what we
1888 believe to be the (static) frame size to the stack pointer because
1889 if we did that, and alloca() had been called during this function,
1890 we would end up returning *without* having fully deallocated all of
1891 the space grabbed by alloca. If that happened, and a function
1892 containing one or more alloca() calls was called over and over again,
1893 then the stack would grow without limit!
1895 Finally note that the epilogues generated here are completely ABI
1896 compliant. They go out of their way to insure that the value in
1897 the frame pointer register is never less than the value in the stack
1898 pointer register. It's not clear why this relationship needs to be
1899 maintained at all times, but maintaining it only costs one extra
1900 instruction, so what the hell.
1903 /* This corresponds to a version 4 TDESC structure. Lower numbered
1904 versions successively omit the last word of the structure. We
1905 don't try to handle version 5 here. */
1907 typedef struct TDESC_flags {
1910 int callable_block:1;
1912 int fregs:6; /* fp regs 2-7 */
1913 int iregs:16; /* regs 0-15 */
1916 typedef struct TDESC {
1918 int integer_reg_offset; /* same as must_preserve_bytes */
1919 int floating_point_reg_offset;
1920 unsigned int positive_frame_size; /* same as frame_upper_bytes */
1921 unsigned int negative_frame_size; /* same as frame_lower_bytes */
1925 function_epilogue (asm_file, local_bytes)
1926 register FILE *asm_file;
1927 register unsigned local_bytes;
1929 register unsigned frame_upper_bytes;
1930 register unsigned frame_lower_bytes;
1931 register unsigned preserved_reg_bytes = 0;
1932 register unsigned i;
1933 register unsigned restored_so_far = 0;
1934 register unsigned int_restored;
1935 register unsigned mask;
1936 unsigned intflags=0;
1937 register TDESC_flags *flags = (TDESC_flags *) &intflags;
1940 flags->reg_packing = 1;
1941 flags->iregs = 8; /* old fp always gets saved */
1943 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1945 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1947 /* Count the number of registers that were preserved in the prologue.
1948 Ignore r0. It is never preserved. */
1950 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1952 if (regs_ever_live[i] && ! call_used_regs[i])
1953 preserved_reg_bytes += 4;
1956 /* The upper part of each frame will contain only saved fp,
1957 the saved r1, and stack slots for all of the other "preserved"
1958 registers that we find we will need to save & restore. */
1960 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1962 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
1965 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1967 /* Restore all of the "preserved" registers that need restoring. */
1971 for (i = 1; i < 32; i++, mask<<=1)
1972 if (regs_ever_live[i] && ! call_used_regs[i]) {
1973 fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
1974 must_preserve_bytes + (4 * restored_so_far++),
1975 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
1976 if (i > 3 && i < 16)
1977 flags->iregs |= mask;
1980 int_restored = restored_so_far;
1983 for (i = 32; i < 64; i++) {
1984 if (regs_ever_live[i] && ! call_used_regs[i]) {
1985 fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
1986 must_preserve_bytes + (4 * restored_so_far++),
1987 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
1988 if (i > 33 & i < 40)
1989 flags->fregs |= mask;
1991 if (i > 33 && i < 40)
1995 /* Get the value we plan to use to restore the stack pointer into r31. */
1997 fprintf (asm_file, "\tadds %d,%sfp,%sr31\n",
1998 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
2000 /* Restore the return address and the old frame pointer. */
2002 if (must_preserve_r1) {
2003 fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
2004 i860_reg_prefix, i860_reg_prefix);
2008 fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
2009 i860_reg_prefix, i860_reg_prefix);
2011 /* Return and restore the old stack pointer value. */
2013 fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2014 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
2016 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
2017 if (! frame_lower_bytes) {
2019 if (! frame_upper_bytes) {
2021 if (restored_so_far == int_restored) /* No FP saves */
2025 assemble_name(asm_file,current_function_original_name);
2026 fputs(".TDESC:\n", asm_file);
2027 fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags);
2028 fprintf(asm_file, "%s %d\n", ASM_LONG,
2029 int_restored ? must_preserve_bytes : 0);
2030 if (flags->version > 1) {
2031 fprintf(asm_file, "%s %d\n", ASM_LONG,
2032 (restored_so_far == int_restored) ? 0 : must_preserve_bytes +
2033 (4 * int_restored));
2034 if (flags->version > 2) {
2035 fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes);
2036 if (flags->version > 3)
2037 fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes);
2041 fprintf(asm_file, "%s ", ASM_LONG);
2042 assemble_name(asm_file, current_function_original_name);
2043 fprintf(asm_file, "\n%s ", ASM_LONG);
2044 assemble_name(asm_file, current_function_original_name);
2045 fputs(".TDESC\n", asm_file);