1 /* Subroutines for insn-output.c for Intel 860
2 Copyright (C) 1989, 1991 Free Software Foundation, Inc.
5 Written by Richard Stallman (rms@ai.mit.edu).
7 Hacked substantially by Ron Guilmette (rfg@netcom.com) to cater
8 to the whims of the System V Release 4 assembler.
10 This file is part of GNU CC.
12 GNU CC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GNU CC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GNU CC; see the file COPYING. If not, write to
24 the Free Software Foundation, 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
39 #include "insn-attr.h"
43 static rtx find_addr_reg ();
45 #ifndef I860_REG_PREFIX
46 #define I860_REG_PREFIX ""
49 char *i860_reg_prefix = I860_REG_PREFIX;
51 /* Save information from a "cmpxx" operation until the branch is emitted. */
53 rtx i860_compare_op0, i860_compare_op1;
55 /* Return non-zero if this pattern, can be evaluated safely, even if it
58 safe_insn_src_p (op, mode)
60 enum machine_mode mode;
62 /* Just experimenting. */
64 /* No floating point src is safe if it contains an arithmetic
65 operation, since that operation may trap. */
66 switch (GET_CODE (op))
78 return CONSTANT_ADDRESS_P (XEXP (op, 0));
80 /* We never need to negate or complement constants. */
82 return (mode != SFmode && mode != DFmode);
99 return (mode != SFmode && mode != DFmode);
106 if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
107 || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
116 /* Return 1 if REG is clobbered in IN.
117 Return 2 if REG is used in IN.
118 Return 3 if REG is both used and clobbered in IN.
119 Return 0 if neither. */
122 reg_clobbered_p (reg, in)
126 register enum rtx_code code;
131 code = GET_CODE (in);
133 if (code == SET || code == CLOBBER)
135 rtx dest = SET_DEST (in);
139 while (GET_CODE (dest) == STRICT_LOW_PART
140 || GET_CODE (dest) == SUBREG
141 || GET_CODE (dest) == SIGN_EXTRACT
142 || GET_CODE (dest) == ZERO_EXTRACT)
143 dest = XEXP (dest, 0);
147 else if (GET_CODE (dest) == REG
148 && refers_to_regno_p (REGNO (reg),
149 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
153 /* Anything that sets just part of the register
154 is considered using as well as setting it.
155 But note that a straight SUBREG of a single-word value
156 clobbers the entire value. */
157 if (dest != SET_DEST (in)
158 && ! (GET_CODE (SET_DEST (in)) == SUBREG
159 || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
166 used = refers_to_regno_p (REGNO (reg),
167 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
170 used = refers_to_regno_p (REGNO (reg),
171 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
175 return set + used * 2;
178 if (refers_to_regno_p (REGNO (reg),
179 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
185 /* Return non-zero if OP can be written to without screwing up
186 GCC's model of what's going on. It is assumed that this operand
187 appears in the dest position of a SET insn in a conditional
188 branch's delay slot. AFTER is the label to start looking from. */
190 operand_clobbered_before_used_after (op, after)
194 /* Just experimenting. */
195 if (GET_CODE (op) == CC0)
197 if (GET_CODE (op) == REG)
201 if (op == stack_pointer_rtx)
204 /* Scan forward from the label, to see if the value of OP
205 is clobbered before the first use. */
207 for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
209 if (GET_CODE (insn) == NOTE)
211 if (GET_CODE (insn) == INSN
212 || GET_CODE (insn) == JUMP_INSN
213 || GET_CODE (insn) == CALL_INSN)
215 switch (reg_clobbered_p (op, PATTERN (insn)))
225 /* If we reach another label without clobbering OP,
226 then we cannot safely write it here. */
227 else if (GET_CODE (insn) == CODE_LABEL)
229 if (GET_CODE (insn) == JUMP_INSN)
231 if (condjump_p (insn))
233 /* This is a jump insn which has already
234 been mangled. We can't tell what it does. */
235 if (GET_CODE (PATTERN (insn)) == PARALLEL)
237 if (! JUMP_LABEL (insn))
239 /* Keep following jumps. */
240 insn = JUMP_LABEL (insn);
246 /* In both of these cases, the first insn executed
247 for this op will be a orh whatever%h,%?r0,%?r31,
248 which is tolerable. */
249 if (GET_CODE (op) == MEM)
250 return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
255 /* Return non-zero if this pattern, as a source to a "SET",
256 is known to yield an instruction of unit size. */
258 single_insn_src_p (op, mode)
260 enum machine_mode mode;
262 switch (GET_CODE (op))
265 /* This is not always a single insn src, technically,
266 but output_delayed_branch knows how to deal with it. */
271 /* This is not a single insn src, technically,
272 but output_delayed_branch knows how to deal with it. */
281 /* We never need to negate or complement constants. */
283 return (mode != DFmode);
290 /* Detect cases that require multiple instructions. */
291 if (CONSTANT_P (XEXP (op, 1))
292 && !(GET_CODE (XEXP (op, 1)) == CONST_INT
293 && SMALL_INT (XEXP (op, 1))))
305 /* Not doing floating point, since they probably
306 take longer than the branch slot they might fill. */
307 return (mode != SFmode && mode != DFmode);
310 if (GET_CODE (XEXP (op, 1)) == NOT)
312 rtx arg = XEXP (XEXP (op, 1), 0);
314 && !(GET_CODE (arg) == CONST_INT
316 || INTVAL (arg) & 0xffff == 0)))
321 /* Both small and round numbers take one instruction;
323 if (CONSTANT_P (XEXP (op, 1))
324 && !(GET_CODE (XEXP (op, 1)) == CONST_INT
325 && (SMALL_INT (XEXP (op, 1))
326 || INTVAL (XEXP (op, 1)) & 0xffff == 0)))
335 if (SUBREG_WORD (op) != 0)
337 return single_insn_src_p (SUBREG_REG (op), mode);
339 /* Not doing floating point, since they probably
340 take longer than the branch slot they might fill. */
354 /* Return non-zero only if OP is a register of mode MODE,
357 reg_or_0_operand (op, mode)
359 enum machine_mode mode;
361 return (op == const0_rtx || register_operand (op, mode)
362 || op == CONST0_RTX (mode));
365 /* Return truth value of whether OP can be used as an operands in a three
366 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
369 arith_operand (op, mode)
371 enum machine_mode mode;
373 return (register_operand (op, mode)
374 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
377 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
380 logic_operand (op, mode)
382 enum machine_mode mode;
384 return (register_operand (op, mode)
385 || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
388 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
391 shift_operand (op, mode)
393 enum machine_mode mode;
395 return (register_operand (op, mode)
396 || (GET_CODE (op) == CONST_INT));
399 /* Return 1 if OP is a valid first operand for either a logical insn
400 or an add insn of mode MODE. */
403 compare_operand (op, mode)
405 enum machine_mode mode;
407 return (register_operand (op, mode)
408 || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
411 /* Return truth value of whether OP can be used as the 5-bit immediate
412 operand of a bte or btne insn. */
415 bte_operand (op, mode)
417 enum machine_mode mode;
419 return (register_operand (op, mode)
420 || (GET_CODE (op) == CONST_INT
421 && (unsigned) INTVAL (op) < 0x20));
424 /* Return 1 if OP is an indexed memory reference of mode MODE. */
427 indexed_operand (op, mode)
429 enum machine_mode mode;
431 return (GET_CODE (op) == MEM && GET_MODE (op) == mode
432 && GET_CODE (XEXP (op, 0)) == PLUS
433 && GET_MODE (XEXP (op, 0)) == SImode
434 && register_operand (XEXP (XEXP (op, 0), 0), SImode)
435 && register_operand (XEXP (XEXP (op, 0), 1), SImode));
438 /* Return 1 if OP is a suitable source operand for a load insn
442 load_operand (op, mode)
444 enum machine_mode mode;
446 return (memory_operand (op, mode) || indexed_operand (op, mode));
449 /* Return truth value of whether OP is a integer which fits the
450 range constraining immediate operands in add/subtract insns. */
455 enum machine_mode mode;
457 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
460 /* Return truth value of whether OP is a integer which fits the
461 range constraining immediate operands in logic insns. */
466 enum machine_mode mode;
468 return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
471 /* Test for a valid operand for a call instruction.
472 Don't allow the arg pointer register or virtual regs
473 since they may change into reg + const, which the patterns
477 call_insn_operand (op, mode)
479 enum machine_mode mode;
481 if (GET_CODE (op) == MEM
482 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
483 || (GET_CODE (XEXP (op, 0)) == REG
484 && XEXP (op, 0) != arg_pointer_rtx
485 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
486 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
491 /* Return the best assembler insn template
492 for moving operands[1] into operands[0] as a fullword. */
495 singlemove_string (operands)
498 if (GET_CODE (operands[0]) == MEM)
500 if (GET_CODE (operands[1]) != MEM)
501 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
503 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
504 && (cc_prev_status.flags & CC_HI_R31_ADJ)
505 && cc_prev_status.mdep == XEXP (operands[0], 0)))
508 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
510 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
511 cc_status.mdep = XEXP (operands[0], 0);
512 return "st.l %r1,%L0(%?r31)";
515 return "st.l %r1,%0";
522 cc_status.flags &= ~CC_F0_IS_0;
523 xoperands[0] = gen_rtx (REG, SFmode, 32);
524 xoperands[1] = operands[1];
525 output_asm_insn (singlemove_string (xoperands), xoperands);
526 xoperands[1] = xoperands[0];
527 xoperands[0] = operands[0];
528 output_asm_insn (singlemove_string (xoperands), xoperands);
533 if (GET_CODE (operands[1]) == MEM)
535 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
537 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
538 && (cc_prev_status.flags & CC_HI_R31_ADJ)
539 && cc_prev_status.mdep == XEXP (operands[1], 0)))
542 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
544 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
545 cc_status.mdep = XEXP (operands[1], 0);
546 return "ld.l %L1(%?r31),%0";
548 return "ld.l %m1,%0";
550 if (GET_CODE (operands[1]) == CONST_INT)
552 if (operands[1] == const0_rtx)
553 return "mov %?r0,%0";
554 if((INTVAL (operands[1]) & 0xffff0000) == 0)
555 return "or %L1,%?r0,%0";
556 if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
557 return "adds %1,%?r0,%0";
558 if((INTVAL (operands[1]) & 0x0000ffff) == 0)
559 return "orh %H1,%?r0,%0";
564 /* Output assembler code to perform a doubleword move insn
565 with operands OPERANDS. */
568 output_move_double (operands)
571 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
573 rtx addreg0 = 0, addreg1 = 0;
574 int highest_first = 0;
575 int no_addreg1_decrement = 0;
577 /* First classify both operands. */
579 if (REG_P (operands[0]))
581 else if (offsettable_memref_p (operands[0]))
583 else if (GET_CODE (operands[0]) == MEM)
588 if (REG_P (operands[1]))
590 else if (CONSTANT_P (operands[1]))
592 else if (offsettable_memref_p (operands[1]))
594 else if (GET_CODE (operands[1]) == MEM)
599 /* Check for the cases that the operand constraints are not
600 supposed to allow to happen. Abort if we get one,
601 because generating code for these cases is painful. */
603 if (optype0 == RNDOP || optype1 == RNDOP)
606 /* If an operand is an unoffsettable memory ref, find a register
607 we can increment temporarily to make it refer to the second word. */
609 if (optype0 == MEMOP)
610 addreg0 = find_addr_reg (XEXP (operands[0], 0));
612 if (optype1 == MEMOP)
613 addreg1 = find_addr_reg (XEXP (operands[1], 0));
615 /* ??? Perhaps in some cases move double words
616 if there is a spare pair of floating regs. */
618 /* Ok, we can do one word at a time.
619 Normally we do the low-numbered word first,
620 but if either operand is autodecrementing then we
621 do the high-numbered word first.
623 In either case, set up in LATEHALF the operands to use
624 for the high-numbered word and in some cases alter the
625 operands in OPERANDS to be suitable for the low-numbered word. */
627 if (optype0 == REGOP)
628 latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
629 else if (optype0 == OFFSOP)
630 latehalf[0] = adj_offsettable_operand (operands[0], 4);
632 latehalf[0] = operands[0];
634 if (optype1 == REGOP)
635 latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
636 else if (optype1 == OFFSOP)
637 latehalf[1] = adj_offsettable_operand (operands[1], 4);
638 else if (optype1 == CNSTOP)
640 if (GET_CODE (operands[1]) == CONST_DOUBLE)
641 split_double (operands[1], &operands[1], &latehalf[1]);
642 else if (CONSTANT_P (operands[1]))
643 latehalf[1] = const0_rtx;
646 latehalf[1] = operands[1];
648 /* If the first move would clobber the source of the second one,
649 do them in the other order.
651 RMS says "This happens only for registers;
652 such overlap can't happen in memory unless the user explicitly
653 sets it up, and that is an undefined circumstance."
655 but it happens on the sparc when loading parameter registers,
656 so I am going to define that circumstance, and make it work
659 if (optype0 == REGOP && optype1 == REGOP
660 && REGNO (operands[0]) == REGNO (latehalf[1]))
662 CC_STATUS_PARTIAL_INIT;
663 /* Make any unoffsettable addresses point at high-numbered word. */
665 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
667 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
670 output_asm_insn (singlemove_string (latehalf), latehalf);
672 /* Undo the adds we just did. */
674 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
676 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
678 /* Do low-numbered word. */
679 return singlemove_string (operands);
681 else if (optype0 == REGOP && optype1 != REGOP
682 && reg_overlap_mentioned_p (operands[0], operands[1]))
684 /* If both halves of dest are used in the src memory address,
685 add the two regs and put them in the low reg (operands[0]).
686 Then it works to load latehalf first. */
687 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
688 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
691 xops[0] = latehalf[0];
692 xops[1] = operands[0];
693 output_asm_insn ("adds %1,%0,%1", xops);
694 operands[1] = gen_rtx (MEM, DImode, operands[0]);
695 latehalf[1] = adj_offsettable_operand (operands[1], 4);
699 /* Only one register in the dest is used in the src memory address,
700 and this is the first register of the dest, so we want to do
701 the late half first here also. */
702 else if (! reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
704 /* Only one register in the dest is used in the src memory address,
705 and this is the second register of the dest, so we want to do
706 the late half last. If addreg1 is set, and addreg1 is the same
707 register as latehalf, then we must suppress the trailing decrement,
708 because it would clobber the value just loaded. */
709 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
710 no_addreg1_decrement = 1;
713 /* Normal case: do the two words, low-numbered first.
714 Overlap case (highest_first set): do high-numbered word first. */
717 output_asm_insn (singlemove_string (operands), operands);
719 CC_STATUS_PARTIAL_INIT;
720 /* Make any unoffsettable addresses point at high-numbered word. */
722 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
724 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
727 output_asm_insn (singlemove_string (latehalf), latehalf);
729 /* Undo the adds we just did. */
731 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
732 if (addreg1 && !no_addreg1_decrement)
733 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
736 output_asm_insn (singlemove_string (operands), operands);
742 output_fp_move_double (operands)
745 /* If the source operand is any sort of zero, use f0 instead. */
747 if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
748 operands[1] = gen_rtx (REG, DFmode, F0_REGNUM);
750 if (FP_REG_P (operands[0]))
752 if (FP_REG_P (operands[1]))
753 return "fmov.dd %1,%0";
754 if (GET_CODE (operands[1]) == REG)
756 output_asm_insn ("ixfr %1,%0", operands);
757 operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
758 operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
761 if (operands[1] == CONST0_RTX (DFmode))
762 return "fmov.dd f0,%0";
763 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
765 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
766 && (cc_prev_status.flags & CC_HI_R31_ADJ)
767 && cc_prev_status.mdep == XEXP (operands[1], 0)))
770 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
772 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
773 cc_status.mdep = XEXP (operands[1], 0);
774 return "fld.d %L1(%?r31),%0";
776 return "fld.d %1,%0";
778 else if (FP_REG_P (operands[1]))
780 if (GET_CODE (operands[0]) == REG)
782 output_asm_insn ("fxfr %1,%0", operands);
783 operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
784 operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
787 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
789 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
790 && (cc_prev_status.flags & CC_HI_R31_ADJ)
791 && cc_prev_status.mdep == XEXP (operands[0], 0)))
794 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
796 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
797 cc_status.mdep = XEXP (operands[0], 0);
798 return "fst.d %1,%L0(%?r31)";
800 return "fst.d %1,%0";
808 /* Return a REG that occurs in ADDR with coefficient 1.
809 ADDR can be effectively incremented by incrementing REG. */
815 while (GET_CODE (addr) == PLUS)
817 if (GET_CODE (XEXP (addr, 0)) == REG)
818 addr = XEXP (addr, 0);
819 else if (GET_CODE (XEXP (addr, 1)) == REG)
820 addr = XEXP (addr, 1);
821 else if (CONSTANT_P (XEXP (addr, 0)))
822 addr = XEXP (addr, 1);
823 else if (CONSTANT_P (XEXP (addr, 1)))
824 addr = XEXP (addr, 0);
828 if (GET_CODE (addr) == REG)
835 /* Return a template for a load instruction with mode MODE and
836 arguments from the string ARGS.
838 This string is in static storage. */
841 load_opcode (mode, args, reg)
842 enum machine_mode mode;
878 sprintf (buf, "%s %s", opcode, args);
882 /* Return a template for a store instruction with mode MODE and
883 arguments from the string ARGS.
885 This string is in static storage. */
888 store_opcode (mode, args, reg)
889 enum machine_mode mode;
925 sprintf (buf, "%s %s", opcode, args);
929 /* Output a store-in-memory whose operands are OPERANDS[0,1].
930 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
932 This function returns a template for an insn.
933 This is in static storage.
935 It may also output some insns directly.
936 It may alter the values of operands[0] and operands[1]. */
939 output_store (operands)
942 enum machine_mode mode = GET_MODE (operands[0]);
943 rtx address = XEXP (operands[0], 0);
946 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
947 cc_status.mdep = address;
949 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
950 && (cc_prev_status.flags & CC_HI_R31_ADJ)
951 && address == cc_prev_status.mdep))
954 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
955 cc_prev_status.mdep = address;
958 /* Store zero in two parts when appropriate. */
959 if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
960 return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
962 /* Code below isn't smart enough to move a doubleword in two parts,
963 so use output_move_double to do that in the cases that require it. */
964 if ((mode == DImode || mode == DFmode)
965 && ! FP_REG_P (operands[1]))
966 return output_move_double (operands);
968 return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
971 /* Output a load-from-memory whose operands are OPERANDS[0,1].
972 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
974 This function returns a template for an insn.
975 This is in static storage.
977 It may also output some insns directly.
978 It may alter the values of operands[0] and operands[1]. */
981 output_load (operands)
984 enum machine_mode mode = GET_MODE (operands[0]);
985 rtx address = XEXP (operands[1], 0);
987 /* We don't bother trying to see if we know %hi(address).
988 This is because we are doing a load, and if we know the
989 %hi value, we probably also know that value in memory. */
990 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
991 cc_status.mdep = address;
993 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
994 && (cc_prev_status.flags & CC_HI_R31_ADJ)
995 && address == cc_prev_status.mdep
996 && cc_prev_status.mdep == cc_status.mdep))
999 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
1000 cc_prev_status.mdep = address;
1003 /* Code below isn't smart enough to move a doubleword in two parts,
1004 so use output_move_double to do that in the cases that require it. */
1005 if ((mode == DImode || mode == DFmode)
1006 && ! FP_REG_P (operands[0]))
1007 return output_move_double (operands);
1009 return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
1013 /* Load the address specified by OPERANDS[3] into the register
1014 specified by OPERANDS[0].
1016 OPERANDS[3] may be the result of a sum, hence it could either be:
1021 (3) REG + REG + CONST_INT
1022 (4) REG + REG (special case of 3).
1024 Note that (3) is not a legitimate address.
1025 All cases are handled here. */
1028 output_load_address (operands)
1033 if (CONSTANT_P (operands[3]))
1035 output_asm_insn ("mov %3,%0", operands);
1039 if (REG_P (operands[3]))
1041 if (REGNO (operands[0]) != REGNO (operands[3]))
1042 output_asm_insn ("shl %?r0,%3,%0", operands);
1046 if (GET_CODE (operands[3]) != PLUS)
1049 base = XEXP (operands[3], 0);
1050 offset = XEXP (operands[3], 1);
1052 if (GET_CODE (base) == CONST_INT)
1059 if (GET_CODE (offset) != CONST_INT)
1061 /* Operand is (PLUS (REG) (REG)). */
1063 offset = const0_rtx;
1069 operands[7] = offset;
1070 CC_STATUS_PARTIAL_INIT;
1071 if (SMALL_INT (offset))
1072 output_asm_insn ("adds %7,%6,%0", operands);
1074 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
1076 else if (GET_CODE (base) == PLUS)
1078 operands[6] = XEXP (base, 0);
1079 operands[7] = XEXP (base, 1);
1080 operands[8] = offset;
1082 CC_STATUS_PARTIAL_INIT;
1083 if (SMALL_INT (offset))
1084 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
1086 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
1093 /* Output code to place a size count SIZE in register REG.
1094 Because block moves are pipelined, we don't include the
1095 first element in the transfer of SIZE to REG.
1096 For this, we subtract ALIGN. (Actually, I think it is not
1097 right to subtract on this machine, so right now we don't.) */
1100 output_size_for_block_move (size, reg, align)
1101 rtx size, reg, align;
1106 xoperands[1] = size;
1107 xoperands[2] = align;
1110 cc_status.flags &= ~ CC_KNOW_HI_R31;
1111 output_asm_insn (singlemove_string (xoperands), xoperands);
1113 if (GET_CODE (size) == REG)
1114 output_asm_insn ("sub %2,%1,%0", xoperands);
1118 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
1119 cc_status.flags &= ~ CC_KNOW_HI_R31;
1120 output_asm_insn ("mov %1,%0", xoperands);
1125 /* Emit code to perform a block move.
1127 OPERANDS[0] is the destination.
1128 OPERANDS[1] is the source.
1129 OPERANDS[2] is the size.
1130 OPERANDS[3] is the known safe alignment.
1131 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1134 output_block_move (operands)
1137 /* A vector for our computed operands. Note that load_output_address
1138 makes use of (and can clobber) up to the 8th element of this vector. */
1141 static int movstrsi_label = 0;
1143 rtx temp1 = operands[4];
1144 rtx alignrtx = operands[3];
1145 int align = INTVAL (alignrtx);
1148 xoperands[0] = operands[0];
1149 xoperands[1] = operands[1];
1150 xoperands[2] = temp1;
1152 /* We can't move more than four bytes at a time
1153 because we have only one register to move them through. */
1157 alignrtx = gen_rtx (CONST_INT, VOIDmode, 4);
1160 /* Recognize special cases of block moves. These occur
1161 when GNU C++ is forced to treat something as BLKmode
1162 to keep it in memory, when its mode could be represented
1163 with something smaller.
1165 We cannot do this for global variables, since we don't know
1166 what pages they don't cross. Sigh. */
1167 if (GET_CODE (operands[2]) == CONST_INT
1168 && ! CONSTANT_ADDRESS_P (operands[0])
1169 && ! CONSTANT_ADDRESS_P (operands[1]))
1171 int size = INTVAL (operands[2]);
1172 rtx op0 = xoperands[0];
1173 rtx op1 = xoperands[1];
1175 if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
1177 if (memory_address_p (SImode, plus_constant (op0, size))
1178 && memory_address_p (SImode, plus_constant (op1, size)))
1180 cc_status.flags &= ~CC_KNOW_HI_R31;
1181 for (i = (size>>2)-1; i >= 0; i--)
1183 xoperands[0] = plus_constant (op0, i * 4);
1184 xoperands[1] = plus_constant (op1, i * 4);
1185 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1191 else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
1193 if (memory_address_p (HImode, plus_constant (op0, size))
1194 && memory_address_p (HImode, plus_constant (op1, size)))
1196 cc_status.flags &= ~CC_KNOW_HI_R31;
1197 for (i = (size>>1)-1; i >= 0; i--)
1199 xoperands[0] = plus_constant (op0, i * 2);
1200 xoperands[1] = plus_constant (op1, i * 2);
1201 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1207 else if (size <= 16)
1209 if (memory_address_p (QImode, plus_constant (op0, size))
1210 && memory_address_p (QImode, plus_constant (op1, size)))
1212 cc_status.flags &= ~CC_KNOW_HI_R31;
1213 for (i = size-1; i >= 0; i--)
1215 xoperands[0] = plus_constant (op0, i);
1216 xoperands[1] = plus_constant (op1, i);
1217 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1225 /* Since we clobber untold things, nix the condition codes. */
1228 /* This is the size of the transfer.
1229 Either use the register which already contains the size,
1230 or use a free register (used by no operands). */
1231 output_size_for_block_move (operands[2], operands[4], alignrtx);
1234 /* Also emit code to decrement the size value by ALIGN. */
1235 zoperands[0] = operands[0];
1236 zoperands[3] = plus_constant (operands[0], align);
1237 output_load_address (zoperands);
1240 /* Generate number for unique label. */
1242 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1244 /* Calculate the size of the chunks we will be trying to move first. */
1247 if ((align & 3) == 0)
1249 else if ((align & 1) == 0)
1255 /* Copy the increment (negative) to a register for bla insn. */
1257 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, - chunk_size);
1258 xoperands[5] = operands[5];
1259 output_asm_insn ("adds %4,%?r0,%5", xoperands);
1261 /* Predecrement the loop counter. This happens again also in the `bla'
1262 instruction which precedes the loop, but we need to have it done
1263 two times before we enter the loop because of the bizarre semantics
1264 of the bla instruction. */
1266 output_asm_insn ("adds %5,%2,%2", xoperands);
1268 /* Check for the case where the original count was less than or equal to
1269 zero. Avoid going through the loop at all if the original count was
1270 indeed less than or equal to zero. Note that we treat the count as
1271 if it were a signed 32-bit quantity here, rather than an unsigned one,
1272 even though we really shouldn't. We have to do this because of the
1273 semantics of the `ble' instruction, which assume that the count is
1274 a signed 32-bit value. Anyway, in practice it won't matter because
1275 nobody is going to try to do a memcpy() of more than half of the
1276 entire address space (i.e. 2 gigabytes) anyway. */
1278 output_asm_insn ("bc .Le%3", xoperands);
1280 /* Make available a register which is a temporary. */
1282 xoperands[6] = operands[6];
1284 /* Now the actual loop.
1285 In xoperands, elements 1 and 0 are the input and output vectors.
1286 Element 2 is the loop index. Element 5 is the increment. */
1288 output_asm_insn ("subs %1,%5,%1", xoperands);
1289 output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
1290 output_asm_insn ("adds %0,%2,%6", xoperands);
1291 output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */
1292 output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */
1293 output_asm_insn ("adds %5,%6,%6", xoperands);
1295 /* NOTE: The code here which is supposed to handle the cases where the
1296 sources and destinations are known to start on a 4 or 2 byte boundary
1297 are currently broken. They fail to do anything about the overflow
1298 bytes which might still need to be copied even after we have copied
1299 some number of words or halfwords. Thus, for now we use the lowest
1300 common denominator, i.e. the code which just copies some number of
1301 totally unaligned individual bytes. (See the calculation of
1302 chunk_size above. */
1304 if (chunk_size == 4)
1306 output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
1307 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1308 output_asm_insn ("st.l %?r31,8(%6)", xoperands);
1310 else if (chunk_size == 2)
1312 output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
1313 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1314 output_asm_insn ("st.s %?r31,4(%6)", xoperands);
1316 else /* chunk_size == 1 */
1318 output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
1319 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1320 output_asm_insn ("st.b %?r31,2(%6)", xoperands);
1322 output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */
1327 /* Output a delayed branch insn with the delay insn in its
1328 branch slot. The delayed branch insn template is in TEMPLATE,
1329 with operands OPERANDS. The insn in its delay slot is INSN.
1331 As a special case, since we know that all memory transfers are via
1332 ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1333 reference around the branch as
1337 ld/st l%x(%?r31),...
1339 As another special case, we handle loading (SYMBOL_REF ...) and
1340 other large constants around branches as well:
1349 output_delayed_branch (template, operands, insn)
1354 rtx src = XVECEXP (PATTERN (insn), 0, 1);
1355 rtx dest = XVECEXP (PATTERN (insn), 0, 0);
1357 /* See if we are doing some branch together with setting some register
1358 to some 32-bit value which does (or may) have some of the high-order
1359 16 bits set. If so, we need to set the register in two stages. One
1360 stage must be done before the branch, and the other one can be done
1361 in the delay slot. */
1363 if ( (GET_CODE (src) == CONST_INT
1364 && ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0)
1365 || (GET_CODE (src) == SYMBOL_REF)
1366 || (GET_CODE (src) == LABEL_REF)
1367 || (GET_CODE (src) == CONST))
1370 xoperands[0] = dest;
1373 CC_STATUS_PARTIAL_INIT;
1374 /* Output the `orh' insn. */
1375 output_asm_insn ("orh %H1,%?r0,%0", xoperands);
1377 /* Output the branch instruction next. */
1378 output_asm_insn (template, operands);
1380 /* Now output the `or' insn. */
1381 output_asm_insn ("or %L1,%0,%0", xoperands);
1383 else if ((GET_CODE (src) == MEM
1384 && CONSTANT_ADDRESS_P (XEXP (src, 0)))
1385 || (GET_CODE (dest) == MEM
1386 && CONSTANT_ADDRESS_P (XEXP (dest, 0))))
1389 char *split_template;
1390 xoperands[0] = dest;
1393 /* Output the `orh' insn. */
1394 if (GET_CODE (src) == MEM)
1396 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1397 && (cc_prev_status.flags & CC_HI_R31_ADJ)
1398 && cc_prev_status.mdep == XEXP (operands[1], 0)))
1401 output_asm_insn ("orh %h1,%?r0,%?r31", xoperands);
1403 split_template = load_opcode (GET_MODE (dest),
1404 "%L1(%?r31),%0", dest);
1408 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1409 && (cc_prev_status.flags & CC_HI_R31_ADJ)
1410 && cc_prev_status.mdep == XEXP (operands[0], 0)))
1413 output_asm_insn ("orh %h0,%?r0,%?r31", xoperands);
1415 split_template = store_opcode (GET_MODE (dest),
1416 "%r1,%L0(%?r31)", src);
1419 /* Output the branch instruction next. */
1420 output_asm_insn (template, operands);
1422 /* Now output the load or store.
1423 No need to do a CC_STATUS_INIT, because we are branching anyway. */
1424 output_asm_insn (split_template, xoperands);
1428 int insn_code_number;
1429 rtx pat = gen_rtx (SET, VOIDmode, dest, src);
1430 rtx delay_insn = gen_rtx (INSN, VOIDmode, 0, 0, 0, pat, -1, 0, 0);
1433 /* Output the branch instruction first. */
1434 output_asm_insn (template, operands);
1436 /* Now recognize the insn which we put in its delay slot.
1437 We must do this after outputting the branch insn,
1438 since operands may just be a pointer to `recog_operand'. */
1439 INSN_CODE (delay_insn) = insn_code_number = recog (pat, delay_insn);
1440 if (insn_code_number == -1)
1443 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1445 if (GET_CODE (recog_operand[i]) == SUBREG)
1446 recog_operand[i] = alter_subreg (recog_operand[i]);
1449 insn_extract (delay_insn);
1450 if (! constrain_operands (insn_code_number, 1))
1451 fatal_insn_not_found (delay_insn);
1453 template = insn_template[insn_code_number];
1455 template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1456 output_asm_insn (template, recog_operand);
1462 /* Output a newly constructed insn DELAY_INSN. */
1464 output_delay_insn (delay_insn)
1468 int insn_code_number;
1471 /* Now recognize the insn which we put in its delay slot.
1472 We must do this after outputting the branch insn,
1473 since operands may just be a pointer to `recog_operand'. */
1474 insn_code_number = recog_memoized (delay_insn);
1475 if (insn_code_number == -1)
1478 /* Extract the operands of this delay insn. */
1479 INSN_CODE (delay_insn) = insn_code_number;
1480 insn_extract (delay_insn);
1482 /* It is possible that this insn has not been properly scanned by final
1483 yet. If this insn's operands don't appear in the peephole's
1484 actual operands, then they won't be fixed up by final, so we
1485 make sure they get fixed up here. -- This is a kludge. */
1486 for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1488 if (GET_CODE (recog_operand[i]) == SUBREG)
1489 recog_operand[i] = alter_subreg (recog_operand[i]);
1492 #ifdef REGISTER_CONSTRAINTS
1493 if (! constrain_operands (insn_code_number))
1497 cc_prev_status = cc_status;
1499 /* Update `cc_status' for this instruction.
1500 The instruction's output routine may change it further.
1501 If the output routine for a jump insn needs to depend
1502 on the cc status, it should look at cc_prev_status. */
1504 NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn);
1506 /* Now get the template for what this insn would
1507 have been, without the branch. */
1509 template = insn_template[insn_code_number];
1511 template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1512 output_asm_insn (template, recog_operand);
1516 /* Special routine to convert an SFmode value represented as a
1517 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1518 We convert the value from a double precision floating-point
1519 value to single precision first, and thence to a bit-wise
1520 equivalent unsigned long value. This routine is used when
1521 generating an immediate move of an SFmode value directly
1522 into a general register because the svr4 assembler doesn't
1523 grok floating literals in instruction operand contexts. */
1526 sfmode_constant_to_ulong (x)
1530 union { float f; unsigned long i; } u2;
1532 if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
1535 #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1536 error IEEE emulation needed
1538 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1543 /* This function generates the assembly code for function entry.
1544 The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1546 ASM_FILE is a stdio stream to output the code to.
1547 SIZE is an int: how many units of temporary storage to allocate.
1549 Refer to the array `regs_ever_live' to determine which registers
1550 to save; `regs_ever_live[I]' is nonzero if register number I
1551 is ever used in the function. This macro is responsible for
1552 knowing which registers should not be saved even if used.
1554 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1555 between the new `fp' value and the new `sp' value after the
1556 prologue is done. `frame_upper_bytes' is the count of bytes
1557 that will lie between the new `fp' and the *old* `sp' value
1558 after the new `fp' is setup (in the prologue). The upper
1559 part of each frame always includes at least 2 words (8 bytes)
1560 to hold the saved frame pointer and the saved return address.
1562 The svr4 ABI for the i860 now requires that the values of the
1563 stack pointer and frame pointer registers be kept aligned to
1564 16-byte boundaries at all times. We obey that restriction here.
1566 The svr4 ABI for the i860 is entirely vague when it comes to specifying
1567 exactly where the "preserved" registers should be saved. The native
1568 svr4 C compiler I now have doesn't help to clarify the requirements
1569 very much because it is plainly out-of-date and non-ABI-compliant
1570 (in at least one important way, i.e. how it generates function
1573 The native svr4 C compiler saves the "preserved" registers (i.e.
1574 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1575 offsets from the frame pointer).
1577 Previous versions of GCC also saved the "preserved" registers in the
1578 "negative" part of the frame, but they saved them using positive
1579 offsets from the (adjusted) stack pointer (after it had been adjusted
1580 to allocate space for the new frame). That's just plain wrong
1581 because if the current function calls alloca(), the stack pointer
1582 will get moved, and it will be impossible to restore the registers
1583 properly again after that.
1585 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1586 by copying their values either into various "preserved" registers or
1587 into stack slots in the lower part of the current frame (as seemed
1588 appropriate, depending upon subsequent usage of these values).
1590 Here we want to save the preserved registers at some offset from the
1591 frame pointer register so as to avoid any possible problems arising
1592 from calls to alloca(). We can either save them at small positive
1593 offsets from the frame pointer, or at small negative offsets from
1594 the frame pointer. If we save them at small negative offsets from
1595 the frame pointer (i.e. in the lower part of the frame) then we
1596 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1597 many bytes of space we plan to use in the lower part of the frame
1598 for this purpose. Since other parts of the compiler reference the
1599 value of STARTING_FRAME_OFFSET long before final() calls this function,
1600 we would have to go ahead and assume the worst-case storage requirements
1601 for saving all of the "preserved" registers (and use that number, i.e.
1602 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1603 the lower part of the frame. That could potentially be very wasteful,
1604 and that wastefulness could really hamper people compiling for embedded
1605 i860 targets with very tight limits on stack space. Thus, we choose
1606 here to save the preserved registers in the upper part of the
1607 frame, so that we can decide at the very last minute how much (or how
1608 little) space we must allocate for this purpose.
1610 To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1611 registers must always be saved so that the saved values of registers
1612 with higher numbers are at higher addresses. We obey that restriction
1615 There are two somewhat different ways that you can generate prologues
1616 here... i.e. pedantically ABI-compliant, and the "other" way. The
1617 "other" way is more consistent with what is currently generated by the
1618 "native" svr4 C compiler for the i860. That's important if you want
1619 to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1620 The SVR4 SDB for the i860 insists on having function prologues be
1623 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1624 in the i860svr4.h file. (By default this is *not* defined).
1626 The differences between the ABI-compliant and non-ABI-compliant prologues
1627 are that (a) the ABI version seems to require the use of *signed*
1628 (rather than unsigned) adds and subtracts, and (b) the ordering of
1629 the various steps (e.g. saving preserved registers, saving the
1630 return address, setting up the new frame pointer value) is different.
1632 For strict ABI compliance, it seems to be the case that the very last
1633 thing that is supposed to happen in the prologue is getting the frame
1634 pointer set to its new value (but only after everything else has
1635 already been properly setup). We do that here, but only if the symbol
1636 I860_STRICT_ABI_PROLOGUES is defined.
1639 #ifndef STACK_ALIGNMENT
1640 #define STACK_ALIGNMENT 16
1643 extern char call_used_regs[];
1644 extern int leaf_function_p ();
1646 char *current_function_original_name;
1648 static int must_preserve_r1;
1649 static unsigned must_preserve_bytes;
1652 function_prologue (asm_file, local_bytes)
1653 register FILE *asm_file;
1654 register unsigned local_bytes;
1656 register unsigned frame_lower_bytes;
1657 register unsigned frame_upper_bytes;
1658 register unsigned total_fsize;
1659 register unsigned preserved_reg_bytes = 0;
1660 register unsigned i;
1661 register unsigned preserved_so_far = 0;
1663 must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
1664 must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
1666 /* Count registers that need preserving. Ignore r0. It never needs
1669 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1671 if (regs_ever_live[i] && ! call_used_regs[i])
1672 preserved_reg_bytes += 4;
1675 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1677 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1679 /* The upper part of each frame will contain the saved fp,
1680 the saved r1, and stack slots for all of the other "preserved"
1681 registers that we find we will need to save & restore. */
1683 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1685 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1688 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1690 total_fsize = frame_upper_bytes + frame_lower_bytes;
1692 #ifndef I860_STRICT_ABI_PROLOGUES
1694 /* There are two kinds of function prologues.
1695 You use the "small" version if the total frame size is
1696 small enough so that it can fit into an immediate 16-bit
1697 value in one instruction. Otherwise, you use the "large"
1698 version of the function prologue. */
1700 if (total_fsize > 0x7fff)
1702 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1703 but the native C compiler on svr4 uses `addu'. */
1705 fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1706 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1708 /* Save the old frame pointer. */
1710 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1711 i860_reg_prefix, i860_reg_prefix);
1713 /* Setup the new frame pointer. The ABI sez to do this after
1714 preserving registers (using adds), but that's not what the
1715 native C compiler on svr4 does. */
1717 fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
1718 i860_reg_prefix, i860_reg_prefix);
1720 /* Get the value of frame_lower_bytes into r31. */
1722 fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1723 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1724 fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1725 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1727 /* Now re-adjust the stack pointer using the value in r31.
1728 The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1730 fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
1731 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1733 /* Preserve registers. The ABI sez to do this before setting
1734 up the new frame pointer, but that's not what the native
1735 C compiler on svr4 does. */
1737 for (i = 1; i < 32; i++)
1738 if (regs_ever_live[i] && ! call_used_regs[i])
1739 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1740 i860_reg_prefix, reg_names[i],
1741 must_preserve_bytes + (4 * preserved_so_far++),
1744 for (i = 32; i < 64; i++)
1745 if (regs_ever_live[i] && ! call_used_regs[i])
1746 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1747 i860_reg_prefix, reg_names[i],
1748 must_preserve_bytes + (4 * preserved_so_far++),
1751 /* Save the return address. */
1753 if (must_preserve_r1)
1754 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1755 i860_reg_prefix, i860_reg_prefix);
1759 /* Adjust the stack pointer. The ABI sez to do this using `adds',
1760 but the native C compiler on svr4 uses `addu'. */
1762 fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1763 total_fsize, i860_reg_prefix, i860_reg_prefix);
1765 /* Save the old frame pointer. */
1767 fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1768 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1770 /* Setup the new frame pointer. The ABI sez to do this after
1771 preserving registers and after saving the return address,
1772 (and its saz to do this using adds), but that's not what the
1773 native C compiler on svr4 does. */
1775 fprintf (asm_file, "\taddu %d,%ssp,%sfp\n",
1776 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1778 /* Preserve registers. The ABI sez to do this before setting
1779 up the new frame pointer, but that's not what the native
1780 compiler on svr4 does. */
1782 for (i = 1; i < 32; i++)
1783 if (regs_ever_live[i] && ! call_used_regs[i])
1784 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1785 i860_reg_prefix, reg_names[i],
1786 must_preserve_bytes + (4 * preserved_so_far++),
1789 for (i = 32; i < 64; i++)
1790 if (regs_ever_live[i] && ! call_used_regs[i])
1791 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1792 i860_reg_prefix, reg_names[i],
1793 must_preserve_bytes + (4 * preserved_so_far++),
1796 /* Save the return address. The ABI sez to do this earlier,
1797 and also via an offset from %sp, but the native C compiler
1798 on svr4 does it later (i.e. now) and uses an offset from
1801 if (must_preserve_r1)
1802 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1803 i860_reg_prefix, i860_reg_prefix);
1806 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1808 /* There are two kinds of function prologues.
1809 You use the "small" version if the total frame size is
1810 small enough so that it can fit into an immediate 16-bit
1811 value in one instruction. Otherwise, you use the "large"
1812 version of the function prologue. */
1814 if (total_fsize > 0x7fff)
1816 /* Adjust the stack pointer (thereby allocating a new frame). */
1818 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1819 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1821 /* Save the caller's frame pointer. */
1823 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1824 i860_reg_prefix, i860_reg_prefix);
1826 /* Save return address. */
1828 if (must_preserve_r1)
1829 fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
1830 i860_reg_prefix, i860_reg_prefix);
1832 /* Get the value of frame_lower_bytes into r31 for later use. */
1834 fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1835 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1836 fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1837 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1839 /* Now re-adjust the stack pointer using the value in r31. */
1841 fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
1842 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1844 /* Pre-compute value to be used as the new frame pointer. */
1846 fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
1847 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1849 /* Preserve registers. */
1851 for (i = 1; i < 32; i++)
1852 if (regs_ever_live[i] && ! call_used_regs[i])
1853 fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
1854 i860_reg_prefix, reg_names[i],
1855 must_preserve_bytes + (4 * preserved_so_far++),
1858 for (i = 32; i < 64; i++)
1859 if (regs_ever_live[i] && ! call_used_regs[i])
1860 fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
1861 i860_reg_prefix, reg_names[i],
1862 must_preserve_bytes + (4 * preserved_so_far++),
1865 /* Actually set the new value of the frame pointer. */
1867 fprintf (asm_file, "\tmov %sr31,%sfp\n",
1868 i860_reg_prefix, i860_reg_prefix);
1872 /* Adjust the stack pointer. */
1874 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1875 total_fsize, i860_reg_prefix, i860_reg_prefix);
1877 /* Save the caller's frame pointer. */
1879 fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1880 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1882 /* Save the return address. */
1884 if (must_preserve_r1)
1885 fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
1886 i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
1888 /* Preserve registers. */
1890 for (i = 1; i < 32; i++)
1891 if (regs_ever_live[i] && ! call_used_regs[i])
1892 fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
1893 i860_reg_prefix, reg_names[i],
1894 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1897 for (i = 32; i < 64; i++)
1898 if (regs_ever_live[i] && ! call_used_regs[i])
1899 fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
1900 i860_reg_prefix, reg_names[i],
1901 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1904 /* Setup the new frame pointer. */
1906 fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
1907 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1909 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1911 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1912 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
1913 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1916 /* This function generates the assembly code for function exit.
1917 The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1919 ASM_FILE is a stdio stream to output the code to.
1920 SIZE is an int: how many units of temporary storage to allocate.
1922 The function epilogue should not depend on the current stack pointer!
1923 It should use the frame pointer only. This is mandatory because
1924 of alloca; we also take advantage of it to omit stack adjustments
1927 Note that when we go to restore the preserved register values we must
1928 not try to address their slots by using offsets from the stack pointer.
1929 That's because the stack pointer may have been moved during the function
1930 execution due to a call to alloca(). Rather, we must restore all
1931 preserved registers via offsets from the frame pointer value.
1933 Note also that when the current frame is being "popped" (by adjusting
1934 the value of the stack pointer) on function exit, we must (for the
1935 sake of alloca) set the new value of the stack pointer based upon
1936 the current value of the frame pointer. We can't just add what we
1937 believe to be the (static) frame size to the stack pointer because
1938 if we did that, and alloca() had been called during this function,
1939 we would end up returning *without* having fully deallocated all of
1940 the space grabbed by alloca. If that happened, and a function
1941 containing one or more alloca() calls was called over and over again,
1942 then the stack would grow without limit!
1944 Finally note that the epilogues generated here are completely ABI
1945 compliant. They go out of their way to insure that the value in
1946 the frame pointer register is never less than the value in the stack
1947 pointer register. It's not clear why this relationship needs to be
1948 maintained at all times, but maintaining it only costs one extra
1949 instruction, so what the hell.
1952 /* This corresponds to a version 4 TDESC structure. Lower numbered
1953 versions successively omit the last word of the structure. We
1954 don't try to handle version 5 here. */
1956 typedef struct TDESC_flags {
1959 int callable_block:1;
1961 int fregs:6; /* fp regs 2-7 */
1962 int iregs:16; /* regs 0-15 */
1965 typedef struct TDESC {
1967 int integer_reg_offset; /* same as must_preserve_bytes */
1968 int floating_point_reg_offset;
1969 unsigned int positive_frame_size; /* same as frame_upper_bytes */
1970 unsigned int negative_frame_size; /* same as frame_lower_bytes */
1974 function_epilogue (asm_file, local_bytes)
1975 register FILE *asm_file;
1976 register unsigned local_bytes;
1978 register unsigned frame_upper_bytes;
1979 register unsigned frame_lower_bytes;
1980 register unsigned preserved_reg_bytes = 0;
1981 register unsigned i;
1982 register unsigned restored_so_far = 0;
1983 register unsigned int_restored;
1984 register unsigned mask;
1985 unsigned intflags=0;
1986 register TDESC_flags *flags = (TDESC_flags *) &intflags;
1989 flags->reg_packing = 1;
1990 flags->iregs = 8; /* old fp always gets saved */
1992 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1994 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1996 /* Count the number of registers that were preserved in the prologue.
1997 Ignore r0. It is never preserved. */
1999 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
2001 if (regs_ever_live[i] && ! call_used_regs[i])
2002 preserved_reg_bytes += 4;
2005 /* The upper part of each frame will contain only saved fp,
2006 the saved r1, and stack slots for all of the other "preserved"
2007 registers that we find we will need to save & restore. */
2009 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
2011 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
2014 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
2016 /* Restore all of the "preserved" registers that need restoring. */
2020 for (i = 1; i < 32; i++, mask<<=1)
2021 if (regs_ever_live[i] && ! call_used_regs[i]) {
2022 fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
2023 must_preserve_bytes + (4 * restored_so_far++),
2024 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
2025 if (i > 3 && i < 16)
2026 flags->iregs |= mask;
2029 int_restored = restored_so_far;
2032 for (i = 32; i < 64; i++) {
2033 if (regs_ever_live[i] && ! call_used_regs[i]) {
2034 fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
2035 must_preserve_bytes + (4 * restored_so_far++),
2036 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
2037 if (i > 33 & i < 40)
2038 flags->fregs |= mask;
2040 if (i > 33 && i < 40)
2044 /* Get the value we plan to use to restore the stack pointer into r31. */
2046 fprintf (asm_file, "\tadds %d,%sfp,%sr31\n",
2047 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
2049 /* Restore the return address and the old frame pointer. */
2051 if (must_preserve_r1) {
2052 fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
2053 i860_reg_prefix, i860_reg_prefix);
2057 fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
2058 i860_reg_prefix, i860_reg_prefix);
2060 /* Return and restore the old stack pointer value. */
2062 fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2063 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
2065 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
2066 if (! frame_lower_bytes) {
2068 if (! frame_upper_bytes) {
2070 if (restored_so_far == int_restored) /* No FP saves */
2074 assemble_name(asm_file,current_function_original_name);
2075 fputs(".TDESC:\n", asm_file);
2076 fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags);
2077 fprintf(asm_file, "%s %d\n", ASM_LONG,
2078 int_restored ? must_preserve_bytes : 0);
2079 if (flags->version > 1) {
2080 fprintf(asm_file, "%s %d\n", ASM_LONG,
2081 (restored_so_far == int_restored) ? 0 : must_preserve_bytes +
2082 (4 * int_restored));
2083 if (flags->version > 2) {
2084 fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes);
2085 if (flags->version > 3)
2086 fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes);
2090 fprintf(asm_file, "%s ", ASM_LONG);
2091 assemble_name(asm_file, current_function_original_name);
2092 fprintf(asm_file, "\n%s ", ASM_LONG);
2093 assemble_name(asm_file, current_function_original_name);
2094 fputs(".TDESC\n", asm_file);