gcc/config/i386/sync.md

   1 ;; GCC machine description for i386 synchronization instructions.
   2 ;; Copyright (C) 2005, 2006
   3 ;; Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
  20 ;; Boston, MA 02110-1301, USA.
  21
  22 (define_mode_macro IMODE [QI HI SI (DI "TARGET_64BIT")])
  23 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
  24 (define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
  25 (define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
  26
  27 (define_mode_macro CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
  28                            (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
  29 (define_mode_macro DCASMODE
  30   [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
  31    (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
  32 (define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
  33 (define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
  34
  35 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
  36 ;; changes.  It's complicated because the insn uses ecx:ebx as the
  37 ;; new value; note that the registers are reversed from the order
  38 ;; that they'd be in with (reg:DI 2 ecx).  Similarly for TImode
  39 ;; data in 64-bit mode.
  40
  41 (define_expand "sync_compare_and_swap<mode>"
  42   [(parallel
  43     [(set (match_operand:CASMODE 0 "register_operand" "")
  44           (match_operand:CASMODE 1 "memory_operand" ""))
  45      (set (match_dup 1)
  46           (unspec_volatile:CASMODE
  47             [(match_dup 1)
  48              (match_operand:CASMODE 2 "register_operand" "")
  49              (match_operand:CASMODE 3 "register_operand" "")]
  50             UNSPECV_CMPXCHG_1))
  51      (clobber (reg:CC FLAGS_REG))])]
  52   "TARGET_CMPXCHG"
  53 {
  54   if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
  55     {
  56       enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
  57       rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
  58       rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
  59                                       GET_MODE_SIZE (hmode));
  60       low = force_reg (hmode, low);
  61       high = force_reg (hmode, high);
  62       if (<MODE>mode == DImode)
  63         emit_insn (gen_sync_double_compare_and_swapdi
  64                    (operands[0], operands[1], operands[2], low, high));
  65       else if (<MODE>mode == TImode)
  66         emit_insn (gen_sync_double_compare_and_swapti
  67                    (operands[0], operands[1], operands[2], low, high));
  68       else
  69         gcc_unreachable ();
  70       DONE;
  71     }
  72 })
  73
  74 (define_insn "*sync_compare_and_swap<mode>"
  75   [(set (match_operand:IMODE 0 "register_operand" "=a")
  76         (match_operand:IMODE 1 "memory_operand" "+m"))
  77    (set (match_dup 1)
  78         (unspec_volatile:IMODE
  79           [(match_dup 1)
  80            (match_operand:IMODE 2 "register_operand" "a")
  81            (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
  82           UNSPECV_CMPXCHG_1))
  83    (clobber (reg:CC FLAGS_REG))]
  84   "TARGET_CMPXCHG"
  85   "lock{\;| }cmpxchg{<modesuffix>\t%3, %1| %1, %3}")
  86
  87 (define_insn "sync_double_compare_and_swap<mode>"
  88   [(set (match_operand:DCASMODE 0 "register_operand" "=A")
  89         (match_operand:DCASMODE 1 "memory_operand" "+m"))
  90    (set (match_dup 1)
  91         (unspec_volatile:DCASMODE
  92           [(match_dup 1)
  93            (match_operand:DCASMODE 2 "register_operand" "A")
  94            (match_operand:<DCASHMODE> 3 "register_operand" "b")
  95            (match_operand:<DCASHMODE> 4 "register_operand" "c")]
  96           UNSPECV_CMPXCHG_1))
  97    (clobber (reg:CC FLAGS_REG))]
  98   ""
  99   "lock{\;| }cmpxchg<doublemodesuffix>b{\t| }%1")
 100
 101 (define_insn "*sync_double_compare_and_swapdi_pic"
 102   [(set (match_operand:DI 0 "register_operand" "=A")
 103         (match_operand:DI 1 "memory_operand" "+m"))
 104    (set (match_dup 1)
 105         (unspec_volatile:DI
 106           [(match_dup 1)
 107            (match_operand:DI 2 "register_operand" "A")
 108            (match_operand:SI 3 "register_operand" "r")
 109            (match_operand:SI 4 "register_operand" "c")]
 110           UNSPECV_CMPXCHG_1))
 111    (clobber (reg:CC FLAGS_REG))]
 112   "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
 113   "xchg{l}\t%%ebx, %3\;lock{\;| }cmpxchg8b{\t| }%1\;xchg{l}\t%%ebx, %3")
 114
 115 (define_expand "sync_compare_and_swap_cc<mode>"
 116   [(parallel
 117     [(set (match_operand:CASMODE 0 "register_operand" "")
 118           (match_operand:CASMODE 1 "memory_operand" ""))
 119      (set (match_dup 1)
 120           (unspec_volatile:CASMODE
 121             [(match_dup 1)
 122              (match_operand:CASMODE 2 "register_operand" "")
 123              (match_operand:CASMODE 3 "register_operand" "")]
 124             UNSPECV_CMPXCHG_1))
 125      (set (match_dup 4)
 126           (compare:CCZ
 127             (unspec_volatile:CASMODE
 128               [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
 129             (match_dup 2)))])]
 130   "TARGET_CMPXCHG"
 131 {
 132   operands[4] = gen_rtx_REG (CCZmode, FLAGS_REG);
 133   ix86_compare_op0 = operands[3];
 134   ix86_compare_op1 = NULL;
 135   ix86_compare_emitted = operands[4];
 136   if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
 137     {
 138       enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
 139       rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
 140       rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
 141                                       GET_MODE_SIZE (hmode));
 142       low = force_reg (hmode, low);
 143       high = force_reg (hmode, high);
 144       if (<MODE>mode == DImode)
 145         emit_insn (gen_sync_double_compare_and_swap_ccdi
 146                    (operands[0], operands[1], operands[2], low, high));
 147       else if (<MODE>mode == TImode)
 148         emit_insn (gen_sync_double_compare_and_swap_ccti
 149                    (operands[0], operands[1], operands[2], low, high));
 150       else
 151         gcc_unreachable ();
 152       DONE;
 153     }
 154 })
 155
 156 (define_insn "*sync_compare_and_swap_cc<mode>"
 157   [(set (match_operand:IMODE 0 "register_operand" "=a")
 158         (match_operand:IMODE 1 "memory_operand" "+m"))
 159    (set (match_dup 1)
 160         (unspec_volatile:IMODE
 161           [(match_dup 1)
 162            (match_operand:IMODE 2 "register_operand" "a")
 163            (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
 164           UNSPECV_CMPXCHG_1))
 165    (set (reg:CCZ FLAGS_REG)
 166         (compare:CCZ
 167           (unspec_volatile:IMODE
 168             [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG_2)
 169           (match_dup 2)))]
 170   "TARGET_CMPXCHG"
 171   "lock{\;| }cmpxchg{<modesuffix>\t%3, %1| %1, %3}")
 172
 173 (define_insn "sync_double_compare_and_swap_cc<mode>"
 174   [(set (match_operand:DCASMODE 0 "register_operand" "=A")
 175         (match_operand:DCASMODE 1 "memory_operand" "+m"))
 176    (set (match_dup 1)
 177         (unspec_volatile:DCASMODE
 178           [(match_dup 1)
 179            (match_operand:DCASMODE 2 "register_operand" "A")
 180            (match_operand:<DCASHMODE> 3 "register_operand" "b")
 181            (match_operand:<DCASHMODE> 4 "register_operand" "c")]
 182           UNSPECV_CMPXCHG_1))
 183    (set (reg:CCZ FLAGS_REG)
 184         (compare:CCZ
 185           (unspec_volatile:DCASMODE
 186             [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
 187             UNSPECV_CMPXCHG_2)
 188           (match_dup 2)))]
 189   ""
 190   "lock{\;| }cmpxchg<doublemodesuffix>b{\t| }%1")
 191
 192 (define_insn "*sync_double_compare_and_swap_ccdi_pic"
 193   [(set (match_operand:DI 0 "register_operand" "=A")
 194         (match_operand:DI 1 "memory_operand" "+m"))
 195    (set (match_dup 1)
 196         (unspec_volatile:DI
 197           [(match_dup 1)
 198            (match_operand:DI 2 "register_operand" "A")
 199            (match_operand:SI 3 "register_operand" "r")
 200            (match_operand:SI 4 "register_operand" "c")]
 201           UNSPECV_CMPXCHG_1))
 202    (set (reg:CCZ FLAGS_REG)
 203         (compare:CCZ
 204           (unspec_volatile:DI
 205             [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
 206             UNSPECV_CMPXCHG_2)
 207           (match_dup 2)))]
 208   "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
 209   "xchg{l}\t%%ebx, %3\;lock{\;| }cmpxchg8b{\t| }%1\;xchg{l}\t%%ebx, %3")
 210
 211 (define_insn "sync_old_add<mode>"
 212   [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
 213         (unspec_volatile:IMODE
 214           [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
 215    (set (match_dup 1)
 216         (plus:IMODE (match_dup 1)
 217                     (match_operand:IMODE 2 "register_operand" "0")))
 218    (clobber (reg:CC FLAGS_REG))]
 219   "TARGET_XADD"
 220   "lock{\;| }xadd{<modesuffix>\t%0, %1| %1, %0}")
 221
 222 ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
 223 (define_insn "sync_lock_test_and_set<mode>"
 224   [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
 225         (unspec_volatile:IMODE
 226           [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
 227    (set (match_dup 1)
 228         (match_operand:IMODE 2 "register_operand" "0"))]
 229   ""
 230   "xchg{<modesuffix>}\t{%1, %0|%0, %1}")
 231
 232 (define_insn "sync_add<mode>"
 233   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 234         (unspec_volatile:IMODE
 235           [(plus:IMODE (match_dup 0)
 236              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 237           UNSPECV_LOCK))
 238    (clobber (reg:CC FLAGS_REG))]
 239   ""
 240 {
 241   if (TARGET_USE_INCDEC)
 242     {
 243       if (operands[1] == const1_rtx)
 244         return "lock{\;| }inc{<modesuffix>\t| }%0";
 245       if (operands[1] == constm1_rtx)
 246         return "lock{\;| }dec{<modesuffix>\t| }%0";
 247     }
 248
 249   return "lock{\;| }add{<modesuffix>\t%1, %0| %0, %1}";
 250 })
 251
 252 (define_insn "sync_sub<mode>"
 253   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 254         (unspec_volatile:IMODE
 255           [(minus:IMODE (match_dup 0)
 256              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 257           UNSPECV_LOCK))
 258    (clobber (reg:CC FLAGS_REG))]
 259   ""
 260 {
 261   if (TARGET_USE_INCDEC)
 262     {
 263       if (operands[1] == const1_rtx)
 264         return "lock{\;| }dec{<modesuffix>\t| }%0";
 265       if (operands[1] == constm1_rtx)
 266         return "lock{\;| }inc{<modesuffix>\t| }%0";
 267     }
 268
 269   return "lock{\;| }sub{<modesuffix>\t%1, %0| %0, %1}";
 270 })
 271
 272 (define_insn "sync_ior<mode>"
 273   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 274         (unspec_volatile:IMODE
 275           [(ior:IMODE (match_dup 0)
 276              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 277           UNSPECV_LOCK))
 278    (clobber (reg:CC FLAGS_REG))]
 279   ""
 280   "lock{\;| }or{<modesuffix>\t%1, %0| %0, %1}")
 281
 282 (define_insn "sync_and<mode>"
 283   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 284         (unspec_volatile:IMODE
 285           [(and:IMODE (match_dup 0)
 286              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 287           UNSPECV_LOCK))
 288    (clobber (reg:CC FLAGS_REG))]
 289   ""
 290   "lock{\;| }and{<modesuffix>\t%1, %0| %0, %1}")
 291
 292 (define_insn "sync_xor<mode>"
 293   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 294         (unspec_volatile:IMODE
 295           [(xor:IMODE (match_dup 0)
 296              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 297           UNSPECV_LOCK))
 298    (clobber (reg:CC FLAGS_REG))]
 299   ""
 300   "lock{\;| }xor{<modesuffix>\t%1, %0| %0, %1}")