gcc/config/i386/sync.md

   1 ;; GCC machine description for i386 synchronization instructions.
   2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009
   3 ;; Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_mode_iterator IMODE [QI HI SI (DI "TARGET_64BIT")])
  22 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
  23 (define_mode_attr modeconstraint [(QI "q") (HI "r") (SI "r") (DI "r")])
  24 (define_mode_attr immconstraint [(QI "i") (HI "i") (SI "i") (DI "e")])
  25
  26 (define_mode_iterator CASMODE [QI HI SI (DI "TARGET_64BIT || TARGET_CMPXCHG8B")
  27                            (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
  28 (define_mode_iterator DCASMODE
  29   [(DI "!TARGET_64BIT && TARGET_CMPXCHG8B && !flag_pic")
  30    (TI "TARGET_64BIT && TARGET_CMPXCHG16B")])
  31 (define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
  32 (define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
  33
  34 (define_expand "memory_barrier"
  35   [(set (match_dup 0)
  36         (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
  37   ""
  38 {
  39   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  40   MEM_VOLATILE_P (operands[0]) = 1;
  41
  42   if (!(TARGET_64BIT || TARGET_SSE2))
  43     {
  44       emit_insn (gen_memory_barrier_nosse (operands[0]));
  45       DONE;
  46     }
  47 })
  48
  49 (define_insn "memory_barrier_nosse"
  50   [(set (match_operand:BLK 0 "" "")
  51         (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
  52    (clobber (reg:CC FLAGS_REG))]
  53   "!(TARGET_64BIT || TARGET_SSE2)"
  54   "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}"
  55   [(set_attr "memory" "unknown")])
  56
  57 ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
  58 ;; changes.  It's complicated because the insn uses ecx:ebx as the
  59 ;; new value; note that the registers are reversed from the order
  60 ;; that they'd be in with (reg:DI 2 ecx).  Similarly for TImode
  61 ;; data in 64-bit mode.
  62
  63 (define_expand "sync_compare_and_swap<mode>"
  64   [(parallel
  65     [(set (match_operand:CASMODE 0 "register_operand" "")
  66           (match_operand:CASMODE 1 "memory_operand" ""))
  67      (set (match_dup 1)
  68           (unspec_volatile:CASMODE
  69             [(match_dup 1)
  70              (match_operand:CASMODE 2 "register_operand" "")
  71              (match_operand:CASMODE 3 "register_operand" "")]
  72             UNSPECV_CMPXCHG))
  73    (set (reg:CCZ FLAGS_REG)
  74         (compare:CCZ
  75           (unspec_volatile:CASMODE
  76             [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
  77           (match_dup 2)))])]
  78   "TARGET_CMPXCHG"
  79 {
  80   if ((<MODE>mode == DImode && !TARGET_64BIT) || <MODE>mode == TImode)
  81     {
  82       enum machine_mode hmode = <MODE>mode == DImode ? SImode : DImode;
  83       rtx low = simplify_gen_subreg (hmode, operands[3], <MODE>mode, 0);
  84       rtx high = simplify_gen_subreg (hmode, operands[3], <MODE>mode,
  85                                       GET_MODE_SIZE (hmode));
  86       low = force_reg (hmode, low);
  87       high = force_reg (hmode, high);
  88       if (<MODE>mode == DImode)
  89         {
  90           if (flag_pic && !cmpxchg8b_pic_memory_operand (operands[1], DImode))
  91             operands[1] = replace_equiv_address (operands[1],
  92                                                  force_reg (Pmode,
  93                                                             XEXP (operands[1],
  94                                                                   0)));
  95           emit_insn (gen_sync_double_compare_and_swapdi
  96                      (operands[0], operands[1], operands[2], low, high));
  97         }
  98       else if (<MODE>mode == TImode)
  99         emit_insn (gen_sync_double_compare_and_swapti
 100                    (operands[0], operands[1], operands[2], low, high));
 101       else
 102         gcc_unreachable ();
 103       DONE;
 104     }
 105 })
 106
 107 (define_insn "*sync_compare_and_swap<mode>"
 108   [(set (match_operand:IMODE 0 "register_operand" "=a")
 109         (match_operand:IMODE 1 "memory_operand" "+m"))
 110    (set (match_dup 1)
 111         (unspec_volatile:IMODE
 112           [(match_dup 1)
 113            (match_operand:IMODE 2 "register_operand" "a")
 114            (match_operand:IMODE 3 "register_operand" "<modeconstraint>")]
 115           UNSPECV_CMPXCHG))
 116    (set (reg:CCZ FLAGS_REG)
 117         (compare:CCZ
 118           (unspec_volatile:IMODE
 119             [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPECV_CMPXCHG)
 120           (match_dup 2)))]
 121   "TARGET_CMPXCHG"
 122   "lock{%;| }cmpxchg{<modesuffix>}\t{%3, %1|%1, %3}")
 123
 124 (define_insn "sync_double_compare_and_swap<mode>"
 125   [(set (match_operand:DCASMODE 0 "register_operand" "=A")
 126         (match_operand:DCASMODE 1 "memory_operand" "+m"))
 127    (set (match_dup 1)
 128         (unspec_volatile:DCASMODE
 129           [(match_dup 1)
 130            (match_operand:DCASMODE 2 "register_operand" "A")
 131            (match_operand:<DCASHMODE> 3 "register_operand" "b")
 132            (match_operand:<DCASHMODE> 4 "register_operand" "c")]
 133           UNSPECV_CMPXCHG))
 134    (set (reg:CCZ FLAGS_REG)
 135         (compare:CCZ
 136           (unspec_volatile:DCASMODE
 137             [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
 138             UNSPECV_CMPXCHG)
 139           (match_dup 2)))]
 140   ""
 141   "lock{%;| }cmpxchg<doublemodesuffix>b\t%1")
 142
 143 ;; Theoretically we'd like to use constraint "r" (any reg) for operand
 144 ;; 3, but that includes ecx.  If operand 3 and 4 are the same (like when
 145 ;; the input is -1LL) GCC might chose to allocate operand 3 to ecx, like
 146 ;; operand 4.  This breaks, as the xchg will move the PIC register contents
 147 ;; to %ecx then --> boom.  Operands 3 and 4 really need to be different
 148 ;; registers, which in this case means operand 3 must not be ecx.
 149 ;; Instead of playing tricks with fake early clobbers or the like we
 150 ;; just enumerate all regs possible here, which (as this is !TARGET_64BIT)
 151 ;; are just esi and edi.
 152 (define_insn "*sync_double_compare_and_swapdi_pic"
 153   [(set (match_operand:DI 0 "register_operand" "=A")
 154         (match_operand:DI 1 "cmpxchg8b_pic_memory_operand" "+m"))
 155    (set (match_dup 1)
 156         (unspec_volatile:DI
 157           [(match_dup 1)
 158            (match_operand:DI 2 "register_operand" "A")
 159            (match_operand:SI 3 "register_operand" "SD")
 160            (match_operand:SI 4 "register_operand" "c")]
 161           UNSPECV_CMPXCHG))
 162    (set (reg:CCZ FLAGS_REG)
 163         (compare:CCZ
 164           (unspec_volatile:DI
 165             [(match_dup 1) (match_dup 2) (match_dup 3) (match_dup 4)]
 166             UNSPECV_CMPXCHG)
 167           (match_dup 2)))]
 168   "!TARGET_64BIT && TARGET_CMPXCHG8B && flag_pic"
 169   "xchg{l}\t%%ebx, %3\;lock{%;| }cmpxchg8b\t%1\;xchg{l}\t%%ebx, %3")
 170
 171 (define_insn "sync_old_add<mode>"
 172   [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
 173         (unspec_volatile:IMODE
 174           [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
 175    (set (match_dup 1)
 176         (plus:IMODE (match_dup 1)
 177                     (match_operand:IMODE 2 "register_operand" "0")))
 178    (clobber (reg:CC FLAGS_REG))]
 179   "TARGET_XADD"
 180   "lock{%;| }xadd{<modesuffix>}\t{%0, %1|%1, %0}")
 181
 182 ;; Recall that xchg implicitly sets LOCK#, so adding it again wastes space.
 183 (define_insn "sync_lock_test_and_set<mode>"
 184   [(set (match_operand:IMODE 0 "register_operand" "=<modeconstraint>")
 185         (unspec_volatile:IMODE
 186           [(match_operand:IMODE 1 "memory_operand" "+m")] UNSPECV_XCHG))
 187    (set (match_dup 1)
 188         (match_operand:IMODE 2 "register_operand" "0"))]
 189   ""
 190   "xchg{<modesuffix>}\t{%1, %0|%0, %1}")
 191
 192 (define_insn "sync_add<mode>"
 193   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 194         (unspec_volatile:IMODE
 195           [(plus:IMODE (match_dup 0)
 196              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 197           UNSPECV_LOCK))
 198    (clobber (reg:CC FLAGS_REG))]
 199   ""
 200 {
 201   if (TARGET_USE_INCDEC)
 202     {
 203       if (operands[1] == const1_rtx)
 204         return "lock{%;| }inc{<modesuffix>}\t%0";
 205       if (operands[1] == constm1_rtx)
 206         return "lock{%;| }dec{<modesuffix>}\t%0";
 207     }
 208
 209   return "lock{%;| }add{<modesuffix>}\t{%1, %0|%0, %1}";
 210 })
 211
 212 (define_insn "sync_sub<mode>"
 213   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 214         (unspec_volatile:IMODE
 215           [(minus:IMODE (match_dup 0)
 216              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 217           UNSPECV_LOCK))
 218    (clobber (reg:CC FLAGS_REG))]
 219   ""
 220 {
 221   if (TARGET_USE_INCDEC)
 222     {
 223       if (operands[1] == const1_rtx)
 224         return "lock{%;| }dec{<modesuffix>}\t%0";
 225       if (operands[1] == constm1_rtx)
 226         return "lock{%;| }inc{<modesuffix>}\t%0";
 227     }
 228
 229   return "lock{%;| }sub{<modesuffix>}\t{%1, %0|%0, %1}";
 230 })
 231
 232 (define_insn "sync_ior<mode>"
 233   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 234         (unspec_volatile:IMODE
 235           [(ior:IMODE (match_dup 0)
 236              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 237           UNSPECV_LOCK))
 238    (clobber (reg:CC FLAGS_REG))]
 239   ""
 240   "lock{%;| }or{<modesuffix>}\t{%1, %0|%0, %1}")
 241
 242 (define_insn "sync_and<mode>"
 243   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 244         (unspec_volatile:IMODE
 245           [(and:IMODE (match_dup 0)
 246              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 247           UNSPECV_LOCK))
 248    (clobber (reg:CC FLAGS_REG))]
 249   ""
 250   "lock{%;| }and{<modesuffix>}\t{%1, %0|%0, %1}")
 251
 252 (define_insn "sync_xor<mode>"
 253   [(set (match_operand:IMODE 0 "memory_operand" "+m")
 254         (unspec_volatile:IMODE
 255           [(xor:IMODE (match_dup 0)
 256              (match_operand:IMODE 1 "nonmemory_operand" "<modeconstraint><immconstraint>"))]
 257           UNSPECV_LOCK))
 258    (clobber (reg:CC FLAGS_REG))]
 259   ""
 260   "lock{%;| }xor{<modesuffix>}\t{%1, %0|%0, %1}")