1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return nonzero if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return nonzero if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return nonzero if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return nonzero if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is a Q_REGS class register.
47 (define_predicate "q_regs_operand"
48 (match_operand 0 "register_operand")
50 if (GET_CODE (op) == SUBREG)
52 return ANY_QI_REG_P (op);
55 ;; Match an SI or HImode register for a zero_extract.
56 (define_special_predicate "ext_register_operand"
57 (match_operand 0 "register_operand")
59 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
60 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
62 if (GET_CODE (op) == SUBREG)
65 /* Be careful to accept only registers having upper parts. */
66 return REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) < 4;
69 ;; Return true if op is the AX register.
70 (define_predicate "ax_reg_operand"
71 (and (match_code "reg")
72 (match_test "REGNO (op) == 0")))
74 ;; Return true if op is the flags register.
75 (define_predicate "flags_reg_operand"
76 (and (match_code "reg")
77 (match_test "REGNO (op) == FLAGS_REG")))
79 ;; Return true if op is a QImode register operand other than
81 (define_predicate "ext_QIreg_operand"
82 (and (match_code "reg")
83 (match_test "TARGET_64BIT
84 && GET_MODE (op) == QImode
85 && REGNO (op) > BX_REG")))
87 ;; Similarly, but don't check mode of the operand.
88 (define_predicate "ext_QIreg_nomode_operand"
89 (and (match_code "reg")
90 (match_test "TARGET_64BIT
91 && REGNO (op) > BX_REG")))
93 ;; Return true if op is not xmm0 register.
94 (define_predicate "reg_not_xmm0_operand"
95 (and (match_operand 0 "register_operand")
96 (match_test "!REG_P (op)
97 || REGNO (op) != FIRST_SSE_REG")))
99 ;; As above, but allow nonimmediate operands.
100 (define_predicate "nonimm_not_xmm0_operand"
101 (and (match_operand 0 "nonimmediate_operand")
102 (match_test "!REG_P (op)
103 || REGNO (op) != FIRST_SSE_REG")))
105 ;; Return 1 if VALUE can be stored in a sign extended immediate field.
106 (define_predicate "x86_64_immediate_operand"
107 (match_code "const_int,symbol_ref,label_ref,const")
110 return immediate_operand (op, mode);
112 switch (GET_CODE (op))
115 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
116 to be at least 32 and this all acceptable constants are
117 represented as CONST_INT. */
118 if (HOST_BITS_PER_WIDE_INT == 32)
122 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
123 return trunc_int_for_mode (val, SImode) == val;
128 /* For certain code models, the symbolic references are known to fit.
129 in CM_SMALL_PIC model we know it fits if it is local to the shared
130 library. Don't count TLS SYMBOL_REFs here, since they should fit
131 only if inside of UNSPEC handled below. */
132 /* TLS symbols are not constant. */
133 if (SYMBOL_REF_TLS_MODEL (op))
135 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
136 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
139 /* For certain code models, the code is near as well. */
140 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
141 || ix86_cmodel == CM_KERNEL);
144 /* We also may accept the offsetted memory references in certain
146 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
147 switch (XINT (XEXP (op, 0), 1))
149 case UNSPEC_GOTPCREL:
151 case UNSPEC_GOTNTPOFF:
158 if (GET_CODE (XEXP (op, 0)) == PLUS)
160 rtx op1 = XEXP (XEXP (op, 0), 0);
161 rtx op2 = XEXP (XEXP (op, 0), 1);
162 HOST_WIDE_INT offset;
164 if (ix86_cmodel == CM_LARGE)
166 if (!CONST_INT_P (op2))
168 offset = trunc_int_for_mode (INTVAL (op2), DImode);
169 switch (GET_CODE (op1))
172 /* TLS symbols are not constant. */
173 if (SYMBOL_REF_TLS_MODEL (op1))
175 /* For CM_SMALL assume that latest object is 16MB before
176 end of 31bits boundary. We may also accept pretty
177 large negative constants knowing that all objects are
178 in the positive half of address space. */
179 if ((ix86_cmodel == CM_SMALL
180 || (ix86_cmodel == CM_MEDIUM
181 && !SYMBOL_REF_FAR_ADDR_P (op1)))
182 && offset < 16*1024*1024
183 && trunc_int_for_mode (offset, SImode) == offset)
185 /* For CM_KERNEL we know that all object resist in the
186 negative half of 32bits address space. We may not
187 accept negative offsets, since they may be just off
188 and we may accept pretty large positive ones. */
189 if (ix86_cmodel == CM_KERNEL
191 && trunc_int_for_mode (offset, SImode) == offset)
196 /* These conditions are similar to SYMBOL_REF ones, just the
197 constraints for code models differ. */
198 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
199 && offset < 16*1024*1024
200 && trunc_int_for_mode (offset, SImode) == offset)
202 if (ix86_cmodel == CM_KERNEL
204 && trunc_int_for_mode (offset, SImode) == offset)
209 switch (XINT (op1, 1))
214 && trunc_int_for_mode (offset, SImode) == offset)
232 ;; Return 1 if VALUE can be stored in the zero extended immediate field.
233 (define_predicate "x86_64_zext_immediate_operand"
234 (match_code "const_double,const_int,symbol_ref,label_ref,const")
236 switch (GET_CODE (op))
239 if (HOST_BITS_PER_WIDE_INT == 32)
240 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
245 if (HOST_BITS_PER_WIDE_INT == 32)
246 return INTVAL (op) >= 0;
248 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
251 /* For certain code models, the symbolic references are known to fit. */
252 /* TLS symbols are not constant. */
253 if (SYMBOL_REF_TLS_MODEL (op))
255 return (ix86_cmodel == CM_SMALL
256 || (ix86_cmodel == CM_MEDIUM
257 && !SYMBOL_REF_FAR_ADDR_P (op)));
260 /* For certain code models, the code is near as well. */
261 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
264 /* We also may accept the offsetted memory references in certain
266 if (GET_CODE (XEXP (op, 0)) == PLUS)
268 rtx op1 = XEXP (XEXP (op, 0), 0);
269 rtx op2 = XEXP (XEXP (op, 0), 1);
271 if (ix86_cmodel == CM_LARGE)
273 switch (GET_CODE (op1))
276 /* TLS symbols are not constant. */
277 if (SYMBOL_REF_TLS_MODEL (op1))
279 /* For small code model we may accept pretty large positive
280 offsets, since one bit is available for free. Negative
281 offsets are limited by the size of NULL pointer area
282 specified by the ABI. */
283 if ((ix86_cmodel == CM_SMALL
284 || (ix86_cmodel == CM_MEDIUM
285 && !SYMBOL_REF_FAR_ADDR_P (op1)))
287 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
288 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
290 /* ??? For the kernel, we may accept adjustment of
291 -0x10000000, since we know that it will just convert
292 negative address space to positive, but perhaps this
293 is not worthwhile. */
297 /* These conditions are similar to SYMBOL_REF ones, just the
298 constraints for code models differ. */
299 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
301 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
302 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
318 ;; Return nonzero if OP is general operand representable on x86_64.
319 (define_predicate "x86_64_general_operand"
320 (if_then_else (match_test "TARGET_64BIT")
321 (ior (match_operand 0 "nonimmediate_operand")
322 (match_operand 0 "x86_64_immediate_operand"))
323 (match_operand 0 "general_operand")))
325 ;; Return nonzero if OP is general operand representable on x86_64
326 ;; as either sign extended or zero extended constant.
327 (define_predicate "x86_64_szext_general_operand"
328 (if_then_else (match_test "TARGET_64BIT")
329 (ior (match_operand 0 "nonimmediate_operand")
330 (match_operand 0 "x86_64_immediate_operand")
331 (match_operand 0 "x86_64_zext_immediate_operand"))
332 (match_operand 0 "general_operand")))
334 ;; Return nonzero if OP is nonmemory operand representable on x86_64.
335 (define_predicate "x86_64_nonmemory_operand"
336 (if_then_else (match_test "TARGET_64BIT")
337 (ior (match_operand 0 "register_operand")
338 (match_operand 0 "x86_64_immediate_operand"))
339 (match_operand 0 "nonmemory_operand")))
341 ;; Return nonzero if OP is nonmemory operand representable on x86_64.
342 (define_predicate "x86_64_szext_nonmemory_operand"
343 (if_then_else (match_test "TARGET_64BIT")
344 (ior (match_operand 0 "register_operand")
345 (match_operand 0 "x86_64_immediate_operand")
346 (match_operand 0 "x86_64_zext_immediate_operand"))
347 (match_operand 0 "nonmemory_operand")))
349 ;; Return true when operand is PIC expression that can be computed by lea
351 (define_predicate "pic_32bit_operand"
352 (match_code "const,symbol_ref,label_ref")
356 /* Rule out relocations that translate into 64bit constants. */
357 if (TARGET_64BIT && GET_CODE (op) == CONST)
360 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
362 if (GET_CODE (op) == UNSPEC
363 && (XINT (op, 1) == UNSPEC_GOTOFF
364 || XINT (op, 1) == UNSPEC_GOT))
367 return symbolic_operand (op, mode);
371 ;; Return nonzero if OP is nonmemory operand acceptable by movabs patterns.
372 (define_predicate "x86_64_movabs_operand"
373 (if_then_else (match_test "!TARGET_64BIT || !flag_pic")
374 (match_operand 0 "nonmemory_operand")
375 (ior (match_operand 0 "register_operand")
376 (and (match_operand 0 "const_double_operand")
377 (match_test "GET_MODE_SIZE (mode) <= 8")))))
379 ;; Returns nonzero if OP is either a symbol reference or a sum of a symbol
380 ;; reference and a constant.
381 (define_predicate "symbolic_operand"
382 (match_code "symbol_ref,label_ref,const")
384 switch (GET_CODE (op))
392 if (GET_CODE (op) == SYMBOL_REF
393 || GET_CODE (op) == LABEL_REF
394 || (GET_CODE (op) == UNSPEC
395 && (XINT (op, 1) == UNSPEC_GOT
396 || XINT (op, 1) == UNSPEC_GOTOFF
397 || XINT (op, 1) == UNSPEC_GOTPCREL)))
399 if (GET_CODE (op) != PLUS
400 || !CONST_INT_P (XEXP (op, 1)))
404 if (GET_CODE (op) == SYMBOL_REF
405 || GET_CODE (op) == LABEL_REF)
407 /* Only @GOTOFF gets offsets. */
408 if (GET_CODE (op) != UNSPEC
409 || XINT (op, 1) != UNSPEC_GOTOFF)
412 op = XVECEXP (op, 0, 0);
413 if (GET_CODE (op) == SYMBOL_REF
414 || GET_CODE (op) == LABEL_REF)
423 ;; Return true if OP is a symbolic operand that resolves locally.
424 (define_predicate "local_symbolic_operand"
425 (match_code "const,label_ref,symbol_ref")
427 if (GET_CODE (op) == CONST
428 && GET_CODE (XEXP (op, 0)) == PLUS
429 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
430 op = XEXP (XEXP (op, 0), 0);
432 if (GET_CODE (op) == LABEL_REF)
435 if (GET_CODE (op) != SYMBOL_REF)
438 if (SYMBOL_REF_TLS_MODEL (op) != 0)
441 if (SYMBOL_REF_LOCAL_P (op))
444 /* There is, however, a not insubstantial body of code in the rest of
445 the compiler that assumes it can just stick the results of
446 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
447 /* ??? This is a hack. Should update the body of the compiler to
448 always create a DECL an invoke targetm.encode_section_info. */
449 if (strncmp (XSTR (op, 0), internal_label_prefix,
450 internal_label_prefix_len) == 0)
456 ;; Test for a legitimate @GOTOFF operand.
458 ;; VxWorks does not impose a fixed gap between segments; the run-time
459 ;; gap can be different from the object-file gap. We therefore can't
460 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
461 ;; same segment as the GOT. Unfortunately, the flexibility of linker
462 ;; scripts means that we can't be sure of that in general, so assume
463 ;; that @GOTOFF is never valid on VxWorks.
464 (define_predicate "gotoff_operand"
465 (and (match_test "!TARGET_VXWORKS_RTP")
466 (match_operand 0 "local_symbolic_operand")))
468 ;; Test for various thread-local symbols.
469 (define_predicate "tls_symbolic_operand"
470 (and (match_code "symbol_ref")
471 (match_test "SYMBOL_REF_TLS_MODEL (op) != 0")))
473 (define_predicate "tls_modbase_operand"
474 (and (match_code "symbol_ref")
475 (match_test "op == ix86_tls_module_base ()")))
477 (define_predicate "tp_or_register_operand"
478 (ior (match_operand 0 "register_operand")
479 (and (match_code "unspec")
480 (match_test "XINT (op, 1) == UNSPEC_TP"))))
482 ;; Test for a pc-relative call operand
483 (define_predicate "constant_call_address_operand"
484 (match_code "symbol_ref")
486 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
488 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
493 ;; True for any non-virtual or eliminable register. Used in places where
494 ;; instantiation of such a register may cause the pattern to not be recognized.
495 (define_predicate "register_no_elim_operand"
496 (match_operand 0 "register_operand")
498 if (GET_CODE (op) == SUBREG)
499 op = SUBREG_REG (op);
500 return !(op == arg_pointer_rtx
501 || op == frame_pointer_rtx
502 || IN_RANGE (REGNO (op),
503 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
506 ;; P6 processors will jump to the address after the decrement when %esp
507 ;; is used as a call operand, so they will execute return address as a code.
508 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
510 (define_predicate "call_register_no_elim_operand"
511 (match_operand 0 "register_operand")
513 if (GET_CODE (op) == SUBREG)
514 op = SUBREG_REG (op);
516 if (!TARGET_64BIT && op == stack_pointer_rtx)
519 return register_no_elim_operand (op, mode);
522 ;; Similarly, but include the stack pointer. This is used to prevent esp
523 ;; from being used as an index reg.
524 (define_predicate "index_register_operand"
525 (match_operand 0 "register_operand")
527 if (GET_CODE (op) == SUBREG)
528 op = SUBREG_REG (op);
529 if (reload_in_progress || reload_completed)
530 return REG_OK_FOR_INDEX_STRICT_P (op);
532 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
535 ;; Return false if this is any eliminable register. Otherwise general_operand.
536 (define_predicate "general_no_elim_operand"
537 (if_then_else (match_code "reg,subreg")
538 (match_operand 0 "register_no_elim_operand")
539 (match_operand 0 "general_operand")))
541 ;; Return false if this is any eliminable register. Otherwise
542 ;; register_operand or a constant.
543 (define_predicate "nonmemory_no_elim_operand"
544 (ior (match_operand 0 "register_no_elim_operand")
545 (match_operand 0 "immediate_operand")))
547 ;; Test for a valid operand for a call instruction.
548 (define_predicate "call_insn_operand"
549 (ior (match_operand 0 "constant_call_address_operand")
550 (match_operand 0 "call_register_no_elim_operand")
551 (match_operand 0 "memory_operand")))
553 ;; Similarly, but for tail calls, in which we cannot allow memory references.
554 (define_predicate "sibcall_insn_operand"
555 (ior (match_operand 0 "constant_call_address_operand")
556 (match_operand 0 "register_no_elim_operand")))
558 ;; Match exactly zero.
559 (define_predicate "const0_operand"
560 (match_code "const_int,const_double,const_vector")
562 if (mode == VOIDmode)
563 mode = GET_MODE (op);
564 return op == CONST0_RTX (mode);
567 ;; Match exactly one.
568 (define_predicate "const1_operand"
569 (and (match_code "const_int")
570 (match_test "op == const1_rtx")))
572 ;; Match exactly eight.
573 (define_predicate "const8_operand"
574 (and (match_code "const_int")
575 (match_test "INTVAL (op) == 8")))
577 ;; Match exactly 128.
578 (define_predicate "const128_operand"
579 (and (match_code "const_int")
580 (match_test "INTVAL (op) == 128")))
582 ;; Match 2, 4, or 8. Used for leal multiplicands.
583 (define_predicate "const248_operand"
584 (match_code "const_int")
586 HOST_WIDE_INT i = INTVAL (op);
587 return i == 2 || i == 4 || i == 8;
591 (define_predicate "const_0_to_1_operand"
592 (and (match_code "const_int")
593 (match_test "op == const0_rtx || op == const1_rtx")))
596 (define_predicate "const_0_to_3_operand"
597 (and (match_code "const_int")
598 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
601 (define_predicate "const_0_to_7_operand"
602 (and (match_code "const_int")
603 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
606 (define_predicate "const_0_to_15_operand"
607 (and (match_code "const_int")
608 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
611 (define_predicate "const_0_to_31_operand"
612 (and (match_code "const_int")
613 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
616 (define_predicate "const_0_to_63_operand"
617 (and (match_code "const_int")
618 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
621 (define_predicate "const_0_to_255_operand"
622 (and (match_code "const_int")
623 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
625 ;; Match (0 to 255) * 8
626 (define_predicate "const_0_to_255_mul_8_operand"
627 (match_code "const_int")
629 unsigned HOST_WIDE_INT val = INTVAL (op);
630 return val <= 255*8 && val % 8 == 0;
633 ;; Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
634 ;; for shift & compare patterns, as shifting by 0 does not change flags).
635 (define_predicate "const_1_to_31_operand"
636 (and (match_code "const_int")
637 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
639 ;; Return nonzero if OP is CONST_INT >= 1 and <= 63 (a valid operand
640 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
641 (define_predicate "const_1_to_63_operand"
642 (and (match_code "const_int")
643 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
646 (define_predicate "const_2_to_3_operand"
647 (and (match_code "const_int")
648 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
651 (define_predicate "const_4_to_5_operand"
652 (and (match_code "const_int")
653 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
656 (define_predicate "const_4_to_7_operand"
657 (and (match_code "const_int")
658 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
661 (define_predicate "const_6_to_7_operand"
662 (and (match_code "const_int")
663 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
666 (define_predicate "const_8_to_11_operand"
667 (and (match_code "const_int")
668 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
671 (define_predicate "const_12_to_15_operand"
672 (and (match_code "const_int")
673 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
675 ;; Match exactly one bit in 2-bit mask.
676 (define_predicate "const_pow2_1_to_2_operand"
677 (and (match_code "const_int")
678 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2")))
680 ;; Match exactly one bit in 4-bit mask.
681 (define_predicate "const_pow2_1_to_8_operand"
682 (match_code "const_int")
684 unsigned int log = exact_log2 (INTVAL (op));
688 ;; Match exactly one bit in 8-bit mask.
689 (define_predicate "const_pow2_1_to_128_operand"
690 (match_code "const_int")
692 unsigned int log = exact_log2 (INTVAL (op));
696 ;; Match exactly one bit in 16-bit mask.
697 (define_predicate "const_pow2_1_to_32768_operand"
698 (match_code "const_int")
700 unsigned int log = exact_log2 (INTVAL (op));
704 ;; True if this is a constant appropriate for an increment or decrement.
705 (define_predicate "incdec_operand"
706 (match_code "const_int")
708 /* On Pentium4, the inc and dec operations causes extra dependency on flag
709 registers, since carry flag is not set. */
710 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
712 return op == const1_rtx || op == constm1_rtx;
715 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
716 (define_predicate "reg_or_pm1_operand"
717 (ior (match_operand 0 "register_operand")
718 (and (match_code "const_int")
719 (match_test "op == const1_rtx || op == constm1_rtx"))))
721 ;; True if OP is acceptable as operand of DImode shift expander.
722 (define_predicate "shiftdi_operand"
723 (if_then_else (match_test "TARGET_64BIT")
724 (match_operand 0 "nonimmediate_operand")
725 (match_operand 0 "register_operand")))
727 (define_predicate "ashldi_input_operand"
728 (if_then_else (match_test "TARGET_64BIT")
729 (match_operand 0 "nonimmediate_operand")
730 (match_operand 0 "reg_or_pm1_operand")))
732 ;; Return true if OP is a vector load from the constant pool with just
733 ;; the first element nonzero.
734 (define_predicate "zero_extended_scalar_load_operand"
738 op = maybe_get_pool_constant (op);
740 if (!(op && GET_CODE (op) == CONST_VECTOR))
743 n_elts = CONST_VECTOR_NUNITS (op);
745 for (n_elts--; n_elts > 0; n_elts--)
747 rtx elt = CONST_VECTOR_ELT (op, n_elts);
748 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
754 /* Return true if operand is a vector constant that is all ones. */
755 (define_predicate "vector_all_ones_operand"
756 (match_code "const_vector")
758 int nunits = GET_MODE_NUNITS (mode);
760 if (GET_CODE (op) == CONST_VECTOR
761 && CONST_VECTOR_NUNITS (op) == nunits)
764 for (i = 0; i < nunits; ++i)
766 rtx x = CONST_VECTOR_ELT (op, i);
767 if (x != constm1_rtx)
776 ; Return 1 when OP is operand acceptable for standard SSE move.
777 (define_predicate "vector_move_operand"
778 (ior (match_operand 0 "nonimmediate_operand")
779 (match_operand 0 "const0_operand")))
781 ;; Return 1 when OP is nonimmediate or standard SSE constant.
782 (define_predicate "nonimmediate_or_sse_const_operand"
783 (match_operand 0 "general_operand")
785 if (nonimmediate_operand (op, mode))
787 if (standard_sse_constant_p (op) > 0)
792 ;; Return true if OP is a register or a zero.
793 (define_predicate "reg_or_0_operand"
794 (ior (match_operand 0 "register_operand")
795 (match_operand 0 "const0_operand")))
797 ;; Return true if op if a valid address, and does not contain
798 ;; a segment override.
799 (define_special_predicate "no_seg_address_operand"
800 (match_operand 0 "address_operand")
802 struct ix86_address parts;
805 ok = ix86_decompose_address (op, &parts);
807 return parts.seg == SEG_DEFAULT;
810 ;; Return nonzero if the rtx is known to be at least 32 bits aligned.
811 (define_predicate "aligned_operand"
812 (match_operand 0 "general_operand")
814 struct ix86_address parts;
817 /* Registers and immediate operands are always "aligned". */
821 /* All patterns using aligned_operand on memory operands ends up
822 in promoting memory operand to 64bit and thus causing memory mismatch. */
823 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
826 /* Don't even try to do any aligned optimizations with volatiles. */
827 if (MEM_VOLATILE_P (op))
830 if (MEM_ALIGN (op) >= 32)
835 /* Pushes and pops are only valid on the stack pointer. */
836 if (GET_CODE (op) == PRE_DEC
837 || GET_CODE (op) == POST_INC)
840 /* Decode the address. */
841 ok = ix86_decompose_address (op, &parts);
844 /* Look for some component that isn't known to be aligned. */
847 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
852 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
857 if (!CONST_INT_P (parts.disp)
858 || (INTVAL (parts.disp) & 3) != 0)
862 /* Didn't find one -- this must be an aligned address. */
866 ;; Returns 1 if OP is memory operand with a displacement.
867 (define_predicate "memory_displacement_operand"
868 (match_operand 0 "memory_operand")
870 struct ix86_address parts;
873 ok = ix86_decompose_address (XEXP (op, 0), &parts);
875 return parts.disp != NULL_RTX;
878 ;; Returns 1 if OP is memory operand with a displacement only.
879 (define_predicate "memory_displacement_only_operand"
880 (match_operand 0 "memory_operand")
882 struct ix86_address parts;
888 ok = ix86_decompose_address (XEXP (op, 0), &parts);
891 if (parts.base || parts.index)
894 return parts.disp != NULL_RTX;
897 ;; Returns 1 if OP is memory operand which will need zero or
898 ;; one register at most, not counting stack pointer or frame pointer.
899 (define_predicate "cmpxchg8b_pic_memory_operand"
900 (match_operand 0 "memory_operand")
902 struct ix86_address parts;
905 ok = ix86_decompose_address (XEXP (op, 0), &parts);
907 if (parts.base == NULL_RTX
908 || parts.base == arg_pointer_rtx
909 || parts.base == frame_pointer_rtx
910 || parts.base == hard_frame_pointer_rtx
911 || parts.base == stack_pointer_rtx)
914 if (parts.index == NULL_RTX
915 || parts.index == arg_pointer_rtx
916 || parts.index == frame_pointer_rtx
917 || parts.index == hard_frame_pointer_rtx
918 || parts.index == stack_pointer_rtx)
925 ;; Returns 1 if OP is memory operand that cannot be represented
926 ;; by the modRM array.
927 (define_predicate "long_memory_operand"
928 (and (match_operand 0 "memory_operand")
929 (match_test "memory_address_length (op) != 0")))
931 ;; Return 1 if OP is a comparison operator that can be issued by fcmov.
932 (define_predicate "fcmov_comparison_operator"
933 (match_operand 0 "comparison_operator")
935 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
936 enum rtx_code code = GET_CODE (op);
938 if (inmode == CCFPmode || inmode == CCFPUmode)
940 if (!ix86_trivial_fp_comparison_operator (op, mode))
942 code = ix86_fp_compare_code_to_integer (code);
944 /* i387 supports just limited amount of conditional codes. */
947 case LTU: case GTU: case LEU: case GEU:
948 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
949 || inmode == CCCmode)
952 case ORDERED: case UNORDERED:
960 ;; Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS insns.
961 ;; The first set are supported directly; the second set can't be done with
962 ;; full IEEE support, i.e. NaNs.
964 ;; ??? It would seem that we have a lot of uses of this predicate that pass
965 ;; it the wrong mode. We got away with this because the old function didn't
966 ;; check the mode at all. Mirror that for now by calling this a special
969 (define_special_predicate "sse_comparison_operator"
970 (match_code "eq,lt,le,unordered,ne,unge,ungt,ordered"))
972 ;; Return 1 if OP is a comparison operator that can be issued by
973 ;; avx predicate generation instructions
974 (define_predicate "avx_comparison_float_operator"
975 (match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt"))
977 (define_predicate "ix86_comparison_int_operator"
978 (match_code "ne,eq,ge,gt,le,lt"))
980 (define_predicate "ix86_comparison_uns_operator"
981 (match_code "ne,eq,geu,gtu,leu,ltu"))
983 (define_predicate "bt_comparison_operator"
984 (match_code "ne,eq"))
986 ;; Return 1 if OP is a valid comparison operator in valid mode.
987 (define_predicate "ix86_comparison_operator"
988 (match_operand 0 "comparison_operator")
990 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
991 enum rtx_code code = GET_CODE (op);
993 if (inmode == CCFPmode || inmode == CCFPUmode)
994 return ix86_trivial_fp_comparison_operator (op, mode);
1001 if (inmode == CCmode || inmode == CCGCmode
1002 || inmode == CCGOCmode || inmode == CCNOmode)
1005 case LTU: case GTU: case LEU: case GEU:
1006 if (inmode == CCmode || inmode == CCCmode)
1009 case ORDERED: case UNORDERED:
1010 if (inmode == CCmode)
1014 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1022 ;; Return 1 if OP is a valid comparison operator testing carry flag to be set.
1023 (define_predicate "ix86_carry_flag_operator"
1024 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1026 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1027 enum rtx_code code = GET_CODE (op);
1029 if (inmode == CCFPmode || inmode == CCFPUmode)
1031 if (!ix86_trivial_fp_comparison_operator (op, mode))
1033 code = ix86_fp_compare_code_to_integer (code);
1035 else if (inmode == CCCmode)
1036 return code == LTU || code == GTU;
1037 else if (inmode != CCmode)
1043 ;; Return 1 if this comparison only requires testing one flag bit.
1044 (define_predicate "ix86_trivial_fp_comparison_operator"
1045 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1047 ;; Return 1 if we know how to do this comparison. Others require
1048 ;; testing more than one flag bit, and we let the generic middle-end
1050 (define_predicate "ix86_fp_comparison_operator"
1051 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1052 == IX86_FPCMP_ARITH")
1053 (match_operand 0 "comparison_operator")
1054 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1056 ;; Nearly general operand, but accept any const_double, since we wish
1057 ;; to be able to drop them into memory rather than have them get pulled
1059 (define_predicate "cmp_fp_expander_operand"
1060 (ior (match_code "const_double")
1061 (match_operand 0 "general_operand")))
1063 ;; Return true if this is a valid binary floating-point operation.
1064 (define_predicate "binary_fp_operator"
1065 (match_code "plus,minus,mult,div"))
1067 ;; Return true if this is a multiply operation.
1068 (define_predicate "mult_operator"
1069 (match_code "mult"))
1071 ;; Return true if this is a division operation.
1072 (define_predicate "div_operator"
1075 ;; Return true if this is a float extend operation.
1076 (define_predicate "float_operator"
1077 (match_code "float"))
1079 ;; Return true for ARITHMETIC_P.
1080 (define_predicate "arith_or_logical_operator"
1081 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1082 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1084 ;; Return true for COMMUTATIVE_P.
1085 (define_predicate "commutative_operator"
1086 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1088 ;; Return 1 if OP is a binary operator that can be promoted to wider mode.
1089 (define_predicate "promotable_binary_operator"
1090 (ior (match_code "plus,and,ior,xor,ashift")
1091 (and (match_code "mult")
1092 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1094 (define_predicate "compare_operator"
1095 (match_code "compare"))
1097 (define_predicate "absneg_operator"
1098 (match_code "abs,neg"))
1100 ;; Return 1 if OP is misaligned memory operand
1101 (define_predicate "misaligned_operand"
1102 (and (match_code "mem")
1103 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1105 ;; Return 1 if OP is a emms operation, known to be a PARALLEL.
1106 (define_predicate "emms_operation"
1107 (match_code "parallel")
1111 if (XVECLEN (op, 0) != 17)
1114 for (i = 0; i < 8; i++)
1116 rtx elt = XVECEXP (op, 0, i+1);
1118 if (GET_CODE (elt) != CLOBBER
1119 || GET_CODE (SET_DEST (elt)) != REG
1120 || GET_MODE (SET_DEST (elt)) != XFmode
1121 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1124 elt = XVECEXP (op, 0, i+9);
1126 if (GET_CODE (elt) != CLOBBER
1127 || GET_CODE (SET_DEST (elt)) != REG
1128 || GET_MODE (SET_DEST (elt)) != DImode
1129 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1135 ;; Return 1 if OP is a vzeroall operation, known to be a PARALLEL.
1136 (define_predicate "vzeroall_operation"
1137 (match_code "parallel")
1139 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1141 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1144 for (i = 0; i < nregs; i++)
1146 rtx elt = XVECEXP (op, 0, i+1);
1148 if (GET_CODE (elt) != SET
1149 || GET_CODE (SET_DEST (elt)) != REG
1150 || GET_MODE (SET_DEST (elt)) != V8SImode
1151 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1152 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1158 ;; Return 1 if OP is a vzeroupper operation, known to be a PARALLEL.
1159 (define_predicate "vzeroupper_operation"
1160 (match_code "parallel")
1162 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1164 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1167 for (i = 0; i < nregs; i++)
1169 rtx elt = XVECEXP (op, 0, i+1);
1171 if (GET_CODE (elt) != CLOBBER
1172 || GET_CODE (SET_DEST (elt)) != REG
1173 || GET_MODE (SET_DEST (elt)) != V8SImode
1174 || REGNO (SET_DEST (elt)) != SSE_REGNO (i))
1180 ;; Return 1 if OP is a parallel for a vpermilp[ds] permute.
1181 ;; ??? It would be much easier if the PARALLEL for a VEC_SELECT
1182 ;; had a mode, but it doesn't. So we have 4 copies and install
1183 ;; the mode by hand.
1185 (define_predicate "avx_vpermilp_v8sf_operand"
1186 (and (match_code "parallel")
1187 (match_test "avx_vpermilp_parallel (op, V8SFmode)")))
1189 (define_predicate "avx_vpermilp_v4df_operand"
1190 (and (match_code "parallel")
1191 (match_test "avx_vpermilp_parallel (op, V4DFmode)")))
1193 (define_predicate "avx_vpermilp_v4sf_operand"
1194 (and (match_code "parallel")
1195 (match_test "avx_vpermilp_parallel (op, V4SFmode)")))
1197 (define_predicate "avx_vpermilp_v2df_operand"
1198 (and (match_code "parallel")
1199 (match_test "avx_vpermilp_parallel (op, V2DFmode)")))
1201 ;; Return 1 if OP is a parallel for a vperm2f128 permute.
1203 (define_predicate "avx_vperm2f128_v8sf_operand"
1204 (and (match_code "parallel")
1205 (match_test "avx_vperm2f128_parallel (op, V8SFmode)")))
1207 (define_predicate "avx_vperm2f128_v8si_operand"
1208 (and (match_code "parallel")
1209 (match_test "avx_vperm2f128_parallel (op, V8SImode)")))
1211 (define_predicate "avx_vperm2f128_v4df_operand"
1212 (and (match_code "parallel")
1213 (match_test "avx_vperm2f128_parallel (op, V4DFmode)")))
1215 ;; Return 1 if OP is a parallel for a vbroadcast permute.
1217 (define_predicate "avx_vbroadcast_operand"
1218 (and (match_code "parallel")
1219 (match_code "const_int" "a"))
1221 rtx elt = XVECEXP (op, 0, 0);
1222 int i, nelt = XVECLEN (op, 0);
1224 /* Don't bother checking there are the right number of operands,
1225 merely that they're all identical. */
1226 for (i = 1; i < nelt; ++i)
1227 if (XVECEXP (op, 0, i) != elt)