1 ;; GCC machine description for MMX and 3dNOW! instructions
2 ;; Copyright (C) 2005, 2007, 2008
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The MMX and 3dNOW! patterns are in the same file because they use
22 ;; the same register file, and 3dNOW! adds a number of extensions to
23 ;; the base integer MMX isa.
25 ;; Note! Except for the basic move instructions, *all* of these
26 ;; patterns are outside the normal optabs namespace. This is because
27 ;; use of these registers requires the insertion of emms or femms
28 ;; instructions to return to normal fpu mode. The compiler doesn't
29 ;; know how to do that itself, which means it's up to the user. Which
30 ;; means that we should never use any of these patterns except at the
31 ;; direction of the user via a builtin.
33 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
34 (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
35 (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI])
37 ;; All 8-byte vector modes handled by MMX
38 (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF])
41 (define_mode_iterator MMXMODE12 [V8QI V4HI])
42 (define_mode_iterator MMXMODE24 [V4HI V2SI])
43 (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
45 ;; Mapping from integer vector mode to mnemonic suffix
46 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")])
48 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
52 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54 ;; All of these patterns are enabled for MMX as well as 3dNOW.
55 ;; This is essential for maintaining stable calling conventions.
57 (define_expand "mov<mode>"
58 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "")
59 (match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))]
62 ix86_expand_vector_move (<MODE>mode, operands);
66 (define_insn "*mov<mode>_internal_rex64"
67 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
68 "=rm,r,!?y,!?y ,m ,!y,*Y2,x,x ,m,r,Yi")
69 (match_operand:MMXMODEI8 1 "vector_move_operand"
70 "Cr ,m,C ,!?ym,!?y,*Y2,!y,C,xm,x,Yi,r"))]
71 "TARGET_64BIT && TARGET_MMX
72 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
74 mov{q}\t{%1, %0|%0, %1}
75 mov{q}\t{%1, %0|%0, %1}
79 movdq2q\t{%1, %0|%0, %1}
80 movq2dq\t{%1, %0|%0, %1}
85 movd\t{%1, %0|%0, %1}"
86 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
87 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
88 (set_attr "mode" "DI")])
90 (define_insn "*mov<mode>_internal"
91 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
92 "=!?y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,r ,m")
93 (match_operand:MMXMODEI8 1 "vector_move_operand"
94 "C ,!ym,!?y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))]
96 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
100 movq\t{%1, %0|%0, %1}
101 movdq2q\t{%1, %0|%0, %1}
102 movq2dq\t{%1, %0|%0, %1}
104 movq\t{%1, %0|%0, %1}
105 movq\t{%1, %0|%0, %1}
107 movaps\t{%1, %0|%0, %1}
108 movlps\t{%1, %0|%0, %1}
109 movlps\t{%1, %0|%0, %1}
112 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
113 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
114 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
116 (define_expand "movv2sf"
117 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
118 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
121 ix86_expand_vector_move (V2SFmode, operands);
125 (define_insn "*movv2sf_internal_rex64"
126 [(set (match_operand:V2SF 0 "nonimmediate_operand"
127 "=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,Yi")
128 (match_operand:V2SF 1 "vector_move_operand"
129 "Cr ,m ,C ,!?ym,!y,*Y2,!y,C,x,m,x,Yi,r"))]
130 "TARGET_64BIT && TARGET_MMX
131 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
133 mov{q}\t{%1, %0|%0, %1}
134 mov{q}\t{%1, %0|%0, %1}
136 movq\t{%1, %0|%0, %1}
137 movq\t{%1, %0|%0, %1}
138 movdq2q\t{%1, %0|%0, %1}
139 movq2dq\t{%1, %0|%0, %1}
141 movaps\t{%1, %0|%0, %1}
142 movlps\t{%1, %0|%0, %1}
143 movlps\t{%1, %0|%0, %1}
144 movd\t{%1, %0|%0, %1}
145 movd\t{%1, %0|%0, %1}"
146 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
147 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
148 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
150 (define_insn "*movv2sf_internal"
151 [(set (match_operand:V2SF 0 "nonimmediate_operand"
152 "=!?y,!?y ,m ,!y ,*Y2,*x,*x,*x,m ,r ,m")
153 (match_operand:V2SF 1 "vector_move_operand"
154 "C ,!?ym,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))]
156 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
159 movq\t{%1, %0|%0, %1}
160 movq\t{%1, %0|%0, %1}
161 movdq2q\t{%1, %0|%0, %1}
162 movq2dq\t{%1, %0|%0, %1}
164 movaps\t{%1, %0|%0, %1}
165 movlps\t{%1, %0|%0, %1}
166 movlps\t{%1, %0|%0, %1}
169 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
170 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
171 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
173 ;; %%% This multiword shite has got to go.
175 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
176 (match_operand:MMXMODE 1 "general_operand" ""))]
177 "!TARGET_64BIT && reload_completed
178 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
179 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
181 "ix86_split_long_move (operands); DONE;")
183 (define_expand "push<mode>1"
184 [(match_operand:MMXMODE 0 "register_operand" "")]
187 ix86_expand_push (<MODE>mode, operands[0]);
191 (define_expand "movmisalign<mode>"
192 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
193 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
196 ix86_expand_vector_move (<MODE>mode, operands);
200 (define_insn "sse_movntdi"
201 [(set (match_operand:DI 0 "memory_operand" "=m")
202 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
204 "TARGET_SSE || TARGET_3DNOW_A"
205 "movntq\t{%1, %0|%0, %1}"
206 [(set_attr "type" "mmxmov")
207 (set_attr "mode" "DI")])
209 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
211 ;; Parallel single-precision floating point arithmetic
213 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
215 (define_expand "mmx_addv2sf3"
216 [(set (match_operand:V2SF 0 "register_operand" "")
218 (match_operand:V2SF 1 "nonimmediate_operand" "")
219 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
221 "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
223 (define_insn "*mmx_addv2sf3"
224 [(set (match_operand:V2SF 0 "register_operand" "=y")
225 (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
226 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
227 "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
228 "pfadd\t{%2, %0|%0, %2}"
229 [(set_attr "type" "mmxadd")
230 (set_attr "mode" "V2SF")])
232 (define_expand "mmx_subv2sf3"
233 [(set (match_operand:V2SF 0 "register_operand" "")
234 (minus:V2SF (match_operand:V2SF 1 "register_operand" "")
235 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
239 (define_expand "mmx_subrv2sf3"
240 [(set (match_operand:V2SF 0 "register_operand" "")
241 (minus:V2SF (match_operand:V2SF 2 "register_operand" "")
242 (match_operand:V2SF 1 "nonimmediate_operand" "")))]
246 (define_insn "*mmx_subv2sf3"
247 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
248 (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
249 (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
250 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
252 pfsub\t{%2, %0|%0, %2}
253 pfsubr\t{%2, %0|%0, %2}"
254 [(set_attr "type" "mmxadd")
255 (set_attr "mode" "V2SF")])
257 (define_expand "mmx_mulv2sf3"
258 [(set (match_operand:V2SF 0 "register_operand" "")
259 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
260 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
262 "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
264 (define_insn "*mmx_mulv2sf3"
265 [(set (match_operand:V2SF 0 "register_operand" "=y")
266 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
267 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
268 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
269 "pfmul\t{%2, %0|%0, %2}"
270 [(set_attr "type" "mmxmul")
271 (set_attr "mode" "V2SF")])
273 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
274 ;; isn't really correct, as those rtl operators aren't defined when
275 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
277 (define_expand "mmx_<code>v2sf3"
278 [(set (match_operand:V2SF 0 "register_operand" "")
280 (match_operand:V2SF 1 "nonimmediate_operand" "")
281 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
284 if (!flag_finite_math_only)
285 operands[1] = force_reg (V2SFmode, operands[1]);
286 ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
289 (define_insn "*mmx_<code>v2sf3_finite"
290 [(set (match_operand:V2SF 0 "register_operand" "=y")
292 (match_operand:V2SF 1 "nonimmediate_operand" "%0")
293 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
294 "TARGET_3DNOW && flag_finite_math_only
295 && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
296 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
297 [(set_attr "type" "mmxadd")
298 (set_attr "mode" "V2SF")])
300 (define_insn "*mmx_<code>v2sf3"
301 [(set (match_operand:V2SF 0 "register_operand" "=y")
303 (match_operand:V2SF 1 "register_operand" "0")
304 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
306 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
307 [(set_attr "type" "mmxadd")
308 (set_attr "mode" "V2SF")])
310 (define_insn "mmx_rcpv2sf2"
311 [(set (match_operand:V2SF 0 "register_operand" "=y")
312 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
315 "pfrcp\t{%1, %0|%0, %1}"
316 [(set_attr "type" "mmx")
317 (set_attr "mode" "V2SF")])
319 (define_insn "mmx_rcpit1v2sf3"
320 [(set (match_operand:V2SF 0 "register_operand" "=y")
321 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
322 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
325 "pfrcpit1\t{%2, %0|%0, %2}"
326 [(set_attr "type" "mmx")
327 (set_attr "mode" "V2SF")])
329 (define_insn "mmx_rcpit2v2sf3"
330 [(set (match_operand:V2SF 0 "register_operand" "=y")
331 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
332 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
335 "pfrcpit2\t{%2, %0|%0, %2}"
336 [(set_attr "type" "mmx")
337 (set_attr "mode" "V2SF")])
339 (define_insn "mmx_rsqrtv2sf2"
340 [(set (match_operand:V2SF 0 "register_operand" "=y")
341 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
344 "pfrsqrt\t{%1, %0|%0, %1}"
345 [(set_attr "type" "mmx")
346 (set_attr "mode" "V2SF")])
348 (define_insn "mmx_rsqit1v2sf3"
349 [(set (match_operand:V2SF 0 "register_operand" "=y")
350 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
351 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
354 "pfrsqit1\t{%2, %0|%0, %2}"
355 [(set_attr "type" "mmx")
356 (set_attr "mode" "V2SF")])
358 (define_insn "mmx_haddv2sf3"
359 [(set (match_operand:V2SF 0 "register_operand" "=y")
363 (match_operand:V2SF 1 "register_operand" "0")
364 (parallel [(const_int 0)]))
365 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
368 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
369 (parallel [(const_int 0)]))
370 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
372 "pfacc\t{%2, %0|%0, %2}"
373 [(set_attr "type" "mmxadd")
374 (set_attr "mode" "V2SF")])
376 (define_insn "mmx_hsubv2sf3"
377 [(set (match_operand:V2SF 0 "register_operand" "=y")
381 (match_operand:V2SF 1 "register_operand" "0")
382 (parallel [(const_int 0)]))
383 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
386 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
387 (parallel [(const_int 0)]))
388 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
390 "pfnacc\t{%2, %0|%0, %2}"
391 [(set_attr "type" "mmxadd")
392 (set_attr "mode" "V2SF")])
394 (define_insn "mmx_addsubv2sf3"
395 [(set (match_operand:V2SF 0 "register_operand" "=y")
398 (match_operand:V2SF 1 "register_operand" "0")
399 (match_operand:V2SF 2 "nonimmediate_operand" "ym"))
400 (minus:V2SF (match_dup 1) (match_dup 2))
403 "pfpnacc\t{%2, %0|%0, %2}"
404 [(set_attr "type" "mmxadd")
405 (set_attr "mode" "V2SF")])
407 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
409 ;; Parallel single-precision floating point comparisons
411 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
413 (define_expand "mmx_eqv2sf3"
414 [(set (match_operand:V2SI 0 "register_operand" "")
415 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "")
416 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
418 "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
420 (define_insn "*mmx_eqv2sf3"
421 [(set (match_operand:V2SI 0 "register_operand" "=y")
422 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
423 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
424 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
425 "pfcmpeq\t{%2, %0|%0, %2}"
426 [(set_attr "type" "mmxcmp")
427 (set_attr "mode" "V2SF")])
429 (define_insn "mmx_gtv2sf3"
430 [(set (match_operand:V2SI 0 "register_operand" "=y")
431 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
432 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
434 "pfcmpgt\t{%2, %0|%0, %2}"
435 [(set_attr "type" "mmxcmp")
436 (set_attr "mode" "V2SF")])
438 (define_insn "mmx_gev2sf3"
439 [(set (match_operand:V2SI 0 "register_operand" "=y")
440 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
441 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
443 "pfcmpge\t{%2, %0|%0, %2}"
444 [(set_attr "type" "mmxcmp")
445 (set_attr "mode" "V2SF")])
447 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
449 ;; Parallel single-precision floating point conversion operations
451 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
453 (define_insn "mmx_pf2id"
454 [(set (match_operand:V2SI 0 "register_operand" "=y")
455 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
457 "pf2id\t{%1, %0|%0, %1}"
458 [(set_attr "type" "mmxcvt")
459 (set_attr "mode" "V2SF")])
461 (define_insn "mmx_pf2iw"
462 [(set (match_operand:V2SI 0 "register_operand" "=y")
466 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
468 "pf2iw\t{%1, %0|%0, %1}"
469 [(set_attr "type" "mmxcvt")
470 (set_attr "mode" "V2SF")])
472 (define_insn "mmx_pi2fw"
473 [(set (match_operand:V2SF 0 "register_operand" "=y")
477 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
479 "pi2fw\t{%1, %0|%0, %1}"
480 [(set_attr "type" "mmxcvt")
481 (set_attr "mode" "V2SF")])
483 (define_insn "mmx_floatv2si2"
484 [(set (match_operand:V2SF 0 "register_operand" "=y")
485 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
487 "pi2fd\t{%1, %0|%0, %1}"
488 [(set_attr "type" "mmxcvt")
489 (set_attr "mode" "V2SF")])
491 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
493 ;; Parallel single-precision floating point element swizzling
495 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
497 (define_insn "mmx_pswapdv2sf2"
498 [(set (match_operand:V2SF 0 "register_operand" "=y")
499 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
500 (parallel [(const_int 1) (const_int 0)])))]
502 "pswapd\t{%1, %0|%0, %1}"
503 [(set_attr "type" "mmxcvt")
504 (set_attr "mode" "V2SF")])
506 (define_insn "*vec_dupv2sf"
507 [(set (match_operand:V2SF 0 "register_operand" "=y")
509 (match_operand:SF 1 "register_operand" "0")))]
512 [(set_attr "type" "mmxcvt")
513 (set_attr "mode" "DI")])
515 (define_insn "*mmx_concatv2sf"
516 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
518 (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
519 (match_operand:SF 2 "vector_move_operand" "ym,C")))]
520 "TARGET_MMX && !TARGET_SSE"
522 punpckldq\t{%2, %0|%0, %2}
523 movd\t{%1, %0|%0, %1}"
524 [(set_attr "type" "mmxcvt,mmxmov")
525 (set_attr "mode" "DI")])
527 (define_expand "vec_setv2sf"
528 [(match_operand:V2SF 0 "register_operand" "")
529 (match_operand:SF 1 "register_operand" "")
530 (match_operand 2 "const_int_operand" "")]
533 ix86_expand_vector_set (false, operands[0], operands[1],
534 INTVAL (operands[2]));
538 ;; Avoid combining registers from different units in a single alternative,
539 ;; see comment above inline_secondary_memory_needed function in i386.c
540 (define_insn_and_split "*vec_extractv2sf_0"
541 [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
543 (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
544 (parallel [(const_int 0)])))]
545 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
547 "&& reload_completed"
550 rtx op1 = operands[1];
552 op1 = gen_rtx_REG (SFmode, REGNO (op1));
554 op1 = gen_lowpart (SFmode, op1);
555 emit_move_insn (operands[0], op1);
559 ;; Avoid combining registers from different units in a single alternative,
560 ;; see comment above inline_secondary_memory_needed function in i386.c
561 (define_insn "*vec_extractv2sf_1"
562 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,y,x,f,r")
564 (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o,o,o,o")
565 (parallel [(const_int 1)])))]
566 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
574 [(set_attr "type" "mmxcvt,sselog1,mmxmov,ssemov,fmov,imov")
575 (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")])
578 [(set (match_operand:SF 0 "register_operand" "")
580 (match_operand:V2SF 1 "memory_operand" "")
581 (parallel [(const_int 1)])))]
582 "TARGET_MMX && reload_completed"
585 operands[1] = adjust_address (operands[1], SFmode, 4);
586 emit_move_insn (operands[0], operands[1]);
590 (define_expand "vec_extractv2sf"
591 [(match_operand:SF 0 "register_operand" "")
592 (match_operand:V2SF 1 "register_operand" "")
593 (match_operand 2 "const_int_operand" "")]
596 ix86_expand_vector_extract (false, operands[0], operands[1],
597 INTVAL (operands[2]));
601 (define_expand "vec_initv2sf"
602 [(match_operand:V2SF 0 "register_operand" "")
603 (match_operand 1 "" "")]
606 ix86_expand_vector_init (false, operands[0], operands[1]);
610 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
612 ;; Parallel integral arithmetic
614 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
616 (define_expand "mmx_<plusminus_insn><mode>3"
617 [(set (match_operand:MMXMODEI8 0 "register_operand" "")
619 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "")
620 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))]
621 "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
622 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
624 (define_insn "*mmx_<plusminus_insn><mode>3"
625 [(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
627 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
628 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
629 "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
630 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
631 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
632 [(set_attr "type" "mmxadd")
633 (set_attr "mode" "DI")])
635 (define_expand "mmx_<plusminus_insn><mode>3"
636 [(set (match_operand:MMXMODE12 0 "register_operand" "")
637 (sat_plusminus:MMXMODE12
638 (match_operand:MMXMODE12 1 "nonimmediate_operand" "")
639 (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))]
641 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
643 (define_insn "*mmx_<plusminus_insn><mode>3"
644 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
645 (sat_plusminus:MMXMODE12
646 (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
647 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
648 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
649 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
650 [(set_attr "type" "mmxadd")
651 (set_attr "mode" "DI")])
653 (define_expand "mmx_mulv4hi3"
654 [(set (match_operand:V4HI 0 "register_operand" "")
655 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "")
656 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
658 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
660 (define_insn "*mmx_mulv4hi3"
661 [(set (match_operand:V4HI 0 "register_operand" "=y")
662 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
663 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
664 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
665 "pmullw\t{%2, %0|%0, %2}"
666 [(set_attr "type" "mmxmul")
667 (set_attr "mode" "DI")])
669 (define_expand "mmx_smulv4hi3_highpart"
670 [(set (match_operand:V4HI 0 "register_operand" "")
675 (match_operand:V4HI 1 "nonimmediate_operand" ""))
677 (match_operand:V4HI 2 "nonimmediate_operand" "")))
680 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
682 (define_insn "*mmx_smulv4hi3_highpart"
683 [(set (match_operand:V4HI 0 "register_operand" "=y")
688 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
690 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
692 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
693 "pmulhw\t{%2, %0|%0, %2}"
694 [(set_attr "type" "mmxmul")
695 (set_attr "mode" "DI")])
697 (define_expand "mmx_umulv4hi3_highpart"
698 [(set (match_operand:V4HI 0 "register_operand" "")
703 (match_operand:V4HI 1 "nonimmediate_operand" ""))
705 (match_operand:V4HI 2 "nonimmediate_operand" "")))
707 "TARGET_SSE || TARGET_3DNOW_A"
708 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
710 (define_insn "*mmx_umulv4hi3_highpart"
711 [(set (match_operand:V4HI 0 "register_operand" "=y")
716 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
718 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
720 "(TARGET_SSE || TARGET_3DNOW_A)
721 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
722 "pmulhuw\t{%2, %0|%0, %2}"
723 [(set_attr "type" "mmxmul")
724 (set_attr "mode" "DI")])
726 (define_expand "mmx_pmaddwd"
727 [(set (match_operand:V2SI 0 "register_operand" "")
732 (match_operand:V4HI 1 "nonimmediate_operand" "")
733 (parallel [(const_int 0) (const_int 2)])))
736 (match_operand:V4HI 2 "nonimmediate_operand" "")
737 (parallel [(const_int 0) (const_int 2)]))))
740 (vec_select:V2HI (match_dup 1)
741 (parallel [(const_int 1) (const_int 3)])))
743 (vec_select:V2HI (match_dup 2)
744 (parallel [(const_int 1) (const_int 3)]))))))]
746 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
748 (define_insn "*mmx_pmaddwd"
749 [(set (match_operand:V2SI 0 "register_operand" "=y")
754 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
755 (parallel [(const_int 0) (const_int 2)])))
758 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
759 (parallel [(const_int 0) (const_int 2)]))))
762 (vec_select:V2HI (match_dup 1)
763 (parallel [(const_int 1) (const_int 3)])))
765 (vec_select:V2HI (match_dup 2)
766 (parallel [(const_int 1) (const_int 3)]))))))]
767 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
768 "pmaddwd\t{%2, %0|%0, %2}"
769 [(set_attr "type" "mmxmul")
770 (set_attr "mode" "DI")])
772 (define_expand "mmx_pmulhrwv4hi3"
773 [(set (match_operand:V4HI 0 "register_operand" "")
779 (match_operand:V4HI 1 "nonimmediate_operand" ""))
781 (match_operand:V4HI 2 "nonimmediate_operand" "")))
782 (const_vector:V4SI [(const_int 32768) (const_int 32768)
783 (const_int 32768) (const_int 32768)]))
786 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
788 (define_insn "*mmx_pmulhrwv4hi3"
789 [(set (match_operand:V4HI 0 "register_operand" "=y")
795 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
797 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
798 (const_vector:V4SI [(const_int 32768) (const_int 32768)
799 (const_int 32768) (const_int 32768)]))
801 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
802 "pmulhrw\t{%2, %0|%0, %2}"
803 [(set_attr "type" "mmxmul")
804 (set_attr "mode" "DI")])
806 (define_expand "sse2_umulv1siv1di3"
807 [(set (match_operand:V1DI 0 "register_operand" "")
811 (match_operand:V2SI 1 "nonimmediate_operand" "")
812 (parallel [(const_int 0)])))
815 (match_operand:V2SI 2 "nonimmediate_operand" "")
816 (parallel [(const_int 0)])))))]
818 "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
820 (define_insn "*sse2_umulv1siv1di3"
821 [(set (match_operand:V1DI 0 "register_operand" "=y")
825 (match_operand:V2SI 1 "nonimmediate_operand" "%0")
826 (parallel [(const_int 0)])))
829 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
830 (parallel [(const_int 0)])))))]
831 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
832 "pmuludq\t{%2, %0|%0, %2}"
833 [(set_attr "type" "mmxmul")
834 (set_attr "mode" "DI")])
836 (define_expand "mmx_<code>v4hi3"
837 [(set (match_operand:V4HI 0 "register_operand" "")
839 (match_operand:V4HI 1 "nonimmediate_operand" "")
840 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
841 "TARGET_SSE || TARGET_3DNOW_A"
842 "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
844 (define_insn "*mmx_<code>v4hi3"
845 [(set (match_operand:V4HI 0 "register_operand" "=y")
847 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
848 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
849 "(TARGET_SSE || TARGET_3DNOW_A)
850 && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
851 "p<maxminiprefix>w\t{%2, %0|%0, %2}"
852 [(set_attr "type" "mmxadd")
853 (set_attr "mode" "DI")])
855 (define_expand "mmx_<code>v8qi3"
856 [(set (match_operand:V8QI 0 "register_operand" "")
858 (match_operand:V8QI 1 "nonimmediate_operand" "")
859 (match_operand:V8QI 2 "nonimmediate_operand" "")))]
860 "TARGET_SSE || TARGET_3DNOW_A"
861 "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
863 (define_insn "*mmx_<code>v8qi3"
864 [(set (match_operand:V8QI 0 "register_operand" "=y")
866 (match_operand:V8QI 1 "nonimmediate_operand" "%0")
867 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
868 "(TARGET_SSE || TARGET_3DNOW_A)
869 && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
870 "p<maxminiprefix>b\t{%2, %0|%0, %2}"
871 [(set_attr "type" "mmxadd")
872 (set_attr "mode" "DI")])
874 (define_insn "mmx_ashr<mode>3"
875 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
877 (match_operand:MMXMODE24 1 "register_operand" "0")
878 (match_operand:SI 2 "nonmemory_operand" "yN")))]
880 "psra<mmxvecsize>\t{%2, %0|%0, %2}"
881 [(set_attr "type" "mmxshft")
882 (set_attr "mode" "DI")])
884 (define_insn "mmx_lshr<mode>3"
885 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
887 (match_operand:MMXMODE248 1 "register_operand" "0")
888 (match_operand:SI 2 "nonmemory_operand" "yN")))]
890 "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
891 [(set_attr "type" "mmxshft")
892 (set_attr "mode" "DI")])
894 (define_insn "mmx_ashl<mode>3"
895 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
897 (match_operand:MMXMODE248 1 "register_operand" "0")
898 (match_operand:SI 2 "nonmemory_operand" "yN")))]
900 "psll<mmxvecsize>\t{%2, %0|%0, %2}"
901 [(set_attr "type" "mmxshft")
902 (set_attr "mode" "DI")])
904 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
906 ;; Parallel integral comparisons
908 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
910 (define_expand "mmx_eq<mode>3"
911 [(set (match_operand:MMXMODEI 0 "register_operand" "")
913 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
914 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
916 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
918 (define_insn "*mmx_eq<mode>3"
919 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
921 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
922 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
923 "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
924 "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}"
925 [(set_attr "type" "mmxcmp")
926 (set_attr "mode" "DI")])
928 (define_insn "mmx_gt<mode>3"
929 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
931 (match_operand:MMXMODEI 1 "register_operand" "0")
932 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
934 "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}"
935 [(set_attr "type" "mmxcmp")
936 (set_attr "mode" "DI")])
938 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
940 ;; Parallel integral logical operations
942 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
944 (define_insn "mmx_nand<mode>3"
945 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
947 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
948 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
950 "pandn\t{%2, %0|%0, %2}"
951 [(set_attr "type" "mmxadd")
952 (set_attr "mode" "DI")])
954 (define_expand "mmx_<code><mode>3"
955 [(set (match_operand:MMXMODEI 0 "register_operand" "")
957 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
958 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
960 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
962 (define_insn "*mmx_<code><mode>3"
963 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
965 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
966 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
967 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
968 "p<plogicprefix>\t{%2, %0|%0, %2}"
969 [(set_attr "type" "mmxadd")
970 (set_attr "mode" "DI")])
972 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
974 ;; Parallel integral element swizzling
976 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
978 (define_insn "mmx_packsswb"
979 [(set (match_operand:V8QI 0 "register_operand" "=y")
982 (match_operand:V4HI 1 "register_operand" "0"))
984 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
986 "packsswb\t{%2, %0|%0, %2}"
987 [(set_attr "type" "mmxshft")
988 (set_attr "mode" "DI")])
990 (define_insn "mmx_packssdw"
991 [(set (match_operand:V4HI 0 "register_operand" "=y")
994 (match_operand:V2SI 1 "register_operand" "0"))
996 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))]
998 "packssdw\t{%2, %0|%0, %2}"
999 [(set_attr "type" "mmxshft")
1000 (set_attr "mode" "DI")])
1002 (define_insn "mmx_packuswb"
1003 [(set (match_operand:V8QI 0 "register_operand" "=y")
1006 (match_operand:V4HI 1 "register_operand" "0"))
1008 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1010 "packuswb\t{%2, %0|%0, %2}"
1011 [(set_attr "type" "mmxshft")
1012 (set_attr "mode" "DI")])
1014 (define_insn "mmx_punpckhbw"
1015 [(set (match_operand:V8QI 0 "register_operand" "=y")
1018 (match_operand:V8QI 1 "register_operand" "0")
1019 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1020 (parallel [(const_int 4) (const_int 12)
1021 (const_int 5) (const_int 13)
1022 (const_int 6) (const_int 14)
1023 (const_int 7) (const_int 15)])))]
1025 "punpckhbw\t{%2, %0|%0, %2}"
1026 [(set_attr "type" "mmxcvt")
1027 (set_attr "mode" "DI")])
1029 (define_insn "mmx_punpcklbw"
1030 [(set (match_operand:V8QI 0 "register_operand" "=y")
1033 (match_operand:V8QI 1 "register_operand" "0")
1034 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1035 (parallel [(const_int 0) (const_int 8)
1036 (const_int 1) (const_int 9)
1037 (const_int 2) (const_int 10)
1038 (const_int 3) (const_int 11)])))]
1040 "punpcklbw\t{%2, %0|%0, %2}"
1041 [(set_attr "type" "mmxcvt")
1042 (set_attr "mode" "DI")])
1044 (define_insn "mmx_punpckhwd"
1045 [(set (match_operand:V4HI 0 "register_operand" "=y")
1048 (match_operand:V4HI 1 "register_operand" "0")
1049 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1050 (parallel [(const_int 2) (const_int 6)
1051 (const_int 3) (const_int 7)])))]
1053 "punpckhwd\t{%2, %0|%0, %2}"
1054 [(set_attr "type" "mmxcvt")
1055 (set_attr "mode" "DI")])
1057 (define_insn "mmx_punpcklwd"
1058 [(set (match_operand:V4HI 0 "register_operand" "=y")
1061 (match_operand:V4HI 1 "register_operand" "0")
1062 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1063 (parallel [(const_int 0) (const_int 4)
1064 (const_int 1) (const_int 5)])))]
1066 "punpcklwd\t{%2, %0|%0, %2}"
1067 [(set_attr "type" "mmxcvt")
1068 (set_attr "mode" "DI")])
1070 (define_insn "mmx_punpckhdq"
1071 [(set (match_operand:V2SI 0 "register_operand" "=y")
1074 (match_operand:V2SI 1 "register_operand" "0")
1075 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1076 (parallel [(const_int 1)
1079 "punpckhdq\t{%2, %0|%0, %2}"
1080 [(set_attr "type" "mmxcvt")
1081 (set_attr "mode" "DI")])
1083 (define_insn "mmx_punpckldq"
1084 [(set (match_operand:V2SI 0 "register_operand" "=y")
1087 (match_operand:V2SI 1 "register_operand" "0")
1088 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1089 (parallel [(const_int 0)
1092 "punpckldq\t{%2, %0|%0, %2}"
1093 [(set_attr "type" "mmxcvt")
1094 (set_attr "mode" "DI")])
1096 (define_expand "mmx_pinsrw"
1097 [(set (match_operand:V4HI 0 "register_operand" "")
1100 (match_operand:SI 2 "nonimmediate_operand" ""))
1101 (match_operand:V4HI 1 "register_operand" "")
1102 (match_operand:SI 3 "const_0_to_3_operand" "")))]
1103 "TARGET_SSE || TARGET_3DNOW_A"
1105 operands[2] = gen_lowpart (HImode, operands[2]);
1106 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
1109 (define_insn "*mmx_pinsrw"
1110 [(set (match_operand:V4HI 0 "register_operand" "=y")
1113 (match_operand:HI 2 "nonimmediate_operand" "rm"))
1114 (match_operand:V4HI 1 "register_operand" "0")
1115 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
1116 "TARGET_SSE || TARGET_3DNOW_A"
1118 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
1119 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
1121 [(set_attr "type" "mmxcvt")
1122 (set_attr "mode" "DI")])
1124 (define_insn "mmx_pextrw"
1125 [(set (match_operand:SI 0 "register_operand" "=r")
1128 (match_operand:V4HI 1 "register_operand" "y")
1129 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
1130 "TARGET_SSE || TARGET_3DNOW_A"
1131 "pextrw\t{%2, %1, %0|%0, %1, %2}"
1132 [(set_attr "type" "mmxcvt")
1133 (set_attr "mode" "DI")])
1135 (define_expand "mmx_pshufw"
1136 [(match_operand:V4HI 0 "register_operand" "")
1137 (match_operand:V4HI 1 "nonimmediate_operand" "")
1138 (match_operand:SI 2 "const_int_operand" "")]
1139 "TARGET_SSE || TARGET_3DNOW_A"
1141 int mask = INTVAL (operands[2]);
1142 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
1143 GEN_INT ((mask >> 0) & 3),
1144 GEN_INT ((mask >> 2) & 3),
1145 GEN_INT ((mask >> 4) & 3),
1146 GEN_INT ((mask >> 6) & 3)));
1150 (define_insn "mmx_pshufw_1"
1151 [(set (match_operand:V4HI 0 "register_operand" "=y")
1153 (match_operand:V4HI 1 "nonimmediate_operand" "ym")
1154 (parallel [(match_operand 2 "const_0_to_3_operand" "")
1155 (match_operand 3 "const_0_to_3_operand" "")
1156 (match_operand 4 "const_0_to_3_operand" "")
1157 (match_operand 5 "const_0_to_3_operand" "")])))]
1158 "TARGET_SSE || TARGET_3DNOW_A"
1161 mask |= INTVAL (operands[2]) << 0;
1162 mask |= INTVAL (operands[3]) << 2;
1163 mask |= INTVAL (operands[4]) << 4;
1164 mask |= INTVAL (operands[5]) << 6;
1165 operands[2] = GEN_INT (mask);
1167 return "pshufw\t{%2, %1, %0|%0, %1, %2}";
1169 [(set_attr "type" "mmxcvt")
1170 (set_attr "mode" "DI")])
1172 (define_insn "mmx_pswapdv2si2"
1173 [(set (match_operand:V2SI 0 "register_operand" "=y")
1175 (match_operand:V2SI 1 "nonimmediate_operand" "ym")
1176 (parallel [(const_int 1) (const_int 0)])))]
1178 "pswapd\t{%1, %0|%0, %1}"
1179 [(set_attr "type" "mmxcvt")
1180 (set_attr "mode" "DI")])
1182 (define_insn "*vec_dupv4hi"
1183 [(set (match_operand:V4HI 0 "register_operand" "=y")
1186 (match_operand:SI 1 "register_operand" "0"))))]
1187 "TARGET_SSE || TARGET_3DNOW_A"
1188 "pshufw\t{$0, %0, %0|%0, %0, 0}"
1189 [(set_attr "type" "mmxcvt")
1190 (set_attr "mode" "DI")])
1192 (define_insn "*vec_dupv2si"
1193 [(set (match_operand:V2SI 0 "register_operand" "=y")
1195 (match_operand:SI 1 "register_operand" "0")))]
1198 [(set_attr "type" "mmxcvt")
1199 (set_attr "mode" "DI")])
1201 (define_insn "*mmx_concatv2si"
1202 [(set (match_operand:V2SI 0 "register_operand" "=y,y")
1204 (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
1205 (match_operand:SI 2 "vector_move_operand" "ym,C")))]
1206 "TARGET_MMX && !TARGET_SSE"
1208 punpckldq\t{%2, %0|%0, %2}
1209 movd\t{%1, %0|%0, %1}"
1210 [(set_attr "type" "mmxcvt,mmxmov")
1211 (set_attr "mode" "DI")])
1213 (define_expand "vec_setv2si"
1214 [(match_operand:V2SI 0 "register_operand" "")
1215 (match_operand:SI 1 "register_operand" "")
1216 (match_operand 2 "const_int_operand" "")]
1219 ix86_expand_vector_set (false, operands[0], operands[1],
1220 INTVAL (operands[2]));
1224 ;; Avoid combining registers from different units in a single alternative,
1225 ;; see comment above inline_secondary_memory_needed function in i386.c
1226 (define_insn_and_split "*vec_extractv2si_0"
1227 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r")
1229 (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m")
1230 (parallel [(const_int 0)])))]
1231 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1233 "&& reload_completed"
1236 rtx op1 = operands[1];
1238 op1 = gen_rtx_REG (SImode, REGNO (op1));
1240 op1 = gen_lowpart (SImode, op1);
1241 emit_move_insn (operands[0], op1);
1245 ;; Avoid combining registers from different units in a single alternative,
1246 ;; see comment above inline_secondary_memory_needed function in i386.c
1247 (define_insn "*vec_extractv2si_1"
1248 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,y,x,r")
1250 (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o,o,o")
1251 (parallel [(const_int 1)])))]
1252 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1256 pshufd\t{$85, %1, %0|%0, %1, 85}
1261 [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
1262 (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
1265 [(set (match_operand:SI 0 "register_operand" "")
1267 (match_operand:V2SI 1 "memory_operand" "")
1268 (parallel [(const_int 1)])))]
1269 "TARGET_MMX && reload_completed"
1272 operands[1] = adjust_address (operands[1], SImode, 4);
1273 emit_move_insn (operands[0], operands[1]);
1277 (define_expand "vec_extractv2si"
1278 [(match_operand:SI 0 "register_operand" "")
1279 (match_operand:V2SI 1 "register_operand" "")
1280 (match_operand 2 "const_int_operand" "")]
1283 ix86_expand_vector_extract (false, operands[0], operands[1],
1284 INTVAL (operands[2]));
1288 (define_expand "vec_initv2si"
1289 [(match_operand:V2SI 0 "register_operand" "")
1290 (match_operand 1 "" "")]
1293 ix86_expand_vector_init (false, operands[0], operands[1]);
1297 (define_expand "vec_setv4hi"
1298 [(match_operand:V4HI 0 "register_operand" "")
1299 (match_operand:HI 1 "register_operand" "")
1300 (match_operand 2 "const_int_operand" "")]
1303 ix86_expand_vector_set (false, operands[0], operands[1],
1304 INTVAL (operands[2]));
1308 (define_expand "vec_extractv4hi"
1309 [(match_operand:HI 0 "register_operand" "")
1310 (match_operand:V4HI 1 "register_operand" "")
1311 (match_operand 2 "const_int_operand" "")]
1314 ix86_expand_vector_extract (false, operands[0], operands[1],
1315 INTVAL (operands[2]));
1319 (define_expand "vec_initv4hi"
1320 [(match_operand:V4HI 0 "register_operand" "")
1321 (match_operand 1 "" "")]
1324 ix86_expand_vector_init (false, operands[0], operands[1]);
1328 (define_expand "vec_setv8qi"
1329 [(match_operand:V8QI 0 "register_operand" "")
1330 (match_operand:QI 1 "register_operand" "")
1331 (match_operand 2 "const_int_operand" "")]
1334 ix86_expand_vector_set (false, operands[0], operands[1],
1335 INTVAL (operands[2]));
1339 (define_expand "vec_extractv8qi"
1340 [(match_operand:QI 0 "register_operand" "")
1341 (match_operand:V8QI 1 "register_operand" "")
1342 (match_operand 2 "const_int_operand" "")]
1345 ix86_expand_vector_extract (false, operands[0], operands[1],
1346 INTVAL (operands[2]));
1350 (define_expand "vec_initv8qi"
1351 [(match_operand:V8QI 0 "register_operand" "")
1352 (match_operand 1 "" "")]
1355 ix86_expand_vector_init (false, operands[0], operands[1]);
1359 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1363 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1365 (define_expand "mmx_uavgv8qi3"
1366 [(set (match_operand:V8QI 0 "register_operand" "")
1372 (match_operand:V8QI 1 "nonimmediate_operand" ""))
1374 (match_operand:V8QI 2 "nonimmediate_operand" "")))
1375 (const_vector:V8HI [(const_int 1) (const_int 1)
1376 (const_int 1) (const_int 1)
1377 (const_int 1) (const_int 1)
1378 (const_int 1) (const_int 1)]))
1380 "TARGET_SSE || TARGET_3DNOW"
1381 "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
1383 (define_insn "*mmx_uavgv8qi3"
1384 [(set (match_operand:V8QI 0 "register_operand" "=y")
1390 (match_operand:V8QI 1 "nonimmediate_operand" "%0"))
1392 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))
1393 (const_vector:V8HI [(const_int 1) (const_int 1)
1394 (const_int 1) (const_int 1)
1395 (const_int 1) (const_int 1)
1396 (const_int 1) (const_int 1)]))
1398 "(TARGET_SSE || TARGET_3DNOW)
1399 && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
1401 /* These two instructions have the same operation, but their encoding
1402 is different. Prefer the one that is de facto standard. */
1403 if (TARGET_SSE || TARGET_3DNOW_A)
1404 return "pavgb\t{%2, %0|%0, %2}";
1406 return "pavgusb\t{%2, %0|%0, %2}";
1408 [(set_attr "type" "mmxshft")
1409 (set_attr "mode" "DI")])
1411 (define_expand "mmx_uavgv4hi3"
1412 [(set (match_operand:V4HI 0 "register_operand" "")
1418 (match_operand:V4HI 1 "nonimmediate_operand" ""))
1420 (match_operand:V4HI 2 "nonimmediate_operand" "")))
1421 (const_vector:V4SI [(const_int 1) (const_int 1)
1422 (const_int 1) (const_int 1)]))
1424 "TARGET_SSE || TARGET_3DNOW_A"
1425 "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
1427 (define_insn "*mmx_uavgv4hi3"
1428 [(set (match_operand:V4HI 0 "register_operand" "=y")
1434 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
1436 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
1437 (const_vector:V4SI [(const_int 1) (const_int 1)
1438 (const_int 1) (const_int 1)]))
1440 "(TARGET_SSE || TARGET_3DNOW_A)
1441 && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
1442 "pavgw\t{%2, %0|%0, %2}"
1443 [(set_attr "type" "mmxshft")
1444 (set_attr "mode" "DI")])
1446 (define_insn "mmx_psadbw"
1447 [(set (match_operand:V1DI 0 "register_operand" "=y")
1448 (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0")
1449 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
1451 "TARGET_SSE || TARGET_3DNOW_A"
1452 "psadbw\t{%2, %0|%0, %2}"
1453 [(set_attr "type" "mmxshft")
1454 (set_attr "mode" "DI")])
1456 (define_insn "mmx_pmovmskb"
1457 [(set (match_operand:SI 0 "register_operand" "=r")
1458 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
1460 "TARGET_SSE || TARGET_3DNOW_A"
1461 "pmovmskb\t{%1, %0|%0, %1}"
1462 [(set_attr "type" "mmxcvt")
1463 (set_attr "mode" "DI")])
1465 (define_expand "mmx_maskmovq"
1466 [(set (match_operand:V8QI 0 "memory_operand" "")
1467 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
1468 (match_operand:V8QI 2 "register_operand" "")
1471 "TARGET_SSE || TARGET_3DNOW_A"
1474 (define_insn "*mmx_maskmovq"
1475 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
1476 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1477 (match_operand:V8QI 2 "register_operand" "y")
1478 (mem:V8QI (match_dup 0))]
1480 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
1481 ;; @@@ check ordering of operands in intel/nonintel syntax
1482 "maskmovq\t{%2, %1|%1, %2}"
1483 [(set_attr "type" "mmxcvt")
1484 (set_attr "mode" "DI")])
1486 (define_insn "*mmx_maskmovq_rex"
1487 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
1488 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1489 (match_operand:V8QI 2 "register_operand" "y")
1490 (mem:V8QI (match_dup 0))]
1492 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
1493 ;; @@@ check ordering of operands in intel/nonintel syntax
1494 "maskmovq\t{%2, %1|%1, %2}"
1495 [(set_attr "type" "mmxcvt")
1496 (set_attr "mode" "DI")])
1498 (define_insn "mmx_emms"
1499 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
1500 (clobber (reg:XF 8))
1501 (clobber (reg:XF 9))
1502 (clobber (reg:XF 10))
1503 (clobber (reg:XF 11))
1504 (clobber (reg:XF 12))
1505 (clobber (reg:XF 13))
1506 (clobber (reg:XF 14))
1507 (clobber (reg:XF 15))
1508 (clobber (reg:DI 29))
1509 (clobber (reg:DI 30))
1510 (clobber (reg:DI 31))
1511 (clobber (reg:DI 32))
1512 (clobber (reg:DI 33))
1513 (clobber (reg:DI 34))
1514 (clobber (reg:DI 35))
1515 (clobber (reg:DI 36))]
1518 [(set_attr "type" "mmx")
1519 (set_attr "memory" "unknown")])
1521 (define_insn "mmx_femms"
1522 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
1523 (clobber (reg:XF 8))
1524 (clobber (reg:XF 9))
1525 (clobber (reg:XF 10))
1526 (clobber (reg:XF 11))
1527 (clobber (reg:XF 12))
1528 (clobber (reg:XF 13))
1529 (clobber (reg:XF 14))
1530 (clobber (reg:XF 15))
1531 (clobber (reg:DI 29))
1532 (clobber (reg:DI 30))
1533 (clobber (reg:DI 31))
1534 (clobber (reg:DI 32))
1535 (clobber (reg:DI 33))
1536 (clobber (reg:DI 34))
1537 (clobber (reg:DI 35))
1538 (clobber (reg:DI 36))]
1541 [(set_attr "type" "mmx")
1542 (set_attr "memory" "none")])