1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
73 (UNSPEC_TLS_LD_BASE 17)
75 ; Other random patterns
85 ; For SSE/MMX support:
96 (UNSPEC_NOP 45) ; prevents combiner cleverness
123 ; x87 Double output FP
124 (UNSPEC_SINCOS_COS 80)
125 (UNSPEC_SINCOS_SIN 81)
128 (UNSPEC_XTRACT_FRACT 84)
129 (UNSPEC_XTRACT_EXP 85)
130 (UNSPEC_FSCALE_FRACT 86)
131 (UNSPEC_FSCALE_EXP 87)
138 (UNSPEC_FRNDINT_FLOOR 96)
139 (UNSPEC_FRNDINT_CEIL 97)
140 (UNSPEC_FRNDINT_TRUNC 98)
141 (UNSPEC_FRNDINT_MASK_PM 99)
146 (UNSPEC_EH_RETURN 76)
150 [(UNSPECV_BLOCKAGE 0)
151 (UNSPECV_STACK_PROBE 10)
162 ;; Registers by name.
171 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
174 ;; In C guard expressions, put expressions which may be compile-time
175 ;; constants first. This allows for better optimization. For
176 ;; example, write "TARGET_64BIT && reload_completed", not
177 ;; "reload_completed && TARGET_64BIT".
180 ;; Processor type. This attribute must exactly match the processor_type
181 ;; enumeration in i386.h.
182 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
183 (const (symbol_ref "ix86_tune")))
185 ;; A basic instruction type. Refinements due to arguments to be
186 ;; provided in other attributes.
189 alu,alu1,negnot,imov,imovx,lea,
190 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
191 icmp,test,ibr,setcc,icmov,
192 push,pop,call,callv,leave,
194 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
195 sselog,sseiadd,sseishft,sseimul,
196 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
197 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
198 (const_string "other"))
200 ;; Main data type used by the insn
202 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
203 (const_string "unknown"))
205 ;; The CPU unit operations uses.
206 (define_attr "unit" "integer,i387,sse,mmx,unknown"
207 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
208 (const_string "i387")
209 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
210 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
212 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
214 (eq_attr "type" "other")
215 (const_string "unknown")]
216 (const_string "integer")))
218 ;; The (bounding maximum) length of an instruction immediate.
219 (define_attr "length_immediate" ""
220 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
222 (eq_attr "unit" "i387,sse,mmx")
224 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
226 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
227 (eq_attr "type" "imov,test")
228 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
229 (eq_attr "type" "call")
230 (if_then_else (match_operand 0 "constant_call_address_operand" "")
233 (eq_attr "type" "callv")
234 (if_then_else (match_operand 1 "constant_call_address_operand" "")
237 ;; We don't know the size before shorten_branches. Expect
238 ;; the instruction to fit for better scheduling.
239 (eq_attr "type" "ibr")
242 (symbol_ref "/* Update immediate_length and other attributes! */
245 ;; The (bounding maximum) length of an instruction address.
246 (define_attr "length_address" ""
247 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
249 (and (eq_attr "type" "call")
250 (match_operand 0 "constant_call_address_operand" ""))
252 (and (eq_attr "type" "callv")
253 (match_operand 1 "constant_call_address_operand" ""))
256 (symbol_ref "ix86_attr_length_address_default (insn)")))
258 ;; Set when length prefix is used.
259 (define_attr "prefix_data16" ""
260 (if_then_else (ior (eq_attr "mode" "HI")
261 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
265 ;; Set when string REP prefix is used.
266 (define_attr "prefix_rep" ""
267 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
271 ;; Set when 0f opcode prefix is used.
272 (define_attr "prefix_0f" ""
274 (ior (eq_attr "type" "imovx,setcc,icmov")
275 (eq_attr "unit" "sse,mmx"))
279 ;; Set when REX opcode prefix is used.
280 (define_attr "prefix_rex" ""
281 (cond [(and (eq_attr "mode" "DI")
282 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
284 (and (eq_attr "mode" "QI")
285 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
288 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
294 ;; Set when modrm byte is used.
295 (define_attr "modrm" ""
296 (cond [(eq_attr "type" "str,cld,leave")
298 (eq_attr "unit" "i387")
300 (and (eq_attr "type" "incdec")
301 (ior (match_operand:SI 1 "register_operand" "")
302 (match_operand:HI 1 "register_operand" "")))
304 (and (eq_attr "type" "push")
305 (not (match_operand 1 "memory_operand" "")))
307 (and (eq_attr "type" "pop")
308 (not (match_operand 0 "memory_operand" "")))
310 (and (eq_attr "type" "imov")
311 (and (match_operand 0 "register_operand" "")
312 (match_operand 1 "immediate_operand" "")))
314 (and (eq_attr "type" "call")
315 (match_operand 0 "constant_call_address_operand" ""))
317 (and (eq_attr "type" "callv")
318 (match_operand 1 "constant_call_address_operand" ""))
323 ;; The (bounding maximum) length of an instruction in bytes.
324 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
325 ;; Later we may want to split them and compute proper length as for
327 (define_attr "length" ""
328 (cond [(eq_attr "type" "other,multi,fistp,frndint")
330 (eq_attr "type" "fcmp")
332 (eq_attr "unit" "i387")
334 (plus (attr "prefix_data16")
335 (attr "length_address")))]
336 (plus (plus (attr "modrm")
337 (plus (attr "prefix_0f")
338 (plus (attr "prefix_rex")
340 (plus (attr "prefix_rep")
341 (plus (attr "prefix_data16")
342 (plus (attr "length_immediate")
343 (attr "length_address")))))))
345 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
346 ;; `store' if there is a simple memory reference therein, or `unknown'
347 ;; if the instruction is complex.
349 (define_attr "memory" "none,load,store,both,unknown"
350 (cond [(eq_attr "type" "other,multi,str")
351 (const_string "unknown")
352 (eq_attr "type" "lea,fcmov,fpspc,cld")
353 (const_string "none")
354 (eq_attr "type" "fistp,leave")
355 (const_string "both")
356 (eq_attr "type" "frndint")
357 (const_string "load")
358 (eq_attr "type" "push")
359 (if_then_else (match_operand 1 "memory_operand" "")
360 (const_string "both")
361 (const_string "store"))
362 (eq_attr "type" "pop")
363 (if_then_else (match_operand 0 "memory_operand" "")
364 (const_string "both")
365 (const_string "load"))
366 (eq_attr "type" "setcc")
367 (if_then_else (match_operand 0 "memory_operand" "")
368 (const_string "store")
369 (const_string "none"))
370 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
371 (if_then_else (ior (match_operand 0 "memory_operand" "")
372 (match_operand 1 "memory_operand" ""))
373 (const_string "load")
374 (const_string "none"))
375 (eq_attr "type" "ibr")
376 (if_then_else (match_operand 0 "memory_operand" "")
377 (const_string "load")
378 (const_string "none"))
379 (eq_attr "type" "call")
380 (if_then_else (match_operand 0 "constant_call_address_operand" "")
381 (const_string "none")
382 (const_string "load"))
383 (eq_attr "type" "callv")
384 (if_then_else (match_operand 1 "constant_call_address_operand" "")
385 (const_string "none")
386 (const_string "load"))
387 (and (eq_attr "type" "alu1,negnot,ishift1")
388 (match_operand 1 "memory_operand" ""))
389 (const_string "both")
390 (and (match_operand 0 "memory_operand" "")
391 (match_operand 1 "memory_operand" ""))
392 (const_string "both")
393 (match_operand 0 "memory_operand" "")
394 (const_string "store")
395 (match_operand 1 "memory_operand" "")
396 (const_string "load")
398 "!alu1,negnot,ishift1,
399 imov,imovx,icmp,test,
401 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
402 mmx,mmxmov,mmxcmp,mmxcvt")
403 (match_operand 2 "memory_operand" ""))
404 (const_string "load")
405 (and (eq_attr "type" "icmov")
406 (match_operand 3 "memory_operand" ""))
407 (const_string "load")
409 (const_string "none")))
411 ;; Indicates if an instruction has both an immediate and a displacement.
413 (define_attr "imm_disp" "false,true,unknown"
414 (cond [(eq_attr "type" "other,multi")
415 (const_string "unknown")
416 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
417 (and (match_operand 0 "memory_displacement_operand" "")
418 (match_operand 1 "immediate_operand" "")))
419 (const_string "true")
420 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
421 (and (match_operand 0 "memory_displacement_operand" "")
422 (match_operand 2 "immediate_operand" "")))
423 (const_string "true")
425 (const_string "false")))
427 ;; Indicates if an FP operation has an integer source.
429 (define_attr "fp_int_src" "false,true"
430 (const_string "false"))
432 ;; Defines rounding mode of an FP operation.
434 (define_attr "i387_cw" "floor,ceil,trunc,mask_pm,uninitialized,any"
435 (const_string "any"))
437 ;; Describe a user's asm statement.
438 (define_asm_attributes
439 [(set_attr "length" "128")
440 (set_attr "type" "multi")])
442 ;; Scheduling descriptions
444 (include "pentium.md")
447 (include "athlon.md")
450 ;; Operand and operator predicates
452 (include "predicates.md")
455 ;; Compare instructions.
457 ;; All compare insns have expanders that save the operands away without
458 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
459 ;; after the cmp) will actually emit the cmpM.
461 (define_expand "cmpdi"
462 [(set (reg:CC FLAGS_REG)
463 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
464 (match_operand:DI 1 "x86_64_general_operand" "")))]
467 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
468 operands[0] = force_reg (DImode, operands[0]);
469 ix86_compare_op0 = operands[0];
470 ix86_compare_op1 = operands[1];
474 (define_expand "cmpsi"
475 [(set (reg:CC FLAGS_REG)
476 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
477 (match_operand:SI 1 "general_operand" "")))]
480 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
481 operands[0] = force_reg (SImode, operands[0]);
482 ix86_compare_op0 = operands[0];
483 ix86_compare_op1 = operands[1];
487 (define_expand "cmphi"
488 [(set (reg:CC FLAGS_REG)
489 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
490 (match_operand:HI 1 "general_operand" "")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
494 operands[0] = force_reg (HImode, operands[0]);
495 ix86_compare_op0 = operands[0];
496 ix86_compare_op1 = operands[1];
500 (define_expand "cmpqi"
501 [(set (reg:CC FLAGS_REG)
502 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
503 (match_operand:QI 1 "general_operand" "")))]
506 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
507 operands[0] = force_reg (QImode, operands[0]);
508 ix86_compare_op0 = operands[0];
509 ix86_compare_op1 = operands[1];
513 (define_insn "cmpdi_ccno_1_rex64"
514 [(set (reg FLAGS_REG)
515 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
516 (match_operand:DI 1 "const0_operand" "n,n")))]
517 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
519 test{q}\t{%0, %0|%0, %0}
520 cmp{q}\t{%1, %0|%0, %1}"
521 [(set_attr "type" "test,icmp")
522 (set_attr "length_immediate" "0,1")
523 (set_attr "mode" "DI")])
525 (define_insn "*cmpdi_minus_1_rex64"
526 [(set (reg FLAGS_REG)
527 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
528 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
530 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
531 "cmp{q}\t{%1, %0|%0, %1}"
532 [(set_attr "type" "icmp")
533 (set_attr "mode" "DI")])
535 (define_expand "cmpdi_1_rex64"
536 [(set (reg:CC FLAGS_REG)
537 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
538 (match_operand:DI 1 "general_operand" "")))]
542 (define_insn "cmpdi_1_insn_rex64"
543 [(set (reg FLAGS_REG)
544 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
545 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
546 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
547 "cmp{q}\t{%1, %0|%0, %1}"
548 [(set_attr "type" "icmp")
549 (set_attr "mode" "DI")])
552 (define_insn "*cmpsi_ccno_1"
553 [(set (reg FLAGS_REG)
554 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
555 (match_operand:SI 1 "const0_operand" "n,n")))]
556 "ix86_match_ccmode (insn, CCNOmode)"
558 test{l}\t{%0, %0|%0, %0}
559 cmp{l}\t{%1, %0|%0, %1}"
560 [(set_attr "type" "test,icmp")
561 (set_attr "length_immediate" "0,1")
562 (set_attr "mode" "SI")])
564 (define_insn "*cmpsi_minus_1"
565 [(set (reg FLAGS_REG)
566 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
567 (match_operand:SI 1 "general_operand" "ri,mr"))
569 "ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{l}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "SI")])
574 (define_expand "cmpsi_1"
575 [(set (reg:CC FLAGS_REG)
576 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
577 (match_operand:SI 1 "general_operand" "ri,mr")))]
581 (define_insn "*cmpsi_1_insn"
582 [(set (reg FLAGS_REG)
583 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
584 (match_operand:SI 1 "general_operand" "ri,mr")))]
585 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
586 && ix86_match_ccmode (insn, CCmode)"
587 "cmp{l}\t{%1, %0|%0, %1}"
588 [(set_attr "type" "icmp")
589 (set_attr "mode" "SI")])
591 (define_insn "*cmphi_ccno_1"
592 [(set (reg FLAGS_REG)
593 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
594 (match_operand:HI 1 "const0_operand" "n,n")))]
595 "ix86_match_ccmode (insn, CCNOmode)"
597 test{w}\t{%0, %0|%0, %0}
598 cmp{w}\t{%1, %0|%0, %1}"
599 [(set_attr "type" "test,icmp")
600 (set_attr "length_immediate" "0,1")
601 (set_attr "mode" "HI")])
603 (define_insn "*cmphi_minus_1"
604 [(set (reg FLAGS_REG)
605 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
606 (match_operand:HI 1 "general_operand" "ri,mr"))
608 "ix86_match_ccmode (insn, CCGOCmode)"
609 "cmp{w}\t{%1, %0|%0, %1}"
610 [(set_attr "type" "icmp")
611 (set_attr "mode" "HI")])
613 (define_insn "*cmphi_1"
614 [(set (reg FLAGS_REG)
615 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
616 (match_operand:HI 1 "general_operand" "ri,mr")))]
617 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
618 && ix86_match_ccmode (insn, CCmode)"
619 "cmp{w}\t{%1, %0|%0, %1}"
620 [(set_attr "type" "icmp")
621 (set_attr "mode" "HI")])
623 (define_insn "*cmpqi_ccno_1"
624 [(set (reg FLAGS_REG)
625 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
626 (match_operand:QI 1 "const0_operand" "n,n")))]
627 "ix86_match_ccmode (insn, CCNOmode)"
629 test{b}\t{%0, %0|%0, %0}
630 cmp{b}\t{$0, %0|%0, 0}"
631 [(set_attr "type" "test,icmp")
632 (set_attr "length_immediate" "0,1")
633 (set_attr "mode" "QI")])
635 (define_insn "*cmpqi_1"
636 [(set (reg FLAGS_REG)
637 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
638 (match_operand:QI 1 "general_operand" "qi,mq")))]
639 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
640 && ix86_match_ccmode (insn, CCmode)"
641 "cmp{b}\t{%1, %0|%0, %1}"
642 [(set_attr "type" "icmp")
643 (set_attr "mode" "QI")])
645 (define_insn "*cmpqi_minus_1"
646 [(set (reg FLAGS_REG)
647 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
648 (match_operand:QI 1 "general_operand" "qi,mq"))
650 "ix86_match_ccmode (insn, CCGOCmode)"
651 "cmp{b}\t{%1, %0|%0, %1}"
652 [(set_attr "type" "icmp")
653 (set_attr "mode" "QI")])
655 (define_insn "*cmpqi_ext_1"
656 [(set (reg FLAGS_REG)
658 (match_operand:QI 0 "general_operand" "Qm")
661 (match_operand 1 "ext_register_operand" "Q")
664 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
665 "cmp{b}\t{%h1, %0|%0, %h1}"
666 [(set_attr "type" "icmp")
667 (set_attr "mode" "QI")])
669 (define_insn "*cmpqi_ext_1_rex64"
670 [(set (reg FLAGS_REG)
672 (match_operand:QI 0 "register_operand" "Q")
675 (match_operand 1 "ext_register_operand" "Q")
678 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
679 "cmp{b}\t{%h1, %0|%0, %h1}"
680 [(set_attr "type" "icmp")
681 (set_attr "mode" "QI")])
683 (define_insn "*cmpqi_ext_2"
684 [(set (reg FLAGS_REG)
688 (match_operand 0 "ext_register_operand" "Q")
691 (match_operand:QI 1 "const0_operand" "n")))]
692 "ix86_match_ccmode (insn, CCNOmode)"
694 [(set_attr "type" "test")
695 (set_attr "length_immediate" "0")
696 (set_attr "mode" "QI")])
698 (define_expand "cmpqi_ext_3"
699 [(set (reg:CC FLAGS_REG)
703 (match_operand 0 "ext_register_operand" "")
706 (match_operand:QI 1 "general_operand" "")))]
710 (define_insn "cmpqi_ext_3_insn"
711 [(set (reg FLAGS_REG)
715 (match_operand 0 "ext_register_operand" "Q")
718 (match_operand:QI 1 "general_operand" "Qmn")))]
719 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
720 "cmp{b}\t{%1, %h0|%h0, %1}"
721 [(set_attr "type" "icmp")
722 (set_attr "mode" "QI")])
724 (define_insn "cmpqi_ext_3_insn_rex64"
725 [(set (reg FLAGS_REG)
729 (match_operand 0 "ext_register_operand" "Q")
732 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
733 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
734 "cmp{b}\t{%1, %h0|%h0, %1}"
735 [(set_attr "type" "icmp")
736 (set_attr "mode" "QI")])
738 (define_insn "*cmpqi_ext_4"
739 [(set (reg FLAGS_REG)
743 (match_operand 0 "ext_register_operand" "Q")
748 (match_operand 1 "ext_register_operand" "Q")
751 "ix86_match_ccmode (insn, CCmode)"
752 "cmp{b}\t{%h1, %h0|%h0, %h1}"
753 [(set_attr "type" "icmp")
754 (set_attr "mode" "QI")])
756 ;; These implement float point compares.
757 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
758 ;; which would allow mix and match FP modes on the compares. Which is what
759 ;; the old patterns did, but with many more of them.
761 (define_expand "cmpxf"
762 [(set (reg:CC FLAGS_REG)
763 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
764 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
767 ix86_compare_op0 = operands[0];
768 ix86_compare_op1 = operands[1];
772 (define_expand "cmpdf"
773 [(set (reg:CC FLAGS_REG)
774 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
775 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
776 "TARGET_80387 || TARGET_SSE2"
778 ix86_compare_op0 = operands[0];
779 ix86_compare_op1 = operands[1];
783 (define_expand "cmpsf"
784 [(set (reg:CC FLAGS_REG)
785 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
786 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
787 "TARGET_80387 || TARGET_SSE"
789 ix86_compare_op0 = operands[0];
790 ix86_compare_op1 = operands[1];
794 ;; FP compares, step 1:
795 ;; Set the FP condition codes.
797 ;; CCFPmode compare with exceptions
798 ;; CCFPUmode compare with no exceptions
800 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
801 ;; used to manage the reg stack popping would not be preserved.
803 (define_insn "*cmpfp_0_sf"
804 [(set (match_operand:HI 0 "register_operand" "=a")
807 (match_operand:SF 1 "register_operand" "f")
808 (match_operand:SF 2 "const0_operand" "X"))]
811 "* return output_fp_compare (insn, operands, 0, 0);"
812 [(set_attr "type" "multi")
813 (set_attr "mode" "SF")])
815 (define_insn "*cmpfp_0_df"
816 [(set (match_operand:HI 0 "register_operand" "=a")
819 (match_operand:DF 1 "register_operand" "f")
820 (match_operand:DF 2 "const0_operand" "X"))]
823 "* return output_fp_compare (insn, operands, 0, 0);"
824 [(set_attr "type" "multi")
825 (set_attr "mode" "DF")])
827 (define_insn "*cmpfp_0_xf"
828 [(set (match_operand:HI 0 "register_operand" "=a")
831 (match_operand:XF 1 "register_operand" "f")
832 (match_operand:XF 2 "const0_operand" "X"))]
835 "* return output_fp_compare (insn, operands, 0, 0);"
836 [(set_attr "type" "multi")
837 (set_attr "mode" "XF")])
839 (define_insn "*cmpfp_sf"
840 [(set (match_operand:HI 0 "register_operand" "=a")
843 (match_operand:SF 1 "register_operand" "f")
844 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
847 "* return output_fp_compare (insn, operands, 0, 0);"
848 [(set_attr "type" "multi")
849 (set_attr "mode" "SF")])
851 (define_insn "*cmpfp_df"
852 [(set (match_operand:HI 0 "register_operand" "=a")
855 (match_operand:DF 1 "register_operand" "f")
856 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
859 "* return output_fp_compare (insn, operands, 0, 0);"
860 [(set_attr "type" "multi")
861 (set_attr "mode" "DF")])
863 (define_insn "*cmpfp_xf"
864 [(set (match_operand:HI 0 "register_operand" "=a")
867 (match_operand:XF 1 "register_operand" "f")
868 (match_operand:XF 2 "register_operand" "f"))]
871 "* return output_fp_compare (insn, operands, 0, 0);"
872 [(set_attr "type" "multi")
873 (set_attr "mode" "XF")])
875 (define_insn "*cmpfp_u"
876 [(set (match_operand:HI 0 "register_operand" "=a")
879 (match_operand 1 "register_operand" "f")
880 (match_operand 2 "register_operand" "f"))]
883 && FLOAT_MODE_P (GET_MODE (operands[1]))
884 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
885 "* return output_fp_compare (insn, operands, 0, 1);"
886 [(set_attr "type" "multi")
888 (cond [(match_operand:SF 1 "" "")
890 (match_operand:DF 1 "" "")
893 (const_string "XF")))])
895 (define_insn "*cmpfp_si"
896 [(set (match_operand:HI 0 "register_operand" "=a")
899 (match_operand 1 "register_operand" "f")
900 (match_operator 3 "float_operator"
901 [(match_operand:SI 2 "memory_operand" "m")]))]
903 "TARGET_80387 && TARGET_USE_FIOP
904 && FLOAT_MODE_P (GET_MODE (operands[1]))
905 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
906 "* return output_fp_compare (insn, operands, 0, 0);"
907 [(set_attr "type" "multi")
908 (set_attr "fp_int_src" "true")
909 (set_attr "mode" "SI")])
911 ;; FP compares, step 2
912 ;; Move the fpsw to ax.
914 (define_insn "x86_fnstsw_1"
915 [(set (match_operand:HI 0 "register_operand" "=a")
916 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
919 [(set_attr "length" "2")
920 (set_attr "mode" "SI")
921 (set_attr "unit" "i387")])
923 ;; FP compares, step 3
924 ;; Get ax into flags, general case.
926 (define_insn "x86_sahf_1"
927 [(set (reg:CC FLAGS_REG)
928 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
931 [(set_attr "length" "1")
932 (set_attr "athlon_decode" "vector")
933 (set_attr "mode" "SI")])
935 ;; Pentium Pro can do steps 1 through 3 in one go.
937 (define_insn "*cmpfp_i"
938 [(set (reg:CCFP FLAGS_REG)
939 (compare:CCFP (match_operand 0 "register_operand" "f")
940 (match_operand 1 "register_operand" "f")))]
941 "TARGET_80387 && TARGET_CMOVE
942 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
943 && FLOAT_MODE_P (GET_MODE (operands[0]))
944 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
945 "* return output_fp_compare (insn, operands, 1, 0);"
946 [(set_attr "type" "fcmp")
948 (cond [(match_operand:SF 1 "" "")
950 (match_operand:DF 1 "" "")
953 (const_string "XF")))
954 (set_attr "athlon_decode" "vector")])
956 (define_insn "*cmpfp_i_sse"
957 [(set (reg:CCFP FLAGS_REG)
958 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
959 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
961 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
962 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
963 "* return output_fp_compare (insn, operands, 1, 0);"
964 [(set_attr "type" "fcmp,ssecomi")
966 (if_then_else (match_operand:SF 1 "" "")
968 (const_string "DF")))
969 (set_attr "athlon_decode" "vector")])
971 (define_insn "*cmpfp_i_sse_only"
972 [(set (reg:CCFP FLAGS_REG)
973 (compare:CCFP (match_operand 0 "register_operand" "x")
974 (match_operand 1 "nonimmediate_operand" "xm")))]
975 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
976 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
977 "* return output_fp_compare (insn, operands, 1, 0);"
978 [(set_attr "type" "ssecomi")
980 (if_then_else (match_operand:SF 1 "" "")
982 (const_string "DF")))
983 (set_attr "athlon_decode" "vector")])
985 (define_insn "*cmpfp_iu"
986 [(set (reg:CCFPU FLAGS_REG)
987 (compare:CCFPU (match_operand 0 "register_operand" "f")
988 (match_operand 1 "register_operand" "f")))]
989 "TARGET_80387 && TARGET_CMOVE
990 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
991 && FLOAT_MODE_P (GET_MODE (operands[0]))
992 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
993 "* return output_fp_compare (insn, operands, 1, 1);"
994 [(set_attr "type" "fcmp")
996 (cond [(match_operand:SF 1 "" "")
998 (match_operand:DF 1 "" "")
1001 (const_string "XF")))
1002 (set_attr "athlon_decode" "vector")])
1004 (define_insn "*cmpfp_iu_sse"
1005 [(set (reg:CCFPU FLAGS_REG)
1006 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1007 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1009 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1010 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1011 "* return output_fp_compare (insn, operands, 1, 1);"
1012 [(set_attr "type" "fcmp,ssecomi")
1014 (if_then_else (match_operand:SF 1 "" "")
1016 (const_string "DF")))
1017 (set_attr "athlon_decode" "vector")])
1019 (define_insn "*cmpfp_iu_sse_only"
1020 [(set (reg:CCFPU FLAGS_REG)
1021 (compare:CCFPU (match_operand 0 "register_operand" "x")
1022 (match_operand 1 "nonimmediate_operand" "xm")))]
1023 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1024 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1025 "* return output_fp_compare (insn, operands, 1, 1);"
1026 [(set_attr "type" "ssecomi")
1028 (if_then_else (match_operand:SF 1 "" "")
1030 (const_string "DF")))
1031 (set_attr "athlon_decode" "vector")])
1033 ;; Move instructions.
1035 ;; General case of fullword move.
1037 (define_expand "movsi"
1038 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1039 (match_operand:SI 1 "general_operand" ""))]
1041 "ix86_expand_move (SImode, operands); DONE;")
1043 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1046 ;; %%% We don't use a post-inc memory reference because x86 is not a
1047 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1048 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1049 ;; targets without our curiosities, and it is just as easy to represent
1050 ;; this differently.
1052 (define_insn "*pushsi2"
1053 [(set (match_operand:SI 0 "push_operand" "=<")
1054 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1057 [(set_attr "type" "push")
1058 (set_attr "mode" "SI")])
1060 ;; For 64BIT abi we always round up to 8 bytes.
1061 (define_insn "*pushsi2_rex64"
1062 [(set (match_operand:SI 0 "push_operand" "=X")
1063 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1066 [(set_attr "type" "push")
1067 (set_attr "mode" "SI")])
1069 (define_insn "*pushsi2_prologue"
1070 [(set (match_operand:SI 0 "push_operand" "=<")
1071 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1072 (clobber (mem:BLK (scratch)))]
1075 [(set_attr "type" "push")
1076 (set_attr "mode" "SI")])
1078 (define_insn "*popsi1_epilogue"
1079 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1080 (mem:SI (reg:SI SP_REG)))
1081 (set (reg:SI SP_REG)
1082 (plus:SI (reg:SI SP_REG) (const_int 4)))
1083 (clobber (mem:BLK (scratch)))]
1086 [(set_attr "type" "pop")
1087 (set_attr "mode" "SI")])
1089 (define_insn "popsi1"
1090 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1091 (mem:SI (reg:SI SP_REG)))
1092 (set (reg:SI SP_REG)
1093 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1096 [(set_attr "type" "pop")
1097 (set_attr "mode" "SI")])
1099 (define_insn "*movsi_xor"
1100 [(set (match_operand:SI 0 "register_operand" "=r")
1101 (match_operand:SI 1 "const0_operand" "i"))
1102 (clobber (reg:CC FLAGS_REG))]
1103 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1104 "xor{l}\t{%0, %0|%0, %0}"
1105 [(set_attr "type" "alu1")
1106 (set_attr "mode" "SI")
1107 (set_attr "length_immediate" "0")])
1109 (define_insn "*movsi_or"
1110 [(set (match_operand:SI 0 "register_operand" "=r")
1111 (match_operand:SI 1 "immediate_operand" "i"))
1112 (clobber (reg:CC FLAGS_REG))]
1114 && operands[1] == constm1_rtx
1115 && (TARGET_PENTIUM || optimize_size)"
1117 operands[1] = constm1_rtx;
1118 return "or{l}\t{%1, %0|%0, %1}";
1120 [(set_attr "type" "alu1")
1121 (set_attr "mode" "SI")
1122 (set_attr "length_immediate" "1")])
1124 (define_insn "*movsi_1"
1125 [(set (match_operand:SI 0 "nonimmediate_operand"
1126 "=r ,m ,!*y,!rm,!*y,!*x,!rm,!*x")
1127 (match_operand:SI 1 "general_operand"
1128 "rinm,rin,*y ,*y ,rm ,*x ,*x ,rm"))]
1129 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1130 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1132 switch (get_attr_type (insn))
1135 if (get_attr_mode (insn) == MODE_TI)
1136 return "movdqa\t{%1, %0|%0, %1}";
1137 return "movd\t{%1, %0|%0, %1}";
1140 if (get_attr_mode (insn) == MODE_DI)
1141 return "movq\t{%1, %0|%0, %1}";
1142 return "movd\t{%1, %0|%0, %1}";
1145 return "lea{l}\t{%1, %0|%0, %1}";
1148 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1150 return "mov{l}\t{%1, %0|%0, %1}";
1154 (cond [(eq_attr "alternative" "2,3,4")
1155 (const_string "mmxmov")
1156 (eq_attr "alternative" "5,6,7")
1157 (const_string "ssemov")
1158 (and (ne (symbol_ref "flag_pic") (const_int 0))
1159 (match_operand:SI 1 "symbolic_operand" ""))
1160 (const_string "lea")
1162 (const_string "imov")))
1163 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1165 (define_insn "*movsi_1_nointernunit"
1166 [(set (match_operand:SI 0 "nonimmediate_operand"
1167 "=r ,m ,!*y,!m,!*y,!*x,!m,!*x")
1168 (match_operand:SI 1 "general_operand"
1169 "rinm,rin,*y ,*y,m ,*x ,*x,m"))]
1170 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1171 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1173 switch (get_attr_type (insn))
1176 if (get_attr_mode (insn) == MODE_TI)
1177 return "movdqa\t{%1, %0|%0, %1}";
1178 return "movd\t{%1, %0|%0, %1}";
1181 if (get_attr_mode (insn) == MODE_DI)
1182 return "movq\t{%1, %0|%0, %1}";
1183 return "movd\t{%1, %0|%0, %1}";
1186 return "lea{l}\t{%1, %0|%0, %1}";
1189 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1191 return "mov{l}\t{%1, %0|%0, %1}";
1195 (cond [(eq_attr "alternative" "2,3,4")
1196 (const_string "mmxmov")
1197 (eq_attr "alternative" "5,6,7")
1198 (const_string "ssemov")
1199 (and (ne (symbol_ref "flag_pic") (const_int 0))
1200 (match_operand:SI 1 "symbolic_operand" ""))
1201 (const_string "lea")
1203 (const_string "imov")))
1204 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1206 ;; Stores and loads of ax to arbitrary constant address.
1207 ;; We fake an second form of instruction to force reload to load address
1208 ;; into register when rax is not available
1209 (define_insn "*movabssi_1_rex64"
1210 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1211 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1212 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1214 movabs{l}\t{%1, %P0|%P0, %1}
1215 mov{l}\t{%1, %a0|%a0, %1}"
1216 [(set_attr "type" "imov")
1217 (set_attr "modrm" "0,*")
1218 (set_attr "length_address" "8,0")
1219 (set_attr "length_immediate" "0,*")
1220 (set_attr "memory" "store")
1221 (set_attr "mode" "SI")])
1223 (define_insn "*movabssi_2_rex64"
1224 [(set (match_operand:SI 0 "register_operand" "=a,r")
1225 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1226 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1228 movabs{l}\t{%P1, %0|%0, %P1}
1229 mov{l}\t{%a1, %0|%0, %a1}"
1230 [(set_attr "type" "imov")
1231 (set_attr "modrm" "0,*")
1232 (set_attr "length_address" "8,0")
1233 (set_attr "length_immediate" "0")
1234 (set_attr "memory" "load")
1235 (set_attr "mode" "SI")])
1237 (define_insn "*swapsi"
1238 [(set (match_operand:SI 0 "register_operand" "+r")
1239 (match_operand:SI 1 "register_operand" "+r"))
1244 [(set_attr "type" "imov")
1245 (set_attr "mode" "SI")
1246 (set_attr "pent_pair" "np")
1247 (set_attr "athlon_decode" "vector")])
1249 (define_expand "movhi"
1250 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1251 (match_operand:HI 1 "general_operand" ""))]
1253 "ix86_expand_move (HImode, operands); DONE;")
1255 (define_insn "*pushhi2"
1256 [(set (match_operand:HI 0 "push_operand" "=<,<")
1257 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1260 push{w}\t{|WORD PTR }%1
1262 [(set_attr "type" "push")
1263 (set_attr "mode" "HI")])
1265 ;; For 64BIT abi we always round up to 8 bytes.
1266 (define_insn "*pushhi2_rex64"
1267 [(set (match_operand:HI 0 "push_operand" "=X")
1268 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1271 [(set_attr "type" "push")
1272 (set_attr "mode" "QI")])
1274 (define_insn "*movhi_1"
1275 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1276 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1277 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1279 switch (get_attr_type (insn))
1282 /* movzwl is faster than movw on p2 due to partial word stalls,
1283 though not as fast as an aligned movl. */
1284 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1286 if (get_attr_mode (insn) == MODE_SI)
1287 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1289 return "mov{w}\t{%1, %0|%0, %1}";
1293 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1294 (const_string "imov")
1295 (and (eq_attr "alternative" "0")
1296 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1298 (eq (symbol_ref "TARGET_HIMODE_MATH")
1300 (const_string "imov")
1301 (and (eq_attr "alternative" "1,2")
1302 (match_operand:HI 1 "aligned_operand" ""))
1303 (const_string "imov")
1304 (and (ne (symbol_ref "TARGET_MOVX")
1306 (eq_attr "alternative" "0,2"))
1307 (const_string "imovx")
1309 (const_string "imov")))
1311 (cond [(eq_attr "type" "imovx")
1313 (and (eq_attr "alternative" "1,2")
1314 (match_operand:HI 1 "aligned_operand" ""))
1316 (and (eq_attr "alternative" "0")
1317 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1319 (eq (symbol_ref "TARGET_HIMODE_MATH")
1323 (const_string "HI")))])
1325 ;; Stores and loads of ax to arbitrary constant address.
1326 ;; We fake an second form of instruction to force reload to load address
1327 ;; into register when rax is not available
1328 (define_insn "*movabshi_1_rex64"
1329 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1330 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1331 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1333 movabs{w}\t{%1, %P0|%P0, %1}
1334 mov{w}\t{%1, %a0|%a0, %1}"
1335 [(set_attr "type" "imov")
1336 (set_attr "modrm" "0,*")
1337 (set_attr "length_address" "8,0")
1338 (set_attr "length_immediate" "0,*")
1339 (set_attr "memory" "store")
1340 (set_attr "mode" "HI")])
1342 (define_insn "*movabshi_2_rex64"
1343 [(set (match_operand:HI 0 "register_operand" "=a,r")
1344 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1345 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1347 movabs{w}\t{%P1, %0|%0, %P1}
1348 mov{w}\t{%a1, %0|%0, %a1}"
1349 [(set_attr "type" "imov")
1350 (set_attr "modrm" "0,*")
1351 (set_attr "length_address" "8,0")
1352 (set_attr "length_immediate" "0")
1353 (set_attr "memory" "load")
1354 (set_attr "mode" "HI")])
1356 (define_insn "*swaphi_1"
1357 [(set (match_operand:HI 0 "register_operand" "+r")
1358 (match_operand:HI 1 "register_operand" "+r"))
1361 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1363 [(set_attr "type" "imov")
1364 (set_attr "mode" "SI")
1365 (set_attr "pent_pair" "np")
1366 (set_attr "athlon_decode" "vector")])
1368 (define_insn "*swaphi_2"
1369 [(set (match_operand:HI 0 "register_operand" "+r")
1370 (match_operand:HI 1 "register_operand" "+r"))
1373 "TARGET_PARTIAL_REG_STALL"
1375 [(set_attr "type" "imov")
1376 (set_attr "mode" "HI")
1377 (set_attr "pent_pair" "np")
1378 (set_attr "athlon_decode" "vector")])
1380 (define_expand "movstricthi"
1381 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1382 (match_operand:HI 1 "general_operand" ""))]
1383 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1385 /* Don't generate memory->memory moves, go through a register */
1386 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1387 operands[1] = force_reg (HImode, operands[1]);
1390 (define_insn "*movstricthi_1"
1391 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1392 (match_operand:HI 1 "general_operand" "rn,m"))]
1393 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1394 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1395 "mov{w}\t{%1, %0|%0, %1}"
1396 [(set_attr "type" "imov")
1397 (set_attr "mode" "HI")])
1399 (define_insn "*movstricthi_xor"
1400 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1401 (match_operand:HI 1 "const0_operand" "i"))
1402 (clobber (reg:CC FLAGS_REG))]
1404 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1405 "xor{w}\t{%0, %0|%0, %0}"
1406 [(set_attr "type" "alu1")
1407 (set_attr "mode" "HI")
1408 (set_attr "length_immediate" "0")])
1410 (define_expand "movqi"
1411 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1412 (match_operand:QI 1 "general_operand" ""))]
1414 "ix86_expand_move (QImode, operands); DONE;")
1416 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1417 ;; "push a byte". But actually we use pushw, which has the effect
1418 ;; of rounding the amount pushed up to a halfword.
1420 (define_insn "*pushqi2"
1421 [(set (match_operand:QI 0 "push_operand" "=X,X")
1422 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1425 push{w}\t{|word ptr }%1
1427 [(set_attr "type" "push")
1428 (set_attr "mode" "HI")])
1430 ;; For 64BIT abi we always round up to 8 bytes.
1431 (define_insn "*pushqi2_rex64"
1432 [(set (match_operand:QI 0 "push_operand" "=X")
1433 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1436 [(set_attr "type" "push")
1437 (set_attr "mode" "QI")])
1439 ;; Situation is quite tricky about when to choose full sized (SImode) move
1440 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1441 ;; partial register dependency machines (such as AMD Athlon), where QImode
1442 ;; moves issue extra dependency and for partial register stalls machines
1443 ;; that don't use QImode patterns (and QImode move cause stall on the next
1446 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1447 ;; register stall machines with, where we use QImode instructions, since
1448 ;; partial register stall can be caused there. Then we use movzx.
1449 (define_insn "*movqi_1"
1450 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1451 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1452 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1454 switch (get_attr_type (insn))
1457 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1459 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1461 if (get_attr_mode (insn) == MODE_SI)
1462 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1464 return "mov{b}\t{%1, %0|%0, %1}";
1468 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1469 (const_string "imov")
1470 (and (eq_attr "alternative" "3")
1471 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1473 (eq (symbol_ref "TARGET_QIMODE_MATH")
1475 (const_string "imov")
1476 (eq_attr "alternative" "3,5")
1477 (const_string "imovx")
1478 (and (ne (symbol_ref "TARGET_MOVX")
1480 (eq_attr "alternative" "2"))
1481 (const_string "imovx")
1483 (const_string "imov")))
1485 (cond [(eq_attr "alternative" "3,4,5")
1487 (eq_attr "alternative" "6")
1489 (eq_attr "type" "imovx")
1491 (and (eq_attr "type" "imov")
1492 (and (eq_attr "alternative" "0,1,2")
1493 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1496 ;; Avoid partial register stalls when not using QImode arithmetic
1497 (and (eq_attr "type" "imov")
1498 (and (eq_attr "alternative" "0,1,2")
1499 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1501 (eq (symbol_ref "TARGET_QIMODE_MATH")
1505 (const_string "QI")))])
1507 (define_expand "reload_outqi"
1508 [(parallel [(match_operand:QI 0 "" "=m")
1509 (match_operand:QI 1 "register_operand" "r")
1510 (match_operand:QI 2 "register_operand" "=&q")])]
1514 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1516 if (reg_overlap_mentioned_p (op2, op0))
1518 if (! q_regs_operand (op1, QImode))
1520 emit_insn (gen_movqi (op2, op1));
1523 emit_insn (gen_movqi (op0, op1));
1527 (define_insn "*swapqi_1"
1528 [(set (match_operand:QI 0 "register_operand" "+r")
1529 (match_operand:QI 1 "register_operand" "+r"))
1532 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1534 [(set_attr "type" "imov")
1535 (set_attr "mode" "SI")
1536 (set_attr "pent_pair" "np")
1537 (set_attr "athlon_decode" "vector")])
1539 (define_insn "*swapqi_2"
1540 [(set (match_operand:QI 0 "register_operand" "+q")
1541 (match_operand:QI 1 "register_operand" "+q"))
1544 "TARGET_PARTIAL_REG_STALL"
1546 [(set_attr "type" "imov")
1547 (set_attr "mode" "QI")
1548 (set_attr "pent_pair" "np")
1549 (set_attr "athlon_decode" "vector")])
1551 (define_expand "movstrictqi"
1552 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1553 (match_operand:QI 1 "general_operand" ""))]
1554 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1556 /* Don't generate memory->memory moves, go through a register. */
1557 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1558 operands[1] = force_reg (QImode, operands[1]);
1561 (define_insn "*movstrictqi_1"
1562 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1563 (match_operand:QI 1 "general_operand" "*qn,m"))]
1564 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1565 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1566 "mov{b}\t{%1, %0|%0, %1}"
1567 [(set_attr "type" "imov")
1568 (set_attr "mode" "QI")])
1570 (define_insn "*movstrictqi_xor"
1571 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1572 (match_operand:QI 1 "const0_operand" "i"))
1573 (clobber (reg:CC FLAGS_REG))]
1574 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1575 "xor{b}\t{%0, %0|%0, %0}"
1576 [(set_attr "type" "alu1")
1577 (set_attr "mode" "QI")
1578 (set_attr "length_immediate" "0")])
1580 (define_insn "*movsi_extv_1"
1581 [(set (match_operand:SI 0 "register_operand" "=R")
1582 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1586 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1587 [(set_attr "type" "imovx")
1588 (set_attr "mode" "SI")])
1590 (define_insn "*movhi_extv_1"
1591 [(set (match_operand:HI 0 "register_operand" "=R")
1592 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1596 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1597 [(set_attr "type" "imovx")
1598 (set_attr "mode" "SI")])
1600 (define_insn "*movqi_extv_1"
1601 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1602 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1607 switch (get_attr_type (insn))
1610 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1612 return "mov{b}\t{%h1, %0|%0, %h1}";
1616 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1617 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1618 (ne (symbol_ref "TARGET_MOVX")
1620 (const_string "imovx")
1621 (const_string "imov")))
1623 (if_then_else (eq_attr "type" "imovx")
1625 (const_string "QI")))])
1627 (define_insn "*movqi_extv_1_rex64"
1628 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1629 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1634 switch (get_attr_type (insn))
1637 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1639 return "mov{b}\t{%h1, %0|%0, %h1}";
1643 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1644 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1645 (ne (symbol_ref "TARGET_MOVX")
1647 (const_string "imovx")
1648 (const_string "imov")))
1650 (if_then_else (eq_attr "type" "imovx")
1652 (const_string "QI")))])
1654 ;; Stores and loads of ax to arbitrary constant address.
1655 ;; We fake an second form of instruction to force reload to load address
1656 ;; into register when rax is not available
1657 (define_insn "*movabsqi_1_rex64"
1658 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1659 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1660 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1662 movabs{b}\t{%1, %P0|%P0, %1}
1663 mov{b}\t{%1, %a0|%a0, %1}"
1664 [(set_attr "type" "imov")
1665 (set_attr "modrm" "0,*")
1666 (set_attr "length_address" "8,0")
1667 (set_attr "length_immediate" "0,*")
1668 (set_attr "memory" "store")
1669 (set_attr "mode" "QI")])
1671 (define_insn "*movabsqi_2_rex64"
1672 [(set (match_operand:QI 0 "register_operand" "=a,r")
1673 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1674 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1676 movabs{b}\t{%P1, %0|%0, %P1}
1677 mov{b}\t{%a1, %0|%0, %a1}"
1678 [(set_attr "type" "imov")
1679 (set_attr "modrm" "0,*")
1680 (set_attr "length_address" "8,0")
1681 (set_attr "length_immediate" "0")
1682 (set_attr "memory" "load")
1683 (set_attr "mode" "QI")])
1685 (define_insn "*movsi_extzv_1"
1686 [(set (match_operand:SI 0 "register_operand" "=R")
1687 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1691 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1692 [(set_attr "type" "imovx")
1693 (set_attr "mode" "SI")])
1695 (define_insn "*movqi_extzv_2"
1696 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1697 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1702 switch (get_attr_type (insn))
1705 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1707 return "mov{b}\t{%h1, %0|%0, %h1}";
1711 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1712 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1713 (ne (symbol_ref "TARGET_MOVX")
1715 (const_string "imovx")
1716 (const_string "imov")))
1718 (if_then_else (eq_attr "type" "imovx")
1720 (const_string "QI")))])
1722 (define_insn "*movqi_extzv_2_rex64"
1723 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1724 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1729 switch (get_attr_type (insn))
1732 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1734 return "mov{b}\t{%h1, %0|%0, %h1}";
1738 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1739 (ne (symbol_ref "TARGET_MOVX")
1741 (const_string "imovx")
1742 (const_string "imov")))
1744 (if_then_else (eq_attr "type" "imovx")
1746 (const_string "QI")))])
1748 (define_insn "movsi_insv_1"
1749 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1752 (match_operand:SI 1 "general_operand" "Qmn"))]
1754 "mov{b}\t{%b1, %h0|%h0, %b1}"
1755 [(set_attr "type" "imov")
1756 (set_attr "mode" "QI")])
1758 (define_insn "movdi_insv_1_rex64"
1759 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1762 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1764 "mov{b}\t{%b1, %h0|%h0, %b1}"
1765 [(set_attr "type" "imov")
1766 (set_attr "mode" "QI")])
1768 (define_insn "*movqi_insv_2"
1769 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1772 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1775 "mov{b}\t{%h1, %h0|%h0, %h1}"
1776 [(set_attr "type" "imov")
1777 (set_attr "mode" "QI")])
1779 (define_expand "movdi"
1780 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1781 (match_operand:DI 1 "general_operand" ""))]
1783 "ix86_expand_move (DImode, operands); DONE;")
1785 (define_insn "*pushdi"
1786 [(set (match_operand:DI 0 "push_operand" "=<")
1787 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1791 (define_insn "*pushdi2_rex64"
1792 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1793 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1798 [(set_attr "type" "push,multi")
1799 (set_attr "mode" "DI")])
1801 ;; Convert impossible pushes of immediate to existing instructions.
1802 ;; First try to get scratch register and go through it. In case this
1803 ;; fails, push sign extended lower part first and then overwrite
1804 ;; upper part by 32bit move.
1806 [(match_scratch:DI 2 "r")
1807 (set (match_operand:DI 0 "push_operand" "")
1808 (match_operand:DI 1 "immediate_operand" ""))]
1809 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1810 && !x86_64_immediate_operand (operands[1], DImode)"
1811 [(set (match_dup 2) (match_dup 1))
1812 (set (match_dup 0) (match_dup 2))]
1815 ;; We need to define this as both peepholer and splitter for case
1816 ;; peephole2 pass is not run.
1817 ;; "&& 1" is needed to keep it from matching the previous pattern.
1819 [(set (match_operand:DI 0 "push_operand" "")
1820 (match_operand:DI 1 "immediate_operand" ""))]
1821 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1822 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1823 [(set (match_dup 0) (match_dup 1))
1824 (set (match_dup 2) (match_dup 3))]
1825 "split_di (operands + 1, 1, operands + 2, operands + 3);
1826 operands[1] = gen_lowpart (DImode, operands[2]);
1827 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1832 [(set (match_operand:DI 0 "push_operand" "")
1833 (match_operand:DI 1 "immediate_operand" ""))]
1834 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
1835 && !symbolic_operand (operands[1], DImode)
1836 && !x86_64_immediate_operand (operands[1], DImode)"
1837 [(set (match_dup 0) (match_dup 1))
1838 (set (match_dup 2) (match_dup 3))]
1839 "split_di (operands + 1, 1, operands + 2, operands + 3);
1840 operands[1] = gen_lowpart (DImode, operands[2]);
1841 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1845 (define_insn "*pushdi2_prologue_rex64"
1846 [(set (match_operand:DI 0 "push_operand" "=<")
1847 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1848 (clobber (mem:BLK (scratch)))]
1851 [(set_attr "type" "push")
1852 (set_attr "mode" "DI")])
1854 (define_insn "*popdi1_epilogue_rex64"
1855 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1856 (mem:DI (reg:DI SP_REG)))
1857 (set (reg:DI SP_REG)
1858 (plus:DI (reg:DI SP_REG) (const_int 8)))
1859 (clobber (mem:BLK (scratch)))]
1862 [(set_attr "type" "pop")
1863 (set_attr "mode" "DI")])
1865 (define_insn "popdi1"
1866 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1867 (mem:DI (reg:DI SP_REG)))
1868 (set (reg:DI SP_REG)
1869 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1872 [(set_attr "type" "pop")
1873 (set_attr "mode" "DI")])
1875 (define_insn "*movdi_xor_rex64"
1876 [(set (match_operand:DI 0 "register_operand" "=r")
1877 (match_operand:DI 1 "const0_operand" "i"))
1878 (clobber (reg:CC FLAGS_REG))]
1879 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1880 && reload_completed"
1881 "xor{l}\t{%k0, %k0|%k0, %k0}"
1882 [(set_attr "type" "alu1")
1883 (set_attr "mode" "SI")
1884 (set_attr "length_immediate" "0")])
1886 (define_insn "*movdi_or_rex64"
1887 [(set (match_operand:DI 0 "register_operand" "=r")
1888 (match_operand:DI 1 "const_int_operand" "i"))
1889 (clobber (reg:CC FLAGS_REG))]
1890 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1892 && operands[1] == constm1_rtx"
1894 operands[1] = constm1_rtx;
1895 return "or{q}\t{%1, %0|%0, %1}";
1897 [(set_attr "type" "alu1")
1898 (set_attr "mode" "DI")
1899 (set_attr "length_immediate" "1")])
1901 (define_insn "*movdi_2"
1902 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*x,!*x")
1903 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*x,*x,m"))]
1905 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1909 movq\t{%1, %0|%0, %1}
1910 movq\t{%1, %0|%0, %1}
1911 movq\t{%1, %0|%0, %1}
1912 movdqa\t{%1, %0|%0, %1}
1913 movq\t{%1, %0|%0, %1}"
1914 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1915 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1918 [(set (match_operand:DI 0 "push_operand" "")
1919 (match_operand:DI 1 "general_operand" ""))]
1920 "!TARGET_64BIT && reload_completed
1921 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1923 "ix86_split_long_move (operands); DONE;")
1925 ;; %%% This multiword shite has got to go.
1927 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1928 (match_operand:DI 1 "general_operand" ""))]
1929 "!TARGET_64BIT && reload_completed
1930 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1931 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1933 "ix86_split_long_move (operands); DONE;")
1935 (define_insn "*movdi_1_rex64"
1936 [(set (match_operand:DI 0 "nonimmediate_operand"
1937 "=r,r ,r,mr,!mr,!*y,!rm,!*y,!*x,!rm,!*x,!*x,!*y")
1938 (match_operand:DI 1 "general_operand"
1939 "Z ,rem,i,re,n ,*y ,*y ,rm ,*x ,*x ,rm ,*y ,*x"))]
1941 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1942 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1944 switch (get_attr_type (insn))
1947 if (which_alternative == 11)
1948 return "movq2dq\t{%1, %0|%0, %1}";
1950 return "movdq2q\t{%1, %0|%0, %1}";
1952 if (get_attr_mode (insn) == MODE_TI)
1953 return "movdqa\t{%1, %0|%0, %1}";
1956 /* Moves from and into integer register is done using movd opcode with
1958 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1959 return "movd\t{%1, %0|%0, %1}";
1960 return "movq\t{%1, %0|%0, %1}";
1964 return "lea{q}\t{%a1, %0|%0, %a1}";
1966 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1968 if (get_attr_mode (insn) == MODE_SI)
1969 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1970 else if (which_alternative == 2)
1971 return "movabs{q}\t{%1, %0|%0, %1}";
1973 return "mov{q}\t{%1, %0|%0, %1}";
1977 (cond [(eq_attr "alternative" "5,6,7")
1978 (const_string "mmxmov")
1979 (eq_attr "alternative" "8,9,10")
1980 (const_string "ssemov")
1981 (eq_attr "alternative" "11,12")
1982 (const_string "ssecvt")
1983 (eq_attr "alternative" "4")
1984 (const_string "multi")
1985 (and (ne (symbol_ref "flag_pic") (const_int 0))
1986 (match_operand:DI 1 "symbolic_operand" ""))
1987 (const_string "lea")
1989 (const_string "imov")))
1990 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*")
1991 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*")
1992 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
1994 (define_insn "*movdi_1_rex64_nointerunit"
1995 [(set (match_operand:DI 0 "nonimmediate_operand"
1996 "=r,r ,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
1997 (match_operand:DI 1 "general_operand"
1998 "Z,rem,i,re,n ,*y ,*y,m ,*Y ,*Y,m"))]
2000 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2001 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2003 switch (get_attr_type (insn))
2006 if (get_attr_mode (insn) == MODE_TI)
2007 return "movdqa\t{%1, %0|%0, %1}";
2010 return "movq\t{%1, %0|%0, %1}";
2014 return "lea{q}\t{%a1, %0|%0, %a1}";
2016 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2018 if (get_attr_mode (insn) == MODE_SI)
2019 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2020 else if (which_alternative == 2)
2021 return "movabs{q}\t{%1, %0|%0, %1}";
2023 return "mov{q}\t{%1, %0|%0, %1}";
2027 (cond [(eq_attr "alternative" "5,6,7")
2028 (const_string "mmxmov")
2029 (eq_attr "alternative" "8,9,10")
2030 (const_string "ssemov")
2031 (eq_attr "alternative" "4")
2032 (const_string "multi")
2033 (and (ne (symbol_ref "flag_pic") (const_int 0))
2034 (match_operand:DI 1 "symbolic_operand" ""))
2035 (const_string "lea")
2037 (const_string "imov")))
2038 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2039 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2040 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2042 ;; Stores and loads of ax to arbitrary constant address.
2043 ;; We fake an second form of instruction to force reload to load address
2044 ;; into register when rax is not available
2045 (define_insn "*movabsdi_1_rex64"
2046 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2047 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2048 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2050 movabs{q}\t{%1, %P0|%P0, %1}
2051 mov{q}\t{%1, %a0|%a0, %1}"
2052 [(set_attr "type" "imov")
2053 (set_attr "modrm" "0,*")
2054 (set_attr "length_address" "8,0")
2055 (set_attr "length_immediate" "0,*")
2056 (set_attr "memory" "store")
2057 (set_attr "mode" "DI")])
2059 (define_insn "*movabsdi_2_rex64"
2060 [(set (match_operand:DI 0 "register_operand" "=a,r")
2061 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2062 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2064 movabs{q}\t{%P1, %0|%0, %P1}
2065 mov{q}\t{%a1, %0|%0, %a1}"
2066 [(set_attr "type" "imov")
2067 (set_attr "modrm" "0,*")
2068 (set_attr "length_address" "8,0")
2069 (set_attr "length_immediate" "0")
2070 (set_attr "memory" "load")
2071 (set_attr "mode" "DI")])
2073 ;; Convert impossible stores of immediate to existing instructions.
2074 ;; First try to get scratch register and go through it. In case this
2075 ;; fails, move by 32bit parts.
2077 [(match_scratch:DI 2 "r")
2078 (set (match_operand:DI 0 "memory_operand" "")
2079 (match_operand:DI 1 "immediate_operand" ""))]
2080 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2081 && !x86_64_immediate_operand (operands[1], DImode)"
2082 [(set (match_dup 2) (match_dup 1))
2083 (set (match_dup 0) (match_dup 2))]
2086 ;; We need to define this as both peepholer and splitter for case
2087 ;; peephole2 pass is not run.
2088 ;; "&& 1" is needed to keep it from matching the previous pattern.
2090 [(set (match_operand:DI 0 "memory_operand" "")
2091 (match_operand:DI 1 "immediate_operand" ""))]
2092 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2093 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2094 [(set (match_dup 2) (match_dup 3))
2095 (set (match_dup 4) (match_dup 5))]
2096 "split_di (operands, 2, operands + 2, operands + 4);")
2099 [(set (match_operand:DI 0 "memory_operand" "")
2100 (match_operand:DI 1 "immediate_operand" ""))]
2101 "TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)
2102 && !symbolic_operand (operands[1], DImode)
2103 && !x86_64_immediate_operand (operands[1], DImode)"
2104 [(set (match_dup 2) (match_dup 3))
2105 (set (match_dup 4) (match_dup 5))]
2106 "split_di (operands, 2, operands + 2, operands + 4);")
2108 (define_insn "*swapdi_rex64"
2109 [(set (match_operand:DI 0 "register_operand" "+r")
2110 (match_operand:DI 1 "register_operand" "+r"))
2115 [(set_attr "type" "imov")
2116 (set_attr "mode" "DI")
2117 (set_attr "pent_pair" "np")
2118 (set_attr "athlon_decode" "vector")])
2120 (define_expand "movsf"
2121 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2122 (match_operand:SF 1 "general_operand" ""))]
2124 "ix86_expand_move (SFmode, operands); DONE;")
2126 (define_insn "*pushsf"
2127 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2128 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2131 switch (which_alternative)
2134 return "push{l}\t%1";
2137 /* This insn should be already split before reg-stack. */
2141 [(set_attr "type" "multi,push,multi")
2142 (set_attr "mode" "SF,SI,SF")])
2144 (define_insn "*pushsf_rex64"
2145 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2146 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2149 switch (which_alternative)
2152 return "push{q}\t%q1";
2155 /* This insn should be already split before reg-stack. */
2159 [(set_attr "type" "multi,push,multi")
2160 (set_attr "mode" "SF,DI,SF")])
2163 [(set (match_operand:SF 0 "push_operand" "")
2164 (match_operand:SF 1 "memory_operand" ""))]
2166 && GET_CODE (operands[1]) == MEM
2167 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2168 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2171 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2174 ;; %%% Kill this when call knows how to work this out.
2176 [(set (match_operand:SF 0 "push_operand" "")
2177 (match_operand:SF 1 "any_fp_register_operand" ""))]
2179 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2180 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2183 [(set (match_operand:SF 0 "push_operand" "")
2184 (match_operand:SF 1 "any_fp_register_operand" ""))]
2186 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2187 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2189 (define_insn "*movsf_1"
2190 [(set (match_operand:SF 0 "nonimmediate_operand"
2191 "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!rm,!*y")
2192 (match_operand:SF 1 "general_operand"
2193 "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,rm ,*y ,*y"))]
2194 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2195 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2196 && (reload_in_progress || reload_completed
2197 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2198 || GET_CODE (operands[1]) != CONST_DOUBLE
2199 || memory_operand (operands[0], SFmode))"
2201 switch (which_alternative)
2204 return output_387_reg_move (insn, operands);
2207 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2208 return "fstp%z0\t%y0";
2210 return "fst%z0\t%y0";
2213 return standard_80387_constant_opcode (operands[1]);
2217 return "mov{l}\t{%1, %0|%0, %1}";
2219 if (get_attr_mode (insn) == MODE_TI)
2220 return "pxor\t%0, %0";
2222 return "xorps\t%0, %0";
2224 if (get_attr_mode (insn) == MODE_V4SF)
2225 return "movaps\t{%1, %0|%0, %1}";
2227 return "movss\t{%1, %0|%0, %1}";
2230 return "movss\t{%1, %0|%0, %1}";
2234 return "movd\t{%1, %0|%0, %1}";
2237 return "movq\t{%1, %0|%0, %1}";
2243 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2245 (cond [(eq_attr "alternative" "3,4,9,10")
2247 (eq_attr "alternative" "5")
2249 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2251 (ne (symbol_ref "TARGET_SSE2")
2253 (eq (symbol_ref "optimize_size")
2256 (const_string "V4SF"))
2257 /* For architectures resolving dependencies on
2258 whole SSE registers use APS move to break dependency
2259 chains, otherwise use short move to avoid extra work.
2261 Do the same for architectures resolving dependencies on
2262 the parts. While in DF mode it is better to always handle
2263 just register parts, the SF mode is different due to lack
2264 of instructions to load just part of the register. It is
2265 better to maintain the whole registers in single format
2266 to avoid problems on using packed logical operations. */
2267 (eq_attr "alternative" "6")
2269 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2271 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2273 (const_string "V4SF")
2274 (const_string "SF"))
2275 (eq_attr "alternative" "11")
2276 (const_string "DI")]
2277 (const_string "SF")))])
2279 (define_insn "*movsf_1_nointerunit"
2280 [(set (match_operand:SF 0 "nonimmediate_operand"
2281 "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!m,!*y")
2282 (match_operand:SF 1 "general_operand"
2283 "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,m ,*y,*y"))]
2284 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2285 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2286 && (reload_in_progress || reload_completed
2287 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2288 || GET_CODE (operands[1]) != CONST_DOUBLE
2289 || memory_operand (operands[0], SFmode))"
2291 switch (which_alternative)
2294 return output_387_reg_move (insn, operands);
2297 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2298 return "fstp%z0\t%y0";
2300 return "fst%z0\t%y0";
2303 return standard_80387_constant_opcode (operands[1]);
2307 return "mov{l}\t{%1, %0|%0, %1}";
2309 if (get_attr_mode (insn) == MODE_TI)
2310 return "pxor\t%0, %0";
2312 return "xorps\t%0, %0";
2314 if (get_attr_mode (insn) == MODE_V4SF)
2315 return "movaps\t{%1, %0|%0, %1}";
2317 return "movss\t{%1, %0|%0, %1}";
2320 return "movss\t{%1, %0|%0, %1}";
2324 return "movd\t{%1, %0|%0, %1}";
2327 return "movq\t{%1, %0|%0, %1}";
2333 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2335 (cond [(eq_attr "alternative" "3,4,9,10")
2337 (eq_attr "alternative" "5")
2339 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2341 (ne (symbol_ref "TARGET_SSE2")
2343 (eq (symbol_ref "optimize_size")
2346 (const_string "V4SF"))
2347 /* For architectures resolving dependencies on
2348 whole SSE registers use APS move to break dependency
2349 chains, otherwise use short move to avoid extra work.
2351 Do the same for architectures resolving dependencies on
2352 the parts. While in DF mode it is better to always handle
2353 just register parts, the SF mode is different due to lack
2354 of instructions to load just part of the register. It is
2355 better to maintain the whole registers in single format
2356 to avoid problems on using packed logical operations. */
2357 (eq_attr "alternative" "6")
2359 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2361 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2363 (const_string "V4SF")
2364 (const_string "SF"))
2365 (eq_attr "alternative" "11")
2366 (const_string "DI")]
2367 (const_string "SF")))])
2369 (define_insn "*swapsf"
2370 [(set (match_operand:SF 0 "fp_register_operand" "+f")
2371 (match_operand:SF 1 "fp_register_operand" "+f"))
2374 "reload_completed || TARGET_80387"
2376 if (STACK_TOP_P (operands[0]))
2381 [(set_attr "type" "fxch")
2382 (set_attr "mode" "SF")])
2384 (define_expand "movdf"
2385 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2386 (match_operand:DF 1 "general_operand" ""))]
2388 "ix86_expand_move (DFmode, operands); DONE;")
2390 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2391 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2392 ;; On the average, pushdf using integers can be still shorter. Allow this
2393 ;; pattern for optimize_size too.
2395 (define_insn "*pushdf_nointeger"
2396 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2397 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2398 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2400 /* This insn should be already split before reg-stack. */
2403 [(set_attr "type" "multi")
2404 (set_attr "mode" "DF,SI,SI,DF")])
2406 (define_insn "*pushdf_integer"
2407 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2408 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2409 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2411 /* This insn should be already split before reg-stack. */
2414 [(set_attr "type" "multi")
2415 (set_attr "mode" "DF,SI,DF")])
2417 ;; %%% Kill this when call knows how to work this out.
2419 [(set (match_operand:DF 0 "push_operand" "")
2420 (match_operand:DF 1 "any_fp_register_operand" ""))]
2421 "!TARGET_64BIT && reload_completed"
2422 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2423 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2427 [(set (match_operand:DF 0 "push_operand" "")
2428 (match_operand:DF 1 "any_fp_register_operand" ""))]
2429 "TARGET_64BIT && reload_completed"
2430 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2431 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2435 [(set (match_operand:DF 0 "push_operand" "")
2436 (match_operand:DF 1 "general_operand" ""))]
2439 "ix86_split_long_move (operands); DONE;")
2441 ;; Moving is usually shorter when only FP registers are used. This separate
2442 ;; movdf pattern avoids the use of integer registers for FP operations
2443 ;; when optimizing for size.
2445 (define_insn "*movdf_nointeger"
2446 [(set (match_operand:DF 0 "nonimmediate_operand"
2447 "=f#x,m ,f#x,*r ,o ,x#f,x#f,x#f ,m")
2448 (match_operand:DF 1 "general_operand"
2449 "fm#x,f#x,G ,*roF,F*r,C ,x#f,xHm#f,x#f"))]
2450 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2451 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2452 && (reload_in_progress || reload_completed
2453 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2454 || GET_CODE (operands[1]) != CONST_DOUBLE
2455 || memory_operand (operands[0], DFmode))"
2457 switch (which_alternative)
2460 return output_387_reg_move (insn, operands);
2463 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2464 return "fstp%z0\t%y0";
2466 return "fst%z0\t%y0";
2469 return standard_80387_constant_opcode (operands[1]);
2475 switch (get_attr_mode (insn))
2478 return "xorps\t%0, %0";
2480 return "xorpd\t%0, %0";
2482 return "pxor\t%0, %0";
2489 switch (get_attr_mode (insn))
2492 return "movaps\t{%1, %0|%0, %1}";
2494 return "movapd\t{%1, %0|%0, %1}";
2496 return "movdqa\t{%1, %0|%0, %1}";
2498 return "movq\t{%1, %0|%0, %1}";
2500 return "movsd\t{%1, %0|%0, %1}";
2502 return "movlpd\t{%1, %0|%0, %1}";
2511 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2513 (cond [(eq_attr "alternative" "3,4")
2516 /* For SSE1, we have many fewer alternatives. */
2517 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2518 (cond [(eq_attr "alternative" "5,6")
2520 (ne (symbol_ref "optimize_size") (const_int 0))
2521 (const_string "V4SF")
2522 (const_string "TI"))
2524 (const_string "DI"))
2526 /* xorps is one byte shorter. */
2527 (eq_attr "alternative" "5")
2528 (cond [(ne (symbol_ref "optimize_size")
2530 (const_string "V4SF")
2531 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2535 (const_string "V2DF"))
2537 /* For architectures resolving dependencies on
2538 whole SSE registers use APD move to break dependency
2539 chains, otherwise use short move to avoid extra work.
2541 movaps encodes one byte shorter. */
2542 (eq_attr "alternative" "6")
2544 [(ne (symbol_ref "optimize_size")
2546 (const_string "V4SF")
2547 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2549 (const_string "V2DF")
2551 (const_string "DF"))
2552 /* For architectures resolving dependencies on register
2553 parts we may avoid extra work to zero out upper part
2555 (eq_attr "alternative" "7")
2557 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2559 (const_string "V1DF")
2560 (const_string "DF"))
2562 (const_string "DF")))])
2564 (define_insn "*movdf_integer"
2565 [(set (match_operand:DF 0 "nonimmediate_operand"
2566 "=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf,Y#rf,Y#rf ,m")
2567 (match_operand:DF 1 "general_operand"
2568 "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf,Ym#rf,Y#rf"))]
2569 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2570 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2571 && (reload_in_progress || reload_completed
2572 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2573 || GET_CODE (operands[1]) != CONST_DOUBLE
2574 || memory_operand (operands[0], DFmode))"
2576 switch (which_alternative)
2579 return output_387_reg_move (insn, operands);
2582 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2583 return "fstp%z0\t%y0";
2585 return "fst%z0\t%y0";
2588 return standard_80387_constant_opcode (operands[1]);
2595 switch (get_attr_mode (insn))
2598 return "xorps\t%0, %0";
2600 return "xorpd\t%0, %0";
2602 return "pxor\t%0, %0";
2609 switch (get_attr_mode (insn))
2612 return "movaps\t{%1, %0|%0, %1}";
2614 return "movapd\t{%1, %0|%0, %1}";
2616 return "movdqa\t{%1, %0|%0, %1}";
2618 return "movq\t{%1, %0|%0, %1}";
2620 return "movsd\t{%1, %0|%0, %1}";
2622 return "movlpd\t{%1, %0|%0, %1}";
2631 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2633 (cond [(eq_attr "alternative" "3,4")
2636 /* For SSE1, we have many fewer alternatives. */
2637 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2638 (cond [(eq_attr "alternative" "5,6")
2640 (ne (symbol_ref "optimize_size") (const_int 0))
2641 (const_string "V4SF")
2642 (const_string "TI"))
2644 (const_string "DI"))
2646 /* xorps is one byte shorter. */
2647 (eq_attr "alternative" "5")
2648 (cond [(ne (symbol_ref "optimize_size")
2650 (const_string "V4SF")
2651 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2655 (const_string "V2DF"))
2657 /* For architectures resolving dependencies on
2658 whole SSE registers use APD move to break dependency
2659 chains, otherwise use short move to avoid extra work.
2661 movaps encodes one byte shorter. */
2662 (eq_attr "alternative" "6")
2664 [(ne (symbol_ref "optimize_size")
2666 (const_string "V4SF")
2667 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2669 (const_string "V2DF")
2671 (const_string "DF"))
2672 /* For architectures resolving dependencies on register
2673 parts we may avoid extra work to zero out upper part
2675 (eq_attr "alternative" "7")
2677 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2679 (const_string "V1DF")
2680 (const_string "DF"))
2682 (const_string "DF")))])
2685 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2686 (match_operand:DF 1 "general_operand" ""))]
2688 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2689 && ! (ANY_FP_REG_P (operands[0]) ||
2690 (GET_CODE (operands[0]) == SUBREG
2691 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2692 && ! (ANY_FP_REG_P (operands[1]) ||
2693 (GET_CODE (operands[1]) == SUBREG
2694 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2696 "ix86_split_long_move (operands); DONE;")
2698 (define_insn "*swapdf"
2699 [(set (match_operand:DF 0 "fp_register_operand" "+f")
2700 (match_operand:DF 1 "fp_register_operand" "+f"))
2703 "reload_completed || TARGET_80387"
2705 if (STACK_TOP_P (operands[0]))
2710 [(set_attr "type" "fxch")
2711 (set_attr "mode" "DF")])
2713 (define_expand "movxf"
2714 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2715 (match_operand:XF 1 "general_operand" ""))]
2717 "ix86_expand_move (XFmode, operands); DONE;")
2719 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2720 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2721 ;; Pushing using integer instructions is longer except for constants
2722 ;; and direct memory references.
2723 ;; (assuming that any given constant is pushed only once, but this ought to be
2724 ;; handled elsewhere).
2726 (define_insn "*pushxf_nointeger"
2727 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2728 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2731 /* This insn should be already split before reg-stack. */
2734 [(set_attr "type" "multi")
2735 (set_attr "mode" "XF,SI,SI")])
2737 (define_insn "*pushxf_integer"
2738 [(set (match_operand:XF 0 "push_operand" "=<,<")
2739 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2742 /* This insn should be already split before reg-stack. */
2745 [(set_attr "type" "multi")
2746 (set_attr "mode" "XF,SI")])
2749 [(set (match_operand 0 "push_operand" "")
2750 (match_operand 1 "general_operand" ""))]
2752 && (GET_MODE (operands[0]) == XFmode
2753 || GET_MODE (operands[0]) == DFmode)
2754 && !ANY_FP_REG_P (operands[1])"
2756 "ix86_split_long_move (operands); DONE;")
2759 [(set (match_operand:XF 0 "push_operand" "")
2760 (match_operand:XF 1 "any_fp_register_operand" ""))]
2762 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2763 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2764 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2767 [(set (match_operand:XF 0 "push_operand" "")
2768 (match_operand:XF 1 "any_fp_register_operand" ""))]
2770 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2771 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2772 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2774 ;; Do not use integer registers when optimizing for size
2775 (define_insn "*movxf_nointeger"
2776 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2777 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2779 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2780 && (reload_in_progress || reload_completed
2781 || GET_CODE (operands[1]) != CONST_DOUBLE
2782 || memory_operand (operands[0], XFmode))"
2784 switch (which_alternative)
2787 return output_387_reg_move (insn, operands);
2790 /* There is no non-popping store to memory for XFmode. So if
2791 we need one, follow the store with a load. */
2792 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2793 return "fstp%z0\t%y0\;fld%z0\t%y0";
2795 return "fstp%z0\t%y0";
2798 return standard_80387_constant_opcode (operands[1]);
2805 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2806 (set_attr "mode" "XF,XF,XF,SI,SI")])
2808 (define_insn "*movxf_integer"
2809 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2810 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2812 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2813 && (reload_in_progress || reload_completed
2814 || GET_CODE (operands[1]) != CONST_DOUBLE
2815 || memory_operand (operands[0], XFmode))"
2817 switch (which_alternative)
2820 return output_387_reg_move (insn, operands);
2823 /* There is no non-popping store to memory for XFmode. So if
2824 we need one, follow the store with a load. */
2825 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2826 return "fstp%z0\t%y0\;fld%z0\t%y0";
2828 return "fstp%z0\t%y0";
2831 return standard_80387_constant_opcode (operands[1]);
2838 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2839 (set_attr "mode" "XF,XF,XF,SI,SI")])
2842 [(set (match_operand 0 "nonimmediate_operand" "")
2843 (match_operand 1 "general_operand" ""))]
2845 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2846 && GET_MODE (operands[0]) == XFmode
2847 && ! (ANY_FP_REG_P (operands[0]) ||
2848 (GET_CODE (operands[0]) == SUBREG
2849 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2850 && ! (ANY_FP_REG_P (operands[1]) ||
2851 (GET_CODE (operands[1]) == SUBREG
2852 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2854 "ix86_split_long_move (operands); DONE;")
2857 [(set (match_operand 0 "register_operand" "")
2858 (match_operand 1 "memory_operand" ""))]
2860 && GET_CODE (operands[1]) == MEM
2861 && (GET_MODE (operands[0]) == XFmode
2862 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2863 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2864 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2865 [(set (match_dup 0) (match_dup 1))]
2867 rtx c = get_pool_constant (XEXP (operands[1], 0));
2868 rtx r = operands[0];
2870 if (GET_CODE (r) == SUBREG)
2875 if (!standard_sse_constant_p (c))
2878 else if (FP_REG_P (r))
2880 if (!standard_80387_constant_p (c))
2883 else if (MMX_REG_P (r))
2889 (define_insn "swapxf"
2890 [(set (match_operand:XF 0 "register_operand" "+f")
2891 (match_operand:XF 1 "register_operand" "+f"))
2896 if (STACK_TOP_P (operands[0]))
2901 [(set_attr "type" "fxch")
2902 (set_attr "mode" "XF")])
2904 ;; Zero extension instructions
2906 (define_expand "zero_extendhisi2"
2907 [(set (match_operand:SI 0 "register_operand" "")
2908 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2911 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2913 operands[1] = force_reg (HImode, operands[1]);
2914 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2919 (define_insn "zero_extendhisi2_and"
2920 [(set (match_operand:SI 0 "register_operand" "=r")
2921 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2922 (clobber (reg:CC FLAGS_REG))]
2923 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2925 [(set_attr "type" "alu1")
2926 (set_attr "mode" "SI")])
2929 [(set (match_operand:SI 0 "register_operand" "")
2930 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2931 (clobber (reg:CC FLAGS_REG))]
2932 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2933 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2934 (clobber (reg:CC FLAGS_REG))])]
2937 (define_insn "*zero_extendhisi2_movzwl"
2938 [(set (match_operand:SI 0 "register_operand" "=r")
2939 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2940 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2941 "movz{wl|x}\t{%1, %0|%0, %1}"
2942 [(set_attr "type" "imovx")
2943 (set_attr "mode" "SI")])
2945 (define_expand "zero_extendqihi2"
2947 [(set (match_operand:HI 0 "register_operand" "")
2948 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2949 (clobber (reg:CC FLAGS_REG))])]
2953 (define_insn "*zero_extendqihi2_and"
2954 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2955 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2956 (clobber (reg:CC FLAGS_REG))]
2957 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2959 [(set_attr "type" "alu1")
2960 (set_attr "mode" "HI")])
2962 (define_insn "*zero_extendqihi2_movzbw_and"
2963 [(set (match_operand:HI 0 "register_operand" "=r,r")
2964 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2965 (clobber (reg:CC FLAGS_REG))]
2966 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2968 [(set_attr "type" "imovx,alu1")
2969 (set_attr "mode" "HI")])
2971 (define_insn "*zero_extendqihi2_movzbw"
2972 [(set (match_operand:HI 0 "register_operand" "=r")
2973 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2974 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
2975 "movz{bw|x}\t{%1, %0|%0, %1}"
2976 [(set_attr "type" "imovx")
2977 (set_attr "mode" "HI")])
2979 ;; For the movzbw case strip only the clobber
2981 [(set (match_operand:HI 0 "register_operand" "")
2982 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2983 (clobber (reg:CC FLAGS_REG))]
2985 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
2986 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
2987 [(set (match_operand:HI 0 "register_operand" "")
2988 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
2990 ;; When source and destination does not overlap, clear destination
2991 ;; first and then do the movb
2993 [(set (match_operand:HI 0 "register_operand" "")
2994 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2995 (clobber (reg:CC FLAGS_REG))]
2997 && ANY_QI_REG_P (operands[0])
2998 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2999 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3000 [(set (match_dup 0) (const_int 0))
3001 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3002 "operands[2] = gen_lowpart (QImode, operands[0]);")
3004 ;; Rest is handled by single and.
3006 [(set (match_operand:HI 0 "register_operand" "")
3007 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3008 (clobber (reg:CC FLAGS_REG))]
3010 && true_regnum (operands[0]) == true_regnum (operands[1])"
3011 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3012 (clobber (reg:CC FLAGS_REG))])]
3015 (define_expand "zero_extendqisi2"
3017 [(set (match_operand:SI 0 "register_operand" "")
3018 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3019 (clobber (reg:CC FLAGS_REG))])]
3023 (define_insn "*zero_extendqisi2_and"
3024 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3025 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3026 (clobber (reg:CC FLAGS_REG))]
3027 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3029 [(set_attr "type" "alu1")
3030 (set_attr "mode" "SI")])
3032 (define_insn "*zero_extendqisi2_movzbw_and"
3033 [(set (match_operand:SI 0 "register_operand" "=r,r")
3034 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3035 (clobber (reg:CC FLAGS_REG))]
3036 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3038 [(set_attr "type" "imovx,alu1")
3039 (set_attr "mode" "SI")])
3041 (define_insn "*zero_extendqisi2_movzbw"
3042 [(set (match_operand:SI 0 "register_operand" "=r")
3043 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3044 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3045 "movz{bl|x}\t{%1, %0|%0, %1}"
3046 [(set_attr "type" "imovx")
3047 (set_attr "mode" "SI")])
3049 ;; For the movzbl case strip only the clobber
3051 [(set (match_operand:SI 0 "register_operand" "")
3052 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3053 (clobber (reg:CC FLAGS_REG))]
3055 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3056 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3058 (zero_extend:SI (match_dup 1)))])
3060 ;; When source and destination does not overlap, clear destination
3061 ;; first and then do the movb
3063 [(set (match_operand:SI 0 "register_operand" "")
3064 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3065 (clobber (reg:CC FLAGS_REG))]
3067 && ANY_QI_REG_P (operands[0])
3068 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3069 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3070 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3071 [(set (match_dup 0) (const_int 0))
3072 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3073 "operands[2] = gen_lowpart (QImode, operands[0]);")
3075 ;; Rest is handled by single and.
3077 [(set (match_operand:SI 0 "register_operand" "")
3078 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3079 (clobber (reg:CC FLAGS_REG))]
3081 && true_regnum (operands[0]) == true_regnum (operands[1])"
3082 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3083 (clobber (reg:CC FLAGS_REG))])]
3086 ;; %%% Kill me once multi-word ops are sane.
3087 (define_expand "zero_extendsidi2"
3088 [(set (match_operand:DI 0 "register_operand" "=r")
3089 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3093 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3098 (define_insn "zero_extendsidi2_32"
3099 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3100 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
3101 (clobber (reg:CC FLAGS_REG))]
3102 "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3107 movd\t{%1, %0|%0, %1}
3108 movd\t{%1, %0|%0, %1}"
3109 [(set_attr "mode" "SI,SI,SI,DI,TI")
3110 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3112 (define_insn "*zero_extendsidi2_32_1"
3113 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
3114 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3115 (clobber (reg:CC FLAGS_REG))]
3116 "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3121 movd\t{%1, %0|%0, %1}
3122 movd\t{%1, %0|%0, %1}"
3123 [(set_attr "mode" "SI,SI,SI,DI,TI")
3124 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3126 (define_insn "zero_extendsidi2_rex64"
3127 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
3128 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
3129 "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
3131 mov\t{%k1, %k0|%k0, %k1}
3133 movd\t{%1, %0|%0, %1}
3134 movd\t{%1, %0|%0, %1}"
3135 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3136 (set_attr "mode" "SI,DI,DI,TI")])
3138 (define_insn "*zero_extendsidi2_rex64_1"
3139 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
3140 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3141 "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
3143 mov\t{%k1, %k0|%k0, %k1}
3145 movd\t{%1, %0|%0, %1}
3146 movd\t{%1, %0|%0, %1}"
3147 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3148 (set_attr "mode" "SI,DI,SI,SI")])
3151 [(set (match_operand:DI 0 "memory_operand" "")
3152 (zero_extend:DI (match_dup 0)))]
3154 [(set (match_dup 4) (const_int 0))]
3155 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3158 [(set (match_operand:DI 0 "register_operand" "")
3159 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3160 (clobber (reg:CC FLAGS_REG))]
3161 "!TARGET_64BIT && reload_completed
3162 && true_regnum (operands[0]) == true_regnum (operands[1])"
3163 [(set (match_dup 4) (const_int 0))]
3164 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3167 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3168 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3169 (clobber (reg:CC FLAGS_REG))]
3170 "!TARGET_64BIT && reload_completed
3171 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3172 [(set (match_dup 3) (match_dup 1))
3173 (set (match_dup 4) (const_int 0))]
3174 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3176 (define_insn "zero_extendhidi2"
3177 [(set (match_operand:DI 0 "register_operand" "=r,r")
3178 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3181 movz{wl|x}\t{%1, %k0|%k0, %1}
3182 movz{wq|x}\t{%1, %0|%0, %1}"
3183 [(set_attr "type" "imovx")
3184 (set_attr "mode" "SI,DI")])
3186 (define_insn "zero_extendqidi2"
3187 [(set (match_operand:DI 0 "register_operand" "=r,r")
3188 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3191 movz{bl|x}\t{%1, %k0|%k0, %1}
3192 movz{bq|x}\t{%1, %0|%0, %1}"
3193 [(set_attr "type" "imovx")
3194 (set_attr "mode" "SI,DI")])
3196 ;; Sign extension instructions
3198 (define_expand "extendsidi2"
3199 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3200 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3201 (clobber (reg:CC FLAGS_REG))
3202 (clobber (match_scratch:SI 2 ""))])]
3207 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3212 (define_insn "*extendsidi2_1"
3213 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3214 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3215 (clobber (reg:CC FLAGS_REG))
3216 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3220 (define_insn "extendsidi2_rex64"
3221 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3222 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3226 movs{lq|x}\t{%1,%0|%0, %1}"
3227 [(set_attr "type" "imovx")
3228 (set_attr "mode" "DI")
3229 (set_attr "prefix_0f" "0")
3230 (set_attr "modrm" "0,1")])
3232 (define_insn "extendhidi2"
3233 [(set (match_operand:DI 0 "register_operand" "=r")
3234 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3236 "movs{wq|x}\t{%1,%0|%0, %1}"
3237 [(set_attr "type" "imovx")
3238 (set_attr "mode" "DI")])
3240 (define_insn "extendqidi2"
3241 [(set (match_operand:DI 0 "register_operand" "=r")
3242 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3244 "movs{bq|x}\t{%1,%0|%0, %1}"
3245 [(set_attr "type" "imovx")
3246 (set_attr "mode" "DI")])
3248 ;; Extend to memory case when source register does die.
3250 [(set (match_operand:DI 0 "memory_operand" "")
3251 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3252 (clobber (reg:CC FLAGS_REG))
3253 (clobber (match_operand:SI 2 "register_operand" ""))]
3255 && dead_or_set_p (insn, operands[1])
3256 && !reg_mentioned_p (operands[1], operands[0]))"
3257 [(set (match_dup 3) (match_dup 1))
3258 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3259 (clobber (reg:CC FLAGS_REG))])
3260 (set (match_dup 4) (match_dup 1))]
3261 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3263 ;; Extend to memory case when source register does not die.
3265 [(set (match_operand:DI 0 "memory_operand" "")
3266 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3267 (clobber (reg:CC FLAGS_REG))
3268 (clobber (match_operand:SI 2 "register_operand" ""))]
3272 split_di (&operands[0], 1, &operands[3], &operands[4]);
3274 emit_move_insn (operands[3], operands[1]);
3276 /* Generate a cltd if possible and doing so it profitable. */
3277 if (true_regnum (operands[1]) == 0
3278 && true_regnum (operands[2]) == 1
3279 && (optimize_size || TARGET_USE_CLTD))
3281 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3285 emit_move_insn (operands[2], operands[1]);
3286 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3288 emit_move_insn (operands[4], operands[2]);
3292 ;; Extend to register case. Optimize case where source and destination
3293 ;; registers match and cases where we can use cltd.
3295 [(set (match_operand:DI 0 "register_operand" "")
3296 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3297 (clobber (reg:CC FLAGS_REG))
3298 (clobber (match_scratch:SI 2 ""))]
3302 split_di (&operands[0], 1, &operands[3], &operands[4]);
3304 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3305 emit_move_insn (operands[3], operands[1]);
3307 /* Generate a cltd if possible and doing so it profitable. */
3308 if (true_regnum (operands[3]) == 0
3309 && (optimize_size || TARGET_USE_CLTD))
3311 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3315 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3316 emit_move_insn (operands[4], operands[1]);
3318 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3322 (define_insn "extendhisi2"
3323 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3324 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3327 switch (get_attr_prefix_0f (insn))
3330 return "{cwtl|cwde}";
3332 return "movs{wl|x}\t{%1,%0|%0, %1}";
3335 [(set_attr "type" "imovx")
3336 (set_attr "mode" "SI")
3337 (set (attr "prefix_0f")
3338 ;; movsx is short decodable while cwtl is vector decoded.
3339 (if_then_else (and (eq_attr "cpu" "!k6")
3340 (eq_attr "alternative" "0"))
3342 (const_string "1")))
3344 (if_then_else (eq_attr "prefix_0f" "0")
3346 (const_string "1")))])
3348 (define_insn "*extendhisi2_zext"
3349 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3351 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3354 switch (get_attr_prefix_0f (insn))
3357 return "{cwtl|cwde}";
3359 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3362 [(set_attr "type" "imovx")
3363 (set_attr "mode" "SI")
3364 (set (attr "prefix_0f")
3365 ;; movsx is short decodable while cwtl is vector decoded.
3366 (if_then_else (and (eq_attr "cpu" "!k6")
3367 (eq_attr "alternative" "0"))
3369 (const_string "1")))
3371 (if_then_else (eq_attr "prefix_0f" "0")
3373 (const_string "1")))])
3375 (define_insn "extendqihi2"
3376 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3377 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3380 switch (get_attr_prefix_0f (insn))
3383 return "{cbtw|cbw}";
3385 return "movs{bw|x}\t{%1,%0|%0, %1}";
3388 [(set_attr "type" "imovx")
3389 (set_attr "mode" "HI")
3390 (set (attr "prefix_0f")
3391 ;; movsx is short decodable while cwtl is vector decoded.
3392 (if_then_else (and (eq_attr "cpu" "!k6")
3393 (eq_attr "alternative" "0"))
3395 (const_string "1")))
3397 (if_then_else (eq_attr "prefix_0f" "0")
3399 (const_string "1")))])
3401 (define_insn "extendqisi2"
3402 [(set (match_operand:SI 0 "register_operand" "=r")
3403 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3405 "movs{bl|x}\t{%1,%0|%0, %1}"
3406 [(set_attr "type" "imovx")
3407 (set_attr "mode" "SI")])
3409 (define_insn "*extendqisi2_zext"
3410 [(set (match_operand:DI 0 "register_operand" "=r")
3412 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3414 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3415 [(set_attr "type" "imovx")
3416 (set_attr "mode" "SI")])
3418 ;; Conversions between float and double.
3420 ;; These are all no-ops in the model used for the 80387. So just
3423 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3424 (define_insn "*dummy_extendsfdf2"
3425 [(set (match_operand:DF 0 "push_operand" "=<")
3426 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3431 [(set (match_operand:DF 0 "push_operand" "")
3432 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3434 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3435 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3438 [(set (match_operand:DF 0 "push_operand" "")
3439 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3441 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3442 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3444 (define_insn "*dummy_extendsfxf2"
3445 [(set (match_operand:XF 0 "push_operand" "=<")
3446 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3451 [(set (match_operand:XF 0 "push_operand" "")
3452 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3454 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3455 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3456 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3459 [(set (match_operand:XF 0 "push_operand" "")
3460 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3462 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3463 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3464 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3467 [(set (match_operand:XF 0 "push_operand" "")
3468 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3470 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3471 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3472 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3475 [(set (match_operand:XF 0 "push_operand" "")
3476 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3478 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3479 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3480 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3482 (define_expand "extendsfdf2"
3483 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3484 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3485 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3487 /* ??? Needed for compress_float_constant since all fp constants
3488 are LEGITIMATE_CONSTANT_P. */
3489 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3490 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3491 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3492 operands[1] = force_reg (SFmode, operands[1]);
3495 (define_insn "*extendsfdf2_mixed"
3496 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m#fY,Y#f")
3497 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3498 "TARGET_SSE2 && TARGET_MIX_SSE_I387
3499 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3501 switch (which_alternative)
3504 return output_387_reg_move (insn, operands);
3507 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3508 return "fstp%z0\t%y0";
3510 return "fst%z0\t%y0";
3513 return "cvtss2sd\t{%1, %0|%0, %1}";
3519 [(set_attr "type" "fmov,fmov,ssecvt")
3520 (set_attr "mode" "SF,XF,DF")])
3522 (define_insn "*extendsfdf2_sse"
3523 [(set (match_operand:DF 0 "register_operand" "=Y")
3524 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3525 "TARGET_SSE2 && TARGET_SSE_MATH
3526 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3527 "cvtss2sd\t{%1, %0|%0, %1}"
3528 [(set_attr "type" "ssecvt")
3529 (set_attr "mode" "DF")])
3531 (define_insn "*extendsfdf2_i387"
3532 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
3533 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3535 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3537 switch (which_alternative)
3540 return output_387_reg_move (insn, operands);
3543 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3544 return "fstp%z0\t%y0";
3546 return "fst%z0\t%y0";
3552 [(set_attr "type" "fmov")
3553 (set_attr "mode" "SF,XF")])
3555 (define_expand "extendsfxf2"
3556 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3557 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3560 /* ??? Needed for compress_float_constant since all fp constants
3561 are LEGITIMATE_CONSTANT_P. */
3562 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3563 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3564 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3565 operands[1] = force_reg (SFmode, operands[1]);
3568 (define_insn "*extendsfxf2_i387"
3569 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3570 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3572 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3574 switch (which_alternative)
3577 return output_387_reg_move (insn, operands);
3580 /* There is no non-popping store to memory for XFmode. So if
3581 we need one, follow the store with a load. */
3582 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3583 return "fstp%z0\t%y0";
3585 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3591 [(set_attr "type" "fmov")
3592 (set_attr "mode" "SF,XF")])
3594 (define_expand "extenddfxf2"
3595 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3596 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3599 /* ??? Needed for compress_float_constant since all fp constants
3600 are LEGITIMATE_CONSTANT_P. */
3601 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3602 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3603 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3604 operands[1] = force_reg (DFmode, operands[1]);
3607 (define_insn "*extenddfxf2_i387"
3608 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3609 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3611 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3613 switch (which_alternative)
3616 return output_387_reg_move (insn, operands);
3619 /* There is no non-popping store to memory for XFmode. So if
3620 we need one, follow the store with a load. */
3621 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3622 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3624 return "fstp%z0\t%y0";
3630 [(set_attr "type" "fmov")
3631 (set_attr "mode" "DF,XF")])
3633 ;; %%% This seems bad bad news.
3634 ;; This cannot output into an f-reg because there is no way to be sure
3635 ;; of truncating in that case. Otherwise this is just like a simple move
3636 ;; insn. So we pretend we can output to a reg in order to get better
3637 ;; register preferencing, but we really use a stack slot.
3639 ;; Conversion from DFmode to SFmode.
3641 (define_expand "truncdfsf2"
3642 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3644 (match_operand:DF 1 "nonimmediate_operand" "")))]
3645 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3647 if (MEM_P (operands[0]) && MEM_P (operands[1]))
3648 operands[1] = force_reg (DFmode, operands[1]);
3650 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
3652 else if (flag_unsafe_math_optimizations)
3656 rtx temp = assign_386_stack_local (SFmode, 0);
3657 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
3662 (define_expand "truncdfsf2_with_temp"
3663 [(parallel [(set (match_operand:SF 0 "" "")
3664 (float_truncate:SF (match_operand:DF 1 "" "")))
3665 (clobber (match_operand:SF 2 "" ""))])]
3668 (define_insn "*truncdfsf_fast_mixed"
3669 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f,Y")
3671 (match_operand:DF 1 "nonimmediate_operand" "f ,f,Ym")))]
3672 "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
3674 switch (which_alternative)
3677 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3678 return "fstp%z0\t%y0";
3680 return "fst%z0\t%y0";
3682 return output_387_reg_move (insn, operands);
3684 return "cvtsd2ss\t{%1, %0|%0, %1}";
3689 [(set_attr "type" "fmov,fmov,ssecvt")
3690 (set_attr "mode" "SF")])
3692 ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
3693 ;; because nothing we do here is unsafe.
3694 (define_insn "*truncdfsf_fast_sse"
3695 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y")
3697 (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
3698 "TARGET_SSE2 && TARGET_SSE_MATH"
3699 "cvtsd2ss\t{%1, %0|%0, %1}"
3700 [(set_attr "type" "ssecvt")
3701 (set_attr "mode" "SF")])
3703 (define_insn "*truncdfsf_fast_i387"
3704 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
3706 (match_operand:DF 1 "nonimmediate_operand" "f")))]
3707 "TARGET_80387 && flag_unsafe_math_optimizations"
3708 "* return output_387_reg_move (insn, operands);"
3709 [(set_attr "type" "fmov")
3710 (set_attr "mode" "SF")])
3712 (define_insn "*truncdfsf_mixed"
3713 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y")
3715 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ym")))
3716 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
3717 "TARGET_MIX_SSE_I387"
3719 switch (which_alternative)
3722 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3723 return "fstp%z0\t%y0";
3725 return "fst%z0\t%y0";
3729 return "cvtsd2ss\t{%1, %0|%0, %1}";
3734 [(set_attr "type" "fmov,multi,ssecvt")
3735 (set_attr "mode" "SF")])
3737 (define_insn "*truncdfsf_i387"
3738 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
3740 (match_operand:DF 1 "nonimmediate_operand" "f,f")))
3741 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
3744 switch (which_alternative)
3747 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3748 return "fstp%z0\t%y0";
3750 return "fst%z0\t%y0";
3757 [(set_attr "type" "fmov,multi")
3758 (set_attr "mode" "SF")])
3761 [(set (match_operand:SF 0 "register_operand" "")
3763 (match_operand:DF 1 "fp_register_operand" "")))
3764 (clobber (match_operand 2 "" ""))]
3766 [(set (match_dup 2) (match_dup 1))
3767 (set (match_dup 0) (match_dup 2))]
3769 operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
3772 ;; Conversion from XFmode to SFmode.
3774 (define_expand "truncxfsf2"
3775 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3777 (match_operand:XF 1 "register_operand" "")))
3778 (clobber (match_dup 2))])]
3781 if (flag_unsafe_math_optimizations)
3783 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3784 emit_insn (gen_truncxfsf2_i387_noop (reg, operands[1]));
3785 if (reg != operands[0])
3786 emit_move_insn (operands[0], reg);
3790 operands[2] = assign_386_stack_local (SFmode, 0);
3793 (define_insn "*truncxfsf2_mixed"
3794 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3796 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3797 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3798 "TARGET_MIX_SSE_I387"
3800 switch (which_alternative)
3803 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3804 return "fstp%z0\t%y0";
3806 return "fst%z0\t%y0";
3811 [(set_attr "type" "fmov,multi,multi,multi")
3812 (set_attr "mode" "SF")])
3814 (define_insn "truncxfsf2_i387_noop"
3815 [(set (match_operand:SF 0 "register_operand" "=f")
3816 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3817 "TARGET_80387 && flag_unsafe_math_optimizations"
3819 return output_387_reg_move (insn, operands);
3821 [(set_attr "type" "fmov")
3822 (set_attr "mode" "SF")])
3824 (define_insn "*truncxfsf2_i387"
3825 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
3827 (match_operand:XF 1 "register_operand" "f,f,f")))
3828 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]
3831 switch (which_alternative)
3834 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3835 return "fstp%z0\t%y0";
3837 return "fst%z0\t%y0";
3842 [(set_attr "type" "fmov,multi,multi")
3843 (set_attr "mode" "SF")])
3845 (define_insn "*truncxfsf2_i387_1"
3846 [(set (match_operand:SF 0 "memory_operand" "=m")
3848 (match_operand:XF 1 "register_operand" "f")))]
3851 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3852 return "fstp%z0\t%y0";
3854 return "fst%z0\t%y0";
3856 [(set_attr "type" "fmov")
3857 (set_attr "mode" "SF")])
3860 [(set (match_operand:SF 0 "register_operand" "")
3862 (match_operand:XF 1 "register_operand" "")))
3863 (clobber (match_operand:SF 2 "memory_operand" ""))]
3864 "TARGET_80387 && reload_completed"
3865 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3866 (set (match_dup 0) (match_dup 2))]
3870 [(set (match_operand:SF 0 "memory_operand" "")
3872 (match_operand:XF 1 "register_operand" "")))
3873 (clobber (match_operand:SF 2 "memory_operand" ""))]
3875 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3878 ;; Conversion from XFmode to DFmode.
3880 (define_expand "truncxfdf2"
3881 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3883 (match_operand:XF 1 "register_operand" "")))
3884 (clobber (match_dup 2))])]
3887 if (flag_unsafe_math_optimizations)
3889 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
3890 emit_insn (gen_truncxfdf2_i387_noop (reg, operands[1]));
3891 if (reg != operands[0])
3892 emit_move_insn (operands[0], reg);
3896 operands[2] = assign_386_stack_local (DFmode, 0);
3899 (define_insn "*truncxfdf2_mixed"
3900 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3902 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3903 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3904 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
3906 switch (which_alternative)
3909 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3910 return "fstp%z0\t%y0";
3912 return "fst%z0\t%y0";
3918 [(set_attr "type" "fmov,multi,multi,multi")
3919 (set_attr "mode" "DF")])
3921 (define_insn "truncxfdf2_i387_noop"
3922 [(set (match_operand:DF 0 "register_operand" "=f")
3923 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
3924 "TARGET_80387 && flag_unsafe_math_optimizations"
3926 return output_387_reg_move (insn, operands);
3928 [(set_attr "type" "fmov")
3929 (set_attr "mode" "DF")])
3931 (define_insn "*truncxfdf2_i387"
3932 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
3934 (match_operand:XF 1 "register_operand" "f,f,f")))
3935 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]
3938 switch (which_alternative)
3941 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3942 return "fstp%z0\t%y0";
3944 return "fst%z0\t%y0";
3949 [(set_attr "type" "fmov,multi,multi")
3950 (set_attr "mode" "DF")])
3952 (define_insn "*truncxfdf2_i387_1"
3953 [(set (match_operand:DF 0 "memory_operand" "=m")
3955 (match_operand:XF 1 "register_operand" "f")))]
3958 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3959 return "fstp%z0\t%y0";
3961 return "fst%z0\t%y0";
3963 [(set_attr "type" "fmov")
3964 (set_attr "mode" "DF")])
3967 [(set (match_operand:DF 0 "register_operand" "")
3969 (match_operand:XF 1 "register_operand" "")))
3970 (clobber (match_operand:DF 2 "memory_operand" ""))]
3971 "TARGET_80387 && reload_completed"
3972 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3973 (set (match_dup 0) (match_dup 2))]
3977 [(set (match_operand:DF 0 "memory_operand" "")
3979 (match_operand:XF 1 "register_operand" "")))
3980 (clobber (match_operand:DF 2 "memory_operand" ""))]
3982 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3985 ;; %%% Break up all these bad boys.
3987 ;; Signed conversion to DImode.
3989 (define_expand "fix_truncxfdi2"
3990 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
3991 (fix:DI (match_operand:XF 1 "register_operand" "")))
3992 (clobber (reg:CC FLAGS_REG))])]
3996 (define_expand "fix_truncdfdi2"
3997 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
3998 (fix:DI (match_operand:DF 1 "register_operand" "")))
3999 (clobber (reg:CC FLAGS_REG))])]
4000 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4002 if (TARGET_64BIT && TARGET_SSE2)
4004 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4005 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4006 if (out != operands[0])
4007 emit_move_insn (operands[0], out);
4012 (define_expand "fix_truncsfdi2"
4013 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4014 (fix:DI (match_operand:SF 1 "register_operand" "")))
4015 (clobber (reg:CC FLAGS_REG))])]
4016 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4018 if (TARGET_SSE && TARGET_64BIT)
4020 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4021 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4022 if (out != operands[0])
4023 emit_move_insn (operands[0], out);
4028 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4029 ;; of the machinery.
4030 (define_insn_and_split "*fix_truncdi_1"
4031 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4032 (fix:DI (match_operand 1 "register_operand" "f,f")))
4033 (clobber (reg:CC FLAGS_REG))]
4034 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4035 && !reload_completed && !reload_in_progress
4036 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4041 ix86_optimize_mode_switching = 1;
4042 operands[2] = assign_386_stack_local (HImode, 1);
4043 operands[3] = assign_386_stack_local (HImode, 2);
4044 if (memory_operand (operands[0], VOIDmode))
4045 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4046 operands[2], operands[3]));
4049 operands[4] = assign_386_stack_local (DImode, 0);
4050 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4051 operands[2], operands[3],
4056 [(set_attr "type" "fistp")
4057 (set_attr "i387_cw" "trunc")
4058 (set_attr "mode" "DI")])
4060 (define_insn "fix_truncdi_nomemory"
4061 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4062 (fix:DI (match_operand 1 "register_operand" "f,f")))
4063 (use (match_operand:HI 2 "memory_operand" "m,m"))
4064 (use (match_operand:HI 3 "memory_operand" "m,m"))
4065 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4066 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4067 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4068 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4070 [(set_attr "type" "fistp")
4071 (set_attr "i387_cw" "trunc")
4072 (set_attr "mode" "DI")])
4074 (define_insn "fix_truncdi_memory"
4075 [(set (match_operand:DI 0 "memory_operand" "=m")
4076 (fix:DI (match_operand 1 "register_operand" "f")))
4077 (use (match_operand:HI 2 "memory_operand" "m"))
4078 (use (match_operand:HI 3 "memory_operand" "m"))
4079 (clobber (match_scratch:DF 4 "=&1f"))]
4080 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4081 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4082 "* return output_fix_trunc (insn, operands);"
4083 [(set_attr "type" "fistp")
4084 (set_attr "i387_cw" "trunc")
4085 (set_attr "mode" "DI")])
4088 [(set (match_operand:DI 0 "register_operand" "")
4089 (fix:DI (match_operand 1 "register_operand" "")))
4090 (use (match_operand:HI 2 "memory_operand" ""))
4091 (use (match_operand:HI 3 "memory_operand" ""))
4092 (clobber (match_operand:DI 4 "memory_operand" ""))
4093 (clobber (match_scratch 5 ""))]
4095 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4098 (clobber (match_dup 5))])
4099 (set (match_dup 0) (match_dup 4))]
4103 [(set (match_operand:DI 0 "memory_operand" "")
4104 (fix:DI (match_operand 1 "register_operand" "")))
4105 (use (match_operand:HI 2 "memory_operand" ""))
4106 (use (match_operand:HI 3 "memory_operand" ""))
4107 (clobber (match_operand:DI 4 "memory_operand" ""))
4108 (clobber (match_scratch 5 ""))]
4110 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4113 (clobber (match_dup 5))])]
4116 ;; When SSE available, it is always faster to use it!
4117 (define_insn "fix_truncsfdi_sse"
4118 [(set (match_operand:DI 0 "register_operand" "=r,r")
4119 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4120 "TARGET_64BIT && TARGET_SSE"
4121 "cvttss2si{q}\t{%1, %0|%0, %1}"
4122 [(set_attr "type" "sseicvt")
4123 (set_attr "mode" "SF")
4124 (set_attr "athlon_decode" "double,vector")])
4126 ;; Avoid vector decoded form of the instruction.
4128 [(match_scratch:SF 2 "x")
4129 (set (match_operand:DI 0 "register_operand" "")
4130 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4131 "TARGET_K8 && !optimize_size"
4132 [(set (match_dup 2) (match_dup 1))
4133 (set (match_dup 0) (fix:DI (match_dup 2)))]
4136 (define_insn "fix_truncdfdi_sse"
4137 [(set (match_operand:DI 0 "register_operand" "=r,r")
4138 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4139 "TARGET_64BIT && TARGET_SSE2"
4140 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4141 [(set_attr "type" "sseicvt,sseicvt")
4142 (set_attr "mode" "DF")
4143 (set_attr "athlon_decode" "double,vector")])
4145 ;; Avoid vector decoded form of the instruction.
4147 [(match_scratch:DF 2 "Y")
4148 (set (match_operand:DI 0 "register_operand" "")
4149 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4150 "TARGET_K8 && !optimize_size"
4151 [(set (match_dup 2) (match_dup 1))
4152 (set (match_dup 0) (fix:DI (match_dup 2)))]
4155 ;; Signed conversion to SImode.
4157 (define_expand "fix_truncxfsi2"
4158 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4159 (fix:SI (match_operand:XF 1 "register_operand" "")))
4160 (clobber (reg:CC FLAGS_REG))])]
4164 (define_expand "fix_truncdfsi2"
4165 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4166 (fix:SI (match_operand:DF 1 "register_operand" "")))
4167 (clobber (reg:CC FLAGS_REG))])]
4168 "TARGET_80387 || TARGET_SSE2"
4172 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4173 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4174 if (out != operands[0])
4175 emit_move_insn (operands[0], out);
4180 (define_expand "fix_truncsfsi2"
4181 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4182 (fix:SI (match_operand:SF 1 "register_operand" "")))
4183 (clobber (reg:CC FLAGS_REG))])]
4184 "TARGET_80387 || TARGET_SSE"
4188 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4189 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4190 if (out != operands[0])
4191 emit_move_insn (operands[0], out);
4196 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4197 ;; of the machinery.
4198 (define_insn_and_split "*fix_truncsi_1"
4199 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4200 (fix:SI (match_operand 1 "register_operand" "f,f")))
4201 (clobber (reg:CC FLAGS_REG))]
4202 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4203 && !reload_completed && !reload_in_progress
4204 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4209 ix86_optimize_mode_switching = 1;
4210 operands[2] = assign_386_stack_local (HImode, 1);
4211 operands[3] = assign_386_stack_local (HImode, 2);
4212 if (memory_operand (operands[0], VOIDmode))
4213 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4214 operands[2], operands[3]));
4217 operands[4] = assign_386_stack_local (SImode, 0);
4218 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4219 operands[2], operands[3],
4224 [(set_attr "type" "fistp")
4225 (set_attr "i387_cw" "trunc")
4226 (set_attr "mode" "SI")])
4228 (define_insn "fix_truncsi_nomemory"
4229 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4230 (fix:SI (match_operand 1 "register_operand" "f,f")))
4231 (use (match_operand:HI 2 "memory_operand" "m,m"))
4232 (use (match_operand:HI 3 "memory_operand" "m,m"))
4233 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4234 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4235 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4237 [(set_attr "type" "fistp")
4238 (set_attr "i387_cw" "trunc")
4239 (set_attr "mode" "SI")])
4241 (define_insn "fix_truncsi_memory"
4242 [(set (match_operand:SI 0 "memory_operand" "=m")
4243 (fix:SI (match_operand 1 "register_operand" "f")))
4244 (use (match_operand:HI 2 "memory_operand" "m"))
4245 (use (match_operand:HI 3 "memory_operand" "m"))]
4246 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4247 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4248 "* return output_fix_trunc (insn, operands);"
4249 [(set_attr "type" "fistp")
4250 (set_attr "i387_cw" "trunc")
4251 (set_attr "mode" "SI")])
4253 ;; When SSE available, it is always faster to use it!
4254 (define_insn "fix_truncsfsi_sse"
4255 [(set (match_operand:SI 0 "register_operand" "=r,r")
4256 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4258 "cvttss2si\t{%1, %0|%0, %1}"
4259 [(set_attr "type" "sseicvt")
4260 (set_attr "mode" "DF")
4261 (set_attr "athlon_decode" "double,vector")])
4263 ;; Avoid vector decoded form of the instruction.
4265 [(match_scratch:SF 2 "x")
4266 (set (match_operand:SI 0 "register_operand" "")
4267 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4268 "TARGET_K8 && !optimize_size"
4269 [(set (match_dup 2) (match_dup 1))
4270 (set (match_dup 0) (fix:SI (match_dup 2)))]
4273 (define_insn "fix_truncdfsi_sse"
4274 [(set (match_operand:SI 0 "register_operand" "=r,r")
4275 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4277 "cvttsd2si\t{%1, %0|%0, %1}"
4278 [(set_attr "type" "sseicvt")
4279 (set_attr "mode" "DF")
4280 (set_attr "athlon_decode" "double,vector")])
4282 ;; Avoid vector decoded form of the instruction.
4284 [(match_scratch:DF 2 "Y")
4285 (set (match_operand:SI 0 "register_operand" "")
4286 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4287 "TARGET_K8 && !optimize_size"
4288 [(set (match_dup 2) (match_dup 1))
4289 (set (match_dup 0) (fix:SI (match_dup 2)))]
4293 [(set (match_operand:SI 0 "register_operand" "")
4294 (fix:SI (match_operand 1 "register_operand" "")))
4295 (use (match_operand:HI 2 "memory_operand" ""))
4296 (use (match_operand:HI 3 "memory_operand" ""))
4297 (clobber (match_operand:SI 4 "memory_operand" ""))]
4299 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4301 (use (match_dup 3))])
4302 (set (match_dup 0) (match_dup 4))]
4306 [(set (match_operand:SI 0 "memory_operand" "")
4307 (fix:SI (match_operand 1 "register_operand" "")))
4308 (use (match_operand:HI 2 "memory_operand" ""))
4309 (use (match_operand:HI 3 "memory_operand" ""))
4310 (clobber (match_operand:SI 4 "memory_operand" ""))]
4312 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4314 (use (match_dup 3))])]
4317 ;; Signed conversion to HImode.
4319 (define_expand "fix_truncxfhi2"
4320 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4321 (fix:HI (match_operand:XF 1 "register_operand" "")))
4322 (clobber (reg:CC FLAGS_REG))])]
4326 (define_expand "fix_truncdfhi2"
4327 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4328 (fix:HI (match_operand:DF 1 "register_operand" "")))
4329 (clobber (reg:CC FLAGS_REG))])]
4330 "TARGET_80387 && !TARGET_SSE2"
4333 (define_expand "fix_truncsfhi2"
4334 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4335 (fix:HI (match_operand:SF 1 "register_operand" "")))
4336 (clobber (reg:CC FLAGS_REG))])]
4337 "TARGET_80387 && !TARGET_SSE"
4340 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4341 ;; of the machinery.
4342 (define_insn_and_split "*fix_trunchi_1"
4343 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4344 (fix:HI (match_operand 1 "register_operand" "f,f")))
4345 (clobber (reg:CC FLAGS_REG))]
4346 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4347 && !reload_completed && !reload_in_progress
4348 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4353 ix86_optimize_mode_switching = 1;
4354 operands[2] = assign_386_stack_local (HImode, 1);
4355 operands[3] = assign_386_stack_local (HImode, 2);
4356 if (memory_operand (operands[0], VOIDmode))
4357 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4358 operands[2], operands[3]));
4361 operands[4] = assign_386_stack_local (HImode, 0);
4362 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4363 operands[2], operands[3],
4368 [(set_attr "type" "fistp")
4369 (set_attr "i387_cw" "trunc")
4370 (set_attr "mode" "HI")])
4372 (define_insn "fix_trunchi_nomemory"
4373 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4374 (fix:HI (match_operand 1 "register_operand" "f,f")))
4375 (use (match_operand:HI 2 "memory_operand" "m,m"))
4376 (use (match_operand:HI 3 "memory_operand" "m,m"))
4377 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4378 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4379 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4381 [(set_attr "type" "fistp")
4382 (set_attr "i387_cw" "trunc")
4383 (set_attr "mode" "HI")])
4385 (define_insn "fix_trunchi_memory"
4386 [(set (match_operand:HI 0 "memory_operand" "=m")
4387 (fix:HI (match_operand 1 "register_operand" "f")))
4388 (use (match_operand:HI 2 "memory_operand" "m"))
4389 (use (match_operand:HI 3 "memory_operand" "m"))]
4390 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4391 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4392 "* return output_fix_trunc (insn, operands);"
4393 [(set_attr "type" "fistp")
4394 (set_attr "i387_cw" "trunc")
4395 (set_attr "mode" "HI")])
4398 [(set (match_operand:HI 0 "memory_operand" "")
4399 (fix:HI (match_operand 1 "register_operand" "")))
4400 (use (match_operand:HI 2 "memory_operand" ""))
4401 (use (match_operand:HI 3 "memory_operand" ""))
4402 (clobber (match_operand:HI 4 "memory_operand" ""))]
4404 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4406 (use (match_dup 3))])]
4410 [(set (match_operand:HI 0 "register_operand" "")
4411 (fix:HI (match_operand 1 "register_operand" "")))
4412 (use (match_operand:HI 2 "memory_operand" ""))
4413 (use (match_operand:HI 3 "memory_operand" ""))
4414 (clobber (match_operand:HI 4 "memory_operand" ""))]
4416 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4419 (clobber (match_dup 4))])
4420 (set (match_dup 0) (match_dup 4))]
4423 (define_insn "x86_fnstcw_1"
4424 [(set (match_operand:HI 0 "memory_operand" "=m")
4425 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4428 [(set_attr "length" "2")
4429 (set_attr "mode" "HI")
4430 (set_attr "unit" "i387")])
4432 (define_insn "x86_fldcw_1"
4433 [(set (reg:HI FPSR_REG)
4434 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4437 [(set_attr "length" "2")
4438 (set_attr "mode" "HI")
4439 (set_attr "unit" "i387")
4440 (set_attr "athlon_decode" "vector")])
4442 ;; Conversion between fixed point and floating point.
4444 ;; Even though we only accept memory inputs, the backend _really_
4445 ;; wants to be able to do this between registers.
4447 (define_expand "floathisf2"
4448 [(set (match_operand:SF 0 "register_operand" "")
4449 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4450 "TARGET_80387 || TARGET_SSE_MATH"
4452 if (TARGET_SSE_MATH)
4454 emit_insn (gen_floatsisf2 (operands[0],
4455 convert_to_mode (SImode, operands[1], 0)));
4460 (define_insn "*floathisf2_i387"
4461 [(set (match_operand:SF 0 "register_operand" "=f,f")
4462 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4463 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
4467 [(set_attr "type" "fmov,multi")
4468 (set_attr "mode" "SF")
4469 (set_attr "fp_int_src" "true")])
4471 (define_expand "floatsisf2"
4472 [(set (match_operand:SF 0 "register_operand" "")
4473 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4474 "TARGET_80387 || TARGET_SSE_MATH"
4477 (define_insn "*floatsisf2_mixed"
4478 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4479 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4480 "TARGET_MIX_SSE_I387"
4484 cvtsi2ss\t{%1, %0|%0, %1}
4485 cvtsi2ss\t{%1, %0|%0, %1}"
4486 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4487 (set_attr "mode" "SF")
4488 (set_attr "athlon_decode" "*,*,vector,double")
4489 (set_attr "fp_int_src" "true")])
4491 (define_insn "*floatsisf2_sse"
4492 [(set (match_operand:SF 0 "register_operand" "=x,x")
4493 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4495 "cvtsi2ss\t{%1, %0|%0, %1}"
4496 [(set_attr "type" "sseicvt")
4497 (set_attr "mode" "SF")
4498 (set_attr "athlon_decode" "vector,double")
4499 (set_attr "fp_int_src" "true")])
4501 (define_insn "*floatsisf2_i387"
4502 [(set (match_operand:SF 0 "register_operand" "=f,f")
4503 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4508 [(set_attr "type" "fmov,multi")
4509 (set_attr "mode" "SF")
4510 (set_attr "fp_int_src" "true")])
4512 (define_expand "floatdisf2"
4513 [(set (match_operand:SF 0 "register_operand" "")
4514 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4515 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
4518 (define_insn "*floatdisf2_mixed"
4519 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4520 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4521 "TARGET_64BIT && TARGET_MIX_SSE_I387"
4525 cvtsi2ss{q}\t{%1, %0|%0, %1}
4526 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4527 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4528 (set_attr "mode" "SF")
4529 (set_attr "athlon_decode" "*,*,vector,double")
4530 (set_attr "fp_int_src" "true")])
4532 (define_insn "*floatdisf2_sse"
4533 [(set (match_operand:SF 0 "register_operand" "=x,x")
4534 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4535 "TARGET_64BIT && TARGET_SSE_MATH"
4536 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4537 [(set_attr "type" "sseicvt")
4538 (set_attr "mode" "SF")
4539 (set_attr "athlon_decode" "vector,double")
4540 (set_attr "fp_int_src" "true")])
4542 (define_insn "*floatdisf2_i387"
4543 [(set (match_operand:SF 0 "register_operand" "=f,f")
4544 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4549 [(set_attr "type" "fmov,multi")
4550 (set_attr "mode" "SF")
4551 (set_attr "fp_int_src" "true")])
4553 (define_expand "floathidf2"
4554 [(set (match_operand:DF 0 "register_operand" "")
4555 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4556 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4558 if (TARGET_SSE2 && TARGET_SSE_MATH)
4560 emit_insn (gen_floatsidf2 (operands[0],
4561 convert_to_mode (SImode, operands[1], 0)));
4566 (define_insn "*floathidf2_i387"
4567 [(set (match_operand:DF 0 "register_operand" "=f,f")
4568 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4569 "TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
4573 [(set_attr "type" "fmov,multi")
4574 (set_attr "mode" "DF")
4575 (set_attr "fp_int_src" "true")])
4577 (define_expand "floatsidf2"
4578 [(set (match_operand:DF 0 "register_operand" "")
4579 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4580 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4583 (define_insn "*floatsidf2_mixed"
4584 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4585 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4586 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
4590 cvtsi2sd\t{%1, %0|%0, %1}
4591 cvtsi2sd\t{%1, %0|%0, %1}"
4592 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4593 (set_attr "mode" "DF")
4594 (set_attr "athlon_decode" "*,*,double,direct")
4595 (set_attr "fp_int_src" "true")])
4597 (define_insn "*floatsidf2_sse"
4598 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4599 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4600 "TARGET_SSE2 && TARGET_SSE_MATH"
4601 "cvtsi2sd\t{%1, %0|%0, %1}"
4602 [(set_attr "type" "sseicvt")
4603 (set_attr "mode" "DF")
4604 (set_attr "athlon_decode" "double,direct")
4605 (set_attr "fp_int_src" "true")])
4607 (define_insn "*floatsidf2_i387"
4608 [(set (match_operand:DF 0 "register_operand" "=f,f")
4609 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4614 [(set_attr "type" "fmov,multi")
4615 (set_attr "mode" "DF")
4616 (set_attr "fp_int_src" "true")])
4618 (define_expand "floatdidf2"
4619 [(set (match_operand:DF 0 "register_operand" "")
4620 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4621 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
4624 (define_insn "*floatdidf2_mixed"
4625 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4626 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4627 "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
4631 cvtsi2sd{q}\t{%1, %0|%0, %1}
4632 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4633 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4634 (set_attr "mode" "DF")
4635 (set_attr "athlon_decode" "*,*,double,direct")
4636 (set_attr "fp_int_src" "true")])
4638 (define_insn "*floatdidf2_sse"
4639 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4640 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4641 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4642 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4643 [(set_attr "type" "sseicvt")
4644 (set_attr "mode" "DF")
4645 (set_attr "athlon_decode" "double,direct")
4646 (set_attr "fp_int_src" "true")])
4648 (define_insn "*floatdidf2_i387"
4649 [(set (match_operand:DF 0 "register_operand" "=f,f")
4650 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4655 [(set_attr "type" "fmov,multi")
4656 (set_attr "mode" "DF")
4657 (set_attr "fp_int_src" "true")])
4659 (define_insn "floathixf2"
4660 [(set (match_operand:XF 0 "register_operand" "=f,f")
4661 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4666 [(set_attr "type" "fmov,multi")
4667 (set_attr "mode" "XF")
4668 (set_attr "fp_int_src" "true")])
4670 (define_insn "floatsixf2"
4671 [(set (match_operand:XF 0 "register_operand" "=f,f")
4672 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4677 [(set_attr "type" "fmov,multi")
4678 (set_attr "mode" "XF")
4679 (set_attr "fp_int_src" "true")])
4681 (define_insn "floatdixf2"
4682 [(set (match_operand:XF 0 "register_operand" "=f,f")
4683 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4688 [(set_attr "type" "fmov,multi")
4689 (set_attr "mode" "XF")
4690 (set_attr "fp_int_src" "true")])
4692 ;; %%% Kill these when reload knows how to do it.
4694 [(set (match_operand 0 "fp_register_operand" "")
4695 (float (match_operand 1 "register_operand" "")))]
4698 && FLOAT_MODE_P (GET_MODE (operands[0]))"
4701 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4702 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4703 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4704 ix86_free_from_memory (GET_MODE (operands[1]));
4708 (define_expand "floatunssisf2"
4709 [(use (match_operand:SF 0 "register_operand" ""))
4710 (use (match_operand:SI 1 "register_operand" ""))]
4711 "!TARGET_64BIT && TARGET_SSE_MATH"
4712 "x86_emit_floatuns (operands); DONE;")
4714 (define_expand "floatunsdisf2"
4715 [(use (match_operand:SF 0 "register_operand" ""))
4716 (use (match_operand:DI 1 "register_operand" ""))]
4717 "TARGET_64BIT && TARGET_SSE_MATH"
4718 "x86_emit_floatuns (operands); DONE;")
4720 (define_expand "floatunsdidf2"
4721 [(use (match_operand:DF 0 "register_operand" ""))
4722 (use (match_operand:DI 1 "register_operand" ""))]
4723 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4724 "x86_emit_floatuns (operands); DONE;")
4726 ;; SSE extract/set expanders
4728 (define_expand "vec_setv2df"
4729 [(match_operand:V2DF 0 "register_operand" "")
4730 (match_operand:DF 1 "register_operand" "")
4731 (match_operand 2 "const_int_operand" "")]
4734 switch (INTVAL (operands[2]))
4737 emit_insn (gen_sse2_loadlpd (operands[0], operands[0], operands[1]));
4740 emit_insn (gen_sse2_loadhpd (operands[0], operands[0], operands[1]));
4748 (define_expand "vec_extractv2df"
4749 [(match_operand:DF 0 "register_operand" "")
4750 (match_operand:V2DF 1 "register_operand" "")
4751 (match_operand 2 "const_int_operand" "")]
4754 switch (INTVAL (operands[2]))
4757 emit_insn (gen_sse2_storelpd (operands[0], operands[1]));
4760 emit_insn (gen_sse2_storehpd (operands[0], operands[1]));
4768 (define_expand "vec_initv2df"
4769 [(match_operand:V2DF 0 "register_operand" "")
4770 (match_operand 1 "" "")]
4773 ix86_expand_vector_init (operands[0], operands[1]);
4777 (define_expand "vec_setv4sf"
4778 [(match_operand:V4SF 0 "register_operand" "")
4779 (match_operand:SF 1 "register_operand" "")
4780 (match_operand 2 "const_int_operand" "")]
4783 switch (INTVAL (operands[2]))
4786 emit_insn (gen_sse_movss (operands[0], operands[0],
4787 simplify_gen_subreg (V4SFmode, operands[1],
4792 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4793 rtx tmp = gen_reg_rtx (V4SFmode);
4795 emit_move_insn (tmp, operands[0]);
4796 emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
4797 emit_insn (gen_sse_movss (operands[0], operands[0], op1));
4798 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4799 GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
4804 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4805 rtx tmp = gen_reg_rtx (V4SFmode);
4807 emit_move_insn (tmp, operands[0]);
4808 emit_insn (gen_sse_movss (tmp, tmp, op1));
4809 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4810 GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
4815 rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4816 rtx tmp = gen_reg_rtx (V4SFmode);
4818 emit_move_insn (tmp, operands[0]);
4819 emit_insn (gen_sse_movss (tmp, tmp, op1));
4820 emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
4821 GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
4830 (define_expand "vec_extractv4sf"
4831 [(match_operand:SF 0 "register_operand" "")
4832 (match_operand:V4SF 1 "register_operand" "")
4833 (match_operand 2 "const_int_operand" "")]
4836 switch (INTVAL (operands[2]))
4839 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
4843 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4844 rtx tmp = gen_reg_rtx (V4SFmode);
4846 emit_move_insn (tmp, operands[1]);
4847 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4853 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4854 rtx tmp = gen_reg_rtx (V4SFmode);
4856 emit_move_insn (tmp, operands[1]);
4857 emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
4862 rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
4863 rtx tmp = gen_reg_rtx (V4SFmode);
4865 emit_move_insn (tmp, operands[1]);
4866 emit_insn (gen_sse_shufps (op0, tmp, tmp,
4876 (define_expand "vec_initv4sf"
4877 [(match_operand:V4SF 0 "register_operand" "")
4878 (match_operand 1 "" "")]
4881 ix86_expand_vector_init (operands[0], operands[1]);
4887 ;; %%% splits for addsidi3
4888 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4889 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4890 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4892 (define_expand "adddi3"
4893 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4894 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4895 (match_operand:DI 2 "x86_64_general_operand" "")))
4896 (clobber (reg:CC FLAGS_REG))]
4898 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4900 (define_insn "*adddi3_1"
4901 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4902 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4903 (match_operand:DI 2 "general_operand" "roiF,riF")))
4904 (clobber (reg:CC FLAGS_REG))]
4905 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4909 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4910 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4911 (match_operand:DI 2 "general_operand" "")))
4912 (clobber (reg:CC FLAGS_REG))]
4913 "!TARGET_64BIT && reload_completed"
4914 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4916 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4917 (parallel [(set (match_dup 3)
4918 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4921 (clobber (reg:CC FLAGS_REG))])]
4922 "split_di (operands+0, 1, operands+0, operands+3);
4923 split_di (operands+1, 1, operands+1, operands+4);
4924 split_di (operands+2, 1, operands+2, operands+5);")
4926 (define_insn "adddi3_carry_rex64"
4927 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4928 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4929 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4930 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4931 (clobber (reg:CC FLAGS_REG))]
4932 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4933 "adc{q}\t{%2, %0|%0, %2}"
4934 [(set_attr "type" "alu")
4935 (set_attr "pent_pair" "pu")
4936 (set_attr "mode" "DI")])
4938 (define_insn "*adddi3_cc_rex64"
4939 [(set (reg:CC FLAGS_REG)
4940 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4941 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4943 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4944 (plus:DI (match_dup 1) (match_dup 2)))]
4945 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4946 "add{q}\t{%2, %0|%0, %2}"
4947 [(set_attr "type" "alu")
4948 (set_attr "mode" "DI")])
4950 (define_insn "addqi3_carry"
4951 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4952 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4953 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4954 (match_operand:QI 2 "general_operand" "qi,qm")))
4955 (clobber (reg:CC FLAGS_REG))]
4956 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4957 "adc{b}\t{%2, %0|%0, %2}"
4958 [(set_attr "type" "alu")
4959 (set_attr "pent_pair" "pu")
4960 (set_attr "mode" "QI")])
4962 (define_insn "addhi3_carry"
4963 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4964 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
4965 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
4966 (match_operand:HI 2 "general_operand" "ri,rm")))
4967 (clobber (reg:CC FLAGS_REG))]
4968 "ix86_binary_operator_ok (PLUS, HImode, operands)"
4969 "adc{w}\t{%2, %0|%0, %2}"
4970 [(set_attr "type" "alu")
4971 (set_attr "pent_pair" "pu")
4972 (set_attr "mode" "HI")])
4974 (define_insn "addsi3_carry"
4975 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4976 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4977 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4978 (match_operand:SI 2 "general_operand" "ri,rm")))
4979 (clobber (reg:CC FLAGS_REG))]
4980 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4981 "adc{l}\t{%2, %0|%0, %2}"
4982 [(set_attr "type" "alu")
4983 (set_attr "pent_pair" "pu")
4984 (set_attr "mode" "SI")])
4986 (define_insn "*addsi3_carry_zext"
4987 [(set (match_operand:DI 0 "register_operand" "=r")
4989 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4990 (match_operand:SI 1 "nonimmediate_operand" "%0"))
4991 (match_operand:SI 2 "general_operand" "rim"))))
4992 (clobber (reg:CC FLAGS_REG))]
4993 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4994 "adc{l}\t{%2, %k0|%k0, %2}"
4995 [(set_attr "type" "alu")
4996 (set_attr "pent_pair" "pu")
4997 (set_attr "mode" "SI")])
4999 (define_insn "*addsi3_cc"
5000 [(set (reg:CC FLAGS_REG)
5001 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5002 (match_operand:SI 2 "general_operand" "ri,rm")]
5004 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5005 (plus:SI (match_dup 1) (match_dup 2)))]
5006 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5007 "add{l}\t{%2, %0|%0, %2}"
5008 [(set_attr "type" "alu")
5009 (set_attr "mode" "SI")])
5011 (define_insn "addqi3_cc"
5012 [(set (reg:CC FLAGS_REG)
5013 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5014 (match_operand:QI 2 "general_operand" "qi,qm")]
5016 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5017 (plus:QI (match_dup 1) (match_dup 2)))]
5018 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5019 "add{b}\t{%2, %0|%0, %2}"
5020 [(set_attr "type" "alu")
5021 (set_attr "mode" "QI")])
5023 (define_expand "addsi3"
5024 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5025 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5026 (match_operand:SI 2 "general_operand" "")))
5027 (clobber (reg:CC FLAGS_REG))])]
5029 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5031 (define_insn "*lea_1"
5032 [(set (match_operand:SI 0 "register_operand" "=r")
5033 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5035 "lea{l}\t{%a1, %0|%0, %a1}"
5036 [(set_attr "type" "lea")
5037 (set_attr "mode" "SI")])
5039 (define_insn "*lea_1_rex64"
5040 [(set (match_operand:SI 0 "register_operand" "=r")
5041 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5043 "lea{l}\t{%a1, %0|%0, %a1}"
5044 [(set_attr "type" "lea")
5045 (set_attr "mode" "SI")])
5047 (define_insn "*lea_1_zext"
5048 [(set (match_operand:DI 0 "register_operand" "=r")
5050 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5052 "lea{l}\t{%a1, %k0|%k0, %a1}"
5053 [(set_attr "type" "lea")
5054 (set_attr "mode" "SI")])
5056 (define_insn "*lea_2_rex64"
5057 [(set (match_operand:DI 0 "register_operand" "=r")
5058 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5060 "lea{q}\t{%a1, %0|%0, %a1}"
5061 [(set_attr "type" "lea")
5062 (set_attr "mode" "DI")])
5064 ;; The lea patterns for non-Pmodes needs to be matched by several
5065 ;; insns converted to real lea by splitters.
5067 (define_insn_and_split "*lea_general_1"
5068 [(set (match_operand 0 "register_operand" "=r")
5069 (plus (plus (match_operand 1 "index_register_operand" "l")
5070 (match_operand 2 "register_operand" "r"))
5071 (match_operand 3 "immediate_operand" "i")))]
5072 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5073 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5074 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5075 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5076 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5077 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5078 || GET_MODE (operands[3]) == VOIDmode)"
5080 "&& reload_completed"
5084 operands[0] = gen_lowpart (SImode, operands[0]);
5085 operands[1] = gen_lowpart (Pmode, operands[1]);
5086 operands[2] = gen_lowpart (Pmode, operands[2]);
5087 operands[3] = gen_lowpart (Pmode, operands[3]);
5088 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5090 if (Pmode != SImode)
5091 pat = gen_rtx_SUBREG (SImode, pat, 0);
5092 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5095 [(set_attr "type" "lea")
5096 (set_attr "mode" "SI")])
5098 (define_insn_and_split "*lea_general_1_zext"
5099 [(set (match_operand:DI 0 "register_operand" "=r")
5101 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
5102 (match_operand:SI 2 "register_operand" "r"))
5103 (match_operand:SI 3 "immediate_operand" "i"))))]
5106 "&& reload_completed"
5108 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5110 (match_dup 3)) 0)))]
5112 operands[1] = gen_lowpart (Pmode, operands[1]);
5113 operands[2] = gen_lowpart (Pmode, operands[2]);
5114 operands[3] = gen_lowpart (Pmode, operands[3]);
5116 [(set_attr "type" "lea")
5117 (set_attr "mode" "SI")])
5119 (define_insn_and_split "*lea_general_2"
5120 [(set (match_operand 0 "register_operand" "=r")
5121 (plus (mult (match_operand 1 "index_register_operand" "l")
5122 (match_operand 2 "const248_operand" "i"))
5123 (match_operand 3 "nonmemory_operand" "ri")))]
5124 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5125 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5126 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5127 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5128 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5129 || GET_MODE (operands[3]) == VOIDmode)"
5131 "&& reload_completed"
5135 operands[0] = gen_lowpart (SImode, operands[0]);
5136 operands[1] = gen_lowpart (Pmode, operands[1]);
5137 operands[3] = gen_lowpart (Pmode, operands[3]);
5138 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5140 if (Pmode != SImode)
5141 pat = gen_rtx_SUBREG (SImode, pat, 0);
5142 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5145 [(set_attr "type" "lea")
5146 (set_attr "mode" "SI")])
5148 (define_insn_and_split "*lea_general_2_zext"
5149 [(set (match_operand:DI 0 "register_operand" "=r")
5151 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
5152 (match_operand:SI 2 "const248_operand" "n"))
5153 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5156 "&& reload_completed"
5158 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5160 (match_dup 3)) 0)))]
5162 operands[1] = gen_lowpart (Pmode, operands[1]);
5163 operands[3] = gen_lowpart (Pmode, operands[3]);
5165 [(set_attr "type" "lea")
5166 (set_attr "mode" "SI")])
5168 (define_insn_and_split "*lea_general_3"
5169 [(set (match_operand 0 "register_operand" "=r")
5170 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
5171 (match_operand 2 "const248_operand" "i"))
5172 (match_operand 3 "register_operand" "r"))
5173 (match_operand 4 "immediate_operand" "i")))]
5174 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5175 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5176 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5177 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5178 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5180 "&& reload_completed"
5184 operands[0] = gen_lowpart (SImode, operands[0]);
5185 operands[1] = gen_lowpart (Pmode, operands[1]);
5186 operands[3] = gen_lowpart (Pmode, operands[3]);
5187 operands[4] = gen_lowpart (Pmode, operands[4]);
5188 pat = gen_rtx_PLUS (Pmode,
5189 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5193 if (Pmode != SImode)
5194 pat = gen_rtx_SUBREG (SImode, pat, 0);
5195 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5198 [(set_attr "type" "lea")
5199 (set_attr "mode" "SI")])
5201 (define_insn_and_split "*lea_general_3_zext"
5202 [(set (match_operand:DI 0 "register_operand" "=r")
5204 (plus:SI (plus:SI (mult:SI
5205 (match_operand:SI 1 "index_register_operand" "l")
5206 (match_operand:SI 2 "const248_operand" "n"))
5207 (match_operand:SI 3 "register_operand" "r"))
5208 (match_operand:SI 4 "immediate_operand" "i"))))]
5211 "&& reload_completed"
5213 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5216 (match_dup 4)) 0)))]
5218 operands[1] = gen_lowpart (Pmode, operands[1]);
5219 operands[3] = gen_lowpart (Pmode, operands[3]);
5220 operands[4] = gen_lowpart (Pmode, operands[4]);
5222 [(set_attr "type" "lea")
5223 (set_attr "mode" "SI")])
5225 (define_insn "*adddi_1_rex64"
5226 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5227 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5228 (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
5229 (clobber (reg:CC FLAGS_REG))]
5230 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5232 switch (get_attr_type (insn))
5235 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5236 return "lea{q}\t{%a2, %0|%0, %a2}";
5239 if (! rtx_equal_p (operands[0], operands[1]))
5241 if (operands[2] == const1_rtx)
5242 return "inc{q}\t%0";
5243 else if (operands[2] == constm1_rtx)
5244 return "dec{q}\t%0";
5249 if (! rtx_equal_p (operands[0], operands[1]))
5252 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5253 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5254 if (GET_CODE (operands[2]) == CONST_INT
5255 /* Avoid overflows. */
5256 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5257 && (INTVAL (operands[2]) == 128
5258 || (INTVAL (operands[2]) < 0
5259 && INTVAL (operands[2]) != -128)))
5261 operands[2] = GEN_INT (-INTVAL (operands[2]));
5262 return "sub{q}\t{%2, %0|%0, %2}";
5264 return "add{q}\t{%2, %0|%0, %2}";
5268 (cond [(eq_attr "alternative" "2")
5269 (const_string "lea")
5270 ; Current assemblers are broken and do not allow @GOTOFF in
5271 ; ought but a memory context.
5272 (match_operand:DI 2 "pic_symbolic_operand" "")
5273 (const_string "lea")
5274 (match_operand:DI 2 "incdec_operand" "")
5275 (const_string "incdec")
5277 (const_string "alu")))
5278 (set_attr "mode" "DI")])
5280 ;; Convert lea to the lea pattern to avoid flags dependency.
5282 [(set (match_operand:DI 0 "register_operand" "")
5283 (plus:DI (match_operand:DI 1 "register_operand" "")
5284 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5285 (clobber (reg:CC FLAGS_REG))]
5286 "TARGET_64BIT && reload_completed
5287 && true_regnum (operands[0]) != true_regnum (operands[1])"
5289 (plus:DI (match_dup 1)
5293 (define_insn "*adddi_2_rex64"
5294 [(set (reg FLAGS_REG)
5296 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5297 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5299 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5300 (plus:DI (match_dup 1) (match_dup 2)))]
5301 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5302 && ix86_binary_operator_ok (PLUS, DImode, operands)
5303 /* Current assemblers are broken and do not allow @GOTOFF in
5304 ought but a memory context. */
5305 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5307 switch (get_attr_type (insn))
5310 if (! rtx_equal_p (operands[0], operands[1]))
5312 if (operands[2] == const1_rtx)
5313 return "inc{q}\t%0";
5314 else if (operands[2] == constm1_rtx)
5315 return "dec{q}\t%0";
5320 if (! rtx_equal_p (operands[0], operands[1]))
5322 /* ???? We ought to handle there the 32bit case too
5323 - do we need new constraint? */
5324 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5325 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5326 if (GET_CODE (operands[2]) == CONST_INT
5327 /* Avoid overflows. */
5328 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5329 && (INTVAL (operands[2]) == 128
5330 || (INTVAL (operands[2]) < 0
5331 && INTVAL (operands[2]) != -128)))
5333 operands[2] = GEN_INT (-INTVAL (operands[2]));
5334 return "sub{q}\t{%2, %0|%0, %2}";
5336 return "add{q}\t{%2, %0|%0, %2}";
5340 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5341 (const_string "incdec")
5342 (const_string "alu")))
5343 (set_attr "mode" "DI")])
5345 (define_insn "*adddi_3_rex64"
5346 [(set (reg FLAGS_REG)
5347 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5348 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5349 (clobber (match_scratch:DI 0 "=r"))]
5351 && ix86_match_ccmode (insn, CCZmode)
5352 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5353 /* Current assemblers are broken and do not allow @GOTOFF in
5354 ought but a memory context. */
5355 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5357 switch (get_attr_type (insn))
5360 if (! rtx_equal_p (operands[0], operands[1]))
5362 if (operands[2] == const1_rtx)
5363 return "inc{q}\t%0";
5364 else if (operands[2] == constm1_rtx)
5365 return "dec{q}\t%0";
5370 if (! rtx_equal_p (operands[0], operands[1]))
5372 /* ???? We ought to handle there the 32bit case too
5373 - do we need new constraint? */
5374 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5375 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5376 if (GET_CODE (operands[2]) == CONST_INT
5377 /* Avoid overflows. */
5378 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5379 && (INTVAL (operands[2]) == 128
5380 || (INTVAL (operands[2]) < 0
5381 && INTVAL (operands[2]) != -128)))
5383 operands[2] = GEN_INT (-INTVAL (operands[2]));
5384 return "sub{q}\t{%2, %0|%0, %2}";
5386 return "add{q}\t{%2, %0|%0, %2}";
5390 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5391 (const_string "incdec")
5392 (const_string "alu")))
5393 (set_attr "mode" "DI")])
5395 ; For comparisons against 1, -1 and 128, we may generate better code
5396 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5397 ; is matched then. We can't accept general immediate, because for
5398 ; case of overflows, the result is messed up.
5399 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5401 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5402 ; only for comparisons not depending on it.
5403 (define_insn "*adddi_4_rex64"
5404 [(set (reg FLAGS_REG)
5405 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5406 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5407 (clobber (match_scratch:DI 0 "=rm"))]
5409 && ix86_match_ccmode (insn, CCGCmode)"
5411 switch (get_attr_type (insn))
5414 if (operands[2] == constm1_rtx)
5415 return "inc{q}\t%0";
5416 else if (operands[2] == const1_rtx)
5417 return "dec{q}\t%0";
5422 if (! rtx_equal_p (operands[0], operands[1]))
5424 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5425 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5426 if ((INTVAL (operands[2]) == -128
5427 || (INTVAL (operands[2]) > 0
5428 && INTVAL (operands[2]) != 128))
5429 /* Avoid overflows. */
5430 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5431 return "sub{q}\t{%2, %0|%0, %2}";
5432 operands[2] = GEN_INT (-INTVAL (operands[2]));
5433 return "add{q}\t{%2, %0|%0, %2}";
5437 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5438 (const_string "incdec")
5439 (const_string "alu")))
5440 (set_attr "mode" "DI")])
5442 (define_insn "*adddi_5_rex64"
5443 [(set (reg FLAGS_REG)
5445 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5446 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5448 (clobber (match_scratch:DI 0 "=r"))]
5450 && ix86_match_ccmode (insn, CCGOCmode)
5451 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5452 /* Current assemblers are broken and do not allow @GOTOFF in
5453 ought but a memory context. */
5454 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5456 switch (get_attr_type (insn))
5459 if (! rtx_equal_p (operands[0], operands[1]))
5461 if (operands[2] == const1_rtx)
5462 return "inc{q}\t%0";
5463 else if (operands[2] == constm1_rtx)
5464 return "dec{q}\t%0";
5469 if (! rtx_equal_p (operands[0], operands[1]))
5471 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5472 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5473 if (GET_CODE (operands[2]) == CONST_INT
5474 /* Avoid overflows. */
5475 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5476 && (INTVAL (operands[2]) == 128
5477 || (INTVAL (operands[2]) < 0
5478 && INTVAL (operands[2]) != -128)))
5480 operands[2] = GEN_INT (-INTVAL (operands[2]));
5481 return "sub{q}\t{%2, %0|%0, %2}";
5483 return "add{q}\t{%2, %0|%0, %2}";
5487 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5488 (const_string "incdec")
5489 (const_string "alu")))
5490 (set_attr "mode" "DI")])
5493 (define_insn "*addsi_1"
5494 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5495 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5496 (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
5497 (clobber (reg:CC FLAGS_REG))]
5498 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5500 switch (get_attr_type (insn))
5503 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5504 return "lea{l}\t{%a2, %0|%0, %a2}";
5507 if (! rtx_equal_p (operands[0], operands[1]))
5509 if (operands[2] == const1_rtx)
5510 return "inc{l}\t%0";
5511 else if (operands[2] == constm1_rtx)
5512 return "dec{l}\t%0";
5517 if (! rtx_equal_p (operands[0], operands[1]))
5520 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5521 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5522 if (GET_CODE (operands[2]) == CONST_INT
5523 && (INTVAL (operands[2]) == 128
5524 || (INTVAL (operands[2]) < 0
5525 && INTVAL (operands[2]) != -128)))
5527 operands[2] = GEN_INT (-INTVAL (operands[2]));
5528 return "sub{l}\t{%2, %0|%0, %2}";
5530 return "add{l}\t{%2, %0|%0, %2}";
5534 (cond [(eq_attr "alternative" "2")
5535 (const_string "lea")
5536 ; Current assemblers are broken and do not allow @GOTOFF in
5537 ; ought but a memory context.
5538 (match_operand:SI 2 "pic_symbolic_operand" "")
5539 (const_string "lea")
5540 (match_operand:SI 2 "incdec_operand" "")
5541 (const_string "incdec")
5543 (const_string "alu")))
5544 (set_attr "mode" "SI")])
5546 ;; Convert lea to the lea pattern to avoid flags dependency.
5548 [(set (match_operand 0 "register_operand" "")
5549 (plus (match_operand 1 "register_operand" "")
5550 (match_operand 2 "nonmemory_operand" "")))
5551 (clobber (reg:CC FLAGS_REG))]
5553 && true_regnum (operands[0]) != true_regnum (operands[1])"
5557 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5558 may confuse gen_lowpart. */
5559 if (GET_MODE (operands[0]) != Pmode)
5561 operands[1] = gen_lowpart (Pmode, operands[1]);
5562 operands[2] = gen_lowpart (Pmode, operands[2]);
5564 operands[0] = gen_lowpart (SImode, operands[0]);
5565 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5566 if (Pmode != SImode)
5567 pat = gen_rtx_SUBREG (SImode, pat, 0);
5568 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5572 ;; It may seem that nonimmediate operand is proper one for operand 1.
5573 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5574 ;; we take care in ix86_binary_operator_ok to not allow two memory
5575 ;; operands so proper swapping will be done in reload. This allow
5576 ;; patterns constructed from addsi_1 to match.
5577 (define_insn "addsi_1_zext"
5578 [(set (match_operand:DI 0 "register_operand" "=r,r")
5580 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5581 (match_operand:SI 2 "general_operand" "rmni,lni"))))
5582 (clobber (reg:CC FLAGS_REG))]
5583 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5585 switch (get_attr_type (insn))
5588 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5589 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5592 if (operands[2] == const1_rtx)
5593 return "inc{l}\t%k0";
5594 else if (operands[2] == constm1_rtx)
5595 return "dec{l}\t%k0";
5600 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5601 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5602 if (GET_CODE (operands[2]) == CONST_INT
5603 && (INTVAL (operands[2]) == 128
5604 || (INTVAL (operands[2]) < 0
5605 && INTVAL (operands[2]) != -128)))
5607 operands[2] = GEN_INT (-INTVAL (operands[2]));
5608 return "sub{l}\t{%2, %k0|%k0, %2}";
5610 return "add{l}\t{%2, %k0|%k0, %2}";
5614 (cond [(eq_attr "alternative" "1")
5615 (const_string "lea")
5616 ; Current assemblers are broken and do not allow @GOTOFF in
5617 ; ought but a memory context.
5618 (match_operand:SI 2 "pic_symbolic_operand" "")
5619 (const_string "lea")
5620 (match_operand:SI 2 "incdec_operand" "")
5621 (const_string "incdec")
5623 (const_string "alu")))
5624 (set_attr "mode" "SI")])
5626 ;; Convert lea to the lea pattern to avoid flags dependency.
5628 [(set (match_operand:DI 0 "register_operand" "")
5630 (plus:SI (match_operand:SI 1 "register_operand" "")
5631 (match_operand:SI 2 "nonmemory_operand" ""))))
5632 (clobber (reg:CC FLAGS_REG))]
5633 "TARGET_64BIT && reload_completed
5634 && true_regnum (operands[0]) != true_regnum (operands[1])"
5636 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5638 operands[1] = gen_lowpart (Pmode, operands[1]);
5639 operands[2] = gen_lowpart (Pmode, operands[2]);
5642 (define_insn "*addsi_2"
5643 [(set (reg FLAGS_REG)
5645 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5646 (match_operand:SI 2 "general_operand" "rmni,rni"))
5648 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5649 (plus:SI (match_dup 1) (match_dup 2)))]
5650 "ix86_match_ccmode (insn, CCGOCmode)
5651 && ix86_binary_operator_ok (PLUS, SImode, operands)
5652 /* Current assemblers are broken and do not allow @GOTOFF in
5653 ought but a memory context. */
5654 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5656 switch (get_attr_type (insn))
5659 if (! rtx_equal_p (operands[0], operands[1]))
5661 if (operands[2] == const1_rtx)
5662 return "inc{l}\t%0";
5663 else if (operands[2] == constm1_rtx)
5664 return "dec{l}\t%0";
5669 if (! rtx_equal_p (operands[0], operands[1]))
5671 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5672 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5673 if (GET_CODE (operands[2]) == CONST_INT
5674 && (INTVAL (operands[2]) == 128
5675 || (INTVAL (operands[2]) < 0
5676 && INTVAL (operands[2]) != -128)))
5678 operands[2] = GEN_INT (-INTVAL (operands[2]));
5679 return "sub{l}\t{%2, %0|%0, %2}";
5681 return "add{l}\t{%2, %0|%0, %2}";
5685 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5686 (const_string "incdec")
5687 (const_string "alu")))
5688 (set_attr "mode" "SI")])
5690 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5691 (define_insn "*addsi_2_zext"
5692 [(set (reg FLAGS_REG)
5694 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5695 (match_operand:SI 2 "general_operand" "rmni"))
5697 (set (match_operand:DI 0 "register_operand" "=r")
5698 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5699 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5700 && ix86_binary_operator_ok (PLUS, SImode, operands)
5701 /* Current assemblers are broken and do not allow @GOTOFF in
5702 ought but a memory context. */
5703 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5705 switch (get_attr_type (insn))
5708 if (operands[2] == const1_rtx)
5709 return "inc{l}\t%k0";
5710 else if (operands[2] == constm1_rtx)
5711 return "dec{l}\t%k0";
5716 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5717 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5718 if (GET_CODE (operands[2]) == CONST_INT
5719 && (INTVAL (operands[2]) == 128
5720 || (INTVAL (operands[2]) < 0
5721 && INTVAL (operands[2]) != -128)))
5723 operands[2] = GEN_INT (-INTVAL (operands[2]));
5724 return "sub{l}\t{%2, %k0|%k0, %2}";
5726 return "add{l}\t{%2, %k0|%k0, %2}";
5730 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5731 (const_string "incdec")
5732 (const_string "alu")))
5733 (set_attr "mode" "SI")])
5735 (define_insn "*addsi_3"
5736 [(set (reg FLAGS_REG)
5737 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5738 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5739 (clobber (match_scratch:SI 0 "=r"))]
5740 "ix86_match_ccmode (insn, CCZmode)
5741 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5742 /* Current assemblers are broken and do not allow @GOTOFF in
5743 ought but a memory context. */
5744 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5746 switch (get_attr_type (insn))
5749 if (! rtx_equal_p (operands[0], operands[1]))
5751 if (operands[2] == const1_rtx)
5752 return "inc{l}\t%0";
5753 else if (operands[2] == constm1_rtx)
5754 return "dec{l}\t%0";
5759 if (! rtx_equal_p (operands[0], operands[1]))
5761 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5762 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5763 if (GET_CODE (operands[2]) == CONST_INT
5764 && (INTVAL (operands[2]) == 128
5765 || (INTVAL (operands[2]) < 0
5766 && INTVAL (operands[2]) != -128)))
5768 operands[2] = GEN_INT (-INTVAL (operands[2]));
5769 return "sub{l}\t{%2, %0|%0, %2}";
5771 return "add{l}\t{%2, %0|%0, %2}";
5775 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5776 (const_string "incdec")
5777 (const_string "alu")))
5778 (set_attr "mode" "SI")])
5780 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5781 (define_insn "*addsi_3_zext"
5782 [(set (reg FLAGS_REG)
5783 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5784 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5785 (set (match_operand:DI 0 "register_operand" "=r")
5786 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5787 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5788 && ix86_binary_operator_ok (PLUS, SImode, operands)
5789 /* Current assemblers are broken and do not allow @GOTOFF in
5790 ought but a memory context. */
5791 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5793 switch (get_attr_type (insn))
5796 if (operands[2] == const1_rtx)
5797 return "inc{l}\t%k0";
5798 else if (operands[2] == constm1_rtx)
5799 return "dec{l}\t%k0";
5804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5806 if (GET_CODE (operands[2]) == CONST_INT
5807 && (INTVAL (operands[2]) == 128
5808 || (INTVAL (operands[2]) < 0
5809 && INTVAL (operands[2]) != -128)))
5811 operands[2] = GEN_INT (-INTVAL (operands[2]));
5812 return "sub{l}\t{%2, %k0|%k0, %2}";
5814 return "add{l}\t{%2, %k0|%k0, %2}";
5818 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5819 (const_string "incdec")
5820 (const_string "alu")))
5821 (set_attr "mode" "SI")])
5823 ; For comparisons against 1, -1 and 128, we may generate better code
5824 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5825 ; is matched then. We can't accept general immediate, because for
5826 ; case of overflows, the result is messed up.
5827 ; This pattern also don't hold of 0x80000000, since the value overflows
5829 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5830 ; only for comparisons not depending on it.
5831 (define_insn "*addsi_4"
5832 [(set (reg FLAGS_REG)
5833 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5834 (match_operand:SI 2 "const_int_operand" "n")))
5835 (clobber (match_scratch:SI 0 "=rm"))]
5836 "ix86_match_ccmode (insn, CCGCmode)
5837 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5839 switch (get_attr_type (insn))
5842 if (operands[2] == constm1_rtx)
5843 return "inc{l}\t%0";
5844 else if (operands[2] == const1_rtx)
5845 return "dec{l}\t%0";
5850 if (! rtx_equal_p (operands[0], operands[1]))
5852 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5853 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5854 if ((INTVAL (operands[2]) == -128
5855 || (INTVAL (operands[2]) > 0
5856 && INTVAL (operands[2]) != 128)))
5857 return "sub{l}\t{%2, %0|%0, %2}";
5858 operands[2] = GEN_INT (-INTVAL (operands[2]));
5859 return "add{l}\t{%2, %0|%0, %2}";
5863 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5864 (const_string "incdec")
5865 (const_string "alu")))
5866 (set_attr "mode" "SI")])
5868 (define_insn "*addsi_5"
5869 [(set (reg FLAGS_REG)
5871 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5872 (match_operand:SI 2 "general_operand" "rmni"))
5874 (clobber (match_scratch:SI 0 "=r"))]
5875 "ix86_match_ccmode (insn, CCGOCmode)
5876 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5877 /* Current assemblers are broken and do not allow @GOTOFF in
5878 ought but a memory context. */
5879 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5881 switch (get_attr_type (insn))
5884 if (! rtx_equal_p (operands[0], operands[1]))
5886 if (operands[2] == const1_rtx)
5887 return "inc{l}\t%0";
5888 else if (operands[2] == constm1_rtx)
5889 return "dec{l}\t%0";
5894 if (! rtx_equal_p (operands[0], operands[1]))
5896 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5897 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5898 if (GET_CODE (operands[2]) == CONST_INT
5899 && (INTVAL (operands[2]) == 128
5900 || (INTVAL (operands[2]) < 0
5901 && INTVAL (operands[2]) != -128)))
5903 operands[2] = GEN_INT (-INTVAL (operands[2]));
5904 return "sub{l}\t{%2, %0|%0, %2}";
5906 return "add{l}\t{%2, %0|%0, %2}";
5910 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5911 (const_string "incdec")
5912 (const_string "alu")))
5913 (set_attr "mode" "SI")])
5915 (define_expand "addhi3"
5916 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5917 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5918 (match_operand:HI 2 "general_operand" "")))
5919 (clobber (reg:CC FLAGS_REG))])]
5920 "TARGET_HIMODE_MATH"
5921 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5923 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5924 ;; type optimizations enabled by define-splits. This is not important
5925 ;; for PII, and in fact harmful because of partial register stalls.
5927 (define_insn "*addhi_1_lea"
5928 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5929 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5930 (match_operand:HI 2 "general_operand" "ri,rm,lni")))
5931 (clobber (reg:CC FLAGS_REG))]
5932 "!TARGET_PARTIAL_REG_STALL
5933 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5935 switch (get_attr_type (insn))
5940 if (operands[2] == const1_rtx)
5941 return "inc{w}\t%0";
5942 else if (operands[2] == constm1_rtx)
5943 return "dec{w}\t%0";
5947 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5948 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5949 if (GET_CODE (operands[2]) == CONST_INT
5950 && (INTVAL (operands[2]) == 128
5951 || (INTVAL (operands[2]) < 0
5952 && INTVAL (operands[2]) != -128)))
5954 operands[2] = GEN_INT (-INTVAL (operands[2]));
5955 return "sub{w}\t{%2, %0|%0, %2}";
5957 return "add{w}\t{%2, %0|%0, %2}";
5961 (if_then_else (eq_attr "alternative" "2")
5962 (const_string "lea")
5963 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5964 (const_string "incdec")
5965 (const_string "alu"))))
5966 (set_attr "mode" "HI,HI,SI")])
5968 (define_insn "*addhi_1"
5969 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5970 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5971 (match_operand:HI 2 "general_operand" "ri,rm")))
5972 (clobber (reg:CC FLAGS_REG))]
5973 "TARGET_PARTIAL_REG_STALL
5974 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5976 switch (get_attr_type (insn))
5979 if (operands[2] == const1_rtx)
5980 return "inc{w}\t%0";
5981 else if (operands[2] == constm1_rtx)
5982 return "dec{w}\t%0";
5986 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5987 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5988 if (GET_CODE (operands[2]) == CONST_INT
5989 && (INTVAL (operands[2]) == 128
5990 || (INTVAL (operands[2]) < 0
5991 && INTVAL (operands[2]) != -128)))
5993 operands[2] = GEN_INT (-INTVAL (operands[2]));
5994 return "sub{w}\t{%2, %0|%0, %2}";
5996 return "add{w}\t{%2, %0|%0, %2}";
6000 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6001 (const_string "incdec")
6002 (const_string "alu")))
6003 (set_attr "mode" "HI")])
6005 (define_insn "*addhi_2"
6006 [(set (reg FLAGS_REG)
6008 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6009 (match_operand:HI 2 "general_operand" "rmni,rni"))
6011 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6012 (plus:HI (match_dup 1) (match_dup 2)))]
6013 "ix86_match_ccmode (insn, CCGOCmode)
6014 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6016 switch (get_attr_type (insn))
6019 if (operands[2] == const1_rtx)
6020 return "inc{w}\t%0";
6021 else if (operands[2] == constm1_rtx)
6022 return "dec{w}\t%0";
6026 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6027 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6028 if (GET_CODE (operands[2]) == CONST_INT
6029 && (INTVAL (operands[2]) == 128
6030 || (INTVAL (operands[2]) < 0
6031 && INTVAL (operands[2]) != -128)))
6033 operands[2] = GEN_INT (-INTVAL (operands[2]));
6034 return "sub{w}\t{%2, %0|%0, %2}";
6036 return "add{w}\t{%2, %0|%0, %2}";
6040 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6041 (const_string "incdec")
6042 (const_string "alu")))
6043 (set_attr "mode" "HI")])
6045 (define_insn "*addhi_3"
6046 [(set (reg FLAGS_REG)
6047 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6048 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6049 (clobber (match_scratch:HI 0 "=r"))]
6050 "ix86_match_ccmode (insn, CCZmode)
6051 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6053 switch (get_attr_type (insn))
6056 if (operands[2] == const1_rtx)
6057 return "inc{w}\t%0";
6058 else if (operands[2] == constm1_rtx)
6059 return "dec{w}\t%0";
6063 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6064 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6065 if (GET_CODE (operands[2]) == CONST_INT
6066 && (INTVAL (operands[2]) == 128
6067 || (INTVAL (operands[2]) < 0
6068 && INTVAL (operands[2]) != -128)))
6070 operands[2] = GEN_INT (-INTVAL (operands[2]));
6071 return "sub{w}\t{%2, %0|%0, %2}";
6073 return "add{w}\t{%2, %0|%0, %2}";
6077 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6078 (const_string "incdec")
6079 (const_string "alu")))
6080 (set_attr "mode" "HI")])
6082 ; See comments above addsi_3_imm for details.
6083 (define_insn "*addhi_4"
6084 [(set (reg FLAGS_REG)
6085 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6086 (match_operand:HI 2 "const_int_operand" "n")))
6087 (clobber (match_scratch:HI 0 "=rm"))]
6088 "ix86_match_ccmode (insn, CCGCmode)
6089 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6091 switch (get_attr_type (insn))
6094 if (operands[2] == constm1_rtx)
6095 return "inc{w}\t%0";
6096 else if (operands[2] == const1_rtx)
6097 return "dec{w}\t%0";
6102 if (! rtx_equal_p (operands[0], operands[1]))
6104 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6105 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6106 if ((INTVAL (operands[2]) == -128
6107 || (INTVAL (operands[2]) > 0
6108 && INTVAL (operands[2]) != 128)))
6109 return "sub{w}\t{%2, %0|%0, %2}";
6110 operands[2] = GEN_INT (-INTVAL (operands[2]));
6111 return "add{w}\t{%2, %0|%0, %2}";
6115 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6116 (const_string "incdec")
6117 (const_string "alu")))
6118 (set_attr "mode" "SI")])
6121 (define_insn "*addhi_5"
6122 [(set (reg FLAGS_REG)
6124 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6125 (match_operand:HI 2 "general_operand" "rmni"))
6127 (clobber (match_scratch:HI 0 "=r"))]
6128 "ix86_match_ccmode (insn, CCGOCmode)
6129 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6131 switch (get_attr_type (insn))
6134 if (operands[2] == const1_rtx)
6135 return "inc{w}\t%0";
6136 else if (operands[2] == constm1_rtx)
6137 return "dec{w}\t%0";
6141 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6142 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6143 if (GET_CODE (operands[2]) == CONST_INT
6144 && (INTVAL (operands[2]) == 128
6145 || (INTVAL (operands[2]) < 0
6146 && INTVAL (operands[2]) != -128)))
6148 operands[2] = GEN_INT (-INTVAL (operands[2]));
6149 return "sub{w}\t{%2, %0|%0, %2}";
6151 return "add{w}\t{%2, %0|%0, %2}";
6155 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6156 (const_string "incdec")
6157 (const_string "alu")))
6158 (set_attr "mode" "HI")])
6160 (define_expand "addqi3"
6161 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6162 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6163 (match_operand:QI 2 "general_operand" "")))
6164 (clobber (reg:CC FLAGS_REG))])]
6165 "TARGET_QIMODE_MATH"
6166 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6168 ;; %%% Potential partial reg stall on alternative 2. What to do?
6169 (define_insn "*addqi_1_lea"
6170 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6171 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6172 (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
6173 (clobber (reg:CC FLAGS_REG))]
6174 "!TARGET_PARTIAL_REG_STALL
6175 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6177 int widen = (which_alternative == 2);
6178 switch (get_attr_type (insn))
6183 if (operands[2] == const1_rtx)
6184 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6185 else if (operands[2] == constm1_rtx)
6186 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6190 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6191 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6192 if (GET_CODE (operands[2]) == CONST_INT
6193 && (INTVAL (operands[2]) == 128
6194 || (INTVAL (operands[2]) < 0
6195 && INTVAL (operands[2]) != -128)))
6197 operands[2] = GEN_INT (-INTVAL (operands[2]));
6199 return "sub{l}\t{%2, %k0|%k0, %2}";
6201 return "sub{b}\t{%2, %0|%0, %2}";
6204 return "add{l}\t{%k2, %k0|%k0, %k2}";
6206 return "add{b}\t{%2, %0|%0, %2}";
6210 (if_then_else (eq_attr "alternative" "3")
6211 (const_string "lea")
6212 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6213 (const_string "incdec")
6214 (const_string "alu"))))
6215 (set_attr "mode" "QI,QI,SI,SI")])
6217 (define_insn "*addqi_1"
6218 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6219 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6220 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6221 (clobber (reg:CC FLAGS_REG))]
6222 "TARGET_PARTIAL_REG_STALL
6223 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6225 int widen = (which_alternative == 2);
6226 switch (get_attr_type (insn))
6229 if (operands[2] == const1_rtx)
6230 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6231 else if (operands[2] == constm1_rtx)
6232 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6236 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6237 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6238 if (GET_CODE (operands[2]) == CONST_INT
6239 && (INTVAL (operands[2]) == 128
6240 || (INTVAL (operands[2]) < 0
6241 && INTVAL (operands[2]) != -128)))
6243 operands[2] = GEN_INT (-INTVAL (operands[2]));
6245 return "sub{l}\t{%2, %k0|%k0, %2}";
6247 return "sub{b}\t{%2, %0|%0, %2}";
6250 return "add{l}\t{%k2, %k0|%k0, %k2}";
6252 return "add{b}\t{%2, %0|%0, %2}";
6256 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6257 (const_string "incdec")
6258 (const_string "alu")))
6259 (set_attr "mode" "QI,QI,SI")])
6261 (define_insn "*addqi_1_slp"
6262 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6263 (plus:QI (match_dup 0)
6264 (match_operand:QI 1 "general_operand" "qn,qnm")))
6265 (clobber (reg:CC FLAGS_REG))]
6266 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6267 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6269 switch (get_attr_type (insn))
6272 if (operands[1] == const1_rtx)
6273 return "inc{b}\t%0";
6274 else if (operands[1] == constm1_rtx)
6275 return "dec{b}\t%0";
6279 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6280 if (GET_CODE (operands[1]) == CONST_INT
6281 && INTVAL (operands[1]) < 0)
6283 operands[1] = GEN_INT (-INTVAL (operands[1]));
6284 return "sub{b}\t{%1, %0|%0, %1}";
6286 return "add{b}\t{%1, %0|%0, %1}";
6290 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6291 (const_string "incdec")
6292 (const_string "alu1")))
6293 (set_attr "mode" "QI")])
6295 (define_insn "*addqi_2"
6296 [(set (reg FLAGS_REG)
6298 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6299 (match_operand:QI 2 "general_operand" "qmni,qni"))
6301 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6302 (plus:QI (match_dup 1) (match_dup 2)))]
6303 "ix86_match_ccmode (insn, CCGOCmode)
6304 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6306 switch (get_attr_type (insn))
6309 if (operands[2] == const1_rtx)
6310 return "inc{b}\t%0";
6311 else if (operands[2] == constm1_rtx
6312 || (GET_CODE (operands[2]) == CONST_INT
6313 && INTVAL (operands[2]) == 255))
6314 return "dec{b}\t%0";
6318 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6319 if (GET_CODE (operands[2]) == CONST_INT
6320 && INTVAL (operands[2]) < 0)
6322 operands[2] = GEN_INT (-INTVAL (operands[2]));
6323 return "sub{b}\t{%2, %0|%0, %2}";
6325 return "add{b}\t{%2, %0|%0, %2}";
6329 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6330 (const_string "incdec")
6331 (const_string "alu")))
6332 (set_attr "mode" "QI")])
6334 (define_insn "*addqi_3"
6335 [(set (reg FLAGS_REG)
6336 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6337 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6338 (clobber (match_scratch:QI 0 "=q"))]
6339 "ix86_match_ccmode (insn, CCZmode)
6340 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6342 switch (get_attr_type (insn))
6345 if (operands[2] == const1_rtx)
6346 return "inc{b}\t%0";
6347 else if (operands[2] == constm1_rtx
6348 || (GET_CODE (operands[2]) == CONST_INT
6349 && INTVAL (operands[2]) == 255))
6350 return "dec{b}\t%0";
6354 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6355 if (GET_CODE (operands[2]) == CONST_INT
6356 && INTVAL (operands[2]) < 0)
6358 operands[2] = GEN_INT (-INTVAL (operands[2]));
6359 return "sub{b}\t{%2, %0|%0, %2}";
6361 return "add{b}\t{%2, %0|%0, %2}";
6365 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6366 (const_string "incdec")
6367 (const_string "alu")))
6368 (set_attr "mode" "QI")])
6370 ; See comments above addsi_3_imm for details.
6371 (define_insn "*addqi_4"
6372 [(set (reg FLAGS_REG)
6373 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6374 (match_operand:QI 2 "const_int_operand" "n")))
6375 (clobber (match_scratch:QI 0 "=qm"))]
6376 "ix86_match_ccmode (insn, CCGCmode)
6377 && (INTVAL (operands[2]) & 0xff) != 0x80"
6379 switch (get_attr_type (insn))
6382 if (operands[2] == constm1_rtx
6383 || (GET_CODE (operands[2]) == CONST_INT
6384 && INTVAL (operands[2]) == 255))
6385 return "inc{b}\t%0";
6386 else if (operands[2] == const1_rtx)
6387 return "dec{b}\t%0";
6392 if (! rtx_equal_p (operands[0], operands[1]))
6394 if (INTVAL (operands[2]) < 0)
6396 operands[2] = GEN_INT (-INTVAL (operands[2]));
6397 return "add{b}\t{%2, %0|%0, %2}";
6399 return "sub{b}\t{%2, %0|%0, %2}";
6403 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6404 (const_string "incdec")
6405 (const_string "alu")))
6406 (set_attr "mode" "QI")])
6409 (define_insn "*addqi_5"
6410 [(set (reg FLAGS_REG)
6412 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6413 (match_operand:QI 2 "general_operand" "qmni"))
6415 (clobber (match_scratch:QI 0 "=q"))]
6416 "ix86_match_ccmode (insn, CCGOCmode)
6417 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6419 switch (get_attr_type (insn))
6422 if (operands[2] == const1_rtx)
6423 return "inc{b}\t%0";
6424 else if (operands[2] == constm1_rtx
6425 || (GET_CODE (operands[2]) == CONST_INT
6426 && INTVAL (operands[2]) == 255))
6427 return "dec{b}\t%0";
6431 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6432 if (GET_CODE (operands[2]) == CONST_INT
6433 && INTVAL (operands[2]) < 0)
6435 operands[2] = GEN_INT (-INTVAL (operands[2]));
6436 return "sub{b}\t{%2, %0|%0, %2}";
6438 return "add{b}\t{%2, %0|%0, %2}";
6442 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6443 (const_string "incdec")
6444 (const_string "alu")))
6445 (set_attr "mode" "QI")])
6448 (define_insn "addqi_ext_1"
6449 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6454 (match_operand 1 "ext_register_operand" "0")
6457 (match_operand:QI 2 "general_operand" "Qmn")))
6458 (clobber (reg:CC FLAGS_REG))]
6461 switch (get_attr_type (insn))
6464 if (operands[2] == const1_rtx)
6465 return "inc{b}\t%h0";
6466 else if (operands[2] == constm1_rtx
6467 || (GET_CODE (operands[2]) == CONST_INT
6468 && INTVAL (operands[2]) == 255))
6469 return "dec{b}\t%h0";
6473 return "add{b}\t{%2, %h0|%h0, %2}";
6477 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6478 (const_string "incdec")
6479 (const_string "alu")))
6480 (set_attr "mode" "QI")])
6482 (define_insn "*addqi_ext_1_rex64"
6483 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6488 (match_operand 1 "ext_register_operand" "0")
6491 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6492 (clobber (reg:CC FLAGS_REG))]
6495 switch (get_attr_type (insn))
6498 if (operands[2] == const1_rtx)
6499 return "inc{b}\t%h0";
6500 else if (operands[2] == constm1_rtx
6501 || (GET_CODE (operands[2]) == CONST_INT
6502 && INTVAL (operands[2]) == 255))
6503 return "dec{b}\t%h0";
6507 return "add{b}\t{%2, %h0|%h0, %2}";
6511 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6512 (const_string "incdec")
6513 (const_string "alu")))
6514 (set_attr "mode" "QI")])
6516 (define_insn "*addqi_ext_2"
6517 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6522 (match_operand 1 "ext_register_operand" "%0")
6526 (match_operand 2 "ext_register_operand" "Q")
6529 (clobber (reg:CC FLAGS_REG))]
6531 "add{b}\t{%h2, %h0|%h0, %h2}"
6532 [(set_attr "type" "alu")
6533 (set_attr "mode" "QI")])
6535 ;; The patterns that match these are at the end of this file.
6537 (define_expand "addxf3"
6538 [(set (match_operand:XF 0 "register_operand" "")
6539 (plus:XF (match_operand:XF 1 "register_operand" "")
6540 (match_operand:XF 2 "register_operand" "")))]
6544 (define_expand "adddf3"
6545 [(set (match_operand:DF 0 "register_operand" "")
6546 (plus:DF (match_operand:DF 1 "register_operand" "")
6547 (match_operand:DF 2 "nonimmediate_operand" "")))]
6548 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6551 (define_expand "addsf3"
6552 [(set (match_operand:SF 0 "register_operand" "")
6553 (plus:SF (match_operand:SF 1 "register_operand" "")
6554 (match_operand:SF 2 "nonimmediate_operand" "")))]
6555 "TARGET_80387 || TARGET_SSE_MATH"
6558 ;; Subtract instructions
6560 ;; %%% splits for subsidi3
6562 (define_expand "subdi3"
6563 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6564 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6565 (match_operand:DI 2 "x86_64_general_operand" "")))
6566 (clobber (reg:CC FLAGS_REG))])]
6568 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6570 (define_insn "*subdi3_1"
6571 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6572 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6573 (match_operand:DI 2 "general_operand" "roiF,riF")))
6574 (clobber (reg:CC FLAGS_REG))]
6575 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6579 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6580 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6581 (match_operand:DI 2 "general_operand" "")))
6582 (clobber (reg:CC FLAGS_REG))]
6583 "!TARGET_64BIT && reload_completed"
6584 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6585 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6586 (parallel [(set (match_dup 3)
6587 (minus:SI (match_dup 4)
6588 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6590 (clobber (reg:CC FLAGS_REG))])]
6591 "split_di (operands+0, 1, operands+0, operands+3);
6592 split_di (operands+1, 1, operands+1, operands+4);
6593 split_di (operands+2, 1, operands+2, operands+5);")
6595 (define_insn "subdi3_carry_rex64"
6596 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6597 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6598 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6599 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6600 (clobber (reg:CC FLAGS_REG))]
6601 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6602 "sbb{q}\t{%2, %0|%0, %2}"
6603 [(set_attr "type" "alu")
6604 (set_attr "pent_pair" "pu")
6605 (set_attr "mode" "DI")])
6607 (define_insn "*subdi_1_rex64"
6608 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6609 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6610 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6611 (clobber (reg:CC FLAGS_REG))]
6612 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6613 "sub{q}\t{%2, %0|%0, %2}"
6614 [(set_attr "type" "alu")
6615 (set_attr "mode" "DI")])
6617 (define_insn "*subdi_2_rex64"
6618 [(set (reg FLAGS_REG)
6620 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6621 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6623 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6624 (minus:DI (match_dup 1) (match_dup 2)))]
6625 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6626 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6627 "sub{q}\t{%2, %0|%0, %2}"
6628 [(set_attr "type" "alu")
6629 (set_attr "mode" "DI")])
6631 (define_insn "*subdi_3_rex63"
6632 [(set (reg FLAGS_REG)
6633 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6634 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6635 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6636 (minus:DI (match_dup 1) (match_dup 2)))]
6637 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6638 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6639 "sub{q}\t{%2, %0|%0, %2}"
6640 [(set_attr "type" "alu")
6641 (set_attr "mode" "DI")])
6643 (define_insn "subqi3_carry"
6644 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6645 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6646 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6647 (match_operand:QI 2 "general_operand" "qi,qm"))))
6648 (clobber (reg:CC FLAGS_REG))]
6649 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6650 "sbb{b}\t{%2, %0|%0, %2}"
6651 [(set_attr "type" "alu")
6652 (set_attr "pent_pair" "pu")
6653 (set_attr "mode" "QI")])
6655 (define_insn "subhi3_carry"
6656 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6657 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6658 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6659 (match_operand:HI 2 "general_operand" "ri,rm"))))
6660 (clobber (reg:CC FLAGS_REG))]
6661 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6662 "sbb{w}\t{%2, %0|%0, %2}"
6663 [(set_attr "type" "alu")
6664 (set_attr "pent_pair" "pu")
6665 (set_attr "mode" "HI")])
6667 (define_insn "subsi3_carry"
6668 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6669 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6670 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6671 (match_operand:SI 2 "general_operand" "ri,rm"))))
6672 (clobber (reg:CC FLAGS_REG))]
6673 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6674 "sbb{l}\t{%2, %0|%0, %2}"
6675 [(set_attr "type" "alu")
6676 (set_attr "pent_pair" "pu")
6677 (set_attr "mode" "SI")])
6679 (define_insn "subsi3_carry_zext"
6680 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6682 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6683 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6684 (match_operand:SI 2 "general_operand" "ri,rm")))))
6685 (clobber (reg:CC FLAGS_REG))]
6686 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6687 "sbb{l}\t{%2, %k0|%k0, %2}"
6688 [(set_attr "type" "alu")
6689 (set_attr "pent_pair" "pu")
6690 (set_attr "mode" "SI")])
6692 (define_expand "subsi3"
6693 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6694 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6695 (match_operand:SI 2 "general_operand" "")))
6696 (clobber (reg:CC FLAGS_REG))])]
6698 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6700 (define_insn "*subsi_1"
6701 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6702 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6703 (match_operand:SI 2 "general_operand" "ri,rm")))
6704 (clobber (reg:CC FLAGS_REG))]
6705 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6706 "sub{l}\t{%2, %0|%0, %2}"
6707 [(set_attr "type" "alu")
6708 (set_attr "mode" "SI")])
6710 (define_insn "*subsi_1_zext"
6711 [(set (match_operand:DI 0 "register_operand" "=r")
6713 (minus:SI (match_operand:SI 1 "register_operand" "0")
6714 (match_operand:SI 2 "general_operand" "rim"))))
6715 (clobber (reg:CC FLAGS_REG))]
6716 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6717 "sub{l}\t{%2, %k0|%k0, %2}"
6718 [(set_attr "type" "alu")
6719 (set_attr "mode" "SI")])
6721 (define_insn "*subsi_2"
6722 [(set (reg FLAGS_REG)
6724 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6725 (match_operand:SI 2 "general_operand" "ri,rm"))
6727 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6728 (minus:SI (match_dup 1) (match_dup 2)))]
6729 "ix86_match_ccmode (insn, CCGOCmode)
6730 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6731 "sub{l}\t{%2, %0|%0, %2}"
6732 [(set_attr "type" "alu")
6733 (set_attr "mode" "SI")])
6735 (define_insn "*subsi_2_zext"
6736 [(set (reg FLAGS_REG)
6738 (minus:SI (match_operand:SI 1 "register_operand" "0")
6739 (match_operand:SI 2 "general_operand" "rim"))
6741 (set (match_operand:DI 0 "register_operand" "=r")
6743 (minus:SI (match_dup 1)
6745 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6746 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6747 "sub{l}\t{%2, %k0|%k0, %2}"
6748 [(set_attr "type" "alu")
6749 (set_attr "mode" "SI")])
6751 (define_insn "*subsi_3"
6752 [(set (reg FLAGS_REG)
6753 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6754 (match_operand:SI 2 "general_operand" "ri,rm")))
6755 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6756 (minus:SI (match_dup 1) (match_dup 2)))]
6757 "ix86_match_ccmode (insn, CCmode)
6758 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6759 "sub{l}\t{%2, %0|%0, %2}"
6760 [(set_attr "type" "alu")
6761 (set_attr "mode" "SI")])
6763 (define_insn "*subsi_3_zext"
6764 [(set (reg FLAGS_REG)
6765 (compare (match_operand:SI 1 "register_operand" "0")
6766 (match_operand:SI 2 "general_operand" "rim")))
6767 (set (match_operand:DI 0 "register_operand" "=r")
6769 (minus:SI (match_dup 1)
6771 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6772 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6773 "sub{q}\t{%2, %0|%0, %2}"
6774 [(set_attr "type" "alu")
6775 (set_attr "mode" "DI")])
6777 (define_expand "subhi3"
6778 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6779 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6780 (match_operand:HI 2 "general_operand" "")))
6781 (clobber (reg:CC FLAGS_REG))])]
6782 "TARGET_HIMODE_MATH"
6783 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6785 (define_insn "*subhi_1"
6786 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6787 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6788 (match_operand:HI 2 "general_operand" "ri,rm")))
6789 (clobber (reg:CC FLAGS_REG))]
6790 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6791 "sub{w}\t{%2, %0|%0, %2}"
6792 [(set_attr "type" "alu")
6793 (set_attr "mode" "HI")])
6795 (define_insn "*subhi_2"
6796 [(set (reg FLAGS_REG)
6798 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6799 (match_operand:HI 2 "general_operand" "ri,rm"))
6801 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6802 (minus:HI (match_dup 1) (match_dup 2)))]
6803 "ix86_match_ccmode (insn, CCGOCmode)
6804 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6805 "sub{w}\t{%2, %0|%0, %2}"
6806 [(set_attr "type" "alu")
6807 (set_attr "mode" "HI")])
6809 (define_insn "*subhi_3"
6810 [(set (reg FLAGS_REG)
6811 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6812 (match_operand:HI 2 "general_operand" "ri,rm")))
6813 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6814 (minus:HI (match_dup 1) (match_dup 2)))]
6815 "ix86_match_ccmode (insn, CCmode)
6816 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6817 "sub{w}\t{%2, %0|%0, %2}"
6818 [(set_attr "type" "alu")
6819 (set_attr "mode" "HI")])
6821 (define_expand "subqi3"
6822 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6823 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6824 (match_operand:QI 2 "general_operand" "")))
6825 (clobber (reg:CC FLAGS_REG))])]
6826 "TARGET_QIMODE_MATH"
6827 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6829 (define_insn "*subqi_1"
6830 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6831 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6832 (match_operand:QI 2 "general_operand" "qn,qmn")))
6833 (clobber (reg:CC FLAGS_REG))]
6834 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6835 "sub{b}\t{%2, %0|%0, %2}"
6836 [(set_attr "type" "alu")
6837 (set_attr "mode" "QI")])
6839 (define_insn "*subqi_1_slp"
6840 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6841 (minus:QI (match_dup 0)
6842 (match_operand:QI 1 "general_operand" "qn,qmn")))
6843 (clobber (reg:CC FLAGS_REG))]
6844 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6845 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6846 "sub{b}\t{%1, %0|%0, %1}"
6847 [(set_attr "type" "alu1")
6848 (set_attr "mode" "QI")])
6850 (define_insn "*subqi_2"
6851 [(set (reg FLAGS_REG)
6853 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6854 (match_operand:QI 2 "general_operand" "qi,qm"))
6856 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6857 (minus:HI (match_dup 1) (match_dup 2)))]
6858 "ix86_match_ccmode (insn, CCGOCmode)
6859 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6860 "sub{b}\t{%2, %0|%0, %2}"
6861 [(set_attr "type" "alu")
6862 (set_attr "mode" "QI")])
6864 (define_insn "*subqi_3"
6865 [(set (reg FLAGS_REG)
6866 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6867 (match_operand:QI 2 "general_operand" "qi,qm")))
6868 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6869 (minus:HI (match_dup 1) (match_dup 2)))]
6870 "ix86_match_ccmode (insn, CCmode)
6871 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6872 "sub{b}\t{%2, %0|%0, %2}"
6873 [(set_attr "type" "alu")
6874 (set_attr "mode" "QI")])
6876 ;; The patterns that match these are at the end of this file.
6878 (define_expand "subxf3"
6879 [(set (match_operand:XF 0 "register_operand" "")
6880 (minus:XF (match_operand:XF 1 "register_operand" "")
6881 (match_operand:XF 2 "register_operand" "")))]
6885 (define_expand "subdf3"
6886 [(set (match_operand:DF 0 "register_operand" "")
6887 (minus:DF (match_operand:DF 1 "register_operand" "")
6888 (match_operand:DF 2 "nonimmediate_operand" "")))]
6889 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6892 (define_expand "subsf3"
6893 [(set (match_operand:SF 0 "register_operand" "")
6894 (minus:SF (match_operand:SF 1 "register_operand" "")
6895 (match_operand:SF 2 "nonimmediate_operand" "")))]
6896 "TARGET_80387 || TARGET_SSE_MATH"
6899 ;; Multiply instructions
6901 (define_expand "muldi3"
6902 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6903 (mult:DI (match_operand:DI 1 "register_operand" "")
6904 (match_operand:DI 2 "x86_64_general_operand" "")))
6905 (clobber (reg:CC FLAGS_REG))])]
6909 (define_insn "*muldi3_1_rex64"
6910 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6911 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6912 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6913 (clobber (reg:CC FLAGS_REG))]
6915 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6917 imul{q}\t{%2, %1, %0|%0, %1, %2}
6918 imul{q}\t{%2, %1, %0|%0, %1, %2}
6919 imul{q}\t{%2, %0|%0, %2}"
6920 [(set_attr "type" "imul")
6921 (set_attr "prefix_0f" "0,0,1")
6922 (set (attr "athlon_decode")
6923 (cond [(eq_attr "cpu" "athlon")
6924 (const_string "vector")
6925 (eq_attr "alternative" "1")
6926 (const_string "vector")
6927 (and (eq_attr "alternative" "2")
6928 (match_operand 1 "memory_operand" ""))
6929 (const_string "vector")]
6930 (const_string "direct")))
6931 (set_attr "mode" "DI")])
6933 (define_expand "mulsi3"
6934 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6935 (mult:SI (match_operand:SI 1 "register_operand" "")
6936 (match_operand:SI 2 "general_operand" "")))
6937 (clobber (reg:CC FLAGS_REG))])]
6941 (define_insn "*mulsi3_1"
6942 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6943 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6944 (match_operand:SI 2 "general_operand" "K,i,mr")))
6945 (clobber (reg:CC FLAGS_REG))]
6946 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6948 imul{l}\t{%2, %1, %0|%0, %1, %2}
6949 imul{l}\t{%2, %1, %0|%0, %1, %2}
6950 imul{l}\t{%2, %0|%0, %2}"
6951 [(set_attr "type" "imul")
6952 (set_attr "prefix_0f" "0,0,1")
6953 (set (attr "athlon_decode")
6954 (cond [(eq_attr "cpu" "athlon")
6955 (const_string "vector")
6956 (eq_attr "alternative" "1")
6957 (const_string "vector")
6958 (and (eq_attr "alternative" "2")
6959 (match_operand 1 "memory_operand" ""))
6960 (const_string "vector")]
6961 (const_string "direct")))
6962 (set_attr "mode" "SI")])
6964 (define_insn "*mulsi3_1_zext"
6965 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6967 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6968 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6969 (clobber (reg:CC FLAGS_REG))]
6971 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6973 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6974 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6975 imul{l}\t{%2, %k0|%k0, %2}"
6976 [(set_attr "type" "imul")
6977 (set_attr "prefix_0f" "0,0,1")
6978 (set (attr "athlon_decode")
6979 (cond [(eq_attr "cpu" "athlon")
6980 (const_string "vector")
6981 (eq_attr "alternative" "1")
6982 (const_string "vector")
6983 (and (eq_attr "alternative" "2")
6984 (match_operand 1 "memory_operand" ""))
6985 (const_string "vector")]
6986 (const_string "direct")))
6987 (set_attr "mode" "SI")])
6989 (define_expand "mulhi3"
6990 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6991 (mult:HI (match_operand:HI 1 "register_operand" "")
6992 (match_operand:HI 2 "general_operand" "")))
6993 (clobber (reg:CC FLAGS_REG))])]
6994 "TARGET_HIMODE_MATH"
6997 (define_insn "*mulhi3_1"
6998 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6999 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7000 (match_operand:HI 2 "general_operand" "K,i,mr")))
7001 (clobber (reg:CC FLAGS_REG))]
7002 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7004 imul{w}\t{%2, %1, %0|%0, %1, %2}
7005 imul{w}\t{%2, %1, %0|%0, %1, %2}
7006 imul{w}\t{%2, %0|%0, %2}"
7007 [(set_attr "type" "imul")
7008 (set_attr "prefix_0f" "0,0,1")
7009 (set (attr "athlon_decode")
7010 (cond [(eq_attr "cpu" "athlon")
7011 (const_string "vector")
7012 (eq_attr "alternative" "1,2")
7013 (const_string "vector")]
7014 (const_string "direct")))
7015 (set_attr "mode" "HI")])
7017 (define_expand "mulqi3"
7018 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7019 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7020 (match_operand:QI 2 "register_operand" "")))
7021 (clobber (reg:CC FLAGS_REG))])]
7022 "TARGET_QIMODE_MATH"
7025 (define_insn "*mulqi3_1"
7026 [(set (match_operand:QI 0 "register_operand" "=a")
7027 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7028 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7029 (clobber (reg:CC FLAGS_REG))]
7031 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7033 [(set_attr "type" "imul")
7034 (set_attr "length_immediate" "0")
7035 (set (attr "athlon_decode")
7036 (if_then_else (eq_attr "cpu" "athlon")
7037 (const_string "vector")
7038 (const_string "direct")))
7039 (set_attr "mode" "QI")])
7041 (define_expand "umulqihi3"
7042 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7043 (mult:HI (zero_extend:HI
7044 (match_operand:QI 1 "nonimmediate_operand" ""))
7046 (match_operand:QI 2 "register_operand" ""))))
7047 (clobber (reg:CC FLAGS_REG))])]
7048 "TARGET_QIMODE_MATH"
7051 (define_insn "*umulqihi3_1"
7052 [(set (match_operand:HI 0 "register_operand" "=a")
7053 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7054 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7055 (clobber (reg:CC FLAGS_REG))]
7057 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7059 [(set_attr "type" "imul")
7060 (set_attr "length_immediate" "0")
7061 (set (attr "athlon_decode")
7062 (if_then_else (eq_attr "cpu" "athlon")
7063 (const_string "vector")
7064 (const_string "direct")))
7065 (set_attr "mode" "QI")])
7067 (define_expand "mulqihi3"
7068 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7069 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7070 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7071 (clobber (reg:CC FLAGS_REG))])]
7072 "TARGET_QIMODE_MATH"
7075 (define_insn "*mulqihi3_insn"
7076 [(set (match_operand:HI 0 "register_operand" "=a")
7077 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7078 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7079 (clobber (reg:CC FLAGS_REG))]
7081 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7083 [(set_attr "type" "imul")
7084 (set_attr "length_immediate" "0")
7085 (set (attr "athlon_decode")
7086 (if_then_else (eq_attr "cpu" "athlon")
7087 (const_string "vector")
7088 (const_string "direct")))
7089 (set_attr "mode" "QI")])
7091 (define_expand "umulditi3"
7092 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7093 (mult:TI (zero_extend:TI
7094 (match_operand:DI 1 "nonimmediate_operand" ""))
7096 (match_operand:DI 2 "register_operand" ""))))
7097 (clobber (reg:CC FLAGS_REG))])]
7101 (define_insn "*umulditi3_insn"
7102 [(set (match_operand:TI 0 "register_operand" "=A")
7103 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7104 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7105 (clobber (reg:CC FLAGS_REG))]
7107 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7109 [(set_attr "type" "imul")
7110 (set_attr "length_immediate" "0")
7111 (set (attr "athlon_decode")
7112 (if_then_else (eq_attr "cpu" "athlon")
7113 (const_string "vector")
7114 (const_string "double")))
7115 (set_attr "mode" "DI")])
7117 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7118 (define_expand "umulsidi3"
7119 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7120 (mult:DI (zero_extend:DI
7121 (match_operand:SI 1 "nonimmediate_operand" ""))
7123 (match_operand:SI 2 "register_operand" ""))))
7124 (clobber (reg:CC FLAGS_REG))])]
7128 (define_insn "*umulsidi3_insn"
7129 [(set (match_operand:DI 0 "register_operand" "=A")
7130 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7131 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7132 (clobber (reg:CC FLAGS_REG))]
7134 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7136 [(set_attr "type" "imul")
7137 (set_attr "length_immediate" "0")
7138 (set (attr "athlon_decode")
7139 (if_then_else (eq_attr "cpu" "athlon")
7140 (const_string "vector")
7141 (const_string "double")))
7142 (set_attr "mode" "SI")])
7144 (define_expand "mulditi3"
7145 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7146 (mult:TI (sign_extend:TI
7147 (match_operand:DI 1 "nonimmediate_operand" ""))
7149 (match_operand:DI 2 "register_operand" ""))))
7150 (clobber (reg:CC FLAGS_REG))])]
7154 (define_insn "*mulditi3_insn"
7155 [(set (match_operand:TI 0 "register_operand" "=A")
7156 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7157 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7158 (clobber (reg:CC FLAGS_REG))]
7160 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7162 [(set_attr "type" "imul")
7163 (set_attr "length_immediate" "0")
7164 (set (attr "athlon_decode")
7165 (if_then_else (eq_attr "cpu" "athlon")
7166 (const_string "vector")
7167 (const_string "double")))
7168 (set_attr "mode" "DI")])
7170 (define_expand "mulsidi3"
7171 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7172 (mult:DI (sign_extend:DI
7173 (match_operand:SI 1 "nonimmediate_operand" ""))
7175 (match_operand:SI 2 "register_operand" ""))))
7176 (clobber (reg:CC FLAGS_REG))])]
7180 (define_insn "*mulsidi3_insn"
7181 [(set (match_operand:DI 0 "register_operand" "=A")
7182 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7183 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7184 (clobber (reg:CC FLAGS_REG))]
7186 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7188 [(set_attr "type" "imul")
7189 (set_attr "length_immediate" "0")
7190 (set (attr "athlon_decode")
7191 (if_then_else (eq_attr "cpu" "athlon")
7192 (const_string "vector")
7193 (const_string "double")))
7194 (set_attr "mode" "SI")])
7196 (define_expand "umuldi3_highpart"
7197 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7200 (mult:TI (zero_extend:TI
7201 (match_operand:DI 1 "nonimmediate_operand" ""))
7203 (match_operand:DI 2 "register_operand" "")))
7205 (clobber (match_scratch:DI 3 ""))
7206 (clobber (reg:CC FLAGS_REG))])]
7210 (define_insn "*umuldi3_highpart_rex64"
7211 [(set (match_operand:DI 0 "register_operand" "=d")
7214 (mult:TI (zero_extend:TI
7215 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7217 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7219 (clobber (match_scratch:DI 3 "=1"))
7220 (clobber (reg:CC FLAGS_REG))]
7222 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7224 [(set_attr "type" "imul")
7225 (set_attr "length_immediate" "0")
7226 (set (attr "athlon_decode")
7227 (if_then_else (eq_attr "cpu" "athlon")
7228 (const_string "vector")
7229 (const_string "double")))
7230 (set_attr "mode" "DI")])
7232 (define_expand "umulsi3_highpart"
7233 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7236 (mult:DI (zero_extend:DI
7237 (match_operand:SI 1 "nonimmediate_operand" ""))
7239 (match_operand:SI 2 "register_operand" "")))
7241 (clobber (match_scratch:SI 3 ""))
7242 (clobber (reg:CC FLAGS_REG))])]
7246 (define_insn "*umulsi3_highpart_insn"
7247 [(set (match_operand:SI 0 "register_operand" "=d")
7250 (mult:DI (zero_extend:DI
7251 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7253 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7255 (clobber (match_scratch:SI 3 "=1"))
7256 (clobber (reg:CC FLAGS_REG))]
7257 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7259 [(set_attr "type" "imul")
7260 (set_attr "length_immediate" "0")
7261 (set (attr "athlon_decode")
7262 (if_then_else (eq_attr "cpu" "athlon")
7263 (const_string "vector")
7264 (const_string "double")))
7265 (set_attr "mode" "SI")])
7267 (define_insn "*umulsi3_highpart_zext"
7268 [(set (match_operand:DI 0 "register_operand" "=d")
7269 (zero_extend:DI (truncate:SI
7271 (mult:DI (zero_extend:DI
7272 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7274 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7276 (clobber (match_scratch:SI 3 "=1"))
7277 (clobber (reg:CC FLAGS_REG))]
7279 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7281 [(set_attr "type" "imul")
7282 (set_attr "length_immediate" "0")
7283 (set (attr "athlon_decode")
7284 (if_then_else (eq_attr "cpu" "athlon")
7285 (const_string "vector")
7286 (const_string "double")))
7287 (set_attr "mode" "SI")])
7289 (define_expand "smuldi3_highpart"
7290 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7293 (mult:TI (sign_extend:TI
7294 (match_operand:DI 1 "nonimmediate_operand" ""))
7296 (match_operand:DI 2 "register_operand" "")))
7298 (clobber (match_scratch:DI 3 ""))
7299 (clobber (reg:CC FLAGS_REG))])]
7303 (define_insn "*smuldi3_highpart_rex64"
7304 [(set (match_operand:DI 0 "register_operand" "=d")
7307 (mult:TI (sign_extend:TI
7308 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7310 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7312 (clobber (match_scratch:DI 3 "=1"))
7313 (clobber (reg:CC FLAGS_REG))]
7315 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7317 [(set_attr "type" "imul")
7318 (set (attr "athlon_decode")
7319 (if_then_else (eq_attr "cpu" "athlon")
7320 (const_string "vector")
7321 (const_string "double")))
7322 (set_attr "mode" "DI")])
7324 (define_expand "smulsi3_highpart"
7325 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7328 (mult:DI (sign_extend:DI
7329 (match_operand:SI 1 "nonimmediate_operand" ""))
7331 (match_operand:SI 2 "register_operand" "")))
7333 (clobber (match_scratch:SI 3 ""))
7334 (clobber (reg:CC FLAGS_REG))])]
7338 (define_insn "*smulsi3_highpart_insn"
7339 [(set (match_operand:SI 0 "register_operand" "=d")
7342 (mult:DI (sign_extend:DI
7343 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7345 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7347 (clobber (match_scratch:SI 3 "=1"))
7348 (clobber (reg:CC FLAGS_REG))]
7349 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7351 [(set_attr "type" "imul")
7352 (set (attr "athlon_decode")
7353 (if_then_else (eq_attr "cpu" "athlon")
7354 (const_string "vector")
7355 (const_string "double")))
7356 (set_attr "mode" "SI")])
7358 (define_insn "*smulsi3_highpart_zext"
7359 [(set (match_operand:DI 0 "register_operand" "=d")
7360 (zero_extend:DI (truncate:SI
7362 (mult:DI (sign_extend:DI
7363 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7365 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7367 (clobber (match_scratch:SI 3 "=1"))
7368 (clobber (reg:CC FLAGS_REG))]
7370 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7372 [(set_attr "type" "imul")
7373 (set (attr "athlon_decode")
7374 (if_then_else (eq_attr "cpu" "athlon")
7375 (const_string "vector")
7376 (const_string "double")))
7377 (set_attr "mode" "SI")])
7379 ;; The patterns that match these are at the end of this file.
7381 (define_expand "mulxf3"
7382 [(set (match_operand:XF 0 "register_operand" "")
7383 (mult:XF (match_operand:XF 1 "register_operand" "")
7384 (match_operand:XF 2 "register_operand" "")))]
7388 (define_expand "muldf3"
7389 [(set (match_operand:DF 0 "register_operand" "")
7390 (mult:DF (match_operand:DF 1 "register_operand" "")
7391 (match_operand:DF 2 "nonimmediate_operand" "")))]
7392 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7395 (define_expand "mulsf3"
7396 [(set (match_operand:SF 0 "register_operand" "")
7397 (mult:SF (match_operand:SF 1 "register_operand" "")
7398 (match_operand:SF 2 "nonimmediate_operand" "")))]
7399 "TARGET_80387 || TARGET_SSE_MATH"
7402 ;; Divide instructions
7404 (define_insn "divqi3"
7405 [(set (match_operand:QI 0 "register_operand" "=a")
7406 (div:QI (match_operand:HI 1 "register_operand" "0")
7407 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7408 (clobber (reg:CC FLAGS_REG))]
7409 "TARGET_QIMODE_MATH"
7411 [(set_attr "type" "idiv")
7412 (set_attr "mode" "QI")])
7414 (define_insn "udivqi3"
7415 [(set (match_operand:QI 0 "register_operand" "=a")
7416 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7417 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7418 (clobber (reg:CC FLAGS_REG))]
7419 "TARGET_QIMODE_MATH"
7421 [(set_attr "type" "idiv")
7422 (set_attr "mode" "QI")])
7424 ;; The patterns that match these are at the end of this file.
7426 (define_expand "divxf3"
7427 [(set (match_operand:XF 0 "register_operand" "")
7428 (div:XF (match_operand:XF 1 "register_operand" "")
7429 (match_operand:XF 2 "register_operand" "")))]
7433 (define_expand "divdf3"
7434 [(set (match_operand:DF 0 "register_operand" "")
7435 (div:DF (match_operand:DF 1 "register_operand" "")
7436 (match_operand:DF 2 "nonimmediate_operand" "")))]
7437 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7440 (define_expand "divsf3"
7441 [(set (match_operand:SF 0 "register_operand" "")
7442 (div:SF (match_operand:SF 1 "register_operand" "")
7443 (match_operand:SF 2 "nonimmediate_operand" "")))]
7444 "TARGET_80387 || TARGET_SSE_MATH"
7447 ;; Remainder instructions.
7449 (define_expand "divmoddi4"
7450 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7451 (div:DI (match_operand:DI 1 "register_operand" "")
7452 (match_operand:DI 2 "nonimmediate_operand" "")))
7453 (set (match_operand:DI 3 "register_operand" "")
7454 (mod:DI (match_dup 1) (match_dup 2)))
7455 (clobber (reg:CC FLAGS_REG))])]
7459 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7460 ;; Penalize eax case slightly because it results in worse scheduling
7462 (define_insn "*divmoddi4_nocltd_rex64"
7463 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7464 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7465 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7466 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7467 (mod:DI (match_dup 2) (match_dup 3)))
7468 (clobber (reg:CC FLAGS_REG))]
7469 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7471 [(set_attr "type" "multi")])
7473 (define_insn "*divmoddi4_cltd_rex64"
7474 [(set (match_operand:DI 0 "register_operand" "=a")
7475 (div:DI (match_operand:DI 2 "register_operand" "a")
7476 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7477 (set (match_operand:DI 1 "register_operand" "=&d")
7478 (mod:DI (match_dup 2) (match_dup 3)))
7479 (clobber (reg:CC FLAGS_REG))]
7480 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7482 [(set_attr "type" "multi")])
7484 (define_insn "*divmoddi_noext_rex64"
7485 [(set (match_operand:DI 0 "register_operand" "=a")
7486 (div:DI (match_operand:DI 1 "register_operand" "0")
7487 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7488 (set (match_operand:DI 3 "register_operand" "=d")
7489 (mod:DI (match_dup 1) (match_dup 2)))
7490 (use (match_operand:DI 4 "register_operand" "3"))
7491 (clobber (reg:CC FLAGS_REG))]
7494 [(set_attr "type" "idiv")
7495 (set_attr "mode" "DI")])
7498 [(set (match_operand:DI 0 "register_operand" "")
7499 (div:DI (match_operand:DI 1 "register_operand" "")
7500 (match_operand:DI 2 "nonimmediate_operand" "")))
7501 (set (match_operand:DI 3 "register_operand" "")
7502 (mod:DI (match_dup 1) (match_dup 2)))
7503 (clobber (reg:CC FLAGS_REG))]
7504 "TARGET_64BIT && reload_completed"
7505 [(parallel [(set (match_dup 3)
7506 (ashiftrt:DI (match_dup 4) (const_int 63)))
7507 (clobber (reg:CC FLAGS_REG))])
7508 (parallel [(set (match_dup 0)
7509 (div:DI (reg:DI 0) (match_dup 2)))
7511 (mod:DI (reg:DI 0) (match_dup 2)))
7513 (clobber (reg:CC FLAGS_REG))])]
7515 /* Avoid use of cltd in favor of a mov+shift. */
7516 if (!TARGET_USE_CLTD && !optimize_size)
7518 if (true_regnum (operands[1]))
7519 emit_move_insn (operands[0], operands[1]);
7521 emit_move_insn (operands[3], operands[1]);
7522 operands[4] = operands[3];
7526 if (true_regnum (operands[1]))
7528 operands[4] = operands[1];
7533 (define_expand "divmodsi4"
7534 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7535 (div:SI (match_operand:SI 1 "register_operand" "")
7536 (match_operand:SI 2 "nonimmediate_operand" "")))
7537 (set (match_operand:SI 3 "register_operand" "")
7538 (mod:SI (match_dup 1) (match_dup 2)))
7539 (clobber (reg:CC FLAGS_REG))])]
7543 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7544 ;; Penalize eax case slightly because it results in worse scheduling
7546 (define_insn "*divmodsi4_nocltd"
7547 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7548 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7549 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7550 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7551 (mod:SI (match_dup 2) (match_dup 3)))
7552 (clobber (reg:CC FLAGS_REG))]
7553 "!optimize_size && !TARGET_USE_CLTD"
7555 [(set_attr "type" "multi")])
7557 (define_insn "*divmodsi4_cltd"
7558 [(set (match_operand:SI 0 "register_operand" "=a")
7559 (div:SI (match_operand:SI 2 "register_operand" "a")
7560 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7561 (set (match_operand:SI 1 "register_operand" "=&d")
7562 (mod:SI (match_dup 2) (match_dup 3)))
7563 (clobber (reg:CC FLAGS_REG))]
7564 "optimize_size || TARGET_USE_CLTD"
7566 [(set_attr "type" "multi")])
7568 (define_insn "*divmodsi_noext"
7569 [(set (match_operand:SI 0 "register_operand" "=a")
7570 (div:SI (match_operand:SI 1 "register_operand" "0")
7571 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7572 (set (match_operand:SI 3 "register_operand" "=d")
7573 (mod:SI (match_dup 1) (match_dup 2)))
7574 (use (match_operand:SI 4 "register_operand" "3"))
7575 (clobber (reg:CC FLAGS_REG))]
7578 [(set_attr "type" "idiv")
7579 (set_attr "mode" "SI")])
7582 [(set (match_operand:SI 0 "register_operand" "")
7583 (div:SI (match_operand:SI 1 "register_operand" "")
7584 (match_operand:SI 2 "nonimmediate_operand" "")))
7585 (set (match_operand:SI 3 "register_operand" "")
7586 (mod:SI (match_dup 1) (match_dup 2)))
7587 (clobber (reg:CC FLAGS_REG))]
7589 [(parallel [(set (match_dup 3)
7590 (ashiftrt:SI (match_dup 4) (const_int 31)))
7591 (clobber (reg:CC FLAGS_REG))])
7592 (parallel [(set (match_dup 0)
7593 (div:SI (reg:SI 0) (match_dup 2)))
7595 (mod:SI (reg:SI 0) (match_dup 2)))
7597 (clobber (reg:CC FLAGS_REG))])]
7599 /* Avoid use of cltd in favor of a mov+shift. */
7600 if (!TARGET_USE_CLTD && !optimize_size)
7602 if (true_regnum (operands[1]))
7603 emit_move_insn (operands[0], operands[1]);
7605 emit_move_insn (operands[3], operands[1]);
7606 operands[4] = operands[3];
7610 if (true_regnum (operands[1]))
7612 operands[4] = operands[1];
7616 (define_insn "divmodhi4"
7617 [(set (match_operand:HI 0 "register_operand" "=a")
7618 (div:HI (match_operand:HI 1 "register_operand" "0")
7619 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7620 (set (match_operand:HI 3 "register_operand" "=&d")
7621 (mod:HI (match_dup 1) (match_dup 2)))
7622 (clobber (reg:CC FLAGS_REG))]
7623 "TARGET_HIMODE_MATH"
7625 [(set_attr "type" "multi")
7626 (set_attr "length_immediate" "0")
7627 (set_attr "mode" "SI")])
7629 (define_insn "udivmoddi4"
7630 [(set (match_operand:DI 0 "register_operand" "=a")
7631 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7632 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7633 (set (match_operand:DI 3 "register_operand" "=&d")
7634 (umod:DI (match_dup 1) (match_dup 2)))
7635 (clobber (reg:CC FLAGS_REG))]
7637 "xor{q}\t%3, %3\;div{q}\t%2"
7638 [(set_attr "type" "multi")
7639 (set_attr "length_immediate" "0")
7640 (set_attr "mode" "DI")])
7642 (define_insn "*udivmoddi4_noext"
7643 [(set (match_operand:DI 0 "register_operand" "=a")
7644 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7645 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7646 (set (match_operand:DI 3 "register_operand" "=d")
7647 (umod:DI (match_dup 1) (match_dup 2)))
7649 (clobber (reg:CC FLAGS_REG))]
7652 [(set_attr "type" "idiv")
7653 (set_attr "mode" "DI")])
7656 [(set (match_operand:DI 0 "register_operand" "")
7657 (udiv:DI (match_operand:DI 1 "register_operand" "")
7658 (match_operand:DI 2 "nonimmediate_operand" "")))
7659 (set (match_operand:DI 3 "register_operand" "")
7660 (umod:DI (match_dup 1) (match_dup 2)))
7661 (clobber (reg:CC FLAGS_REG))]
7662 "TARGET_64BIT && reload_completed"
7663 [(set (match_dup 3) (const_int 0))
7664 (parallel [(set (match_dup 0)
7665 (udiv:DI (match_dup 1) (match_dup 2)))
7667 (umod:DI (match_dup 1) (match_dup 2)))
7669 (clobber (reg:CC FLAGS_REG))])]
7672 (define_insn "udivmodsi4"
7673 [(set (match_operand:SI 0 "register_operand" "=a")
7674 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7675 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7676 (set (match_operand:SI 3 "register_operand" "=&d")
7677 (umod:SI (match_dup 1) (match_dup 2)))
7678 (clobber (reg:CC FLAGS_REG))]
7680 "xor{l}\t%3, %3\;div{l}\t%2"
7681 [(set_attr "type" "multi")
7682 (set_attr "length_immediate" "0")
7683 (set_attr "mode" "SI")])
7685 (define_insn "*udivmodsi4_noext"
7686 [(set (match_operand:SI 0 "register_operand" "=a")
7687 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7688 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7689 (set (match_operand:SI 3 "register_operand" "=d")
7690 (umod:SI (match_dup 1) (match_dup 2)))
7692 (clobber (reg:CC FLAGS_REG))]
7695 [(set_attr "type" "idiv")
7696 (set_attr "mode" "SI")])
7699 [(set (match_operand:SI 0 "register_operand" "")
7700 (udiv:SI (match_operand:SI 1 "register_operand" "")
7701 (match_operand:SI 2 "nonimmediate_operand" "")))
7702 (set (match_operand:SI 3 "register_operand" "")
7703 (umod:SI (match_dup 1) (match_dup 2)))
7704 (clobber (reg:CC FLAGS_REG))]
7706 [(set (match_dup 3) (const_int 0))
7707 (parallel [(set (match_dup 0)
7708 (udiv:SI (match_dup 1) (match_dup 2)))
7710 (umod:SI (match_dup 1) (match_dup 2)))
7712 (clobber (reg:CC FLAGS_REG))])]
7715 (define_expand "udivmodhi4"
7716 [(set (match_dup 4) (const_int 0))
7717 (parallel [(set (match_operand:HI 0 "register_operand" "")
7718 (udiv:HI (match_operand:HI 1 "register_operand" "")
7719 (match_operand:HI 2 "nonimmediate_operand" "")))
7720 (set (match_operand:HI 3 "register_operand" "")
7721 (umod:HI (match_dup 1) (match_dup 2)))
7723 (clobber (reg:CC FLAGS_REG))])]
7724 "TARGET_HIMODE_MATH"
7725 "operands[4] = gen_reg_rtx (HImode);")
7727 (define_insn "*udivmodhi_noext"
7728 [(set (match_operand:HI 0 "register_operand" "=a")
7729 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7730 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7731 (set (match_operand:HI 3 "register_operand" "=d")
7732 (umod:HI (match_dup 1) (match_dup 2)))
7733 (use (match_operand:HI 4 "register_operand" "3"))
7734 (clobber (reg:CC FLAGS_REG))]
7737 [(set_attr "type" "idiv")
7738 (set_attr "mode" "HI")])
7740 ;; We cannot use div/idiv for double division, because it causes
7741 ;; "division by zero" on the overflow and that's not what we expect
7742 ;; from truncate. Because true (non truncating) double division is
7743 ;; never generated, we can't create this insn anyway.
7746 ; [(set (match_operand:SI 0 "register_operand" "=a")
7748 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7750 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7751 ; (set (match_operand:SI 3 "register_operand" "=d")
7753 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7754 ; (clobber (reg:CC FLAGS_REG))]
7756 ; "div{l}\t{%2, %0|%0, %2}"
7757 ; [(set_attr "type" "idiv")])
7759 ;;- Logical AND instructions
7761 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7762 ;; Note that this excludes ah.
7764 (define_insn "*testdi_1_rex64"
7765 [(set (reg FLAGS_REG)
7767 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7768 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7770 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7771 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7773 test{l}\t{%k1, %k0|%k0, %k1}
7774 test{l}\t{%k1, %k0|%k0, %k1}
7775 test{q}\t{%1, %0|%0, %1}
7776 test{q}\t{%1, %0|%0, %1}
7777 test{q}\t{%1, %0|%0, %1}"
7778 [(set_attr "type" "test")
7779 (set_attr "modrm" "0,1,0,1,1")
7780 (set_attr "mode" "SI,SI,DI,DI,DI")
7781 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7783 (define_insn "testsi_1"
7784 [(set (reg FLAGS_REG)
7786 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7787 (match_operand:SI 1 "general_operand" "in,in,rin"))
7789 "ix86_match_ccmode (insn, CCNOmode)
7790 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7791 "test{l}\t{%1, %0|%0, %1}"
7792 [(set_attr "type" "test")
7793 (set_attr "modrm" "0,1,1")
7794 (set_attr "mode" "SI")
7795 (set_attr "pent_pair" "uv,np,uv")])
7797 (define_expand "testsi_ccno_1"
7798 [(set (reg:CCNO FLAGS_REG)
7800 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7801 (match_operand:SI 1 "nonmemory_operand" ""))
7806 (define_insn "*testhi_1"
7807 [(set (reg FLAGS_REG)
7808 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7809 (match_operand:HI 1 "general_operand" "n,n,rn"))
7811 "ix86_match_ccmode (insn, CCNOmode)
7812 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7813 "test{w}\t{%1, %0|%0, %1}"
7814 [(set_attr "type" "test")
7815 (set_attr "modrm" "0,1,1")
7816 (set_attr "mode" "HI")
7817 (set_attr "pent_pair" "uv,np,uv")])
7819 (define_expand "testqi_ccz_1"
7820 [(set (reg:CCZ FLAGS_REG)
7821 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7822 (match_operand:QI 1 "nonmemory_operand" ""))
7827 (define_insn "*testqi_1_maybe_si"
7828 [(set (reg FLAGS_REG)
7831 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7832 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7834 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7835 && ix86_match_ccmode (insn,
7836 GET_CODE (operands[1]) == CONST_INT
7837 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7839 if (which_alternative == 3)
7841 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
7842 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7843 return "test{l}\t{%1, %k0|%k0, %1}";
7845 return "test{b}\t{%1, %0|%0, %1}";
7847 [(set_attr "type" "test")
7848 (set_attr "modrm" "0,1,1,1")
7849 (set_attr "mode" "QI,QI,QI,SI")
7850 (set_attr "pent_pair" "uv,np,uv,np")])
7852 (define_insn "*testqi_1"
7853 [(set (reg FLAGS_REG)
7856 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
7857 (match_operand:QI 1 "general_operand" "n,n,qn"))
7859 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7860 && ix86_match_ccmode (insn, CCNOmode)"
7861 "test{b}\t{%1, %0|%0, %1}"
7862 [(set_attr "type" "test")
7863 (set_attr "modrm" "0,1,1")
7864 (set_attr "mode" "QI")
7865 (set_attr "pent_pair" "uv,np,uv")])
7867 (define_expand "testqi_ext_ccno_0"
7868 [(set (reg:CCNO FLAGS_REG)
7872 (match_operand 0 "ext_register_operand" "")
7875 (match_operand 1 "const_int_operand" ""))
7880 (define_insn "*testqi_ext_0"
7881 [(set (reg FLAGS_REG)
7885 (match_operand 0 "ext_register_operand" "Q")
7888 (match_operand 1 "const_int_operand" "n"))
7890 "ix86_match_ccmode (insn, CCNOmode)"
7891 "test{b}\t{%1, %h0|%h0, %1}"
7892 [(set_attr "type" "test")
7893 (set_attr "mode" "QI")
7894 (set_attr "length_immediate" "1")
7895 (set_attr "pent_pair" "np")])
7897 (define_insn "*testqi_ext_1"
7898 [(set (reg FLAGS_REG)
7902 (match_operand 0 "ext_register_operand" "Q")
7906 (match_operand:QI 1 "general_operand" "Qm")))
7908 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7909 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7910 "test{b}\t{%1, %h0|%h0, %1}"
7911 [(set_attr "type" "test")
7912 (set_attr "mode" "QI")])
7914 (define_insn "*testqi_ext_1_rex64"
7915 [(set (reg FLAGS_REG)
7919 (match_operand 0 "ext_register_operand" "Q")
7923 (match_operand:QI 1 "register_operand" "Q")))
7925 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7926 "test{b}\t{%1, %h0|%h0, %1}"
7927 [(set_attr "type" "test")
7928 (set_attr "mode" "QI")])
7930 (define_insn "*testqi_ext_2"
7931 [(set (reg FLAGS_REG)
7935 (match_operand 0 "ext_register_operand" "Q")
7939 (match_operand 1 "ext_register_operand" "Q")
7943 "ix86_match_ccmode (insn, CCNOmode)"
7944 "test{b}\t{%h1, %h0|%h0, %h1}"
7945 [(set_attr "type" "test")
7946 (set_attr "mode" "QI")])
7948 ;; Combine likes to form bit extractions for some tests. Humor it.
7949 (define_insn "*testqi_ext_3"
7950 [(set (reg FLAGS_REG)
7951 (compare (zero_extract:SI
7952 (match_operand 0 "nonimmediate_operand" "rm")
7953 (match_operand:SI 1 "const_int_operand" "")
7954 (match_operand:SI 2 "const_int_operand" ""))
7956 "ix86_match_ccmode (insn, CCNOmode)
7957 && (GET_MODE (operands[0]) == SImode
7958 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7959 || GET_MODE (operands[0]) == HImode
7960 || GET_MODE (operands[0]) == QImode)"
7963 (define_insn "*testqi_ext_3_rex64"
7964 [(set (reg FLAGS_REG)
7965 (compare (zero_extract:DI
7966 (match_operand 0 "nonimmediate_operand" "rm")
7967 (match_operand:DI 1 "const_int_operand" "")
7968 (match_operand:DI 2 "const_int_operand" ""))
7971 && ix86_match_ccmode (insn, CCNOmode)
7972 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7973 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7974 /* Ensure that resulting mask is zero or sign extended operand. */
7975 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7976 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7977 && INTVAL (operands[1]) > 32))
7978 && (GET_MODE (operands[0]) == SImode
7979 || GET_MODE (operands[0]) == DImode
7980 || GET_MODE (operands[0]) == HImode
7981 || GET_MODE (operands[0]) == QImode)"
7985 [(set (match_operand 0 "flags_reg_operand" "")
7986 (match_operator 1 "compare_operator"
7988 (match_operand 2 "nonimmediate_operand" "")
7989 (match_operand 3 "const_int_operand" "")
7990 (match_operand 4 "const_int_operand" ""))
7992 "ix86_match_ccmode (insn, CCNOmode)"
7993 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
7995 rtx val = operands[2];
7996 HOST_WIDE_INT len = INTVAL (operands[3]);
7997 HOST_WIDE_INT pos = INTVAL (operands[4]);
7999 enum machine_mode mode, submode;
8001 mode = GET_MODE (val);
8002 if (GET_CODE (val) == MEM)
8004 /* ??? Combine likes to put non-volatile mem extractions in QImode
8005 no matter the size of the test. So find a mode that works. */
8006 if (! MEM_VOLATILE_P (val))
8008 mode = smallest_mode_for_size (pos + len, MODE_INT);
8009 val = adjust_address (val, mode, 0);
8012 else if (GET_CODE (val) == SUBREG
8013 && (submode = GET_MODE (SUBREG_REG (val)),
8014 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8015 && pos + len <= GET_MODE_BITSIZE (submode))
8017 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8019 val = SUBREG_REG (val);
8021 else if (mode == HImode && pos + len <= 8)
8023 /* Small HImode tests can be converted to QImode. */
8025 val = gen_lowpart (QImode, val);
8028 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8029 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8031 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
8034 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8035 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8036 ;; this is relatively important trick.
8037 ;; Do the conversion only post-reload to avoid limiting of the register class
8040 [(set (match_operand 0 "flags_reg_operand" "")
8041 (match_operator 1 "compare_operator"
8042 [(and (match_operand 2 "register_operand" "")
8043 (match_operand 3 "const_int_operand" ""))
8046 && QI_REG_P (operands[2])
8047 && GET_MODE (operands[2]) != QImode
8048 && ((ix86_match_ccmode (insn, CCZmode)
8049 && !(INTVAL (operands[3]) & ~(255 << 8)))
8050 || (ix86_match_ccmode (insn, CCNOmode)
8051 && !(INTVAL (operands[3]) & ~(127 << 8))))"
8054 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
8057 "operands[2] = gen_lowpart (SImode, operands[2]);
8058 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
8061 [(set (match_operand 0 "flags_reg_operand" "")
8062 (match_operator 1 "compare_operator"
8063 [(and (match_operand 2 "nonimmediate_operand" "")
8064 (match_operand 3 "const_int_operand" ""))
8067 && GET_MODE (operands[2]) != QImode
8068 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
8069 && ((ix86_match_ccmode (insn, CCZmode)
8070 && !(INTVAL (operands[3]) & ~255))
8071 || (ix86_match_ccmode (insn, CCNOmode)
8072 && !(INTVAL (operands[3]) & ~127)))"
8074 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
8076 "operands[2] = gen_lowpart (QImode, operands[2]);
8077 operands[3] = gen_lowpart (QImode, operands[3]);")
8080 ;; %%% This used to optimize known byte-wide and operations to memory,
8081 ;; and sometimes to QImode registers. If this is considered useful,
8082 ;; it should be done with splitters.
8084 (define_expand "anddi3"
8085 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8086 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8087 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8088 (clobber (reg:CC FLAGS_REG))]
8090 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8092 (define_insn "*anddi_1_rex64"
8093 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8094 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8095 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8096 (clobber (reg:CC FLAGS_REG))]
8097 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8099 switch (get_attr_type (insn))
8103 enum machine_mode mode;
8105 if (GET_CODE (operands[2]) != CONST_INT)
8107 if (INTVAL (operands[2]) == 0xff)
8109 else if (INTVAL (operands[2]) == 0xffff)
8114 operands[1] = gen_lowpart (mode, operands[1]);
8116 return "movz{bq|x}\t{%1,%0|%0, %1}";
8118 return "movz{wq|x}\t{%1,%0|%0, %1}";
8122 if (! rtx_equal_p (operands[0], operands[1]))
8124 if (get_attr_mode (insn) == MODE_SI)
8125 return "and{l}\t{%k2, %k0|%k0, %k2}";
8127 return "and{q}\t{%2, %0|%0, %2}";
8130 [(set_attr "type" "alu,alu,alu,imovx")
8131 (set_attr "length_immediate" "*,*,*,0")
8132 (set_attr "mode" "SI,DI,DI,DI")])
8134 (define_insn "*anddi_2"
8135 [(set (reg FLAGS_REG)
8136 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8137 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8139 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8140 (and:DI (match_dup 1) (match_dup 2)))]
8141 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8142 && ix86_binary_operator_ok (AND, DImode, operands)"
8144 and{l}\t{%k2, %k0|%k0, %k2}
8145 and{q}\t{%2, %0|%0, %2}
8146 and{q}\t{%2, %0|%0, %2}"
8147 [(set_attr "type" "alu")
8148 (set_attr "mode" "SI,DI,DI")])
8150 (define_expand "andsi3"
8151 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8152 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8153 (match_operand:SI 2 "general_operand" "")))
8154 (clobber (reg:CC FLAGS_REG))]
8156 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8158 (define_insn "*andsi_1"
8159 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8160 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8161 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8162 (clobber (reg:CC FLAGS_REG))]
8163 "ix86_binary_operator_ok (AND, SImode, operands)"
8165 switch (get_attr_type (insn))
8169 enum machine_mode mode;
8171 if (GET_CODE (operands[2]) != CONST_INT)
8173 if (INTVAL (operands[2]) == 0xff)
8175 else if (INTVAL (operands[2]) == 0xffff)
8180 operands[1] = gen_lowpart (mode, operands[1]);
8182 return "movz{bl|x}\t{%1,%0|%0, %1}";
8184 return "movz{wl|x}\t{%1,%0|%0, %1}";
8188 if (! rtx_equal_p (operands[0], operands[1]))
8190 return "and{l}\t{%2, %0|%0, %2}";
8193 [(set_attr "type" "alu,alu,imovx")
8194 (set_attr "length_immediate" "*,*,0")
8195 (set_attr "mode" "SI")])
8198 [(set (match_operand 0 "register_operand" "")
8200 (const_int -65536)))
8201 (clobber (reg:CC FLAGS_REG))]
8202 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8203 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8204 "operands[1] = gen_lowpart (HImode, operands[0]);")
8207 [(set (match_operand 0 "ext_register_operand" "")
8210 (clobber (reg:CC FLAGS_REG))]
8211 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8212 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8213 "operands[1] = gen_lowpart (QImode, operands[0]);")
8216 [(set (match_operand 0 "ext_register_operand" "")
8218 (const_int -65281)))
8219 (clobber (reg:CC FLAGS_REG))]
8220 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8221 [(parallel [(set (zero_extract:SI (match_dup 0)
8225 (zero_extract:SI (match_dup 0)
8228 (zero_extract:SI (match_dup 0)
8231 (clobber (reg:CC FLAGS_REG))])]
8232 "operands[0] = gen_lowpart (SImode, operands[0]);")
8234 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8235 (define_insn "*andsi_1_zext"
8236 [(set (match_operand:DI 0 "register_operand" "=r")
8238 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8239 (match_operand:SI 2 "general_operand" "rim"))))
8240 (clobber (reg:CC FLAGS_REG))]
8241 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8242 "and{l}\t{%2, %k0|%k0, %2}"
8243 [(set_attr "type" "alu")
8244 (set_attr "mode" "SI")])
8246 (define_insn "*andsi_2"
8247 [(set (reg FLAGS_REG)
8248 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8249 (match_operand:SI 2 "general_operand" "rim,ri"))
8251 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8252 (and:SI (match_dup 1) (match_dup 2)))]
8253 "ix86_match_ccmode (insn, CCNOmode)
8254 && ix86_binary_operator_ok (AND, SImode, operands)"
8255 "and{l}\t{%2, %0|%0, %2}"
8256 [(set_attr "type" "alu")
8257 (set_attr "mode" "SI")])
8259 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8260 (define_insn "*andsi_2_zext"
8261 [(set (reg FLAGS_REG)
8262 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8263 (match_operand:SI 2 "general_operand" "rim"))
8265 (set (match_operand:DI 0 "register_operand" "=r")
8266 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8267 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8268 && ix86_binary_operator_ok (AND, SImode, operands)"
8269 "and{l}\t{%2, %k0|%k0, %2}"
8270 [(set_attr "type" "alu")
8271 (set_attr "mode" "SI")])
8273 (define_expand "andhi3"
8274 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8275 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8276 (match_operand:HI 2 "general_operand" "")))
8277 (clobber (reg:CC FLAGS_REG))]
8278 "TARGET_HIMODE_MATH"
8279 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8281 (define_insn "*andhi_1"
8282 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8283 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8284 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8285 (clobber (reg:CC FLAGS_REG))]
8286 "ix86_binary_operator_ok (AND, HImode, operands)"
8288 switch (get_attr_type (insn))
8291 if (GET_CODE (operands[2]) != CONST_INT)
8293 if (INTVAL (operands[2]) == 0xff)
8294 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8298 if (! rtx_equal_p (operands[0], operands[1]))
8301 return "and{w}\t{%2, %0|%0, %2}";
8304 [(set_attr "type" "alu,alu,imovx")
8305 (set_attr "length_immediate" "*,*,0")
8306 (set_attr "mode" "HI,HI,SI")])
8308 (define_insn "*andhi_2"
8309 [(set (reg FLAGS_REG)
8310 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8311 (match_operand:HI 2 "general_operand" "rim,ri"))
8313 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8314 (and:HI (match_dup 1) (match_dup 2)))]
8315 "ix86_match_ccmode (insn, CCNOmode)
8316 && ix86_binary_operator_ok (AND, HImode, operands)"
8317 "and{w}\t{%2, %0|%0, %2}"
8318 [(set_attr "type" "alu")
8319 (set_attr "mode" "HI")])
8321 (define_expand "andqi3"
8322 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8323 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8324 (match_operand:QI 2 "general_operand" "")))
8325 (clobber (reg:CC FLAGS_REG))]
8326 "TARGET_QIMODE_MATH"
8327 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8329 ;; %%% Potential partial reg stall on alternative 2. What to do?
8330 (define_insn "*andqi_1"
8331 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8332 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8333 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8334 (clobber (reg:CC FLAGS_REG))]
8335 "ix86_binary_operator_ok (AND, QImode, operands)"
8337 and{b}\t{%2, %0|%0, %2}
8338 and{b}\t{%2, %0|%0, %2}
8339 and{l}\t{%k2, %k0|%k0, %k2}"
8340 [(set_attr "type" "alu")
8341 (set_attr "mode" "QI,QI,SI")])
8343 (define_insn "*andqi_1_slp"
8344 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8345 (and:QI (match_dup 0)
8346 (match_operand:QI 1 "general_operand" "qi,qmi")))
8347 (clobber (reg:CC FLAGS_REG))]
8348 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8349 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8350 "and{b}\t{%1, %0|%0, %1}"
8351 [(set_attr "type" "alu1")
8352 (set_attr "mode" "QI")])
8354 (define_insn "*andqi_2_maybe_si"
8355 [(set (reg FLAGS_REG)
8357 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8358 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8360 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8361 (and:QI (match_dup 1) (match_dup 2)))]
8362 "ix86_binary_operator_ok (AND, QImode, operands)
8363 && ix86_match_ccmode (insn,
8364 GET_CODE (operands[2]) == CONST_INT
8365 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
8367 if (which_alternative == 2)
8369 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8370 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8371 return "and{l}\t{%2, %k0|%k0, %2}";
8373 return "and{b}\t{%2, %0|%0, %2}";
8375 [(set_attr "type" "alu")
8376 (set_attr "mode" "QI,QI,SI")])
8378 (define_insn "*andqi_2"
8379 [(set (reg FLAGS_REG)
8381 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8382 (match_operand:QI 2 "general_operand" "qim,qi"))
8384 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8385 (and:QI (match_dup 1) (match_dup 2)))]
8386 "ix86_match_ccmode (insn, CCNOmode)
8387 && ix86_binary_operator_ok (AND, QImode, operands)"
8388 "and{b}\t{%2, %0|%0, %2}"
8389 [(set_attr "type" "alu")
8390 (set_attr "mode" "QI")])
8392 (define_insn "*andqi_2_slp"
8393 [(set (reg FLAGS_REG)
8395 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8396 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8398 (set (strict_low_part (match_dup 0))
8399 (and:QI (match_dup 0) (match_dup 1)))]
8400 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8401 && ix86_match_ccmode (insn, CCNOmode)
8402 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8403 "and{b}\t{%1, %0|%0, %1}"
8404 [(set_attr "type" "alu1")
8405 (set_attr "mode" "QI")])
8407 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8408 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8409 ;; for a QImode operand, which of course failed.
8411 (define_insn "andqi_ext_0"
8412 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8417 (match_operand 1 "ext_register_operand" "0")
8420 (match_operand 2 "const_int_operand" "n")))
8421 (clobber (reg:CC FLAGS_REG))]
8423 "and{b}\t{%2, %h0|%h0, %2}"
8424 [(set_attr "type" "alu")
8425 (set_attr "length_immediate" "1")
8426 (set_attr "mode" "QI")])
8428 ;; Generated by peephole translating test to and. This shows up
8429 ;; often in fp comparisons.
8431 (define_insn "*andqi_ext_0_cc"
8432 [(set (reg FLAGS_REG)
8436 (match_operand 1 "ext_register_operand" "0")
8439 (match_operand 2 "const_int_operand" "n"))
8441 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8450 "ix86_match_ccmode (insn, CCNOmode)"
8451 "and{b}\t{%2, %h0|%h0, %2}"
8452 [(set_attr "type" "alu")
8453 (set_attr "length_immediate" "1")
8454 (set_attr "mode" "QI")])
8456 (define_insn "*andqi_ext_1"
8457 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8462 (match_operand 1 "ext_register_operand" "0")
8466 (match_operand:QI 2 "general_operand" "Qm"))))
8467 (clobber (reg:CC FLAGS_REG))]
8469 "and{b}\t{%2, %h0|%h0, %2}"
8470 [(set_attr "type" "alu")
8471 (set_attr "length_immediate" "0")
8472 (set_attr "mode" "QI")])
8474 (define_insn "*andqi_ext_1_rex64"
8475 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8480 (match_operand 1 "ext_register_operand" "0")
8484 (match_operand 2 "ext_register_operand" "Q"))))
8485 (clobber (reg:CC FLAGS_REG))]
8487 "and{b}\t{%2, %h0|%h0, %2}"
8488 [(set_attr "type" "alu")
8489 (set_attr "length_immediate" "0")
8490 (set_attr "mode" "QI")])
8492 (define_insn "*andqi_ext_2"
8493 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8498 (match_operand 1 "ext_register_operand" "%0")
8502 (match_operand 2 "ext_register_operand" "Q")
8505 (clobber (reg:CC FLAGS_REG))]
8507 "and{b}\t{%h2, %h0|%h0, %h2}"
8508 [(set_attr "type" "alu")
8509 (set_attr "length_immediate" "0")
8510 (set_attr "mode" "QI")])
8512 ;; Convert wide AND instructions with immediate operand to shorter QImode
8513 ;; equivalents when possible.
8514 ;; Don't do the splitting with memory operands, since it introduces risk
8515 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8516 ;; for size, but that can (should?) be handled by generic code instead.
8518 [(set (match_operand 0 "register_operand" "")
8519 (and (match_operand 1 "register_operand" "")
8520 (match_operand 2 "const_int_operand" "")))
8521 (clobber (reg:CC FLAGS_REG))]
8523 && QI_REG_P (operands[0])
8524 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8525 && !(~INTVAL (operands[2]) & ~(255 << 8))
8526 && GET_MODE (operands[0]) != QImode"
8527 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8528 (and:SI (zero_extract:SI (match_dup 1)
8529 (const_int 8) (const_int 8))
8531 (clobber (reg:CC FLAGS_REG))])]
8532 "operands[0] = gen_lowpart (SImode, operands[0]);
8533 operands[1] = gen_lowpart (SImode, operands[1]);
8534 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8536 ;; Since AND can be encoded with sign extended immediate, this is only
8537 ;; profitable when 7th bit is not set.
8539 [(set (match_operand 0 "register_operand" "")
8540 (and (match_operand 1 "general_operand" "")
8541 (match_operand 2 "const_int_operand" "")))
8542 (clobber (reg:CC FLAGS_REG))]
8544 && ANY_QI_REG_P (operands[0])
8545 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8546 && !(~INTVAL (operands[2]) & ~255)
8547 && !(INTVAL (operands[2]) & 128)
8548 && GET_MODE (operands[0]) != QImode"
8549 [(parallel [(set (strict_low_part (match_dup 0))
8550 (and:QI (match_dup 1)
8552 (clobber (reg:CC FLAGS_REG))])]
8553 "operands[0] = gen_lowpart (QImode, operands[0]);
8554 operands[1] = gen_lowpart (QImode, operands[1]);
8555 operands[2] = gen_lowpart (QImode, operands[2]);")
8557 ;; Logical inclusive OR instructions
8559 ;; %%% This used to optimize known byte-wide and operations to memory.
8560 ;; If this is considered useful, it should be done with splitters.
8562 (define_expand "iordi3"
8563 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8564 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8565 (match_operand:DI 2 "x86_64_general_operand" "")))
8566 (clobber (reg:CC FLAGS_REG))]
8568 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8570 (define_insn "*iordi_1_rex64"
8571 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8572 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8573 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8574 (clobber (reg:CC FLAGS_REG))]
8576 && ix86_binary_operator_ok (IOR, DImode, operands)"
8577 "or{q}\t{%2, %0|%0, %2}"
8578 [(set_attr "type" "alu")
8579 (set_attr "mode" "DI")])
8581 (define_insn "*iordi_2_rex64"
8582 [(set (reg FLAGS_REG)
8583 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8584 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8586 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8587 (ior:DI (match_dup 1) (match_dup 2)))]
8589 && ix86_match_ccmode (insn, CCNOmode)
8590 && ix86_binary_operator_ok (IOR, DImode, operands)"
8591 "or{q}\t{%2, %0|%0, %2}"
8592 [(set_attr "type" "alu")
8593 (set_attr "mode" "DI")])
8595 (define_insn "*iordi_3_rex64"
8596 [(set (reg FLAGS_REG)
8597 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8598 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8600 (clobber (match_scratch:DI 0 "=r"))]
8602 && ix86_match_ccmode (insn, CCNOmode)
8603 && ix86_binary_operator_ok (IOR, DImode, operands)"
8604 "or{q}\t{%2, %0|%0, %2}"
8605 [(set_attr "type" "alu")
8606 (set_attr "mode" "DI")])
8609 (define_expand "iorsi3"
8610 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8611 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8612 (match_operand:SI 2 "general_operand" "")))
8613 (clobber (reg:CC FLAGS_REG))]
8615 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8617 (define_insn "*iorsi_1"
8618 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8619 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8620 (match_operand:SI 2 "general_operand" "ri,rmi")))
8621 (clobber (reg:CC FLAGS_REG))]
8622 "ix86_binary_operator_ok (IOR, SImode, operands)"
8623 "or{l}\t{%2, %0|%0, %2}"
8624 [(set_attr "type" "alu")
8625 (set_attr "mode" "SI")])
8627 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8628 (define_insn "*iorsi_1_zext"
8629 [(set (match_operand:DI 0 "register_operand" "=rm")
8631 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8632 (match_operand:SI 2 "general_operand" "rim"))))
8633 (clobber (reg:CC FLAGS_REG))]
8634 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8635 "or{l}\t{%2, %k0|%k0, %2}"
8636 [(set_attr "type" "alu")
8637 (set_attr "mode" "SI")])
8639 (define_insn "*iorsi_1_zext_imm"
8640 [(set (match_operand:DI 0 "register_operand" "=rm")
8641 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8642 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8643 (clobber (reg:CC FLAGS_REG))]
8645 "or{l}\t{%2, %k0|%k0, %2}"
8646 [(set_attr "type" "alu")
8647 (set_attr "mode" "SI")])
8649 (define_insn "*iorsi_2"
8650 [(set (reg FLAGS_REG)
8651 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8652 (match_operand:SI 2 "general_operand" "rim,ri"))
8654 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8655 (ior:SI (match_dup 1) (match_dup 2)))]
8656 "ix86_match_ccmode (insn, CCNOmode)
8657 && ix86_binary_operator_ok (IOR, SImode, operands)"
8658 "or{l}\t{%2, %0|%0, %2}"
8659 [(set_attr "type" "alu")
8660 (set_attr "mode" "SI")])
8662 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8663 ;; ??? Special case for immediate operand is missing - it is tricky.
8664 (define_insn "*iorsi_2_zext"
8665 [(set (reg FLAGS_REG)
8666 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8667 (match_operand:SI 2 "general_operand" "rim"))
8669 (set (match_operand:DI 0 "register_operand" "=r")
8670 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8671 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8672 && ix86_binary_operator_ok (IOR, SImode, operands)"
8673 "or{l}\t{%2, %k0|%k0, %2}"
8674 [(set_attr "type" "alu")
8675 (set_attr "mode" "SI")])
8677 (define_insn "*iorsi_2_zext_imm"
8678 [(set (reg FLAGS_REG)
8679 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8680 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8682 (set (match_operand:DI 0 "register_operand" "=r")
8683 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8684 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8685 && ix86_binary_operator_ok (IOR, SImode, operands)"
8686 "or{l}\t{%2, %k0|%k0, %2}"
8687 [(set_attr "type" "alu")
8688 (set_attr "mode" "SI")])
8690 (define_insn "*iorsi_3"
8691 [(set (reg FLAGS_REG)
8692 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8693 (match_operand:SI 2 "general_operand" "rim"))
8695 (clobber (match_scratch:SI 0 "=r"))]
8696 "ix86_match_ccmode (insn, CCNOmode)
8697 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8698 "or{l}\t{%2, %0|%0, %2}"
8699 [(set_attr "type" "alu")
8700 (set_attr "mode" "SI")])
8702 (define_expand "iorhi3"
8703 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8704 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8705 (match_operand:HI 2 "general_operand" "")))
8706 (clobber (reg:CC FLAGS_REG))]
8707 "TARGET_HIMODE_MATH"
8708 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8710 (define_insn "*iorhi_1"
8711 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8712 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8713 (match_operand:HI 2 "general_operand" "rmi,ri")))
8714 (clobber (reg:CC FLAGS_REG))]
8715 "ix86_binary_operator_ok (IOR, HImode, operands)"
8716 "or{w}\t{%2, %0|%0, %2}"
8717 [(set_attr "type" "alu")
8718 (set_attr "mode" "HI")])
8720 (define_insn "*iorhi_2"
8721 [(set (reg FLAGS_REG)
8722 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8723 (match_operand:HI 2 "general_operand" "rim,ri"))
8725 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8726 (ior:HI (match_dup 1) (match_dup 2)))]
8727 "ix86_match_ccmode (insn, CCNOmode)
8728 && ix86_binary_operator_ok (IOR, HImode, operands)"
8729 "or{w}\t{%2, %0|%0, %2}"
8730 [(set_attr "type" "alu")
8731 (set_attr "mode" "HI")])
8733 (define_insn "*iorhi_3"
8734 [(set (reg FLAGS_REG)
8735 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8736 (match_operand:HI 2 "general_operand" "rim"))
8738 (clobber (match_scratch:HI 0 "=r"))]
8739 "ix86_match_ccmode (insn, CCNOmode)
8740 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8741 "or{w}\t{%2, %0|%0, %2}"
8742 [(set_attr "type" "alu")
8743 (set_attr "mode" "HI")])
8745 (define_expand "iorqi3"
8746 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8747 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8748 (match_operand:QI 2 "general_operand" "")))
8749 (clobber (reg:CC FLAGS_REG))]
8750 "TARGET_QIMODE_MATH"
8751 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8753 ;; %%% Potential partial reg stall on alternative 2. What to do?
8754 (define_insn "*iorqi_1"
8755 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8756 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8757 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8758 (clobber (reg:CC FLAGS_REG))]
8759 "ix86_binary_operator_ok (IOR, QImode, operands)"
8761 or{b}\t{%2, %0|%0, %2}
8762 or{b}\t{%2, %0|%0, %2}
8763 or{l}\t{%k2, %k0|%k0, %k2}"
8764 [(set_attr "type" "alu")
8765 (set_attr "mode" "QI,QI,SI")])
8767 (define_insn "*iorqi_1_slp"
8768 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8769 (ior:QI (match_dup 0)
8770 (match_operand:QI 1 "general_operand" "qmi,qi")))
8771 (clobber (reg:CC FLAGS_REG))]
8772 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8773 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8774 "or{b}\t{%1, %0|%0, %1}"
8775 [(set_attr "type" "alu1")
8776 (set_attr "mode" "QI")])
8778 (define_insn "*iorqi_2"
8779 [(set (reg FLAGS_REG)
8780 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8781 (match_operand:QI 2 "general_operand" "qim,qi"))
8783 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8784 (ior:QI (match_dup 1) (match_dup 2)))]
8785 "ix86_match_ccmode (insn, CCNOmode)
8786 && ix86_binary_operator_ok (IOR, QImode, operands)"
8787 "or{b}\t{%2, %0|%0, %2}"
8788 [(set_attr "type" "alu")
8789 (set_attr "mode" "QI")])
8791 (define_insn "*iorqi_2_slp"
8792 [(set (reg FLAGS_REG)
8793 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8794 (match_operand:QI 1 "general_operand" "qim,qi"))
8796 (set (strict_low_part (match_dup 0))
8797 (ior:QI (match_dup 0) (match_dup 1)))]
8798 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8799 && ix86_match_ccmode (insn, CCNOmode)
8800 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8801 "or{b}\t{%1, %0|%0, %1}"
8802 [(set_attr "type" "alu1")
8803 (set_attr "mode" "QI")])
8805 (define_insn "*iorqi_3"
8806 [(set (reg FLAGS_REG)
8807 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8808 (match_operand:QI 2 "general_operand" "qim"))
8810 (clobber (match_scratch:QI 0 "=q"))]
8811 "ix86_match_ccmode (insn, CCNOmode)
8812 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8813 "or{b}\t{%2, %0|%0, %2}"
8814 [(set_attr "type" "alu")
8815 (set_attr "mode" "QI")])
8817 (define_insn "iorqi_ext_0"
8818 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8823 (match_operand 1 "ext_register_operand" "0")
8826 (match_operand 2 "const_int_operand" "n")))
8827 (clobber (reg:CC FLAGS_REG))]
8828 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8829 "or{b}\t{%2, %h0|%h0, %2}"
8830 [(set_attr "type" "alu")
8831 (set_attr "length_immediate" "1")
8832 (set_attr "mode" "QI")])
8834 (define_insn "*iorqi_ext_1"
8835 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8840 (match_operand 1 "ext_register_operand" "0")
8844 (match_operand:QI 2 "general_operand" "Qm"))))
8845 (clobber (reg:CC FLAGS_REG))]
8847 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8848 "or{b}\t{%2, %h0|%h0, %2}"
8849 [(set_attr "type" "alu")
8850 (set_attr "length_immediate" "0")
8851 (set_attr "mode" "QI")])
8853 (define_insn "*iorqi_ext_1_rex64"
8854 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8859 (match_operand 1 "ext_register_operand" "0")
8863 (match_operand 2 "ext_register_operand" "Q"))))
8864 (clobber (reg:CC FLAGS_REG))]
8866 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8867 "or{b}\t{%2, %h0|%h0, %2}"
8868 [(set_attr "type" "alu")
8869 (set_attr "length_immediate" "0")
8870 (set_attr "mode" "QI")])
8872 (define_insn "*iorqi_ext_2"
8873 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8877 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8880 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8883 (clobber (reg:CC FLAGS_REG))]
8884 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8885 "ior{b}\t{%h2, %h0|%h0, %h2}"
8886 [(set_attr "type" "alu")
8887 (set_attr "length_immediate" "0")
8888 (set_attr "mode" "QI")])
8891 [(set (match_operand 0 "register_operand" "")
8892 (ior (match_operand 1 "register_operand" "")
8893 (match_operand 2 "const_int_operand" "")))
8894 (clobber (reg:CC FLAGS_REG))]
8896 && QI_REG_P (operands[0])
8897 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8898 && !(INTVAL (operands[2]) & ~(255 << 8))
8899 && GET_MODE (operands[0]) != QImode"
8900 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8901 (ior:SI (zero_extract:SI (match_dup 1)
8902 (const_int 8) (const_int 8))
8904 (clobber (reg:CC FLAGS_REG))])]
8905 "operands[0] = gen_lowpart (SImode, operands[0]);
8906 operands[1] = gen_lowpart (SImode, operands[1]);
8907 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8909 ;; Since OR can be encoded with sign extended immediate, this is only
8910 ;; profitable when 7th bit is set.
8912 [(set (match_operand 0 "register_operand" "")
8913 (ior (match_operand 1 "general_operand" "")
8914 (match_operand 2 "const_int_operand" "")))
8915 (clobber (reg:CC FLAGS_REG))]
8917 && ANY_QI_REG_P (operands[0])
8918 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8919 && !(INTVAL (operands[2]) & ~255)
8920 && (INTVAL (operands[2]) & 128)
8921 && GET_MODE (operands[0]) != QImode"
8922 [(parallel [(set (strict_low_part (match_dup 0))
8923 (ior:QI (match_dup 1)
8925 (clobber (reg:CC FLAGS_REG))])]
8926 "operands[0] = gen_lowpart (QImode, operands[0]);
8927 operands[1] = gen_lowpart (QImode, operands[1]);
8928 operands[2] = gen_lowpart (QImode, operands[2]);")
8930 ;; Logical XOR instructions
8932 ;; %%% This used to optimize known byte-wide and operations to memory.
8933 ;; If this is considered useful, it should be done with splitters.
8935 (define_expand "xordi3"
8936 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8937 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8938 (match_operand:DI 2 "x86_64_general_operand" "")))
8939 (clobber (reg:CC FLAGS_REG))]
8941 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8943 (define_insn "*xordi_1_rex64"
8944 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8945 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8946 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8947 (clobber (reg:CC FLAGS_REG))]
8949 && ix86_binary_operator_ok (XOR, DImode, operands)"
8951 xor{q}\t{%2, %0|%0, %2}
8952 xor{q}\t{%2, %0|%0, %2}"
8953 [(set_attr "type" "alu")
8954 (set_attr "mode" "DI,DI")])
8956 (define_insn "*xordi_2_rex64"
8957 [(set (reg FLAGS_REG)
8958 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8959 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8961 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8962 (xor:DI (match_dup 1) (match_dup 2)))]
8964 && ix86_match_ccmode (insn, CCNOmode)
8965 && ix86_binary_operator_ok (XOR, DImode, operands)"
8967 xor{q}\t{%2, %0|%0, %2}
8968 xor{q}\t{%2, %0|%0, %2}"
8969 [(set_attr "type" "alu")
8970 (set_attr "mode" "DI,DI")])
8972 (define_insn "*xordi_3_rex64"
8973 [(set (reg FLAGS_REG)
8974 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8975 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8977 (clobber (match_scratch:DI 0 "=r"))]
8979 && ix86_match_ccmode (insn, CCNOmode)
8980 && ix86_binary_operator_ok (XOR, DImode, operands)"
8981 "xor{q}\t{%2, %0|%0, %2}"
8982 [(set_attr "type" "alu")
8983 (set_attr "mode" "DI")])
8985 (define_expand "xorsi3"
8986 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8987 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8988 (match_operand:SI 2 "general_operand" "")))
8989 (clobber (reg:CC FLAGS_REG))]
8991 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8993 (define_insn "*xorsi_1"
8994 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8995 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8996 (match_operand:SI 2 "general_operand" "ri,rm")))
8997 (clobber (reg:CC FLAGS_REG))]
8998 "ix86_binary_operator_ok (XOR, SImode, operands)"
8999 "xor{l}\t{%2, %0|%0, %2}"
9000 [(set_attr "type" "alu")
9001 (set_attr "mode" "SI")])
9003 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9004 ;; Add speccase for immediates
9005 (define_insn "*xorsi_1_zext"
9006 [(set (match_operand:DI 0 "register_operand" "=r")
9008 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9009 (match_operand:SI 2 "general_operand" "rim"))))
9010 (clobber (reg:CC FLAGS_REG))]
9011 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9012 "xor{l}\t{%2, %k0|%k0, %2}"
9013 [(set_attr "type" "alu")
9014 (set_attr "mode" "SI")])
9016 (define_insn "*xorsi_1_zext_imm"
9017 [(set (match_operand:DI 0 "register_operand" "=r")
9018 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9019 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9020 (clobber (reg:CC FLAGS_REG))]
9021 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9022 "xor{l}\t{%2, %k0|%k0, %2}"
9023 [(set_attr "type" "alu")
9024 (set_attr "mode" "SI")])
9026 (define_insn "*xorsi_2"
9027 [(set (reg FLAGS_REG)
9028 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9029 (match_operand:SI 2 "general_operand" "rim,ri"))
9031 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9032 (xor:SI (match_dup 1) (match_dup 2)))]
9033 "ix86_match_ccmode (insn, CCNOmode)
9034 && ix86_binary_operator_ok (XOR, SImode, operands)"
9035 "xor{l}\t{%2, %0|%0, %2}"
9036 [(set_attr "type" "alu")
9037 (set_attr "mode" "SI")])
9039 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9040 ;; ??? Special case for immediate operand is missing - it is tricky.
9041 (define_insn "*xorsi_2_zext"
9042 [(set (reg FLAGS_REG)
9043 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9044 (match_operand:SI 2 "general_operand" "rim"))
9046 (set (match_operand:DI 0 "register_operand" "=r")
9047 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9048 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9049 && ix86_binary_operator_ok (XOR, SImode, operands)"
9050 "xor{l}\t{%2, %k0|%k0, %2}"
9051 [(set_attr "type" "alu")
9052 (set_attr "mode" "SI")])
9054 (define_insn "*xorsi_2_zext_imm"
9055 [(set (reg FLAGS_REG)
9056 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9057 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9059 (set (match_operand:DI 0 "register_operand" "=r")
9060 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9061 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9062 && ix86_binary_operator_ok (XOR, SImode, operands)"
9063 "xor{l}\t{%2, %k0|%k0, %2}"
9064 [(set_attr "type" "alu")
9065 (set_attr "mode" "SI")])
9067 (define_insn "*xorsi_3"
9068 [(set (reg FLAGS_REG)
9069 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9070 (match_operand:SI 2 "general_operand" "rim"))
9072 (clobber (match_scratch:SI 0 "=r"))]
9073 "ix86_match_ccmode (insn, CCNOmode)
9074 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9075 "xor{l}\t{%2, %0|%0, %2}"
9076 [(set_attr "type" "alu")
9077 (set_attr "mode" "SI")])
9079 (define_expand "xorhi3"
9080 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9081 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9082 (match_operand:HI 2 "general_operand" "")))
9083 (clobber (reg:CC FLAGS_REG))]
9084 "TARGET_HIMODE_MATH"
9085 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9087 (define_insn "*xorhi_1"
9088 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9089 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9090 (match_operand:HI 2 "general_operand" "rmi,ri")))
9091 (clobber (reg:CC FLAGS_REG))]
9092 "ix86_binary_operator_ok (XOR, HImode, operands)"
9093 "xor{w}\t{%2, %0|%0, %2}"
9094 [(set_attr "type" "alu")
9095 (set_attr "mode" "HI")])
9097 (define_insn "*xorhi_2"
9098 [(set (reg FLAGS_REG)
9099 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9100 (match_operand:HI 2 "general_operand" "rim,ri"))
9102 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9103 (xor:HI (match_dup 1) (match_dup 2)))]
9104 "ix86_match_ccmode (insn, CCNOmode)
9105 && ix86_binary_operator_ok (XOR, HImode, operands)"
9106 "xor{w}\t{%2, %0|%0, %2}"
9107 [(set_attr "type" "alu")
9108 (set_attr "mode" "HI")])
9110 (define_insn "*xorhi_3"
9111 [(set (reg FLAGS_REG)
9112 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9113 (match_operand:HI 2 "general_operand" "rim"))
9115 (clobber (match_scratch:HI 0 "=r"))]
9116 "ix86_match_ccmode (insn, CCNOmode)
9117 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9118 "xor{w}\t{%2, %0|%0, %2}"
9119 [(set_attr "type" "alu")
9120 (set_attr "mode" "HI")])
9122 (define_expand "xorqi3"
9123 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9124 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9125 (match_operand:QI 2 "general_operand" "")))
9126 (clobber (reg:CC FLAGS_REG))]
9127 "TARGET_QIMODE_MATH"
9128 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9130 ;; %%% Potential partial reg stall on alternative 2. What to do?
9131 (define_insn "*xorqi_1"
9132 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9133 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9134 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9135 (clobber (reg:CC FLAGS_REG))]
9136 "ix86_binary_operator_ok (XOR, QImode, operands)"
9138 xor{b}\t{%2, %0|%0, %2}
9139 xor{b}\t{%2, %0|%0, %2}
9140 xor{l}\t{%k2, %k0|%k0, %k2}"
9141 [(set_attr "type" "alu")
9142 (set_attr "mode" "QI,QI,SI")])
9144 (define_insn "*xorqi_1_slp"
9145 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9146 (xor:QI (match_dup 0)
9147 (match_operand:QI 1 "general_operand" "qi,qmi")))
9148 (clobber (reg:CC FLAGS_REG))]
9149 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9150 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9151 "xor{b}\t{%1, %0|%0, %1}"
9152 [(set_attr "type" "alu1")
9153 (set_attr "mode" "QI")])
9155 (define_insn "xorqi_ext_0"
9156 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9161 (match_operand 1 "ext_register_operand" "0")
9164 (match_operand 2 "const_int_operand" "n")))
9165 (clobber (reg:CC FLAGS_REG))]
9166 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9167 "xor{b}\t{%2, %h0|%h0, %2}"
9168 [(set_attr "type" "alu")
9169 (set_attr "length_immediate" "1")
9170 (set_attr "mode" "QI")])
9172 (define_insn "*xorqi_ext_1"
9173 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9178 (match_operand 1 "ext_register_operand" "0")
9182 (match_operand:QI 2 "general_operand" "Qm"))))
9183 (clobber (reg:CC FLAGS_REG))]
9185 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9186 "xor{b}\t{%2, %h0|%h0, %2}"
9187 [(set_attr "type" "alu")
9188 (set_attr "length_immediate" "0")
9189 (set_attr "mode" "QI")])
9191 (define_insn "*xorqi_ext_1_rex64"
9192 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9197 (match_operand 1 "ext_register_operand" "0")
9201 (match_operand 2 "ext_register_operand" "Q"))))
9202 (clobber (reg:CC FLAGS_REG))]
9204 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9205 "xor{b}\t{%2, %h0|%h0, %2}"
9206 [(set_attr "type" "alu")
9207 (set_attr "length_immediate" "0")
9208 (set_attr "mode" "QI")])
9210 (define_insn "*xorqi_ext_2"
9211 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9215 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9218 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9221 (clobber (reg:CC FLAGS_REG))]
9222 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9223 "xor{b}\t{%h2, %h0|%h0, %h2}"
9224 [(set_attr "type" "alu")
9225 (set_attr "length_immediate" "0")
9226 (set_attr "mode" "QI")])
9228 (define_insn "*xorqi_cc_1"
9229 [(set (reg FLAGS_REG)
9231 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9232 (match_operand:QI 2 "general_operand" "qim,qi"))
9234 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9235 (xor:QI (match_dup 1) (match_dup 2)))]
9236 "ix86_match_ccmode (insn, CCNOmode)
9237 && ix86_binary_operator_ok (XOR, QImode, operands)"
9238 "xor{b}\t{%2, %0|%0, %2}"
9239 [(set_attr "type" "alu")
9240 (set_attr "mode" "QI")])
9242 (define_insn "*xorqi_2_slp"
9243 [(set (reg FLAGS_REG)
9244 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9245 (match_operand:QI 1 "general_operand" "qim,qi"))
9247 (set (strict_low_part (match_dup 0))
9248 (xor:QI (match_dup 0) (match_dup 1)))]
9249 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9250 && ix86_match_ccmode (insn, CCNOmode)
9251 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9252 "xor{b}\t{%1, %0|%0, %1}"
9253 [(set_attr "type" "alu1")
9254 (set_attr "mode" "QI")])
9256 (define_insn "*xorqi_cc_2"
9257 [(set (reg FLAGS_REG)
9259 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9260 (match_operand:QI 2 "general_operand" "qim"))
9262 (clobber (match_scratch:QI 0 "=q"))]
9263 "ix86_match_ccmode (insn, CCNOmode)
9264 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9265 "xor{b}\t{%2, %0|%0, %2}"
9266 [(set_attr "type" "alu")
9267 (set_attr "mode" "QI")])
9269 (define_insn "*xorqi_cc_ext_1"
9270 [(set (reg FLAGS_REG)
9274 (match_operand 1 "ext_register_operand" "0")
9277 (match_operand:QI 2 "general_operand" "qmn"))
9279 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9283 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9285 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9286 "xor{b}\t{%2, %h0|%h0, %2}"
9287 [(set_attr "type" "alu")
9288 (set_attr "mode" "QI")])
9290 (define_insn "*xorqi_cc_ext_1_rex64"
9291 [(set (reg FLAGS_REG)
9295 (match_operand 1 "ext_register_operand" "0")
9298 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9300 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9304 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9306 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9307 "xor{b}\t{%2, %h0|%h0, %2}"
9308 [(set_attr "type" "alu")
9309 (set_attr "mode" "QI")])
9311 (define_expand "xorqi_cc_ext_1"
9313 (set (reg:CCNO FLAGS_REG)
9317 (match_operand 1 "ext_register_operand" "")
9320 (match_operand:QI 2 "general_operand" ""))
9322 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9326 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9332 [(set (match_operand 0 "register_operand" "")
9333 (xor (match_operand 1 "register_operand" "")
9334 (match_operand 2 "const_int_operand" "")))
9335 (clobber (reg:CC FLAGS_REG))]
9337 && QI_REG_P (operands[0])
9338 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9339 && !(INTVAL (operands[2]) & ~(255 << 8))
9340 && GET_MODE (operands[0]) != QImode"
9341 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9342 (xor:SI (zero_extract:SI (match_dup 1)
9343 (const_int 8) (const_int 8))
9345 (clobber (reg:CC FLAGS_REG))])]
9346 "operands[0] = gen_lowpart (SImode, operands[0]);
9347 operands[1] = gen_lowpart (SImode, operands[1]);
9348 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9350 ;; Since XOR can be encoded with sign extended immediate, this is only
9351 ;; profitable when 7th bit is set.
9353 [(set (match_operand 0 "register_operand" "")
9354 (xor (match_operand 1 "general_operand" "")
9355 (match_operand 2 "const_int_operand" "")))
9356 (clobber (reg:CC FLAGS_REG))]
9358 && ANY_QI_REG_P (operands[0])
9359 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9360 && !(INTVAL (operands[2]) & ~255)
9361 && (INTVAL (operands[2]) & 128)
9362 && GET_MODE (operands[0]) != QImode"
9363 [(parallel [(set (strict_low_part (match_dup 0))
9364 (xor:QI (match_dup 1)
9366 (clobber (reg:CC FLAGS_REG))])]
9367 "operands[0] = gen_lowpart (QImode, operands[0]);
9368 operands[1] = gen_lowpart (QImode, operands[1]);
9369 operands[2] = gen_lowpart (QImode, operands[2]);")
9371 ;; Negation instructions
9373 (define_expand "negdi2"
9374 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9375 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9376 (clobber (reg:CC FLAGS_REG))])]
9378 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9380 (define_insn "*negdi2_1"
9381 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9382 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9383 (clobber (reg:CC FLAGS_REG))]
9385 && ix86_unary_operator_ok (NEG, DImode, operands)"
9389 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9390 (neg:DI (match_operand:DI 1 "general_operand" "")))
9391 (clobber (reg:CC FLAGS_REG))]
9392 "!TARGET_64BIT && reload_completed"
9394 [(set (reg:CCZ FLAGS_REG)
9395 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9396 (set (match_dup 0) (neg:SI (match_dup 2)))])
9399 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9402 (clobber (reg:CC FLAGS_REG))])
9405 (neg:SI (match_dup 1)))
9406 (clobber (reg:CC FLAGS_REG))])]
9407 "split_di (operands+1, 1, operands+2, operands+3);
9408 split_di (operands+0, 1, operands+0, operands+1);")
9410 (define_insn "*negdi2_1_rex64"
9411 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9412 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9413 (clobber (reg:CC FLAGS_REG))]
9414 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9416 [(set_attr "type" "negnot")
9417 (set_attr "mode" "DI")])
9419 ;; The problem with neg is that it does not perform (compare x 0),
9420 ;; it really performs (compare 0 x), which leaves us with the zero
9421 ;; flag being the only useful item.
9423 (define_insn "*negdi2_cmpz_rex64"
9424 [(set (reg:CCZ FLAGS_REG)
9425 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9427 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9428 (neg:DI (match_dup 1)))]
9429 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9431 [(set_attr "type" "negnot")
9432 (set_attr "mode" "DI")])
9435 (define_expand "negsi2"
9436 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9437 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9438 (clobber (reg:CC FLAGS_REG))])]
9440 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9442 (define_insn "*negsi2_1"
9443 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9444 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9445 (clobber (reg:CC FLAGS_REG))]
9446 "ix86_unary_operator_ok (NEG, SImode, operands)"
9448 [(set_attr "type" "negnot")
9449 (set_attr "mode" "SI")])
9451 ;; Combine is quite creative about this pattern.
9452 (define_insn "*negsi2_1_zext"
9453 [(set (match_operand:DI 0 "register_operand" "=r")
9454 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9457 (clobber (reg:CC FLAGS_REG))]
9458 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9460 [(set_attr "type" "negnot")
9461 (set_attr "mode" "SI")])
9463 ;; The problem with neg is that it does not perform (compare x 0),
9464 ;; it really performs (compare 0 x), which leaves us with the zero
9465 ;; flag being the only useful item.
9467 (define_insn "*negsi2_cmpz"
9468 [(set (reg:CCZ FLAGS_REG)
9469 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9471 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9472 (neg:SI (match_dup 1)))]
9473 "ix86_unary_operator_ok (NEG, SImode, operands)"
9475 [(set_attr "type" "negnot")
9476 (set_attr "mode" "SI")])
9478 (define_insn "*negsi2_cmpz_zext"
9479 [(set (reg:CCZ FLAGS_REG)
9480 (compare:CCZ (lshiftrt:DI
9482 (match_operand:DI 1 "register_operand" "0")
9486 (set (match_operand:DI 0 "register_operand" "=r")
9487 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9490 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9492 [(set_attr "type" "negnot")
9493 (set_attr "mode" "SI")])
9495 (define_expand "neghi2"
9496 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9497 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9498 (clobber (reg:CC FLAGS_REG))])]
9499 "TARGET_HIMODE_MATH"
9500 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9502 (define_insn "*neghi2_1"
9503 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9504 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9505 (clobber (reg:CC FLAGS_REG))]
9506 "ix86_unary_operator_ok (NEG, HImode, operands)"
9508 [(set_attr "type" "negnot")
9509 (set_attr "mode" "HI")])
9511 (define_insn "*neghi2_cmpz"
9512 [(set (reg:CCZ FLAGS_REG)
9513 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9515 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9516 (neg:HI (match_dup 1)))]
9517 "ix86_unary_operator_ok (NEG, HImode, operands)"
9519 [(set_attr "type" "negnot")
9520 (set_attr "mode" "HI")])
9522 (define_expand "negqi2"
9523 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9524 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9525 (clobber (reg:CC FLAGS_REG))])]
9526 "TARGET_QIMODE_MATH"
9527 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9529 (define_insn "*negqi2_1"
9530 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9531 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9532 (clobber (reg:CC FLAGS_REG))]
9533 "ix86_unary_operator_ok (NEG, QImode, operands)"
9535 [(set_attr "type" "negnot")
9536 (set_attr "mode" "QI")])
9538 (define_insn "*negqi2_cmpz"
9539 [(set (reg:CCZ FLAGS_REG)
9540 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9542 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9543 (neg:QI (match_dup 1)))]
9544 "ix86_unary_operator_ok (NEG, QImode, operands)"
9546 [(set_attr "type" "negnot")
9547 (set_attr "mode" "QI")])
9549 ;; Changing of sign for FP values is doable using integer unit too.
9551 (define_expand "negsf2"
9552 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9553 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9554 "TARGET_80387 || TARGET_SSE_MATH"
9555 "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
9557 (define_expand "abssf2"
9558 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9559 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9560 "TARGET_80387 || TARGET_SSE_MATH"
9561 "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
9563 (define_insn "*absnegsf2_mixed"
9564 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9565 (match_operator:SF 3 "absneg_operator"
9566 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#fr,0 ,0")]))
9567 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
9568 (clobber (reg:CC FLAGS_REG))]
9569 "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9570 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9573 (define_insn "*absnegsf2_sse"
9574 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#r,x#r,rm#x")
9575 (match_operator:SF 3 "absneg_operator"
9576 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#r,0")]))
9577 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X"))
9578 (clobber (reg:CC FLAGS_REG))]
9580 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9583 (define_insn "*absnegsf2_i387"
9584 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9585 (match_operator:SF 3 "absneg_operator"
9586 [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
9587 (use (match_operand 2 "" ""))
9588 (clobber (reg:CC FLAGS_REG))]
9589 "TARGET_80387 && !TARGET_SSE_MATH
9590 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9593 (define_expand "negdf2"
9594 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9595 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9596 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9597 "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
9599 (define_expand "absdf2"
9600 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9601 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9602 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9603 "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
9605 (define_insn "*absnegdf2_mixed"
9606 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
9607 (match_operator:DF 3 "absneg_operator"
9608 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#fr,0 ,0")]))
9609 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
9610 (clobber (reg:CC FLAGS_REG))]
9611 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9612 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9615 (define_insn "*absnegdf2_sse"
9616 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#r,Y#r,rm#Y")
9617 (match_operator:DF 3 "absneg_operator"
9618 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#r,0")]))
9619 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X"))
9620 (clobber (reg:CC FLAGS_REG))]
9621 "TARGET_SSE2 && TARGET_SSE_MATH
9622 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9625 (define_insn "*absnegdf2_i387"
9626 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
9627 (match_operator:DF 3 "absneg_operator"
9628 [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
9629 (use (match_operand 2 "" ""))
9630 (clobber (reg:CC FLAGS_REG))]
9631 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
9632 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9635 (define_expand "negxf2"
9636 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9637 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9639 "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
9641 (define_expand "absxf2"
9642 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9643 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9645 "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
9647 (define_insn "*absnegxf2_i387"
9648 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
9649 (match_operator:XF 3 "absneg_operator"
9650 [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
9651 (use (match_operand 2 "" ""))
9652 (clobber (reg:CC FLAGS_REG))]
9654 && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
9657 ;; Splitters for fp abs and neg.
9660 [(set (match_operand 0 "fp_register_operand" "")
9661 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9662 (use (match_operand 2 "" ""))
9663 (clobber (reg:CC FLAGS_REG))]
9665 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
9668 [(set (match_operand 0 "register_operand" "")
9669 (match_operator 3 "absneg_operator"
9670 [(match_operand 1 "register_operand" "")]))
9671 (use (match_operand 2 "nonimmediate_operand" ""))
9672 (clobber (reg:CC FLAGS_REG))]
9673 "reload_completed && SSE_REG_P (operands[0])"
9674 [(set (match_dup 0) (match_dup 3))]
9676 enum machine_mode mode = GET_MODE (operands[0]);
9677 enum machine_mode vmode = GET_MODE (operands[2]);
9680 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
9681 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
9682 if (operands_match_p (operands[0], operands[2]))
9685 operands[1] = operands[2];
9688 if (GET_CODE (operands[3]) == ABS)
9689 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
9691 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
9696 [(set (match_operand:SF 0 "register_operand" "")
9697 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
9698 (use (match_operand:V4SF 2 "" ""))
9699 (clobber (reg:CC FLAGS_REG))]
9701 [(parallel [(set (match_dup 0) (match_dup 1))
9702 (clobber (reg:CC FLAGS_REG))])]
9705 operands[0] = gen_lowpart (SImode, operands[0]);
9706 if (GET_CODE (operands[1]) == ABS)
9708 tmp = gen_int_mode (0x7fffffff, SImode);
9709 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9713 tmp = gen_int_mode (0x80000000, SImode);
9714 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9720 [(set (match_operand:DF 0 "register_operand" "")
9721 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
9722 (use (match_operand 2 "" ""))
9723 (clobber (reg:CC FLAGS_REG))]
9725 [(parallel [(set (match_dup 0) (match_dup 1))
9726 (clobber (reg:CC FLAGS_REG))])]
9731 tmp = gen_lowpart (DImode, operands[0]);
9732 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
9735 if (GET_CODE (operands[1]) == ABS)
9738 tmp = gen_rtx_NOT (DImode, tmp);
9742 operands[0] = gen_highpart (SImode, operands[0]);
9743 if (GET_CODE (operands[1]) == ABS)
9745 tmp = gen_int_mode (0x7fffffff, SImode);
9746 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9750 tmp = gen_int_mode (0x80000000, SImode);
9751 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9758 [(set (match_operand:XF 0 "register_operand" "")
9759 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
9760 (use (match_operand 2 "" ""))
9761 (clobber (reg:CC FLAGS_REG))]
9763 [(parallel [(set (match_dup 0) (match_dup 1))
9764 (clobber (reg:CC FLAGS_REG))])]
9767 operands[0] = gen_rtx_REG (SImode,
9768 true_regnum (operands[0])
9769 + (TARGET_64BIT ? 1 : 2));
9770 if (GET_CODE (operands[1]) == ABS)
9772 tmp = GEN_INT (0x7fff);
9773 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9777 tmp = GEN_INT (0x8000);
9778 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9784 [(set (match_operand 0 "memory_operand" "")
9785 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9786 (use (match_operand 2 "" ""))
9787 (clobber (reg:CC FLAGS_REG))]
9789 [(parallel [(set (match_dup 0) (match_dup 1))
9790 (clobber (reg:CC FLAGS_REG))])]
9792 enum machine_mode mode = GET_MODE (operands[0]);
9793 int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
9796 operands[0] = adjust_address (operands[0], QImode, size - 1);
9797 if (GET_CODE (operands[1]) == ABS)
9799 tmp = gen_int_mode (0x7f, QImode);
9800 tmp = gen_rtx_AND (QImode, operands[0], tmp);
9804 tmp = gen_int_mode (0x80, QImode);
9805 tmp = gen_rtx_XOR (QImode, operands[0], tmp);
9810 ;; Conditionalize these after reload. If they match before reload, we
9811 ;; lose the clobber and ability to use integer instructions.
9813 (define_insn "*negsf2_1"
9814 [(set (match_operand:SF 0 "register_operand" "=f")
9815 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9816 "TARGET_80387 && reload_completed"
9818 [(set_attr "type" "fsgn")
9819 (set_attr "mode" "SF")])
9821 (define_insn "*negdf2_1"
9822 [(set (match_operand:DF 0 "register_operand" "=f")
9823 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9824 "TARGET_80387 && reload_completed"
9826 [(set_attr "type" "fsgn")
9827 (set_attr "mode" "DF")])
9829 (define_insn "*negxf2_1"
9830 [(set (match_operand:XF 0 "register_operand" "=f")
9831 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9832 "TARGET_80387 && reload_completed"
9834 [(set_attr "type" "fsgn")
9835 (set_attr "mode" "XF")])
9837 (define_insn "*abssf2_1"
9838 [(set (match_operand:SF 0 "register_operand" "=f")
9839 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9840 "TARGET_80387 && reload_completed"
9842 [(set_attr "type" "fsgn")
9843 (set_attr "mode" "SF")])
9845 (define_insn "*absdf2_1"
9846 [(set (match_operand:DF 0 "register_operand" "=f")
9847 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9848 "TARGET_80387 && reload_completed"
9850 [(set_attr "type" "fsgn")
9851 (set_attr "mode" "DF")])
9853 (define_insn "*absxf2_1"
9854 [(set (match_operand:XF 0 "register_operand" "=f")
9855 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9856 "TARGET_80387 && reload_completed"
9858 [(set_attr "type" "fsgn")
9859 (set_attr "mode" "DF")])
9861 (define_insn "*negextendsfdf2"
9862 [(set (match_operand:DF 0 "register_operand" "=f")
9863 (neg:DF (float_extend:DF
9864 (match_operand:SF 1 "register_operand" "0"))))]
9865 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9867 [(set_attr "type" "fsgn")
9868 (set_attr "mode" "DF")])
9870 (define_insn "*negextenddfxf2"
9871 [(set (match_operand:XF 0 "register_operand" "=f")
9872 (neg:XF (float_extend:XF
9873 (match_operand:DF 1 "register_operand" "0"))))]
9876 [(set_attr "type" "fsgn")
9877 (set_attr "mode" "XF")])
9879 (define_insn "*negextendsfxf2"
9880 [(set (match_operand:XF 0 "register_operand" "=f")
9881 (neg:XF (float_extend:XF
9882 (match_operand:SF 1 "register_operand" "0"))))]
9885 [(set_attr "type" "fsgn")
9886 (set_attr "mode" "XF")])
9888 (define_insn "*absextendsfdf2"
9889 [(set (match_operand:DF 0 "register_operand" "=f")
9890 (abs:DF (float_extend:DF
9891 (match_operand:SF 1 "register_operand" "0"))))]
9892 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9894 [(set_attr "type" "fsgn")
9895 (set_attr "mode" "DF")])
9897 (define_insn "*absextenddfxf2"
9898 [(set (match_operand:XF 0 "register_operand" "=f")
9899 (abs:XF (float_extend:XF
9900 (match_operand:DF 1 "register_operand" "0"))))]
9903 [(set_attr "type" "fsgn")
9904 (set_attr "mode" "XF")])
9906 (define_insn "*absextendsfxf2"
9907 [(set (match_operand:XF 0 "register_operand" "=f")
9908 (abs:XF (float_extend:XF
9909 (match_operand:SF 1 "register_operand" "0"))))]
9912 [(set_attr "type" "fsgn")
9913 (set_attr "mode" "XF")])
9915 ;; One complement instructions
9917 (define_expand "one_cmpldi2"
9918 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9919 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9921 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9923 (define_insn "*one_cmpldi2_1_rex64"
9924 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9925 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9926 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9928 [(set_attr "type" "negnot")
9929 (set_attr "mode" "DI")])
9931 (define_insn "*one_cmpldi2_2_rex64"
9932 [(set (reg FLAGS_REG)
9933 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9935 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9936 (not:DI (match_dup 1)))]
9937 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9938 && ix86_unary_operator_ok (NOT, DImode, operands)"
9940 [(set_attr "type" "alu1")
9941 (set_attr "mode" "DI")])
9944 [(set (match_operand 0 "flags_reg_operand" "")
9945 (match_operator 2 "compare_operator"
9946 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
9948 (set (match_operand:DI 1 "nonimmediate_operand" "")
9949 (not:DI (match_dup 3)))]
9950 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9951 [(parallel [(set (match_dup 0)
9953 [(xor:DI (match_dup 3) (const_int -1))
9956 (xor:DI (match_dup 3) (const_int -1)))])]
9959 (define_expand "one_cmplsi2"
9960 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9961 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
9963 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
9965 (define_insn "*one_cmplsi2_1"
9966 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9967 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
9968 "ix86_unary_operator_ok (NOT, SImode, operands)"
9970 [(set_attr "type" "negnot")
9971 (set_attr "mode" "SI")])
9973 ;; ??? Currently never generated - xor is used instead.
9974 (define_insn "*one_cmplsi2_1_zext"
9975 [(set (match_operand:DI 0 "register_operand" "=r")
9976 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
9977 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
9979 [(set_attr "type" "negnot")
9980 (set_attr "mode" "SI")])
9982 (define_insn "*one_cmplsi2_2"
9983 [(set (reg FLAGS_REG)
9984 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9986 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9987 (not:SI (match_dup 1)))]
9988 "ix86_match_ccmode (insn, CCNOmode)
9989 && ix86_unary_operator_ok (NOT, SImode, operands)"
9991 [(set_attr "type" "alu1")
9992 (set_attr "mode" "SI")])
9995 [(set (match_operand 0 "flags_reg_operand" "")
9996 (match_operator 2 "compare_operator"
9997 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
9999 (set (match_operand:SI 1 "nonimmediate_operand" "")
10000 (not:SI (match_dup 3)))]
10001 "ix86_match_ccmode (insn, CCNOmode)"
10002 [(parallel [(set (match_dup 0)
10003 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10006 (xor:SI (match_dup 3) (const_int -1)))])]
10009 ;; ??? Currently never generated - xor is used instead.
10010 (define_insn "*one_cmplsi2_2_zext"
10011 [(set (reg FLAGS_REG)
10012 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10014 (set (match_operand:DI 0 "register_operand" "=r")
10015 (zero_extend:DI (not:SI (match_dup 1))))]
10016 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10017 && ix86_unary_operator_ok (NOT, SImode, operands)"
10019 [(set_attr "type" "alu1")
10020 (set_attr "mode" "SI")])
10023 [(set (match_operand 0 "flags_reg_operand" "")
10024 (match_operator 2 "compare_operator"
10025 [(not:SI (match_operand:SI 3 "register_operand" ""))
10027 (set (match_operand:DI 1 "register_operand" "")
10028 (zero_extend:DI (not:SI (match_dup 3))))]
10029 "ix86_match_ccmode (insn, CCNOmode)"
10030 [(parallel [(set (match_dup 0)
10031 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10034 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10037 (define_expand "one_cmplhi2"
10038 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10039 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10040 "TARGET_HIMODE_MATH"
10041 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10043 (define_insn "*one_cmplhi2_1"
10044 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10045 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10046 "ix86_unary_operator_ok (NOT, HImode, operands)"
10048 [(set_attr "type" "negnot")
10049 (set_attr "mode" "HI")])
10051 (define_insn "*one_cmplhi2_2"
10052 [(set (reg FLAGS_REG)
10053 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10055 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10056 (not:HI (match_dup 1)))]
10057 "ix86_match_ccmode (insn, CCNOmode)
10058 && ix86_unary_operator_ok (NEG, HImode, operands)"
10060 [(set_attr "type" "alu1")
10061 (set_attr "mode" "HI")])
10064 [(set (match_operand 0 "flags_reg_operand" "")
10065 (match_operator 2 "compare_operator"
10066 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10068 (set (match_operand:HI 1 "nonimmediate_operand" "")
10069 (not:HI (match_dup 3)))]
10070 "ix86_match_ccmode (insn, CCNOmode)"
10071 [(parallel [(set (match_dup 0)
10072 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10075 (xor:HI (match_dup 3) (const_int -1)))])]
10078 ;; %%% Potential partial reg stall on alternative 1. What to do?
10079 (define_expand "one_cmplqi2"
10080 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10081 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10082 "TARGET_QIMODE_MATH"
10083 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10085 (define_insn "*one_cmplqi2_1"
10086 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10087 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10088 "ix86_unary_operator_ok (NOT, QImode, operands)"
10092 [(set_attr "type" "negnot")
10093 (set_attr "mode" "QI,SI")])
10095 (define_insn "*one_cmplqi2_2"
10096 [(set (reg FLAGS_REG)
10097 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10099 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10100 (not:QI (match_dup 1)))]
10101 "ix86_match_ccmode (insn, CCNOmode)
10102 && ix86_unary_operator_ok (NOT, QImode, operands)"
10104 [(set_attr "type" "alu1")
10105 (set_attr "mode" "QI")])
10108 [(set (match_operand 0 "flags_reg_operand" "")
10109 (match_operator 2 "compare_operator"
10110 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10112 (set (match_operand:QI 1 "nonimmediate_operand" "")
10113 (not:QI (match_dup 3)))]
10114 "ix86_match_ccmode (insn, CCNOmode)"
10115 [(parallel [(set (match_dup 0)
10116 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10119 (xor:QI (match_dup 3) (const_int -1)))])]
10122 ;; Arithmetic shift instructions
10124 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10125 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10126 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10127 ;; from the assembler input.
10129 ;; This instruction shifts the target reg/mem as usual, but instead of
10130 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10131 ;; is a left shift double, bits are taken from the high order bits of
10132 ;; reg, else if the insn is a shift right double, bits are taken from the
10133 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10134 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10136 ;; Since sh[lr]d does not change the `reg' operand, that is done
10137 ;; separately, making all shifts emit pairs of shift double and normal
10138 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10139 ;; support a 63 bit shift, each shift where the count is in a reg expands
10140 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10142 ;; If the shift count is a constant, we need never emit more than one
10143 ;; shift pair, instead using moves and sign extension for counts greater
10146 (define_expand "ashldi3"
10147 [(set (match_operand:DI 0 "shiftdi_operand" "")
10148 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
10149 (match_operand:QI 2 "nonmemory_operand" "")))]
10151 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
10153 (define_insn "*ashldi3_1_rex64"
10154 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10155 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
10156 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10157 (clobber (reg:CC FLAGS_REG))]
10158 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10160 switch (get_attr_type (insn))
10163 if (operands[2] != const1_rtx)
10165 if (!rtx_equal_p (operands[0], operands[1]))
10167 return "add{q}\t{%0, %0|%0, %0}";
10170 if (GET_CODE (operands[2]) != CONST_INT
10171 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
10173 operands[1] = gen_rtx_MULT (DImode, operands[1],
10174 GEN_INT (1 << INTVAL (operands[2])));
10175 return "lea{q}\t{%a1, %0|%0, %a1}";
10178 if (REG_P (operands[2]))
10179 return "sal{q}\t{%b2, %0|%0, %b2}";
10180 else if (operands[2] == const1_rtx
10181 && (TARGET_SHIFT1 || optimize_size))
10182 return "sal{q}\t%0";
10184 return "sal{q}\t{%2, %0|%0, %2}";
10187 [(set (attr "type")
10188 (cond [(eq_attr "alternative" "1")
10189 (const_string "lea")
10190 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10192 (match_operand 0 "register_operand" ""))
10193 (match_operand 2 "const1_operand" ""))
10194 (const_string "alu")
10196 (const_string "ishift")))
10197 (set_attr "mode" "DI")])
10199 ;; Convert lea to the lea pattern to avoid flags dependency.
10201 [(set (match_operand:DI 0 "register_operand" "")
10202 (ashift:DI (match_operand:DI 1 "index_register_operand" "")
10203 (match_operand:QI 2 "immediate_operand" "")))
10204 (clobber (reg:CC FLAGS_REG))]
10205 "TARGET_64BIT && reload_completed
10206 && true_regnum (operands[0]) != true_regnum (operands[1])"
10207 [(set (match_dup 0)
10208 (mult:DI (match_dup 1)
10210 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10212 ;; This pattern can't accept a variable shift count, since shifts by
10213 ;; zero don't affect the flags. We assume that shifts by constant
10214 ;; zero are optimized away.
10215 (define_insn "*ashldi3_cmp_rex64"
10216 [(set (reg FLAGS_REG)
10218 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10219 (match_operand:QI 2 "immediate_operand" "e"))
10221 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10222 (ashift:DI (match_dup 1) (match_dup 2)))]
10223 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10224 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10226 switch (get_attr_type (insn))
10229 if (operands[2] != const1_rtx)
10231 return "add{q}\t{%0, %0|%0, %0}";
10234 if (REG_P (operands[2]))
10235 return "sal{q}\t{%b2, %0|%0, %b2}";
10236 else if (operands[2] == const1_rtx
10237 && (TARGET_SHIFT1 || optimize_size))
10238 return "sal{q}\t%0";
10240 return "sal{q}\t{%2, %0|%0, %2}";
10243 [(set (attr "type")
10244 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10246 (match_operand 0 "register_operand" ""))
10247 (match_operand 2 "const1_operand" ""))
10248 (const_string "alu")
10250 (const_string "ishift")))
10251 (set_attr "mode" "DI")])
10253 (define_insn "*ashldi3_1"
10254 [(set (match_operand:DI 0 "register_operand" "=&r,r")
10255 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
10256 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
10257 (clobber (reg:CC FLAGS_REG))]
10260 [(set_attr "type" "multi")])
10262 ;; By default we don't ask for a scratch register, because when DImode
10263 ;; values are manipulated, registers are already at a premium. But if
10264 ;; we have one handy, we won't turn it away.
10266 [(match_scratch:SI 3 "r")
10267 (parallel [(set (match_operand:DI 0 "register_operand" "")
10268 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10269 (match_operand:QI 2 "nonmemory_operand" "")))
10270 (clobber (reg:CC FLAGS_REG))])
10272 "!TARGET_64BIT && TARGET_CMOVE"
10274 "ix86_split_ashldi (operands, operands[3]); DONE;")
10277 [(set (match_operand:DI 0 "register_operand" "")
10278 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10279 (match_operand:QI 2 "nonmemory_operand" "")))
10280 (clobber (reg:CC FLAGS_REG))]
10281 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10283 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
10285 (define_insn "x86_shld_1"
10286 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10287 (ior:SI (ashift:SI (match_dup 0)
10288 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10289 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10290 (minus:QI (const_int 32) (match_dup 2)))))
10291 (clobber (reg:CC FLAGS_REG))]
10294 shld{l}\t{%2, %1, %0|%0, %1, %2}
10295 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10296 [(set_attr "type" "ishift")
10297 (set_attr "prefix_0f" "1")
10298 (set_attr "mode" "SI")
10299 (set_attr "pent_pair" "np")
10300 (set_attr "athlon_decode" "vector")])
10302 (define_expand "x86_shift_adj_1"
10303 [(set (reg:CCZ FLAGS_REG)
10304 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10307 (set (match_operand:SI 0 "register_operand" "")
10308 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10309 (match_operand:SI 1 "register_operand" "")
10312 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10313 (match_operand:SI 3 "register_operand" "r")
10318 (define_expand "x86_shift_adj_2"
10319 [(use (match_operand:SI 0 "register_operand" ""))
10320 (use (match_operand:SI 1 "register_operand" ""))
10321 (use (match_operand:QI 2 "register_operand" ""))]
10324 rtx label = gen_label_rtx ();
10327 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10329 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10330 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10331 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10332 gen_rtx_LABEL_REF (VOIDmode, label),
10334 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10335 JUMP_LABEL (tmp) = label;
10337 emit_move_insn (operands[0], operands[1]);
10338 ix86_expand_clear (operands[1]);
10340 emit_label (label);
10341 LABEL_NUSES (label) = 1;
10346 (define_expand "ashlsi3"
10347 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10348 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10349 (match_operand:QI 2 "nonmemory_operand" "")))
10350 (clobber (reg:CC FLAGS_REG))]
10352 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10354 (define_insn "*ashlsi3_1"
10355 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10356 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
10357 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10358 (clobber (reg:CC FLAGS_REG))]
10359 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10361 switch (get_attr_type (insn))
10364 if (operands[2] != const1_rtx)
10366 if (!rtx_equal_p (operands[0], operands[1]))
10368 return "add{l}\t{%0, %0|%0, %0}";
10374 if (REG_P (operands[2]))
10375 return "sal{l}\t{%b2, %0|%0, %b2}";
10376 else if (operands[2] == const1_rtx
10377 && (TARGET_SHIFT1 || optimize_size))
10378 return "sal{l}\t%0";
10380 return "sal{l}\t{%2, %0|%0, %2}";
10383 [(set (attr "type")
10384 (cond [(eq_attr "alternative" "1")
10385 (const_string "lea")
10386 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10388 (match_operand 0 "register_operand" ""))
10389 (match_operand 2 "const1_operand" ""))
10390 (const_string "alu")
10392 (const_string "ishift")))
10393 (set_attr "mode" "SI")])
10395 ;; Convert lea to the lea pattern to avoid flags dependency.
10397 [(set (match_operand 0 "register_operand" "")
10398 (ashift (match_operand 1 "index_register_operand" "")
10399 (match_operand:QI 2 "const_int_operand" "")))
10400 (clobber (reg:CC FLAGS_REG))]
10402 && true_regnum (operands[0]) != true_regnum (operands[1])
10403 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
10407 enum machine_mode mode = GET_MODE (operands[0]);
10409 if (GET_MODE_SIZE (mode) < 4)
10410 operands[0] = gen_lowpart (SImode, operands[0]);
10412 operands[1] = gen_lowpart (Pmode, operands[1]);
10413 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10415 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10416 if (Pmode != SImode)
10417 pat = gen_rtx_SUBREG (SImode, pat, 0);
10418 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10422 ;; Rare case of shifting RSP is handled by generating move and shift
10424 [(set (match_operand 0 "register_operand" "")
10425 (ashift (match_operand 1 "register_operand" "")
10426 (match_operand:QI 2 "const_int_operand" "")))
10427 (clobber (reg:CC FLAGS_REG))]
10429 && true_regnum (operands[0]) != true_regnum (operands[1])"
10433 emit_move_insn (operands[1], operands[0]);
10434 pat = gen_rtx_SET (VOIDmode, operands[0],
10435 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10436 operands[0], operands[2]));
10437 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10438 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10442 (define_insn "*ashlsi3_1_zext"
10443 [(set (match_operand:DI 0 "register_operand" "=r,r")
10444 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
10445 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10446 (clobber (reg:CC FLAGS_REG))]
10447 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10449 switch (get_attr_type (insn))
10452 if (operands[2] != const1_rtx)
10454 return "add{l}\t{%k0, %k0|%k0, %k0}";
10460 if (REG_P (operands[2]))
10461 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10462 else if (operands[2] == const1_rtx
10463 && (TARGET_SHIFT1 || optimize_size))
10464 return "sal{l}\t%k0";
10466 return "sal{l}\t{%2, %k0|%k0, %2}";
10469 [(set (attr "type")
10470 (cond [(eq_attr "alternative" "1")
10471 (const_string "lea")
10472 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10474 (match_operand 2 "const1_operand" ""))
10475 (const_string "alu")
10477 (const_string "ishift")))
10478 (set_attr "mode" "SI")])
10480 ;; Convert lea to the lea pattern to avoid flags dependency.
10482 [(set (match_operand:DI 0 "register_operand" "")
10483 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10484 (match_operand:QI 2 "const_int_operand" ""))))
10485 (clobber (reg:CC FLAGS_REG))]
10486 "TARGET_64BIT && reload_completed
10487 && true_regnum (operands[0]) != true_regnum (operands[1])"
10488 [(set (match_dup 0) (zero_extend:DI
10489 (subreg:SI (mult:SI (match_dup 1)
10490 (match_dup 2)) 0)))]
10492 operands[1] = gen_lowpart (Pmode, operands[1]);
10493 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10496 ;; This pattern can't accept a variable shift count, since shifts by
10497 ;; zero don't affect the flags. We assume that shifts by constant
10498 ;; zero are optimized away.
10499 (define_insn "*ashlsi3_cmp"
10500 [(set (reg FLAGS_REG)
10502 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10503 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10505 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10506 (ashift:SI (match_dup 1) (match_dup 2)))]
10507 "ix86_match_ccmode (insn, CCGOCmode)
10508 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10510 switch (get_attr_type (insn))
10513 if (operands[2] != const1_rtx)
10515 return "add{l}\t{%0, %0|%0, %0}";
10518 if (REG_P (operands[2]))
10519 return "sal{l}\t{%b2, %0|%0, %b2}";
10520 else if (operands[2] == const1_rtx
10521 && (TARGET_SHIFT1 || optimize_size))
10522 return "sal{l}\t%0";
10524 return "sal{l}\t{%2, %0|%0, %2}";
10527 [(set (attr "type")
10528 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10530 (match_operand 0 "register_operand" ""))
10531 (match_operand 2 "const1_operand" ""))
10532 (const_string "alu")
10534 (const_string "ishift")))
10535 (set_attr "mode" "SI")])
10537 (define_insn "*ashlsi3_cmp_zext"
10538 [(set (reg FLAGS_REG)
10540 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10541 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10543 (set (match_operand:DI 0 "register_operand" "=r")
10544 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10545 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10546 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10548 switch (get_attr_type (insn))
10551 if (operands[2] != const1_rtx)
10553 return "add{l}\t{%k0, %k0|%k0, %k0}";
10556 if (REG_P (operands[2]))
10557 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10558 else if (operands[2] == const1_rtx
10559 && (TARGET_SHIFT1 || optimize_size))
10560 return "sal{l}\t%k0";
10562 return "sal{l}\t{%2, %k0|%k0, %2}";
10565 [(set (attr "type")
10566 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10568 (match_operand 2 "const1_operand" ""))
10569 (const_string "alu")
10571 (const_string "ishift")))
10572 (set_attr "mode" "SI")])
10574 (define_expand "ashlhi3"
10575 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10576 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10577 (match_operand:QI 2 "nonmemory_operand" "")))
10578 (clobber (reg:CC FLAGS_REG))]
10579 "TARGET_HIMODE_MATH"
10580 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10582 (define_insn "*ashlhi3_1_lea"
10583 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10584 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
10585 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10586 (clobber (reg:CC FLAGS_REG))]
10587 "!TARGET_PARTIAL_REG_STALL
10588 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10590 switch (get_attr_type (insn))
10595 if (operands[2] != const1_rtx)
10597 return "add{w}\t{%0, %0|%0, %0}";
10600 if (REG_P (operands[2]))
10601 return "sal{w}\t{%b2, %0|%0, %b2}";
10602 else if (operands[2] == const1_rtx
10603 && (TARGET_SHIFT1 || optimize_size))
10604 return "sal{w}\t%0";
10606 return "sal{w}\t{%2, %0|%0, %2}";
10609 [(set (attr "type")
10610 (cond [(eq_attr "alternative" "1")
10611 (const_string "lea")
10612 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10614 (match_operand 0 "register_operand" ""))
10615 (match_operand 2 "const1_operand" ""))
10616 (const_string "alu")
10618 (const_string "ishift")))
10619 (set_attr "mode" "HI,SI")])
10621 (define_insn "*ashlhi3_1"
10622 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10623 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10624 (match_operand:QI 2 "nonmemory_operand" "cI")))
10625 (clobber (reg:CC FLAGS_REG))]
10626 "TARGET_PARTIAL_REG_STALL
10627 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10629 switch (get_attr_type (insn))
10632 if (operands[2] != const1_rtx)
10634 return "add{w}\t{%0, %0|%0, %0}";
10637 if (REG_P (operands[2]))
10638 return "sal{w}\t{%b2, %0|%0, %b2}";
10639 else if (operands[2] == const1_rtx
10640 && (TARGET_SHIFT1 || optimize_size))
10641 return "sal{w}\t%0";
10643 return "sal{w}\t{%2, %0|%0, %2}";
10646 [(set (attr "type")
10647 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10649 (match_operand 0 "register_operand" ""))
10650 (match_operand 2 "const1_operand" ""))
10651 (const_string "alu")
10653 (const_string "ishift")))
10654 (set_attr "mode" "HI")])
10656 ;; This pattern can't accept a variable shift count, since shifts by
10657 ;; zero don't affect the flags. We assume that shifts by constant
10658 ;; zero are optimized away.
10659 (define_insn "*ashlhi3_cmp"
10660 [(set (reg FLAGS_REG)
10662 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10663 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10665 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10666 (ashift:HI (match_dup 1) (match_dup 2)))]
10667 "ix86_match_ccmode (insn, CCGOCmode)
10668 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10670 switch (get_attr_type (insn))
10673 if (operands[2] != const1_rtx)
10675 return "add{w}\t{%0, %0|%0, %0}";
10678 if (REG_P (operands[2]))
10679 return "sal{w}\t{%b2, %0|%0, %b2}";
10680 else if (operands[2] == const1_rtx
10681 && (TARGET_SHIFT1 || optimize_size))
10682 return "sal{w}\t%0";
10684 return "sal{w}\t{%2, %0|%0, %2}";
10687 [(set (attr "type")
10688 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10690 (match_operand 0 "register_operand" ""))
10691 (match_operand 2 "const1_operand" ""))
10692 (const_string "alu")
10694 (const_string "ishift")))
10695 (set_attr "mode" "HI")])
10697 (define_expand "ashlqi3"
10698 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10699 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10700 (match_operand:QI 2 "nonmemory_operand" "")))
10701 (clobber (reg:CC FLAGS_REG))]
10702 "TARGET_QIMODE_MATH"
10703 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10705 ;; %%% Potential partial reg stall on alternative 2. What to do?
10707 (define_insn "*ashlqi3_1_lea"
10708 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10709 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
10710 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10711 (clobber (reg:CC FLAGS_REG))]
10712 "!TARGET_PARTIAL_REG_STALL
10713 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10715 switch (get_attr_type (insn))
10720 if (operands[2] != const1_rtx)
10722 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10723 return "add{l}\t{%k0, %k0|%k0, %k0}";
10725 return "add{b}\t{%0, %0|%0, %0}";
10728 if (REG_P (operands[2]))
10730 if (get_attr_mode (insn) == MODE_SI)
10731 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10733 return "sal{b}\t{%b2, %0|%0, %b2}";
10735 else if (operands[2] == const1_rtx
10736 && (TARGET_SHIFT1 || optimize_size))
10738 if (get_attr_mode (insn) == MODE_SI)
10739 return "sal{l}\t%0";
10741 return "sal{b}\t%0";
10745 if (get_attr_mode (insn) == MODE_SI)
10746 return "sal{l}\t{%2, %k0|%k0, %2}";
10748 return "sal{b}\t{%2, %0|%0, %2}";
10752 [(set (attr "type")
10753 (cond [(eq_attr "alternative" "2")
10754 (const_string "lea")
10755 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10757 (match_operand 0 "register_operand" ""))
10758 (match_operand 2 "const1_operand" ""))
10759 (const_string "alu")
10761 (const_string "ishift")))
10762 (set_attr "mode" "QI,SI,SI")])
10764 (define_insn "*ashlqi3_1"
10765 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10766 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10767 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10768 (clobber (reg:CC FLAGS_REG))]
10769 "TARGET_PARTIAL_REG_STALL
10770 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10772 switch (get_attr_type (insn))
10775 if (operands[2] != const1_rtx)
10777 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10778 return "add{l}\t{%k0, %k0|%k0, %k0}";
10780 return "add{b}\t{%0, %0|%0, %0}";
10783 if (REG_P (operands[2]))
10785 if (get_attr_mode (insn) == MODE_SI)
10786 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10788 return "sal{b}\t{%b2, %0|%0, %b2}";
10790 else if (operands[2] == const1_rtx
10791 && (TARGET_SHIFT1 || optimize_size))
10793 if (get_attr_mode (insn) == MODE_SI)
10794 return "sal{l}\t%0";
10796 return "sal{b}\t%0";
10800 if (get_attr_mode (insn) == MODE_SI)
10801 return "sal{l}\t{%2, %k0|%k0, %2}";
10803 return "sal{b}\t{%2, %0|%0, %2}";
10807 [(set (attr "type")
10808 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10810 (match_operand 0 "register_operand" ""))
10811 (match_operand 2 "const1_operand" ""))
10812 (const_string "alu")
10814 (const_string "ishift")))
10815 (set_attr "mode" "QI,SI")])
10817 ;; This pattern can't accept a variable shift count, since shifts by
10818 ;; zero don't affect the flags. We assume that shifts by constant
10819 ;; zero are optimized away.
10820 (define_insn "*ashlqi3_cmp"
10821 [(set (reg FLAGS_REG)
10823 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10824 (match_operand:QI 2 "const_int_1_31_operand" "I"))
10826 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10827 (ashift:QI (match_dup 1) (match_dup 2)))]
10828 "ix86_match_ccmode (insn, CCGOCmode)
10829 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10831 switch (get_attr_type (insn))
10834 if (operands[2] != const1_rtx)
10836 return "add{b}\t{%0, %0|%0, %0}";
10839 if (REG_P (operands[2]))
10840 return "sal{b}\t{%b2, %0|%0, %b2}";
10841 else if (operands[2] == const1_rtx
10842 && (TARGET_SHIFT1 || optimize_size))
10843 return "sal{b}\t%0";
10845 return "sal{b}\t{%2, %0|%0, %2}";
10848 [(set (attr "type")
10849 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10851 (match_operand 0 "register_operand" ""))
10852 (match_operand 2 "const1_operand" ""))
10853 (const_string "alu")
10855 (const_string "ishift")))
10856 (set_attr "mode" "QI")])
10858 ;; See comment above `ashldi3' about how this works.
10860 (define_expand "ashrdi3"
10861 [(set (match_operand:DI 0 "shiftdi_operand" "")
10862 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
10863 (match_operand:QI 2 "nonmemory_operand" "")))]
10865 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
10867 (define_insn "*ashrdi3_63_rex64"
10868 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
10869 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
10870 (match_operand:DI 2 "const_int_operand" "i,i")))
10871 (clobber (reg:CC FLAGS_REG))]
10872 "TARGET_64BIT && INTVAL (operands[2]) == 63
10873 && (TARGET_USE_CLTD || optimize_size)
10874 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10877 sar{q}\t{%2, %0|%0, %2}"
10878 [(set_attr "type" "imovx,ishift")
10879 (set_attr "prefix_0f" "0,*")
10880 (set_attr "length_immediate" "0,*")
10881 (set_attr "modrm" "0,1")
10882 (set_attr "mode" "DI")])
10884 (define_insn "*ashrdi3_1_one_bit_rex64"
10885 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10886 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10887 (match_operand:QI 2 "const1_operand" "")))
10888 (clobber (reg:CC FLAGS_REG))]
10889 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
10890 && (TARGET_SHIFT1 || optimize_size)"
10892 [(set_attr "type" "ishift")
10893 (set (attr "length")
10894 (if_then_else (match_operand:DI 0 "register_operand" "")
10896 (const_string "*")))])
10898 (define_insn "*ashrdi3_1_rex64"
10899 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
10900 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
10901 (match_operand:QI 2 "nonmemory_operand" "J,c")))
10902 (clobber (reg:CC FLAGS_REG))]
10903 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10905 sar{q}\t{%2, %0|%0, %2}
10906 sar{q}\t{%b2, %0|%0, %b2}"
10907 [(set_attr "type" "ishift")
10908 (set_attr "mode" "DI")])
10910 ;; This pattern can't accept a variable shift count, since shifts by
10911 ;; zero don't affect the flags. We assume that shifts by constant
10912 ;; zero are optimized away.
10913 (define_insn "*ashrdi3_one_bit_cmp_rex64"
10914 [(set (reg FLAGS_REG)
10916 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10917 (match_operand:QI 2 "const1_operand" ""))
10919 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10920 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10921 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10922 && (TARGET_SHIFT1 || optimize_size)
10923 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10925 [(set_attr "type" "ishift")
10926 (set (attr "length")
10927 (if_then_else (match_operand:DI 0 "register_operand" "")
10929 (const_string "*")))])
10931 ;; This pattern can't accept a variable shift count, since shifts by
10932 ;; zero don't affect the flags. We assume that shifts by constant
10933 ;; zero are optimized away.
10934 (define_insn "*ashrdi3_cmp_rex64"
10935 [(set (reg FLAGS_REG)
10937 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10938 (match_operand:QI 2 "const_int_operand" "n"))
10940 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10941 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
10942 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10943 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
10944 "sar{q}\t{%2, %0|%0, %2}"
10945 [(set_attr "type" "ishift")
10946 (set_attr "mode" "DI")])
10948 (define_insn "*ashrdi3_1"
10949 [(set (match_operand:DI 0 "register_operand" "=r")
10950 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
10951 (match_operand:QI 2 "nonmemory_operand" "Jc")))
10952 (clobber (reg:CC FLAGS_REG))]
10955 [(set_attr "type" "multi")])
10957 ;; By default we don't ask for a scratch register, because when DImode
10958 ;; values are manipulated, registers are already at a premium. But if
10959 ;; we have one handy, we won't turn it away.
10961 [(match_scratch:SI 3 "r")
10962 (parallel [(set (match_operand:DI 0 "register_operand" "")
10963 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10964 (match_operand:QI 2 "nonmemory_operand" "")))
10965 (clobber (reg:CC FLAGS_REG))])
10967 "!TARGET_64BIT && TARGET_CMOVE"
10969 "ix86_split_ashrdi (operands, operands[3]); DONE;")
10972 [(set (match_operand:DI 0 "register_operand" "")
10973 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
10974 (match_operand:QI 2 "nonmemory_operand" "")))
10975 (clobber (reg:CC FLAGS_REG))]
10976 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
10978 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
10980 (define_insn "x86_shrd_1"
10981 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10982 (ior:SI (ashiftrt:SI (match_dup 0)
10983 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10984 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
10985 (minus:QI (const_int 32) (match_dup 2)))))
10986 (clobber (reg:CC FLAGS_REG))]
10989 shrd{l}\t{%2, %1, %0|%0, %1, %2}
10990 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
10991 [(set_attr "type" "ishift")
10992 (set_attr "prefix_0f" "1")
10993 (set_attr "pent_pair" "np")
10994 (set_attr "mode" "SI")])
10996 (define_expand "x86_shift_adj_3"
10997 [(use (match_operand:SI 0 "register_operand" ""))
10998 (use (match_operand:SI 1 "register_operand" ""))
10999 (use (match_operand:QI 2 "register_operand" ""))]
11002 rtx label = gen_label_rtx ();
11005 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11007 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11008 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11009 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11010 gen_rtx_LABEL_REF (VOIDmode, label),
11012 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11013 JUMP_LABEL (tmp) = label;
11015 emit_move_insn (operands[0], operands[1]);
11016 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11018 emit_label (label);
11019 LABEL_NUSES (label) = 1;
11024 (define_insn "ashrsi3_31"
11025 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11026 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11027 (match_operand:SI 2 "const_int_operand" "i,i")))
11028 (clobber (reg:CC FLAGS_REG))]
11029 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11030 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11033 sar{l}\t{%2, %0|%0, %2}"
11034 [(set_attr "type" "imovx,ishift")
11035 (set_attr "prefix_0f" "0,*")
11036 (set_attr "length_immediate" "0,*")
11037 (set_attr "modrm" "0,1")
11038 (set_attr "mode" "SI")])
11040 (define_insn "*ashrsi3_31_zext"
11041 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11042 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11043 (match_operand:SI 2 "const_int_operand" "i,i"))))
11044 (clobber (reg:CC FLAGS_REG))]
11045 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11046 && INTVAL (operands[2]) == 31
11047 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11050 sar{l}\t{%2, %k0|%k0, %2}"
11051 [(set_attr "type" "imovx,ishift")
11052 (set_attr "prefix_0f" "0,*")
11053 (set_attr "length_immediate" "0,*")
11054 (set_attr "modrm" "0,1")
11055 (set_attr "mode" "SI")])
11057 (define_expand "ashrsi3"
11058 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11059 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11060 (match_operand:QI 2 "nonmemory_operand" "")))
11061 (clobber (reg:CC FLAGS_REG))]
11063 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11065 (define_insn "*ashrsi3_1_one_bit"
11066 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11067 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11068 (match_operand:QI 2 "const1_operand" "")))
11069 (clobber (reg:CC FLAGS_REG))]
11070 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11071 && (TARGET_SHIFT1 || optimize_size)"
11073 [(set_attr "type" "ishift")
11074 (set (attr "length")
11075 (if_then_else (match_operand:SI 0 "register_operand" "")
11077 (const_string "*")))])
11079 (define_insn "*ashrsi3_1_one_bit_zext"
11080 [(set (match_operand:DI 0 "register_operand" "=r")
11081 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11082 (match_operand:QI 2 "const1_operand" ""))))
11083 (clobber (reg:CC FLAGS_REG))]
11084 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11085 && (TARGET_SHIFT1 || optimize_size)"
11087 [(set_attr "type" "ishift")
11088 (set_attr "length" "2")])
11090 (define_insn "*ashrsi3_1"
11091 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11092 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11093 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11094 (clobber (reg:CC FLAGS_REG))]
11095 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11097 sar{l}\t{%2, %0|%0, %2}
11098 sar{l}\t{%b2, %0|%0, %b2}"
11099 [(set_attr "type" "ishift")
11100 (set_attr "mode" "SI")])
11102 (define_insn "*ashrsi3_1_zext"
11103 [(set (match_operand:DI 0 "register_operand" "=r,r")
11104 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11105 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11106 (clobber (reg:CC FLAGS_REG))]
11107 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11109 sar{l}\t{%2, %k0|%k0, %2}
11110 sar{l}\t{%b2, %k0|%k0, %b2}"
11111 [(set_attr "type" "ishift")
11112 (set_attr "mode" "SI")])
11114 ;; This pattern can't accept a variable shift count, since shifts by
11115 ;; zero don't affect the flags. We assume that shifts by constant
11116 ;; zero are optimized away.
11117 (define_insn "*ashrsi3_one_bit_cmp"
11118 [(set (reg FLAGS_REG)
11120 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11121 (match_operand:QI 2 "const1_operand" ""))
11123 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11124 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11125 "ix86_match_ccmode (insn, CCGOCmode)
11126 && (TARGET_SHIFT1 || optimize_size)
11127 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11129 [(set_attr "type" "ishift")
11130 (set (attr "length")
11131 (if_then_else (match_operand:SI 0 "register_operand" "")
11133 (const_string "*")))])
11135 (define_insn "*ashrsi3_one_bit_cmp_zext"
11136 [(set (reg FLAGS_REG)
11138 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11139 (match_operand:QI 2 "const1_operand" ""))
11141 (set (match_operand:DI 0 "register_operand" "=r")
11142 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11143 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11144 && (TARGET_SHIFT1 || optimize_size)
11145 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11147 [(set_attr "type" "ishift")
11148 (set_attr "length" "2")])
11150 ;; This pattern can't accept a variable shift count, since shifts by
11151 ;; zero don't affect the flags. We assume that shifts by constant
11152 ;; zero are optimized away.
11153 (define_insn "*ashrsi3_cmp"
11154 [(set (reg FLAGS_REG)
11156 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11157 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11159 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11160 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11161 "ix86_match_ccmode (insn, CCGOCmode)
11162 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11163 "sar{l}\t{%2, %0|%0, %2}"
11164 [(set_attr "type" "ishift")
11165 (set_attr "mode" "SI")])
11167 (define_insn "*ashrsi3_cmp_zext"
11168 [(set (reg FLAGS_REG)
11170 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11171 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11173 (set (match_operand:DI 0 "register_operand" "=r")
11174 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11175 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11176 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11177 "sar{l}\t{%2, %k0|%k0, %2}"
11178 [(set_attr "type" "ishift")
11179 (set_attr "mode" "SI")])
11181 (define_expand "ashrhi3"
11182 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11183 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11184 (match_operand:QI 2 "nonmemory_operand" "")))
11185 (clobber (reg:CC FLAGS_REG))]
11186 "TARGET_HIMODE_MATH"
11187 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11189 (define_insn "*ashrhi3_1_one_bit"
11190 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11191 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11192 (match_operand:QI 2 "const1_operand" "")))
11193 (clobber (reg:CC FLAGS_REG))]
11194 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11195 && (TARGET_SHIFT1 || optimize_size)"
11197 [(set_attr "type" "ishift")
11198 (set (attr "length")
11199 (if_then_else (match_operand 0 "register_operand" "")
11201 (const_string "*")))])
11203 (define_insn "*ashrhi3_1"
11204 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11205 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11206 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11207 (clobber (reg:CC FLAGS_REG))]
11208 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11210 sar{w}\t{%2, %0|%0, %2}
11211 sar{w}\t{%b2, %0|%0, %b2}"
11212 [(set_attr "type" "ishift")
11213 (set_attr "mode" "HI")])
11215 ;; This pattern can't accept a variable shift count, since shifts by
11216 ;; zero don't affect the flags. We assume that shifts by constant
11217 ;; zero are optimized away.
11218 (define_insn "*ashrhi3_one_bit_cmp"
11219 [(set (reg FLAGS_REG)
11221 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11222 (match_operand:QI 2 "const1_operand" ""))
11224 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11225 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11226 "ix86_match_ccmode (insn, CCGOCmode)
11227 && (TARGET_SHIFT1 || optimize_size)
11228 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11230 [(set_attr "type" "ishift")
11231 (set (attr "length")
11232 (if_then_else (match_operand 0 "register_operand" "")
11234 (const_string "*")))])
11236 ;; This pattern can't accept a variable shift count, since shifts by
11237 ;; zero don't affect the flags. We assume that shifts by constant
11238 ;; zero are optimized away.
11239 (define_insn "*ashrhi3_cmp"
11240 [(set (reg FLAGS_REG)
11242 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11243 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11245 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11246 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11247 "ix86_match_ccmode (insn, CCGOCmode)
11248 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11249 "sar{w}\t{%2, %0|%0, %2}"
11250 [(set_attr "type" "ishift")
11251 (set_attr "mode" "HI")])
11253 (define_expand "ashrqi3"
11254 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11255 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11256 (match_operand:QI 2 "nonmemory_operand" "")))
11257 (clobber (reg:CC FLAGS_REG))]
11258 "TARGET_QIMODE_MATH"
11259 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11261 (define_insn "*ashrqi3_1_one_bit"
11262 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11263 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11264 (match_operand:QI 2 "const1_operand" "")))
11265 (clobber (reg:CC FLAGS_REG))]
11266 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11267 && (TARGET_SHIFT1 || optimize_size)"
11269 [(set_attr "type" "ishift")
11270 (set (attr "length")
11271 (if_then_else (match_operand 0 "register_operand" "")
11273 (const_string "*")))])
11275 (define_insn "*ashrqi3_1_one_bit_slp"
11276 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11277 (ashiftrt:QI (match_dup 0)
11278 (match_operand:QI 1 "const1_operand" "")))
11279 (clobber (reg:CC FLAGS_REG))]
11280 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11281 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11282 && (TARGET_SHIFT1 || optimize_size)"
11284 [(set_attr "type" "ishift1")
11285 (set (attr "length")
11286 (if_then_else (match_operand 0 "register_operand" "")
11288 (const_string "*")))])
11290 (define_insn "*ashrqi3_1"
11291 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11292 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11293 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11294 (clobber (reg:CC FLAGS_REG))]
11295 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11297 sar{b}\t{%2, %0|%0, %2}
11298 sar{b}\t{%b2, %0|%0, %b2}"
11299 [(set_attr "type" "ishift")
11300 (set_attr "mode" "QI")])
11302 (define_insn "*ashrqi3_1_slp"
11303 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11304 (ashiftrt:QI (match_dup 0)
11305 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11306 (clobber (reg:CC FLAGS_REG))]
11307 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11308 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11310 sar{b}\t{%1, %0|%0, %1}
11311 sar{b}\t{%b1, %0|%0, %b1}"
11312 [(set_attr "type" "ishift1")
11313 (set_attr "mode" "QI")])
11315 ;; This pattern can't accept a variable shift count, since shifts by
11316 ;; zero don't affect the flags. We assume that shifts by constant
11317 ;; zero are optimized away.
11318 (define_insn "*ashrqi3_one_bit_cmp"
11319 [(set (reg FLAGS_REG)
11321 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11322 (match_operand:QI 2 "const1_operand" "I"))
11324 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11325 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11326 "ix86_match_ccmode (insn, CCGOCmode)
11327 && (TARGET_SHIFT1 || optimize_size)
11328 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11330 [(set_attr "type" "ishift")
11331 (set (attr "length")
11332 (if_then_else (match_operand 0 "register_operand" "")
11334 (const_string "*")))])
11336 ;; This pattern can't accept a variable shift count, since shifts by
11337 ;; zero don't affect the flags. We assume that shifts by constant
11338 ;; zero are optimized away.
11339 (define_insn "*ashrqi3_cmp"
11340 [(set (reg FLAGS_REG)
11342 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11343 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11345 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11346 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11347 "ix86_match_ccmode (insn, CCGOCmode)
11348 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11349 "sar{b}\t{%2, %0|%0, %2}"
11350 [(set_attr "type" "ishift")
11351 (set_attr "mode" "QI")])
11353 ;; Logical shift instructions
11355 ;; See comment above `ashldi3' about how this works.
11357 (define_expand "lshrdi3"
11358 [(set (match_operand:DI 0 "shiftdi_operand" "")
11359 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11360 (match_operand:QI 2 "nonmemory_operand" "")))]
11362 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
11364 (define_insn "*lshrdi3_1_one_bit_rex64"
11365 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11366 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11367 (match_operand:QI 2 "const1_operand" "")))
11368 (clobber (reg:CC FLAGS_REG))]
11369 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11370 && (TARGET_SHIFT1 || optimize_size)"
11372 [(set_attr "type" "ishift")
11373 (set (attr "length")
11374 (if_then_else (match_operand:DI 0 "register_operand" "")
11376 (const_string "*")))])
11378 (define_insn "*lshrdi3_1_rex64"
11379 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11380 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11381 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11382 (clobber (reg:CC FLAGS_REG))]
11383 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11385 shr{q}\t{%2, %0|%0, %2}
11386 shr{q}\t{%b2, %0|%0, %b2}"
11387 [(set_attr "type" "ishift")
11388 (set_attr "mode" "DI")])
11390 ;; This pattern can't accept a variable shift count, since shifts by
11391 ;; zero don't affect the flags. We assume that shifts by constant
11392 ;; zero are optimized away.
11393 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11394 [(set (reg FLAGS_REG)
11396 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11397 (match_operand:QI 2 "const1_operand" ""))
11399 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11400 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11401 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11402 && (TARGET_SHIFT1 || optimize_size)
11403 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11405 [(set_attr "type" "ishift")
11406 (set (attr "length")
11407 (if_then_else (match_operand:DI 0 "register_operand" "")
11409 (const_string "*")))])
11411 ;; This pattern can't accept a variable shift count, since shifts by
11412 ;; zero don't affect the flags. We assume that shifts by constant
11413 ;; zero are optimized away.
11414 (define_insn "*lshrdi3_cmp_rex64"
11415 [(set (reg FLAGS_REG)
11417 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11418 (match_operand:QI 2 "const_int_operand" "e"))
11420 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11421 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11422 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11423 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11424 "shr{q}\t{%2, %0|%0, %2}"
11425 [(set_attr "type" "ishift")
11426 (set_attr "mode" "DI")])
11428 (define_insn "*lshrdi3_1"
11429 [(set (match_operand:DI 0 "register_operand" "=r")
11430 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11431 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11432 (clobber (reg:CC FLAGS_REG))]
11435 [(set_attr "type" "multi")])
11437 ;; By default we don't ask for a scratch register, because when DImode
11438 ;; values are manipulated, registers are already at a premium. But if
11439 ;; we have one handy, we won't turn it away.
11441 [(match_scratch:SI 3 "r")
11442 (parallel [(set (match_operand:DI 0 "register_operand" "")
11443 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11444 (match_operand:QI 2 "nonmemory_operand" "")))
11445 (clobber (reg:CC FLAGS_REG))])
11447 "!TARGET_64BIT && TARGET_CMOVE"
11449 "ix86_split_lshrdi (operands, operands[3]); DONE;")
11452 [(set (match_operand:DI 0 "register_operand" "")
11453 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11454 (match_operand:QI 2 "nonmemory_operand" "")))
11455 (clobber (reg:CC FLAGS_REG))]
11456 "!TARGET_64BIT && (flag_peephole2 ? flow2_completed : reload_completed)"
11458 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
11460 (define_expand "lshrsi3"
11461 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11462 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11463 (match_operand:QI 2 "nonmemory_operand" "")))
11464 (clobber (reg:CC FLAGS_REG))]
11466 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11468 (define_insn "*lshrsi3_1_one_bit"
11469 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11470 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11471 (match_operand:QI 2 "const1_operand" "")))
11472 (clobber (reg:CC FLAGS_REG))]
11473 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11474 && (TARGET_SHIFT1 || optimize_size)"
11476 [(set_attr "type" "ishift")
11477 (set (attr "length")
11478 (if_then_else (match_operand:SI 0 "register_operand" "")
11480 (const_string "*")))])
11482 (define_insn "*lshrsi3_1_one_bit_zext"
11483 [(set (match_operand:DI 0 "register_operand" "=r")
11484 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11485 (match_operand:QI 2 "const1_operand" "")))
11486 (clobber (reg:CC FLAGS_REG))]
11487 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11488 && (TARGET_SHIFT1 || optimize_size)"
11490 [(set_attr "type" "ishift")
11491 (set_attr "length" "2")])
11493 (define_insn "*lshrsi3_1"
11494 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11495 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11496 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11497 (clobber (reg:CC FLAGS_REG))]
11498 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11500 shr{l}\t{%2, %0|%0, %2}
11501 shr{l}\t{%b2, %0|%0, %b2}"
11502 [(set_attr "type" "ishift")
11503 (set_attr "mode" "SI")])
11505 (define_insn "*lshrsi3_1_zext"
11506 [(set (match_operand:DI 0 "register_operand" "=r,r")
11508 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11509 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11510 (clobber (reg:CC FLAGS_REG))]
11511 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11513 shr{l}\t{%2, %k0|%k0, %2}
11514 shr{l}\t{%b2, %k0|%k0, %b2}"
11515 [(set_attr "type" "ishift")
11516 (set_attr "mode" "SI")])
11518 ;; This pattern can't accept a variable shift count, since shifts by
11519 ;; zero don't affect the flags. We assume that shifts by constant
11520 ;; zero are optimized away.
11521 (define_insn "*lshrsi3_one_bit_cmp"
11522 [(set (reg FLAGS_REG)
11524 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11525 (match_operand:QI 2 "const1_operand" ""))
11527 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11528 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11529 "ix86_match_ccmode (insn, CCGOCmode)
11530 && (TARGET_SHIFT1 || optimize_size)
11531 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11533 [(set_attr "type" "ishift")
11534 (set (attr "length")
11535 (if_then_else (match_operand:SI 0 "register_operand" "")
11537 (const_string "*")))])
11539 (define_insn "*lshrsi3_cmp_one_bit_zext"
11540 [(set (reg FLAGS_REG)
11542 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11543 (match_operand:QI 2 "const1_operand" ""))
11545 (set (match_operand:DI 0 "register_operand" "=r")
11546 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11547 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11548 && (TARGET_SHIFT1 || optimize_size)
11549 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11551 [(set_attr "type" "ishift")
11552 (set_attr "length" "2")])
11554 ;; This pattern can't accept a variable shift count, since shifts by
11555 ;; zero don't affect the flags. We assume that shifts by constant
11556 ;; zero are optimized away.
11557 (define_insn "*lshrsi3_cmp"
11558 [(set (reg FLAGS_REG)
11560 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11561 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11563 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11564 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11565 "ix86_match_ccmode (insn, CCGOCmode)
11566 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11567 "shr{l}\t{%2, %0|%0, %2}"
11568 [(set_attr "type" "ishift")
11569 (set_attr "mode" "SI")])
11571 (define_insn "*lshrsi3_cmp_zext"
11572 [(set (reg FLAGS_REG)
11574 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11575 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11577 (set (match_operand:DI 0 "register_operand" "=r")
11578 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11579 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11580 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11581 "shr{l}\t{%2, %k0|%k0, %2}"
11582 [(set_attr "type" "ishift")
11583 (set_attr "mode" "SI")])
11585 (define_expand "lshrhi3"
11586 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11587 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11588 (match_operand:QI 2 "nonmemory_operand" "")))
11589 (clobber (reg:CC FLAGS_REG))]
11590 "TARGET_HIMODE_MATH"
11591 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11593 (define_insn "*lshrhi3_1_one_bit"
11594 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11595 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11596 (match_operand:QI 2 "const1_operand" "")))
11597 (clobber (reg:CC FLAGS_REG))]
11598 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11599 && (TARGET_SHIFT1 || optimize_size)"
11601 [(set_attr "type" "ishift")
11602 (set (attr "length")
11603 (if_then_else (match_operand 0 "register_operand" "")
11605 (const_string "*")))])
11607 (define_insn "*lshrhi3_1"
11608 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11609 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11610 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11611 (clobber (reg:CC FLAGS_REG))]
11612 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11614 shr{w}\t{%2, %0|%0, %2}
11615 shr{w}\t{%b2, %0|%0, %b2}"
11616 [(set_attr "type" "ishift")
11617 (set_attr "mode" "HI")])
11619 ;; This pattern can't accept a variable shift count, since shifts by
11620 ;; zero don't affect the flags. We assume that shifts by constant
11621 ;; zero are optimized away.
11622 (define_insn "*lshrhi3_one_bit_cmp"
11623 [(set (reg FLAGS_REG)
11625 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11626 (match_operand:QI 2 "const1_operand" ""))
11628 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11629 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11630 "ix86_match_ccmode (insn, CCGOCmode)
11631 && (TARGET_SHIFT1 || optimize_size)
11632 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11634 [(set_attr "type" "ishift")
11635 (set (attr "length")
11636 (if_then_else (match_operand:SI 0 "register_operand" "")
11638 (const_string "*")))])
11640 ;; This pattern can't accept a variable shift count, since shifts by
11641 ;; zero don't affect the flags. We assume that shifts by constant
11642 ;; zero are optimized away.
11643 (define_insn "*lshrhi3_cmp"
11644 [(set (reg FLAGS_REG)
11646 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11647 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11649 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11650 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11651 "ix86_match_ccmode (insn, CCGOCmode)
11652 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11653 "shr{w}\t{%2, %0|%0, %2}"
11654 [(set_attr "type" "ishift")
11655 (set_attr "mode" "HI")])
11657 (define_expand "lshrqi3"
11658 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11659 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11660 (match_operand:QI 2 "nonmemory_operand" "")))
11661 (clobber (reg:CC FLAGS_REG))]
11662 "TARGET_QIMODE_MATH"
11663 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11665 (define_insn "*lshrqi3_1_one_bit"
11666 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11667 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11668 (match_operand:QI 2 "const1_operand" "")))
11669 (clobber (reg:CC FLAGS_REG))]
11670 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11671 && (TARGET_SHIFT1 || optimize_size)"
11673 [(set_attr "type" "ishift")
11674 (set (attr "length")
11675 (if_then_else (match_operand 0 "register_operand" "")
11677 (const_string "*")))])
11679 (define_insn "*lshrqi3_1_one_bit_slp"
11680 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11681 (lshiftrt:QI (match_dup 0)
11682 (match_operand:QI 1 "const1_operand" "")))
11683 (clobber (reg:CC FLAGS_REG))]
11684 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11685 && (TARGET_SHIFT1 || optimize_size)"
11687 [(set_attr "type" "ishift1")
11688 (set (attr "length")
11689 (if_then_else (match_operand 0 "register_operand" "")
11691 (const_string "*")))])
11693 (define_insn "*lshrqi3_1"
11694 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11695 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11696 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11697 (clobber (reg:CC FLAGS_REG))]
11698 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11700 shr{b}\t{%2, %0|%0, %2}
11701 shr{b}\t{%b2, %0|%0, %b2}"
11702 [(set_attr "type" "ishift")
11703 (set_attr "mode" "QI")])
11705 (define_insn "*lshrqi3_1_slp"
11706 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11707 (lshiftrt:QI (match_dup 0)
11708 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11709 (clobber (reg:CC FLAGS_REG))]
11710 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11711 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11713 shr{b}\t{%1, %0|%0, %1}
11714 shr{b}\t{%b1, %0|%0, %b1}"
11715 [(set_attr "type" "ishift1")
11716 (set_attr "mode" "QI")])
11718 ;; This pattern can't accept a variable shift count, since shifts by
11719 ;; zero don't affect the flags. We assume that shifts by constant
11720 ;; zero are optimized away.
11721 (define_insn "*lshrqi2_one_bit_cmp"
11722 [(set (reg FLAGS_REG)
11724 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11725 (match_operand:QI 2 "const1_operand" ""))
11727 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11728 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11729 "ix86_match_ccmode (insn, CCGOCmode)
11730 && (TARGET_SHIFT1 || optimize_size)
11731 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11733 [(set_attr "type" "ishift")
11734 (set (attr "length")
11735 (if_then_else (match_operand:SI 0 "register_operand" "")
11737 (const_string "*")))])
11739 ;; This pattern can't accept a variable shift count, since shifts by
11740 ;; zero don't affect the flags. We assume that shifts by constant
11741 ;; zero are optimized away.
11742 (define_insn "*lshrqi2_cmp"
11743 [(set (reg FLAGS_REG)
11745 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11746 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11748 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11749 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11750 "ix86_match_ccmode (insn, CCGOCmode)
11751 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11752 "shr{b}\t{%2, %0|%0, %2}"
11753 [(set_attr "type" "ishift")
11754 (set_attr "mode" "QI")])
11756 ;; Rotate instructions
11758 (define_expand "rotldi3"
11759 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11760 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
11761 (match_operand:QI 2 "nonmemory_operand" "")))
11762 (clobber (reg:CC FLAGS_REG))]
11764 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
11766 (define_insn "*rotlsi3_1_one_bit_rex64"
11767 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11768 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11769 (match_operand:QI 2 "const1_operand" "")))
11770 (clobber (reg:CC FLAGS_REG))]
11771 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
11772 && (TARGET_SHIFT1 || optimize_size)"
11774 [(set_attr "type" "rotate")
11775 (set (attr "length")
11776 (if_then_else (match_operand:DI 0 "register_operand" "")
11778 (const_string "*")))])
11780 (define_insn "*rotldi3_1_rex64"
11781 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11782 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11783 (match_operand:QI 2 "nonmemory_operand" "e,c")))
11784 (clobber (reg:CC FLAGS_REG))]
11785 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
11787 rol{q}\t{%2, %0|%0, %2}
11788 rol{q}\t{%b2, %0|%0, %b2}"
11789 [(set_attr "type" "rotate")
11790 (set_attr "mode" "DI")])
11792 (define_expand "rotlsi3"
11793 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11794 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
11795 (match_operand:QI 2 "nonmemory_operand" "")))
11796 (clobber (reg:CC FLAGS_REG))]
11798 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
11800 (define_insn "*rotlsi3_1_one_bit"
11801 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11802 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11803 (match_operand:QI 2 "const1_operand" "")))
11804 (clobber (reg:CC FLAGS_REG))]
11805 "ix86_binary_operator_ok (ROTATE, SImode, operands)
11806 && (TARGET_SHIFT1 || optimize_size)"
11808 [(set_attr "type" "rotate")
11809 (set (attr "length")
11810 (if_then_else (match_operand:SI 0 "register_operand" "")
11812 (const_string "*")))])
11814 (define_insn "*rotlsi3_1_one_bit_zext"
11815 [(set (match_operand:DI 0 "register_operand" "=r")
11817 (rotate:SI (match_operand:SI 1 "register_operand" "0")
11818 (match_operand:QI 2 "const1_operand" ""))))
11819 (clobber (reg:CC FLAGS_REG))]
11820 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
11821 && (TARGET_SHIFT1 || optimize_size)"
11823 [(set_attr "type" "rotate")
11824 (set_attr "length" "2")])
11826 (define_insn "*rotlsi3_1"
11827 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11828 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11829 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11830 (clobber (reg:CC FLAGS_REG))]
11831 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
11833 rol{l}\t{%2, %0|%0, %2}
11834 rol{l}\t{%b2, %0|%0, %b2}"
11835 [(set_attr "type" "rotate")
11836 (set_attr "mode" "SI")])
11838 (define_insn "*rotlsi3_1_zext"
11839 [(set (match_operand:DI 0 "register_operand" "=r,r")
11841 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
11842 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11843 (clobber (reg:CC FLAGS_REG))]
11844 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
11846 rol{l}\t{%2, %k0|%k0, %2}
11847 rol{l}\t{%b2, %k0|%k0, %b2}"
11848 [(set_attr "type" "rotate")
11849 (set_attr "mode" "SI")])
11851 (define_expand "rotlhi3"
11852 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11853 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
11854 (match_operand:QI 2 "nonmemory_operand" "")))
11855 (clobber (reg:CC FLAGS_REG))]
11856 "TARGET_HIMODE_MATH"
11857 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
11859 (define_insn "*rotlhi3_1_one_bit"
11860 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11861 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11862 (match_operand:QI 2 "const1_operand" "")))
11863 (clobber (reg:CC FLAGS_REG))]
11864 "ix86_binary_operator_ok (ROTATE, HImode, operands)
11865 && (TARGET_SHIFT1 || optimize_size)"
11867 [(set_attr "type" "rotate")
11868 (set (attr "length")
11869 (if_then_else (match_operand 0 "register_operand" "")
11871 (const_string "*")))])
11873 (define_insn "*rotlhi3_1"
11874 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11875 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11876 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11877 (clobber (reg:CC FLAGS_REG))]
11878 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
11880 rol{w}\t{%2, %0|%0, %2}
11881 rol{w}\t{%b2, %0|%0, %b2}"
11882 [(set_attr "type" "rotate")
11883 (set_attr "mode" "HI")])
11885 (define_expand "rotlqi3"
11886 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11887 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
11888 (match_operand:QI 2 "nonmemory_operand" "")))
11889 (clobber (reg:CC FLAGS_REG))]
11890 "TARGET_QIMODE_MATH"
11891 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
11893 (define_insn "*rotlqi3_1_one_bit_slp"
11894 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11895 (rotate:QI (match_dup 0)
11896 (match_operand:QI 1 "const1_operand" "")))
11897 (clobber (reg:CC FLAGS_REG))]
11898 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11899 && (TARGET_SHIFT1 || optimize_size)"
11901 [(set_attr "type" "rotate1")
11902 (set (attr "length")
11903 (if_then_else (match_operand 0 "register_operand" "")
11905 (const_string "*")))])
11907 (define_insn "*rotlqi3_1_one_bit"
11908 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11909 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11910 (match_operand:QI 2 "const1_operand" "")))
11911 (clobber (reg:CC FLAGS_REG))]
11912 "ix86_binary_operator_ok (ROTATE, QImode, operands)
11913 && (TARGET_SHIFT1 || optimize_size)"
11915 [(set_attr "type" "rotate")
11916 (set (attr "length")
11917 (if_then_else (match_operand 0 "register_operand" "")
11919 (const_string "*")))])
11921 (define_insn "*rotlqi3_1_slp"
11922 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11923 (rotate:QI (match_dup 0)
11924 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11925 (clobber (reg:CC FLAGS_REG))]
11926 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11927 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11929 rol{b}\t{%1, %0|%0, %1}
11930 rol{b}\t{%b1, %0|%0, %b1}"
11931 [(set_attr "type" "rotate1")
11932 (set_attr "mode" "QI")])
11934 (define_insn "*rotlqi3_1"
11935 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11936 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11937 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11938 (clobber (reg:CC FLAGS_REG))]
11939 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
11941 rol{b}\t{%2, %0|%0, %2}
11942 rol{b}\t{%b2, %0|%0, %b2}"
11943 [(set_attr "type" "rotate")
11944 (set_attr "mode" "QI")])
11946 (define_expand "rotrdi3"
11947 [(set (match_operand:DI 0 "nonimmediate_operand" "")
11948 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
11949 (match_operand:QI 2 "nonmemory_operand" "")))
11950 (clobber (reg:CC FLAGS_REG))]
11952 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
11954 (define_insn "*rotrdi3_1_one_bit_rex64"
11955 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11956 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11957 (match_operand:QI 2 "const1_operand" "")))
11958 (clobber (reg:CC FLAGS_REG))]
11959 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
11960 && (TARGET_SHIFT1 || optimize_size)"
11962 [(set_attr "type" "rotate")
11963 (set (attr "length")
11964 (if_then_else (match_operand:DI 0 "register_operand" "")
11966 (const_string "*")))])
11968 (define_insn "*rotrdi3_1_rex64"
11969 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11970 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11971 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11972 (clobber (reg:CC FLAGS_REG))]
11973 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
11975 ror{q}\t{%2, %0|%0, %2}
11976 ror{q}\t{%b2, %0|%0, %b2}"
11977 [(set_attr "type" "rotate")
11978 (set_attr "mode" "DI")])
11980 (define_expand "rotrsi3"
11981 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11982 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
11983 (match_operand:QI 2 "nonmemory_operand" "")))
11984 (clobber (reg:CC FLAGS_REG))]
11986 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
11988 (define_insn "*rotrsi3_1_one_bit"
11989 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11990 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11991 (match_operand:QI 2 "const1_operand" "")))
11992 (clobber (reg:CC FLAGS_REG))]
11993 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
11994 && (TARGET_SHIFT1 || optimize_size)"
11996 [(set_attr "type" "rotate")
11997 (set (attr "length")
11998 (if_then_else (match_operand:SI 0 "register_operand" "")
12000 (const_string "*")))])
12002 (define_insn "*rotrsi3_1_one_bit_zext"
12003 [(set (match_operand:DI 0 "register_operand" "=r")
12005 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12006 (match_operand:QI 2 "const1_operand" ""))))
12007 (clobber (reg:CC FLAGS_REG))]
12008 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12009 && (TARGET_SHIFT1 || optimize_size)"
12011 [(set_attr "type" "rotate")
12012 (set (attr "length")
12013 (if_then_else (match_operand:SI 0 "register_operand" "")
12015 (const_string "*")))])
12017 (define_insn "*rotrsi3_1"
12018 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12019 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12020 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12021 (clobber (reg:CC FLAGS_REG))]
12022 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12024 ror{l}\t{%2, %0|%0, %2}
12025 ror{l}\t{%b2, %0|%0, %b2}"
12026 [(set_attr "type" "rotate")
12027 (set_attr "mode" "SI")])
12029 (define_insn "*rotrsi3_1_zext"
12030 [(set (match_operand:DI 0 "register_operand" "=r,r")
12032 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12033 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12034 (clobber (reg:CC FLAGS_REG))]
12035 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12037 ror{l}\t{%2, %k0|%k0, %2}
12038 ror{l}\t{%b2, %k0|%k0, %b2}"
12039 [(set_attr "type" "rotate")
12040 (set_attr "mode" "SI")])
12042 (define_expand "rotrhi3"
12043 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12044 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12045 (match_operand:QI 2 "nonmemory_operand" "")))
12046 (clobber (reg:CC FLAGS_REG))]
12047 "TARGET_HIMODE_MATH"
12048 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12050 (define_insn "*rotrhi3_one_bit"
12051 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12052 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12053 (match_operand:QI 2 "const1_operand" "")))
12054 (clobber (reg:CC FLAGS_REG))]
12055 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12056 && (TARGET_SHIFT1 || optimize_size)"
12058 [(set_attr "type" "rotate")
12059 (set (attr "length")
12060 (if_then_else (match_operand 0 "register_operand" "")
12062 (const_string "*")))])
12064 (define_insn "*rotrhi3"
12065 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12066 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12067 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12068 (clobber (reg:CC FLAGS_REG))]
12069 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12071 ror{w}\t{%2, %0|%0, %2}
12072 ror{w}\t{%b2, %0|%0, %b2}"
12073 [(set_attr "type" "rotate")
12074 (set_attr "mode" "HI")])
12076 (define_expand "rotrqi3"
12077 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12078 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12079 (match_operand:QI 2 "nonmemory_operand" "")))
12080 (clobber (reg:CC FLAGS_REG))]
12081 "TARGET_QIMODE_MATH"
12082 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12084 (define_insn "*rotrqi3_1_one_bit"
12085 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12086 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12087 (match_operand:QI 2 "const1_operand" "")))
12088 (clobber (reg:CC FLAGS_REG))]
12089 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12090 && (TARGET_SHIFT1 || optimize_size)"
12092 [(set_attr "type" "rotate")
12093 (set (attr "length")
12094 (if_then_else (match_operand 0 "register_operand" "")
12096 (const_string "*")))])
12098 (define_insn "*rotrqi3_1_one_bit_slp"
12099 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12100 (rotatert:QI (match_dup 0)
12101 (match_operand:QI 1 "const1_operand" "")))
12102 (clobber (reg:CC FLAGS_REG))]
12103 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12104 && (TARGET_SHIFT1 || optimize_size)"
12106 [(set_attr "type" "rotate1")
12107 (set (attr "length")
12108 (if_then_else (match_operand 0 "register_operand" "")
12110 (const_string "*")))])
12112 (define_insn "*rotrqi3_1"
12113 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12114 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12115 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12116 (clobber (reg:CC FLAGS_REG))]
12117 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12119 ror{b}\t{%2, %0|%0, %2}
12120 ror{b}\t{%b2, %0|%0, %b2}"
12121 [(set_attr "type" "rotate")
12122 (set_attr "mode" "QI")])
12124 (define_insn "*rotrqi3_1_slp"
12125 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12126 (rotatert:QI (match_dup 0)
12127 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12128 (clobber (reg:CC FLAGS_REG))]
12129 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12130 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12132 ror{b}\t{%1, %0|%0, %1}
12133 ror{b}\t{%b1, %0|%0, %b1}"
12134 [(set_attr "type" "rotate1")
12135 (set_attr "mode" "QI")])
12137 ;; Bit set / bit test instructions
12139 (define_expand "extv"
12140 [(set (match_operand:SI 0 "register_operand" "")
12141 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12142 (match_operand:SI 2 "immediate_operand" "")
12143 (match_operand:SI 3 "immediate_operand" "")))]
12146 /* Handle extractions from %ah et al. */
12147 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12150 /* From mips.md: extract_bit_field doesn't verify that our source
12151 matches the predicate, so check it again here. */
12152 if (! ext_register_operand (operands[1], VOIDmode))
12156 (define_expand "extzv"
12157 [(set (match_operand:SI 0 "register_operand" "")
12158 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12159 (match_operand:SI 2 "immediate_operand" "")
12160 (match_operand:SI 3 "immediate_operand" "")))]
12163 /* Handle extractions from %ah et al. */
12164 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12167 /* From mips.md: extract_bit_field doesn't verify that our source
12168 matches the predicate, so check it again here. */
12169 if (! ext_register_operand (operands[1], VOIDmode))
12173 (define_expand "insv"
12174 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12175 (match_operand 1 "immediate_operand" "")
12176 (match_operand 2 "immediate_operand" ""))
12177 (match_operand 3 "register_operand" ""))]
12180 /* Handle extractions from %ah et al. */
12181 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12184 /* From mips.md: insert_bit_field doesn't verify that our source
12185 matches the predicate, so check it again here. */
12186 if (! ext_register_operand (operands[0], VOIDmode))
12190 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12192 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12197 ;; %%% bts, btr, btc, bt.
12198 ;; In general these instructions are *slow* when applied to memory,
12199 ;; since they enforce atomic operation. When applied to registers,
12200 ;; it depends on the cpu implementation. They're never faster than
12201 ;; the corresponding and/ior/xor operations, so with 32-bit there's
12202 ;; no point. But in 64-bit, we can't hold the relevant immediates
12203 ;; within the instruction itself, so operating on bits in the high
12204 ;; 32-bits of a register becomes easier.
12206 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
12207 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
12208 ;; negdf respectively, so they can never be disabled entirely.
12210 (define_insn "*btsq"
12211 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12213 (match_operand:DI 1 "const_0_to_63_operand" ""))
12215 (clobber (reg:CC FLAGS_REG))]
12216 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12218 [(set_attr "type" "alu1")])
12220 (define_insn "*btrq"
12221 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12223 (match_operand:DI 1 "const_0_to_63_operand" ""))
12225 (clobber (reg:CC FLAGS_REG))]
12226 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12228 [(set_attr "type" "alu1")])
12230 (define_insn "*btcq"
12231 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12233 (match_operand:DI 1 "const_0_to_63_operand" ""))
12234 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
12235 (clobber (reg:CC FLAGS_REG))]
12236 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12238 [(set_attr "type" "alu1")])
12240 ;; Allow Nocona to avoid these instructions if a register is available.
12243 [(match_scratch:DI 2 "r")
12244 (parallel [(set (zero_extract:DI
12245 (match_operand:DI 0 "register_operand" "")
12247 (match_operand:DI 1 "const_0_to_63_operand" ""))
12249 (clobber (reg:CC FLAGS_REG))])]
12250 "TARGET_64BIT && !TARGET_USE_BT"
12253 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12256 if (HOST_BITS_PER_WIDE_INT >= 64)
12257 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12258 else if (i < HOST_BITS_PER_WIDE_INT)
12259 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12261 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12263 op1 = immed_double_const (lo, hi, DImode);
12266 emit_move_insn (operands[2], op1);
12270 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
12275 [(match_scratch:DI 2 "r")
12276 (parallel [(set (zero_extract:DI
12277 (match_operand:DI 0 "register_operand" "")
12279 (match_operand:DI 1 "const_0_to_63_operand" ""))
12281 (clobber (reg:CC FLAGS_REG))])]
12282 "TARGET_64BIT && !TARGET_USE_BT"
12285 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12288 if (HOST_BITS_PER_WIDE_INT >= 64)
12289 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12290 else if (i < HOST_BITS_PER_WIDE_INT)
12291 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12293 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12295 op1 = immed_double_const (~lo, ~hi, DImode);
12298 emit_move_insn (operands[2], op1);
12302 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
12307 [(match_scratch:DI 2 "r")
12308 (parallel [(set (zero_extract:DI
12309 (match_operand:DI 0 "register_operand" "")
12311 (match_operand:DI 1 "const_0_to_63_operand" ""))
12312 (not:DI (zero_extract:DI
12313 (match_dup 0) (const_int 1) (match_dup 1))))
12314 (clobber (reg:CC FLAGS_REG))])]
12315 "TARGET_64BIT && !TARGET_USE_BT"
12318 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12321 if (HOST_BITS_PER_WIDE_INT >= 64)
12322 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12323 else if (i < HOST_BITS_PER_WIDE_INT)
12324 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12326 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12328 op1 = immed_double_const (lo, hi, DImode);
12331 emit_move_insn (operands[2], op1);
12335 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
12339 ;; Store-flag instructions.
12341 ;; For all sCOND expanders, also expand the compare or test insn that
12342 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12344 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12345 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12346 ;; way, which can later delete the movzx if only QImode is needed.
12348 (define_expand "seq"
12349 [(set (match_operand:QI 0 "register_operand" "")
12350 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12352 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12354 (define_expand "sne"
12355 [(set (match_operand:QI 0 "register_operand" "")
12356 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12358 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12360 (define_expand "sgt"
12361 [(set (match_operand:QI 0 "register_operand" "")
12362 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12364 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12366 (define_expand "sgtu"
12367 [(set (match_operand:QI 0 "register_operand" "")
12368 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12370 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12372 (define_expand "slt"
12373 [(set (match_operand:QI 0 "register_operand" "")
12374 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12376 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12378 (define_expand "sltu"
12379 [(set (match_operand:QI 0 "register_operand" "")
12380 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12382 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12384 (define_expand "sge"
12385 [(set (match_operand:QI 0 "register_operand" "")
12386 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12388 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12390 (define_expand "sgeu"
12391 [(set (match_operand:QI 0 "register_operand" "")
12392 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12394 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12396 (define_expand "sle"
12397 [(set (match_operand:QI 0 "register_operand" "")
12398 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12400 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12402 (define_expand "sleu"
12403 [(set (match_operand:QI 0 "register_operand" "")
12404 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12406 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12408 (define_expand "sunordered"
12409 [(set (match_operand:QI 0 "register_operand" "")
12410 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12411 "TARGET_80387 || TARGET_SSE"
12412 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12414 (define_expand "sordered"
12415 [(set (match_operand:QI 0 "register_operand" "")
12416 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12418 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12420 (define_expand "suneq"
12421 [(set (match_operand:QI 0 "register_operand" "")
12422 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12423 "TARGET_80387 || TARGET_SSE"
12424 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12426 (define_expand "sunge"
12427 [(set (match_operand:QI 0 "register_operand" "")
12428 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12429 "TARGET_80387 || TARGET_SSE"
12430 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12432 (define_expand "sungt"
12433 [(set (match_operand:QI 0 "register_operand" "")
12434 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12435 "TARGET_80387 || TARGET_SSE"
12436 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12438 (define_expand "sunle"
12439 [(set (match_operand:QI 0 "register_operand" "")
12440 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12441 "TARGET_80387 || TARGET_SSE"
12442 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12444 (define_expand "sunlt"
12445 [(set (match_operand:QI 0 "register_operand" "")
12446 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12447 "TARGET_80387 || TARGET_SSE"
12448 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12450 (define_expand "sltgt"
12451 [(set (match_operand:QI 0 "register_operand" "")
12452 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12453 "TARGET_80387 || TARGET_SSE"
12454 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12456 (define_insn "*setcc_1"
12457 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12458 (match_operator:QI 1 "ix86_comparison_operator"
12459 [(reg FLAGS_REG) (const_int 0)]))]
12462 [(set_attr "type" "setcc")
12463 (set_attr "mode" "QI")])
12465 (define_insn "*setcc_2"
12466 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12467 (match_operator:QI 1 "ix86_comparison_operator"
12468 [(reg FLAGS_REG) (const_int 0)]))]
12471 [(set_attr "type" "setcc")
12472 (set_attr "mode" "QI")])
12474 ;; In general it is not safe to assume too much about CCmode registers,
12475 ;; so simplify-rtx stops when it sees a second one. Under certain
12476 ;; conditions this is safe on x86, so help combine not create
12483 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12484 (ne:QI (match_operator 1 "ix86_comparison_operator"
12485 [(reg FLAGS_REG) (const_int 0)])
12488 [(set (match_dup 0) (match_dup 1))]
12490 PUT_MODE (operands[1], QImode);
12494 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12495 (ne:QI (match_operator 1 "ix86_comparison_operator"
12496 [(reg FLAGS_REG) (const_int 0)])
12499 [(set (match_dup 0) (match_dup 1))]
12501 PUT_MODE (operands[1], QImode);
12505 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12506 (eq:QI (match_operator 1 "ix86_comparison_operator"
12507 [(reg FLAGS_REG) (const_int 0)])
12510 [(set (match_dup 0) (match_dup 1))]
12512 rtx new_op1 = copy_rtx (operands[1]);
12513 operands[1] = new_op1;
12514 PUT_MODE (new_op1, QImode);
12515 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12516 GET_MODE (XEXP (new_op1, 0))));
12518 /* Make sure that (a) the CCmode we have for the flags is strong
12519 enough for the reversed compare or (b) we have a valid FP compare. */
12520 if (! ix86_comparison_operator (new_op1, VOIDmode))
12525 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12526 (eq:QI (match_operator 1 "ix86_comparison_operator"
12527 [(reg FLAGS_REG) (const_int 0)])
12530 [(set (match_dup 0) (match_dup 1))]
12532 rtx new_op1 = copy_rtx (operands[1]);
12533 operands[1] = new_op1;
12534 PUT_MODE (new_op1, QImode);
12535 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12536 GET_MODE (XEXP (new_op1, 0))));
12538 /* Make sure that (a) the CCmode we have for the flags is strong
12539 enough for the reversed compare or (b) we have a valid FP compare. */
12540 if (! ix86_comparison_operator (new_op1, VOIDmode))
12544 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12545 ;; subsequent logical operations are used to imitate conditional moves.
12546 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12547 ;; it directly. Further holding this value in pseudo register might bring
12548 ;; problem in implicit normalization in spill code.
12549 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
12550 ;; instructions after reload by splitting the conditional move patterns.
12552 (define_insn "*sse_setccsf"
12553 [(set (match_operand:SF 0 "register_operand" "=x")
12554 (match_operator:SF 1 "sse_comparison_operator"
12555 [(match_operand:SF 2 "register_operand" "0")
12556 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12557 "TARGET_SSE && reload_completed"
12558 "cmp%D1ss\t{%3, %0|%0, %3}"
12559 [(set_attr "type" "ssecmp")
12560 (set_attr "mode" "SF")])
12562 (define_insn "*sse_setccdf"
12563 [(set (match_operand:DF 0 "register_operand" "=Y")
12564 (match_operator:DF 1 "sse_comparison_operator"
12565 [(match_operand:DF 2 "register_operand" "0")
12566 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12567 "TARGET_SSE2 && reload_completed"
12568 "cmp%D1sd\t{%3, %0|%0, %3}"
12569 [(set_attr "type" "ssecmp")
12570 (set_attr "mode" "DF")])
12572 ;; Basic conditional jump instructions.
12573 ;; We ignore the overflow flag for signed branch instructions.
12575 ;; For all bCOND expanders, also expand the compare or test insn that
12576 ;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
12578 (define_expand "beq"
12580 (if_then_else (match_dup 1)
12581 (label_ref (match_operand 0 "" ""))
12584 "ix86_expand_branch (EQ, operands[0]); DONE;")
12586 (define_expand "bne"
12588 (if_then_else (match_dup 1)
12589 (label_ref (match_operand 0 "" ""))
12592 "ix86_expand_branch (NE, operands[0]); DONE;")
12594 (define_expand "bgt"
12596 (if_then_else (match_dup 1)
12597 (label_ref (match_operand 0 "" ""))
12600 "ix86_expand_branch (GT, operands[0]); DONE;")
12602 (define_expand "bgtu"
12604 (if_then_else (match_dup 1)
12605 (label_ref (match_operand 0 "" ""))
12608 "ix86_expand_branch (GTU, operands[0]); DONE;")
12610 (define_expand "blt"
12612 (if_then_else (match_dup 1)
12613 (label_ref (match_operand 0 "" ""))
12616 "ix86_expand_branch (LT, operands[0]); DONE;")
12618 (define_expand "bltu"
12620 (if_then_else (match_dup 1)
12621 (label_ref (match_operand 0 "" ""))
12624 "ix86_expand_branch (LTU, operands[0]); DONE;")
12626 (define_expand "bge"
12628 (if_then_else (match_dup 1)
12629 (label_ref (match_operand 0 "" ""))
12632 "ix86_expand_branch (GE, operands[0]); DONE;")
12634 (define_expand "bgeu"
12636 (if_then_else (match_dup 1)
12637 (label_ref (match_operand 0 "" ""))
12640 "ix86_expand_branch (GEU, operands[0]); DONE;")
12642 (define_expand "ble"
12644 (if_then_else (match_dup 1)
12645 (label_ref (match_operand 0 "" ""))
12648 "ix86_expand_branch (LE, operands[0]); DONE;")
12650 (define_expand "bleu"
12652 (if_then_else (match_dup 1)
12653 (label_ref (match_operand 0 "" ""))
12656 "ix86_expand_branch (LEU, operands[0]); DONE;")
12658 (define_expand "bunordered"
12660 (if_then_else (match_dup 1)
12661 (label_ref (match_operand 0 "" ""))
12663 "TARGET_80387 || TARGET_SSE"
12664 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12666 (define_expand "bordered"
12668 (if_then_else (match_dup 1)
12669 (label_ref (match_operand 0 "" ""))
12671 "TARGET_80387 || TARGET_SSE"
12672 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
12674 (define_expand "buneq"
12676 (if_then_else (match_dup 1)
12677 (label_ref (match_operand 0 "" ""))
12679 "TARGET_80387 || TARGET_SSE"
12680 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
12682 (define_expand "bunge"
12684 (if_then_else (match_dup 1)
12685 (label_ref (match_operand 0 "" ""))
12687 "TARGET_80387 || TARGET_SSE"
12688 "ix86_expand_branch (UNGE, operands[0]); DONE;")
12690 (define_expand "bungt"
12692 (if_then_else (match_dup 1)
12693 (label_ref (match_operand 0 "" ""))
12695 "TARGET_80387 || TARGET_SSE"
12696 "ix86_expand_branch (UNGT, operands[0]); DONE;")
12698 (define_expand "bunle"
12700 (if_then_else (match_dup 1)
12701 (label_ref (match_operand 0 "" ""))
12703 "TARGET_80387 || TARGET_SSE"
12704 "ix86_expand_branch (UNLE, operands[0]); DONE;")
12706 (define_expand "bunlt"
12708 (if_then_else (match_dup 1)
12709 (label_ref (match_operand 0 "" ""))
12711 "TARGET_80387 || TARGET_SSE"
12712 "ix86_expand_branch (UNLT, operands[0]); DONE;")
12714 (define_expand "bltgt"
12716 (if_then_else (match_dup 1)
12717 (label_ref (match_operand 0 "" ""))
12719 "TARGET_80387 || TARGET_SSE"
12720 "ix86_expand_branch (LTGT, operands[0]); DONE;")
12722 (define_insn "*jcc_1"
12724 (if_then_else (match_operator 1 "ix86_comparison_operator"
12725 [(reg FLAGS_REG) (const_int 0)])
12726 (label_ref (match_operand 0 "" ""))
12730 [(set_attr "type" "ibr")
12731 (set_attr "modrm" "0")
12732 (set (attr "length")
12733 (if_then_else (and (ge (minus (match_dup 0) (pc))
12735 (lt (minus (match_dup 0) (pc))
12740 (define_insn "*jcc_2"
12742 (if_then_else (match_operator 1 "ix86_comparison_operator"
12743 [(reg FLAGS_REG) (const_int 0)])
12745 (label_ref (match_operand 0 "" ""))))]
12748 [(set_attr "type" "ibr")
12749 (set_attr "modrm" "0")
12750 (set (attr "length")
12751 (if_then_else (and (ge (minus (match_dup 0) (pc))
12753 (lt (minus (match_dup 0) (pc))
12758 ;; In general it is not safe to assume too much about CCmode registers,
12759 ;; so simplify-rtx stops when it sees a second one. Under certain
12760 ;; conditions this is safe on x86, so help combine not create
12768 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
12769 [(reg FLAGS_REG) (const_int 0)])
12771 (label_ref (match_operand 1 "" ""))
12775 (if_then_else (match_dup 0)
12776 (label_ref (match_dup 1))
12779 PUT_MODE (operands[0], VOIDmode);
12784 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
12785 [(reg FLAGS_REG) (const_int 0)])
12787 (label_ref (match_operand 1 "" ""))
12791 (if_then_else (match_dup 0)
12792 (label_ref (match_dup 1))
12795 rtx new_op0 = copy_rtx (operands[0]);
12796 operands[0] = new_op0;
12797 PUT_MODE (new_op0, VOIDmode);
12798 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
12799 GET_MODE (XEXP (new_op0, 0))));
12801 /* Make sure that (a) the CCmode we have for the flags is strong
12802 enough for the reversed compare or (b) we have a valid FP compare. */
12803 if (! ix86_comparison_operator (new_op0, VOIDmode))
12807 ;; Define combination compare-and-branch fp compare instructions to use
12808 ;; during early optimization. Splitting the operation apart early makes
12809 ;; for bad code when we want to reverse the operation.
12811 (define_insn "*fp_jcc_1"
12813 (if_then_else (match_operator 0 "comparison_operator"
12814 [(match_operand 1 "register_operand" "f")
12815 (match_operand 2 "register_operand" "f")])
12816 (label_ref (match_operand 3 "" ""))
12818 (clobber (reg:CCFP FPSR_REG))
12819 (clobber (reg:CCFP FLAGS_REG))]
12820 "TARGET_CMOVE && TARGET_80387
12821 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12822 && FLOAT_MODE_P (GET_MODE (operands[1]))
12823 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12824 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12827 (define_insn "*fp_jcc_1_sse"
12829 (if_then_else (match_operator 0 "comparison_operator"
12830 [(match_operand 1 "register_operand" "f#x,x#f")
12831 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12832 (label_ref (match_operand 3 "" ""))
12834 (clobber (reg:CCFP FPSR_REG))
12835 (clobber (reg:CCFP FLAGS_REG))]
12837 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12838 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12839 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12842 (define_insn "*fp_jcc_1_sse_only"
12844 (if_then_else (match_operator 0 "comparison_operator"
12845 [(match_operand 1 "register_operand" "x")
12846 (match_operand 2 "nonimmediate_operand" "xm")])
12847 (label_ref (match_operand 3 "" ""))
12849 (clobber (reg:CCFP FPSR_REG))
12850 (clobber (reg:CCFP FLAGS_REG))]
12851 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12852 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12853 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12856 (define_insn "*fp_jcc_2"
12858 (if_then_else (match_operator 0 "comparison_operator"
12859 [(match_operand 1 "register_operand" "f")
12860 (match_operand 2 "register_operand" "f")])
12862 (label_ref (match_operand 3 "" ""))))
12863 (clobber (reg:CCFP FPSR_REG))
12864 (clobber (reg:CCFP FLAGS_REG))]
12865 "TARGET_CMOVE && TARGET_80387
12866 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12867 && FLOAT_MODE_P (GET_MODE (operands[1]))
12868 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12869 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12872 (define_insn "*fp_jcc_2_sse"
12874 (if_then_else (match_operator 0 "comparison_operator"
12875 [(match_operand 1 "register_operand" "f#x,x#f")
12876 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
12878 (label_ref (match_operand 3 "" ""))))
12879 (clobber (reg:CCFP FPSR_REG))
12880 (clobber (reg:CCFP FLAGS_REG))]
12882 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12883 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12884 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12887 (define_insn "*fp_jcc_2_sse_only"
12889 (if_then_else (match_operator 0 "comparison_operator"
12890 [(match_operand 1 "register_operand" "x")
12891 (match_operand 2 "nonimmediate_operand" "xm")])
12893 (label_ref (match_operand 3 "" ""))))
12894 (clobber (reg:CCFP FPSR_REG))
12895 (clobber (reg:CCFP FLAGS_REG))]
12896 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
12897 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12898 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12901 (define_insn "*fp_jcc_3"
12903 (if_then_else (match_operator 0 "comparison_operator"
12904 [(match_operand 1 "register_operand" "f")
12905 (match_operand 2 "nonimmediate_operand" "fm")])
12906 (label_ref (match_operand 3 "" ""))
12908 (clobber (reg:CCFP FPSR_REG))
12909 (clobber (reg:CCFP FLAGS_REG))
12910 (clobber (match_scratch:HI 4 "=a"))]
12912 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12913 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12914 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12915 && SELECT_CC_MODE (GET_CODE (operands[0]),
12916 operands[1], operands[2]) == CCFPmode
12917 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12920 (define_insn "*fp_jcc_4"
12922 (if_then_else (match_operator 0 "comparison_operator"
12923 [(match_operand 1 "register_operand" "f")
12924 (match_operand 2 "nonimmediate_operand" "fm")])
12926 (label_ref (match_operand 3 "" ""))))
12927 (clobber (reg:CCFP FPSR_REG))
12928 (clobber (reg:CCFP FLAGS_REG))
12929 (clobber (match_scratch:HI 4 "=a"))]
12931 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
12932 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12933 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12934 && SELECT_CC_MODE (GET_CODE (operands[0]),
12935 operands[1], operands[2]) == CCFPmode
12936 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12939 (define_insn "*fp_jcc_5"
12941 (if_then_else (match_operator 0 "comparison_operator"
12942 [(match_operand 1 "register_operand" "f")
12943 (match_operand 2 "register_operand" "f")])
12944 (label_ref (match_operand 3 "" ""))
12946 (clobber (reg:CCFP FPSR_REG))
12947 (clobber (reg:CCFP FLAGS_REG))
12948 (clobber (match_scratch:HI 4 "=a"))]
12950 && FLOAT_MODE_P (GET_MODE (operands[1]))
12951 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12952 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12955 (define_insn "*fp_jcc_6"
12957 (if_then_else (match_operator 0 "comparison_operator"
12958 [(match_operand 1 "register_operand" "f")
12959 (match_operand 2 "register_operand" "f")])
12961 (label_ref (match_operand 3 "" ""))))
12962 (clobber (reg:CCFP FPSR_REG))
12963 (clobber (reg:CCFP FLAGS_REG))
12964 (clobber (match_scratch:HI 4 "=a"))]
12966 && FLOAT_MODE_P (GET_MODE (operands[1]))
12967 && GET_MODE (operands[1]) == GET_MODE (operands[2])
12968 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12971 (define_insn "*fp_jcc_7"
12973 (if_then_else (match_operator 0 "comparison_operator"
12974 [(match_operand 1 "register_operand" "f")
12975 (match_operand 2 "const_double_operand" "C")])
12976 (label_ref (match_operand 3 "" ""))
12978 (clobber (reg:CCFP FPSR_REG))
12979 (clobber (reg:CCFP FLAGS_REG))
12980 (clobber (match_scratch:HI 4 "=a"))]
12982 && FLOAT_MODE_P (GET_MODE (operands[1]))
12983 && operands[2] == CONST0_RTX (GET_MODE (operands[1]))
12984 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
12985 && SELECT_CC_MODE (GET_CODE (operands[0]),
12986 operands[1], operands[2]) == CCFPmode
12987 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
12990 ;; The order of operands in *fp_jcc_8 is forced by combine in
12991 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
12992 ;; with a precedence over other operators and is always put in the first
12993 ;; place. Swap condition and operands to match ficom instruction.
12995 (define_insn "*fp_jcc_8"
12997 (if_then_else (match_operator 0 "comparison_operator"
12998 [(match_operator 1 "float_operator"
12999 [(match_operand:SI 2 "nonimmediate_operand" "m,?r")])
13000 (match_operand 3 "register_operand" "f,f")])
13001 (label_ref (match_operand 4 "" ""))
13003 (clobber (reg:CCFP FPSR_REG))
13004 (clobber (reg:CCFP FLAGS_REG))
13005 (clobber (match_scratch:HI 5 "=a,a"))]
13006 "TARGET_80387 && TARGET_USE_FIOP
13007 && FLOAT_MODE_P (GET_MODE (operands[3]))
13008 && GET_MODE (operands[1]) == GET_MODE (operands[3])
13009 && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
13010 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
13011 && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
13016 (if_then_else (match_operator 0 "comparison_operator"
13017 [(match_operand 1 "register_operand" "")
13018 (match_operand 2 "nonimmediate_operand" "")])
13019 (match_operand 3 "" "")
13020 (match_operand 4 "" "")))
13021 (clobber (reg:CCFP FPSR_REG))
13022 (clobber (reg:CCFP FLAGS_REG))]
13026 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13027 operands[3], operands[4], NULL_RTX, NULL_RTX);
13033 (if_then_else (match_operator 0 "comparison_operator"
13034 [(match_operand 1 "register_operand" "")
13035 (match_operand 2 "general_operand" "")])
13036 (match_operand 3 "" "")
13037 (match_operand 4 "" "")))
13038 (clobber (reg:CCFP FPSR_REG))
13039 (clobber (reg:CCFP FLAGS_REG))
13040 (clobber (match_scratch:HI 5 "=a"))]
13044 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13045 operands[3], operands[4], operands[5], NULL_RTX);
13051 (if_then_else (match_operator 0 "comparison_operator"
13052 [(match_operator 1 "float_operator"
13053 [(match_operand:SI 2 "memory_operand" "")])
13054 (match_operand 3 "register_operand" "")])
13055 (match_operand 4 "" "")
13056 (match_operand 5 "" "")))
13057 (clobber (reg:CCFP FPSR_REG))
13058 (clobber (reg:CCFP FLAGS_REG))
13059 (clobber (match_scratch:HI 6 "=a"))]
13063 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
13064 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13065 operands[3], operands[7],
13066 operands[4], operands[5], operands[6], NULL_RTX);
13070 ;; %%% Kill this when reload knows how to do it.
13073 (if_then_else (match_operator 0 "comparison_operator"
13074 [(match_operator 1 "float_operator"
13075 [(match_operand:SI 2 "register_operand" "")])
13076 (match_operand 3 "register_operand" "")])
13077 (match_operand 4 "" "")
13078 (match_operand 5 "" "")))
13079 (clobber (reg:CCFP FPSR_REG))
13080 (clobber (reg:CCFP FLAGS_REG))
13081 (clobber (match_scratch:HI 6 "=a"))]
13085 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13086 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
13087 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13088 operands[3], operands[7],
13089 operands[4], operands[5], operands[6], operands[2]);
13093 ;; Unconditional and other jump instructions
13095 (define_insn "jump"
13097 (label_ref (match_operand 0 "" "")))]
13100 [(set_attr "type" "ibr")
13101 (set (attr "length")
13102 (if_then_else (and (ge (minus (match_dup 0) (pc))
13104 (lt (minus (match_dup 0) (pc))
13108 (set_attr "modrm" "0")])
13110 (define_expand "indirect_jump"
13111 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13115 (define_insn "*indirect_jump"
13116 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13119 [(set_attr "type" "ibr")
13120 (set_attr "length_immediate" "0")])
13122 (define_insn "*indirect_jump_rtx64"
13123 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13126 [(set_attr "type" "ibr")
13127 (set_attr "length_immediate" "0")])
13129 (define_expand "tablejump"
13130 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13131 (use (label_ref (match_operand 1 "" "")))])]
13134 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13135 relative. Convert the relative address to an absolute address. */
13139 enum rtx_code code;
13145 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13147 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13151 op1 = pic_offset_table_rtx;
13156 op0 = pic_offset_table_rtx;
13160 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13165 (define_insn "*tablejump_1"
13166 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13167 (use (label_ref (match_operand 1 "" "")))]
13170 [(set_attr "type" "ibr")
13171 (set_attr "length_immediate" "0")])
13173 (define_insn "*tablejump_1_rtx64"
13174 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13175 (use (label_ref (match_operand 1 "" "")))]
13178 [(set_attr "type" "ibr")
13179 (set_attr "length_immediate" "0")])
13181 ;; Loop instruction
13183 ;; This is all complicated by the fact that since this is a jump insn
13184 ;; we must handle our own reloads.
13186 (define_expand "doloop_end"
13187 [(use (match_operand 0 "" "")) ; loop pseudo
13188 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13189 (use (match_operand 2 "" "")) ; max iterations
13190 (use (match_operand 3 "" "")) ; loop level
13191 (use (match_operand 4 "" ""))] ; label
13192 "!TARGET_64BIT && TARGET_USE_LOOP"
13195 /* Only use cloop on innermost loops. */
13196 if (INTVAL (operands[3]) > 1)
13198 if (GET_MODE (operands[0]) != SImode)
13200 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13205 (define_insn "doloop_end_internal"
13207 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13209 (label_ref (match_operand 0 "" ""))
13211 (set (match_operand:SI 2 "nonimmediate_operand" "=1,1,*m*r")
13212 (plus:SI (match_dup 1)
13214 (clobber (match_scratch:SI 3 "=X,X,r"))
13215 (clobber (reg:CC FLAGS_REG))]
13216 "!TARGET_64BIT && TARGET_USE_LOOP
13217 && (reload_in_progress || reload_completed
13218 || register_operand (operands[2], VOIDmode))"
13220 if (which_alternative != 0)
13222 if (get_attr_length (insn) == 2)
13223 return "%+loop\t%l0";
13225 return "dec{l}\t%1\;%+jne\t%l0";
13227 [(set (attr "length")
13228 (if_then_else (and (eq_attr "alternative" "0")
13229 (and (ge (minus (match_dup 0) (pc))
13231 (lt (minus (match_dup 0) (pc))
13235 ;; We don't know the type before shorten branches. Optimistically expect
13236 ;; the loop instruction to match.
13237 (set (attr "type") (const_string "ibr"))])
13241 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13243 (match_operand 0 "" "")
13246 (plus:SI (match_dup 1)
13248 (clobber (match_scratch:SI 2 ""))
13249 (clobber (reg:CC FLAGS_REG))]
13250 "!TARGET_64BIT && TARGET_USE_LOOP
13251 && reload_completed
13252 && REGNO (operands[1]) != 2"
13253 [(parallel [(set (reg:CCZ FLAGS_REG)
13254 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13256 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13257 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13264 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13266 (match_operand 0 "" "")
13268 (set (match_operand:SI 2 "nonimmediate_operand" "")
13269 (plus:SI (match_dup 1)
13271 (clobber (match_scratch:SI 3 ""))
13272 (clobber (reg:CC FLAGS_REG))]
13273 "!TARGET_64BIT && TARGET_USE_LOOP
13274 && reload_completed
13275 && (! REG_P (operands[2])
13276 || ! rtx_equal_p (operands[1], operands[2]))"
13277 [(set (match_dup 3) (match_dup 1))
13278 (parallel [(set (reg:CCZ FLAGS_REG)
13279 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13281 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13282 (set (match_dup 2) (match_dup 3))
13283 (set (pc) (if_then_else (ne (reg:CCZ FLAGS_REG) (const_int 0))
13288 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13291 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13292 (set (match_operand:QI 1 "register_operand" "")
13293 (match_operator:QI 2 "ix86_comparison_operator"
13294 [(reg FLAGS_REG) (const_int 0)]))
13295 (set (match_operand 3 "q_regs_operand" "")
13296 (zero_extend (match_dup 1)))]
13297 "(peep2_reg_dead_p (3, operands[1])
13298 || operands_match_p (operands[1], operands[3]))
13299 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13300 [(set (match_dup 4) (match_dup 0))
13301 (set (strict_low_part (match_dup 5))
13304 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13305 operands[5] = gen_lowpart (QImode, operands[3]);
13306 ix86_expand_clear (operands[3]);
13309 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13312 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13313 (set (match_operand:QI 1 "register_operand" "")
13314 (match_operator:QI 2 "ix86_comparison_operator"
13315 [(reg FLAGS_REG) (const_int 0)]))
13316 (parallel [(set (match_operand 3 "q_regs_operand" "")
13317 (zero_extend (match_dup 1)))
13318 (clobber (reg:CC FLAGS_REG))])]
13319 "(peep2_reg_dead_p (3, operands[1])
13320 || operands_match_p (operands[1], operands[3]))
13321 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13322 [(set (match_dup 4) (match_dup 0))
13323 (set (strict_low_part (match_dup 5))
13326 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13327 operands[5] = gen_lowpart (QImode, operands[3]);
13328 ix86_expand_clear (operands[3]);
13331 ;; Call instructions.
13333 ;; The predicates normally associated with named expanders are not properly
13334 ;; checked for calls. This is a bug in the generic code, but it isn't that
13335 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13337 ;; Call subroutine returning no value.
13339 (define_expand "call_pop"
13340 [(parallel [(call (match_operand:QI 0 "" "")
13341 (match_operand:SI 1 "" ""))
13342 (set (reg:SI SP_REG)
13343 (plus:SI (reg:SI SP_REG)
13344 (match_operand:SI 3 "" "")))])]
13347 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13351 (define_insn "*call_pop_0"
13352 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13353 (match_operand:SI 1 "" ""))
13354 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13355 (match_operand:SI 2 "immediate_operand" "")))]
13358 if (SIBLING_CALL_P (insn))
13361 return "call\t%P0";
13363 [(set_attr "type" "call")])
13365 (define_insn "*call_pop_1"
13366 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13367 (match_operand:SI 1 "" ""))
13368 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13369 (match_operand:SI 2 "immediate_operand" "i")))]
13372 if (constant_call_address_operand (operands[0], Pmode))
13374 if (SIBLING_CALL_P (insn))
13377 return "call\t%P0";
13379 if (SIBLING_CALL_P (insn))
13382 return "call\t%A0";
13384 [(set_attr "type" "call")])
13386 (define_expand "call"
13387 [(call (match_operand:QI 0 "" "")
13388 (match_operand 1 "" ""))
13389 (use (match_operand 2 "" ""))]
13392 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13396 (define_expand "sibcall"
13397 [(call (match_operand:QI 0 "" "")
13398 (match_operand 1 "" ""))
13399 (use (match_operand 2 "" ""))]
13402 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13406 (define_insn "*call_0"
13407 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13408 (match_operand 1 "" ""))]
13411 if (SIBLING_CALL_P (insn))
13414 return "call\t%P0";
13416 [(set_attr "type" "call")])
13418 (define_insn "*call_1"
13419 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13420 (match_operand 1 "" ""))]
13421 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13423 if (constant_call_address_operand (operands[0], Pmode))
13424 return "call\t%P0";
13425 return "call\t%A0";
13427 [(set_attr "type" "call")])
13429 (define_insn "*sibcall_1"
13430 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13431 (match_operand 1 "" ""))]
13432 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13434 if (constant_call_address_operand (operands[0], Pmode))
13438 [(set_attr "type" "call")])
13440 (define_insn "*call_1_rex64"
13441 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13442 (match_operand 1 "" ""))]
13443 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13445 if (constant_call_address_operand (operands[0], Pmode))
13446 return "call\t%P0";
13447 return "call\t%A0";
13449 [(set_attr "type" "call")])
13451 (define_insn "*sibcall_1_rex64"
13452 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13453 (match_operand 1 "" ""))]
13454 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13456 [(set_attr "type" "call")])
13458 (define_insn "*sibcall_1_rex64_v"
13459 [(call (mem:QI (reg:DI 40))
13460 (match_operand 0 "" ""))]
13461 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13463 [(set_attr "type" "call")])
13466 ;; Call subroutine, returning value in operand 0
13468 (define_expand "call_value_pop"
13469 [(parallel [(set (match_operand 0 "" "")
13470 (call (match_operand:QI 1 "" "")
13471 (match_operand:SI 2 "" "")))
13472 (set (reg:SI SP_REG)
13473 (plus:SI (reg:SI SP_REG)
13474 (match_operand:SI 4 "" "")))])]
13477 ix86_expand_call (operands[0], operands[1], operands[2],
13478 operands[3], operands[4], 0);
13482 (define_expand "call_value"
13483 [(set (match_operand 0 "" "")
13484 (call (match_operand:QI 1 "" "")
13485 (match_operand:SI 2 "" "")))
13486 (use (match_operand:SI 3 "" ""))]
13487 ;; Operand 2 not used on the i386.
13490 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13494 (define_expand "sibcall_value"
13495 [(set (match_operand 0 "" "")
13496 (call (match_operand:QI 1 "" "")
13497 (match_operand:SI 2 "" "")))
13498 (use (match_operand:SI 3 "" ""))]
13499 ;; Operand 2 not used on the i386.
13502 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13506 ;; Call subroutine returning any type.
13508 (define_expand "untyped_call"
13509 [(parallel [(call (match_operand 0 "" "")
13511 (match_operand 1 "" "")
13512 (match_operand 2 "" "")])]
13517 /* In order to give reg-stack an easier job in validating two
13518 coprocessor registers as containing a possible return value,
13519 simply pretend the untyped call returns a complex long double
13522 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13523 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13524 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13527 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13529 rtx set = XVECEXP (operands[2], 0, i);
13530 emit_move_insn (SET_DEST (set), SET_SRC (set));
13533 /* The optimizer does not know that the call sets the function value
13534 registers we stored in the result block. We avoid problems by
13535 claiming that all hard registers are used and clobbered at this
13537 emit_insn (gen_blockage (const0_rtx));
13542 ;; Prologue and epilogue instructions
13544 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13545 ;; all of memory. This blocks insns from being moved across this point.
13547 (define_insn "blockage"
13548 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13551 [(set_attr "length" "0")])
13553 ;; Insn emitted into the body of a function to return from a function.
13554 ;; This is only done if the function's epilogue is known to be simple.
13555 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13557 (define_expand "return"
13559 "ix86_can_use_return_insn_p ()"
13561 if (current_function_pops_args)
13563 rtx popc = GEN_INT (current_function_pops_args);
13564 emit_jump_insn (gen_return_pop_internal (popc));
13569 (define_insn "return_internal"
13573 [(set_attr "length" "1")
13574 (set_attr "length_immediate" "0")
13575 (set_attr "modrm" "0")])
13577 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13578 ;; instruction Athlon and K8 have.
13580 (define_insn "return_internal_long"
13582 (unspec [(const_int 0)] UNSPEC_REP)]
13585 [(set_attr "length" "1")
13586 (set_attr "length_immediate" "0")
13587 (set_attr "prefix_rep" "1")
13588 (set_attr "modrm" "0")])
13590 (define_insn "return_pop_internal"
13592 (use (match_operand:SI 0 "const_int_operand" ""))]
13595 [(set_attr "length" "3")
13596 (set_attr "length_immediate" "2")
13597 (set_attr "modrm" "0")])
13599 (define_insn "return_indirect_internal"
13601 (use (match_operand:SI 0 "register_operand" "r"))]
13604 [(set_attr "type" "ibr")
13605 (set_attr "length_immediate" "0")])
13611 [(set_attr "length" "1")
13612 (set_attr "length_immediate" "0")
13613 (set_attr "modrm" "0")])
13615 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13616 ;; branch prediction penalty for the third jump in a 16-byte
13619 (define_insn "align"
13620 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13623 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13624 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13626 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13627 The align insn is used to avoid 3 jump instructions in the row to improve
13628 branch prediction and the benefits hardly outweight the cost of extra 8
13629 nops on the average inserted by full alignment pseudo operation. */
13633 [(set_attr "length" "16")])
13635 (define_expand "prologue"
13638 "ix86_expand_prologue (); DONE;")
13640 (define_insn "set_got"
13641 [(set (match_operand:SI 0 "register_operand" "=r")
13642 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13643 (clobber (reg:CC FLAGS_REG))]
13645 { return output_set_got (operands[0]); }
13646 [(set_attr "type" "multi")
13647 (set_attr "length" "12")])
13649 (define_expand "epilogue"
13652 "ix86_expand_epilogue (1); DONE;")
13654 (define_expand "sibcall_epilogue"
13657 "ix86_expand_epilogue (0); DONE;")
13659 (define_expand "eh_return"
13660 [(use (match_operand 0 "register_operand" ""))]
13663 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13665 /* Tricky bit: we write the address of the handler to which we will
13666 be returning into someone else's stack frame, one word below the
13667 stack address we wish to restore. */
13668 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13669 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13670 tmp = gen_rtx_MEM (Pmode, tmp);
13671 emit_move_insn (tmp, ra);
13673 if (Pmode == SImode)
13674 emit_jump_insn (gen_eh_return_si (sa));
13676 emit_jump_insn (gen_eh_return_di (sa));
13681 (define_insn_and_split "eh_return_si"
13683 (unspec [(match_operand:SI 0 "register_operand" "c")]
13684 UNSPEC_EH_RETURN))]
13689 "ix86_expand_epilogue (2); DONE;")
13691 (define_insn_and_split "eh_return_di"
13693 (unspec [(match_operand:DI 0 "register_operand" "c")]
13694 UNSPEC_EH_RETURN))]
13699 "ix86_expand_epilogue (2); DONE;")
13701 (define_insn "leave"
13702 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13703 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13704 (clobber (mem:BLK (scratch)))]
13707 [(set_attr "type" "leave")])
13709 (define_insn "leave_rex64"
13710 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13711 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13712 (clobber (mem:BLK (scratch)))]
13715 [(set_attr "type" "leave")])
13717 (define_expand "ffssi2"
13719 [(set (match_operand:SI 0 "register_operand" "")
13720 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13721 (clobber (match_scratch:SI 2 ""))
13722 (clobber (reg:CC FLAGS_REG))])]
13726 (define_insn_and_split "*ffs_cmove"
13727 [(set (match_operand:SI 0 "register_operand" "=r")
13728 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13729 (clobber (match_scratch:SI 2 "=&r"))
13730 (clobber (reg:CC FLAGS_REG))]
13733 "&& reload_completed"
13734 [(set (match_dup 2) (const_int -1))
13735 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13736 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13737 (set (match_dup 0) (if_then_else:SI
13738 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13741 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13742 (clobber (reg:CC FLAGS_REG))])]
13745 (define_insn_and_split "*ffs_no_cmove"
13746 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
13747 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13748 (clobber (match_scratch:SI 2 "=&q"))
13749 (clobber (reg:CC FLAGS_REG))]
13753 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13754 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13755 (set (strict_low_part (match_dup 3))
13756 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
13757 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
13758 (clobber (reg:CC FLAGS_REG))])
13759 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
13760 (clobber (reg:CC FLAGS_REG))])
13761 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13762 (clobber (reg:CC FLAGS_REG))])]
13764 operands[3] = gen_lowpart (QImode, operands[2]);
13765 ix86_expand_clear (operands[2]);
13768 (define_insn "*ffssi_1"
13769 [(set (reg:CCZ FLAGS_REG)
13770 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
13772 (set (match_operand:SI 0 "register_operand" "=r")
13773 (ctz:SI (match_dup 1)))]
13775 "bsf{l}\t{%1, %0|%0, %1}"
13776 [(set_attr "prefix_0f" "1")])
13778 (define_expand "ffsdi2"
13780 [(set (match_operand:DI 0 "register_operand" "")
13781 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
13782 (clobber (match_scratch:DI 2 ""))
13783 (clobber (reg:CC FLAGS_REG))])]
13784 "TARGET_64BIT && TARGET_CMOVE"
13787 (define_insn_and_split "*ffs_rex64"
13788 [(set (match_operand:DI 0 "register_operand" "=r")
13789 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13790 (clobber (match_scratch:DI 2 "=&r"))
13791 (clobber (reg:CC FLAGS_REG))]
13792 "TARGET_64BIT && TARGET_CMOVE"
13794 "&& reload_completed"
13795 [(set (match_dup 2) (const_int -1))
13796 (parallel [(set (reg:CCZ FLAGS_REG)
13797 (compare:CCZ (match_dup 1) (const_int 0)))
13798 (set (match_dup 0) (ctz:DI (match_dup 1)))])
13799 (set (match_dup 0) (if_then_else:DI
13800 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13803 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
13804 (clobber (reg:CC FLAGS_REG))])]
13807 (define_insn "*ffsdi_1"
13808 [(set (reg:CCZ FLAGS_REG)
13809 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
13811 (set (match_operand:DI 0 "register_operand" "=r")
13812 (ctz:DI (match_dup 1)))]
13814 "bsf{q}\t{%1, %0|%0, %1}"
13815 [(set_attr "prefix_0f" "1")])
13817 (define_insn "ctzsi2"
13818 [(set (match_operand:SI 0 "register_operand" "=r")
13819 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13820 (clobber (reg:CC FLAGS_REG))]
13822 "bsf{l}\t{%1, %0|%0, %1}"
13823 [(set_attr "prefix_0f" "1")])
13825 (define_insn "ctzdi2"
13826 [(set (match_operand:DI 0 "register_operand" "=r")
13827 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
13828 (clobber (reg:CC FLAGS_REG))]
13830 "bsf{q}\t{%1, %0|%0, %1}"
13831 [(set_attr "prefix_0f" "1")])
13833 (define_expand "clzsi2"
13835 [(set (match_operand:SI 0 "register_operand" "")
13836 (minus:SI (const_int 31)
13837 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
13838 (clobber (reg:CC FLAGS_REG))])
13840 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
13841 (clobber (reg:CC FLAGS_REG))])]
13845 (define_insn "*bsr"
13846 [(set (match_operand:SI 0 "register_operand" "=r")
13847 (minus:SI (const_int 31)
13848 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
13849 (clobber (reg:CC FLAGS_REG))]
13851 "bsr{l}\t{%1, %0|%0, %1}"
13852 [(set_attr "prefix_0f" "1")])
13854 (define_expand "clzdi2"
13856 [(set (match_operand:DI 0 "register_operand" "")
13857 (minus:DI (const_int 63)
13858 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
13859 (clobber (reg:CC FLAGS_REG))])
13861 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
13862 (clobber (reg:CC FLAGS_REG))])]
13866 (define_insn "*bsr_rex64"
13867 [(set (match_operand:DI 0 "register_operand" "=r")
13868 (minus:DI (const_int 63)
13869 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
13870 (clobber (reg:CC FLAGS_REG))]
13872 "bsr{q}\t{%1, %0|%0, %1}"
13873 [(set_attr "prefix_0f" "1")])
13875 ;; Thread-local storage patterns for ELF.
13877 ;; Note that these code sequences must appear exactly as shown
13878 ;; in order to allow linker relaxation.
13880 (define_insn "*tls_global_dynamic_32_gnu"
13881 [(set (match_operand:SI 0 "register_operand" "=a")
13882 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13883 (match_operand:SI 2 "tls_symbolic_operand" "")
13884 (match_operand:SI 3 "call_insn_operand" "")]
13886 (clobber (match_scratch:SI 4 "=d"))
13887 (clobber (match_scratch:SI 5 "=c"))
13888 (clobber (reg:CC FLAGS_REG))]
13889 "!TARGET_64BIT && TARGET_GNU_TLS"
13890 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
13891 [(set_attr "type" "multi")
13892 (set_attr "length" "12")])
13894 (define_insn "*tls_global_dynamic_32_sun"
13895 [(set (match_operand:SI 0 "register_operand" "=a")
13896 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13897 (match_operand:SI 2 "tls_symbolic_operand" "")
13898 (match_operand:SI 3 "call_insn_operand" "")]
13900 (clobber (match_scratch:SI 4 "=d"))
13901 (clobber (match_scratch:SI 5 "=c"))
13902 (clobber (reg:CC FLAGS_REG))]
13903 "!TARGET_64BIT && TARGET_SUN_TLS"
13904 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
13905 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
13906 [(set_attr "type" "multi")
13907 (set_attr "length" "14")])
13909 (define_expand "tls_global_dynamic_32"
13910 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13913 (match_operand:SI 1 "tls_symbolic_operand" "")
13916 (clobber (match_scratch:SI 4 ""))
13917 (clobber (match_scratch:SI 5 ""))
13918 (clobber (reg:CC FLAGS_REG))])]
13922 operands[2] = pic_offset_table_rtx;
13925 operands[2] = gen_reg_rtx (Pmode);
13926 emit_insn (gen_set_got (operands[2]));
13928 operands[3] = ix86_tls_get_addr ();
13931 (define_insn "*tls_global_dynamic_64"
13932 [(set (match_operand:DI 0 "register_operand" "=a")
13933 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
13934 (match_operand:DI 3 "" "")))
13935 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13938 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
13939 [(set_attr "type" "multi")
13940 (set_attr "length" "16")])
13942 (define_expand "tls_global_dynamic_64"
13943 [(parallel [(set (match_operand:DI 0 "register_operand" "")
13944 (call (mem:QI (match_dup 2)) (const_int 0)))
13945 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
13949 operands[2] = ix86_tls_get_addr ();
13952 (define_insn "*tls_local_dynamic_base_32_gnu"
13953 [(set (match_operand:SI 0 "register_operand" "=a")
13954 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13955 (match_operand:SI 2 "call_insn_operand" "")]
13956 UNSPEC_TLS_LD_BASE))
13957 (clobber (match_scratch:SI 3 "=d"))
13958 (clobber (match_scratch:SI 4 "=c"))
13959 (clobber (reg:CC FLAGS_REG))]
13960 "!TARGET_64BIT && TARGET_GNU_TLS"
13961 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
13962 [(set_attr "type" "multi")
13963 (set_attr "length" "11")])
13965 (define_insn "*tls_local_dynamic_base_32_sun"
13966 [(set (match_operand:SI 0 "register_operand" "=a")
13967 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
13968 (match_operand:SI 2 "call_insn_operand" "")]
13969 UNSPEC_TLS_LD_BASE))
13970 (clobber (match_scratch:SI 3 "=d"))
13971 (clobber (match_scratch:SI 4 "=c"))
13972 (clobber (reg:CC FLAGS_REG))]
13973 "!TARGET_64BIT && TARGET_SUN_TLS"
13974 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
13975 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
13976 [(set_attr "type" "multi")
13977 (set_attr "length" "13")])
13979 (define_expand "tls_local_dynamic_base_32"
13980 [(parallel [(set (match_operand:SI 0 "register_operand" "")
13981 (unspec:SI [(match_dup 1) (match_dup 2)]
13982 UNSPEC_TLS_LD_BASE))
13983 (clobber (match_scratch:SI 3 ""))
13984 (clobber (match_scratch:SI 4 ""))
13985 (clobber (reg:CC FLAGS_REG))])]
13989 operands[1] = pic_offset_table_rtx;
13992 operands[1] = gen_reg_rtx (Pmode);
13993 emit_insn (gen_set_got (operands[1]));
13995 operands[2] = ix86_tls_get_addr ();
13998 (define_insn "*tls_local_dynamic_base_64"
13999 [(set (match_operand:DI 0 "register_operand" "=a")
14000 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14001 (match_operand:DI 2 "" "")))
14002 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14004 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14005 [(set_attr "type" "multi")
14006 (set_attr "length" "12")])
14008 (define_expand "tls_local_dynamic_base_64"
14009 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14010 (call (mem:QI (match_dup 1)) (const_int 0)))
14011 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14014 operands[1] = ix86_tls_get_addr ();
14017 ;; Local dynamic of a single variable is a lose. Show combine how
14018 ;; to convert that back to global dynamic.
14020 (define_insn_and_split "*tls_local_dynamic_32_once"
14021 [(set (match_operand:SI 0 "register_operand" "=a")
14022 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14023 (match_operand:SI 2 "call_insn_operand" "")]
14024 UNSPEC_TLS_LD_BASE)
14025 (const:SI (unspec:SI
14026 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14028 (clobber (match_scratch:SI 4 "=d"))
14029 (clobber (match_scratch:SI 5 "=c"))
14030 (clobber (reg:CC FLAGS_REG))]
14034 [(parallel [(set (match_dup 0)
14035 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14037 (clobber (match_dup 4))
14038 (clobber (match_dup 5))
14039 (clobber (reg:CC FLAGS_REG))])]
14042 ;; Load and add the thread base pointer from %gs:0.
14044 (define_insn "*load_tp_si"
14045 [(set (match_operand:SI 0 "register_operand" "=r")
14046 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14048 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14049 [(set_attr "type" "imov")
14050 (set_attr "modrm" "0")
14051 (set_attr "length" "7")
14052 (set_attr "memory" "load")
14053 (set_attr "imm_disp" "false")])
14055 (define_insn "*add_tp_si"
14056 [(set (match_operand:SI 0 "register_operand" "=r")
14057 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14058 (match_operand:SI 1 "register_operand" "0")))
14059 (clobber (reg:CC FLAGS_REG))]
14061 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14062 [(set_attr "type" "alu")
14063 (set_attr "modrm" "0")
14064 (set_attr "length" "7")
14065 (set_attr "memory" "load")
14066 (set_attr "imm_disp" "false")])
14068 (define_insn "*load_tp_di"
14069 [(set (match_operand:DI 0 "register_operand" "=r")
14070 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14072 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14073 [(set_attr "type" "imov")
14074 (set_attr "modrm" "0")
14075 (set_attr "length" "7")
14076 (set_attr "memory" "load")
14077 (set_attr "imm_disp" "false")])
14079 (define_insn "*add_tp_di"
14080 [(set (match_operand:DI 0 "register_operand" "=r")
14081 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14082 (match_operand:DI 1 "register_operand" "0")))
14083 (clobber (reg:CC FLAGS_REG))]
14085 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14086 [(set_attr "type" "alu")
14087 (set_attr "modrm" "0")
14088 (set_attr "length" "7")
14089 (set_attr "memory" "load")
14090 (set_attr "imm_disp" "false")])
14092 ;; These patterns match the binary 387 instructions for addM3, subM3,
14093 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14094 ;; SFmode. The first is the normal insn, the second the same insn but
14095 ;; with one operand a conversion, and the third the same insn but with
14096 ;; the other operand a conversion. The conversion may be SFmode or
14097 ;; SImode if the target mode DFmode, but only SImode if the target mode
14100 ;; Gcc is slightly more smart about handling normal two address instructions
14101 ;; so use special patterns for add and mull.
14103 (define_insn "*fop_sf_comm_mixed"
14104 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14105 (match_operator:SF 3 "binary_fp_operator"
14106 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14107 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14108 "TARGET_MIX_SSE_I387
14109 && COMMUTATIVE_ARITH_P (operands[3])
14110 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14111 "* return output_387_binary_op (insn, operands);"
14112 [(set (attr "type")
14113 (if_then_else (eq_attr "alternative" "1")
14114 (if_then_else (match_operand:SF 3 "mult_operator" "")
14115 (const_string "ssemul")
14116 (const_string "sseadd"))
14117 (if_then_else (match_operand:SF 3 "mult_operator" "")
14118 (const_string "fmul")
14119 (const_string "fop"))))
14120 (set_attr "mode" "SF")])
14122 (define_insn "*fop_sf_comm_sse"
14123 [(set (match_operand:SF 0 "register_operand" "=x")
14124 (match_operator:SF 3 "binary_fp_operator"
14125 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14126 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14128 && COMMUTATIVE_ARITH_P (operands[3])
14129 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14130 "* return output_387_binary_op (insn, operands);"
14131 [(set (attr "type")
14132 (if_then_else (match_operand:SF 3 "mult_operator" "")
14133 (const_string "ssemul")
14134 (const_string "sseadd")))
14135 (set_attr "mode" "SF")])
14137 (define_insn "*fop_sf_comm_i387"
14138 [(set (match_operand:SF 0 "register_operand" "=f")
14139 (match_operator:SF 3 "binary_fp_operator"
14140 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14141 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14143 && COMMUTATIVE_ARITH_P (operands[3])
14144 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14145 "* return output_387_binary_op (insn, operands);"
14146 [(set (attr "type")
14147 (if_then_else (match_operand:SF 3 "mult_operator" "")
14148 (const_string "fmul")
14149 (const_string "fop")))
14150 (set_attr "mode" "SF")])
14152 (define_insn "*fop_sf_1_mixed"
14153 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14154 (match_operator:SF 3 "binary_fp_operator"
14155 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14156 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14157 "TARGET_MIX_SSE_I387
14158 && !COMMUTATIVE_ARITH_P (operands[3])
14159 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14160 "* return output_387_binary_op (insn, operands);"
14161 [(set (attr "type")
14162 (cond [(and (eq_attr "alternative" "2")
14163 (match_operand:SF 3 "mult_operator" ""))
14164 (const_string "ssemul")
14165 (and (eq_attr "alternative" "2")
14166 (match_operand:SF 3 "div_operator" ""))
14167 (const_string "ssediv")
14168 (eq_attr "alternative" "2")
14169 (const_string "sseadd")
14170 (match_operand:SF 3 "mult_operator" "")
14171 (const_string "fmul")
14172 (match_operand:SF 3 "div_operator" "")
14173 (const_string "fdiv")
14175 (const_string "fop")))
14176 (set_attr "mode" "SF")])
14178 (define_insn "*fop_sf_1_sse"
14179 [(set (match_operand:SF 0 "register_operand" "=x")
14180 (match_operator:SF 3 "binary_fp_operator"
14181 [(match_operand:SF 1 "register_operand" "0")
14182 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14184 && !COMMUTATIVE_ARITH_P (operands[3])"
14185 "* return output_387_binary_op (insn, operands);"
14186 [(set (attr "type")
14187 (cond [(match_operand:SF 3 "mult_operator" "")
14188 (const_string "ssemul")
14189 (match_operand:SF 3 "div_operator" "")
14190 (const_string "ssediv")
14192 (const_string "sseadd")))
14193 (set_attr "mode" "SF")])
14195 (define_insn "*fop_sf_1_i387"
14196 [(set (match_operand:SF 0 "register_operand" "=f,f")
14197 (match_operator:SF 3 "binary_fp_operator"
14198 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14199 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14201 && !COMMUTATIVE_ARITH_P (operands[3])
14202 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14203 "* return output_387_binary_op (insn, operands);"
14204 [(set (attr "type")
14205 (cond [(match_operand:SF 3 "mult_operator" "")
14206 (const_string "fmul")
14207 (match_operand:SF 3 "div_operator" "")
14208 (const_string "fdiv")
14210 (const_string "fop")))
14211 (set_attr "mode" "SF")])
14214 ;; ??? Add SSE splitters for these!
14215 (define_insn "*fop_sf_2_i387"
14216 [(set (match_operand:SF 0 "register_operand" "=f,f")
14217 (match_operator:SF 3 "binary_fp_operator"
14218 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14219 (match_operand:SF 2 "register_operand" "0,0")]))]
14220 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14221 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14222 [(set (attr "type")
14223 (cond [(match_operand:SF 3 "mult_operator" "")
14224 (const_string "fmul")
14225 (match_operand:SF 3 "div_operator" "")
14226 (const_string "fdiv")
14228 (const_string "fop")))
14229 (set_attr "fp_int_src" "true")
14230 (set_attr "mode" "SI")])
14232 (define_insn "*fop_sf_3_i387"
14233 [(set (match_operand:SF 0 "register_operand" "=f,f")
14234 (match_operator:SF 3 "binary_fp_operator"
14235 [(match_operand:SF 1 "register_operand" "0,0")
14236 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14237 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14238 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14239 [(set (attr "type")
14240 (cond [(match_operand:SF 3 "mult_operator" "")
14241 (const_string "fmul")
14242 (match_operand:SF 3 "div_operator" "")
14243 (const_string "fdiv")
14245 (const_string "fop")))
14246 (set_attr "fp_int_src" "true")
14247 (set_attr "mode" "SI")])
14249 (define_insn "*fop_df_comm_mixed"
14250 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14251 (match_operator:DF 3 "binary_fp_operator"
14252 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14253 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14254 "TARGET_SSE2 && TARGET_MIX_SSE_I387
14255 && COMMUTATIVE_ARITH_P (operands[3])
14256 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14257 "* return output_387_binary_op (insn, operands);"
14258 [(set (attr "type")
14259 (if_then_else (eq_attr "alternative" "1")
14260 (if_then_else (match_operand:SF 3 "mult_operator" "")
14261 (const_string "ssemul")
14262 (const_string "sseadd"))
14263 (if_then_else (match_operand:SF 3 "mult_operator" "")
14264 (const_string "fmul")
14265 (const_string "fop"))))
14266 (set_attr "mode" "DF")])
14268 (define_insn "*fop_df_comm_sse"
14269 [(set (match_operand:DF 0 "register_operand" "=Y")
14270 (match_operator:DF 3 "binary_fp_operator"
14271 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14272 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14273 "TARGET_SSE2 && TARGET_SSE_MATH
14274 && COMMUTATIVE_ARITH_P (operands[3])
14275 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14276 "* return output_387_binary_op (insn, operands);"
14277 [(set (attr "type")
14278 (if_then_else (match_operand:SF 3 "mult_operator" "")
14279 (const_string "ssemul")
14280 (const_string "sseadd")))
14281 (set_attr "mode" "DF")])
14283 (define_insn "*fop_df_comm_i387"
14284 [(set (match_operand:DF 0 "register_operand" "=f")
14285 (match_operator:DF 3 "binary_fp_operator"
14286 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14287 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14289 && COMMUTATIVE_ARITH_P (operands[3])
14290 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14291 "* return output_387_binary_op (insn, operands);"
14292 [(set (attr "type")
14293 (if_then_else (match_operand:SF 3 "mult_operator" "")
14294 (const_string "fmul")
14295 (const_string "fop")))
14296 (set_attr "mode" "DF")])
14298 (define_insn "*fop_df_1_mixed"
14299 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14300 (match_operator:DF 3 "binary_fp_operator"
14301 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14302 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14303 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14304 && !COMMUTATIVE_ARITH_P (operands[3])
14305 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14306 "* return output_387_binary_op (insn, operands);"
14307 [(set (attr "type")
14308 (cond [(and (eq_attr "alternative" "2")
14309 (match_operand:SF 3 "mult_operator" ""))
14310 (const_string "ssemul")
14311 (and (eq_attr "alternative" "2")
14312 (match_operand:SF 3 "div_operator" ""))
14313 (const_string "ssediv")
14314 (eq_attr "alternative" "2")
14315 (const_string "sseadd")
14316 (match_operand:DF 3 "mult_operator" "")
14317 (const_string "fmul")
14318 (match_operand:DF 3 "div_operator" "")
14319 (const_string "fdiv")
14321 (const_string "fop")))
14322 (set_attr "mode" "DF")])
14324 (define_insn "*fop_df_1_sse"
14325 [(set (match_operand:DF 0 "register_operand" "=Y")
14326 (match_operator:DF 3 "binary_fp_operator"
14327 [(match_operand:DF 1 "register_operand" "0")
14328 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14329 "TARGET_SSE2 && TARGET_SSE_MATH
14330 && !COMMUTATIVE_ARITH_P (operands[3])"
14331 "* return output_387_binary_op (insn, operands);"
14332 [(set_attr "mode" "DF")
14334 (cond [(match_operand:SF 3 "mult_operator" "")
14335 (const_string "ssemul")
14336 (match_operand:SF 3 "div_operator" "")
14337 (const_string "ssediv")
14339 (const_string "sseadd")))])
14341 (define_insn "*fop_df_1_i387"
14342 [(set (match_operand:DF 0 "register_operand" "=f,f")
14343 (match_operator:DF 3 "binary_fp_operator"
14344 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14345 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14347 && !COMMUTATIVE_ARITH_P (operands[3])
14348 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14349 "* return output_387_binary_op (insn, operands);"
14350 [(set (attr "type")
14351 (cond [(match_operand:DF 3 "mult_operator" "")
14352 (const_string "fmul")
14353 (match_operand:DF 3 "div_operator" "")
14354 (const_string "fdiv")
14356 (const_string "fop")))
14357 (set_attr "mode" "DF")])
14359 ;; ??? Add SSE splitters for these!
14360 (define_insn "*fop_df_2_i387"
14361 [(set (match_operand:DF 0 "register_operand" "=f,f")
14362 (match_operator:DF 3 "binary_fp_operator"
14363 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14364 (match_operand:DF 2 "register_operand" "0,0")]))]
14365 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14366 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14367 [(set (attr "type")
14368 (cond [(match_operand:DF 3 "mult_operator" "")
14369 (const_string "fmul")
14370 (match_operand:DF 3 "div_operator" "")
14371 (const_string "fdiv")
14373 (const_string "fop")))
14374 (set_attr "fp_int_src" "true")
14375 (set_attr "mode" "SI")])
14377 (define_insn "*fop_df_3_i387"
14378 [(set (match_operand:DF 0 "register_operand" "=f,f")
14379 (match_operator:DF 3 "binary_fp_operator"
14380 [(match_operand:DF 1 "register_operand" "0,0")
14381 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14382 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14383 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14384 [(set (attr "type")
14385 (cond [(match_operand:DF 3 "mult_operator" "")
14386 (const_string "fmul")
14387 (match_operand:DF 3 "div_operator" "")
14388 (const_string "fdiv")
14390 (const_string "fop")))
14391 (set_attr "fp_int_src" "true")
14392 (set_attr "mode" "SI")])
14394 (define_insn "*fop_df_4_i387"
14395 [(set (match_operand:DF 0 "register_operand" "=f,f")
14396 (match_operator:DF 3 "binary_fp_operator"
14397 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14398 (match_operand:DF 2 "register_operand" "0,f")]))]
14399 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
14400 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14401 "* return output_387_binary_op (insn, operands);"
14402 [(set (attr "type")
14403 (cond [(match_operand:DF 3 "mult_operator" "")
14404 (const_string "fmul")
14405 (match_operand:DF 3 "div_operator" "")
14406 (const_string "fdiv")
14408 (const_string "fop")))
14409 (set_attr "mode" "SF")])
14411 (define_insn "*fop_df_5_i387"
14412 [(set (match_operand:DF 0 "register_operand" "=f,f")
14413 (match_operator:DF 3 "binary_fp_operator"
14414 [(match_operand:DF 1 "register_operand" "0,f")
14416 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14417 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14418 "* return output_387_binary_op (insn, operands);"
14419 [(set (attr "type")
14420 (cond [(match_operand:DF 3 "mult_operator" "")
14421 (const_string "fmul")
14422 (match_operand:DF 3 "div_operator" "")
14423 (const_string "fdiv")
14425 (const_string "fop")))
14426 (set_attr "mode" "SF")])
14428 (define_insn "*fop_df_6_i387"
14429 [(set (match_operand:DF 0 "register_operand" "=f,f")
14430 (match_operator:DF 3 "binary_fp_operator"
14432 (match_operand:SF 1 "register_operand" "0,f"))
14434 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14435 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14436 "* return output_387_binary_op (insn, operands);"
14437 [(set (attr "type")
14438 (cond [(match_operand:DF 3 "mult_operator" "")
14439 (const_string "fmul")
14440 (match_operand:DF 3 "div_operator" "")
14441 (const_string "fdiv")
14443 (const_string "fop")))
14444 (set_attr "mode" "SF")])
14446 (define_insn "*fop_xf_comm_i387"
14447 [(set (match_operand:XF 0 "register_operand" "=f")
14448 (match_operator:XF 3 "binary_fp_operator"
14449 [(match_operand:XF 1 "register_operand" "%0")
14450 (match_operand:XF 2 "register_operand" "f")]))]
14452 && COMMUTATIVE_ARITH_P (operands[3])"
14453 "* return output_387_binary_op (insn, operands);"
14454 [(set (attr "type")
14455 (if_then_else (match_operand:XF 3 "mult_operator" "")
14456 (const_string "fmul")
14457 (const_string "fop")))
14458 (set_attr "mode" "XF")])
14460 (define_insn "*fop_xf_1_i387"
14461 [(set (match_operand:XF 0 "register_operand" "=f,f")
14462 (match_operator:XF 3 "binary_fp_operator"
14463 [(match_operand:XF 1 "register_operand" "0,f")
14464 (match_operand:XF 2 "register_operand" "f,0")]))]
14466 && !COMMUTATIVE_ARITH_P (operands[3])"
14467 "* return output_387_binary_op (insn, operands);"
14468 [(set (attr "type")
14469 (cond [(match_operand:XF 3 "mult_operator" "")
14470 (const_string "fmul")
14471 (match_operand:XF 3 "div_operator" "")
14472 (const_string "fdiv")
14474 (const_string "fop")))
14475 (set_attr "mode" "XF")])
14477 (define_insn "*fop_xf_2_i387"
14478 [(set (match_operand:XF 0 "register_operand" "=f,f")
14479 (match_operator:XF 3 "binary_fp_operator"
14480 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14481 (match_operand:XF 2 "register_operand" "0,0")]))]
14482 "TARGET_80387 && TARGET_USE_FIOP"
14483 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14484 [(set (attr "type")
14485 (cond [(match_operand:XF 3 "mult_operator" "")
14486 (const_string "fmul")
14487 (match_operand:XF 3 "div_operator" "")
14488 (const_string "fdiv")
14490 (const_string "fop")))
14491 (set_attr "fp_int_src" "true")
14492 (set_attr "mode" "SI")])
14494 (define_insn "*fop_xf_3_i387"
14495 [(set (match_operand:XF 0 "register_operand" "=f,f")
14496 (match_operator:XF 3 "binary_fp_operator"
14497 [(match_operand:XF 1 "register_operand" "0,0")
14498 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14499 "TARGET_80387 && TARGET_USE_FIOP"
14500 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14501 [(set (attr "type")
14502 (cond [(match_operand:XF 3 "mult_operator" "")
14503 (const_string "fmul")
14504 (match_operand:XF 3 "div_operator" "")
14505 (const_string "fdiv")
14507 (const_string "fop")))
14508 (set_attr "fp_int_src" "true")
14509 (set_attr "mode" "SI")])
14511 (define_insn "*fop_xf_4_i387"
14512 [(set (match_operand:XF 0 "register_operand" "=f,f")
14513 (match_operator:XF 3 "binary_fp_operator"
14514 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14515 (match_operand:XF 2 "register_operand" "0,f")]))]
14517 "* return output_387_binary_op (insn, operands);"
14518 [(set (attr "type")
14519 (cond [(match_operand:XF 3 "mult_operator" "")
14520 (const_string "fmul")
14521 (match_operand:XF 3 "div_operator" "")
14522 (const_string "fdiv")
14524 (const_string "fop")))
14525 (set_attr "mode" "SF")])
14527 (define_insn "*fop_xf_5_i387"
14528 [(set (match_operand:XF 0 "register_operand" "=f,f")
14529 (match_operator:XF 3 "binary_fp_operator"
14530 [(match_operand:XF 1 "register_operand" "0,f")
14532 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14534 "* return output_387_binary_op (insn, operands);"
14535 [(set (attr "type")
14536 (cond [(match_operand:XF 3 "mult_operator" "")
14537 (const_string "fmul")
14538 (match_operand:XF 3 "div_operator" "")
14539 (const_string "fdiv")
14541 (const_string "fop")))
14542 (set_attr "mode" "SF")])
14544 (define_insn "*fop_xf_6_i387"
14545 [(set (match_operand:XF 0 "register_operand" "=f,f")
14546 (match_operator:XF 3 "binary_fp_operator"
14548 (match_operand 1 "register_operand" "0,f"))
14550 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14552 "* return output_387_binary_op (insn, operands);"
14553 [(set (attr "type")
14554 (cond [(match_operand:XF 3 "mult_operator" "")
14555 (const_string "fmul")
14556 (match_operand:XF 3 "div_operator" "")
14557 (const_string "fdiv")
14559 (const_string "fop")))
14560 (set_attr "mode" "SF")])
14563 [(set (match_operand 0 "register_operand" "")
14564 (match_operator 3 "binary_fp_operator"
14565 [(float (match_operand:SI 1 "register_operand" ""))
14566 (match_operand 2 "register_operand" "")]))]
14567 "TARGET_80387 && reload_completed
14568 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14571 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14572 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14573 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14574 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14575 GET_MODE (operands[3]),
14578 ix86_free_from_memory (GET_MODE (operands[1]));
14583 [(set (match_operand 0 "register_operand" "")
14584 (match_operator 3 "binary_fp_operator"
14585 [(match_operand 1 "register_operand" "")
14586 (float (match_operand:SI 2 "register_operand" ""))]))]
14587 "TARGET_80387 && reload_completed
14588 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14591 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14592 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14593 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14594 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14595 GET_MODE (operands[3]),
14598 ix86_free_from_memory (GET_MODE (operands[2]));
14602 ;; FPU special functions.
14604 (define_expand "sqrtsf2"
14605 [(set (match_operand:SF 0 "register_operand" "")
14606 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14607 "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
14609 if (!TARGET_SSE_MATH)
14610 operands[1] = force_reg (SFmode, operands[1]);
14613 (define_insn "*sqrtsf2_mixed"
14614 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14615 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14616 "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
14619 sqrtss\t{%1, %0|%0, %1}"
14620 [(set_attr "type" "fpspc,sse")
14621 (set_attr "mode" "SF,SF")
14622 (set_attr "athlon_decode" "direct,*")])
14624 (define_insn "*sqrtsf2_sse"
14625 [(set (match_operand:SF 0 "register_operand" "=x")
14626 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14628 "sqrtss\t{%1, %0|%0, %1}"
14629 [(set_attr "type" "sse")
14630 (set_attr "mode" "SF")
14631 (set_attr "athlon_decode" "*")])
14633 (define_insn "*sqrtsf2_i387"
14634 [(set (match_operand:SF 0 "register_operand" "=f")
14635 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14636 "TARGET_USE_FANCY_MATH_387"
14638 [(set_attr "type" "fpspc")
14639 (set_attr "mode" "SF")
14640 (set_attr "athlon_decode" "direct")])
14642 (define_expand "sqrtdf2"
14643 [(set (match_operand:DF 0 "register_operand" "")
14644 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14645 "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14647 if (!(TARGET_SSE2 && TARGET_SSE_MATH))
14648 operands[1] = force_reg (DFmode, operands[1]);
14651 (define_insn "*sqrtdf2_mixed"
14652 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14653 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14654 "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
14657 sqrtsd\t{%1, %0|%0, %1}"
14658 [(set_attr "type" "fpspc,sse")
14659 (set_attr "mode" "DF,DF")
14660 (set_attr "athlon_decode" "direct,*")])
14662 (define_insn "*sqrtdf2_sse"
14663 [(set (match_operand:DF 0 "register_operand" "=Y")
14664 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14665 "TARGET_SSE2 && TARGET_SSE_MATH"
14666 "sqrtsd\t{%1, %0|%0, %1}"
14667 [(set_attr "type" "sse")
14668 (set_attr "mode" "DF")
14669 (set_attr "athlon_decode" "*")])
14671 (define_insn "*sqrtdf2_i387"
14672 [(set (match_operand:DF 0 "register_operand" "=f")
14673 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14674 "TARGET_USE_FANCY_MATH_387"
14676 [(set_attr "type" "fpspc")
14677 (set_attr "mode" "DF")
14678 (set_attr "athlon_decode" "direct")])
14680 (define_insn "*sqrtextendsfdf2_i387"
14681 [(set (match_operand:DF 0 "register_operand" "=f")
14682 (sqrt:DF (float_extend:DF
14683 (match_operand:SF 1 "register_operand" "0"))))]
14684 "TARGET_USE_FANCY_MATH_387
14685 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
14687 [(set_attr "type" "fpspc")
14688 (set_attr "mode" "DF")
14689 (set_attr "athlon_decode" "direct")])
14691 (define_insn "sqrtxf2"
14692 [(set (match_operand:XF 0 "register_operand" "=f")
14693 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14694 "TARGET_USE_FANCY_MATH_387
14695 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14697 [(set_attr "type" "fpspc")
14698 (set_attr "mode" "XF")
14699 (set_attr "athlon_decode" "direct")])
14701 (define_insn "*sqrtextendsfxf2_i387"
14702 [(set (match_operand:XF 0 "register_operand" "=f")
14703 (sqrt:XF (float_extend:XF
14704 (match_operand:SF 1 "register_operand" "0"))))]
14705 "TARGET_USE_FANCY_MATH_387"
14707 [(set_attr "type" "fpspc")
14708 (set_attr "mode" "XF")
14709 (set_attr "athlon_decode" "direct")])
14711 (define_insn "*sqrtextenddfxf2_i387"
14712 [(set (match_operand:XF 0 "register_operand" "=f")
14713 (sqrt:XF (float_extend:XF
14714 (match_operand:DF 1 "register_operand" "0"))))]
14715 "TARGET_USE_FANCY_MATH_387"
14717 [(set_attr "type" "fpspc")
14718 (set_attr "mode" "XF")
14719 (set_attr "athlon_decode" "direct")])
14721 (define_insn "fpremxf4"
14722 [(set (match_operand:XF 0 "register_operand" "=f")
14723 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14724 (match_operand:XF 3 "register_operand" "1")]
14726 (set (match_operand:XF 1 "register_operand" "=u")
14727 (unspec:XF [(match_dup 2) (match_dup 3)]
14729 (set (reg:CCFP FPSR_REG)
14730 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14731 "TARGET_USE_FANCY_MATH_387
14732 && flag_unsafe_math_optimizations"
14734 [(set_attr "type" "fpspc")
14735 (set_attr "mode" "XF")])
14737 (define_expand "fmodsf3"
14738 [(use (match_operand:SF 0 "register_operand" ""))
14739 (use (match_operand:SF 1 "register_operand" ""))
14740 (use (match_operand:SF 2 "register_operand" ""))]
14741 "TARGET_USE_FANCY_MATH_387
14742 && flag_unsafe_math_optimizations"
14744 rtx label = gen_label_rtx ();
14746 rtx op1 = gen_reg_rtx (XFmode);
14747 rtx op2 = gen_reg_rtx (XFmode);
14749 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14750 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14752 emit_label (label);
14754 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14755 ix86_emit_fp_unordered_jump (label);
14757 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
14761 (define_expand "fmoddf3"
14762 [(use (match_operand:DF 0 "register_operand" ""))
14763 (use (match_operand:DF 1 "register_operand" ""))
14764 (use (match_operand:DF 2 "register_operand" ""))]
14765 "TARGET_USE_FANCY_MATH_387
14766 && flag_unsafe_math_optimizations"
14768 rtx label = gen_label_rtx ();
14770 rtx op1 = gen_reg_rtx (XFmode);
14771 rtx op2 = gen_reg_rtx (XFmode);
14773 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14774 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14776 emit_label (label);
14778 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14779 ix86_emit_fp_unordered_jump (label);
14781 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
14785 (define_expand "fmodxf3"
14786 [(use (match_operand:XF 0 "register_operand" ""))
14787 (use (match_operand:XF 1 "register_operand" ""))
14788 (use (match_operand:XF 2 "register_operand" ""))]
14789 "TARGET_USE_FANCY_MATH_387
14790 && flag_unsafe_math_optimizations"
14792 rtx label = gen_label_rtx ();
14794 emit_label (label);
14796 emit_insn (gen_fpremxf4 (operands[1], operands[2],
14797 operands[1], operands[2]));
14798 ix86_emit_fp_unordered_jump (label);
14800 emit_move_insn (operands[0], operands[1]);
14804 (define_insn "fprem1xf4"
14805 [(set (match_operand:XF 0 "register_operand" "=f")
14806 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14807 (match_operand:XF 3 "register_operand" "1")]
14809 (set (match_operand:XF 1 "register_operand" "=u")
14810 (unspec:XF [(match_dup 2) (match_dup 3)]
14812 (set (reg:CCFP FPSR_REG)
14813 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14814 "TARGET_USE_FANCY_MATH_387
14815 && flag_unsafe_math_optimizations"
14817 [(set_attr "type" "fpspc")
14818 (set_attr "mode" "XF")])
14820 (define_expand "dremsf3"
14821 [(use (match_operand:SF 0 "register_operand" ""))
14822 (use (match_operand:SF 1 "register_operand" ""))
14823 (use (match_operand:SF 2 "register_operand" ""))]
14824 "TARGET_USE_FANCY_MATH_387
14825 && flag_unsafe_math_optimizations"
14827 rtx label = gen_label_rtx ();
14829 rtx op1 = gen_reg_rtx (XFmode);
14830 rtx op2 = gen_reg_rtx (XFmode);
14832 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14833 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14835 emit_label (label);
14837 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14838 ix86_emit_fp_unordered_jump (label);
14840 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
14844 (define_expand "dremdf3"
14845 [(use (match_operand:DF 0 "register_operand" ""))
14846 (use (match_operand:DF 1 "register_operand" ""))
14847 (use (match_operand:DF 2 "register_operand" ""))]
14848 "TARGET_USE_FANCY_MATH_387
14849 && flag_unsafe_math_optimizations"
14851 rtx label = gen_label_rtx ();
14853 rtx op1 = gen_reg_rtx (XFmode);
14854 rtx op2 = gen_reg_rtx (XFmode);
14856 emit_insn (gen_extenddfxf2 (op1, operands[1]));
14857 emit_insn (gen_extenddfxf2 (op2, operands[2]));
14859 emit_label (label);
14861 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
14862 ix86_emit_fp_unordered_jump (label);
14864 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
14868 (define_expand "dremxf3"
14869 [(use (match_operand:XF 0 "register_operand" ""))
14870 (use (match_operand:XF 1 "register_operand" ""))
14871 (use (match_operand:XF 2 "register_operand" ""))]
14872 "TARGET_USE_FANCY_MATH_387
14873 && flag_unsafe_math_optimizations"
14875 rtx label = gen_label_rtx ();
14877 emit_label (label);
14879 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
14880 operands[1], operands[2]));
14881 ix86_emit_fp_unordered_jump (label);
14883 emit_move_insn (operands[0], operands[1]);
14887 (define_insn "*sindf2"
14888 [(set (match_operand:DF 0 "register_operand" "=f")
14889 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
14890 "TARGET_USE_FANCY_MATH_387
14891 && flag_unsafe_math_optimizations"
14893 [(set_attr "type" "fpspc")
14894 (set_attr "mode" "DF")])
14896 (define_insn "*sinsf2"
14897 [(set (match_operand:SF 0 "register_operand" "=f")
14898 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
14899 "TARGET_USE_FANCY_MATH_387
14900 && flag_unsafe_math_optimizations"
14902 [(set_attr "type" "fpspc")
14903 (set_attr "mode" "SF")])
14905 (define_insn "*sinextendsfdf2"
14906 [(set (match_operand:DF 0 "register_operand" "=f")
14907 (unspec:DF [(float_extend:DF
14908 (match_operand:SF 1 "register_operand" "0"))]
14910 "TARGET_USE_FANCY_MATH_387
14911 && flag_unsafe_math_optimizations"
14913 [(set_attr "type" "fpspc")
14914 (set_attr "mode" "DF")])
14916 (define_insn "*sinxf2"
14917 [(set (match_operand:XF 0 "register_operand" "=f")
14918 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
14919 "TARGET_USE_FANCY_MATH_387
14920 && flag_unsafe_math_optimizations"
14922 [(set_attr "type" "fpspc")
14923 (set_attr "mode" "XF")])
14925 (define_insn "*cosdf2"
14926 [(set (match_operand:DF 0 "register_operand" "=f")
14927 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
14928 "TARGET_USE_FANCY_MATH_387
14929 && flag_unsafe_math_optimizations"
14931 [(set_attr "type" "fpspc")
14932 (set_attr "mode" "DF")])
14934 (define_insn "*cossf2"
14935 [(set (match_operand:SF 0 "register_operand" "=f")
14936 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
14937 "TARGET_USE_FANCY_MATH_387
14938 && flag_unsafe_math_optimizations"
14940 [(set_attr "type" "fpspc")
14941 (set_attr "mode" "SF")])
14943 (define_insn "*cosextendsfdf2"
14944 [(set (match_operand:DF 0 "register_operand" "=f")
14945 (unspec:DF [(float_extend:DF
14946 (match_operand:SF 1 "register_operand" "0"))]
14948 "TARGET_USE_FANCY_MATH_387
14949 && flag_unsafe_math_optimizations"
14951 [(set_attr "type" "fpspc")
14952 (set_attr "mode" "DF")])
14954 (define_insn "*cosxf2"
14955 [(set (match_operand:XF 0 "register_operand" "=f")
14956 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
14957 "TARGET_USE_FANCY_MATH_387
14958 && flag_unsafe_math_optimizations"
14960 [(set_attr "type" "fpspc")
14961 (set_attr "mode" "XF")])
14963 ;; With sincos pattern defined, sin and cos builtin function will be
14964 ;; expanded to sincos pattern with one of its outputs left unused.
14965 ;; Cse pass will detected, if two sincos patterns can be combined,
14966 ;; otherwise sincos pattern will be split back to sin or cos pattern,
14967 ;; depending on the unused output.
14969 (define_insn "sincosdf3"
14970 [(set (match_operand:DF 0 "register_operand" "=f")
14971 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
14972 UNSPEC_SINCOS_COS))
14973 (set (match_operand:DF 1 "register_operand" "=u")
14974 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
14975 "TARGET_USE_FANCY_MATH_387
14976 && flag_unsafe_math_optimizations"
14978 [(set_attr "type" "fpspc")
14979 (set_attr "mode" "DF")])
14982 [(set (match_operand:DF 0 "register_operand" "")
14983 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
14984 UNSPEC_SINCOS_COS))
14985 (set (match_operand:DF 1 "register_operand" "")
14986 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
14987 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
14988 && !reload_completed && !reload_in_progress"
14989 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
14993 [(set (match_operand:DF 0 "register_operand" "")
14994 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
14995 UNSPEC_SINCOS_COS))
14996 (set (match_operand:DF 1 "register_operand" "")
14997 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
14998 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
14999 && !reload_completed && !reload_in_progress"
15000 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15003 (define_insn "sincossf3"
15004 [(set (match_operand:SF 0 "register_operand" "=f")
15005 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15006 UNSPEC_SINCOS_COS))
15007 (set (match_operand:SF 1 "register_operand" "=u")
15008 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15009 "TARGET_USE_FANCY_MATH_387
15010 && flag_unsafe_math_optimizations"
15012 [(set_attr "type" "fpspc")
15013 (set_attr "mode" "SF")])
15016 [(set (match_operand:SF 0 "register_operand" "")
15017 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15018 UNSPEC_SINCOS_COS))
15019 (set (match_operand:SF 1 "register_operand" "")
15020 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15021 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15022 && !reload_completed && !reload_in_progress"
15023 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15027 [(set (match_operand:SF 0 "register_operand" "")
15028 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15029 UNSPEC_SINCOS_COS))
15030 (set (match_operand:SF 1 "register_operand" "")
15031 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15032 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15033 && !reload_completed && !reload_in_progress"
15034 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15037 (define_insn "*sincosextendsfdf3"
15038 [(set (match_operand:DF 0 "register_operand" "=f")
15039 (unspec:DF [(float_extend:DF
15040 (match_operand:SF 2 "register_operand" "0"))]
15041 UNSPEC_SINCOS_COS))
15042 (set (match_operand:DF 1 "register_operand" "=u")
15043 (unspec:DF [(float_extend:DF
15044 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15045 "TARGET_USE_FANCY_MATH_387
15046 && flag_unsafe_math_optimizations"
15048 [(set_attr "type" "fpspc")
15049 (set_attr "mode" "DF")])
15052 [(set (match_operand:DF 0 "register_operand" "")
15053 (unspec:DF [(float_extend:DF
15054 (match_operand:SF 2 "register_operand" ""))]
15055 UNSPEC_SINCOS_COS))
15056 (set (match_operand:DF 1 "register_operand" "")
15057 (unspec:DF [(float_extend:DF
15058 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15059 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15060 && !reload_completed && !reload_in_progress"
15061 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15062 (match_dup 2))] UNSPEC_SIN))]
15066 [(set (match_operand:DF 0 "register_operand" "")
15067 (unspec:DF [(float_extend:DF
15068 (match_operand:SF 2 "register_operand" ""))]
15069 UNSPEC_SINCOS_COS))
15070 (set (match_operand:DF 1 "register_operand" "")
15071 (unspec:DF [(float_extend:DF
15072 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15073 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15074 && !reload_completed && !reload_in_progress"
15075 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15076 (match_dup 2))] UNSPEC_COS))]
15079 (define_insn "sincosxf3"
15080 [(set (match_operand:XF 0 "register_operand" "=f")
15081 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15082 UNSPEC_SINCOS_COS))
15083 (set (match_operand:XF 1 "register_operand" "=u")
15084 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15085 "TARGET_USE_FANCY_MATH_387
15086 && flag_unsafe_math_optimizations"
15088 [(set_attr "type" "fpspc")
15089 (set_attr "mode" "XF")])
15092 [(set (match_operand:XF 0 "register_operand" "")
15093 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15094 UNSPEC_SINCOS_COS))
15095 (set (match_operand:XF 1 "register_operand" "")
15096 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15097 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15098 && !reload_completed && !reload_in_progress"
15099 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15103 [(set (match_operand:XF 0 "register_operand" "")
15104 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15105 UNSPEC_SINCOS_COS))
15106 (set (match_operand:XF 1 "register_operand" "")
15107 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15108 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15109 && !reload_completed && !reload_in_progress"
15110 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15113 (define_insn "*tandf3_1"
15114 [(set (match_operand:DF 0 "register_operand" "=f")
15115 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15117 (set (match_operand:DF 1 "register_operand" "=u")
15118 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15119 "TARGET_USE_FANCY_MATH_387
15120 && flag_unsafe_math_optimizations"
15122 [(set_attr "type" "fpspc")
15123 (set_attr "mode" "DF")])
15125 ;; optimize sequence: fptan
15128 ;; into fptan insn.
15131 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15132 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15134 (set (match_operand:DF 1 "register_operand" "")
15135 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15137 (match_operand:DF 3 "immediate_operand" ""))]
15138 "standard_80387_constant_p (operands[3]) == 2"
15139 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15140 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15143 (define_expand "tandf2"
15144 [(parallel [(set (match_dup 2)
15145 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15147 (set (match_operand:DF 0 "register_operand" "")
15148 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15149 "TARGET_USE_FANCY_MATH_387
15150 && flag_unsafe_math_optimizations"
15152 operands[2] = gen_reg_rtx (DFmode);
15155 (define_insn "*tansf3_1"
15156 [(set (match_operand:SF 0 "register_operand" "=f")
15157 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15159 (set (match_operand:SF 1 "register_operand" "=u")
15160 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15161 "TARGET_USE_FANCY_MATH_387
15162 && flag_unsafe_math_optimizations"
15164 [(set_attr "type" "fpspc")
15165 (set_attr "mode" "SF")])
15167 ;; optimize sequence: fptan
15170 ;; into fptan insn.
15173 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15174 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15176 (set (match_operand:SF 1 "register_operand" "")
15177 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15179 (match_operand:SF 3 "immediate_operand" ""))]
15180 "standard_80387_constant_p (operands[3]) == 2"
15181 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15182 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15185 (define_expand "tansf2"
15186 [(parallel [(set (match_dup 2)
15187 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15189 (set (match_operand:SF 0 "register_operand" "")
15190 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15191 "TARGET_USE_FANCY_MATH_387
15192 && flag_unsafe_math_optimizations"
15194 operands[2] = gen_reg_rtx (SFmode);
15197 (define_insn "*tanxf3_1"
15198 [(set (match_operand:XF 0 "register_operand" "=f")
15199 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15201 (set (match_operand:XF 1 "register_operand" "=u")
15202 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15203 "TARGET_USE_FANCY_MATH_387
15204 && flag_unsafe_math_optimizations"
15206 [(set_attr "type" "fpspc")
15207 (set_attr "mode" "XF")])
15209 ;; optimize sequence: fptan
15212 ;; into fptan insn.
15215 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15216 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15218 (set (match_operand:XF 1 "register_operand" "")
15219 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15221 (match_operand:XF 3 "immediate_operand" ""))]
15222 "standard_80387_constant_p (operands[3]) == 2"
15223 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15224 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15227 (define_expand "tanxf2"
15228 [(parallel [(set (match_dup 2)
15229 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15231 (set (match_operand:XF 0 "register_operand" "")
15232 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15233 "TARGET_USE_FANCY_MATH_387
15234 && flag_unsafe_math_optimizations"
15236 operands[2] = gen_reg_rtx (XFmode);
15239 (define_insn "atan2df3_1"
15240 [(set (match_operand:DF 0 "register_operand" "=f")
15241 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15242 (match_operand:DF 1 "register_operand" "u")]
15244 (clobber (match_scratch:DF 3 "=1"))]
15245 "TARGET_USE_FANCY_MATH_387
15246 && flag_unsafe_math_optimizations"
15248 [(set_attr "type" "fpspc")
15249 (set_attr "mode" "DF")])
15251 (define_expand "atan2df3"
15252 [(use (match_operand:DF 0 "register_operand" "=f"))
15253 (use (match_operand:DF 2 "register_operand" "0"))
15254 (use (match_operand:DF 1 "register_operand" "u"))]
15255 "TARGET_USE_FANCY_MATH_387
15256 && flag_unsafe_math_optimizations"
15258 rtx copy = gen_reg_rtx (DFmode);
15259 emit_move_insn (copy, operands[1]);
15260 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15264 (define_expand "atandf2"
15265 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15266 (unspec:DF [(match_dup 2)
15267 (match_operand:DF 1 "register_operand" "")]
15269 (clobber (match_scratch:DF 3 ""))])]
15270 "TARGET_USE_FANCY_MATH_387
15271 && flag_unsafe_math_optimizations"
15273 operands[2] = gen_reg_rtx (DFmode);
15274 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15277 (define_insn "atan2sf3_1"
15278 [(set (match_operand:SF 0 "register_operand" "=f")
15279 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15280 (match_operand:SF 1 "register_operand" "u")]
15282 (clobber (match_scratch:SF 3 "=1"))]
15283 "TARGET_USE_FANCY_MATH_387
15284 && flag_unsafe_math_optimizations"
15286 [(set_attr "type" "fpspc")
15287 (set_attr "mode" "SF")])
15289 (define_expand "atan2sf3"
15290 [(use (match_operand:SF 0 "register_operand" "=f"))
15291 (use (match_operand:SF 2 "register_operand" "0"))
15292 (use (match_operand:SF 1 "register_operand" "u"))]
15293 "TARGET_USE_FANCY_MATH_387
15294 && flag_unsafe_math_optimizations"
15296 rtx copy = gen_reg_rtx (SFmode);
15297 emit_move_insn (copy, operands[1]);
15298 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15302 (define_expand "atansf2"
15303 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15304 (unspec:SF [(match_dup 2)
15305 (match_operand:SF 1 "register_operand" "")]
15307 (clobber (match_scratch:SF 3 ""))])]
15308 "TARGET_USE_FANCY_MATH_387
15309 && flag_unsafe_math_optimizations"
15311 operands[2] = gen_reg_rtx (SFmode);
15312 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15315 (define_insn "atan2xf3_1"
15316 [(set (match_operand:XF 0 "register_operand" "=f")
15317 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15318 (match_operand:XF 1 "register_operand" "u")]
15320 (clobber (match_scratch:XF 3 "=1"))]
15321 "TARGET_USE_FANCY_MATH_387
15322 && flag_unsafe_math_optimizations"
15324 [(set_attr "type" "fpspc")
15325 (set_attr "mode" "XF")])
15327 (define_expand "atan2xf3"
15328 [(use (match_operand:XF 0 "register_operand" "=f"))
15329 (use (match_operand:XF 2 "register_operand" "0"))
15330 (use (match_operand:XF 1 "register_operand" "u"))]
15331 "TARGET_USE_FANCY_MATH_387
15332 && flag_unsafe_math_optimizations"
15334 rtx copy = gen_reg_rtx (XFmode);
15335 emit_move_insn (copy, operands[1]);
15336 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15340 (define_expand "atanxf2"
15341 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15342 (unspec:XF [(match_dup 2)
15343 (match_operand:XF 1 "register_operand" "")]
15345 (clobber (match_scratch:XF 3 ""))])]
15346 "TARGET_USE_FANCY_MATH_387
15347 && flag_unsafe_math_optimizations"
15349 operands[2] = gen_reg_rtx (XFmode);
15350 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15353 (define_expand "asindf2"
15354 [(set (match_dup 2)
15355 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15356 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15357 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15358 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15359 (parallel [(set (match_dup 7)
15360 (unspec:XF [(match_dup 6) (match_dup 2)]
15362 (clobber (match_scratch:XF 8 ""))])
15363 (set (match_operand:DF 0 "register_operand" "")
15364 (float_truncate:DF (match_dup 7)))]
15365 "TARGET_USE_FANCY_MATH_387
15366 && flag_unsafe_math_optimizations"
15370 for (i=2; i<8; i++)
15371 operands[i] = gen_reg_rtx (XFmode);
15373 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15376 (define_expand "asinsf2"
15377 [(set (match_dup 2)
15378 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15379 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15380 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15381 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15382 (parallel [(set (match_dup 7)
15383 (unspec:XF [(match_dup 6) (match_dup 2)]
15385 (clobber (match_scratch:XF 8 ""))])
15386 (set (match_operand:SF 0 "register_operand" "")
15387 (float_truncate:SF (match_dup 7)))]
15388 "TARGET_USE_FANCY_MATH_387
15389 && flag_unsafe_math_optimizations"
15393 for (i=2; i<8; i++)
15394 operands[i] = gen_reg_rtx (XFmode);
15396 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15399 (define_expand "asinxf2"
15400 [(set (match_dup 2)
15401 (mult:XF (match_operand:XF 1 "register_operand" "")
15403 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15404 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15405 (parallel [(set (match_operand:XF 0 "register_operand" "")
15406 (unspec:XF [(match_dup 5) (match_dup 1)]
15408 (clobber (match_scratch:XF 6 ""))])]
15409 "TARGET_USE_FANCY_MATH_387
15410 && flag_unsafe_math_optimizations"
15414 for (i=2; i<6; i++)
15415 operands[i] = gen_reg_rtx (XFmode);
15417 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15420 (define_expand "acosdf2"
15421 [(set (match_dup 2)
15422 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15423 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15424 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15425 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15426 (parallel [(set (match_dup 7)
15427 (unspec:XF [(match_dup 2) (match_dup 6)]
15429 (clobber (match_scratch:XF 8 ""))])
15430 (set (match_operand:DF 0 "register_operand" "")
15431 (float_truncate:DF (match_dup 7)))]
15432 "TARGET_USE_FANCY_MATH_387
15433 && flag_unsafe_math_optimizations"
15437 for (i=2; i<8; i++)
15438 operands[i] = gen_reg_rtx (XFmode);
15440 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15443 (define_expand "acossf2"
15444 [(set (match_dup 2)
15445 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15446 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15447 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15448 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15449 (parallel [(set (match_dup 7)
15450 (unspec:XF [(match_dup 2) (match_dup 6)]
15452 (clobber (match_scratch:XF 8 ""))])
15453 (set (match_operand:SF 0 "register_operand" "")
15454 (float_truncate:SF (match_dup 7)))]
15455 "TARGET_USE_FANCY_MATH_387
15456 && flag_unsafe_math_optimizations"
15460 for (i=2; i<8; i++)
15461 operands[i] = gen_reg_rtx (XFmode);
15463 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15466 (define_expand "acosxf2"
15467 [(set (match_dup 2)
15468 (mult:XF (match_operand:XF 1 "register_operand" "")
15470 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15471 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15472 (parallel [(set (match_operand:XF 0 "register_operand" "")
15473 (unspec:XF [(match_dup 1) (match_dup 5)]
15475 (clobber (match_scratch:XF 6 ""))])]
15476 "TARGET_USE_FANCY_MATH_387
15477 && flag_unsafe_math_optimizations"
15481 for (i=2; i<6; i++)
15482 operands[i] = gen_reg_rtx (XFmode);
15484 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15487 (define_insn "fyl2x_xf3"
15488 [(set (match_operand:XF 0 "register_operand" "=f")
15489 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15490 (match_operand:XF 1 "register_operand" "u")]
15492 (clobber (match_scratch:XF 3 "=1"))]
15493 "TARGET_USE_FANCY_MATH_387
15494 && flag_unsafe_math_optimizations"
15496 [(set_attr "type" "fpspc")
15497 (set_attr "mode" "XF")])
15499 (define_expand "logsf2"
15500 [(set (match_dup 2)
15501 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15502 (parallel [(set (match_dup 4)
15503 (unspec:XF [(match_dup 2)
15504 (match_dup 3)] UNSPEC_FYL2X))
15505 (clobber (match_scratch:XF 5 ""))])
15506 (set (match_operand:SF 0 "register_operand" "")
15507 (float_truncate:SF (match_dup 4)))]
15508 "TARGET_USE_FANCY_MATH_387
15509 && flag_unsafe_math_optimizations"
15513 operands[2] = gen_reg_rtx (XFmode);
15514 operands[3] = gen_reg_rtx (XFmode);
15515 operands[4] = gen_reg_rtx (XFmode);
15517 temp = standard_80387_constant_rtx (4); /* fldln2 */
15518 emit_move_insn (operands[3], temp);
15521 (define_expand "logdf2"
15522 [(set (match_dup 2)
15523 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15524 (parallel [(set (match_dup 4)
15525 (unspec:XF [(match_dup 2)
15526 (match_dup 3)] UNSPEC_FYL2X))
15527 (clobber (match_scratch:XF 5 ""))])
15528 (set (match_operand:DF 0 "register_operand" "")
15529 (float_truncate:DF (match_dup 4)))]
15530 "TARGET_USE_FANCY_MATH_387
15531 && flag_unsafe_math_optimizations"
15535 operands[2] = gen_reg_rtx (XFmode);
15536 operands[3] = gen_reg_rtx (XFmode);
15537 operands[4] = gen_reg_rtx (XFmode);
15539 temp = standard_80387_constant_rtx (4); /* fldln2 */
15540 emit_move_insn (operands[3], temp);
15543 (define_expand "logxf2"
15544 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15545 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15546 (match_dup 2)] UNSPEC_FYL2X))
15547 (clobber (match_scratch:XF 3 ""))])]
15548 "TARGET_USE_FANCY_MATH_387
15549 && flag_unsafe_math_optimizations"
15553 operands[2] = gen_reg_rtx (XFmode);
15554 temp = standard_80387_constant_rtx (4); /* fldln2 */
15555 emit_move_insn (operands[2], temp);
15558 (define_expand "log10sf2"
15559 [(set (match_dup 2)
15560 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15561 (parallel [(set (match_dup 4)
15562 (unspec:XF [(match_dup 2)
15563 (match_dup 3)] UNSPEC_FYL2X))
15564 (clobber (match_scratch:XF 5 ""))])
15565 (set (match_operand:SF 0 "register_operand" "")
15566 (float_truncate:SF (match_dup 4)))]
15567 "TARGET_USE_FANCY_MATH_387
15568 && flag_unsafe_math_optimizations"
15572 operands[2] = gen_reg_rtx (XFmode);
15573 operands[3] = gen_reg_rtx (XFmode);
15574 operands[4] = gen_reg_rtx (XFmode);
15576 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15577 emit_move_insn (operands[3], temp);
15580 (define_expand "log10df2"
15581 [(set (match_dup 2)
15582 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15583 (parallel [(set (match_dup 4)
15584 (unspec:XF [(match_dup 2)
15585 (match_dup 3)] UNSPEC_FYL2X))
15586 (clobber (match_scratch:XF 5 ""))])
15587 (set (match_operand:DF 0 "register_operand" "")
15588 (float_truncate:DF (match_dup 4)))]
15589 "TARGET_USE_FANCY_MATH_387
15590 && flag_unsafe_math_optimizations"
15594 operands[2] = gen_reg_rtx (XFmode);
15595 operands[3] = gen_reg_rtx (XFmode);
15596 operands[4] = gen_reg_rtx (XFmode);
15598 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15599 emit_move_insn (operands[3], temp);
15602 (define_expand "log10xf2"
15603 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15604 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15605 (match_dup 2)] UNSPEC_FYL2X))
15606 (clobber (match_scratch:XF 3 ""))])]
15607 "TARGET_USE_FANCY_MATH_387
15608 && flag_unsafe_math_optimizations"
15612 operands[2] = gen_reg_rtx (XFmode);
15613 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15614 emit_move_insn (operands[2], temp);
15617 (define_expand "log2sf2"
15618 [(set (match_dup 2)
15619 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15620 (parallel [(set (match_dup 4)
15621 (unspec:XF [(match_dup 2)
15622 (match_dup 3)] UNSPEC_FYL2X))
15623 (clobber (match_scratch:XF 5 ""))])
15624 (set (match_operand:SF 0 "register_operand" "")
15625 (float_truncate:SF (match_dup 4)))]
15626 "TARGET_USE_FANCY_MATH_387
15627 && flag_unsafe_math_optimizations"
15629 operands[2] = gen_reg_rtx (XFmode);
15630 operands[3] = gen_reg_rtx (XFmode);
15631 operands[4] = gen_reg_rtx (XFmode);
15633 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15636 (define_expand "log2df2"
15637 [(set (match_dup 2)
15638 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15639 (parallel [(set (match_dup 4)
15640 (unspec:XF [(match_dup 2)
15641 (match_dup 3)] UNSPEC_FYL2X))
15642 (clobber (match_scratch:XF 5 ""))])
15643 (set (match_operand:DF 0 "register_operand" "")
15644 (float_truncate:DF (match_dup 4)))]
15645 "TARGET_USE_FANCY_MATH_387
15646 && flag_unsafe_math_optimizations"
15648 operands[2] = gen_reg_rtx (XFmode);
15649 operands[3] = gen_reg_rtx (XFmode);
15650 operands[4] = gen_reg_rtx (XFmode);
15652 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15655 (define_expand "log2xf2"
15656 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15657 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15658 (match_dup 2)] UNSPEC_FYL2X))
15659 (clobber (match_scratch:XF 3 ""))])]
15660 "TARGET_USE_FANCY_MATH_387
15661 && flag_unsafe_math_optimizations"
15663 operands[2] = gen_reg_rtx (XFmode);
15664 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15667 (define_insn "fyl2xp1_xf3"
15668 [(set (match_operand:XF 0 "register_operand" "=f")
15669 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15670 (match_operand:XF 1 "register_operand" "u")]
15672 (clobber (match_scratch:XF 3 "=1"))]
15673 "TARGET_USE_FANCY_MATH_387
15674 && flag_unsafe_math_optimizations"
15676 [(set_attr "type" "fpspc")
15677 (set_attr "mode" "XF")])
15679 (define_expand "log1psf2"
15680 [(use (match_operand:XF 0 "register_operand" ""))
15681 (use (match_operand:XF 1 "register_operand" ""))]
15682 "TARGET_USE_FANCY_MATH_387
15683 && flag_unsafe_math_optimizations"
15685 rtx op0 = gen_reg_rtx (XFmode);
15686 rtx op1 = gen_reg_rtx (XFmode);
15688 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15689 ix86_emit_i387_log1p (op0, op1);
15690 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
15694 (define_expand "log1pdf2"
15695 [(use (match_operand:XF 0 "register_operand" ""))
15696 (use (match_operand:XF 1 "register_operand" ""))]
15697 "TARGET_USE_FANCY_MATH_387
15698 && flag_unsafe_math_optimizations"
15700 rtx op0 = gen_reg_rtx (XFmode);
15701 rtx op1 = gen_reg_rtx (XFmode);
15703 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15704 ix86_emit_i387_log1p (op0, op1);
15705 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
15709 (define_expand "log1pxf2"
15710 [(use (match_operand:XF 0 "register_operand" ""))
15711 (use (match_operand:XF 1 "register_operand" ""))]
15712 "TARGET_USE_FANCY_MATH_387
15713 && flag_unsafe_math_optimizations"
15715 ix86_emit_i387_log1p (operands[0], operands[1]);
15719 (define_insn "*fxtractxf3"
15720 [(set (match_operand:XF 0 "register_operand" "=f")
15721 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15722 UNSPEC_XTRACT_FRACT))
15723 (set (match_operand:XF 1 "register_operand" "=u")
15724 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15725 "TARGET_USE_FANCY_MATH_387
15726 && flag_unsafe_math_optimizations"
15728 [(set_attr "type" "fpspc")
15729 (set_attr "mode" "XF")])
15731 (define_expand "logbsf2"
15732 [(set (match_dup 2)
15733 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15734 (parallel [(set (match_dup 3)
15735 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15737 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15738 (set (match_operand:SF 0 "register_operand" "")
15739 (float_truncate:SF (match_dup 4)))]
15740 "TARGET_USE_FANCY_MATH_387
15741 && flag_unsafe_math_optimizations"
15743 operands[2] = gen_reg_rtx (XFmode);
15744 operands[3] = gen_reg_rtx (XFmode);
15745 operands[4] = gen_reg_rtx (XFmode);
15748 (define_expand "logbdf2"
15749 [(set (match_dup 2)
15750 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15751 (parallel [(set (match_dup 3)
15752 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
15754 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
15755 (set (match_operand:DF 0 "register_operand" "")
15756 (float_truncate:DF (match_dup 4)))]
15757 "TARGET_USE_FANCY_MATH_387
15758 && flag_unsafe_math_optimizations"
15760 operands[2] = gen_reg_rtx (XFmode);
15761 operands[3] = gen_reg_rtx (XFmode);
15762 operands[4] = gen_reg_rtx (XFmode);
15765 (define_expand "logbxf2"
15766 [(parallel [(set (match_dup 2)
15767 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15768 UNSPEC_XTRACT_FRACT))
15769 (set (match_operand:XF 0 "register_operand" "")
15770 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
15771 "TARGET_USE_FANCY_MATH_387
15772 && flag_unsafe_math_optimizations"
15774 operands[2] = gen_reg_rtx (XFmode);
15777 (define_expand "ilogbsi2"
15778 [(parallel [(set (match_dup 2)
15779 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15780 UNSPEC_XTRACT_FRACT))
15781 (set (match_operand:XF 3 "register_operand" "")
15782 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
15783 (parallel [(set (match_operand:SI 0 "register_operand" "")
15784 (fix:SI (match_dup 3)))
15785 (clobber (reg:CC FLAGS_REG))])]
15786 "TARGET_USE_FANCY_MATH_387
15787 && flag_unsafe_math_optimizations"
15789 operands[2] = gen_reg_rtx (XFmode);
15790 operands[3] = gen_reg_rtx (XFmode);
15793 (define_insn "*f2xm1xf2"
15794 [(set (match_operand:XF 0 "register_operand" "=f")
15795 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15797 "TARGET_USE_FANCY_MATH_387
15798 && flag_unsafe_math_optimizations"
15800 [(set_attr "type" "fpspc")
15801 (set_attr "mode" "XF")])
15803 (define_insn "*fscalexf4"
15804 [(set (match_operand:XF 0 "register_operand" "=f")
15805 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15806 (match_operand:XF 3 "register_operand" "1")]
15807 UNSPEC_FSCALE_FRACT))
15808 (set (match_operand:XF 1 "register_operand" "=u")
15809 (unspec:XF [(match_dup 2) (match_dup 3)]
15810 UNSPEC_FSCALE_EXP))]
15811 "TARGET_USE_FANCY_MATH_387
15812 && flag_unsafe_math_optimizations"
15814 [(set_attr "type" "fpspc")
15815 (set_attr "mode" "XF")])
15817 (define_expand "expsf2"
15818 [(set (match_dup 2)
15819 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15820 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15821 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15822 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15823 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15824 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15825 (parallel [(set (match_dup 10)
15826 (unspec:XF [(match_dup 9) (match_dup 5)]
15827 UNSPEC_FSCALE_FRACT))
15828 (set (match_dup 11)
15829 (unspec:XF [(match_dup 9) (match_dup 5)]
15830 UNSPEC_FSCALE_EXP))])
15831 (set (match_operand:SF 0 "register_operand" "")
15832 (float_truncate:SF (match_dup 10)))]
15833 "TARGET_USE_FANCY_MATH_387
15834 && flag_unsafe_math_optimizations"
15839 for (i=2; i<12; i++)
15840 operands[i] = gen_reg_rtx (XFmode);
15841 temp = standard_80387_constant_rtx (5); /* fldl2e */
15842 emit_move_insn (operands[3], temp);
15843 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15846 (define_expand "expdf2"
15847 [(set (match_dup 2)
15848 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15849 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15850 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15851 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15852 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15853 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15854 (parallel [(set (match_dup 10)
15855 (unspec:XF [(match_dup 9) (match_dup 5)]
15856 UNSPEC_FSCALE_FRACT))
15857 (set (match_dup 11)
15858 (unspec:XF [(match_dup 9) (match_dup 5)]
15859 UNSPEC_FSCALE_EXP))])
15860 (set (match_operand:DF 0 "register_operand" "")
15861 (float_truncate:DF (match_dup 10)))]
15862 "TARGET_USE_FANCY_MATH_387
15863 && flag_unsafe_math_optimizations"
15868 for (i=2; i<12; i++)
15869 operands[i] = gen_reg_rtx (XFmode);
15870 temp = standard_80387_constant_rtx (5); /* fldl2e */
15871 emit_move_insn (operands[3], temp);
15872 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15875 (define_expand "expxf2"
15876 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15878 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15879 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15880 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15881 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15882 (parallel [(set (match_operand:XF 0 "register_operand" "")
15883 (unspec:XF [(match_dup 8) (match_dup 4)]
15884 UNSPEC_FSCALE_FRACT))
15886 (unspec:XF [(match_dup 8) (match_dup 4)]
15887 UNSPEC_FSCALE_EXP))])]
15888 "TARGET_USE_FANCY_MATH_387
15889 && flag_unsafe_math_optimizations"
15894 for (i=2; i<10; i++)
15895 operands[i] = gen_reg_rtx (XFmode);
15896 temp = standard_80387_constant_rtx (5); /* fldl2e */
15897 emit_move_insn (operands[2], temp);
15898 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15901 (define_expand "exp10sf2"
15902 [(set (match_dup 2)
15903 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15904 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15905 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15906 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15907 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15908 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15909 (parallel [(set (match_dup 10)
15910 (unspec:XF [(match_dup 9) (match_dup 5)]
15911 UNSPEC_FSCALE_FRACT))
15912 (set (match_dup 11)
15913 (unspec:XF [(match_dup 9) (match_dup 5)]
15914 UNSPEC_FSCALE_EXP))])
15915 (set (match_operand:SF 0 "register_operand" "")
15916 (float_truncate:SF (match_dup 10)))]
15917 "TARGET_USE_FANCY_MATH_387
15918 && flag_unsafe_math_optimizations"
15923 for (i=2; i<12; i++)
15924 operands[i] = gen_reg_rtx (XFmode);
15925 temp = standard_80387_constant_rtx (6); /* fldl2t */
15926 emit_move_insn (operands[3], temp);
15927 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15930 (define_expand "exp10df2"
15931 [(set (match_dup 2)
15932 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15933 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15934 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15935 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15936 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15937 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15938 (parallel [(set (match_dup 10)
15939 (unspec:XF [(match_dup 9) (match_dup 5)]
15940 UNSPEC_FSCALE_FRACT))
15941 (set (match_dup 11)
15942 (unspec:XF [(match_dup 9) (match_dup 5)]
15943 UNSPEC_FSCALE_EXP))])
15944 (set (match_operand:DF 0 "register_operand" "")
15945 (float_truncate:DF (match_dup 10)))]
15946 "TARGET_USE_FANCY_MATH_387
15947 && flag_unsafe_math_optimizations"
15952 for (i=2; i<12; i++)
15953 operands[i] = gen_reg_rtx (XFmode);
15954 temp = standard_80387_constant_rtx (6); /* fldl2t */
15955 emit_move_insn (operands[3], temp);
15956 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15959 (define_expand "exp10xf2"
15960 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15962 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15963 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15964 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15965 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15966 (parallel [(set (match_operand:XF 0 "register_operand" "")
15967 (unspec:XF [(match_dup 8) (match_dup 4)]
15968 UNSPEC_FSCALE_FRACT))
15970 (unspec:XF [(match_dup 8) (match_dup 4)]
15971 UNSPEC_FSCALE_EXP))])]
15972 "TARGET_USE_FANCY_MATH_387
15973 && flag_unsafe_math_optimizations"
15978 for (i=2; i<10; i++)
15979 operands[i] = gen_reg_rtx (XFmode);
15980 temp = standard_80387_constant_rtx (6); /* fldl2t */
15981 emit_move_insn (operands[2], temp);
15982 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15985 (define_expand "exp2sf2"
15986 [(set (match_dup 2)
15987 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15988 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
15989 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
15990 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
15991 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
15992 (parallel [(set (match_dup 8)
15993 (unspec:XF [(match_dup 7) (match_dup 3)]
15994 UNSPEC_FSCALE_FRACT))
15996 (unspec:XF [(match_dup 7) (match_dup 3)]
15997 UNSPEC_FSCALE_EXP))])
15998 (set (match_operand:SF 0 "register_operand" "")
15999 (float_truncate:SF (match_dup 8)))]
16000 "TARGET_USE_FANCY_MATH_387
16001 && flag_unsafe_math_optimizations"
16005 for (i=2; i<10; i++)
16006 operands[i] = gen_reg_rtx (XFmode);
16007 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16010 (define_expand "exp2df2"
16011 [(set (match_dup 2)
16012 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16013 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16014 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16015 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16016 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16017 (parallel [(set (match_dup 8)
16018 (unspec:XF [(match_dup 7) (match_dup 3)]
16019 UNSPEC_FSCALE_FRACT))
16021 (unspec:XF [(match_dup 7) (match_dup 3)]
16022 UNSPEC_FSCALE_EXP))])
16023 (set (match_operand:DF 0 "register_operand" "")
16024 (float_truncate:DF (match_dup 8)))]
16025 "TARGET_USE_FANCY_MATH_387
16026 && flag_unsafe_math_optimizations"
16030 for (i=2; i<10; i++)
16031 operands[i] = gen_reg_rtx (XFmode);
16032 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16035 (define_expand "exp2xf2"
16036 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16037 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16038 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16039 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16040 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16041 (parallel [(set (match_operand:XF 0 "register_operand" "")
16042 (unspec:XF [(match_dup 7) (match_dup 3)]
16043 UNSPEC_FSCALE_FRACT))
16045 (unspec:XF [(match_dup 7) (match_dup 3)]
16046 UNSPEC_FSCALE_EXP))])]
16047 "TARGET_USE_FANCY_MATH_387
16048 && flag_unsafe_math_optimizations"
16052 for (i=2; i<9; i++)
16053 operands[i] = gen_reg_rtx (XFmode);
16054 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16057 (define_expand "expm1df2"
16058 [(set (match_dup 2)
16059 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16060 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16061 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16062 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16063 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16064 (parallel [(set (match_dup 8)
16065 (unspec:XF [(match_dup 7) (match_dup 5)]
16066 UNSPEC_FSCALE_FRACT))
16068 (unspec:XF [(match_dup 7) (match_dup 5)]
16069 UNSPEC_FSCALE_EXP))])
16070 (parallel [(set (match_dup 11)
16071 (unspec:XF [(match_dup 10) (match_dup 9)]
16072 UNSPEC_FSCALE_FRACT))
16073 (set (match_dup 12)
16074 (unspec:XF [(match_dup 10) (match_dup 9)]
16075 UNSPEC_FSCALE_EXP))])
16076 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16077 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16078 (set (match_operand:DF 0 "register_operand" "")
16079 (float_truncate:DF (match_dup 14)))]
16080 "TARGET_USE_FANCY_MATH_387
16081 && flag_unsafe_math_optimizations"
16086 for (i=2; i<15; i++)
16087 operands[i] = gen_reg_rtx (XFmode);
16088 temp = standard_80387_constant_rtx (5); /* fldl2e */
16089 emit_move_insn (operands[3], temp);
16090 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16093 (define_expand "expm1sf2"
16094 [(set (match_dup 2)
16095 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16096 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16097 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16098 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16099 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16100 (parallel [(set (match_dup 8)
16101 (unspec:XF [(match_dup 7) (match_dup 5)]
16102 UNSPEC_FSCALE_FRACT))
16104 (unspec:XF [(match_dup 7) (match_dup 5)]
16105 UNSPEC_FSCALE_EXP))])
16106 (parallel [(set (match_dup 11)
16107 (unspec:XF [(match_dup 10) (match_dup 9)]
16108 UNSPEC_FSCALE_FRACT))
16109 (set (match_dup 12)
16110 (unspec:XF [(match_dup 10) (match_dup 9)]
16111 UNSPEC_FSCALE_EXP))])
16112 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16113 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16114 (set (match_operand:SF 0 "register_operand" "")
16115 (float_truncate:SF (match_dup 14)))]
16116 "TARGET_USE_FANCY_MATH_387
16117 && flag_unsafe_math_optimizations"
16122 for (i=2; i<15; i++)
16123 operands[i] = gen_reg_rtx (XFmode);
16124 temp = standard_80387_constant_rtx (5); /* fldl2e */
16125 emit_move_insn (operands[3], temp);
16126 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16129 (define_expand "expm1xf2"
16130 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16132 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16133 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16134 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16135 (parallel [(set (match_dup 7)
16136 (unspec:XF [(match_dup 6) (match_dup 4)]
16137 UNSPEC_FSCALE_FRACT))
16139 (unspec:XF [(match_dup 6) (match_dup 4)]
16140 UNSPEC_FSCALE_EXP))])
16141 (parallel [(set (match_dup 10)
16142 (unspec:XF [(match_dup 9) (match_dup 8)]
16143 UNSPEC_FSCALE_FRACT))
16144 (set (match_dup 11)
16145 (unspec:XF [(match_dup 9) (match_dup 8)]
16146 UNSPEC_FSCALE_EXP))])
16147 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16148 (set (match_operand:XF 0 "register_operand" "")
16149 (plus:XF (match_dup 12) (match_dup 7)))]
16150 "TARGET_USE_FANCY_MATH_387
16151 && flag_unsafe_math_optimizations"
16156 for (i=2; i<13; i++)
16157 operands[i] = gen_reg_rtx (XFmode);
16158 temp = standard_80387_constant_rtx (5); /* fldl2e */
16159 emit_move_insn (operands[2], temp);
16160 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16164 (define_insn "frndintxf2"
16165 [(set (match_operand:XF 0 "register_operand" "=f")
16166 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16168 "TARGET_USE_FANCY_MATH_387
16169 && flag_unsafe_math_optimizations"
16171 [(set_attr "type" "fpspc")
16172 (set_attr "mode" "XF")])
16174 (define_expand "rintdf2"
16175 [(use (match_operand:DF 0 "register_operand" ""))
16176 (use (match_operand:DF 1 "register_operand" ""))]
16177 "TARGET_USE_FANCY_MATH_387
16178 && flag_unsafe_math_optimizations"
16180 rtx op0 = gen_reg_rtx (XFmode);
16181 rtx op1 = gen_reg_rtx (XFmode);
16183 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16184 emit_insn (gen_frndintxf2 (op0, op1));
16186 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16190 (define_expand "rintsf2"
16191 [(use (match_operand:SF 0 "register_operand" ""))
16192 (use (match_operand:SF 1 "register_operand" ""))]
16193 "TARGET_USE_FANCY_MATH_387
16194 && flag_unsafe_math_optimizations"
16196 rtx op0 = gen_reg_rtx (XFmode);
16197 rtx op1 = gen_reg_rtx (XFmode);
16199 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16200 emit_insn (gen_frndintxf2 (op0, op1));
16202 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16206 (define_expand "rintxf2"
16207 [(use (match_operand:XF 0 "register_operand" ""))
16208 (use (match_operand:XF 1 "register_operand" ""))]
16209 "TARGET_USE_FANCY_MATH_387
16210 && flag_unsafe_math_optimizations"
16212 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16216 (define_insn "frndintxf2_floor"
16217 [(set (match_operand:XF 0 "register_operand" "=f")
16218 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16219 UNSPEC_FRNDINT_FLOOR))
16220 (use (match_operand:HI 2 "memory_operand" "m"))
16221 (use (match_operand:HI 3 "memory_operand" "m"))]
16222 "TARGET_USE_FANCY_MATH_387
16223 && flag_unsafe_math_optimizations"
16224 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16225 [(set_attr "type" "frndint")
16226 (set_attr "i387_cw" "floor")
16227 (set_attr "mode" "XF")])
16229 (define_expand "floordf2"
16230 [(use (match_operand:DF 0 "register_operand" ""))
16231 (use (match_operand:DF 1 "register_operand" ""))]
16232 "TARGET_USE_FANCY_MATH_387
16233 && flag_unsafe_math_optimizations"
16235 rtx op0 = gen_reg_rtx (XFmode);
16236 rtx op1 = gen_reg_rtx (XFmode);
16237 rtx op2 = assign_386_stack_local (HImode, 1);
16238 rtx op3 = assign_386_stack_local (HImode, 2);
16240 ix86_optimize_mode_switching = 1;
16242 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16243 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16245 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16249 (define_expand "floorsf2"
16250 [(use (match_operand:SF 0 "register_operand" ""))
16251 (use (match_operand:SF 1 "register_operand" ""))]
16252 "TARGET_USE_FANCY_MATH_387
16253 && flag_unsafe_math_optimizations"
16255 rtx op0 = gen_reg_rtx (XFmode);
16256 rtx op1 = gen_reg_rtx (XFmode);
16257 rtx op2 = assign_386_stack_local (HImode, 1);
16258 rtx op3 = assign_386_stack_local (HImode, 2);
16260 ix86_optimize_mode_switching = 1;
16262 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16263 emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
16265 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16269 (define_expand "floorxf2"
16270 [(use (match_operand:XF 0 "register_operand" ""))
16271 (use (match_operand:XF 1 "register_operand" ""))]
16272 "TARGET_USE_FANCY_MATH_387
16273 && flag_unsafe_math_optimizations"
16275 rtx op2 = assign_386_stack_local (HImode, 1);
16276 rtx op3 = assign_386_stack_local (HImode, 2);
16278 ix86_optimize_mode_switching = 1;
16280 emit_insn (gen_frndintxf2_floor (operands[0], operands[1], op2, op3));
16284 (define_insn "frndintxf2_ceil"
16285 [(set (match_operand:XF 0 "register_operand" "=f")
16286 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16287 UNSPEC_FRNDINT_CEIL))
16288 (use (match_operand:HI 2 "memory_operand" "m"))
16289 (use (match_operand:HI 3 "memory_operand" "m"))]
16290 "TARGET_USE_FANCY_MATH_387
16291 && flag_unsafe_math_optimizations"
16292 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16293 [(set_attr "type" "frndint")
16294 (set_attr "i387_cw" "ceil")
16295 (set_attr "mode" "XF")])
16297 (define_expand "ceildf2"
16298 [(use (match_operand:DF 0 "register_operand" ""))
16299 (use (match_operand:DF 1 "register_operand" ""))]
16300 "TARGET_USE_FANCY_MATH_387
16301 && flag_unsafe_math_optimizations"
16303 rtx op0 = gen_reg_rtx (XFmode);
16304 rtx op1 = gen_reg_rtx (XFmode);
16305 rtx op2 = assign_386_stack_local (HImode, 1);
16306 rtx op3 = assign_386_stack_local (HImode, 2);
16308 ix86_optimize_mode_switching = 1;
16310 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16311 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16313 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16317 (define_expand "ceilsf2"
16318 [(use (match_operand:SF 0 "register_operand" ""))
16319 (use (match_operand:SF 1 "register_operand" ""))]
16320 "TARGET_USE_FANCY_MATH_387
16321 && flag_unsafe_math_optimizations"
16323 rtx op0 = gen_reg_rtx (XFmode);
16324 rtx op1 = gen_reg_rtx (XFmode);
16325 rtx op2 = assign_386_stack_local (HImode, 1);
16326 rtx op3 = assign_386_stack_local (HImode, 2);
16328 ix86_optimize_mode_switching = 1;
16330 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16331 emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
16333 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16337 (define_expand "ceilxf2"
16338 [(use (match_operand:XF 0 "register_operand" ""))
16339 (use (match_operand:XF 1 "register_operand" ""))]
16340 "TARGET_USE_FANCY_MATH_387
16341 && flag_unsafe_math_optimizations"
16343 rtx op2 = assign_386_stack_local (HImode, 1);
16344 rtx op3 = assign_386_stack_local (HImode, 2);
16346 ix86_optimize_mode_switching = 1;
16348 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1], op2, op3));
16352 (define_insn "frndintxf2_trunc"
16353 [(set (match_operand:XF 0 "register_operand" "=f")
16354 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16355 UNSPEC_FRNDINT_TRUNC))
16356 (use (match_operand:HI 2 "memory_operand" "m"))
16357 (use (match_operand:HI 3 "memory_operand" "m"))]
16358 "TARGET_USE_FANCY_MATH_387
16359 && flag_unsafe_math_optimizations"
16360 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16361 [(set_attr "type" "frndint")
16362 (set_attr "i387_cw" "trunc")
16363 (set_attr "mode" "XF")])
16365 (define_expand "btruncdf2"
16366 [(use (match_operand:DF 0 "register_operand" ""))
16367 (use (match_operand:DF 1 "register_operand" ""))]
16368 "TARGET_USE_FANCY_MATH_387
16369 && flag_unsafe_math_optimizations"
16371 rtx op0 = gen_reg_rtx (XFmode);
16372 rtx op1 = gen_reg_rtx (XFmode);
16373 rtx op2 = assign_386_stack_local (HImode, 1);
16374 rtx op3 = assign_386_stack_local (HImode, 2);
16376 ix86_optimize_mode_switching = 1;
16378 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16379 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16381 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16385 (define_expand "btruncsf2"
16386 [(use (match_operand:SF 0 "register_operand" ""))
16387 (use (match_operand:SF 1 "register_operand" ""))]
16388 "TARGET_USE_FANCY_MATH_387
16389 && flag_unsafe_math_optimizations"
16391 rtx op0 = gen_reg_rtx (XFmode);
16392 rtx op1 = gen_reg_rtx (XFmode);
16393 rtx op2 = assign_386_stack_local (HImode, 1);
16394 rtx op3 = assign_386_stack_local (HImode, 2);
16396 ix86_optimize_mode_switching = 1;
16398 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16399 emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
16401 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16405 (define_expand "btruncxf2"
16406 [(use (match_operand:XF 0 "register_operand" ""))
16407 (use (match_operand:XF 1 "register_operand" ""))]
16408 "TARGET_USE_FANCY_MATH_387
16409 && flag_unsafe_math_optimizations"
16411 rtx op2 = assign_386_stack_local (HImode, 1);
16412 rtx op3 = assign_386_stack_local (HImode, 2);
16414 ix86_optimize_mode_switching = 1;
16416 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1], op2, op3));
16420 (define_insn "frndintxf2_mask_pm"
16421 [(set (match_operand:XF 0 "register_operand" "=f")
16422 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16423 UNSPEC_FRNDINT_MASK_PM))
16424 (use (match_operand:HI 2 "memory_operand" "m"))
16425 (use (match_operand:HI 3 "memory_operand" "m"))]
16426 "TARGET_USE_FANCY_MATH_387
16427 && flag_unsafe_math_optimizations"
16428 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
16429 [(set_attr "type" "frndint")
16430 (set_attr "i387_cw" "mask_pm")
16431 (set_attr "mode" "XF")])
16433 (define_expand "nearbyintdf2"
16434 [(use (match_operand:DF 0 "register_operand" ""))
16435 (use (match_operand:DF 1 "register_operand" ""))]
16436 "TARGET_USE_FANCY_MATH_387
16437 && flag_unsafe_math_optimizations"
16439 rtx op0 = gen_reg_rtx (XFmode);
16440 rtx op1 = gen_reg_rtx (XFmode);
16441 rtx op2 = assign_386_stack_local (HImode, 1);
16442 rtx op3 = assign_386_stack_local (HImode, 2);
16444 ix86_optimize_mode_switching = 1;
16446 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16447 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16449 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16453 (define_expand "nearbyintsf2"
16454 [(use (match_operand:SF 0 "register_operand" ""))
16455 (use (match_operand:SF 1 "register_operand" ""))]
16456 "TARGET_USE_FANCY_MATH_387
16457 && flag_unsafe_math_optimizations"
16459 rtx op0 = gen_reg_rtx (XFmode);
16460 rtx op1 = gen_reg_rtx (XFmode);
16461 rtx op2 = assign_386_stack_local (HImode, 1);
16462 rtx op3 = assign_386_stack_local (HImode, 2);
16464 ix86_optimize_mode_switching = 1;
16466 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16467 emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
16469 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16473 (define_expand "nearbyintxf2"
16474 [(use (match_operand:XF 0 "register_operand" ""))
16475 (use (match_operand:XF 1 "register_operand" ""))]
16476 "TARGET_USE_FANCY_MATH_387
16477 && flag_unsafe_math_optimizations"
16479 rtx op2 = assign_386_stack_local (HImode, 1);
16480 rtx op3 = assign_386_stack_local (HImode, 2);
16482 ix86_optimize_mode_switching = 1;
16484 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1],
16490 ;; Block operation instructions
16493 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
16496 [(set_attr "type" "cld")])
16498 (define_expand "movmemsi"
16499 [(use (match_operand:BLK 0 "memory_operand" ""))
16500 (use (match_operand:BLK 1 "memory_operand" ""))
16501 (use (match_operand:SI 2 "nonmemory_operand" ""))
16502 (use (match_operand:SI 3 "const_int_operand" ""))]
16505 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16511 (define_expand "movmemdi"
16512 [(use (match_operand:BLK 0 "memory_operand" ""))
16513 (use (match_operand:BLK 1 "memory_operand" ""))
16514 (use (match_operand:DI 2 "nonmemory_operand" ""))
16515 (use (match_operand:DI 3 "const_int_operand" ""))]
16518 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
16524 ;; Most CPUs don't like single string operations
16525 ;; Handle this case here to simplify previous expander.
16527 (define_expand "strmov"
16528 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
16529 (set (match_operand 1 "memory_operand" "") (match_dup 4))
16530 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
16531 (clobber (reg:CC FLAGS_REG))])
16532 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
16533 (clobber (reg:CC FLAGS_REG))])]
16536 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
16538 /* If .md ever supports :P for Pmode, these can be directly
16539 in the pattern above. */
16540 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
16541 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
16543 if (TARGET_SINGLE_STRINGOP || optimize_size)
16545 emit_insn (gen_strmov_singleop (operands[0], operands[1],
16546 operands[2], operands[3],
16547 operands[5], operands[6]));
16551 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
16554 (define_expand "strmov_singleop"
16555 [(parallel [(set (match_operand 1 "memory_operand" "")
16556 (match_operand 3 "memory_operand" ""))
16557 (set (match_operand 0 "register_operand" "")
16558 (match_operand 4 "" ""))
16559 (set (match_operand 2 "register_operand" "")
16560 (match_operand 5 "" ""))
16561 (use (reg:SI DIRFLAG_REG))])]
16562 "TARGET_SINGLE_STRINGOP || optimize_size"
16565 (define_insn "*strmovdi_rex_1"
16566 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16567 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16568 (set (match_operand:DI 0 "register_operand" "=D")
16569 (plus:DI (match_dup 2)
16571 (set (match_operand:DI 1 "register_operand" "=S")
16572 (plus:DI (match_dup 3)
16574 (use (reg:SI DIRFLAG_REG))]
16575 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16577 [(set_attr "type" "str")
16578 (set_attr "mode" "DI")
16579 (set_attr "memory" "both")])
16581 (define_insn "*strmovsi_1"
16582 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16583 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16584 (set (match_operand:SI 0 "register_operand" "=D")
16585 (plus:SI (match_dup 2)
16587 (set (match_operand:SI 1 "register_operand" "=S")
16588 (plus:SI (match_dup 3)
16590 (use (reg:SI DIRFLAG_REG))]
16591 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16593 [(set_attr "type" "str")
16594 (set_attr "mode" "SI")
16595 (set_attr "memory" "both")])
16597 (define_insn "*strmovsi_rex_1"
16598 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16599 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16600 (set (match_operand:DI 0 "register_operand" "=D")
16601 (plus:DI (match_dup 2)
16603 (set (match_operand:DI 1 "register_operand" "=S")
16604 (plus:DI (match_dup 3)
16606 (use (reg:SI DIRFLAG_REG))]
16607 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16609 [(set_attr "type" "str")
16610 (set_attr "mode" "SI")
16611 (set_attr "memory" "both")])
16613 (define_insn "*strmovhi_1"
16614 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16615 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16616 (set (match_operand:SI 0 "register_operand" "=D")
16617 (plus:SI (match_dup 2)
16619 (set (match_operand:SI 1 "register_operand" "=S")
16620 (plus:SI (match_dup 3)
16622 (use (reg:SI DIRFLAG_REG))]
16623 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16625 [(set_attr "type" "str")
16626 (set_attr "memory" "both")
16627 (set_attr "mode" "HI")])
16629 (define_insn "*strmovhi_rex_1"
16630 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16631 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16632 (set (match_operand:DI 0 "register_operand" "=D")
16633 (plus:DI (match_dup 2)
16635 (set (match_operand:DI 1 "register_operand" "=S")
16636 (plus:DI (match_dup 3)
16638 (use (reg:SI DIRFLAG_REG))]
16639 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16641 [(set_attr "type" "str")
16642 (set_attr "memory" "both")
16643 (set_attr "mode" "HI")])
16645 (define_insn "*strmovqi_1"
16646 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16647 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16648 (set (match_operand:SI 0 "register_operand" "=D")
16649 (plus:SI (match_dup 2)
16651 (set (match_operand:SI 1 "register_operand" "=S")
16652 (plus:SI (match_dup 3)
16654 (use (reg:SI DIRFLAG_REG))]
16655 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16657 [(set_attr "type" "str")
16658 (set_attr "memory" "both")
16659 (set_attr "mode" "QI")])
16661 (define_insn "*strmovqi_rex_1"
16662 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16663 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16664 (set (match_operand:DI 0 "register_operand" "=D")
16665 (plus:DI (match_dup 2)
16667 (set (match_operand:DI 1 "register_operand" "=S")
16668 (plus:DI (match_dup 3)
16670 (use (reg:SI DIRFLAG_REG))]
16671 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16673 [(set_attr "type" "str")
16674 (set_attr "memory" "both")
16675 (set_attr "mode" "QI")])
16677 (define_expand "rep_mov"
16678 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
16679 (set (match_operand 0 "register_operand" "")
16680 (match_operand 5 "" ""))
16681 (set (match_operand 2 "register_operand" "")
16682 (match_operand 6 "" ""))
16683 (set (match_operand 1 "memory_operand" "")
16684 (match_operand 3 "memory_operand" ""))
16685 (use (match_dup 4))
16686 (use (reg:SI DIRFLAG_REG))])]
16690 (define_insn "*rep_movdi_rex64"
16691 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16692 (set (match_operand:DI 0 "register_operand" "=D")
16693 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16695 (match_operand:DI 3 "register_operand" "0")))
16696 (set (match_operand:DI 1 "register_operand" "=S")
16697 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16698 (match_operand:DI 4 "register_operand" "1")))
16699 (set (mem:BLK (match_dup 3))
16700 (mem:BLK (match_dup 4)))
16701 (use (match_dup 5))
16702 (use (reg:SI DIRFLAG_REG))]
16704 "{rep\;movsq|rep movsq}"
16705 [(set_attr "type" "str")
16706 (set_attr "prefix_rep" "1")
16707 (set_attr "memory" "both")
16708 (set_attr "mode" "DI")])
16710 (define_insn "*rep_movsi"
16711 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16712 (set (match_operand:SI 0 "register_operand" "=D")
16713 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16715 (match_operand:SI 3 "register_operand" "0")))
16716 (set (match_operand:SI 1 "register_operand" "=S")
16717 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16718 (match_operand:SI 4 "register_operand" "1")))
16719 (set (mem:BLK (match_dup 3))
16720 (mem:BLK (match_dup 4)))
16721 (use (match_dup 5))
16722 (use (reg:SI DIRFLAG_REG))]
16724 "{rep\;movsl|rep movsd}"
16725 [(set_attr "type" "str")
16726 (set_attr "prefix_rep" "1")
16727 (set_attr "memory" "both")
16728 (set_attr "mode" "SI")])
16730 (define_insn "*rep_movsi_rex64"
16731 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16732 (set (match_operand:DI 0 "register_operand" "=D")
16733 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16735 (match_operand:DI 3 "register_operand" "0")))
16736 (set (match_operand:DI 1 "register_operand" "=S")
16737 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16738 (match_operand:DI 4 "register_operand" "1")))
16739 (set (mem:BLK (match_dup 3))
16740 (mem:BLK (match_dup 4)))
16741 (use (match_dup 5))
16742 (use (reg:SI DIRFLAG_REG))]
16744 "{rep\;movsl|rep movsd}"
16745 [(set_attr "type" "str")
16746 (set_attr "prefix_rep" "1")
16747 (set_attr "memory" "both")
16748 (set_attr "mode" "SI")])
16750 (define_insn "*rep_movqi"
16751 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16752 (set (match_operand:SI 0 "register_operand" "=D")
16753 (plus:SI (match_operand:SI 3 "register_operand" "0")
16754 (match_operand:SI 5 "register_operand" "2")))
16755 (set (match_operand:SI 1 "register_operand" "=S")
16756 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16757 (set (mem:BLK (match_dup 3))
16758 (mem:BLK (match_dup 4)))
16759 (use (match_dup 5))
16760 (use (reg:SI DIRFLAG_REG))]
16762 "{rep\;movsb|rep movsb}"
16763 [(set_attr "type" "str")
16764 (set_attr "prefix_rep" "1")
16765 (set_attr "memory" "both")
16766 (set_attr "mode" "SI")])
16768 (define_insn "*rep_movqi_rex64"
16769 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16770 (set (match_operand:DI 0 "register_operand" "=D")
16771 (plus:DI (match_operand:DI 3 "register_operand" "0")
16772 (match_operand:DI 5 "register_operand" "2")))
16773 (set (match_operand:DI 1 "register_operand" "=S")
16774 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16775 (set (mem:BLK (match_dup 3))
16776 (mem:BLK (match_dup 4)))
16777 (use (match_dup 5))
16778 (use (reg:SI DIRFLAG_REG))]
16780 "{rep\;movsb|rep movsb}"
16781 [(set_attr "type" "str")
16782 (set_attr "prefix_rep" "1")
16783 (set_attr "memory" "both")
16784 (set_attr "mode" "SI")])
16786 (define_expand "clrmemsi"
16787 [(use (match_operand:BLK 0 "memory_operand" ""))
16788 (use (match_operand:SI 1 "nonmemory_operand" ""))
16789 (use (match_operand 2 "const_int_operand" ""))]
16792 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16798 (define_expand "clrmemdi"
16799 [(use (match_operand:BLK 0 "memory_operand" ""))
16800 (use (match_operand:DI 1 "nonmemory_operand" ""))
16801 (use (match_operand 2 "const_int_operand" ""))]
16804 if (ix86_expand_clrmem (operands[0], operands[1], operands[2]))
16810 ;; Most CPUs don't like single string operations
16811 ;; Handle this case here to simplify previous expander.
16813 (define_expand "strset"
16814 [(set (match_operand 1 "memory_operand" "")
16815 (match_operand 2 "register_operand" ""))
16816 (parallel [(set (match_operand 0 "register_operand" "")
16818 (clobber (reg:CC FLAGS_REG))])]
16821 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
16822 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
16824 /* If .md ever supports :P for Pmode, this can be directly
16825 in the pattern above. */
16826 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
16827 GEN_INT (GET_MODE_SIZE (GET_MODE
16829 if (TARGET_SINGLE_STRINGOP || optimize_size)
16831 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
16837 (define_expand "strset_singleop"
16838 [(parallel [(set (match_operand 1 "memory_operand" "")
16839 (match_operand 2 "register_operand" ""))
16840 (set (match_operand 0 "register_operand" "")
16841 (match_operand 3 "" ""))
16842 (use (reg:SI DIRFLAG_REG))])]
16843 "TARGET_SINGLE_STRINGOP || optimize_size"
16846 (define_insn "*strsetdi_rex_1"
16847 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
16848 (match_operand:DI 2 "register_operand" "a"))
16849 (set (match_operand:DI 0 "register_operand" "=D")
16850 (plus:DI (match_dup 1)
16852 (use (reg:SI DIRFLAG_REG))]
16853 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16855 [(set_attr "type" "str")
16856 (set_attr "memory" "store")
16857 (set_attr "mode" "DI")])
16859 (define_insn "*strsetsi_1"
16860 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16861 (match_operand:SI 2 "register_operand" "a"))
16862 (set (match_operand:SI 0 "register_operand" "=D")
16863 (plus:SI (match_dup 1)
16865 (use (reg:SI DIRFLAG_REG))]
16866 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16868 [(set_attr "type" "str")
16869 (set_attr "memory" "store")
16870 (set_attr "mode" "SI")])
16872 (define_insn "*strsetsi_rex_1"
16873 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16874 (match_operand:SI 2 "register_operand" "a"))
16875 (set (match_operand:DI 0 "register_operand" "=D")
16876 (plus:DI (match_dup 1)
16878 (use (reg:SI DIRFLAG_REG))]
16879 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16881 [(set_attr "type" "str")
16882 (set_attr "memory" "store")
16883 (set_attr "mode" "SI")])
16885 (define_insn "*strsethi_1"
16886 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16887 (match_operand:HI 2 "register_operand" "a"))
16888 (set (match_operand:SI 0 "register_operand" "=D")
16889 (plus:SI (match_dup 1)
16891 (use (reg:SI DIRFLAG_REG))]
16892 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16894 [(set_attr "type" "str")
16895 (set_attr "memory" "store")
16896 (set_attr "mode" "HI")])
16898 (define_insn "*strsethi_rex_1"
16899 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16900 (match_operand:HI 2 "register_operand" "a"))
16901 (set (match_operand:DI 0 "register_operand" "=D")
16902 (plus:DI (match_dup 1)
16904 (use (reg:SI DIRFLAG_REG))]
16905 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16907 [(set_attr "type" "str")
16908 (set_attr "memory" "store")
16909 (set_attr "mode" "HI")])
16911 (define_insn "*strsetqi_1"
16912 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16913 (match_operand:QI 2 "register_operand" "a"))
16914 (set (match_operand:SI 0 "register_operand" "=D")
16915 (plus:SI (match_dup 1)
16917 (use (reg:SI DIRFLAG_REG))]
16918 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16920 [(set_attr "type" "str")
16921 (set_attr "memory" "store")
16922 (set_attr "mode" "QI")])
16924 (define_insn "*strsetqi_rex_1"
16925 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16926 (match_operand:QI 2 "register_operand" "a"))
16927 (set (match_operand:DI 0 "register_operand" "=D")
16928 (plus:DI (match_dup 1)
16930 (use (reg:SI DIRFLAG_REG))]
16931 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16933 [(set_attr "type" "str")
16934 (set_attr "memory" "store")
16935 (set_attr "mode" "QI")])
16937 (define_expand "rep_stos"
16938 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
16939 (set (match_operand 0 "register_operand" "")
16940 (match_operand 4 "" ""))
16941 (set (match_operand 2 "memory_operand" "") (const_int 0))
16942 (use (match_operand 3 "register_operand" ""))
16943 (use (match_dup 1))
16944 (use (reg:SI DIRFLAG_REG))])]
16948 (define_insn "*rep_stosdi_rex64"
16949 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16950 (set (match_operand:DI 0 "register_operand" "=D")
16951 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16953 (match_operand:DI 3 "register_operand" "0")))
16954 (set (mem:BLK (match_dup 3))
16956 (use (match_operand:DI 2 "register_operand" "a"))
16957 (use (match_dup 4))
16958 (use (reg:SI DIRFLAG_REG))]
16960 "{rep\;stosq|rep stosq}"
16961 [(set_attr "type" "str")
16962 (set_attr "prefix_rep" "1")
16963 (set_attr "memory" "store")
16964 (set_attr "mode" "DI")])
16966 (define_insn "*rep_stossi"
16967 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16968 (set (match_operand:SI 0 "register_operand" "=D")
16969 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16971 (match_operand:SI 3 "register_operand" "0")))
16972 (set (mem:BLK (match_dup 3))
16974 (use (match_operand:SI 2 "register_operand" "a"))
16975 (use (match_dup 4))
16976 (use (reg:SI DIRFLAG_REG))]
16978 "{rep\;stosl|rep stosd}"
16979 [(set_attr "type" "str")
16980 (set_attr "prefix_rep" "1")
16981 (set_attr "memory" "store")
16982 (set_attr "mode" "SI")])
16984 (define_insn "*rep_stossi_rex64"
16985 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16986 (set (match_operand:DI 0 "register_operand" "=D")
16987 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16989 (match_operand:DI 3 "register_operand" "0")))
16990 (set (mem:BLK (match_dup 3))
16992 (use (match_operand:SI 2 "register_operand" "a"))
16993 (use (match_dup 4))
16994 (use (reg:SI DIRFLAG_REG))]
16996 "{rep\;stosl|rep stosd}"
16997 [(set_attr "type" "str")
16998 (set_attr "prefix_rep" "1")
16999 (set_attr "memory" "store")
17000 (set_attr "mode" "SI")])
17002 (define_insn "*rep_stosqi"
17003 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17004 (set (match_operand:SI 0 "register_operand" "=D")
17005 (plus:SI (match_operand:SI 3 "register_operand" "0")
17006 (match_operand:SI 4 "register_operand" "1")))
17007 (set (mem:BLK (match_dup 3))
17009 (use (match_operand:QI 2 "register_operand" "a"))
17010 (use (match_dup 4))
17011 (use (reg:SI DIRFLAG_REG))]
17013 "{rep\;stosb|rep stosb}"
17014 [(set_attr "type" "str")
17015 (set_attr "prefix_rep" "1")
17016 (set_attr "memory" "store")
17017 (set_attr "mode" "QI")])
17019 (define_insn "*rep_stosqi_rex64"
17020 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17021 (set (match_operand:DI 0 "register_operand" "=D")
17022 (plus:DI (match_operand:DI 3 "register_operand" "0")
17023 (match_operand:DI 4 "register_operand" "1")))
17024 (set (mem:BLK (match_dup 3))
17026 (use (match_operand:QI 2 "register_operand" "a"))
17027 (use (match_dup 4))
17028 (use (reg:SI DIRFLAG_REG))]
17030 "{rep\;stosb|rep stosb}"
17031 [(set_attr "type" "str")
17032 (set_attr "prefix_rep" "1")
17033 (set_attr "memory" "store")
17034 (set_attr "mode" "QI")])
17036 (define_expand "cmpstrsi"
17037 [(set (match_operand:SI 0 "register_operand" "")
17038 (compare:SI (match_operand:BLK 1 "general_operand" "")
17039 (match_operand:BLK 2 "general_operand" "")))
17040 (use (match_operand 3 "general_operand" ""))
17041 (use (match_operand 4 "immediate_operand" ""))]
17042 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17044 rtx addr1, addr2, out, outlow, count, countreg, align;
17046 /* Can't use this if the user has appropriated esi or edi. */
17047 if (global_regs[4] || global_regs[5])
17051 if (GET_CODE (out) != REG)
17052 out = gen_reg_rtx (SImode);
17054 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17055 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17056 if (addr1 != XEXP (operands[1], 0))
17057 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17058 if (addr2 != XEXP (operands[2], 0))
17059 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17061 count = operands[3];
17062 countreg = ix86_zero_extend_to_Pmode (count);
17064 /* %%% Iff we are testing strict equality, we can use known alignment
17065 to good advantage. This may be possible with combine, particularly
17066 once cc0 is dead. */
17067 align = operands[4];
17069 emit_insn (gen_cld ());
17070 if (GET_CODE (count) == CONST_INT)
17072 if (INTVAL (count) == 0)
17074 emit_move_insn (operands[0], const0_rtx);
17077 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
17078 operands[1], operands[2]));
17083 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17085 emit_insn (gen_cmpsi_1 (countreg, countreg));
17086 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
17087 operands[1], operands[2]));
17090 outlow = gen_lowpart (QImode, out);
17091 emit_insn (gen_cmpintqi (outlow));
17092 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17094 if (operands[0] != out)
17095 emit_move_insn (operands[0], out);
17100 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17102 (define_expand "cmpintqi"
17103 [(set (match_dup 1)
17104 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17106 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17107 (parallel [(set (match_operand:QI 0 "register_operand" "")
17108 (minus:QI (match_dup 1)
17110 (clobber (reg:CC FLAGS_REG))])]
17112 "operands[1] = gen_reg_rtx (QImode);
17113 operands[2] = gen_reg_rtx (QImode);")
17115 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17116 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17118 (define_expand "cmpstrqi_nz_1"
17119 [(parallel [(set (reg:CC FLAGS_REG)
17120 (compare:CC (match_operand 4 "memory_operand" "")
17121 (match_operand 5 "memory_operand" "")))
17122 (use (match_operand 2 "register_operand" ""))
17123 (use (match_operand:SI 3 "immediate_operand" ""))
17124 (use (reg:SI DIRFLAG_REG))
17125 (clobber (match_operand 0 "register_operand" ""))
17126 (clobber (match_operand 1 "register_operand" ""))
17127 (clobber (match_dup 2))])]
17131 (define_insn "*cmpstrqi_nz_1"
17132 [(set (reg:CC FLAGS_REG)
17133 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17134 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
17135 (use (match_operand:SI 6 "register_operand" "2"))
17136 (use (match_operand:SI 3 "immediate_operand" "i"))
17137 (use (reg:SI DIRFLAG_REG))
17138 (clobber (match_operand:SI 0 "register_operand" "=S"))
17139 (clobber (match_operand:SI 1 "register_operand" "=D"))
17140 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17143 [(set_attr "type" "str")
17144 (set_attr "mode" "QI")
17145 (set_attr "prefix_rep" "1")])
17147 (define_insn "*cmpstrqi_nz_rex_1"
17148 [(set (reg:CC FLAGS_REG)
17149 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17150 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
17151 (use (match_operand:DI 6 "register_operand" "2"))
17152 (use (match_operand:SI 3 "immediate_operand" "i"))
17153 (use (reg:SI DIRFLAG_REG))
17154 (clobber (match_operand:DI 0 "register_operand" "=S"))
17155 (clobber (match_operand:DI 1 "register_operand" "=D"))
17156 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17159 [(set_attr "type" "str")
17160 (set_attr "mode" "QI")
17161 (set_attr "prefix_rep" "1")])
17163 ;; The same, but the count is not known to not be zero.
17165 (define_expand "cmpstrqi_1"
17166 [(parallel [(set (reg:CC FLAGS_REG)
17167 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
17169 (compare:CC (match_operand 4 "memory_operand" "")
17170 (match_operand 5 "memory_operand" ""))
17172 (use (match_operand:SI 3 "immediate_operand" ""))
17173 (use (reg:CC FLAGS_REG))
17174 (use (reg:SI DIRFLAG_REG))
17175 (clobber (match_operand 0 "register_operand" ""))
17176 (clobber (match_operand 1 "register_operand" ""))
17177 (clobber (match_dup 2))])]
17181 (define_insn "*cmpstrqi_1"
17182 [(set (reg:CC FLAGS_REG)
17183 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
17185 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
17186 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
17188 (use (match_operand:SI 3 "immediate_operand" "i"))
17189 (use (reg:CC FLAGS_REG))
17190 (use (reg:SI DIRFLAG_REG))
17191 (clobber (match_operand:SI 0 "register_operand" "=S"))
17192 (clobber (match_operand:SI 1 "register_operand" "=D"))
17193 (clobber (match_operand:SI 2 "register_operand" "=c"))]
17196 [(set_attr "type" "str")
17197 (set_attr "mode" "QI")
17198 (set_attr "prefix_rep" "1")])
17200 (define_insn "*cmpstrqi_rex_1"
17201 [(set (reg:CC FLAGS_REG)
17202 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
17204 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
17205 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
17207 (use (match_operand:SI 3 "immediate_operand" "i"))
17208 (use (reg:CC FLAGS_REG))
17209 (use (reg:SI DIRFLAG_REG))
17210 (clobber (match_operand:DI 0 "register_operand" "=S"))
17211 (clobber (match_operand:DI 1 "register_operand" "=D"))
17212 (clobber (match_operand:DI 2 "register_operand" "=c"))]
17215 [(set_attr "type" "str")
17216 (set_attr "mode" "QI")
17217 (set_attr "prefix_rep" "1")])
17219 (define_expand "strlensi"
17220 [(set (match_operand:SI 0 "register_operand" "")
17221 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
17222 (match_operand:QI 2 "immediate_operand" "")
17223 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17226 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17232 (define_expand "strlendi"
17233 [(set (match_operand:DI 0 "register_operand" "")
17234 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
17235 (match_operand:QI 2 "immediate_operand" "")
17236 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
17239 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
17245 (define_expand "strlenqi_1"
17246 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
17247 (use (reg:SI DIRFLAG_REG))
17248 (clobber (match_operand 1 "register_operand" ""))
17249 (clobber (reg:CC FLAGS_REG))])]
17253 (define_insn "*strlenqi_1"
17254 [(set (match_operand:SI 0 "register_operand" "=&c")
17255 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
17256 (match_operand:QI 2 "register_operand" "a")
17257 (match_operand:SI 3 "immediate_operand" "i")
17258 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
17259 (use (reg:SI DIRFLAG_REG))
17260 (clobber (match_operand:SI 1 "register_operand" "=D"))
17261 (clobber (reg:CC FLAGS_REG))]
17264 [(set_attr "type" "str")
17265 (set_attr "mode" "QI")
17266 (set_attr "prefix_rep" "1")])
17268 (define_insn "*strlenqi_rex_1"
17269 [(set (match_operand:DI 0 "register_operand" "=&c")
17270 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
17271 (match_operand:QI 2 "register_operand" "a")
17272 (match_operand:DI 3 "immediate_operand" "i")
17273 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
17274 (use (reg:SI DIRFLAG_REG))
17275 (clobber (match_operand:DI 1 "register_operand" "=D"))
17276 (clobber (reg:CC FLAGS_REG))]
17279 [(set_attr "type" "str")
17280 (set_attr "mode" "QI")
17281 (set_attr "prefix_rep" "1")])
17283 ;; Peephole optimizations to clean up after cmpstr*. This should be
17284 ;; handled in combine, but it is not currently up to the task.
17285 ;; When used for their truth value, the cmpstr* expanders generate
17294 ;; The intermediate three instructions are unnecessary.
17296 ;; This one handles cmpstr*_nz_1...
17299 (set (reg:CC FLAGS_REG)
17300 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17301 (mem:BLK (match_operand 5 "register_operand" ""))))
17302 (use (match_operand 6 "register_operand" ""))
17303 (use (match_operand:SI 3 "immediate_operand" ""))
17304 (use (reg:SI DIRFLAG_REG))
17305 (clobber (match_operand 0 "register_operand" ""))
17306 (clobber (match_operand 1 "register_operand" ""))
17307 (clobber (match_operand 2 "register_operand" ""))])
17308 (set (match_operand:QI 7 "register_operand" "")
17309 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17310 (set (match_operand:QI 8 "register_operand" "")
17311 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17312 (set (reg FLAGS_REG)
17313 (compare (match_dup 7) (match_dup 8)))
17315 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17317 (set (reg:CC FLAGS_REG)
17318 (compare:CC (mem:BLK (match_dup 4))
17319 (mem:BLK (match_dup 5))))
17320 (use (match_dup 6))
17321 (use (match_dup 3))
17322 (use (reg:SI DIRFLAG_REG))
17323 (clobber (match_dup 0))
17324 (clobber (match_dup 1))
17325 (clobber (match_dup 2))])]
17328 ;; ...and this one handles cmpstr*_1.
17331 (set (reg:CC FLAGS_REG)
17332 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
17334 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
17335 (mem:BLK (match_operand 5 "register_operand" "")))
17337 (use (match_operand:SI 3 "immediate_operand" ""))
17338 (use (reg:CC FLAGS_REG))
17339 (use (reg:SI DIRFLAG_REG))
17340 (clobber (match_operand 0 "register_operand" ""))
17341 (clobber (match_operand 1 "register_operand" ""))
17342 (clobber (match_operand 2 "register_operand" ""))])
17343 (set (match_operand:QI 7 "register_operand" "")
17344 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17345 (set (match_operand:QI 8 "register_operand" "")
17346 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17347 (set (reg FLAGS_REG)
17348 (compare (match_dup 7) (match_dup 8)))
17350 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
17352 (set (reg:CC FLAGS_REG)
17353 (if_then_else:CC (ne (match_dup 6)
17355 (compare:CC (mem:BLK (match_dup 4))
17356 (mem:BLK (match_dup 5)))
17358 (use (match_dup 3))
17359 (use (reg:CC FLAGS_REG))
17360 (use (reg:SI DIRFLAG_REG))
17361 (clobber (match_dup 0))
17362 (clobber (match_dup 1))
17363 (clobber (match_dup 2))])]
17368 ;; Conditional move instructions.
17370 (define_expand "movdicc"
17371 [(set (match_operand:DI 0 "register_operand" "")
17372 (if_then_else:DI (match_operand 1 "comparison_operator" "")
17373 (match_operand:DI 2 "general_operand" "")
17374 (match_operand:DI 3 "general_operand" "")))]
17376 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17378 (define_insn "x86_movdicc_0_m1_rex64"
17379 [(set (match_operand:DI 0 "register_operand" "=r")
17380 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
17383 (clobber (reg:CC FLAGS_REG))]
17386 ; Since we don't have the proper number of operands for an alu insn,
17387 ; fill in all the blanks.
17388 [(set_attr "type" "alu")
17389 (set_attr "pent_pair" "pu")
17390 (set_attr "memory" "none")
17391 (set_attr "imm_disp" "false")
17392 (set_attr "mode" "DI")
17393 (set_attr "length_immediate" "0")])
17395 (define_insn "movdicc_c_rex64"
17396 [(set (match_operand:DI 0 "register_operand" "=r,r")
17397 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
17398 [(reg FLAGS_REG) (const_int 0)])
17399 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
17400 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
17401 "TARGET_64BIT && TARGET_CMOVE
17402 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17404 cmov%O2%C1\t{%2, %0|%0, %2}
17405 cmov%O2%c1\t{%3, %0|%0, %3}"
17406 [(set_attr "type" "icmov")
17407 (set_attr "mode" "DI")])
17409 (define_expand "movsicc"
17410 [(set (match_operand:SI 0 "register_operand" "")
17411 (if_then_else:SI (match_operand 1 "comparison_operator" "")
17412 (match_operand:SI 2 "general_operand" "")
17413 (match_operand:SI 3 "general_operand" "")))]
17415 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17417 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
17418 ;; the register first winds up with `sbbl $0,reg', which is also weird.
17419 ;; So just document what we're doing explicitly.
17421 (define_insn "x86_movsicc_0_m1"
17422 [(set (match_operand:SI 0 "register_operand" "=r")
17423 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
17426 (clobber (reg:CC FLAGS_REG))]
17429 ; Since we don't have the proper number of operands for an alu insn,
17430 ; fill in all the blanks.
17431 [(set_attr "type" "alu")
17432 (set_attr "pent_pair" "pu")
17433 (set_attr "memory" "none")
17434 (set_attr "imm_disp" "false")
17435 (set_attr "mode" "SI")
17436 (set_attr "length_immediate" "0")])
17438 (define_insn "*movsicc_noc"
17439 [(set (match_operand:SI 0 "register_operand" "=r,r")
17440 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17441 [(reg FLAGS_REG) (const_int 0)])
17442 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17443 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17445 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17447 cmov%O2%C1\t{%2, %0|%0, %2}
17448 cmov%O2%c1\t{%3, %0|%0, %3}"
17449 [(set_attr "type" "icmov")
17450 (set_attr "mode" "SI")])
17452 (define_expand "movhicc"
17453 [(set (match_operand:HI 0 "register_operand" "")
17454 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17455 (match_operand:HI 2 "general_operand" "")
17456 (match_operand:HI 3 "general_operand" "")))]
17457 "TARGET_HIMODE_MATH"
17458 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17460 (define_insn "*movhicc_noc"
17461 [(set (match_operand:HI 0 "register_operand" "=r,r")
17462 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17463 [(reg FLAGS_REG) (const_int 0)])
17464 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17465 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17467 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17469 cmov%O2%C1\t{%2, %0|%0, %2}
17470 cmov%O2%c1\t{%3, %0|%0, %3}"
17471 [(set_attr "type" "icmov")
17472 (set_attr "mode" "HI")])
17474 (define_expand "movqicc"
17475 [(set (match_operand:QI 0 "register_operand" "")
17476 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17477 (match_operand:QI 2 "general_operand" "")
17478 (match_operand:QI 3 "general_operand" "")))]
17479 "TARGET_QIMODE_MATH"
17480 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17482 (define_insn_and_split "*movqicc_noc"
17483 [(set (match_operand:QI 0 "register_operand" "=r,r")
17484 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17485 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17486 (match_operand:QI 2 "register_operand" "r,0")
17487 (match_operand:QI 3 "register_operand" "0,r")))]
17488 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17490 "&& reload_completed"
17491 [(set (match_dup 0)
17492 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17495 "operands[0] = gen_lowpart (SImode, operands[0]);
17496 operands[2] = gen_lowpart (SImode, operands[2]);
17497 operands[3] = gen_lowpart (SImode, operands[3]);"
17498 [(set_attr "type" "icmov")
17499 (set_attr "mode" "SI")])
17501 (define_expand "movsfcc"
17502 [(set (match_operand:SF 0 "register_operand" "")
17503 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17504 (match_operand:SF 2 "register_operand" "")
17505 (match_operand:SF 3 "register_operand" "")))]
17507 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17509 (define_insn "*movsfcc_1"
17510 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17511 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17512 [(reg FLAGS_REG) (const_int 0)])
17513 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17514 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17516 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17518 fcmov%F1\t{%2, %0|%0, %2}
17519 fcmov%f1\t{%3, %0|%0, %3}
17520 cmov%O2%C1\t{%2, %0|%0, %2}
17521 cmov%O2%c1\t{%3, %0|%0, %3}"
17522 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17523 (set_attr "mode" "SF,SF,SI,SI")])
17525 (define_expand "movdfcc"
17526 [(set (match_operand:DF 0 "register_operand" "")
17527 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17528 (match_operand:DF 2 "register_operand" "")
17529 (match_operand:DF 3 "register_operand" "")))]
17531 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17533 (define_insn "*movdfcc_1"
17534 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17535 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17536 [(reg FLAGS_REG) (const_int 0)])
17537 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17538 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17539 "!TARGET_64BIT && TARGET_CMOVE
17540 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17542 fcmov%F1\t{%2, %0|%0, %2}
17543 fcmov%f1\t{%3, %0|%0, %3}
17546 [(set_attr "type" "fcmov,fcmov,multi,multi")
17547 (set_attr "mode" "DF")])
17549 (define_insn "*movdfcc_1_rex64"
17550 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17551 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17552 [(reg FLAGS_REG) (const_int 0)])
17553 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17554 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17555 "TARGET_64BIT && TARGET_CMOVE
17556 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17558 fcmov%F1\t{%2, %0|%0, %2}
17559 fcmov%f1\t{%3, %0|%0, %3}
17560 cmov%O2%C1\t{%2, %0|%0, %2}
17561 cmov%O2%c1\t{%3, %0|%0, %3}"
17562 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17563 (set_attr "mode" "DF")])
17566 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17567 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17568 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17569 (match_operand:DF 2 "nonimmediate_operand" "")
17570 (match_operand:DF 3 "nonimmediate_operand" "")))]
17571 "!TARGET_64BIT && reload_completed"
17572 [(set (match_dup 2)
17573 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17577 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17580 "split_di (operands+2, 1, operands+5, operands+6);
17581 split_di (operands+3, 1, operands+7, operands+8);
17582 split_di (operands, 1, operands+2, operands+3);")
17584 (define_expand "movxfcc"
17585 [(set (match_operand:XF 0 "register_operand" "")
17586 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17587 (match_operand:XF 2 "register_operand" "")
17588 (match_operand:XF 3 "register_operand" "")))]
17590 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17592 (define_insn "*movxfcc_1"
17593 [(set (match_operand:XF 0 "register_operand" "=f,f")
17594 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17595 [(reg FLAGS_REG) (const_int 0)])
17596 (match_operand:XF 2 "register_operand" "f,0")
17597 (match_operand:XF 3 "register_operand" "0,f")))]
17600 fcmov%F1\t{%2, %0|%0, %2}
17601 fcmov%f1\t{%3, %0|%0, %3}"
17602 [(set_attr "type" "fcmov")
17603 (set_attr "mode" "XF")])
17605 (define_expand "minsf3"
17607 (set (match_operand:SF 0 "register_operand" "")
17608 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17609 (match_operand:SF 2 "nonimmediate_operand" ""))
17612 (clobber (reg:CC FLAGS_REG))])]
17616 (define_insn "*minsf"
17617 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17618 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17619 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17622 (clobber (reg:CC FLAGS_REG))]
17623 "TARGET_SSE && TARGET_IEEE_FP"
17626 (define_insn "*minsf_nonieee"
17627 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17628 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17629 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17632 (clobber (reg:CC FLAGS_REG))]
17633 "TARGET_SSE && !TARGET_IEEE_FP
17634 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17638 [(set (match_operand:SF 0 "register_operand" "")
17639 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17640 (match_operand:SF 2 "nonimmediate_operand" ""))
17641 (match_operand:SF 3 "register_operand" "")
17642 (match_operand:SF 4 "nonimmediate_operand" "")))
17643 (clobber (reg:CC FLAGS_REG))]
17644 "SSE_REG_P (operands[0]) && reload_completed
17645 && ((operands_match_p (operands[1], operands[3])
17646 && operands_match_p (operands[2], operands[4]))
17647 || (operands_match_p (operands[1], operands[4])
17648 && operands_match_p (operands[2], operands[3])))"
17649 [(set (match_dup 0)
17650 (if_then_else:SF (lt (match_dup 1)
17655 ;; Conditional addition patterns
17656 (define_expand "addqicc"
17657 [(match_operand:QI 0 "register_operand" "")
17658 (match_operand 1 "comparison_operator" "")
17659 (match_operand:QI 2 "register_operand" "")
17660 (match_operand:QI 3 "const_int_operand" "")]
17662 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17664 (define_expand "addhicc"
17665 [(match_operand:HI 0 "register_operand" "")
17666 (match_operand 1 "comparison_operator" "")
17667 (match_operand:HI 2 "register_operand" "")
17668 (match_operand:HI 3 "const_int_operand" "")]
17670 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17672 (define_expand "addsicc"
17673 [(match_operand:SI 0 "register_operand" "")
17674 (match_operand 1 "comparison_operator" "")
17675 (match_operand:SI 2 "register_operand" "")
17676 (match_operand:SI 3 "const_int_operand" "")]
17678 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17680 (define_expand "adddicc"
17681 [(match_operand:DI 0 "register_operand" "")
17682 (match_operand 1 "comparison_operator" "")
17683 (match_operand:DI 2 "register_operand" "")
17684 (match_operand:DI 3 "const_int_operand" "")]
17686 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17688 ;; We can't represent the LT test directly. Do this by swapping the operands.
17691 [(set (match_operand:SF 0 "fp_register_operand" "")
17692 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17693 (match_operand:SF 2 "register_operand" ""))
17694 (match_operand:SF 3 "register_operand" "")
17695 (match_operand:SF 4 "register_operand" "")))
17696 (clobber (reg:CC FLAGS_REG))]
17698 && ((operands_match_p (operands[1], operands[3])
17699 && operands_match_p (operands[2], operands[4]))
17700 || (operands_match_p (operands[1], operands[4])
17701 && operands_match_p (operands[2], operands[3])))"
17702 [(set (reg:CCFP FLAGS_REG)
17703 (compare:CCFP (match_dup 2)
17706 (if_then_else:SF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17710 (define_insn "*minsf_sse"
17711 [(set (match_operand:SF 0 "register_operand" "=x")
17712 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17713 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17716 "TARGET_SSE && reload_completed"
17717 "minss\t{%2, %0|%0, %2}"
17718 [(set_attr "type" "sse")
17719 (set_attr "mode" "SF")])
17721 (define_expand "mindf3"
17723 (set (match_operand:DF 0 "register_operand" "")
17724 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17725 (match_operand:DF 2 "nonimmediate_operand" ""))
17728 (clobber (reg:CC FLAGS_REG))])]
17729 "TARGET_SSE2 && TARGET_SSE_MATH"
17732 (define_insn "*mindf"
17733 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17734 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17735 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17738 (clobber (reg:CC FLAGS_REG))]
17739 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17742 (define_insn "*mindf_nonieee"
17743 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17744 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17745 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17748 (clobber (reg:CC FLAGS_REG))]
17749 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17750 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17754 [(set (match_operand:DF 0 "register_operand" "")
17755 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17756 (match_operand:DF 2 "nonimmediate_operand" ""))
17757 (match_operand:DF 3 "register_operand" "")
17758 (match_operand:DF 4 "nonimmediate_operand" "")))
17759 (clobber (reg:CC FLAGS_REG))]
17760 "SSE_REG_P (operands[0]) && reload_completed
17761 && ((operands_match_p (operands[1], operands[3])
17762 && operands_match_p (operands[2], operands[4]))
17763 || (operands_match_p (operands[1], operands[4])
17764 && operands_match_p (operands[2], operands[3])))"
17765 [(set (match_dup 0)
17766 (if_then_else:DF (lt (match_dup 1)
17771 ;; We can't represent the LT test directly. Do this by swapping the operands.
17773 [(set (match_operand:DF 0 "fp_register_operand" "")
17774 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17775 (match_operand:DF 2 "register_operand" ""))
17776 (match_operand:DF 3 "register_operand" "")
17777 (match_operand:DF 4 "register_operand" "")))
17778 (clobber (reg:CC FLAGS_REG))]
17780 && ((operands_match_p (operands[1], operands[3])
17781 && operands_match_p (operands[2], operands[4]))
17782 || (operands_match_p (operands[1], operands[4])
17783 && operands_match_p (operands[2], operands[3])))"
17784 [(set (reg:CCFP FLAGS_REG)
17785 (compare:CCFP (match_dup 2)
17788 (if_then_else:DF (ge (reg:CCFP FLAGS_REG) (const_int 0))
17792 (define_insn "*mindf_sse"
17793 [(set (match_operand:DF 0 "register_operand" "=Y")
17794 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17795 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17798 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17799 "minsd\t{%2, %0|%0, %2}"
17800 [(set_attr "type" "sse")
17801 (set_attr "mode" "DF")])
17803 (define_expand "maxsf3"
17805 (set (match_operand:SF 0 "register_operand" "")
17806 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17807 (match_operand:SF 2 "nonimmediate_operand" ""))
17810 (clobber (reg:CC FLAGS_REG))])]
17814 (define_insn "*maxsf"
17815 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17816 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17817 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17820 (clobber (reg:CC FLAGS_REG))]
17821 "TARGET_SSE && TARGET_IEEE_FP"
17824 (define_insn "*maxsf_nonieee"
17825 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17826 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17827 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17830 (clobber (reg:CC FLAGS_REG))]
17831 "TARGET_SSE && !TARGET_IEEE_FP
17832 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17836 [(set (match_operand:SF 0 "register_operand" "")
17837 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17838 (match_operand:SF 2 "nonimmediate_operand" ""))
17839 (match_operand:SF 3 "register_operand" "")
17840 (match_operand:SF 4 "nonimmediate_operand" "")))
17841 (clobber (reg:CC FLAGS_REG))]
17842 "SSE_REG_P (operands[0]) && reload_completed
17843 && ((operands_match_p (operands[1], operands[3])
17844 && operands_match_p (operands[2], operands[4]))
17845 || (operands_match_p (operands[1], operands[4])
17846 && operands_match_p (operands[2], operands[3])))"
17847 [(set (match_dup 0)
17848 (if_then_else:SF (gt (match_dup 1)
17854 [(set (match_operand:SF 0 "fp_register_operand" "")
17855 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17856 (match_operand:SF 2 "register_operand" ""))
17857 (match_operand:SF 3 "register_operand" "")
17858 (match_operand:SF 4 "register_operand" "")))
17859 (clobber (reg:CC FLAGS_REG))]
17861 && ((operands_match_p (operands[1], operands[3])
17862 && operands_match_p (operands[2], operands[4]))
17863 || (operands_match_p (operands[1], operands[4])
17864 && operands_match_p (operands[2], operands[3])))"
17865 [(set (reg:CCFP FLAGS_REG)
17866 (compare:CCFP (match_dup 1)
17869 (if_then_else:SF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17873 (define_insn "*maxsf_sse"
17874 [(set (match_operand:SF 0 "register_operand" "=x")
17875 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17876 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17879 "TARGET_SSE && reload_completed"
17880 "maxss\t{%2, %0|%0, %2}"
17881 [(set_attr "type" "sse")
17882 (set_attr "mode" "SF")])
17884 (define_expand "maxdf3"
17886 (set (match_operand:DF 0 "register_operand" "")
17887 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17888 (match_operand:DF 2 "nonimmediate_operand" ""))
17891 (clobber (reg:CC FLAGS_REG))])]
17892 "TARGET_SSE2 && TARGET_SSE_MATH"
17895 (define_insn "*maxdf"
17896 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17897 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17898 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17901 (clobber (reg:CC FLAGS_REG))]
17902 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17905 (define_insn "*maxdf_nonieee"
17906 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17907 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17908 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17911 (clobber (reg:CC FLAGS_REG))]
17912 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17913 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17917 [(set (match_operand:DF 0 "register_operand" "")
17918 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17919 (match_operand:DF 2 "nonimmediate_operand" ""))
17920 (match_operand:DF 3 "register_operand" "")
17921 (match_operand:DF 4 "nonimmediate_operand" "")))
17922 (clobber (reg:CC FLAGS_REG))]
17923 "SSE_REG_P (operands[0]) && reload_completed
17924 && ((operands_match_p (operands[1], operands[3])
17925 && operands_match_p (operands[2], operands[4]))
17926 || (operands_match_p (operands[1], operands[4])
17927 && operands_match_p (operands[2], operands[3])))"
17928 [(set (match_dup 0)
17929 (if_then_else:DF (gt (match_dup 1)
17935 [(set (match_operand:DF 0 "fp_register_operand" "")
17936 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17937 (match_operand:DF 2 "register_operand" ""))
17938 (match_operand:DF 3 "register_operand" "")
17939 (match_operand:DF 4 "register_operand" "")))
17940 (clobber (reg:CC FLAGS_REG))]
17942 && ((operands_match_p (operands[1], operands[3])
17943 && operands_match_p (operands[2], operands[4]))
17944 || (operands_match_p (operands[1], operands[4])
17945 && operands_match_p (operands[2], operands[3])))"
17946 [(set (reg:CCFP FLAGS_REG)
17947 (compare:CCFP (match_dup 1)
17950 (if_then_else:DF (gt (reg:CCFP FLAGS_REG) (const_int 0))
17954 (define_insn "*maxdf_sse"
17955 [(set (match_operand:DF 0 "register_operand" "=Y")
17956 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17957 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17960 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17961 "maxsd\t{%2, %0|%0, %2}"
17962 [(set_attr "type" "sse")
17963 (set_attr "mode" "DF")])
17965 ;; Misc patterns (?)
17967 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17968 ;; Otherwise there will be nothing to keep
17970 ;; [(set (reg ebp) (reg esp))]
17971 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17972 ;; (clobber (eflags)]
17973 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17975 ;; in proper program order.
17976 (define_insn "pro_epilogue_adjust_stack_1"
17977 [(set (match_operand:SI 0 "register_operand" "=r,r")
17978 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17979 (match_operand:SI 2 "immediate_operand" "i,i")))
17980 (clobber (reg:CC FLAGS_REG))
17981 (clobber (mem:BLK (scratch)))]
17984 switch (get_attr_type (insn))
17987 return "mov{l}\t{%1, %0|%0, %1}";
17990 if (GET_CODE (operands[2]) == CONST_INT
17991 && (INTVAL (operands[2]) == 128
17992 || (INTVAL (operands[2]) < 0
17993 && INTVAL (operands[2]) != -128)))
17995 operands[2] = GEN_INT (-INTVAL (operands[2]));
17996 return "sub{l}\t{%2, %0|%0, %2}";
17998 return "add{l}\t{%2, %0|%0, %2}";
18001 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18002 return "lea{l}\t{%a2, %0|%0, %a2}";
18008 [(set (attr "type")
18009 (cond [(eq_attr "alternative" "0")
18010 (const_string "alu")
18011 (match_operand:SI 2 "const0_operand" "")
18012 (const_string "imov")
18014 (const_string "lea")))
18015 (set_attr "mode" "SI")])
18017 (define_insn "pro_epilogue_adjust_stack_rex64"
18018 [(set (match_operand:DI 0 "register_operand" "=r,r")
18019 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18020 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18021 (clobber (reg:CC FLAGS_REG))
18022 (clobber (mem:BLK (scratch)))]
18025 switch (get_attr_type (insn))
18028 return "mov{q}\t{%1, %0|%0, %1}";
18031 if (GET_CODE (operands[2]) == CONST_INT
18032 /* Avoid overflows. */
18033 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18034 && (INTVAL (operands[2]) == 128
18035 || (INTVAL (operands[2]) < 0
18036 && INTVAL (operands[2]) != -128)))
18038 operands[2] = GEN_INT (-INTVAL (operands[2]));
18039 return "sub{q}\t{%2, %0|%0, %2}";
18041 return "add{q}\t{%2, %0|%0, %2}";
18044 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18045 return "lea{q}\t{%a2, %0|%0, %a2}";
18051 [(set (attr "type")
18052 (cond [(eq_attr "alternative" "0")
18053 (const_string "alu")
18054 (match_operand:DI 2 "const0_operand" "")
18055 (const_string "imov")
18057 (const_string "lea")))
18058 (set_attr "mode" "DI")])
18060 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18061 [(set (match_operand:DI 0 "register_operand" "=r,r")
18062 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18063 (match_operand:DI 3 "immediate_operand" "i,i")))
18064 (use (match_operand:DI 2 "register_operand" "r,r"))
18065 (clobber (reg:CC FLAGS_REG))
18066 (clobber (mem:BLK (scratch)))]
18069 switch (get_attr_type (insn))
18072 return "add{q}\t{%2, %0|%0, %2}";
18075 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18076 return "lea{q}\t{%a2, %0|%0, %a2}";
18082 [(set_attr "type" "alu,lea")
18083 (set_attr "mode" "DI")])
18085 ;; Placeholder for the conditional moves. This one is split either to SSE
18086 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
18087 ;; fact is that compares supported by the cmp??ss instructions are exactly
18088 ;; swapped of those supported by cmove sequence.
18089 ;; The EQ/NE comparisons also needs bit care, since they are not directly
18090 ;; supported by i387 comparisons and we do need to emit two conditional moves
18093 (define_insn "sse_movsfcc"
18094 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
18095 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18096 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
18097 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
18098 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
18099 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
18100 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18101 (clobber (reg:CC FLAGS_REG))]
18103 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18104 /* Avoid combine from being smart and converting min/max
18105 instruction patterns into conditional moves. */
18106 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18107 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18108 || !rtx_equal_p (operands[4], operands[2])
18109 || !rtx_equal_p (operands[5], operands[3]))
18110 && (!TARGET_IEEE_FP
18111 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18114 (define_insn "sse_movsfcc_eq"
18115 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
18116 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
18117 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
18118 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
18119 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
18120 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
18121 (clobber (reg:CC FLAGS_REG))]
18123 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18126 (define_insn "sse_movdfcc"
18127 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
18128 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18129 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
18130 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
18131 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
18132 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
18133 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
18134 (clobber (reg:CC FLAGS_REG))]
18136 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
18137 /* Avoid combine from being smart and converting min/max
18138 instruction patterns into conditional moves. */
18139 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
18140 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
18141 || !rtx_equal_p (operands[4], operands[2])
18142 || !rtx_equal_p (operands[5], operands[3]))
18143 && (!TARGET_IEEE_FP
18144 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
18147 (define_insn "sse_movdfcc_eq"
18148 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
18149 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
18150 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
18151 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
18152 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
18153 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
18154 (clobber (reg:CC FLAGS_REG))]
18156 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18159 ;; For non-sse moves just expand the usual cmove sequence.
18161 [(set (match_operand 0 "register_operand" "")
18162 (if_then_else (match_operator 1 "comparison_operator"
18163 [(match_operand 4 "nonimmediate_operand" "")
18164 (match_operand 5 "register_operand" "")])
18165 (match_operand 2 "nonimmediate_operand" "")
18166 (match_operand 3 "nonimmediate_operand" "")))
18167 (clobber (match_operand 6 "" ""))
18168 (clobber (reg:CC FLAGS_REG))]
18169 "!SSE_REG_P (operands[0]) && reload_completed
18170 && (GET_MODE (operands[0]) == SFmode
18171 || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))"
18174 ix86_compare_op0 = operands[5];
18175 ix86_compare_op1 = operands[4];
18176 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
18177 VOIDmode, operands[5], operands[4]);
18178 ix86_expand_fp_movcc (operands);
18182 ;; Split SSE based conditional move into sequence:
18183 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
18184 ;; and op2, op0 - zero op2 if comparison was false
18185 ;; nand op0, op3 - load op3 to op0 if comparison was false
18186 ;; or op2, op0 - get the nonzero one into the result.
18188 [(set (match_operand:SF 0 "register_operand" "")
18189 (if_then_else:SF (match_operator:SF 1 "sse_comparison_operator"
18190 [(match_operand:SF 4 "register_operand" "")
18191 (match_operand:SF 5 "nonimmediate_operand" "")])
18192 (match_operand:SF 2 "register_operand" "")
18193 (match_operand:SF 3 "register_operand" "")))
18194 (clobber (match_operand 6 "" ""))
18195 (clobber (reg:CC FLAGS_REG))]
18196 "SSE_REG_P (operands[0]) && reload_completed"
18197 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18198 (set (match_dup 2) (and:V4SF (match_dup 2)
18200 (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8))
18202 (set (match_dup 0) (ior:V4SF (match_dup 6)
18205 /* If op2 == op3, op3 would be clobbered before it is used. */
18206 if (operands_match_p (operands[2], operands[3]))
18208 emit_move_insn (operands[0], operands[2]);
18212 PUT_MODE (operands[1], GET_MODE (operands[0]));
18213 if (operands_match_p (operands[0], operands[4]))
18214 operands[6] = operands[4], operands[7] = operands[2];
18216 operands[6] = operands[2], operands[7] = operands[4];
18217 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18218 operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0);
18219 operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0);
18220 operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0);
18221 operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0);
18222 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18226 [(set (match_operand:DF 0 "register_operand" "")
18227 (if_then_else:DF (match_operator:DF 1 "sse_comparison_operator"
18228 [(match_operand:DF 4 "register_operand" "")
18229 (match_operand:DF 5 "nonimmediate_operand" "")])
18230 (match_operand:DF 2 "register_operand" "")
18231 (match_operand:DF 3 "register_operand" "")))
18232 (clobber (match_operand 6 "" ""))
18233 (clobber (reg:CC FLAGS_REG))]
18234 "SSE_REG_P (operands[0]) && reload_completed"
18235 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
18236 (set (match_dup 2) (and:V2DF (match_dup 2)
18238 (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8))
18240 (set (match_dup 0) (ior:V2DF (match_dup 6)
18243 if (TARGET_SSE_SPLIT_REGS && !optimize_size)
18245 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18246 emit_insn (gen_sse2_unpcklpd (op, op, op));
18247 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18248 emit_insn (gen_sse2_unpcklpd (op, op, op));
18251 /* If op2 == op3, op3 would be clobbered before it is used. */
18252 if (operands_match_p (operands[2], operands[3]))
18254 emit_move_insn (operands[0], operands[2]);
18258 PUT_MODE (operands[1], GET_MODE (operands[0]));
18259 if (operands_match_p (operands[0], operands[4]))
18260 operands[6] = operands[4], operands[7] = operands[2];
18262 operands[6] = operands[2], operands[7] = operands[4];
18263 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18264 operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18265 operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18266 operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0);
18267 operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0);
18268 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18271 ;; Special case of conditional move we can handle effectively.
18272 ;; Do not brother with the integer/floating point case, since these are
18273 ;; bot considerably slower, unlike in the generic case.
18274 (define_insn "*sse_movsfcc_const0_1"
18275 [(set (match_operand:SF 0 "register_operand" "=&x")
18276 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18277 [(match_operand:SF 4 "register_operand" "0")
18278 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18279 (match_operand:SF 2 "register_operand" "x")
18280 (match_operand:SF 3 "const0_operand" "X")))]
18284 (define_insn "*sse_movsfcc_const0_2"
18285 [(set (match_operand:SF 0 "register_operand" "=&x")
18286 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
18287 [(match_operand:SF 4 "register_operand" "0")
18288 (match_operand:SF 5 "nonimmediate_operand" "xm")])
18289 (match_operand:SF 2 "const0_operand" "X")
18290 (match_operand:SF 3 "register_operand" "x")))]
18294 (define_insn "*sse_movsfcc_const0_3"
18295 [(set (match_operand:SF 0 "register_operand" "=&x")
18296 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18297 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18298 (match_operand:SF 5 "register_operand" "0")])
18299 (match_operand:SF 2 "register_operand" "x")
18300 (match_operand:SF 3 "const0_operand" "X")))]
18304 (define_insn "*sse_movsfcc_const0_4"
18305 [(set (match_operand:SF 0 "register_operand" "=&x")
18306 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18307 [(match_operand:SF 4 "nonimmediate_operand" "xm")
18308 (match_operand:SF 5 "register_operand" "0")])
18309 (match_operand:SF 2 "const0_operand" "X")
18310 (match_operand:SF 3 "register_operand" "x")))]
18314 (define_insn "*sse_movdfcc_const0_1"
18315 [(set (match_operand:DF 0 "register_operand" "=&Y")
18316 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18317 [(match_operand:DF 4 "register_operand" "0")
18318 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18319 (match_operand:DF 2 "register_operand" "Y")
18320 (match_operand:DF 3 "const0_operand" "X")))]
18324 (define_insn "*sse_movdfcc_const0_2"
18325 [(set (match_operand:DF 0 "register_operand" "=&Y")
18326 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
18327 [(match_operand:DF 4 "register_operand" "0")
18328 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
18329 (match_operand:DF 2 "const0_operand" "X")
18330 (match_operand:DF 3 "register_operand" "Y")))]
18334 (define_insn "*sse_movdfcc_const0_3"
18335 [(set (match_operand:DF 0 "register_operand" "=&Y")
18336 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18337 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18338 (match_operand:DF 5 "register_operand" "0")])
18339 (match_operand:DF 2 "register_operand" "Y")
18340 (match_operand:DF 3 "const0_operand" "X")))]
18344 (define_insn "*sse_movdfcc_const0_4"
18345 [(set (match_operand:DF 0 "register_operand" "=&Y")
18346 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18347 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
18348 (match_operand:DF 5 "register_operand" "0")])
18349 (match_operand:DF 2 "const0_operand" "X")
18350 (match_operand:DF 3 "register_operand" "Y")))]
18355 [(set (match_operand:SF 0 "register_operand" "")
18356 (if_then_else:SF (match_operator 1 "comparison_operator"
18357 [(match_operand:SF 4 "nonimmediate_operand" "")
18358 (match_operand:SF 5 "nonimmediate_operand" "")])
18359 (match_operand:SF 2 "nonmemory_operand" "")
18360 (match_operand:SF 3 "nonmemory_operand" "")))]
18361 "SSE_REG_P (operands[0]) && reload_completed
18362 && (const0_operand (operands[2], GET_MODE (operands[0]))
18363 || const0_operand (operands[3], GET_MODE (operands[0])))"
18364 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18365 (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))]
18367 PUT_MODE (operands[1], GET_MODE (operands[0]));
18368 if (!sse_comparison_operator (operands[1], VOIDmode)
18369 || !rtx_equal_p (operands[0], operands[4]))
18371 rtx tmp = operands[5];
18372 operands[5] = operands[4];
18374 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18376 if (!rtx_equal_p (operands[0], operands[4]))
18378 operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
18379 if (const0_operand (operands[2], GET_MODE (operands[2])))
18381 operands[7] = operands[3];
18382 operands[6] = gen_rtx_NOT (V4SFmode, operands[8]);
18386 operands[7] = operands[2];
18387 operands[6] = operands[8];
18389 operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0);
18393 [(set (match_operand:DF 0 "register_operand" "")
18394 (if_then_else:DF (match_operator 1 "comparison_operator"
18395 [(match_operand:DF 4 "nonimmediate_operand" "")
18396 (match_operand:DF 5 "nonimmediate_operand" "")])
18397 (match_operand:DF 2 "nonmemory_operand" "")
18398 (match_operand:DF 3 "nonmemory_operand" "")))]
18399 "SSE_REG_P (operands[0]) && reload_completed
18400 && (const0_operand (operands[2], GET_MODE (operands[0]))
18401 || const0_operand (operands[3], GET_MODE (operands[0])))"
18402 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
18403 (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
18405 if (TARGET_SSE_SPLIT_REGS && !optimize_size)
18407 if (REG_P (operands[2]))
18409 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
18410 emit_insn (gen_sse2_unpcklpd (op, op, op));
18412 if (REG_P (operands[3]))
18414 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
18415 emit_insn (gen_sse2_unpcklpd (op, op, op));
18418 PUT_MODE (operands[1], GET_MODE (operands[0]));
18419 if (!sse_comparison_operator (operands[1], VOIDmode)
18420 || !rtx_equal_p (operands[0], operands[4]))
18422 rtx tmp = operands[5];
18423 operands[5] = operands[4];
18425 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
18427 if (!rtx_equal_p (operands[0], operands[4]))
18429 operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
18430 if (const0_operand (operands[2], GET_MODE (operands[2])))
18432 operands[7] = operands[3];
18433 operands[6] = gen_rtx_NOT (V2DFmode, operands[8]);
18437 operands[7] = operands[2];
18438 operands[6] = operands[8];
18440 operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0);
18443 (define_expand "allocate_stack_worker"
18444 [(match_operand:SI 0 "register_operand" "")]
18445 "TARGET_STACK_PROBE"
18447 if (reload_completed)
18450 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18452 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18457 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18459 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18464 (define_insn "allocate_stack_worker_1"
18465 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18466 UNSPECV_STACK_PROBE)
18467 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18468 (clobber (match_scratch:SI 1 "=0"))
18469 (clobber (reg:CC FLAGS_REG))]
18470 "!TARGET_64BIT && TARGET_STACK_PROBE"
18472 [(set_attr "type" "multi")
18473 (set_attr "length" "5")])
18475 (define_expand "allocate_stack_worker_postreload"
18476 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18477 UNSPECV_STACK_PROBE)
18478 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18479 (clobber (match_dup 0))
18480 (clobber (reg:CC FLAGS_REG))])]
18484 (define_insn "allocate_stack_worker_rex64"
18485 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18486 UNSPECV_STACK_PROBE)
18487 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18488 (clobber (match_scratch:DI 1 "=0"))
18489 (clobber (reg:CC FLAGS_REG))]
18490 "TARGET_64BIT && TARGET_STACK_PROBE"
18492 [(set_attr "type" "multi")
18493 (set_attr "length" "5")])
18495 (define_expand "allocate_stack_worker_rex64_postreload"
18496 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18497 UNSPECV_STACK_PROBE)
18498 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18499 (clobber (match_dup 0))
18500 (clobber (reg:CC FLAGS_REG))])]
18504 (define_expand "allocate_stack"
18505 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18506 (minus:SI (reg:SI SP_REG)
18507 (match_operand:SI 1 "general_operand" "")))
18508 (clobber (reg:CC FLAGS_REG))])
18509 (parallel [(set (reg:SI SP_REG)
18510 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18511 (clobber (reg:CC FLAGS_REG))])]
18512 "TARGET_STACK_PROBE"
18514 #ifdef CHECK_STACK_LIMIT
18515 if (GET_CODE (operands[1]) == CONST_INT
18516 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18517 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18521 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18524 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18528 (define_expand "builtin_setjmp_receiver"
18529 [(label_ref (match_operand 0 "" ""))]
18530 "!TARGET_64BIT && flag_pic"
18532 emit_insn (gen_set_got (pic_offset_table_rtx));
18536 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18539 [(set (match_operand 0 "register_operand" "")
18540 (match_operator 3 "promotable_binary_operator"
18541 [(match_operand 1 "register_operand" "")
18542 (match_operand 2 "aligned_operand" "")]))
18543 (clobber (reg:CC FLAGS_REG))]
18544 "! TARGET_PARTIAL_REG_STALL && reload_completed
18545 && ((GET_MODE (operands[0]) == HImode
18546 && ((!optimize_size && !TARGET_FAST_PREFIX)
18547 || GET_CODE (operands[2]) != CONST_INT
18548 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18549 || (GET_MODE (operands[0]) == QImode
18550 && (TARGET_PROMOTE_QImode || optimize_size)))"
18551 [(parallel [(set (match_dup 0)
18552 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18553 (clobber (reg:CC FLAGS_REG))])]
18554 "operands[0] = gen_lowpart (SImode, operands[0]);
18555 operands[1] = gen_lowpart (SImode, operands[1]);
18556 if (GET_CODE (operands[3]) != ASHIFT)
18557 operands[2] = gen_lowpart (SImode, operands[2]);
18558 PUT_MODE (operands[3], SImode);")
18560 ; Promote the QImode tests, as i386 has encoding of the AND
18561 ; instruction with 32-bit sign-extended immediate and thus the
18562 ; instruction size is unchanged, except in the %eax case for
18563 ; which it is increased by one byte, hence the ! optimize_size.
18565 [(set (match_operand 0 "flags_reg_operand" "")
18566 (match_operator 2 "compare_operator"
18567 [(and (match_operand 3 "aligned_operand" "")
18568 (match_operand 4 "const_int_operand" ""))
18570 (set (match_operand 1 "register_operand" "")
18571 (and (match_dup 3) (match_dup 4)))]
18572 "! TARGET_PARTIAL_REG_STALL && reload_completed
18573 /* Ensure that the operand will remain sign-extended immediate. */
18574 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
18576 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
18577 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
18578 [(parallel [(set (match_dup 0)
18579 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
18582 (and:SI (match_dup 3) (match_dup 4)))])]
18585 = gen_int_mode (INTVAL (operands[4])
18586 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
18587 operands[1] = gen_lowpart (SImode, operands[1]);
18588 operands[3] = gen_lowpart (SImode, operands[3]);
18591 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18592 ; the TEST instruction with 32-bit sign-extended immediate and thus
18593 ; the instruction size would at least double, which is not what we
18594 ; want even with ! optimize_size.
18596 [(set (match_operand 0 "flags_reg_operand" "")
18597 (match_operator 1 "compare_operator"
18598 [(and (match_operand:HI 2 "aligned_operand" "")
18599 (match_operand:HI 3 "const_int_operand" ""))
18601 "! TARGET_PARTIAL_REG_STALL && reload_completed
18602 /* Ensure that the operand will remain sign-extended immediate. */
18603 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
18604 && ! TARGET_FAST_PREFIX
18605 && ! optimize_size"
18606 [(set (match_dup 0)
18607 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18611 = gen_int_mode (INTVAL (operands[3])
18612 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
18613 operands[2] = gen_lowpart (SImode, operands[2]);
18617 [(set (match_operand 0 "register_operand" "")
18618 (neg (match_operand 1 "register_operand" "")))
18619 (clobber (reg:CC FLAGS_REG))]
18620 "! TARGET_PARTIAL_REG_STALL && reload_completed
18621 && (GET_MODE (operands[0]) == HImode
18622 || (GET_MODE (operands[0]) == QImode
18623 && (TARGET_PROMOTE_QImode || optimize_size)))"
18624 [(parallel [(set (match_dup 0)
18625 (neg:SI (match_dup 1)))
18626 (clobber (reg:CC FLAGS_REG))])]
18627 "operands[0] = gen_lowpart (SImode, operands[0]);
18628 operands[1] = gen_lowpart (SImode, operands[1]);")
18631 [(set (match_operand 0 "register_operand" "")
18632 (not (match_operand 1 "register_operand" "")))]
18633 "! TARGET_PARTIAL_REG_STALL && reload_completed
18634 && (GET_MODE (operands[0]) == HImode
18635 || (GET_MODE (operands[0]) == QImode
18636 && (TARGET_PROMOTE_QImode || optimize_size)))"
18637 [(set (match_dup 0)
18638 (not:SI (match_dup 1)))]
18639 "operands[0] = gen_lowpart (SImode, operands[0]);
18640 operands[1] = gen_lowpart (SImode, operands[1]);")
18643 [(set (match_operand 0 "register_operand" "")
18644 (if_then_else (match_operator 1 "comparison_operator"
18645 [(reg FLAGS_REG) (const_int 0)])
18646 (match_operand 2 "register_operand" "")
18647 (match_operand 3 "register_operand" "")))]
18648 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18649 && (GET_MODE (operands[0]) == HImode
18650 || (GET_MODE (operands[0]) == QImode
18651 && (TARGET_PROMOTE_QImode || optimize_size)))"
18652 [(set (match_dup 0)
18653 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18654 "operands[0] = gen_lowpart (SImode, operands[0]);
18655 operands[2] = gen_lowpart (SImode, operands[2]);
18656 operands[3] = gen_lowpart (SImode, operands[3]);")
18659 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18660 ;; transform a complex memory operation into two memory to register operations.
18662 ;; Don't push memory operands
18664 [(set (match_operand:SI 0 "push_operand" "")
18665 (match_operand:SI 1 "memory_operand" ""))
18666 (match_scratch:SI 2 "r")]
18667 "! optimize_size && ! TARGET_PUSH_MEMORY"
18668 [(set (match_dup 2) (match_dup 1))
18669 (set (match_dup 0) (match_dup 2))]
18673 [(set (match_operand:DI 0 "push_operand" "")
18674 (match_operand:DI 1 "memory_operand" ""))
18675 (match_scratch:DI 2 "r")]
18676 "! optimize_size && ! TARGET_PUSH_MEMORY"
18677 [(set (match_dup 2) (match_dup 1))
18678 (set (match_dup 0) (match_dup 2))]
18681 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18684 [(set (match_operand:SF 0 "push_operand" "")
18685 (match_operand:SF 1 "memory_operand" ""))
18686 (match_scratch:SF 2 "r")]
18687 "! optimize_size && ! TARGET_PUSH_MEMORY"
18688 [(set (match_dup 2) (match_dup 1))
18689 (set (match_dup 0) (match_dup 2))]
18693 [(set (match_operand:HI 0 "push_operand" "")
18694 (match_operand:HI 1 "memory_operand" ""))
18695 (match_scratch:HI 2 "r")]
18696 "! optimize_size && ! TARGET_PUSH_MEMORY"
18697 [(set (match_dup 2) (match_dup 1))
18698 (set (match_dup 0) (match_dup 2))]
18702 [(set (match_operand:QI 0 "push_operand" "")
18703 (match_operand:QI 1 "memory_operand" ""))
18704 (match_scratch:QI 2 "q")]
18705 "! optimize_size && ! TARGET_PUSH_MEMORY"
18706 [(set (match_dup 2) (match_dup 1))
18707 (set (match_dup 0) (match_dup 2))]
18710 ;; Don't move an immediate directly to memory when the instruction
18713 [(match_scratch:SI 1 "r")
18714 (set (match_operand:SI 0 "memory_operand" "")
18717 && ! TARGET_USE_MOV0
18718 && TARGET_SPLIT_LONG_MOVES
18719 && get_attr_length (insn) >= ix86_cost->large_insn
18720 && peep2_regno_dead_p (0, FLAGS_REG)"
18721 [(parallel [(set (match_dup 1) (const_int 0))
18722 (clobber (reg:CC FLAGS_REG))])
18723 (set (match_dup 0) (match_dup 1))]
18727 [(match_scratch:HI 1 "r")
18728 (set (match_operand:HI 0 "memory_operand" "")
18731 && ! TARGET_USE_MOV0
18732 && TARGET_SPLIT_LONG_MOVES
18733 && get_attr_length (insn) >= ix86_cost->large_insn
18734 && peep2_regno_dead_p (0, FLAGS_REG)"
18735 [(parallel [(set (match_dup 2) (const_int 0))
18736 (clobber (reg:CC FLAGS_REG))])
18737 (set (match_dup 0) (match_dup 1))]
18738 "operands[2] = gen_lowpart (SImode, operands[1]);")
18741 [(match_scratch:QI 1 "q")
18742 (set (match_operand:QI 0 "memory_operand" "")
18745 && ! TARGET_USE_MOV0
18746 && TARGET_SPLIT_LONG_MOVES
18747 && get_attr_length (insn) >= ix86_cost->large_insn
18748 && peep2_regno_dead_p (0, FLAGS_REG)"
18749 [(parallel [(set (match_dup 2) (const_int 0))
18750 (clobber (reg:CC FLAGS_REG))])
18751 (set (match_dup 0) (match_dup 1))]
18752 "operands[2] = gen_lowpart (SImode, operands[1]);")
18755 [(match_scratch:SI 2 "r")
18756 (set (match_operand:SI 0 "memory_operand" "")
18757 (match_operand:SI 1 "immediate_operand" ""))]
18759 && get_attr_length (insn) >= ix86_cost->large_insn
18760 && TARGET_SPLIT_LONG_MOVES"
18761 [(set (match_dup 2) (match_dup 1))
18762 (set (match_dup 0) (match_dup 2))]
18766 [(match_scratch:HI 2 "r")
18767 (set (match_operand:HI 0 "memory_operand" "")
18768 (match_operand:HI 1 "immediate_operand" ""))]
18769 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18770 && TARGET_SPLIT_LONG_MOVES"
18771 [(set (match_dup 2) (match_dup 1))
18772 (set (match_dup 0) (match_dup 2))]
18776 [(match_scratch:QI 2 "q")
18777 (set (match_operand:QI 0 "memory_operand" "")
18778 (match_operand:QI 1 "immediate_operand" ""))]
18779 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18780 && TARGET_SPLIT_LONG_MOVES"
18781 [(set (match_dup 2) (match_dup 1))
18782 (set (match_dup 0) (match_dup 2))]
18785 ;; Don't compare memory with zero, load and use a test instead.
18787 [(set (match_operand 0 "flags_reg_operand" "")
18788 (match_operator 1 "compare_operator"
18789 [(match_operand:SI 2 "memory_operand" "")
18791 (match_scratch:SI 3 "r")]
18792 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
18793 [(set (match_dup 3) (match_dup 2))
18794 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
18797 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
18798 ;; Don't split NOTs with a displacement operand, because resulting XOR
18799 ;; will not be pairable anyway.
18801 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
18802 ;; represented using a modRM byte. The XOR replacement is long decoded,
18803 ;; so this split helps here as well.
18805 ;; Note: Can't do this as a regular split because we can't get proper
18806 ;; lifetime information then.
18809 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18810 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18812 && peep2_regno_dead_p (0, FLAGS_REG)
18813 && ((TARGET_PENTIUM
18814 && (GET_CODE (operands[0]) != MEM
18815 || !memory_displacement_operand (operands[0], SImode)))
18816 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18817 [(parallel [(set (match_dup 0)
18818 (xor:SI (match_dup 1) (const_int -1)))
18819 (clobber (reg:CC FLAGS_REG))])]
18823 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18824 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18826 && peep2_regno_dead_p (0, FLAGS_REG)
18827 && ((TARGET_PENTIUM
18828 && (GET_CODE (operands[0]) != MEM
18829 || !memory_displacement_operand (operands[0], HImode)))
18830 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18831 [(parallel [(set (match_dup 0)
18832 (xor:HI (match_dup 1) (const_int -1)))
18833 (clobber (reg:CC FLAGS_REG))])]
18837 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18838 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18840 && peep2_regno_dead_p (0, FLAGS_REG)
18841 && ((TARGET_PENTIUM
18842 && (GET_CODE (operands[0]) != MEM
18843 || !memory_displacement_operand (operands[0], QImode)))
18844 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18845 [(parallel [(set (match_dup 0)
18846 (xor:QI (match_dup 1) (const_int -1)))
18847 (clobber (reg:CC FLAGS_REG))])]
18850 ;; Non pairable "test imm, reg" instructions can be translated to
18851 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18852 ;; byte opcode instead of two, have a short form for byte operands),
18853 ;; so do it for other CPUs as well. Given that the value was dead,
18854 ;; this should not create any new dependencies. Pass on the sub-word
18855 ;; versions if we're concerned about partial register stalls.
18858 [(set (match_operand 0 "flags_reg_operand" "")
18859 (match_operator 1 "compare_operator"
18860 [(and:SI (match_operand:SI 2 "register_operand" "")
18861 (match_operand:SI 3 "immediate_operand" ""))
18863 "ix86_match_ccmode (insn, CCNOmode)
18864 && (true_regnum (operands[2]) != 0
18865 || (GET_CODE (operands[3]) == CONST_INT
18866 && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
18867 && peep2_reg_dead_p (1, operands[2])"
18869 [(set (match_dup 0)
18870 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18873 (and:SI (match_dup 2) (match_dup 3)))])]
18876 ;; We don't need to handle HImode case, because it will be promoted to SImode
18877 ;; on ! TARGET_PARTIAL_REG_STALL
18880 [(set (match_operand 0 "flags_reg_operand" "")
18881 (match_operator 1 "compare_operator"
18882 [(and:QI (match_operand:QI 2 "register_operand" "")
18883 (match_operand:QI 3 "immediate_operand" ""))
18885 "! TARGET_PARTIAL_REG_STALL
18886 && ix86_match_ccmode (insn, CCNOmode)
18887 && true_regnum (operands[2]) != 0
18888 && peep2_reg_dead_p (1, operands[2])"
18890 [(set (match_dup 0)
18891 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
18894 (and:QI (match_dup 2) (match_dup 3)))])]
18898 [(set (match_operand 0 "flags_reg_operand" "")
18899 (match_operator 1 "compare_operator"
18902 (match_operand 2 "ext_register_operand" "")
18905 (match_operand 3 "const_int_operand" ""))
18907 "! TARGET_PARTIAL_REG_STALL
18908 && ix86_match_ccmode (insn, CCNOmode)
18909 && true_regnum (operands[2]) != 0
18910 && peep2_reg_dead_p (1, operands[2])"
18911 [(parallel [(set (match_dup 0)
18920 (set (zero_extract:SI (match_dup 2)
18931 ;; Don't do logical operations with memory inputs.
18933 [(match_scratch:SI 2 "r")
18934 (parallel [(set (match_operand:SI 0 "register_operand" "")
18935 (match_operator:SI 3 "arith_or_logical_operator"
18937 (match_operand:SI 1 "memory_operand" "")]))
18938 (clobber (reg:CC FLAGS_REG))])]
18939 "! optimize_size && ! TARGET_READ_MODIFY"
18940 [(set (match_dup 2) (match_dup 1))
18941 (parallel [(set (match_dup 0)
18942 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18943 (clobber (reg:CC FLAGS_REG))])]
18947 [(match_scratch:SI 2 "r")
18948 (parallel [(set (match_operand:SI 0 "register_operand" "")
18949 (match_operator:SI 3 "arith_or_logical_operator"
18950 [(match_operand:SI 1 "memory_operand" "")
18952 (clobber (reg:CC FLAGS_REG))])]
18953 "! optimize_size && ! TARGET_READ_MODIFY"
18954 [(set (match_dup 2) (match_dup 1))
18955 (parallel [(set (match_dup 0)
18956 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18957 (clobber (reg:CC FLAGS_REG))])]
18960 ; Don't do logical operations with memory outputs
18962 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18963 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18964 ; the same decoder scheduling characteristics as the original.
18967 [(match_scratch:SI 2 "r")
18968 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18969 (match_operator:SI 3 "arith_or_logical_operator"
18971 (match_operand:SI 1 "nonmemory_operand" "")]))
18972 (clobber (reg:CC FLAGS_REG))])]
18973 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18974 [(set (match_dup 2) (match_dup 0))
18975 (parallel [(set (match_dup 2)
18976 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18977 (clobber (reg:CC FLAGS_REG))])
18978 (set (match_dup 0) (match_dup 2))]
18982 [(match_scratch:SI 2 "r")
18983 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18984 (match_operator:SI 3 "arith_or_logical_operator"
18985 [(match_operand:SI 1 "nonmemory_operand" "")
18987 (clobber (reg:CC FLAGS_REG))])]
18988 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18989 [(set (match_dup 2) (match_dup 0))
18990 (parallel [(set (match_dup 2)
18991 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18992 (clobber (reg:CC FLAGS_REG))])
18993 (set (match_dup 0) (match_dup 2))]
18996 ;; Attempt to always use XOR for zeroing registers.
18998 [(set (match_operand 0 "register_operand" "")
19000 "(GET_MODE (operands[0]) == QImode
19001 || GET_MODE (operands[0]) == HImode
19002 || GET_MODE (operands[0]) == SImode
19003 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19004 && (! TARGET_USE_MOV0 || optimize_size)
19005 && peep2_regno_dead_p (0, FLAGS_REG)"
19006 [(parallel [(set (match_dup 0) (const_int 0))
19007 (clobber (reg:CC FLAGS_REG))])]
19008 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19012 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19014 "(GET_MODE (operands[0]) == QImode
19015 || GET_MODE (operands[0]) == HImode)
19016 && (! TARGET_USE_MOV0 || optimize_size)
19017 && peep2_regno_dead_p (0, FLAGS_REG)"
19018 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19019 (clobber (reg:CC FLAGS_REG))])])
19021 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19023 [(set (match_operand 0 "register_operand" "")
19025 "(GET_MODE (operands[0]) == HImode
19026 || GET_MODE (operands[0]) == SImode
19027 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19028 && (optimize_size || TARGET_PENTIUM)
19029 && peep2_regno_dead_p (0, FLAGS_REG)"
19030 [(parallel [(set (match_dup 0) (const_int -1))
19031 (clobber (reg:CC FLAGS_REG))])]
19032 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19035 ;; Attempt to convert simple leas to adds. These can be created by
19038 [(set (match_operand:SI 0 "register_operand" "")
19039 (plus:SI (match_dup 0)
19040 (match_operand:SI 1 "nonmemory_operand" "")))]
19041 "peep2_regno_dead_p (0, FLAGS_REG)"
19042 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19043 (clobber (reg:CC FLAGS_REG))])]
19047 [(set (match_operand:SI 0 "register_operand" "")
19048 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19049 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19050 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19051 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19052 (clobber (reg:CC FLAGS_REG))])]
19053 "operands[2] = gen_lowpart (SImode, operands[2]);")
19056 [(set (match_operand:DI 0 "register_operand" "")
19057 (plus:DI (match_dup 0)
19058 (match_operand:DI 1 "x86_64_general_operand" "")))]
19059 "peep2_regno_dead_p (0, FLAGS_REG)"
19060 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19061 (clobber (reg:CC FLAGS_REG))])]
19065 [(set (match_operand:SI 0 "register_operand" "")
19066 (mult:SI (match_dup 0)
19067 (match_operand:SI 1 "const_int_operand" "")))]
19068 "exact_log2 (INTVAL (operands[1])) >= 0
19069 && peep2_regno_dead_p (0, FLAGS_REG)"
19070 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19071 (clobber (reg:CC FLAGS_REG))])]
19072 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19075 [(set (match_operand:DI 0 "register_operand" "")
19076 (mult:DI (match_dup 0)
19077 (match_operand:DI 1 "const_int_operand" "")))]
19078 "exact_log2 (INTVAL (operands[1])) >= 0
19079 && peep2_regno_dead_p (0, FLAGS_REG)"
19080 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19081 (clobber (reg:CC FLAGS_REG))])]
19082 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19085 [(set (match_operand:SI 0 "register_operand" "")
19086 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19087 (match_operand:DI 2 "const_int_operand" "")) 0))]
19088 "exact_log2 (INTVAL (operands[2])) >= 0
19089 && REGNO (operands[0]) == REGNO (operands[1])
19090 && peep2_regno_dead_p (0, FLAGS_REG)"
19091 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19092 (clobber (reg:CC FLAGS_REG))])]
19093 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19095 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19096 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19097 ;; many CPUs it is also faster, since special hardware to avoid esp
19098 ;; dependencies is present.
19100 ;; While some of these conversions may be done using splitters, we use peepholes
19101 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19103 ;; Convert prologue esp subtractions to push.
19104 ;; We need register to push. In order to keep verify_flow_info happy we have
19106 ;; - use scratch and clobber it in order to avoid dependencies
19107 ;; - use already live register
19108 ;; We can't use the second way right now, since there is no reliable way how to
19109 ;; verify that given register is live. First choice will also most likely in
19110 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19111 ;; call clobbered registers are dead. We may want to use base pointer as an
19112 ;; alternative when no register is available later.
19115 [(match_scratch:SI 0 "r")
19116 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19117 (clobber (reg:CC FLAGS_REG))
19118 (clobber (mem:BLK (scratch)))])]
19119 "optimize_size || !TARGET_SUB_ESP_4"
19120 [(clobber (match_dup 0))
19121 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19122 (clobber (mem:BLK (scratch)))])])
19125 [(match_scratch:SI 0 "r")
19126 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19127 (clobber (reg:CC FLAGS_REG))
19128 (clobber (mem:BLK (scratch)))])]
19129 "optimize_size || !TARGET_SUB_ESP_8"
19130 [(clobber (match_dup 0))
19131 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19132 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19133 (clobber (mem:BLK (scratch)))])])
19135 ;; Convert esp subtractions to push.
19137 [(match_scratch:SI 0 "r")
19138 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19139 (clobber (reg:CC FLAGS_REG))])]
19140 "optimize_size || !TARGET_SUB_ESP_4"
19141 [(clobber (match_dup 0))
19142 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19145 [(match_scratch:SI 0 "r")
19146 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19147 (clobber (reg:CC FLAGS_REG))])]
19148 "optimize_size || !TARGET_SUB_ESP_8"
19149 [(clobber (match_dup 0))
19150 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19151 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19153 ;; Convert epilogue deallocator to pop.
19155 [(match_scratch:SI 0 "r")
19156 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19157 (clobber (reg:CC FLAGS_REG))
19158 (clobber (mem:BLK (scratch)))])]
19159 "optimize_size || !TARGET_ADD_ESP_4"
19160 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19161 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19162 (clobber (mem:BLK (scratch)))])]
19165 ;; Two pops case is tricky, since pop causes dependency on destination register.
19166 ;; We use two registers if available.
19168 [(match_scratch:SI 0 "r")
19169 (match_scratch:SI 1 "r")
19170 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19171 (clobber (reg:CC FLAGS_REG))
19172 (clobber (mem:BLK (scratch)))])]
19173 "optimize_size || !TARGET_ADD_ESP_8"
19174 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19175 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19176 (clobber (mem:BLK (scratch)))])
19177 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19178 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19182 [(match_scratch:SI 0 "r")
19183 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19184 (clobber (reg:CC FLAGS_REG))
19185 (clobber (mem:BLK (scratch)))])]
19187 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19188 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19189 (clobber (mem:BLK (scratch)))])
19190 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19191 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19194 ;; Convert esp additions to pop.
19196 [(match_scratch:SI 0 "r")
19197 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19198 (clobber (reg:CC FLAGS_REG))])]
19200 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19201 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19204 ;; Two pops case is tricky, since pop causes dependency on destination register.
19205 ;; We use two registers if available.
19207 [(match_scratch:SI 0 "r")
19208 (match_scratch:SI 1 "r")
19209 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19210 (clobber (reg:CC FLAGS_REG))])]
19212 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19213 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19214 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19215 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19219 [(match_scratch:SI 0 "r")
19220 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19221 (clobber (reg:CC FLAGS_REG))])]
19223 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19224 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19225 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19226 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19229 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19230 ;; required and register dies. Similarly for 128 to plus -128.
19232 [(set (match_operand 0 "flags_reg_operand" "")
19233 (match_operator 1 "compare_operator"
19234 [(match_operand 2 "register_operand" "")
19235 (match_operand 3 "const_int_operand" "")]))]
19236 "(INTVAL (operands[3]) == -1
19237 || INTVAL (operands[3]) == 1
19238 || INTVAL (operands[3]) == 128)
19239 && ix86_match_ccmode (insn, CCGCmode)
19240 && peep2_reg_dead_p (1, operands[2])"
19241 [(parallel [(set (match_dup 0)
19242 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
19243 (clobber (match_dup 2))])]
19247 [(match_scratch:DI 0 "r")
19248 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19249 (clobber (reg:CC FLAGS_REG))
19250 (clobber (mem:BLK (scratch)))])]
19251 "optimize_size || !TARGET_SUB_ESP_4"
19252 [(clobber (match_dup 0))
19253 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19254 (clobber (mem:BLK (scratch)))])])
19257 [(match_scratch:DI 0 "r")
19258 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19259 (clobber (reg:CC FLAGS_REG))
19260 (clobber (mem:BLK (scratch)))])]
19261 "optimize_size || !TARGET_SUB_ESP_8"
19262 [(clobber (match_dup 0))
19263 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19264 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19265 (clobber (mem:BLK (scratch)))])])
19267 ;; Convert esp subtractions to push.
19269 [(match_scratch:DI 0 "r")
19270 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19271 (clobber (reg:CC FLAGS_REG))])]
19272 "optimize_size || !TARGET_SUB_ESP_4"
19273 [(clobber (match_dup 0))
19274 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19277 [(match_scratch:DI 0 "r")
19278 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19279 (clobber (reg:CC FLAGS_REG))])]
19280 "optimize_size || !TARGET_SUB_ESP_8"
19281 [(clobber (match_dup 0))
19282 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19283 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19285 ;; Convert epilogue deallocator to pop.
19287 [(match_scratch:DI 0 "r")
19288 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19289 (clobber (reg:CC FLAGS_REG))
19290 (clobber (mem:BLK (scratch)))])]
19291 "optimize_size || !TARGET_ADD_ESP_4"
19292 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19293 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19294 (clobber (mem:BLK (scratch)))])]
19297 ;; Two pops case is tricky, since pop causes dependency on destination register.
19298 ;; We use two registers if available.
19300 [(match_scratch:DI 0 "r")
19301 (match_scratch:DI 1 "r")
19302 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19303 (clobber (reg:CC FLAGS_REG))
19304 (clobber (mem:BLK (scratch)))])]
19305 "optimize_size || !TARGET_ADD_ESP_8"
19306 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19307 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19308 (clobber (mem:BLK (scratch)))])
19309 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19310 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19314 [(match_scratch:DI 0 "r")
19315 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19316 (clobber (reg:CC FLAGS_REG))
19317 (clobber (mem:BLK (scratch)))])]
19319 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19320 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19321 (clobber (mem:BLK (scratch)))])
19322 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19323 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19326 ;; Convert esp additions to pop.
19328 [(match_scratch:DI 0 "r")
19329 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19330 (clobber (reg:CC FLAGS_REG))])]
19332 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19333 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19336 ;; Two pops case is tricky, since pop causes dependency on destination register.
19337 ;; We use two registers if available.
19339 [(match_scratch:DI 0 "r")
19340 (match_scratch:DI 1 "r")
19341 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19342 (clobber (reg:CC FLAGS_REG))])]
19344 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19345 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19346 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19347 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19351 [(match_scratch:DI 0 "r")
19352 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19353 (clobber (reg:CC FLAGS_REG))])]
19355 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19356 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19357 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19358 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19361 ;; Convert imul by three, five and nine into lea
19364 [(set (match_operand:SI 0 "register_operand" "")
19365 (mult:SI (match_operand:SI 1 "register_operand" "")
19366 (match_operand:SI 2 "const_int_operand" "")))
19367 (clobber (reg:CC FLAGS_REG))])]
19368 "INTVAL (operands[2]) == 3
19369 || INTVAL (operands[2]) == 5
19370 || INTVAL (operands[2]) == 9"
19371 [(set (match_dup 0)
19372 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19374 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19378 [(set (match_operand:SI 0 "register_operand" "")
19379 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19380 (match_operand:SI 2 "const_int_operand" "")))
19381 (clobber (reg:CC FLAGS_REG))])]
19383 && (INTVAL (operands[2]) == 3
19384 || INTVAL (operands[2]) == 5
19385 || INTVAL (operands[2]) == 9)"
19386 [(set (match_dup 0) (match_dup 1))
19388 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19390 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19394 [(set (match_operand:DI 0 "register_operand" "")
19395 (mult:DI (match_operand:DI 1 "register_operand" "")
19396 (match_operand:DI 2 "const_int_operand" "")))
19397 (clobber (reg:CC FLAGS_REG))])]
19399 && (INTVAL (operands[2]) == 3
19400 || INTVAL (operands[2]) == 5
19401 || INTVAL (operands[2]) == 9)"
19402 [(set (match_dup 0)
19403 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19405 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19409 [(set (match_operand:DI 0 "register_operand" "")
19410 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19411 (match_operand:DI 2 "const_int_operand" "")))
19412 (clobber (reg:CC FLAGS_REG))])]
19415 && (INTVAL (operands[2]) == 3
19416 || INTVAL (operands[2]) == 5
19417 || INTVAL (operands[2]) == 9)"
19418 [(set (match_dup 0) (match_dup 1))
19420 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19422 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19424 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19425 ;; imul $32bit_imm, reg, reg is direct decoded.
19427 [(match_scratch:DI 3 "r")
19428 (parallel [(set (match_operand:DI 0 "register_operand" "")
19429 (mult:DI (match_operand:DI 1 "memory_operand" "")
19430 (match_operand:DI 2 "immediate_operand" "")))
19431 (clobber (reg:CC FLAGS_REG))])]
19432 "TARGET_K8 && !optimize_size
19433 && (GET_CODE (operands[2]) != CONST_INT
19434 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19435 [(set (match_dup 3) (match_dup 1))
19436 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19437 (clobber (reg:CC FLAGS_REG))])]
19441 [(match_scratch:SI 3 "r")
19442 (parallel [(set (match_operand:SI 0 "register_operand" "")
19443 (mult:SI (match_operand:SI 1 "memory_operand" "")
19444 (match_operand:SI 2 "immediate_operand" "")))
19445 (clobber (reg:CC FLAGS_REG))])]
19446 "TARGET_K8 && !optimize_size
19447 && (GET_CODE (operands[2]) != CONST_INT
19448 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19449 [(set (match_dup 3) (match_dup 1))
19450 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19451 (clobber (reg:CC FLAGS_REG))])]
19455 [(match_scratch:SI 3 "r")
19456 (parallel [(set (match_operand:DI 0 "register_operand" "")
19458 (mult:SI (match_operand:SI 1 "memory_operand" "")
19459 (match_operand:SI 2 "immediate_operand" ""))))
19460 (clobber (reg:CC FLAGS_REG))])]
19461 "TARGET_K8 && !optimize_size
19462 && (GET_CODE (operands[2]) != CONST_INT
19463 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19464 [(set (match_dup 3) (match_dup 1))
19465 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19466 (clobber (reg:CC FLAGS_REG))])]
19469 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19470 ;; Convert it into imul reg, reg
19471 ;; It would be better to force assembler to encode instruction using long
19472 ;; immediate, but there is apparently no way to do so.
19474 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19475 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19476 (match_operand:DI 2 "const_int_operand" "")))
19477 (clobber (reg:CC FLAGS_REG))])
19478 (match_scratch:DI 3 "r")]
19479 "TARGET_K8 && !optimize_size
19480 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19481 [(set (match_dup 3) (match_dup 2))
19482 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19483 (clobber (reg:CC FLAGS_REG))])]
19485 if (!rtx_equal_p (operands[0], operands[1]))
19486 emit_move_insn (operands[0], operands[1]);
19490 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19491 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19492 (match_operand:SI 2 "const_int_operand" "")))
19493 (clobber (reg:CC FLAGS_REG))])
19494 (match_scratch:SI 3 "r")]
19495 "TARGET_K8 && !optimize_size
19496 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19497 [(set (match_dup 3) (match_dup 2))
19498 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19499 (clobber (reg:CC FLAGS_REG))])]
19501 if (!rtx_equal_p (operands[0], operands[1]))
19502 emit_move_insn (operands[0], operands[1]);
19506 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19507 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19508 (match_operand:HI 2 "immediate_operand" "")))
19509 (clobber (reg:CC FLAGS_REG))])
19510 (match_scratch:HI 3 "r")]
19511 "TARGET_K8 && !optimize_size"
19512 [(set (match_dup 3) (match_dup 2))
19513 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19514 (clobber (reg:CC FLAGS_REG))])]
19516 if (!rtx_equal_p (operands[0], operands[1]))
19517 emit_move_insn (operands[0], operands[1]);
19520 ;; Call-value patterns last so that the wildcard operand does not
19521 ;; disrupt insn-recog's switch tables.
19523 (define_insn "*call_value_pop_0"
19524 [(set (match_operand 0 "" "")
19525 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19526 (match_operand:SI 2 "" "")))
19527 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19528 (match_operand:SI 3 "immediate_operand" "")))]
19531 if (SIBLING_CALL_P (insn))
19534 return "call\t%P1";
19536 [(set_attr "type" "callv")])
19538 (define_insn "*call_value_pop_1"
19539 [(set (match_operand 0 "" "")
19540 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19541 (match_operand:SI 2 "" "")))
19542 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19543 (match_operand:SI 3 "immediate_operand" "i")))]
19546 if (constant_call_address_operand (operands[1], Pmode))
19548 if (SIBLING_CALL_P (insn))
19551 return "call\t%P1";
19553 if (SIBLING_CALL_P (insn))
19556 return "call\t%A1";
19558 [(set_attr "type" "callv")])
19560 (define_insn "*call_value_0"
19561 [(set (match_operand 0 "" "")
19562 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19563 (match_operand:SI 2 "" "")))]
19566 if (SIBLING_CALL_P (insn))
19569 return "call\t%P1";
19571 [(set_attr "type" "callv")])
19573 (define_insn "*call_value_0_rex64"
19574 [(set (match_operand 0 "" "")
19575 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19576 (match_operand:DI 2 "const_int_operand" "")))]
19579 if (SIBLING_CALL_P (insn))
19582 return "call\t%P1";
19584 [(set_attr "type" "callv")])
19586 (define_insn "*call_value_1"
19587 [(set (match_operand 0 "" "")
19588 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19589 (match_operand:SI 2 "" "")))]
19590 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19592 if (constant_call_address_operand (operands[1], Pmode))
19593 return "call\t%P1";
19594 return "call\t%A1";
19596 [(set_attr "type" "callv")])
19598 (define_insn "*sibcall_value_1"
19599 [(set (match_operand 0 "" "")
19600 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19601 (match_operand:SI 2 "" "")))]
19602 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19604 if (constant_call_address_operand (operands[1], Pmode))
19608 [(set_attr "type" "callv")])
19610 (define_insn "*call_value_1_rex64"
19611 [(set (match_operand 0 "" "")
19612 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19613 (match_operand:DI 2 "" "")))]
19614 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19616 if (constant_call_address_operand (operands[1], Pmode))
19617 return "call\t%P1";
19618 return "call\t%A1";
19620 [(set_attr "type" "callv")])
19622 (define_insn "*sibcall_value_1_rex64"
19623 [(set (match_operand 0 "" "")
19624 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19625 (match_operand:DI 2 "" "")))]
19626 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19628 [(set_attr "type" "callv")])
19630 (define_insn "*sibcall_value_1_rex64_v"
19631 [(set (match_operand 0 "" "")
19632 (call (mem:QI (reg:DI 40))
19633 (match_operand:DI 1 "" "")))]
19634 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19636 [(set_attr "type" "callv")])
19638 (define_insn "trap"
19639 [(trap_if (const_int 1) (const_int 5))]
19643 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19644 ;;; for the sake of bounds checking. By emitting bounds checks as
19645 ;;; conditional traps rather than as conditional jumps around
19646 ;;; unconditional traps we avoid introducing spurious basic-block
19647 ;;; boundaries and facilitate elimination of redundant checks. In
19648 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19651 ;;; FIXME: Static branch prediction rules for ix86 are such that
19652 ;;; forward conditional branches predict as untaken. As implemented
19653 ;;; below, pseudo conditional traps violate that rule. We should use
19654 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19655 ;;; section loaded at the end of the text segment and branch forward
19656 ;;; there on bounds-failure, and then jump back immediately (in case
19657 ;;; the system chooses to ignore bounds violations, or to report
19658 ;;; violations and continue execution).
19660 (define_expand "conditional_trap"
19661 [(trap_if (match_operator 0 "comparison_operator"
19662 [(match_dup 2) (const_int 0)])
19663 (match_operand 1 "const_int_operand" ""))]
19666 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19667 ix86_expand_compare (GET_CODE (operands[0]),
19673 (define_insn "*conditional_trap_1"
19674 [(trap_if (match_operator 0 "comparison_operator"
19675 [(reg FLAGS_REG) (const_int 0)])
19676 (match_operand 1 "const_int_operand" ""))]
19679 operands[2] = gen_label_rtx ();
19680 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19681 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19682 CODE_LABEL_NUMBER (operands[2]));
19686 ;; Pentium III SIMD instructions.
19688 ;; Moves for SSE/MMX regs.
19690 (define_expand "movv4sf"
19691 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19692 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
19695 ix86_expand_vector_move (V4SFmode, operands);
19699 (define_insn "*movv4sf_internal"
19700 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
19701 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
19705 movaps\t{%1, %0|%0, %1}
19706 movaps\t{%1, %0|%0, %1}"
19707 [(set_attr "type" "ssemov")
19708 (set_attr "mode" "V4SF")])
19711 [(set (match_operand:V4SF 0 "register_operand" "")
19712 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
19713 "TARGET_SSE && reload_completed"
19714 [(set (match_dup 0)
19716 (vec_duplicate:V4SF (match_dup 1))
19720 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
19721 operands[2] = CONST0_RTX (V4SFmode);
19724 (define_expand "movv2df"
19725 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
19726 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
19729 ix86_expand_vector_move (V2DFmode, operands);
19733 (define_insn "*movv2df_internal"
19734 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
19735 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
19737 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19739 switch (which_alternative)
19742 if (get_attr_mode (insn) == MODE_V4SF)
19743 return "xorps\t%0, %0";
19745 return "xorpd\t%0, %0";
19748 if (get_attr_mode (insn) == MODE_V4SF)
19749 return "movaps\t{%1, %0|%0, %1}";
19751 return "movapd\t{%1, %0|%0, %1}";
19756 [(set_attr "type" "ssemov")
19758 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
19759 (const_string "V4SF")
19760 (eq_attr "alternative" "0,1")
19762 (ne (symbol_ref "optimize_size")
19764 (const_string "V4SF")
19765 (const_string "V2DF"))
19766 (eq_attr "alternative" "2")
19768 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19770 (ne (symbol_ref "optimize_size")
19772 (const_string "V4SF")
19773 (const_string "V2DF"))]
19774 (const_string "V2DF")))])
19777 [(set (match_operand:V2DF 0 "register_operand" "")
19778 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
19779 "TARGET_SSE2 && reload_completed"
19780 [(set (match_dup 0)
19782 (vec_duplicate:V2DF (match_dup 1))
19786 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
19787 operands[2] = CONST0_RTX (V2DFmode);
19790 ;; 16 byte integral modes handled by SSE, minus TImode, which gets
19791 ;; special-cased for TARGET_64BIT.
19792 (define_mode_macro SSEMODEI [V16QI V8HI V4SI V2DI])
19794 (define_expand "mov<mode>"
19795 [(set (match_operand:SSEMODEI 0 "nonimmediate_operand" "")
19796 (match_operand:SSEMODEI 1 "nonimmediate_operand" ""))]
19799 ix86_expand_vector_move (<MODE>mode, operands);
19803 (define_insn "*mov<mode>_internal"
19804 [(set (match_operand:SSEMODEI 0 "nonimmediate_operand" "=x,x ,m")
19805 (match_operand:SSEMODEI 1 "vector_move_operand" "C ,xm,x"))]
19807 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19809 switch (which_alternative)
19812 if (get_attr_mode (insn) == MODE_V4SF)
19813 return "xorps\t%0, %0";
19815 return "pxor\t%0, %0";
19818 if (get_attr_mode (insn) == MODE_V4SF)
19819 return "movaps\t{%1, %0|%0, %1}";
19821 return "movdqa\t{%1, %0|%0, %1}";
19826 [(set_attr "type" "ssemov")
19828 (cond [(eq_attr "alternative" "0,1")
19830 (ne (symbol_ref "optimize_size")
19832 (const_string "V4SF")
19833 (const_string "TI"))
19834 (eq_attr "alternative" "2")
19836 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19838 (ne (symbol_ref "optimize_size")
19840 (const_string "V4SF")
19841 (const_string "TI"))]
19842 (const_string "TI")))])
19844 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
19845 (define_mode_macro MMXMODEI [V8QI V4HI V2SI])
19847 (define_expand "mov<mode>"
19848 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" "")
19849 (match_operand:MMXMODEI 1 "nonimmediate_operand" ""))]
19852 ix86_expand_vector_move (<MODE>mode, operands);
19856 (define_insn "*mov<mode>_internal"
19857 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
19858 "=y,y ,m,!y,!*Y,*x,?*x,?m")
19859 (match_operand:MMXMODEI 1 "vector_move_operand"
19860 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
19862 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19865 movq\t{%1, %0|%0, %1}
19866 movq\t{%1, %0|%0, %1}
19867 movdq2q\t{%1, %0|%0, %1}
19868 movq2dq\t{%1, %0|%0, %1}
19870 movq\t{%1, %0|%0, %1}
19871 movq\t{%1, %0|%0, %1}"
19872 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
19873 (set_attr "mode" "DI")])
19875 (define_expand "movv2sf"
19876 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19877 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19880 ix86_expand_vector_move (V2SFmode, operands);
19884 (define_insn "*movv2sf_internal"
19885 [(set (match_operand:V2SF 0 "nonimmediate_operand"
19886 "=y,y ,m,!y,!*Y,*x,?*x,?m")
19887 (match_operand:V2SF 1 "vector_move_operand"
19888 "C ,ym,y,*Y,y ,C ,*xm,*x"))]
19890 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19893 movq\t{%1, %0|%0, %1}
19894 movq\t{%1, %0|%0, %1}
19895 movdq2q\t{%1, %0|%0, %1}
19896 movq2dq\t{%1, %0|%0, %1}
19898 movlps\t{%1, %0|%0, %1}
19899 movlps\t{%1, %0|%0, %1}"
19900 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
19901 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V2SF,V2SF")])
19903 (define_expand "movti"
19904 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19905 (match_operand:TI 1 "nonimmediate_operand" ""))]
19906 "TARGET_SSE || TARGET_64BIT"
19909 ix86_expand_move (TImode, operands);
19911 ix86_expand_vector_move (TImode, operands);
19915 (define_insn "*movti_internal"
19916 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19917 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19918 "TARGET_SSE && !TARGET_64BIT
19919 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19921 switch (which_alternative)
19924 if (get_attr_mode (insn) == MODE_V4SF)
19925 return "xorps\t%0, %0";
19927 return "pxor\t%0, %0";
19930 if (get_attr_mode (insn) == MODE_V4SF)
19931 return "movaps\t{%1, %0|%0, %1}";
19933 return "movdqa\t{%1, %0|%0, %1}";
19938 [(set_attr "type" "ssemov,ssemov,ssemov")
19940 (cond [(eq_attr "alternative" "0,1")
19942 (ne (symbol_ref "optimize_size")
19944 (const_string "V4SF")
19945 (const_string "TI"))
19946 (eq_attr "alternative" "2")
19948 (ne (symbol_ref "optimize_size")
19950 (const_string "V4SF")
19951 (const_string "TI"))]
19952 (const_string "TI")))])
19954 (define_insn "*movti_rex64"
19955 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
19956 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
19958 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19960 switch (which_alternative)
19966 if (get_attr_mode (insn) == MODE_V4SF)
19967 return "xorps\t%0, %0";
19969 return "pxor\t%0, %0";
19972 if (get_attr_mode (insn) == MODE_V4SF)
19973 return "movaps\t{%1, %0|%0, %1}";
19975 return "movdqa\t{%1, %0|%0, %1}";
19980 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19982 (cond [(eq_attr "alternative" "2,3")
19984 (ne (symbol_ref "optimize_size")
19986 (const_string "V4SF")
19987 (const_string "TI"))
19988 (eq_attr "alternative" "4")
19990 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19992 (ne (symbol_ref "optimize_size")
19994 (const_string "V4SF")
19995 (const_string "TI"))]
19996 (const_string "DI")))])
19998 (define_expand "movtf"
19999 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20000 (match_operand:TF 1 "nonimmediate_operand" ""))]
20003 ix86_expand_move (TFmode, operands);
20007 (define_insn "*movtf_internal"
20008 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
20009 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
20011 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20013 switch (which_alternative)
20019 if (get_attr_mode (insn) == MODE_V4SF)
20020 return "xorps\t%0, %0";
20022 return "pxor\t%0, %0";
20025 if (get_attr_mode (insn) == MODE_V4SF)
20026 return "movaps\t{%1, %0|%0, %1}";
20028 return "movdqa\t{%1, %0|%0, %1}";
20033 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
20035 (cond [(eq_attr "alternative" "2,3")
20037 (ne (symbol_ref "optimize_size")
20039 (const_string "V4SF")
20040 (const_string "TI"))
20041 (eq_attr "alternative" "4")
20043 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
20045 (ne (symbol_ref "optimize_size")
20047 (const_string "V4SF")
20048 (const_string "TI"))]
20049 (const_string "DI")))])
20051 (define_mode_macro SSEPUSH [V16QI V8HI V4SI V2DI TI V4SF V2DF])
20053 (define_insn "*push<mode>"
20054 [(set (match_operand:SSEPUSH 0 "push_operand" "=<")
20055 (match_operand:SSEPUSH 1 "register_operand" "x"))]
20059 (define_mode_macro MMXPUSH [V8QI V4HI V2SI V2SF])
20061 (define_insn "*push<mode>"
20062 [(set (match_operand:MMXPUSH 0 "push_operand" "=<")
20063 (match_operand:MMXPUSH 1 "register_operand" "xy"))]
20068 [(set (match_operand 0 "push_operand" "")
20069 (match_operand 1 "register_operand" ""))]
20070 "!TARGET_64BIT && reload_completed
20071 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20072 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
20073 (set (match_dup 2) (match_dup 1))]
20074 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20075 stack_pointer_rtx);
20076 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20079 [(set (match_operand 0 "push_operand" "")
20080 (match_operand 1 "register_operand" ""))]
20081 "TARGET_64BIT && reload_completed
20082 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
20083 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
20084 (set (match_dup 2) (match_dup 1))]
20085 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
20086 stack_pointer_rtx);
20087 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
20091 [(set (match_operand:TI 0 "nonimmediate_operand" "")
20092 (match_operand:TI 1 "general_operand" ""))]
20093 "reload_completed && !SSE_REG_P (operands[0])
20094 && !SSE_REG_P (operands[1])"
20096 "ix86_split_long_move (operands); DONE;")
20099 [(set (match_operand:TF 0 "nonimmediate_operand" "")
20100 (match_operand:TF 1 "general_operand" ""))]
20101 "reload_completed && !SSE_REG_P (operands[0])
20102 && !SSE_REG_P (operands[1])"
20104 "ix86_split_long_move (operands); DONE;")
20106 ;; All 16-byte vector modes handled by SSE
20107 (define_mode_macro SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
20109 (define_expand "movmisalign<mode>"
20110 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
20111 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
20114 ix86_expand_vector_move_misalign (<MODE>mode, operands);
20118 ;; All 8-byte vector modes handled by MMX
20119 (define_mode_macro MMXMODE [V8QI V4HI V2SI V2SF])
20121 (define_expand "movmisalign<mode>"
20122 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
20123 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
20126 ix86_expand_vector_move (<MODE>mode, operands);
20130 ;; These two patterns are useful for specifying exactly whether to use
20131 ;; movaps or movups
20132 (define_expand "sse_movaps"
20133 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20134 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20138 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20140 rtx tmp = gen_reg_rtx (V4SFmode);
20141 emit_insn (gen_sse_movaps (tmp, operands[1]));
20142 emit_move_insn (operands[0], tmp);
20147 (define_insn "*sse_movaps_1"
20148 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20149 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20152 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20153 "movaps\t{%1, %0|%0, %1}"
20154 [(set_attr "type" "ssemov,ssemov")
20155 (set_attr "mode" "V4SF")])
20157 (define_expand "sse_movups"
20158 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
20159 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
20163 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
20165 rtx tmp = gen_reg_rtx (V4SFmode);
20166 emit_insn (gen_sse_movups (tmp, operands[1]));
20167 emit_move_insn (operands[0], tmp);
20172 (define_insn "*sse_movups_1"
20173 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20174 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
20177 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
20178 "movups\t{%1, %0|%0, %1}"
20179 [(set_attr "type" "ssecvt,ssecvt")
20180 (set_attr "mode" "V4SF")])
20182 ;; SSE Strange Moves.
20184 (define_insn "sse_movmskps"
20185 [(set (match_operand:SI 0 "register_operand" "=r")
20186 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
20189 "movmskps\t{%1, %0|%0, %1}"
20190 [(set_attr "type" "ssecvt")
20191 (set_attr "mode" "V4SF")])
20193 (define_insn "mmx_pmovmskb"
20194 [(set (match_operand:SI 0 "register_operand" "=r")
20195 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
20197 "TARGET_SSE || TARGET_3DNOW_A"
20198 "pmovmskb\t{%1, %0|%0, %1}"
20199 [(set_attr "type" "ssecvt")
20200 (set_attr "mode" "V4SF")])
20203 (define_insn "mmx_maskmovq"
20204 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
20205 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20206 (match_operand:V8QI 2 "register_operand" "y")]
20208 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
20209 ;; @@@ check ordering of operands in intel/nonintel syntax
20210 "maskmovq\t{%2, %1|%1, %2}"
20211 [(set_attr "type" "mmxcvt")
20212 (set_attr "mode" "DI")])
20214 (define_insn "mmx_maskmovq_rex"
20215 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
20216 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
20217 (match_operand:V8QI 2 "register_operand" "y")]
20219 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
20220 ;; @@@ check ordering of operands in intel/nonintel syntax
20221 "maskmovq\t{%2, %1|%1, %2}"
20222 [(set_attr "type" "mmxcvt")
20223 (set_attr "mode" "DI")])
20225 (define_insn "sse_movntv4sf"
20226 [(set (match_operand:V4SF 0 "memory_operand" "=m")
20227 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
20230 "movntps\t{%1, %0|%0, %1}"
20231 [(set_attr "type" "ssemov")
20232 (set_attr "mode" "V4SF")])
20234 (define_insn "sse_movntdi"
20235 [(set (match_operand:DI 0 "memory_operand" "=m")
20236 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
20238 "TARGET_SSE || TARGET_3DNOW_A"
20239 "movntq\t{%1, %0|%0, %1}"
20240 [(set_attr "type" "mmxmov")
20241 (set_attr "mode" "DI")])
20243 (define_insn "sse_movhlps"
20244 [(set (match_operand:V4SF 0 "register_operand" "=x")
20246 (match_operand:V4SF 1 "register_operand" "0")
20247 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20248 (parallel [(const_int 2)
20254 "movhlps\t{%2, %0|%0, %2}"
20255 [(set_attr "type" "ssecvt")
20256 (set_attr "mode" "V4SF")])
20258 (define_insn "sse_movlhps"
20259 [(set (match_operand:V4SF 0 "register_operand" "=x")
20261 (match_operand:V4SF 1 "register_operand" "0")
20262 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20263 (parallel [(const_int 2)
20269 "movlhps\t{%2, %0|%0, %2}"
20270 [(set_attr "type" "ssecvt")
20271 (set_attr "mode" "V4SF")])
20273 (define_insn "sse_movhps"
20274 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20276 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20277 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20280 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20281 "movhps\t{%2, %0|%0, %2}"
20282 [(set_attr "type" "ssecvt")
20283 (set_attr "mode" "V4SF")])
20285 (define_insn "sse_movlps"
20286 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
20288 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
20289 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
20292 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
20293 "movlps\t{%2, %0|%0, %2}"
20294 [(set_attr "type" "ssecvt")
20295 (set_attr "mode" "V4SF")])
20297 (define_expand "sse_loadss"
20298 [(match_operand:V4SF 0 "register_operand" "")
20299 (match_operand:SF 1 "memory_operand" "")]
20302 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
20303 CONST0_RTX (V4SFmode)));
20307 (define_insn "sse_loadss_1"
20308 [(set (match_operand:V4SF 0 "register_operand" "=x")
20310 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
20311 (match_operand:V4SF 2 "const0_operand" "X")
20314 "movss\t{%1, %0|%0, %1}"
20315 [(set_attr "type" "ssemov")
20316 (set_attr "mode" "SF")])
20318 (define_insn "sse_movss"
20319 [(set (match_operand:V4SF 0 "register_operand" "=x")
20321 (match_operand:V4SF 1 "register_operand" "0")
20322 (match_operand:V4SF 2 "register_operand" "x")
20325 "movss\t{%2, %0|%0, %2}"
20326 [(set_attr "type" "ssemov")
20327 (set_attr "mode" "SF")])
20329 (define_insn "sse_storess"
20330 [(set (match_operand:SF 0 "memory_operand" "=m")
20332 (match_operand:V4SF 1 "register_operand" "x")
20333 (parallel [(const_int 0)])))]
20335 "movss\t{%1, %0|%0, %1}"
20336 [(set_attr "type" "ssemov")
20337 (set_attr "mode" "SF")])
20339 (define_insn "sse_shufps"
20340 [(set (match_operand:V4SF 0 "register_operand" "=x")
20341 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
20342 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
20343 (match_operand:SI 3 "immediate_operand" "i")]
20346 ;; @@@ check operand order for intel/nonintel syntax
20347 "shufps\t{%3, %2, %0|%0, %2, %3}"
20348 [(set_attr "type" "ssecvt")
20349 (set_attr "mode" "V4SF")])
20354 (define_insn "addv4sf3"
20355 [(set (match_operand:V4SF 0 "register_operand" "=x")
20356 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20357 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20359 "addps\t{%2, %0|%0, %2}"
20360 [(set_attr "type" "sseadd")
20361 (set_attr "mode" "V4SF")])
20363 (define_insn "vmaddv4sf3"
20364 [(set (match_operand:V4SF 0 "register_operand" "=x")
20366 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20367 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20371 "addss\t{%2, %0|%0, %2}"
20372 [(set_attr "type" "sseadd")
20373 (set_attr "mode" "SF")])
20375 (define_insn "subv4sf3"
20376 [(set (match_operand:V4SF 0 "register_operand" "=x")
20377 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20378 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20380 "subps\t{%2, %0|%0, %2}"
20381 [(set_attr "type" "sseadd")
20382 (set_attr "mode" "V4SF")])
20384 (define_insn "vmsubv4sf3"
20385 [(set (match_operand:V4SF 0 "register_operand" "=x")
20387 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
20388 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20392 "subss\t{%2, %0|%0, %2}"
20393 [(set_attr "type" "sseadd")
20394 (set_attr "mode" "SF")])
20396 ;; ??? Should probably be done by generic code instead.
20397 (define_expand "negv4sf2"
20398 [(set (match_operand:V4SF 0 "register_operand" "")
20399 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
20403 rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
20404 rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
20405 operands[2] = force_reg (V4SFmode, vm0);
20408 (define_insn "mulv4sf3"
20409 [(set (match_operand:V4SF 0 "register_operand" "=x")
20410 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20411 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20413 "mulps\t{%2, %0|%0, %2}"
20414 [(set_attr "type" "ssemul")
20415 (set_attr "mode" "V4SF")])
20417 (define_insn "vmmulv4sf3"
20418 [(set (match_operand:V4SF 0 "register_operand" "=x")
20420 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
20421 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20425 "mulss\t{%2, %0|%0, %2}"
20426 [(set_attr "type" "ssemul")
20427 (set_attr "mode" "SF")])
20429 (define_insn "divv4sf3"
20430 [(set (match_operand:V4SF 0 "register_operand" "=x")
20431 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20432 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20434 "divps\t{%2, %0|%0, %2}"
20435 [(set_attr "type" "ssediv")
20436 (set_attr "mode" "V4SF")])
20438 (define_insn "vmdivv4sf3"
20439 [(set (match_operand:V4SF 0 "register_operand" "=x")
20441 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20442 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20446 "divss\t{%2, %0|%0, %2}"
20447 [(set_attr "type" "ssediv")
20448 (set_attr "mode" "SF")])
20451 ;; SSE square root/reciprocal
20453 (define_insn "rcpv4sf2"
20454 [(set (match_operand:V4SF 0 "register_operand" "=x")
20456 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
20458 "rcpps\t{%1, %0|%0, %1}"
20459 [(set_attr "type" "sse")
20460 (set_attr "mode" "V4SF")])
20462 (define_insn "vmrcpv4sf2"
20463 [(set (match_operand:V4SF 0 "register_operand" "=x")
20465 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20467 (match_operand:V4SF 2 "register_operand" "0")
20470 "rcpss\t{%1, %0|%0, %1}"
20471 [(set_attr "type" "sse")
20472 (set_attr "mode" "SF")])
20474 (define_insn "rsqrtv4sf2"
20475 [(set (match_operand:V4SF 0 "register_operand" "=x")
20477 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
20479 "rsqrtps\t{%1, %0|%0, %1}"
20480 [(set_attr "type" "sse")
20481 (set_attr "mode" "V4SF")])
20483 (define_insn "vmrsqrtv4sf2"
20484 [(set (match_operand:V4SF 0 "register_operand" "=x")
20486 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20488 (match_operand:V4SF 2 "register_operand" "0")
20491 "rsqrtss\t{%1, %0|%0, %1}"
20492 [(set_attr "type" "sse")
20493 (set_attr "mode" "SF")])
20495 (define_insn "sqrtv4sf2"
20496 [(set (match_operand:V4SF 0 "register_operand" "=x")
20497 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20499 "sqrtps\t{%1, %0|%0, %1}"
20500 [(set_attr "type" "sse")
20501 (set_attr "mode" "V4SF")])
20503 (define_insn "vmsqrtv4sf2"
20504 [(set (match_operand:V4SF 0 "register_operand" "=x")
20506 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20507 (match_operand:V4SF 2 "register_operand" "0")
20510 "sqrtss\t{%1, %0|%0, %1}"
20511 [(set_attr "type" "sse")
20512 (set_attr "mode" "SF")])
20514 ;; SSE logical operations.
20516 ;; SSE defines logical operations on floating point values. This brings
20517 ;; interesting challenge to RTL representation where logicals are only valid
20518 ;; on integral types. We deal with this by representing the floating point
20519 ;; logical as logical on arguments casted to TImode as this is what hardware
20520 ;; really does. Unfortunately hardware requires the type information to be
20521 ;; present and thus we must avoid subregs from being simplified and eliminated
20522 ;; in later compilation phases.
20524 ;; We have following variants from each instruction:
20525 ;; sse_andsf3 - the operation taking V4SF vector operands
20526 ;; and doing TImode cast on them
20527 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
20528 ;; TImode, since backend insist on eliminating casts
20529 ;; on memory operands
20530 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
20531 ;; We cannot accept memory operand here as instruction reads
20532 ;; whole scalar. This is generated only post reload by GCC
20533 ;; scalar float operations that expands to logicals (fabs)
20534 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
20535 ;; memory operand. Eventually combine can be able
20536 ;; to synthesize these using splitter.
20537 ;; sse2_anddf3, *sse2_anddf3_memory
20540 ;; These are not called andti3 etc. because we really really don't want
20541 ;; the compiler to widen DImode ands to TImode ands and then try to move
20542 ;; into DImode subregs of SSE registers, and them together, and move out
20543 ;; of DImode subregs again!
20544 ;; SSE1 single precision floating point logical operation
20545 (define_expand "sse_andv4sf3"
20546 [(set (match_operand:V4SF 0 "register_operand" "")
20547 (and:V4SF (match_operand:V4SF 1 "register_operand" "")
20548 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20552 (define_insn "*sse_andv4sf3"
20553 [(set (match_operand:V4SF 0 "register_operand" "=x")
20554 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20555 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20557 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20558 "andps\t{%2, %0|%0, %2}"
20559 [(set_attr "type" "sselog")
20560 (set_attr "mode" "V4SF")])
20562 (define_expand "sse_nandv4sf3"
20563 [(set (match_operand:V4SF 0 "register_operand" "")
20564 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
20565 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20569 (define_insn "*sse_nandv4sf3"
20570 [(set (match_operand:V4SF 0 "register_operand" "=x")
20571 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
20572 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20574 "andnps\t{%2, %0|%0, %2}"
20575 [(set_attr "type" "sselog")
20576 (set_attr "mode" "V4SF")])
20578 (define_expand "sse_iorv4sf3"
20579 [(set (match_operand:V4SF 0 "register_operand" "")
20580 (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
20581 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20585 (define_insn "*sse_iorv4sf3"
20586 [(set (match_operand:V4SF 0 "register_operand" "=x")
20587 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20588 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20590 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20591 "orps\t{%2, %0|%0, %2}"
20592 [(set_attr "type" "sselog")
20593 (set_attr "mode" "V4SF")])
20595 (define_expand "sse_xorv4sf3"
20596 [(set (match_operand:V4SF 0 "register_operand" "")
20597 (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
20598 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
20602 (define_insn "*sse_xorv4sf3"
20603 [(set (match_operand:V4SF 0 "register_operand" "=x")
20604 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
20605 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20607 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20608 "xorps\t{%2, %0|%0, %2}"
20609 [(set_attr "type" "sselog")
20610 (set_attr "mode" "V4SF")])
20612 ;; SSE2 double precision floating point logical operation
20614 (define_expand "sse2_andv2df3"
20615 [(set (match_operand:V2DF 0 "register_operand" "")
20616 (and:V2DF (match_operand:V2DF 1 "register_operand" "")
20617 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20621 (define_insn "*sse2_andv2df3"
20622 [(set (match_operand:V2DF 0 "register_operand" "=x")
20623 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20624 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20626 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20627 "andpd\t{%2, %0|%0, %2}"
20628 [(set_attr "type" "sselog")
20629 (set_attr "mode" "V2DF")])
20631 (define_expand "sse2_nandv2df3"
20632 [(set (match_operand:V2DF 0 "register_operand" "")
20633 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
20634 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20638 (define_insn "*sse2_nandv2df3"
20639 [(set (match_operand:V2DF 0 "register_operand" "=x")
20640 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
20641 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20643 "andnpd\t{%2, %0|%0, %2}"
20644 [(set_attr "type" "sselog")
20645 (set_attr "mode" "V2DF")])
20647 (define_expand "sse2_iorv2df3"
20648 [(set (match_operand:V2DF 0 "register_operand" "")
20649 (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
20650 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20654 (define_insn "*sse2_iorv2df3"
20655 [(set (match_operand:V2DF 0 "register_operand" "=x")
20656 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20657 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20659 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20660 "orpd\t{%2, %0|%0, %2}"
20661 [(set_attr "type" "sselog")
20662 (set_attr "mode" "V2DF")])
20664 (define_expand "sse2_xorv2df3"
20665 [(set (match_operand:V2DF 0 "register_operand" "")
20666 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
20667 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
20671 (define_insn "*sse2_xorv2df3"
20672 [(set (match_operand:V2DF 0 "register_operand" "=x")
20673 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
20674 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
20676 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20677 "xorpd\t{%2, %0|%0, %2}"
20678 [(set_attr "type" "sselog")
20679 (set_attr "mode" "V2DF")])
20681 ;; SSE2 integral logicals. These patterns must always come after floating
20682 ;; point ones since we don't want compiler to use integer opcodes on floating
20683 ;; point SSE values to avoid matching of subregs in the match_operand.
20684 (define_insn "*sse2_andti3"
20685 [(set (match_operand:TI 0 "register_operand" "=x")
20686 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20687 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20689 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20690 "pand\t{%2, %0|%0, %2}"
20691 [(set_attr "type" "sselog")
20692 (set_attr "mode" "TI")])
20694 (define_insn "sse2_andv2di3"
20695 [(set (match_operand:V2DI 0 "register_operand" "=x")
20696 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20697 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20699 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20700 "pand\t{%2, %0|%0, %2}"
20701 [(set_attr "type" "sselog")
20702 (set_attr "mode" "TI")])
20704 (define_insn "*sse2_nandti3"
20705 [(set (match_operand:TI 0 "register_operand" "=x")
20706 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20707 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20709 "pandn\t{%2, %0|%0, %2}"
20710 [(set_attr "type" "sselog")
20711 (set_attr "mode" "TI")])
20713 (define_insn "sse2_nandv2di3"
20714 [(set (match_operand:V2DI 0 "register_operand" "=x")
20715 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
20716 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20718 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20719 "pandn\t{%2, %0|%0, %2}"
20720 [(set_attr "type" "sselog")
20721 (set_attr "mode" "TI")])
20723 (define_insn "*sse2_iorti3"
20724 [(set (match_operand:TI 0 "register_operand" "=x")
20725 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20726 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20728 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20729 "por\t{%2, %0|%0, %2}"
20730 [(set_attr "type" "sselog")
20731 (set_attr "mode" "TI")])
20733 (define_insn "sse2_iorv2di3"
20734 [(set (match_operand:V2DI 0 "register_operand" "=x")
20735 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20736 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20738 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20739 "por\t{%2, %0|%0, %2}"
20740 [(set_attr "type" "sselog")
20741 (set_attr "mode" "TI")])
20743 (define_insn "*sse2_xorti3"
20744 [(set (match_operand:TI 0 "register_operand" "=x")
20745 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20746 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20748 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20749 "pxor\t{%2, %0|%0, %2}"
20750 [(set_attr "type" "sselog")
20751 (set_attr "mode" "TI")])
20753 (define_insn "sse2_xorv2di3"
20754 [(set (match_operand:V2DI 0 "register_operand" "=x")
20755 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20756 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20758 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20759 "pxor\t{%2, %0|%0, %2}"
20760 [(set_attr "type" "sselog")
20761 (set_attr "mode" "TI")])
20763 ;; Use xor, but don't show input operands so they aren't live before
20765 (define_insn "sse_clrv4sf"
20766 [(set (match_operand:V4SF 0 "register_operand" "=x")
20767 (match_operand:V4SF 1 "const0_operand" "X"))]
20770 if (get_attr_mode (insn) == MODE_TI)
20771 return "pxor\t{%0, %0|%0, %0}";
20773 return "xorps\t{%0, %0|%0, %0}";
20775 [(set_attr "type" "sselog")
20776 (set_attr "memory" "none")
20779 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
20781 (ne (symbol_ref "TARGET_SSE2")
20783 (eq (symbol_ref "optimize_size")
20785 (const_string "TI")
20786 (const_string "V4SF")))])
20788 ;; Use xor, but don't show input operands so they aren't live before
20790 (define_insn "sse_clrv2df"
20791 [(set (match_operand:V2DF 0 "register_operand" "=x")
20792 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
20794 "xorpd\t{%0, %0|%0, %0}"
20795 [(set_attr "type" "sselog")
20796 (set_attr "memory" "none")
20797 (set_attr "mode" "V4SF")])
20799 ;; SSE mask-generating compares
20801 (define_insn "maskcmpv4sf3"
20802 [(set (match_operand:V4SI 0 "register_operand" "=x")
20803 (match_operator:V4SI 3 "sse_comparison_operator"
20804 [(match_operand:V4SF 1 "register_operand" "0")
20805 (match_operand:V4SF 2 "register_operand" "x")]))]
20807 "cmp%D3ps\t{%2, %0|%0, %2}"
20808 [(set_attr "type" "ssecmp")
20809 (set_attr "mode" "V4SF")])
20811 (define_insn "maskncmpv4sf3"
20812 [(set (match_operand:V4SI 0 "register_operand" "=x")
20814 (match_operator:V4SI 3 "sse_comparison_operator"
20815 [(match_operand:V4SF 1 "register_operand" "0")
20816 (match_operand:V4SF 2 "register_operand" "x")])))]
20819 if (GET_CODE (operands[3]) == UNORDERED)
20820 return "cmpordps\t{%2, %0|%0, %2}";
20822 return "cmpn%D3ps\t{%2, %0|%0, %2}";
20824 [(set_attr "type" "ssecmp")
20825 (set_attr "mode" "V4SF")])
20827 (define_insn "vmmaskcmpv4sf3"
20828 [(set (match_operand:V4SI 0 "register_operand" "=x")
20830 (match_operator:V4SI 3 "sse_comparison_operator"
20831 [(match_operand:V4SF 1 "register_operand" "0")
20832 (match_operand:V4SF 2 "register_operand" "x")])
20833 (subreg:V4SI (match_dup 1) 0)
20836 "cmp%D3ss\t{%2, %0|%0, %2}"
20837 [(set_attr "type" "ssecmp")
20838 (set_attr "mode" "SF")])
20840 (define_insn "vmmaskncmpv4sf3"
20841 [(set (match_operand:V4SI 0 "register_operand" "=x")
20844 (match_operator:V4SI 3 "sse_comparison_operator"
20845 [(match_operand:V4SF 1 "register_operand" "0")
20846 (match_operand:V4SF 2 "register_operand" "x")]))
20847 (subreg:V4SI (match_dup 1) 0)
20851 if (GET_CODE (operands[3]) == UNORDERED)
20852 return "cmpordss\t{%2, %0|%0, %2}";
20854 return "cmpn%D3ss\t{%2, %0|%0, %2}";
20856 [(set_attr "type" "ssecmp")
20857 (set_attr "mode" "SF")])
20859 (define_insn "sse_comi"
20860 [(set (reg:CCFP FLAGS_REG)
20861 (compare:CCFP (vec_select:SF
20862 (match_operand:V4SF 0 "register_operand" "x")
20863 (parallel [(const_int 0)]))
20865 (match_operand:V4SF 1 "register_operand" "x")
20866 (parallel [(const_int 0)]))))]
20868 "comiss\t{%1, %0|%0, %1}"
20869 [(set_attr "type" "ssecomi")
20870 (set_attr "mode" "SF")])
20872 (define_insn "sse_ucomi"
20873 [(set (reg:CCFPU FLAGS_REG)
20874 (compare:CCFPU (vec_select:SF
20875 (match_operand:V4SF 0 "register_operand" "x")
20876 (parallel [(const_int 0)]))
20878 (match_operand:V4SF 1 "register_operand" "x")
20879 (parallel [(const_int 0)]))))]
20881 "ucomiss\t{%1, %0|%0, %1}"
20882 [(set_attr "type" "ssecomi")
20883 (set_attr "mode" "SF")])
20888 (define_insn "sse_unpckhps"
20889 [(set (match_operand:V4SF 0 "register_operand" "=x")
20891 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20892 (parallel [(const_int 2)
20896 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20897 (parallel [(const_int 0)
20903 "unpckhps\t{%2, %0|%0, %2}"
20904 [(set_attr "type" "ssecvt")
20905 (set_attr "mode" "V4SF")])
20907 (define_insn "sse_unpcklps"
20908 [(set (match_operand:V4SF 0 "register_operand" "=x")
20910 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20911 (parallel [(const_int 0)
20915 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20916 (parallel [(const_int 2)
20922 "unpcklps\t{%2, %0|%0, %2}"
20923 [(set_attr "type" "ssecvt")
20924 (set_attr "mode" "V4SF")])
20929 (define_insn "smaxv4sf3"
20930 [(set (match_operand:V4SF 0 "register_operand" "=x")
20931 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20932 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20934 "maxps\t{%2, %0|%0, %2}"
20935 [(set_attr "type" "sse")
20936 (set_attr "mode" "V4SF")])
20938 (define_insn "vmsmaxv4sf3"
20939 [(set (match_operand:V4SF 0 "register_operand" "=x")
20941 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20942 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20946 "maxss\t{%2, %0|%0, %2}"
20947 [(set_attr "type" "sse")
20948 (set_attr "mode" "SF")])
20950 (define_insn "sminv4sf3"
20951 [(set (match_operand:V4SF 0 "register_operand" "=x")
20952 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20953 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20955 "minps\t{%2, %0|%0, %2}"
20956 [(set_attr "type" "sse")
20957 (set_attr "mode" "V4SF")])
20959 (define_insn "vmsminv4sf3"
20960 [(set (match_operand:V4SF 0 "register_operand" "=x")
20962 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20963 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20967 "minss\t{%2, %0|%0, %2}"
20968 [(set_attr "type" "sse")
20969 (set_attr "mode" "SF")])
20971 ;; SSE <-> integer/MMX conversions
20973 (define_insn "cvtpi2ps"
20974 [(set (match_operand:V4SF 0 "register_operand" "=x")
20976 (match_operand:V4SF 1 "register_operand" "0")
20977 (vec_duplicate:V4SF
20978 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
20981 "cvtpi2ps\t{%2, %0|%0, %2}"
20982 [(set_attr "type" "ssecvt")
20983 (set_attr "mode" "V4SF")])
20985 (define_insn "cvtps2pi"
20986 [(set (match_operand:V2SI 0 "register_operand" "=y")
20988 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20989 (parallel [(const_int 0) (const_int 1)])))]
20991 "cvtps2pi\t{%1, %0|%0, %1}"
20992 [(set_attr "type" "ssecvt")
20993 (set_attr "mode" "V4SF")])
20995 (define_insn "cvttps2pi"
20996 [(set (match_operand:V2SI 0 "register_operand" "=y")
20998 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21000 (parallel [(const_int 0) (const_int 1)])))]
21002 "cvttps2pi\t{%1, %0|%0, %1}"
21003 [(set_attr "type" "ssecvt")
21004 (set_attr "mode" "SF")])
21006 (define_insn "cvtsi2ss"
21007 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21009 (match_operand:V4SF 1 "register_operand" "0,0")
21010 (vec_duplicate:V4SF
21011 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21014 "cvtsi2ss\t{%2, %0|%0, %2}"
21015 [(set_attr "type" "sseicvt")
21016 (set_attr "athlon_decode" "vector,double")
21017 (set_attr "mode" "SF")])
21019 (define_insn "cvtsi2ssq"
21020 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21022 (match_operand:V4SF 1 "register_operand" "0,0")
21023 (vec_duplicate:V4SF
21024 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21026 "TARGET_SSE && TARGET_64BIT"
21027 "cvtsi2ssq\t{%2, %0|%0, %2}"
21028 [(set_attr "type" "sseicvt")
21029 (set_attr "athlon_decode" "vector,double")
21030 (set_attr "mode" "SF")])
21032 (define_insn "cvtss2si"
21033 [(set (match_operand:SI 0 "register_operand" "=r,r")
21035 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21036 (parallel [(const_int 0)])))]
21038 "cvtss2si\t{%1, %0|%0, %1}"
21039 [(set_attr "type" "sseicvt")
21040 (set_attr "athlon_decode" "double,vector")
21041 (set_attr "mode" "SI")])
21043 (define_insn "cvtss2siq"
21044 [(set (match_operand:DI 0 "register_operand" "=r,r")
21046 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
21047 (parallel [(const_int 0)])))]
21049 "cvtss2siq\t{%1, %0|%0, %1}"
21050 [(set_attr "type" "sseicvt")
21051 (set_attr "athlon_decode" "double,vector")
21052 (set_attr "mode" "DI")])
21054 (define_insn "cvttss2si"
21055 [(set (match_operand:SI 0 "register_operand" "=r,r")
21057 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21059 (parallel [(const_int 0)])))]
21061 "cvttss2si\t{%1, %0|%0, %1}"
21062 [(set_attr "type" "sseicvt")
21063 (set_attr "mode" "SF")
21064 (set_attr "athlon_decode" "double,vector")])
21066 (define_insn "cvttss2siq"
21067 [(set (match_operand:DI 0 "register_operand" "=r,r")
21069 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
21071 (parallel [(const_int 0)])))]
21072 "TARGET_SSE && TARGET_64BIT"
21073 "cvttss2siq\t{%1, %0|%0, %1}"
21074 [(set_attr "type" "sseicvt")
21075 (set_attr "mode" "SF")
21076 (set_attr "athlon_decode" "double,vector")])
21083 (define_insn "addv8qi3"
21084 [(set (match_operand:V8QI 0 "register_operand" "=y")
21085 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21086 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21088 "paddb\t{%2, %0|%0, %2}"
21089 [(set_attr "type" "mmxadd")
21090 (set_attr "mode" "DI")])
21092 (define_insn "addv4hi3"
21093 [(set (match_operand:V4HI 0 "register_operand" "=y")
21094 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21095 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21097 "paddw\t{%2, %0|%0, %2}"
21098 [(set_attr "type" "mmxadd")
21099 (set_attr "mode" "DI")])
21101 (define_insn "addv2si3"
21102 [(set (match_operand:V2SI 0 "register_operand" "=y")
21103 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
21104 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21106 "paddd\t{%2, %0|%0, %2}"
21107 [(set_attr "type" "mmxadd")
21108 (set_attr "mode" "DI")])
21110 (define_insn "mmx_adddi3"
21111 [(set (match_operand:DI 0 "register_operand" "=y")
21113 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
21114 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21117 "paddq\t{%2, %0|%0, %2}"
21118 [(set_attr "type" "mmxadd")
21119 (set_attr "mode" "DI")])
21121 (define_insn "ssaddv8qi3"
21122 [(set (match_operand:V8QI 0 "register_operand" "=y")
21123 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21124 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21126 "paddsb\t{%2, %0|%0, %2}"
21127 [(set_attr "type" "mmxadd")
21128 (set_attr "mode" "DI")])
21130 (define_insn "ssaddv4hi3"
21131 [(set (match_operand:V4HI 0 "register_operand" "=y")
21132 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21133 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21135 "paddsw\t{%2, %0|%0, %2}"
21136 [(set_attr "type" "mmxadd")
21137 (set_attr "mode" "DI")])
21139 (define_insn "usaddv8qi3"
21140 [(set (match_operand:V8QI 0 "register_operand" "=y")
21141 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
21142 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21144 "paddusb\t{%2, %0|%0, %2}"
21145 [(set_attr "type" "mmxadd")
21146 (set_attr "mode" "DI")])
21148 (define_insn "usaddv4hi3"
21149 [(set (match_operand:V4HI 0 "register_operand" "=y")
21150 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
21151 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21153 "paddusw\t{%2, %0|%0, %2}"
21154 [(set_attr "type" "mmxadd")
21155 (set_attr "mode" "DI")])
21157 (define_insn "subv8qi3"
21158 [(set (match_operand:V8QI 0 "register_operand" "=y")
21159 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21160 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21162 "psubb\t{%2, %0|%0, %2}"
21163 [(set_attr "type" "mmxadd")
21164 (set_attr "mode" "DI")])
21166 (define_insn "subv4hi3"
21167 [(set (match_operand:V4HI 0 "register_operand" "=y")
21168 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21169 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21171 "psubw\t{%2, %0|%0, %2}"
21172 [(set_attr "type" "mmxadd")
21173 (set_attr "mode" "DI")])
21175 (define_insn "subv2si3"
21176 [(set (match_operand:V2SI 0 "register_operand" "=y")
21177 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
21178 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21180 "psubd\t{%2, %0|%0, %2}"
21181 [(set_attr "type" "mmxadd")
21182 (set_attr "mode" "DI")])
21184 (define_insn "mmx_subdi3"
21185 [(set (match_operand:DI 0 "register_operand" "=y")
21187 [(minus:DI (match_operand:DI 1 "register_operand" "0")
21188 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21191 "psubq\t{%2, %0|%0, %2}"
21192 [(set_attr "type" "mmxadd")
21193 (set_attr "mode" "DI")])
21195 (define_insn "sssubv8qi3"
21196 [(set (match_operand:V8QI 0 "register_operand" "=y")
21197 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21198 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21200 "psubsb\t{%2, %0|%0, %2}"
21201 [(set_attr "type" "mmxadd")
21202 (set_attr "mode" "DI")])
21204 (define_insn "sssubv4hi3"
21205 [(set (match_operand:V4HI 0 "register_operand" "=y")
21206 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21207 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21209 "psubsw\t{%2, %0|%0, %2}"
21210 [(set_attr "type" "mmxadd")
21211 (set_attr "mode" "DI")])
21213 (define_insn "ussubv8qi3"
21214 [(set (match_operand:V8QI 0 "register_operand" "=y")
21215 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
21216 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21218 "psubusb\t{%2, %0|%0, %2}"
21219 [(set_attr "type" "mmxadd")
21220 (set_attr "mode" "DI")])
21222 (define_insn "ussubv4hi3"
21223 [(set (match_operand:V4HI 0 "register_operand" "=y")
21224 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
21225 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21227 "psubusw\t{%2, %0|%0, %2}"
21228 [(set_attr "type" "mmxadd")
21229 (set_attr "mode" "DI")])
21231 (define_insn "mulv4hi3"
21232 [(set (match_operand:V4HI 0 "register_operand" "=y")
21233 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
21234 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21236 "pmullw\t{%2, %0|%0, %2}"
21237 [(set_attr "type" "mmxmul")
21238 (set_attr "mode" "DI")])
21240 (define_insn "smulv4hi3_highpart"
21241 [(set (match_operand:V4HI 0 "register_operand" "=y")
21244 (mult:V4SI (sign_extend:V4SI
21245 (match_operand:V4HI 1 "register_operand" "0"))
21247 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21250 "pmulhw\t{%2, %0|%0, %2}"
21251 [(set_attr "type" "mmxmul")
21252 (set_attr "mode" "DI")])
21254 (define_insn "umulv4hi3_highpart"
21255 [(set (match_operand:V4HI 0 "register_operand" "=y")
21258 (mult:V4SI (zero_extend:V4SI
21259 (match_operand:V4HI 1 "register_operand" "0"))
21261 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21263 "TARGET_SSE || TARGET_3DNOW_A"
21264 "pmulhuw\t{%2, %0|%0, %2}"
21265 [(set_attr "type" "mmxmul")
21266 (set_attr "mode" "DI")])
21268 (define_insn "mmx_pmaddwd"
21269 [(set (match_operand:V2SI 0 "register_operand" "=y")
21273 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
21274 (parallel [(const_int 0) (const_int 2)])))
21276 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
21277 (parallel [(const_int 0) (const_int 2)]))))
21279 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
21280 (parallel [(const_int 1)
21282 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
21283 (parallel [(const_int 1)
21284 (const_int 3)]))))))]
21286 "pmaddwd\t{%2, %0|%0, %2}"
21287 [(set_attr "type" "mmxmul")
21288 (set_attr "mode" "DI")])
21291 ;; MMX logical operations
21292 ;; Note we don't want to declare these as regular iordi3 insns to prevent
21293 ;; normal code that also wants to use the FPU from getting broken.
21294 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
21295 (define_insn "mmx_iordi3"
21296 [(set (match_operand:DI 0 "register_operand" "=y")
21298 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
21299 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21302 "por\t{%2, %0|%0, %2}"
21303 [(set_attr "type" "mmxadd")
21304 (set_attr "mode" "DI")])
21306 (define_insn "mmx_xordi3"
21307 [(set (match_operand:DI 0 "register_operand" "=y")
21309 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
21310 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21313 "pxor\t{%2, %0|%0, %2}"
21314 [(set_attr "type" "mmxadd")
21315 (set_attr "mode" "DI")
21316 (set_attr "memory" "none")])
21318 ;; Same as pxor, but don't show input operands so that we don't think
21320 (define_insn "mmx_clrdi"
21321 [(set (match_operand:DI 0 "register_operand" "=y")
21322 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
21324 "pxor\t{%0, %0|%0, %0}"
21325 [(set_attr "type" "mmxadd")
21326 (set_attr "mode" "DI")
21327 (set_attr "memory" "none")])
21329 (define_insn "mmx_anddi3"
21330 [(set (match_operand:DI 0 "register_operand" "=y")
21332 [(and:DI (match_operand:DI 1 "register_operand" "%0")
21333 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21336 "pand\t{%2, %0|%0, %2}"
21337 [(set_attr "type" "mmxadd")
21338 (set_attr "mode" "DI")])
21340 (define_insn "mmx_nanddi3"
21341 [(set (match_operand:DI 0 "register_operand" "=y")
21343 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
21344 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
21347 "pandn\t{%2, %0|%0, %2}"
21348 [(set_attr "type" "mmxadd")
21349 (set_attr "mode" "DI")])
21352 ;; MMX unsigned averages/sum of absolute differences
21354 (define_insn "mmx_uavgv8qi3"
21355 [(set (match_operand:V8QI 0 "register_operand" "=y")
21357 (plus:V8QI (plus:V8QI
21358 (match_operand:V8QI 1 "register_operand" "0")
21359 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
21360 (const_vector:V8QI [(const_int 1)
21369 "TARGET_SSE || TARGET_3DNOW_A"
21370 "pavgb\t{%2, %0|%0, %2}"
21371 [(set_attr "type" "mmxshft")
21372 (set_attr "mode" "DI")])
21374 (define_insn "mmx_uavgv4hi3"
21375 [(set (match_operand:V4HI 0 "register_operand" "=y")
21377 (plus:V4HI (plus:V4HI
21378 (match_operand:V4HI 1 "register_operand" "0")
21379 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
21380 (const_vector:V4HI [(const_int 1)
21385 "TARGET_SSE || TARGET_3DNOW_A"
21386 "pavgw\t{%2, %0|%0, %2}"
21387 [(set_attr "type" "mmxshft")
21388 (set_attr "mode" "DI")])
21390 (define_insn "mmx_psadbw"
21391 [(set (match_operand:DI 0 "register_operand" "=y")
21392 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
21393 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21395 "TARGET_SSE || TARGET_3DNOW_A"
21396 "psadbw\t{%2, %0|%0, %2}"
21397 [(set_attr "type" "mmxshft")
21398 (set_attr "mode" "DI")])
21401 ;; MMX insert/extract/shuffle
21403 (define_insn "mmx_pinsrw"
21404 [(set (match_operand:V4HI 0 "register_operand" "=y")
21405 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
21406 (vec_duplicate:V4HI
21407 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
21408 (match_operand:SI 3 "const_0_to_15_operand" "N")))]
21409 "TARGET_SSE || TARGET_3DNOW_A"
21410 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21411 [(set_attr "type" "mmxcvt")
21412 (set_attr "mode" "DI")])
21414 (define_insn "mmx_pextrw"
21415 [(set (match_operand:SI 0 "register_operand" "=r")
21416 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
21418 [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
21419 "TARGET_SSE || TARGET_3DNOW_A"
21420 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21421 [(set_attr "type" "mmxcvt")
21422 (set_attr "mode" "DI")])
21424 (define_insn "mmx_pshufw"
21425 [(set (match_operand:V4HI 0 "register_operand" "=y")
21426 (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
21427 (match_operand:SI 2 "immediate_operand" "i")]
21429 "TARGET_SSE || TARGET_3DNOW_A"
21430 "pshufw\t{%2, %1, %0|%0, %1, %2}"
21431 [(set_attr "type" "mmxcvt")
21432 (set_attr "mode" "DI")])
21435 ;; MMX mask-generating comparisons
21437 (define_insn "eqv8qi3"
21438 [(set (match_operand:V8QI 0 "register_operand" "=y")
21439 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
21440 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21442 "pcmpeqb\t{%2, %0|%0, %2}"
21443 [(set_attr "type" "mmxcmp")
21444 (set_attr "mode" "DI")])
21446 (define_insn "eqv4hi3"
21447 [(set (match_operand:V4HI 0 "register_operand" "=y")
21448 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
21449 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21451 "pcmpeqw\t{%2, %0|%0, %2}"
21452 [(set_attr "type" "mmxcmp")
21453 (set_attr "mode" "DI")])
21455 (define_insn "eqv2si3"
21456 [(set (match_operand:V2SI 0 "register_operand" "=y")
21457 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
21458 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21460 "pcmpeqd\t{%2, %0|%0, %2}"
21461 [(set_attr "type" "mmxcmp")
21462 (set_attr "mode" "DI")])
21464 (define_insn "gtv8qi3"
21465 [(set (match_operand:V8QI 0 "register_operand" "=y")
21466 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
21467 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21469 "pcmpgtb\t{%2, %0|%0, %2}"
21470 [(set_attr "type" "mmxcmp")
21471 (set_attr "mode" "DI")])
21473 (define_insn "gtv4hi3"
21474 [(set (match_operand:V4HI 0 "register_operand" "=y")
21475 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21476 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21478 "pcmpgtw\t{%2, %0|%0, %2}"
21479 [(set_attr "type" "mmxcmp")
21480 (set_attr "mode" "DI")])
21482 (define_insn "gtv2si3"
21483 [(set (match_operand:V2SI 0 "register_operand" "=y")
21484 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21485 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21487 "pcmpgtd\t{%2, %0|%0, %2}"
21488 [(set_attr "type" "mmxcmp")
21489 (set_attr "mode" "DI")])
21492 ;; MMX max/min insns
21494 (define_insn "umaxv8qi3"
21495 [(set (match_operand:V8QI 0 "register_operand" "=y")
21496 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
21497 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21498 "TARGET_SSE || TARGET_3DNOW_A"
21499 "pmaxub\t{%2, %0|%0, %2}"
21500 [(set_attr "type" "mmxadd")
21501 (set_attr "mode" "DI")])
21503 (define_insn "smaxv4hi3"
21504 [(set (match_operand:V4HI 0 "register_operand" "=y")
21505 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
21506 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21507 "TARGET_SSE || TARGET_3DNOW_A"
21508 "pmaxsw\t{%2, %0|%0, %2}"
21509 [(set_attr "type" "mmxadd")
21510 (set_attr "mode" "DI")])
21512 (define_insn "uminv8qi3"
21513 [(set (match_operand:V8QI 0 "register_operand" "=y")
21514 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
21515 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21516 "TARGET_SSE || TARGET_3DNOW_A"
21517 "pminub\t{%2, %0|%0, %2}"
21518 [(set_attr "type" "mmxadd")
21519 (set_attr "mode" "DI")])
21521 (define_insn "sminv4hi3"
21522 [(set (match_operand:V4HI 0 "register_operand" "=y")
21523 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
21524 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21525 "TARGET_SSE || TARGET_3DNOW_A"
21526 "pminsw\t{%2, %0|%0, %2}"
21527 [(set_attr "type" "mmxadd")
21528 (set_attr "mode" "DI")])
21533 (define_insn "ashrv4hi3"
21534 [(set (match_operand:V4HI 0 "register_operand" "=y")
21535 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21536 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21538 "psraw\t{%2, %0|%0, %2}"
21539 [(set_attr "type" "mmxshft")
21540 (set_attr "mode" "DI")])
21542 (define_insn "ashrv2si3"
21543 [(set (match_operand:V2SI 0 "register_operand" "=y")
21544 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21545 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21547 "psrad\t{%2, %0|%0, %2}"
21548 [(set_attr "type" "mmxshft")
21549 (set_attr "mode" "DI")])
21551 (define_insn "lshrv4hi3"
21552 [(set (match_operand:V4HI 0 "register_operand" "=y")
21553 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21554 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21556 "psrlw\t{%2, %0|%0, %2}"
21557 [(set_attr "type" "mmxshft")
21558 (set_attr "mode" "DI")])
21560 (define_insn "lshrv2si3"
21561 [(set (match_operand:V2SI 0 "register_operand" "=y")
21562 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21563 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21565 "psrld\t{%2, %0|%0, %2}"
21566 [(set_attr "type" "mmxshft")
21567 (set_attr "mode" "DI")])
21569 ;; See logical MMX insns.
21570 (define_insn "mmx_lshrdi3"
21571 [(set (match_operand:DI 0 "register_operand" "=y")
21573 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
21574 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21577 "psrlq\t{%2, %0|%0, %2}"
21578 [(set_attr "type" "mmxshft")
21579 (set_attr "mode" "DI")])
21581 (define_insn "ashlv4hi3"
21582 [(set (match_operand:V4HI 0 "register_operand" "=y")
21583 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
21584 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21586 "psllw\t{%2, %0|%0, %2}"
21587 [(set_attr "type" "mmxshft")
21588 (set_attr "mode" "DI")])
21590 (define_insn "ashlv2si3"
21591 [(set (match_operand:V2SI 0 "register_operand" "=y")
21592 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
21593 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21595 "pslld\t{%2, %0|%0, %2}"
21596 [(set_attr "type" "mmxshft")
21597 (set_attr "mode" "DI")])
21599 ;; See logical MMX insns.
21600 (define_insn "mmx_ashldi3"
21601 [(set (match_operand:DI 0 "register_operand" "=y")
21603 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
21604 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21607 "psllq\t{%2, %0|%0, %2}"
21608 [(set_attr "type" "mmxshft")
21609 (set_attr "mode" "DI")])
21612 ;; MMX pack/unpack insns.
21614 (define_insn "mmx_packsswb"
21615 [(set (match_operand:V8QI 0 "register_operand" "=y")
21617 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21618 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21620 "packsswb\t{%2, %0|%0, %2}"
21621 [(set_attr "type" "mmxshft")
21622 (set_attr "mode" "DI")])
21624 (define_insn "mmx_packssdw"
21625 [(set (match_operand:V4HI 0 "register_operand" "=y")
21627 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
21628 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
21630 "packssdw\t{%2, %0|%0, %2}"
21631 [(set_attr "type" "mmxshft")
21632 (set_attr "mode" "DI")])
21634 (define_insn "mmx_packuswb"
21635 [(set (match_operand:V8QI 0 "register_operand" "=y")
21637 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21638 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21640 "packuswb\t{%2, %0|%0, %2}"
21641 [(set_attr "type" "mmxshft")
21642 (set_attr "mode" "DI")])
21644 (define_insn "mmx_punpckhbw"
21645 [(set (match_operand:V8QI 0 "register_operand" "=y")
21647 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21648 (parallel [(const_int 4)
21656 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21657 (parallel [(const_int 0)
21667 "punpckhbw\t{%2, %0|%0, %2}"
21668 [(set_attr "type" "mmxcvt")
21669 (set_attr "mode" "DI")])
21671 (define_insn "mmx_punpckhwd"
21672 [(set (match_operand:V4HI 0 "register_operand" "=y")
21674 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21675 (parallel [(const_int 0)
21679 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21680 (parallel [(const_int 2)
21686 "punpckhwd\t{%2, %0|%0, %2}"
21687 [(set_attr "type" "mmxcvt")
21688 (set_attr "mode" "DI")])
21690 (define_insn "mmx_punpckhdq"
21691 [(set (match_operand:V2SI 0 "register_operand" "=y")
21693 (match_operand:V2SI 1 "register_operand" "0")
21694 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
21695 (parallel [(const_int 1)
21699 "punpckhdq\t{%2, %0|%0, %2}"
21700 [(set_attr "type" "mmxcvt")
21701 (set_attr "mode" "DI")])
21703 (define_insn "mmx_punpcklbw"
21704 [(set (match_operand:V8QI 0 "register_operand" "=y")
21706 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21707 (parallel [(const_int 0)
21715 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21716 (parallel [(const_int 4)
21726 "punpcklbw\t{%2, %0|%0, %2}"
21727 [(set_attr "type" "mmxcvt")
21728 (set_attr "mode" "DI")])
21730 (define_insn "mmx_punpcklwd"
21731 [(set (match_operand:V4HI 0 "register_operand" "=y")
21733 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21734 (parallel [(const_int 2)
21738 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21739 (parallel [(const_int 0)
21745 "punpcklwd\t{%2, %0|%0, %2}"
21746 [(set_attr "type" "mmxcvt")
21747 (set_attr "mode" "DI")])
21749 (define_insn "mmx_punpckldq"
21750 [(set (match_operand:V2SI 0 "register_operand" "=y")
21752 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
21753 (parallel [(const_int 1)
21755 (match_operand:V2SI 2 "register_operand" "y")
21758 "punpckldq\t{%2, %0|%0, %2}"
21759 [(set_attr "type" "mmxcvt")
21760 (set_attr "mode" "DI")])
21763 ;; Miscellaneous stuff
21765 (define_insn "emms"
21766 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21767 (clobber (reg:XF 8))
21768 (clobber (reg:XF 9))
21769 (clobber (reg:XF 10))
21770 (clobber (reg:XF 11))
21771 (clobber (reg:XF 12))
21772 (clobber (reg:XF 13))
21773 (clobber (reg:XF 14))
21774 (clobber (reg:XF 15))
21775 (clobber (reg:DI 29))
21776 (clobber (reg:DI 30))
21777 (clobber (reg:DI 31))
21778 (clobber (reg:DI 32))
21779 (clobber (reg:DI 33))
21780 (clobber (reg:DI 34))
21781 (clobber (reg:DI 35))
21782 (clobber (reg:DI 36))]
21785 [(set_attr "type" "mmx")
21786 (set_attr "memory" "unknown")])
21788 (define_insn "ldmxcsr"
21789 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
21793 [(set_attr "type" "sse")
21794 (set_attr "memory" "load")])
21796 (define_insn "stmxcsr"
21797 [(set (match_operand:SI 0 "memory_operand" "=m")
21798 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
21801 [(set_attr "type" "sse")
21802 (set_attr "memory" "store")])
21804 (define_expand "sfence"
21805 [(set (match_dup 0)
21806 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21807 "TARGET_SSE || TARGET_3DNOW_A"
21809 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21810 MEM_VOLATILE_P (operands[0]) = 1;
21813 (define_insn "*sfence_insn"
21814 [(set (match_operand:BLK 0 "" "")
21815 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21816 "TARGET_SSE || TARGET_3DNOW_A"
21818 [(set_attr "type" "sse")
21819 (set_attr "memory" "unknown")])
21821 (define_expand "sse_prologue_save"
21822 [(parallel [(set (match_operand:BLK 0 "" "")
21823 (unspec:BLK [(reg:DI 21)
21830 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21831 (use (match_operand:DI 1 "register_operand" ""))
21832 (use (match_operand:DI 2 "immediate_operand" ""))
21833 (use (label_ref:DI (match_operand 3 "" "")))])]
21837 (define_insn "*sse_prologue_save_insn"
21838 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21839 (match_operand:DI 4 "const_int_operand" "n")))
21840 (unspec:BLK [(reg:DI 21)
21847 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21848 (use (match_operand:DI 1 "register_operand" "r"))
21849 (use (match_operand:DI 2 "const_int_operand" "i"))
21850 (use (label_ref:DI (match_operand 3 "" "X")))]
21852 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21853 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21857 operands[0] = gen_rtx_MEM (Pmode,
21858 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21859 output_asm_insn (\"jmp\\t%A1\", operands);
21860 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21862 operands[4] = adjust_address (operands[0], DImode, i*16);
21863 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21864 PUT_MODE (operands[4], TImode);
21865 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21866 output_asm_insn (\"rex\", operands);
21867 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21869 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21870 CODE_LABEL_NUMBER (operands[3]));
21874 [(set_attr "type" "other")
21875 (set_attr "length_immediate" "0")
21876 (set_attr "length_address" "0")
21877 (set_attr "length" "135")
21878 (set_attr "memory" "store")
21879 (set_attr "modrm" "0")
21880 (set_attr "mode" "DI")])
21882 ;; 3Dnow! instructions
21884 (define_insn "addv2sf3"
21885 [(set (match_operand:V2SF 0 "register_operand" "=y")
21886 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21887 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21889 "pfadd\\t{%2, %0|%0, %2}"
21890 [(set_attr "type" "mmxadd")
21891 (set_attr "mode" "V2SF")])
21893 (define_insn "subv2sf3"
21894 [(set (match_operand:V2SF 0 "register_operand" "=y")
21895 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21896 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21898 "pfsub\\t{%2, %0|%0, %2}"
21899 [(set_attr "type" "mmxadd")
21900 (set_attr "mode" "V2SF")])
21902 (define_insn "subrv2sf3"
21903 [(set (match_operand:V2SF 0 "register_operand" "=y")
21904 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
21905 (match_operand:V2SF 1 "register_operand" "0")))]
21907 "pfsubr\\t{%2, %0|%0, %2}"
21908 [(set_attr "type" "mmxadd")
21909 (set_attr "mode" "V2SF")])
21911 (define_insn "gtv2sf3"
21912 [(set (match_operand:V2SI 0 "register_operand" "=y")
21913 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
21914 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21916 "pfcmpgt\\t{%2, %0|%0, %2}"
21917 [(set_attr "type" "mmxcmp")
21918 (set_attr "mode" "V2SF")])
21920 (define_insn "gev2sf3"
21921 [(set (match_operand:V2SI 0 "register_operand" "=y")
21922 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
21923 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21925 "pfcmpge\\t{%2, %0|%0, %2}"
21926 [(set_attr "type" "mmxcmp")
21927 (set_attr "mode" "V2SF")])
21929 (define_insn "eqv2sf3"
21930 [(set (match_operand:V2SI 0 "register_operand" "=y")
21931 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
21932 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21934 "pfcmpeq\\t{%2, %0|%0, %2}"
21935 [(set_attr "type" "mmxcmp")
21936 (set_attr "mode" "V2SF")])
21938 (define_insn "pfmaxv2sf3"
21939 [(set (match_operand:V2SF 0 "register_operand" "=y")
21940 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
21941 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21943 "pfmax\\t{%2, %0|%0, %2}"
21944 [(set_attr "type" "mmxadd")
21945 (set_attr "mode" "V2SF")])
21947 (define_insn "pfminv2sf3"
21948 [(set (match_operand:V2SF 0 "register_operand" "=y")
21949 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
21950 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21952 "pfmin\\t{%2, %0|%0, %2}"
21953 [(set_attr "type" "mmxadd")
21954 (set_attr "mode" "V2SF")])
21956 (define_insn "mulv2sf3"
21957 [(set (match_operand:V2SF 0 "register_operand" "=y")
21958 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
21959 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21961 "pfmul\\t{%2, %0|%0, %2}"
21962 [(set_attr "type" "mmxmul")
21963 (set_attr "mode" "V2SF")])
21965 (define_insn "femms"
21966 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
21967 (clobber (reg:XF 8))
21968 (clobber (reg:XF 9))
21969 (clobber (reg:XF 10))
21970 (clobber (reg:XF 11))
21971 (clobber (reg:XF 12))
21972 (clobber (reg:XF 13))
21973 (clobber (reg:XF 14))
21974 (clobber (reg:XF 15))
21975 (clobber (reg:DI 29))
21976 (clobber (reg:DI 30))
21977 (clobber (reg:DI 31))
21978 (clobber (reg:DI 32))
21979 (clobber (reg:DI 33))
21980 (clobber (reg:DI 34))
21981 (clobber (reg:DI 35))
21982 (clobber (reg:DI 36))]
21985 [(set_attr "type" "mmx")
21986 (set_attr "memory" "none")])
21988 (define_insn "pf2id"
21989 [(set (match_operand:V2SI 0 "register_operand" "=y")
21990 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
21992 "pf2id\\t{%1, %0|%0, %1}"
21993 [(set_attr "type" "mmxcvt")
21994 (set_attr "mode" "V2SF")])
21996 (define_insn "pf2iw"
21997 [(set (match_operand:V2SI 0 "register_operand" "=y")
22000 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
22002 "pf2iw\\t{%1, %0|%0, %1}"
22003 [(set_attr "type" "mmxcvt")
22004 (set_attr "mode" "V2SF")])
22006 (define_insn "pfacc"
22007 [(set (match_operand:V2SF 0 "register_operand" "=y")
22010 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22011 (parallel [(const_int 0)]))
22012 (vec_select:SF (match_dup 1)
22013 (parallel [(const_int 1)])))
22015 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22016 (parallel [(const_int 0)]))
22017 (vec_select:SF (match_dup 2)
22018 (parallel [(const_int 1)])))))]
22020 "pfacc\\t{%2, %0|%0, %2}"
22021 [(set_attr "type" "mmxadd")
22022 (set_attr "mode" "V2SF")])
22024 (define_insn "pfnacc"
22025 [(set (match_operand:V2SF 0 "register_operand" "=y")
22028 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22029 (parallel [(const_int 0)]))
22030 (vec_select:SF (match_dup 1)
22031 (parallel [(const_int 1)])))
22033 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22034 (parallel [(const_int 0)]))
22035 (vec_select:SF (match_dup 2)
22036 (parallel [(const_int 1)])))))]
22038 "pfnacc\\t{%2, %0|%0, %2}"
22039 [(set_attr "type" "mmxadd")
22040 (set_attr "mode" "V2SF")])
22042 (define_insn "pfpnacc"
22043 [(set (match_operand:V2SF 0 "register_operand" "=y")
22046 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
22047 (parallel [(const_int 0)]))
22048 (vec_select:SF (match_dup 1)
22049 (parallel [(const_int 1)])))
22051 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
22052 (parallel [(const_int 0)]))
22053 (vec_select:SF (match_dup 2)
22054 (parallel [(const_int 1)])))))]
22056 "pfpnacc\\t{%2, %0|%0, %2}"
22057 [(set_attr "type" "mmxadd")
22058 (set_attr "mode" "V2SF")])
22060 (define_insn "pi2fw"
22061 [(set (match_operand:V2SF 0 "register_operand" "=y")
22066 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22067 (parallel [(const_int 0)]))))
22070 (vec_select:SI (match_dup 1)
22071 (parallel [(const_int 1)])))))))]
22073 "pi2fw\\t{%1, %0|%0, %1}"
22074 [(set_attr "type" "mmxcvt")
22075 (set_attr "mode" "V2SF")])
22077 (define_insn "floatv2si2"
22078 [(set (match_operand:V2SF 0 "register_operand" "=y")
22079 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22081 "pi2fd\\t{%1, %0|%0, %1}"
22082 [(set_attr "type" "mmxcvt")
22083 (set_attr "mode" "V2SF")])
22085 ;; This insn is identical to pavgb in operation, but the opcode is
22086 ;; different. To avoid accidentally matching pavgb, use an unspec.
22088 (define_insn "pavgusb"
22089 [(set (match_operand:V8QI 0 "register_operand" "=y")
22091 [(match_operand:V8QI 1 "register_operand" "0")
22092 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
22095 "pavgusb\\t{%2, %0|%0, %2}"
22096 [(set_attr "type" "mmxshft")
22097 (set_attr "mode" "TI")])
22099 ;; 3DNow reciprocal and sqrt
22101 (define_insn "pfrcpv2sf2"
22102 [(set (match_operand:V2SF 0 "register_operand" "=y")
22103 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22106 "pfrcp\\t{%1, %0|%0, %1}"
22107 [(set_attr "type" "mmx")
22108 (set_attr "mode" "TI")])
22110 (define_insn "pfrcpit1v2sf3"
22111 [(set (match_operand:V2SF 0 "register_operand" "=y")
22112 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22113 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22116 "pfrcpit1\\t{%2, %0|%0, %2}"
22117 [(set_attr "type" "mmx")
22118 (set_attr "mode" "TI")])
22120 (define_insn "pfrcpit2v2sf3"
22121 [(set (match_operand:V2SF 0 "register_operand" "=y")
22122 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22123 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22126 "pfrcpit2\\t{%2, %0|%0, %2}"
22127 [(set_attr "type" "mmx")
22128 (set_attr "mode" "TI")])
22130 (define_insn "pfrsqrtv2sf2"
22131 [(set (match_operand:V2SF 0 "register_operand" "=y")
22132 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
22135 "pfrsqrt\\t{%1, %0|%0, %1}"
22136 [(set_attr "type" "mmx")
22137 (set_attr "mode" "TI")])
22139 (define_insn "pfrsqit1v2sf3"
22140 [(set (match_operand:V2SF 0 "register_operand" "=y")
22141 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
22142 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
22145 "pfrsqit1\\t{%2, %0|%0, %2}"
22146 [(set_attr "type" "mmx")
22147 (set_attr "mode" "TI")])
22149 (define_insn "pmulhrwv4hi3"
22150 [(set (match_operand:V4HI 0 "register_operand" "=y")
22156 (match_operand:V4HI 1 "register_operand" "0"))
22158 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
22159 (const_vector:V4SI [(const_int 32768)
22162 (const_int 32768)]))
22165 "pmulhrw\\t{%2, %0|%0, %2}"
22166 [(set_attr "type" "mmxmul")
22167 (set_attr "mode" "TI")])
22169 (define_insn "pswapdv2si2"
22170 [(set (match_operand:V2SI 0 "register_operand" "=y")
22171 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
22172 (parallel [(const_int 1) (const_int 0)])))]
22174 "pswapd\\t{%1, %0|%0, %1}"
22175 [(set_attr "type" "mmxcvt")
22176 (set_attr "mode" "TI")])
22178 (define_insn "pswapdv2sf2"
22179 [(set (match_operand:V2SF 0 "register_operand" "=y")
22180 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
22181 (parallel [(const_int 1) (const_int 0)])))]
22183 "pswapd\\t{%1, %0|%0, %1}"
22184 [(set_attr "type" "mmxcvt")
22185 (set_attr "mode" "TI")])
22187 (define_expand "prefetch"
22188 [(prefetch (match_operand 0 "address_operand" "")
22189 (match_operand:SI 1 "const_int_operand" "")
22190 (match_operand:SI 2 "const_int_operand" ""))]
22191 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
22193 int rw = INTVAL (operands[1]);
22194 int locality = INTVAL (operands[2]);
22196 if (rw != 0 && rw != 1)
22198 if (locality < 0 || locality > 3)
22200 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
22203 /* Use 3dNOW prefetch in case we are asking for write prefetch not
22204 suported by SSE counterpart or the SSE prefetch is not available
22205 (K6 machines). Otherwise use SSE prefetch as it allows specifying
22207 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
22208 operands[2] = GEN_INT (3);
22210 operands[1] = const0_rtx;
22213 (define_insn "*prefetch_sse"
22214 [(prefetch (match_operand:SI 0 "address_operand" "p")
22216 (match_operand:SI 1 "const_int_operand" ""))]
22217 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
22219 static const char * const patterns[4] = {
22220 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22223 int locality = INTVAL (operands[1]);
22224 if (locality < 0 || locality > 3)
22227 return patterns[locality];
22229 [(set_attr "type" "sse")
22230 (set_attr "memory" "none")])
22232 (define_insn "*prefetch_sse_rex"
22233 [(prefetch (match_operand:DI 0 "address_operand" "p")
22235 (match_operand:SI 1 "const_int_operand" ""))]
22236 "TARGET_PREFETCH_SSE && TARGET_64BIT"
22238 static const char * const patterns[4] = {
22239 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
22242 int locality = INTVAL (operands[1]);
22243 if (locality < 0 || locality > 3)
22246 return patterns[locality];
22248 [(set_attr "type" "sse")
22249 (set_attr "memory" "none")])
22251 (define_insn "*prefetch_3dnow"
22252 [(prefetch (match_operand:SI 0 "address_operand" "p")
22253 (match_operand:SI 1 "const_int_operand" "n")
22255 "TARGET_3DNOW && !TARGET_64BIT"
22257 if (INTVAL (operands[1]) == 0)
22258 return "prefetch\t%a0";
22260 return "prefetchw\t%a0";
22262 [(set_attr "type" "mmx")
22263 (set_attr "memory" "none")])
22265 (define_insn "*prefetch_3dnow_rex"
22266 [(prefetch (match_operand:DI 0 "address_operand" "p")
22267 (match_operand:SI 1 "const_int_operand" "n")
22269 "TARGET_3DNOW && TARGET_64BIT"
22271 if (INTVAL (operands[1]) == 0)
22272 return "prefetch\t%a0";
22274 return "prefetchw\t%a0";
22276 [(set_attr "type" "mmx")
22277 (set_attr "memory" "none")])
22281 (define_insn "addv2df3"
22282 [(set (match_operand:V2DF 0 "register_operand" "=x")
22283 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22284 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22286 "addpd\t{%2, %0|%0, %2}"
22287 [(set_attr "type" "sseadd")
22288 (set_attr "mode" "V2DF")])
22290 (define_insn "vmaddv2df3"
22291 [(set (match_operand:V2DF 0 "register_operand" "=x")
22292 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22293 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22297 "addsd\t{%2, %0|%0, %2}"
22298 [(set_attr "type" "sseadd")
22299 (set_attr "mode" "DF")])
22301 (define_insn "subv2df3"
22302 [(set (match_operand:V2DF 0 "register_operand" "=x")
22303 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22304 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22306 "subpd\t{%2, %0|%0, %2}"
22307 [(set_attr "type" "sseadd")
22308 (set_attr "mode" "V2DF")])
22310 (define_insn "vmsubv2df3"
22311 [(set (match_operand:V2DF 0 "register_operand" "=x")
22312 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
22313 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22317 "subsd\t{%2, %0|%0, %2}"
22318 [(set_attr "type" "sseadd")
22319 (set_attr "mode" "DF")])
22321 (define_insn "mulv2df3"
22322 [(set (match_operand:V2DF 0 "register_operand" "=x")
22323 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22324 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22326 "mulpd\t{%2, %0|%0, %2}"
22327 [(set_attr "type" "ssemul")
22328 (set_attr "mode" "V2DF")])
22330 (define_insn "vmmulv2df3"
22331 [(set (match_operand:V2DF 0 "register_operand" "=x")
22332 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
22333 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22337 "mulsd\t{%2, %0|%0, %2}"
22338 [(set_attr "type" "ssemul")
22339 (set_attr "mode" "DF")])
22341 (define_insn "divv2df3"
22342 [(set (match_operand:V2DF 0 "register_operand" "=x")
22343 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22344 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22346 "divpd\t{%2, %0|%0, %2}"
22347 [(set_attr "type" "ssediv")
22348 (set_attr "mode" "V2DF")])
22350 (define_insn "vmdivv2df3"
22351 [(set (match_operand:V2DF 0 "register_operand" "=x")
22352 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22353 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22357 "divsd\t{%2, %0|%0, %2}"
22358 [(set_attr "type" "ssediv")
22359 (set_attr "mode" "DF")])
22363 (define_insn "smaxv2df3"
22364 [(set (match_operand:V2DF 0 "register_operand" "=x")
22365 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22366 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22368 "maxpd\t{%2, %0|%0, %2}"
22369 [(set_attr "type" "sseadd")
22370 (set_attr "mode" "V2DF")])
22372 (define_insn "vmsmaxv2df3"
22373 [(set (match_operand:V2DF 0 "register_operand" "=x")
22374 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22375 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22379 "maxsd\t{%2, %0|%0, %2}"
22380 [(set_attr "type" "sseadd")
22381 (set_attr "mode" "DF")])
22383 (define_insn "sminv2df3"
22384 [(set (match_operand:V2DF 0 "register_operand" "=x")
22385 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22386 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22388 "minpd\t{%2, %0|%0, %2}"
22389 [(set_attr "type" "sseadd")
22390 (set_attr "mode" "V2DF")])
22392 (define_insn "vmsminv2df3"
22393 [(set (match_operand:V2DF 0 "register_operand" "=x")
22394 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22395 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22399 "minsd\t{%2, %0|%0, %2}"
22400 [(set_attr "type" "sseadd")
22401 (set_attr "mode" "DF")])
22402 ;; SSE2 square root. There doesn't appear to be an extension for the
22403 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
22405 (define_insn "sqrtv2df2"
22406 [(set (match_operand:V2DF 0 "register_operand" "=x")
22407 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
22409 "sqrtpd\t{%1, %0|%0, %1}"
22410 [(set_attr "type" "sse")
22411 (set_attr "mode" "V2DF")])
22413 (define_insn "vmsqrtv2df2"
22414 [(set (match_operand:V2DF 0 "register_operand" "=x")
22415 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
22416 (match_operand:V2DF 2 "register_operand" "0")
22419 "sqrtsd\t{%1, %0|%0, %1}"
22420 [(set_attr "type" "sse")
22421 (set_attr "mode" "SF")])
22423 ;; SSE mask-generating compares
22425 (define_insn "maskcmpv2df3"
22426 [(set (match_operand:V2DI 0 "register_operand" "=x")
22427 (match_operator:V2DI 3 "sse_comparison_operator"
22428 [(match_operand:V2DF 1 "register_operand" "0")
22429 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
22431 "cmp%D3pd\t{%2, %0|%0, %2}"
22432 [(set_attr "type" "ssecmp")
22433 (set_attr "mode" "V2DF")])
22435 (define_insn "maskncmpv2df3"
22436 [(set (match_operand:V2DI 0 "register_operand" "=x")
22438 (match_operator:V2DI 3 "sse_comparison_operator"
22439 [(match_operand:V2DF 1 "register_operand" "0")
22440 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
22443 if (GET_CODE (operands[3]) == UNORDERED)
22444 return "cmpordps\t{%2, %0|%0, %2}";
22446 return "cmpn%D3pd\t{%2, %0|%0, %2}";
22448 [(set_attr "type" "ssecmp")
22449 (set_attr "mode" "V2DF")])
22451 (define_insn "vmmaskcmpv2df3"
22452 [(set (match_operand:V2DI 0 "register_operand" "=x")
22454 (match_operator:V2DI 3 "sse_comparison_operator"
22455 [(match_operand:V2DF 1 "register_operand" "0")
22456 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
22457 (subreg:V2DI (match_dup 1) 0)
22460 "cmp%D3sd\t{%2, %0|%0, %2}"
22461 [(set_attr "type" "ssecmp")
22462 (set_attr "mode" "DF")])
22464 (define_insn "vmmaskncmpv2df3"
22465 [(set (match_operand:V2DI 0 "register_operand" "=x")
22468 (match_operator:V2DI 3 "sse_comparison_operator"
22469 [(match_operand:V2DF 1 "register_operand" "0")
22470 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
22471 (subreg:V2DI (match_dup 1) 0)
22475 if (GET_CODE (operands[3]) == UNORDERED)
22476 return "cmpordsd\t{%2, %0|%0, %2}";
22478 return "cmpn%D3sd\t{%2, %0|%0, %2}";
22480 [(set_attr "type" "ssecmp")
22481 (set_attr "mode" "DF")])
22483 (define_insn "sse2_comi"
22484 [(set (reg:CCFP FLAGS_REG)
22485 (compare:CCFP (vec_select:DF
22486 (match_operand:V2DF 0 "register_operand" "x")
22487 (parallel [(const_int 0)]))
22489 (match_operand:V2DF 1 "register_operand" "x")
22490 (parallel [(const_int 0)]))))]
22492 "comisd\t{%1, %0|%0, %1}"
22493 [(set_attr "type" "ssecomi")
22494 (set_attr "mode" "DF")])
22496 (define_insn "sse2_ucomi"
22497 [(set (reg:CCFPU FLAGS_REG)
22498 (compare:CCFPU (vec_select:DF
22499 (match_operand:V2DF 0 "register_operand" "x")
22500 (parallel [(const_int 0)]))
22502 (match_operand:V2DF 1 "register_operand" "x")
22503 (parallel [(const_int 0)]))))]
22505 "ucomisd\t{%1, %0|%0, %1}"
22506 [(set_attr "type" "ssecomi")
22507 (set_attr "mode" "DF")])
22509 ;; SSE Strange Moves.
22511 (define_insn "sse2_movmskpd"
22512 [(set (match_operand:SI 0 "register_operand" "=r")
22513 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
22516 "movmskpd\t{%1, %0|%0, %1}"
22517 [(set_attr "type" "ssecvt")
22518 (set_attr "mode" "V2DF")])
22520 (define_insn "sse2_pmovmskb"
22521 [(set (match_operand:SI 0 "register_operand" "=r")
22522 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
22525 "pmovmskb\t{%1, %0|%0, %1}"
22526 [(set_attr "type" "ssecvt")
22527 (set_attr "mode" "V2DF")])
22529 (define_insn "sse2_maskmovdqu"
22530 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
22531 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22532 (match_operand:V16QI 2 "register_operand" "x")]
22535 ;; @@@ check ordering of operands in intel/nonintel syntax
22536 "maskmovdqu\t{%2, %1|%1, %2}"
22537 [(set_attr "type" "ssecvt")
22538 (set_attr "mode" "TI")])
22540 (define_insn "sse2_maskmovdqu_rex64"
22541 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
22542 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22543 (match_operand:V16QI 2 "register_operand" "x")]
22546 ;; @@@ check ordering of operands in intel/nonintel syntax
22547 "maskmovdqu\t{%2, %1|%1, %2}"
22548 [(set_attr "type" "ssecvt")
22549 (set_attr "mode" "TI")])
22551 (define_insn "sse2_movntv2df"
22552 [(set (match_operand:V2DF 0 "memory_operand" "=m")
22553 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
22556 "movntpd\t{%1, %0|%0, %1}"
22557 [(set_attr "type" "ssecvt")
22558 (set_attr "mode" "V2DF")])
22560 (define_insn "sse2_movntv2di"
22561 [(set (match_operand:V2DI 0 "memory_operand" "=m")
22562 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
22565 "movntdq\t{%1, %0|%0, %1}"
22566 [(set_attr "type" "ssecvt")
22567 (set_attr "mode" "TI")])
22569 (define_insn "sse2_movntsi"
22570 [(set (match_operand:SI 0 "memory_operand" "=m")
22571 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
22574 "movnti\t{%1, %0|%0, %1}"
22575 [(set_attr "type" "ssecvt")
22576 (set_attr "mode" "V2DF")])
22578 ;; SSE <-> integer/MMX conversions
22580 ;; Conversions between SI and SF
22582 (define_insn "cvtdq2ps"
22583 [(set (match_operand:V4SF 0 "register_operand" "=x")
22584 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
22586 "cvtdq2ps\t{%1, %0|%0, %1}"
22587 [(set_attr "type" "ssecvt")
22588 (set_attr "mode" "V2DF")])
22590 (define_insn "cvtps2dq"
22591 [(set (match_operand:V4SI 0 "register_operand" "=x")
22592 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
22594 "cvtps2dq\t{%1, %0|%0, %1}"
22595 [(set_attr "type" "ssecvt")
22596 (set_attr "mode" "TI")])
22598 (define_insn "cvttps2dq"
22599 [(set (match_operand:V4SI 0 "register_operand" "=x")
22600 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
22603 "cvttps2dq\t{%1, %0|%0, %1}"
22604 [(set_attr "type" "ssecvt")
22605 (set_attr "mode" "TI")])
22607 ;; Conversions between SI and DF
22609 (define_insn "cvtdq2pd"
22610 [(set (match_operand:V2DF 0 "register_operand" "=x")
22611 (float:V2DF (vec_select:V2SI
22612 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
22615 (const_int 1)]))))]
22617 "cvtdq2pd\t{%1, %0|%0, %1}"
22618 [(set_attr "type" "ssecvt")
22619 (set_attr "mode" "V2DF")])
22621 (define_insn "cvtpd2dq"
22622 [(set (match_operand:V4SI 0 "register_operand" "=x")
22624 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
22625 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22627 "cvtpd2dq\t{%1, %0|%0, %1}"
22628 [(set_attr "type" "ssecvt")
22629 (set_attr "mode" "TI")])
22631 (define_insn "cvttpd2dq"
22632 [(set (match_operand:V4SI 0 "register_operand" "=x")
22634 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22636 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22638 "cvttpd2dq\t{%1, %0|%0, %1}"
22639 [(set_attr "type" "ssecvt")
22640 (set_attr "mode" "TI")])
22642 (define_insn "cvtpd2pi"
22643 [(set (match_operand:V2SI 0 "register_operand" "=y")
22644 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
22646 "cvtpd2pi\t{%1, %0|%0, %1}"
22647 [(set_attr "type" "ssecvt")
22648 (set_attr "mode" "TI")])
22650 (define_insn "cvttpd2pi"
22651 [(set (match_operand:V2SI 0 "register_operand" "=y")
22652 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22655 "cvttpd2pi\t{%1, %0|%0, %1}"
22656 [(set_attr "type" "ssecvt")
22657 (set_attr "mode" "TI")])
22659 (define_insn "cvtpi2pd"
22660 [(set (match_operand:V2DF 0 "register_operand" "=x")
22661 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22663 "cvtpi2pd\t{%1, %0|%0, %1}"
22664 [(set_attr "type" "ssecvt")
22665 (set_attr "mode" "TI")])
22667 ;; Conversions between SI and DF
22669 (define_insn "cvtsd2si"
22670 [(set (match_operand:SI 0 "register_operand" "=r,r")
22671 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22672 (parallel [(const_int 0)]))))]
22674 "cvtsd2si\t{%1, %0|%0, %1}"
22675 [(set_attr "type" "sseicvt")
22676 (set_attr "athlon_decode" "double,vector")
22677 (set_attr "mode" "SI")])
22679 (define_insn "cvtsd2siq"
22680 [(set (match_operand:DI 0 "register_operand" "=r,r")
22681 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22682 (parallel [(const_int 0)]))))]
22683 "TARGET_SSE2 && TARGET_64BIT"
22684 "cvtsd2siq\t{%1, %0|%0, %1}"
22685 [(set_attr "type" "sseicvt")
22686 (set_attr "athlon_decode" "double,vector")
22687 (set_attr "mode" "DI")])
22689 (define_insn "cvttsd2si"
22690 [(set (match_operand:SI 0 "register_operand" "=r,r")
22691 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22692 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22694 "cvttsd2si\t{%1, %0|%0, %1}"
22695 [(set_attr "type" "sseicvt")
22696 (set_attr "mode" "SI")
22697 (set_attr "athlon_decode" "double,vector")])
22699 (define_insn "cvttsd2siq"
22700 [(set (match_operand:DI 0 "register_operand" "=r,r")
22701 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22702 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22703 "TARGET_SSE2 && TARGET_64BIT"
22704 "cvttsd2siq\t{%1, %0|%0, %1}"
22705 [(set_attr "type" "sseicvt")
22706 (set_attr "mode" "DI")
22707 (set_attr "athlon_decode" "double,vector")])
22709 (define_insn "cvtsi2sd"
22710 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22711 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22712 (vec_duplicate:V2DF
22714 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
22717 "cvtsi2sd\t{%2, %0|%0, %2}"
22718 [(set_attr "type" "sseicvt")
22719 (set_attr "mode" "DF")
22720 (set_attr "athlon_decode" "double,direct")])
22722 (define_insn "cvtsi2sdq"
22723 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22724 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22725 (vec_duplicate:V2DF
22727 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
22729 "TARGET_SSE2 && TARGET_64BIT"
22730 "cvtsi2sdq\t{%2, %0|%0, %2}"
22731 [(set_attr "type" "sseicvt")
22732 (set_attr "mode" "DF")
22733 (set_attr "athlon_decode" "double,direct")])
22735 ;; Conversions between SF and DF
22737 (define_insn "cvtsd2ss"
22738 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
22739 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
22740 (vec_duplicate:V4SF
22741 (float_truncate:V2SF
22742 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
22745 "cvtsd2ss\t{%2, %0|%0, %2}"
22746 [(set_attr "type" "ssecvt")
22747 (set_attr "athlon_decode" "vector,double")
22748 (set_attr "mode" "SF")])
22750 (define_insn "cvtss2sd"
22751 [(set (match_operand:V2DF 0 "register_operand" "=x")
22752 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
22755 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
22756 (parallel [(const_int 0)
22760 "cvtss2sd\t{%2, %0|%0, %2}"
22761 [(set_attr "type" "ssecvt")
22762 (set_attr "mode" "DF")])
22764 (define_insn "cvtpd2ps"
22765 [(set (match_operand:V4SF 0 "register_operand" "=x")
22768 (subreg:V2SI (float_truncate:V2SF
22769 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22770 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22772 "cvtpd2ps\t{%1, %0|%0, %1}"
22773 [(set_attr "type" "ssecvt")
22774 (set_attr "mode" "V4SF")])
22776 (define_insn "cvtps2pd"
22777 [(set (match_operand:V2DF 0 "register_operand" "=x")
22779 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
22780 (parallel [(const_int 0)
22781 (const_int 1)]))))]
22783 "cvtps2pd\t{%1, %0|%0, %1}"
22784 [(set_attr "type" "ssecvt")
22785 (set_attr "mode" "V2DF")])
22787 ;; SSE2 variants of MMX insns
22791 (define_insn "addv16qi3"
22792 [(set (match_operand:V16QI 0 "register_operand" "=x")
22793 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22794 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22796 "paddb\t{%2, %0|%0, %2}"
22797 [(set_attr "type" "sseiadd")
22798 (set_attr "mode" "TI")])
22800 (define_insn "addv8hi3"
22801 [(set (match_operand:V8HI 0 "register_operand" "=x")
22802 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22803 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22805 "paddw\t{%2, %0|%0, %2}"
22806 [(set_attr "type" "sseiadd")
22807 (set_attr "mode" "TI")])
22809 (define_insn "addv4si3"
22810 [(set (match_operand:V4SI 0 "register_operand" "=x")
22811 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
22812 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22814 "paddd\t{%2, %0|%0, %2}"
22815 [(set_attr "type" "sseiadd")
22816 (set_attr "mode" "TI")])
22818 (define_insn "addv2di3"
22819 [(set (match_operand:V2DI 0 "register_operand" "=x")
22820 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
22821 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22823 "paddq\t{%2, %0|%0, %2}"
22824 [(set_attr "type" "sseiadd")
22825 (set_attr "mode" "TI")])
22827 (define_insn "ssaddv16qi3"
22828 [(set (match_operand:V16QI 0 "register_operand" "=x")
22829 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22830 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22832 "paddsb\t{%2, %0|%0, %2}"
22833 [(set_attr "type" "sseiadd")
22834 (set_attr "mode" "TI")])
22836 (define_insn "ssaddv8hi3"
22837 [(set (match_operand:V8HI 0 "register_operand" "=x")
22838 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22839 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22841 "paddsw\t{%2, %0|%0, %2}"
22842 [(set_attr "type" "sseiadd")
22843 (set_attr "mode" "TI")])
22845 (define_insn "usaddv16qi3"
22846 [(set (match_operand:V16QI 0 "register_operand" "=x")
22847 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22848 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22850 "paddusb\t{%2, %0|%0, %2}"
22851 [(set_attr "type" "sseiadd")
22852 (set_attr "mode" "TI")])
22854 (define_insn "usaddv8hi3"
22855 [(set (match_operand:V8HI 0 "register_operand" "=x")
22856 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22857 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22859 "paddusw\t{%2, %0|%0, %2}"
22860 [(set_attr "type" "sseiadd")
22861 (set_attr "mode" "TI")])
22863 (define_insn "subv16qi3"
22864 [(set (match_operand:V16QI 0 "register_operand" "=x")
22865 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22866 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22868 "psubb\t{%2, %0|%0, %2}"
22869 [(set_attr "type" "sseiadd")
22870 (set_attr "mode" "TI")])
22872 (define_insn "subv8hi3"
22873 [(set (match_operand:V8HI 0 "register_operand" "=x")
22874 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22875 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22877 "psubw\t{%2, %0|%0, %2}"
22878 [(set_attr "type" "sseiadd")
22879 (set_attr "mode" "TI")])
22881 (define_insn "subv4si3"
22882 [(set (match_operand:V4SI 0 "register_operand" "=x")
22883 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
22884 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22886 "psubd\t{%2, %0|%0, %2}"
22887 [(set_attr "type" "sseiadd")
22888 (set_attr "mode" "TI")])
22890 (define_insn "subv2di3"
22891 [(set (match_operand:V2DI 0 "register_operand" "=x")
22892 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
22893 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22895 "psubq\t{%2, %0|%0, %2}"
22896 [(set_attr "type" "sseiadd")
22897 (set_attr "mode" "TI")])
22899 (define_insn "sssubv16qi3"
22900 [(set (match_operand:V16QI 0 "register_operand" "=x")
22901 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22902 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22904 "psubsb\t{%2, %0|%0, %2}"
22905 [(set_attr "type" "sseiadd")
22906 (set_attr "mode" "TI")])
22908 (define_insn "sssubv8hi3"
22909 [(set (match_operand:V8HI 0 "register_operand" "=x")
22910 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22911 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22913 "psubsw\t{%2, %0|%0, %2}"
22914 [(set_attr "type" "sseiadd")
22915 (set_attr "mode" "TI")])
22917 (define_insn "ussubv16qi3"
22918 [(set (match_operand:V16QI 0 "register_operand" "=x")
22919 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22920 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22922 "psubusb\t{%2, %0|%0, %2}"
22923 [(set_attr "type" "sseiadd")
22924 (set_attr "mode" "TI")])
22926 (define_insn "ussubv8hi3"
22927 [(set (match_operand:V8HI 0 "register_operand" "=x")
22928 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22929 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22931 "psubusw\t{%2, %0|%0, %2}"
22932 [(set_attr "type" "sseiadd")
22933 (set_attr "mode" "TI")])
22935 (define_insn "mulv8hi3"
22936 [(set (match_operand:V8HI 0 "register_operand" "=x")
22937 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
22938 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22940 "pmullw\t{%2, %0|%0, %2}"
22941 [(set_attr "type" "sseimul")
22942 (set_attr "mode" "TI")])
22944 (define_insn "smulv8hi3_highpart"
22945 [(set (match_operand:V8HI 0 "register_operand" "=x")
22948 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22949 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22952 "pmulhw\t{%2, %0|%0, %2}"
22953 [(set_attr "type" "sseimul")
22954 (set_attr "mode" "TI")])
22956 (define_insn "umulv8hi3_highpart"
22957 [(set (match_operand:V8HI 0 "register_operand" "=x")
22960 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22961 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22964 "pmulhuw\t{%2, %0|%0, %2}"
22965 [(set_attr "type" "sseimul")
22966 (set_attr "mode" "TI")])
22968 (define_insn "sse2_umulsidi3"
22969 [(set (match_operand:DI 0 "register_operand" "=y")
22970 (mult:DI (zero_extend:DI (vec_select:SI
22971 (match_operand:V2SI 1 "register_operand" "0")
22972 (parallel [(const_int 0)])))
22973 (zero_extend:DI (vec_select:SI
22974 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
22975 (parallel [(const_int 0)])))))]
22977 "pmuludq\t{%2, %0|%0, %2}"
22978 [(set_attr "type" "mmxmul")
22979 (set_attr "mode" "DI")])
22981 (define_insn "sse2_umulv2siv2di3"
22982 [(set (match_operand:V2DI 0 "register_operand" "=x")
22983 (mult:V2DI (zero_extend:V2DI
22985 (match_operand:V4SI 1 "register_operand" "0")
22986 (parallel [(const_int 0) (const_int 2)])))
22989 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
22990 (parallel [(const_int 0) (const_int 2)])))))]
22992 "pmuludq\t{%2, %0|%0, %2}"
22993 [(set_attr "type" "sseimul")
22994 (set_attr "mode" "TI")])
22996 (define_insn "sse2_pmaddwd"
22997 [(set (match_operand:V4SI 0 "register_operand" "=x")
23000 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
23001 (parallel [(const_int 0)
23005 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
23006 (parallel [(const_int 0)
23011 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
23012 (parallel [(const_int 1)
23016 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
23017 (parallel [(const_int 1)
23020 (const_int 7)]))))))]
23022 "pmaddwd\t{%2, %0|%0, %2}"
23023 [(set_attr "type" "sseiadd")
23024 (set_attr "mode" "TI")])
23026 ;; Same as pxor, but don't show input operands so that we don't think
23028 (define_insn "sse2_clrti"
23029 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
23032 if (get_attr_mode (insn) == MODE_TI)
23033 return "pxor\t%0, %0";
23035 return "xorps\t%0, %0";
23037 [(set_attr "type" "ssemov")
23038 (set_attr "memory" "none")
23041 (ne (symbol_ref "optimize_size")
23043 (const_string "V4SF")
23044 (const_string "TI")))])
23046 ;; MMX unsigned averages/sum of absolute differences
23048 (define_insn "sse2_uavgv16qi3"
23049 [(set (match_operand:V16QI 0 "register_operand" "=x")
23051 (plus:V16QI (plus:V16QI
23052 (match_operand:V16QI 1 "register_operand" "0")
23053 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
23054 (const_vector:V16QI [(const_int 1) (const_int 1)
23055 (const_int 1) (const_int 1)
23056 (const_int 1) (const_int 1)
23057 (const_int 1) (const_int 1)
23058 (const_int 1) (const_int 1)
23059 (const_int 1) (const_int 1)
23060 (const_int 1) (const_int 1)
23061 (const_int 1) (const_int 1)]))
23064 "pavgb\t{%2, %0|%0, %2}"
23065 [(set_attr "type" "sseiadd")
23066 (set_attr "mode" "TI")])
23068 (define_insn "sse2_uavgv8hi3"
23069 [(set (match_operand:V8HI 0 "register_operand" "=x")
23071 (plus:V8HI (plus:V8HI
23072 (match_operand:V8HI 1 "register_operand" "0")
23073 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
23074 (const_vector:V8HI [(const_int 1) (const_int 1)
23075 (const_int 1) (const_int 1)
23076 (const_int 1) (const_int 1)
23077 (const_int 1) (const_int 1)]))
23080 "pavgw\t{%2, %0|%0, %2}"
23081 [(set_attr "type" "sseiadd")
23082 (set_attr "mode" "TI")])
23084 ;; @@@ this isn't the right representation.
23085 (define_insn "sse2_psadbw"
23086 [(set (match_operand:V2DI 0 "register_operand" "=x")
23087 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
23088 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
23091 "psadbw\t{%2, %0|%0, %2}"
23092 [(set_attr "type" "sseiadd")
23093 (set_attr "mode" "TI")])
23096 ;; MMX insert/extract/shuffle
23098 (define_insn "sse2_pinsrw"
23099 [(set (match_operand:V8HI 0 "register_operand" "=x")
23100 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
23101 (vec_duplicate:V8HI
23103 (match_operand:SI 2 "nonimmediate_operand" "rm")))
23104 (match_operand:SI 3 "const_0_to_255_operand" "N")))]
23106 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
23107 [(set_attr "type" "ssecvt")
23108 (set_attr "mode" "TI")])
23110 (define_insn "sse2_pextrw"
23111 [(set (match_operand:SI 0 "register_operand" "=r")
23113 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
23115 [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
23117 "pextrw\t{%2, %1, %0|%0, %1, %2}"
23118 [(set_attr "type" "ssecvt")
23119 (set_attr "mode" "TI")])
23121 (define_insn "sse2_pshufd"
23122 [(set (match_operand:V4SI 0 "register_operand" "=x")
23123 (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
23124 (match_operand:SI 2 "immediate_operand" "i")]
23127 "pshufd\t{%2, %1, %0|%0, %1, %2}"
23128 [(set_attr "type" "ssecvt")
23129 (set_attr "mode" "TI")])
23131 (define_insn "sse2_pshuflw"
23132 [(set (match_operand:V8HI 0 "register_operand" "=x")
23133 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23134 (match_operand:SI 2 "immediate_operand" "i")]
23137 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
23138 [(set_attr "type" "ssecvt")
23139 (set_attr "mode" "TI")])
23141 (define_insn "sse2_pshufhw"
23142 [(set (match_operand:V8HI 0 "register_operand" "=x")
23143 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
23144 (match_operand:SI 2 "immediate_operand" "i")]
23147 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
23148 [(set_attr "type" "ssecvt")
23149 (set_attr "mode" "TI")])
23151 ;; MMX mask-generating comparisons
23153 (define_insn "eqv16qi3"
23154 [(set (match_operand:V16QI 0 "register_operand" "=x")
23155 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
23156 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23158 "pcmpeqb\t{%2, %0|%0, %2}"
23159 [(set_attr "type" "ssecmp")
23160 (set_attr "mode" "TI")])
23162 (define_insn "eqv8hi3"
23163 [(set (match_operand:V8HI 0 "register_operand" "=x")
23164 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
23165 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23167 "pcmpeqw\t{%2, %0|%0, %2}"
23168 [(set_attr "type" "ssecmp")
23169 (set_attr "mode" "TI")])
23171 (define_insn "eqv4si3"
23172 [(set (match_operand:V4SI 0 "register_operand" "=x")
23173 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
23174 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23176 "pcmpeqd\t{%2, %0|%0, %2}"
23177 [(set_attr "type" "ssecmp")
23178 (set_attr "mode" "TI")])
23180 (define_insn "gtv16qi3"
23181 [(set (match_operand:V16QI 0 "register_operand" "=x")
23182 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
23183 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23185 "pcmpgtb\t{%2, %0|%0, %2}"
23186 [(set_attr "type" "ssecmp")
23187 (set_attr "mode" "TI")])
23189 (define_insn "gtv8hi3"
23190 [(set (match_operand:V8HI 0 "register_operand" "=x")
23191 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23192 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23194 "pcmpgtw\t{%2, %0|%0, %2}"
23195 [(set_attr "type" "ssecmp")
23196 (set_attr "mode" "TI")])
23198 (define_insn "gtv4si3"
23199 [(set (match_operand:V4SI 0 "register_operand" "=x")
23200 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23201 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
23203 "pcmpgtd\t{%2, %0|%0, %2}"
23204 [(set_attr "type" "ssecmp")
23205 (set_attr "mode" "TI")])
23208 ;; MMX max/min insns
23210 (define_insn "umaxv16qi3"
23211 [(set (match_operand:V16QI 0 "register_operand" "=x")
23212 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
23213 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23215 "pmaxub\t{%2, %0|%0, %2}"
23216 [(set_attr "type" "sseiadd")
23217 (set_attr "mode" "TI")])
23219 (define_insn "smaxv8hi3"
23220 [(set (match_operand:V8HI 0 "register_operand" "=x")
23221 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
23222 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23224 "pmaxsw\t{%2, %0|%0, %2}"
23225 [(set_attr "type" "sseiadd")
23226 (set_attr "mode" "TI")])
23228 (define_insn "uminv16qi3"
23229 [(set (match_operand:V16QI 0 "register_operand" "=x")
23230 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
23231 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
23233 "pminub\t{%2, %0|%0, %2}"
23234 [(set_attr "type" "sseiadd")
23235 (set_attr "mode" "TI")])
23237 (define_insn "sminv8hi3"
23238 [(set (match_operand:V8HI 0 "register_operand" "=x")
23239 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
23240 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
23242 "pminsw\t{%2, %0|%0, %2}"
23243 [(set_attr "type" "sseiadd")
23244 (set_attr "mode" "TI")])
23249 (define_insn "ashrv8hi3"
23250 [(set (match_operand:V8HI 0 "register_operand" "=x")
23251 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23252 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23254 "psraw\t{%2, %0|%0, %2}"
23255 [(set_attr "type" "sseishft")
23256 (set_attr "mode" "TI")])
23258 (define_insn "ashrv4si3"
23259 [(set (match_operand:V4SI 0 "register_operand" "=x")
23260 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23261 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23263 "psrad\t{%2, %0|%0, %2}"
23264 [(set_attr "type" "sseishft")
23265 (set_attr "mode" "TI")])
23267 (define_insn "lshrv8hi3"
23268 [(set (match_operand:V8HI 0 "register_operand" "=x")
23269 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23270 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23272 "psrlw\t{%2, %0|%0, %2}"
23273 [(set_attr "type" "sseishft")
23274 (set_attr "mode" "TI")])
23276 (define_insn "lshrv4si3"
23277 [(set (match_operand:V4SI 0 "register_operand" "=x")
23278 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23279 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23281 "psrld\t{%2, %0|%0, %2}"
23282 [(set_attr "type" "sseishft")
23283 (set_attr "mode" "TI")])
23285 (define_insn "lshrv2di3"
23286 [(set (match_operand:V2DI 0 "register_operand" "=x")
23287 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23288 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23290 "psrlq\t{%2, %0|%0, %2}"
23291 [(set_attr "type" "sseishft")
23292 (set_attr "mode" "TI")])
23294 (define_insn "ashlv8hi3"
23295 [(set (match_operand:V8HI 0 "register_operand" "=x")
23296 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23297 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23299 "psllw\t{%2, %0|%0, %2}"
23300 [(set_attr "type" "sseishft")
23301 (set_attr "mode" "TI")])
23303 (define_insn "ashlv4si3"
23304 [(set (match_operand:V4SI 0 "register_operand" "=x")
23305 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23306 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23308 "pslld\t{%2, %0|%0, %2}"
23309 [(set_attr "type" "sseishft")
23310 (set_attr "mode" "TI")])
23312 (define_insn "ashlv2di3"
23313 [(set (match_operand:V2DI 0 "register_operand" "=x")
23314 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23315 (match_operand:SI 2 "nonmemory_operand" "xi")))]
23317 "psllq\t{%2, %0|%0, %2}"
23318 [(set_attr "type" "sseishft")
23319 (set_attr "mode" "TI")])
23321 (define_insn "ashrv8hi3_ti"
23322 [(set (match_operand:V8HI 0 "register_operand" "=x")
23323 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23324 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23326 "psraw\t{%2, %0|%0, %2}"
23327 [(set_attr "type" "sseishft")
23328 (set_attr "mode" "TI")])
23330 (define_insn "ashrv4si3_ti"
23331 [(set (match_operand:V4SI 0 "register_operand" "=x")
23332 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23333 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23335 "psrad\t{%2, %0|%0, %2}"
23336 [(set_attr "type" "sseishft")
23337 (set_attr "mode" "TI")])
23339 (define_insn "lshrv8hi3_ti"
23340 [(set (match_operand:V8HI 0 "register_operand" "=x")
23341 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
23342 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23344 "psrlw\t{%2, %0|%0, %2}"
23345 [(set_attr "type" "sseishft")
23346 (set_attr "mode" "TI")])
23348 (define_insn "lshrv4si3_ti"
23349 [(set (match_operand:V4SI 0 "register_operand" "=x")
23350 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23351 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23353 "psrld\t{%2, %0|%0, %2}"
23354 [(set_attr "type" "sseishft")
23355 (set_attr "mode" "TI")])
23357 (define_insn "lshrv2di3_ti"
23358 [(set (match_operand:V2DI 0 "register_operand" "=x")
23359 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23360 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23362 "psrlq\t{%2, %0|%0, %2}"
23363 [(set_attr "type" "sseishft")
23364 (set_attr "mode" "TI")])
23366 (define_insn "ashlv8hi3_ti"
23367 [(set (match_operand:V8HI 0 "register_operand" "=x")
23368 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23369 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23371 "psllw\t{%2, %0|%0, %2}"
23372 [(set_attr "type" "sseishft")
23373 (set_attr "mode" "TI")])
23375 (define_insn "ashlv4si3_ti"
23376 [(set (match_operand:V4SI 0 "register_operand" "=x")
23377 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23378 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23380 "pslld\t{%2, %0|%0, %2}"
23381 [(set_attr "type" "sseishft")
23382 (set_attr "mode" "TI")])
23384 (define_insn "ashlv2di3_ti"
23385 [(set (match_operand:V2DI 0 "register_operand" "=x")
23386 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23387 (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23389 "psllq\t{%2, %0|%0, %2}"
23390 [(set_attr "type" "sseishft")
23391 (set_attr "mode" "TI")])
23393 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
23394 ;; we wouldn't need here it since we never generate TImode arithmetic.
23396 ;; There has to be some kind of prize for the weirdest new instruction...
23397 (define_insn "sse2_ashlti3"
23398 [(set (match_operand:TI 0 "register_operand" "=x")
23400 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
23401 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23402 (const_int 8)))] UNSPEC_NOP))]
23404 "pslldq\t{%2, %0|%0, %2}"
23405 [(set_attr "type" "sseishft")
23406 (set_attr "mode" "TI")])
23408 (define_insn "sse2_lshrti3"
23409 [(set (match_operand:TI 0 "register_operand" "=x")
23411 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
23412 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23413 (const_int 8)))] UNSPEC_NOP))]
23415 "psrldq\t{%2, %0|%0, %2}"
23416 [(set_attr "type" "sseishft")
23417 (set_attr "mode" "TI")])
23421 (define_insn "sse2_unpckhpd"
23422 [(set (match_operand:V2DF 0 "register_operand" "=x")
23424 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23425 (parallel [(const_int 1)]))
23426 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23427 (parallel [(const_int 1)]))))]
23429 "unpckhpd\t{%2, %0|%0, %2}"
23430 [(set_attr "type" "ssecvt")
23431 (set_attr "mode" "V2DF")])
23433 (define_insn "sse2_unpcklpd"
23434 [(set (match_operand:V2DF 0 "register_operand" "=x")
23436 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23437 (parallel [(const_int 0)]))
23438 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23439 (parallel [(const_int 0)]))))]
23441 "unpcklpd\t{%2, %0|%0, %2}"
23442 [(set_attr "type" "ssecvt")
23443 (set_attr "mode" "V2DF")])
23445 ;; MMX pack/unpack insns.
23447 (define_insn "sse2_packsswb"
23448 [(set (match_operand:V16QI 0 "register_operand" "=x")
23450 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23451 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23453 "packsswb\t{%2, %0|%0, %2}"
23454 [(set_attr "type" "ssecvt")
23455 (set_attr "mode" "TI")])
23457 (define_insn "sse2_packssdw"
23458 [(set (match_operand:V8HI 0 "register_operand" "=x")
23460 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
23461 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
23463 "packssdw\t{%2, %0|%0, %2}"
23464 [(set_attr "type" "ssecvt")
23465 (set_attr "mode" "TI")])
23467 (define_insn "sse2_packuswb"
23468 [(set (match_operand:V16QI 0 "register_operand" "=x")
23470 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23471 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23473 "packuswb\t{%2, %0|%0, %2}"
23474 [(set_attr "type" "ssecvt")
23475 (set_attr "mode" "TI")])
23477 (define_insn "sse2_punpckhbw"
23478 [(set (match_operand:V16QI 0 "register_operand" "=x")
23480 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23481 (parallel [(const_int 8) (const_int 0)
23482 (const_int 9) (const_int 1)
23483 (const_int 10) (const_int 2)
23484 (const_int 11) (const_int 3)
23485 (const_int 12) (const_int 4)
23486 (const_int 13) (const_int 5)
23487 (const_int 14) (const_int 6)
23488 (const_int 15) (const_int 7)]))
23489 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23490 (parallel [(const_int 0) (const_int 8)
23491 (const_int 1) (const_int 9)
23492 (const_int 2) (const_int 10)
23493 (const_int 3) (const_int 11)
23494 (const_int 4) (const_int 12)
23495 (const_int 5) (const_int 13)
23496 (const_int 6) (const_int 14)
23497 (const_int 7) (const_int 15)]))
23498 (const_int 21845)))]
23500 "punpckhbw\t{%2, %0|%0, %2}"
23501 [(set_attr "type" "ssecvt")
23502 (set_attr "mode" "TI")])
23504 (define_insn "sse2_punpckhwd"
23505 [(set (match_operand:V8HI 0 "register_operand" "=x")
23507 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23508 (parallel [(const_int 4) (const_int 0)
23509 (const_int 5) (const_int 1)
23510 (const_int 6) (const_int 2)
23511 (const_int 7) (const_int 3)]))
23512 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23513 (parallel [(const_int 0) (const_int 4)
23514 (const_int 1) (const_int 5)
23515 (const_int 2) (const_int 6)
23516 (const_int 3) (const_int 7)]))
23519 "punpckhwd\t{%2, %0|%0, %2}"
23520 [(set_attr "type" "ssecvt")
23521 (set_attr "mode" "TI")])
23523 (define_insn "sse2_punpckhdq"
23524 [(set (match_operand:V4SI 0 "register_operand" "=x")
23526 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23527 (parallel [(const_int 2) (const_int 0)
23528 (const_int 3) (const_int 1)]))
23529 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23530 (parallel [(const_int 0) (const_int 2)
23531 (const_int 1) (const_int 3)]))
23534 "punpckhdq\t{%2, %0|%0, %2}"
23535 [(set_attr "type" "ssecvt")
23536 (set_attr "mode" "TI")])
23538 (define_insn "sse2_punpcklbw"
23539 [(set (match_operand:V16QI 0 "register_operand" "=x")
23541 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23542 (parallel [(const_int 0) (const_int 8)
23543 (const_int 1) (const_int 9)
23544 (const_int 2) (const_int 10)
23545 (const_int 3) (const_int 11)
23546 (const_int 4) (const_int 12)
23547 (const_int 5) (const_int 13)
23548 (const_int 6) (const_int 14)
23549 (const_int 7) (const_int 15)]))
23550 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23551 (parallel [(const_int 8) (const_int 0)
23552 (const_int 9) (const_int 1)
23553 (const_int 10) (const_int 2)
23554 (const_int 11) (const_int 3)
23555 (const_int 12) (const_int 4)
23556 (const_int 13) (const_int 5)
23557 (const_int 14) (const_int 6)
23558 (const_int 15) (const_int 7)]))
23559 (const_int 21845)))]
23561 "punpcklbw\t{%2, %0|%0, %2}"
23562 [(set_attr "type" "ssecvt")
23563 (set_attr "mode" "TI")])
23565 (define_insn "sse2_punpcklwd"
23566 [(set (match_operand:V8HI 0 "register_operand" "=x")
23568 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23569 (parallel [(const_int 0) (const_int 4)
23570 (const_int 1) (const_int 5)
23571 (const_int 2) (const_int 6)
23572 (const_int 3) (const_int 7)]))
23573 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23574 (parallel [(const_int 4) (const_int 0)
23575 (const_int 5) (const_int 1)
23576 (const_int 6) (const_int 2)
23577 (const_int 7) (const_int 3)]))
23580 "punpcklwd\t{%2, %0|%0, %2}"
23581 [(set_attr "type" "ssecvt")
23582 (set_attr "mode" "TI")])
23584 (define_insn "sse2_punpckldq"
23585 [(set (match_operand:V4SI 0 "register_operand" "=x")
23587 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23588 (parallel [(const_int 0) (const_int 2)
23589 (const_int 1) (const_int 3)]))
23590 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23591 (parallel [(const_int 2) (const_int 0)
23592 (const_int 3) (const_int 1)]))
23595 "punpckldq\t{%2, %0|%0, %2}"
23596 [(set_attr "type" "ssecvt")
23597 (set_attr "mode" "TI")])
23599 (define_insn "sse2_punpcklqdq"
23600 [(set (match_operand:V2DI 0 "register_operand" "=x")
23602 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23603 (parallel [(const_int 1)
23605 (match_operand:V2DI 1 "register_operand" "0")
23608 "punpcklqdq\t{%2, %0|%0, %2}"
23609 [(set_attr "type" "ssecvt")
23610 (set_attr "mode" "TI")])
23612 (define_insn "sse2_punpckhqdq"
23613 [(set (match_operand:V2DI 0 "register_operand" "=x")
23615 (match_operand:V2DI 1 "register_operand" "0")
23616 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23617 (parallel [(const_int 1)
23621 "punpckhqdq\t{%2, %0|%0, %2}"
23622 [(set_attr "type" "ssecvt")
23623 (set_attr "mode" "TI")])
23627 (define_insn "sse2_movapd"
23628 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23629 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23632 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23633 "movapd\t{%1, %0|%0, %1}"
23634 [(set_attr "type" "ssemov")
23635 (set_attr "mode" "V2DF")])
23637 (define_insn "sse2_movupd"
23638 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23639 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23642 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23643 "movupd\t{%1, %0|%0, %1}"
23644 [(set_attr "type" "ssecvt")
23645 (set_attr "mode" "V2DF")])
23647 (define_insn "sse2_movdqa"
23648 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23649 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23652 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23653 "movdqa\t{%1, %0|%0, %1}"
23654 [(set_attr "type" "ssemov")
23655 (set_attr "mode" "TI")])
23657 (define_insn "sse2_movdqu"
23658 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23659 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23662 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23663 "movdqu\t{%1, %0|%0, %1}"
23664 [(set_attr "type" "ssecvt")
23665 (set_attr "mode" "TI")])
23667 (define_insn "sse2_movdq2q"
23668 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
23669 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
23670 (parallel [(const_int 0)])))]
23671 "TARGET_SSE2 && !TARGET_64BIT"
23673 movq\t{%1, %0|%0, %1}
23674 movdq2q\t{%1, %0|%0, %1}"
23675 [(set_attr "type" "ssecvt")
23676 (set_attr "mode" "TI")])
23678 (define_insn "sse2_movdq2q_rex64"
23679 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
23680 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
23681 (parallel [(const_int 0)])))]
23682 "TARGET_SSE2 && TARGET_64BIT"
23684 movq\t{%1, %0|%0, %1}
23685 movdq2q\t{%1, %0|%0, %1}
23686 movd\t{%1, %0|%0, %1}"
23687 [(set_attr "type" "ssecvt")
23688 (set_attr "mode" "TI")])
23690 (define_insn "sse2_movq2dq"
23691 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
23692 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
23694 "TARGET_SSE2 && !TARGET_64BIT"
23696 movq\t{%1, %0|%0, %1}
23697 movq2dq\t{%1, %0|%0, %1}"
23698 [(set_attr "type" "ssecvt,ssemov")
23699 (set_attr "mode" "TI")])
23701 (define_insn "sse2_movq2dq_rex64"
23702 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
23703 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
23705 "TARGET_SSE2 && TARGET_64BIT"
23707 movq\t{%1, %0|%0, %1}
23708 movq2dq\t{%1, %0|%0, %1}
23709 movd\t{%1, %0|%0, %1}"
23710 [(set_attr "type" "ssecvt,ssemov,ssecvt")
23711 (set_attr "mode" "TI")])
23713 (define_insn "sse2_movq"
23714 [(set (match_operand:V2DI 0 "register_operand" "=x")
23715 (vec_concat:V2DI (vec_select:DI
23716 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
23717 (parallel [(const_int 0)]))
23720 "movq\t{%1, %0|%0, %1}"
23721 [(set_attr "type" "ssemov")
23722 (set_attr "mode" "TI")])
23724 (define_insn "sse2_loadd"
23725 [(set (match_operand:V4SI 0 "register_operand" "=x")
23727 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
23728 (const_vector:V4SI [(const_int 0)
23734 "movd\t{%1, %0|%0, %1}"
23735 [(set_attr "type" "ssemov")
23736 (set_attr "mode" "TI")])
23738 (define_insn "sse2_stored"
23739 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
23741 (match_operand:V4SI 1 "register_operand" "x")
23742 (parallel [(const_int 0)])))]
23744 "movd\t{%1, %0|%0, %1}"
23745 [(set_attr "type" "ssemov")
23746 (set_attr "mode" "TI")])
23748 ;; Store the high double of the source vector into the double destination.
23749 (define_insn "sse2_storehpd"
23750 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,Y,Y")
23752 (match_operand:V2DF 1 "nonimmediate_operand" " Y,0,o")
23753 (parallel [(const_int 1)])))]
23756 movhpd\t{%1, %0|%0, %1}
23759 [(set_attr "type" "ssecvt")
23760 (set_attr "mode" "V2DF")])
23763 [(set (match_operand:DF 0 "register_operand" "")
23765 (match_operand:V2DF 1 "memory_operand" "")
23766 (parallel [(const_int 1)])))]
23767 "TARGET_SSE2 && reload_completed"
23770 emit_move_insn (operands[0], adjust_address (operands[1], DFmode, 8));
23774 ;; Load the high double of the target vector from the source scalar.
23775 (define_insn "sse2_loadhpd"
23776 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=Y,Y,o")
23779 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
23780 (parallel [(const_int 0)]))
23781 (match_operand:DF 2 "nonimmediate_operand" " m,Y,Y")))]
23784 movhpd\t{%2, %0|%0, %2}
23785 unpcklpd\t{%2, %0|%0, %2}
23787 [(set_attr "type" "ssecvt")
23788 (set_attr "mode" "V2DF")])
23791 [(set (match_operand:V2DF 0 "memory_operand" "")
23793 (vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
23794 (match_operand:DF 1 "register_operand" "")))]
23795 "TARGET_SSE2 && reload_completed"
23798 emit_move_insn (adjust_address (operands[0], DFmode, 8), operands[1]);
23802 ;; Store the low double of the source vector into the double destination.
23803 (define_expand "sse2_storelpd"
23804 [(set (match_operand:DF 0 "nonimmediate_operand" "")
23806 (match_operand:V2DF 1 "nonimmediate_operand" "")
23807 (parallel [(const_int 1)])))]
23810 operands[1] = gen_lowpart (DFmode, operands[1]);
23811 emit_move_insn (operands[0], operands[1]);
23815 ;; Load the load double of the target vector from the source scalar.
23816 (define_insn "sse2_loadlpd"
23817 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=Y,Y,m")
23819 (match_operand:DF 2 "nonimmediate_operand" " m,Y,Y")
23821 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
23822 (parallel [(const_int 1)]))))]
23825 movlpd\t{%2, %0|%0, %2}
23826 movsd\t{%2, %0|%0, %2}
23827 movlpd\t{%2, %0|%0, %2}"
23828 [(set_attr "type" "ssecvt")
23829 (set_attr "mode" "V2DF")])
23831 ;; Merge the low part of the source vector into the low part of the target.
23832 (define_insn "sse2_movsd"
23833 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=Y,Y,m")
23835 (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
23836 (match_operand:V2DF 2 "nonimmediate_operand" "x,m,Y")
23839 "@movsd\t{%2, %0|%0, %2}
23840 movlpd\t{%2, %0|%0, %2}
23841 movlpd\t{%2, %0|%0, %2}"
23842 [(set_attr "type" "ssecvt")
23843 (set_attr "mode" "DF,V2DF,V2DF")])
23845 (define_expand "sse2_loadsd"
23846 [(match_operand:V2DF 0 "register_operand" "")
23847 (match_operand:DF 1 "memory_operand" "")]
23850 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23851 CONST0_RTX (V2DFmode)));
23855 (define_insn "sse2_loadsd_1"
23856 [(set (match_operand:V2DF 0 "register_operand" "=x")
23858 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
23859 (match_operand:V2DF 2 "const0_operand" "X")
23862 "movsd\t{%1, %0|%0, %1}"
23863 [(set_attr "type" "ssecvt")
23864 (set_attr "mode" "DF")])
23866 (define_insn "sse2_storesd"
23867 [(set (match_operand:DF 0 "memory_operand" "=m")
23869 (match_operand:V2DF 1 "register_operand" "x")
23870 (parallel [(const_int 0)])))]
23872 "movsd\t{%1, %0|%0, %1}"
23873 [(set_attr "type" "ssecvt")
23874 (set_attr "mode" "DF")])
23876 (define_insn "sse2_shufpd"
23877 [(set (match_operand:V2DF 0 "register_operand" "=x")
23878 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23879 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
23880 (match_operand:SI 3 "immediate_operand" "i")]
23883 ;; @@@ check operand order for intel/nonintel syntax
23884 "shufpd\t{%3, %2, %0|%0, %2, %3}"
23885 [(set_attr "type" "ssecvt")
23886 (set_attr "mode" "V2DF")])
23888 (define_insn "sse2_clflush"
23889 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
23893 [(set_attr "type" "sse")
23894 (set_attr "memory" "unknown")])
23896 (define_expand "sse2_mfence"
23897 [(set (match_dup 0)
23898 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23901 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23902 MEM_VOLATILE_P (operands[0]) = 1;
23905 (define_insn "*mfence_insn"
23906 [(set (match_operand:BLK 0 "" "")
23907 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23910 [(set_attr "type" "sse")
23911 (set_attr "memory" "unknown")])
23913 (define_expand "sse2_lfence"
23914 [(set (match_dup 0)
23915 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23918 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23919 MEM_VOLATILE_P (operands[0]) = 1;
23922 (define_insn "*lfence_insn"
23923 [(set (match_operand:BLK 0 "" "")
23924 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23927 [(set_attr "type" "sse")
23928 (set_attr "memory" "unknown")])
23932 (define_insn "mwait"
23933 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
23934 (match_operand:SI 1 "register_operand" "c")]
23938 [(set_attr "length" "3")])
23940 (define_insn "monitor"
23941 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
23942 (match_operand:SI 1 "register_operand" "c")
23943 (match_operand:SI 2 "register_operand" "d")]
23946 "monitor\t%0, %1, %2"
23947 [(set_attr "length" "3")])
23951 (define_insn "addsubv4sf3"
23952 [(set (match_operand:V4SF 0 "register_operand" "=x")
23953 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
23954 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
23957 "addsubps\t{%2, %0|%0, %2}"
23958 [(set_attr "type" "sseadd")
23959 (set_attr "mode" "V4SF")])
23961 (define_insn "addsubv2df3"
23962 [(set (match_operand:V2DF 0 "register_operand" "=x")
23963 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23964 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
23967 "addsubpd\t{%2, %0|%0, %2}"
23968 [(set_attr "type" "sseadd")
23969 (set_attr "mode" "V2DF")])
23971 (define_insn "haddv4sf3"
23972 [(set (match_operand:V4SF 0 "register_operand" "=x")
23973 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
23974 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
23977 "haddps\t{%2, %0|%0, %2}"
23978 [(set_attr "type" "sseadd")
23979 (set_attr "mode" "V4SF")])
23981 (define_insn "haddv2df3"
23982 [(set (match_operand:V2DF 0 "register_operand" "=x")
23983 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23984 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
23987 "haddpd\t{%2, %0|%0, %2}"
23988 [(set_attr "type" "sseadd")
23989 (set_attr "mode" "V2DF")])
23991 (define_insn "hsubv4sf3"
23992 [(set (match_operand:V4SF 0 "register_operand" "=x")
23993 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
23994 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
23997 "hsubps\t{%2, %0|%0, %2}"
23998 [(set_attr "type" "sseadd")
23999 (set_attr "mode" "V4SF")])
24001 (define_insn "hsubv2df3"
24002 [(set (match_operand:V2DF 0 "register_operand" "=x")
24003 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
24004 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
24007 "hsubpd\t{%2, %0|%0, %2}"
24008 [(set_attr "type" "sseadd")
24009 (set_attr "mode" "V2DF")])
24011 (define_insn "movshdup"
24012 [(set (match_operand:V4SF 0 "register_operand" "=x")
24014 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
24016 "movshdup\t{%1, %0|%0, %1}"
24017 [(set_attr "type" "sse")
24018 (set_attr "mode" "V4SF")])
24020 (define_insn "movsldup"
24021 [(set (match_operand:V4SF 0 "register_operand" "=x")
24023 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
24025 "movsldup\t{%1, %0|%0, %1}"
24026 [(set_attr "type" "sse")
24027 (set_attr "mode" "V4SF")])
24029 (define_insn "lddqu"
24030 [(set (match_operand:V16QI 0 "register_operand" "=x")
24031 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
24034 "lddqu\t{%1, %0|%0, %1}"
24035 [(set_attr "type" "ssecvt")
24036 (set_attr "mode" "TI")])
24038 (define_insn "loadddup"
24039 [(set (match_operand:V2DF 0 "register_operand" "=x")
24040 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
24042 "movddup\t{%1, %0|%0, %1}"
24043 [(set_attr "type" "ssecvt")
24044 (set_attr "mode" "DF")])
24046 (define_insn "movddup"
24047 [(set (match_operand:V2DF 0 "register_operand" "=x")
24048 (vec_duplicate:V2DF
24049 (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
24050 (parallel [(const_int 0)]))))]
24052 "movddup\t{%1, %0|%0, %1}"
24053 [(set_attr "type" "ssecvt")
24054 (set_attr "mode" "DF")])