1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>. */
24 ;; The original PO technology requires these to be ordered by speed,
25 ;; so that assigner will pick the fastest.
27 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; The special asm out single letter directives following a '%' are:
30 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
32 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
33 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
34 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
35 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
36 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
37 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
38 ;; 'J' Print the appropriate jump operand.
40 ;; 'b' Print the QImode name of the register for the indicated operand.
41 ;; %b0 would print %al if operands[0] is reg 0.
42 ;; 'w' Likewise, print the HImode name of the register.
43 ;; 'k' Likewise, print the SImode name of the register.
44 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
45 ;; 'y' Print "st(0)" instead of "st" as a register.
50 [; Relocation specifiers
63 (UNSPEC_STACK_ALLOC 11)
65 (UNSPEC_SSE_PROLOGUE_SAVE 13)
69 (UNSPEC_SET_GOT_OFFSET 17)
74 (UNSPEC_TLS_LD_BASE 20)
77 ; Other random patterns
86 (UNSPEC_LD_MPIC 38) ; load_macho_picbase
87 (UNSPEC_TRUNC_NOOP 39)
89 ; For SSE/MMX support:
90 (UNSPEC_FIX_NOTRUNC 40)
98 (UNSPEC_NOP 48) ; prevents combiner cleverness
109 ; Generic math support
111 (UNSPEC_IEEE_MIN 51) ; not commutative
112 (UNSPEC_IEEE_MAX 52) ; not commutative
127 (UNSPEC_FRNDINT_FLOOR 70)
128 (UNSPEC_FRNDINT_CEIL 71)
129 (UNSPEC_FRNDINT_TRUNC 72)
130 (UNSPEC_FRNDINT_MASK_PM 73)
131 (UNSPEC_FIST_FLOOR 74)
132 (UNSPEC_FIST_CEIL 75)
134 ; x87 Double output FP
135 (UNSPEC_SINCOS_COS 80)
136 (UNSPEC_SINCOS_SIN 81)
137 (UNSPEC_XTRACT_FRACT 84)
138 (UNSPEC_XTRACT_EXP 85)
139 (UNSPEC_FSCALE_FRACT 86)
140 (UNSPEC_FSCALE_EXP 87)
151 (UNSPEC_SP_TLS_SET 102)
152 (UNSPEC_SP_TLS_TEST 103)
162 (UNSPEC_INSERTQI 132)
167 (UNSPEC_INSERTPS 135)
169 (UNSPEC_MOVNTDQA 137)
171 (UNSPEC_PHMINPOSUW 139)
177 (UNSPEC_PCMPESTR 144)
178 (UNSPEC_PCMPISTR 145)
181 (UNSPEC_SSE5_INTRINSIC 150)
182 (UNSPEC_SSE5_UNSIGNED_CMP 151)
183 (UNSPEC_SSE5_TRUEFALSE 152)
184 (UNSPEC_SSE5_PERMUTE 153)
185 (UNSPEC_SSE5_ASHIFT 154)
186 (UNSPEC_SSE5_LSHIFT 155)
188 (UNSPEC_CVTPH2PS 157)
189 (UNSPEC_CVTPS2PH 158)
193 [(UNSPECV_BLOCKAGE 0)
194 (UNSPECV_STACK_PROBE 1)
203 (UNSPECV_CMPXCHG_1 10)
204 (UNSPECV_CMPXCHG_2 11)
207 (UNSPECV_PROLOGUE_USE 14)
210 ;; Constants to represent pcomtrue/pcomfalse variants
220 ;; Registers by name.
236 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
239 ;; In C guard expressions, put expressions which may be compile-time
240 ;; constants first. This allows for better optimization. For
241 ;; example, write "TARGET_64BIT && reload_completed", not
242 ;; "reload_completed && TARGET_64BIT".
245 ;; Processor type. This attribute must exactly match the processor_type
246 ;; enumeration in i386.h.
247 (define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
248 nocona,core2,generic32,generic64,amdfam10"
249 (const (symbol_ref "ix86_tune")))
251 ;; A basic instruction type. Refinements due to arguments to be
252 ;; provided in other attributes.
255 alu,alu1,negnot,imov,imovx,lea,
256 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
257 icmp,test,ibr,setcc,icmov,
258 push,pop,call,callv,leave,
260 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
261 sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
262 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
264 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
265 (const_string "other"))
267 ;; Main data type used by the insn
269 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
270 (const_string "unknown"))
272 ;; The CPU unit operations uses.
273 (define_attr "unit" "integer,i387,sse,mmx,unknown"
274 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
275 (const_string "i387")
276 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
277 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,
278 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
280 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
282 (eq_attr "type" "other")
283 (const_string "unknown")]
284 (const_string "integer")))
286 ;; The (bounding maximum) length of an instruction immediate.
287 (define_attr "length_immediate" ""
288 (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
291 (eq_attr "unit" "i387,sse,mmx")
293 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
295 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
296 (eq_attr "type" "imov,test")
297 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
298 (eq_attr "type" "call")
299 (if_then_else (match_operand 0 "constant_call_address_operand" "")
302 (eq_attr "type" "callv")
303 (if_then_else (match_operand 1 "constant_call_address_operand" "")
306 ;; We don't know the size before shorten_branches. Expect
307 ;; the instruction to fit for better scheduling.
308 (eq_attr "type" "ibr")
311 (symbol_ref "/* Update immediate_length and other attributes! */
312 gcc_unreachable (),1")))
314 ;; The (bounding maximum) length of an instruction address.
315 (define_attr "length_address" ""
316 (cond [(eq_attr "type" "str,other,multi,fxch")
318 (and (eq_attr "type" "call")
319 (match_operand 0 "constant_call_address_operand" ""))
321 (and (eq_attr "type" "callv")
322 (match_operand 1 "constant_call_address_operand" ""))
325 (symbol_ref "ix86_attr_length_address_default (insn)")))
327 ;; Set when length prefix is used.
328 (define_attr "prefix_data16" ""
329 (if_then_else (ior (eq_attr "mode" "HI")
330 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
334 ;; Set when string REP prefix is used.
335 (define_attr "prefix_rep" ""
336 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
340 ;; Set when 0f opcode prefix is used.
341 (define_attr "prefix_0f" ""
343 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
344 (eq_attr "unit" "sse,mmx"))
348 ;; Set when REX opcode prefix is used.
349 (define_attr "prefix_rex" ""
350 (cond [(and (eq_attr "mode" "DI")
351 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
353 (and (eq_attr "mode" "QI")
354 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
357 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
363 ;; There are also additional prefixes in SSSE3.
364 (define_attr "prefix_extra" "" (const_int 0))
366 ;; Set when modrm byte is used.
367 (define_attr "modrm" ""
368 (cond [(eq_attr "type" "str,leave")
370 (eq_attr "unit" "i387")
372 (and (eq_attr "type" "incdec")
373 (ior (match_operand:SI 1 "register_operand" "")
374 (match_operand:HI 1 "register_operand" "")))
376 (and (eq_attr "type" "push")
377 (not (match_operand 1 "memory_operand" "")))
379 (and (eq_attr "type" "pop")
380 (not (match_operand 0 "memory_operand" "")))
382 (and (eq_attr "type" "imov")
383 (ior (and (match_operand 0 "register_operand" "")
384 (match_operand 1 "immediate_operand" ""))
385 (ior (and (match_operand 0 "ax_reg_operand" "")
386 (match_operand 1 "memory_displacement_only_operand" ""))
387 (and (match_operand 0 "memory_displacement_only_operand" "")
388 (match_operand 1 "ax_reg_operand" "")))))
390 (and (eq_attr "type" "call")
391 (match_operand 0 "constant_call_address_operand" ""))
393 (and (eq_attr "type" "callv")
394 (match_operand 1 "constant_call_address_operand" ""))
399 ;; The (bounding maximum) length of an instruction in bytes.
400 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
401 ;; Later we may want to split them and compute proper length as for
403 (define_attr "length" ""
404 (cond [(eq_attr "type" "other,multi,fistp,frndint")
406 (eq_attr "type" "fcmp")
408 (eq_attr "unit" "i387")
410 (plus (attr "prefix_data16")
411 (attr "length_address")))]
412 (plus (plus (attr "modrm")
413 (plus (attr "prefix_0f")
414 (plus (attr "prefix_rex")
415 (plus (attr "prefix_extra")
417 (plus (attr "prefix_rep")
418 (plus (attr "prefix_data16")
419 (plus (attr "length_immediate")
420 (attr "length_address")))))))
422 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
423 ;; `store' if there is a simple memory reference therein, or `unknown'
424 ;; if the instruction is complex.
426 (define_attr "memory" "none,load,store,both,unknown"
427 (cond [(eq_attr "type" "other,multi,str")
428 (const_string "unknown")
429 (eq_attr "type" "lea,fcmov,fpspc")
430 (const_string "none")
431 (eq_attr "type" "fistp,leave")
432 (const_string "both")
433 (eq_attr "type" "frndint")
434 (const_string "load")
435 (eq_attr "type" "push")
436 (if_then_else (match_operand 1 "memory_operand" "")
437 (const_string "both")
438 (const_string "store"))
439 (eq_attr "type" "pop")
440 (if_then_else (match_operand 0 "memory_operand" "")
441 (const_string "both")
442 (const_string "load"))
443 (eq_attr "type" "setcc")
444 (if_then_else (match_operand 0 "memory_operand" "")
445 (const_string "store")
446 (const_string "none"))
447 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
448 (if_then_else (ior (match_operand 0 "memory_operand" "")
449 (match_operand 1 "memory_operand" ""))
450 (const_string "load")
451 (const_string "none"))
452 (eq_attr "type" "ibr")
453 (if_then_else (match_operand 0 "memory_operand" "")
454 (const_string "load")
455 (const_string "none"))
456 (eq_attr "type" "call")
457 (if_then_else (match_operand 0 "constant_call_address_operand" "")
458 (const_string "none")
459 (const_string "load"))
460 (eq_attr "type" "callv")
461 (if_then_else (match_operand 1 "constant_call_address_operand" "")
462 (const_string "none")
463 (const_string "load"))
464 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
465 (match_operand 1 "memory_operand" ""))
466 (const_string "both")
467 (and (match_operand 0 "memory_operand" "")
468 (match_operand 1 "memory_operand" ""))
469 (const_string "both")
470 (match_operand 0 "memory_operand" "")
471 (const_string "store")
472 (match_operand 1 "memory_operand" "")
473 (const_string "load")
475 "!alu1,negnot,ishift1,
476 imov,imovx,icmp,test,bitmanip,
478 sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
479 sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
480 (match_operand 2 "memory_operand" ""))
481 (const_string "load")
482 (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
483 (match_operand 3 "memory_operand" ""))
484 (const_string "load")
486 (const_string "none")))
488 ;; Indicates if an instruction has both an immediate and a displacement.
490 (define_attr "imm_disp" "false,true,unknown"
491 (cond [(eq_attr "type" "other,multi")
492 (const_string "unknown")
493 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
494 (and (match_operand 0 "memory_displacement_operand" "")
495 (match_operand 1 "immediate_operand" "")))
496 (const_string "true")
497 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
498 (and (match_operand 0 "memory_displacement_operand" "")
499 (match_operand 2 "immediate_operand" "")))
500 (const_string "true")
502 (const_string "false")))
504 ;; Indicates if an FP operation has an integer source.
506 (define_attr "fp_int_src" "false,true"
507 (const_string "false"))
509 ;; Defines rounding mode of an FP operation.
511 (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
512 (const_string "any"))
514 ;; Describe a user's asm statement.
515 (define_asm_attributes
516 [(set_attr "length" "128")
517 (set_attr "type" "multi")])
519 (define_code_iterator plusminus [plus minus])
521 ;; Base name for define_insn and insn mnemonic.
522 (define_code_attr addsub [(plus "add") (minus "sub")])
524 ;; Mark commutative operators as such in constraints.
525 (define_code_attr comm [(plus "%") (minus "")])
527 ;; All single word integer modes.
528 (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
530 ;; Instruction suffix for integer modes.
531 (define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
533 ;; Register class for integer modes.
534 (define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
536 ;; Immediate operand constraint for integer modes.
537 (define_mode_attr i [(QI "i") (HI "i") (SI "i") (DI "e")])
539 ;; General operand predicate for integer modes.
540 (define_mode_attr general_operand
541 [(QI "general_operand")
542 (HI "general_operand")
543 (SI "general_operand")
544 (DI "x86_64_general_operand")])
546 ;; SSE and x87 SFmode and DFmode floating point modes
547 (define_mode_iterator MODEF [SF DF])
549 ;; All x87 floating point modes
550 (define_mode_iterator X87MODEF [SF DF XF])
552 ;; All integer modes handled by x87 fisttp operator.
553 (define_mode_iterator X87MODEI [HI SI DI])
555 ;; All integer modes handled by integer x87 operators.
556 (define_mode_iterator X87MODEI12 [HI SI])
558 ;; All integer modes handled by SSE cvtts?2si* operators.
559 (define_mode_iterator SSEMODEI24 [SI DI])
561 ;; SSE asm suffix for floating point modes
562 (define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])
564 ;; SSE vector mode corresponding to a scalar mode
565 (define_mode_attr ssevecmode
566 [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
568 ;; Scheduling descriptions
570 (include "pentium.md")
573 (include "athlon.md")
577 ;; Operand and operator predicates and constraints
579 (include "predicates.md")
580 (include "constraints.md")
583 ;; Compare instructions.
585 ;; All compare insns have expanders that save the operands away without
586 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
587 ;; after the cmp) will actually emit the cmpM.
589 (define_expand "cmpti"
590 [(set (reg:CC FLAGS_REG)
591 (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
592 (match_operand:TI 1 "x86_64_general_operand" "")))]
595 if (MEM_P (operands[0]) && MEM_P (operands[1]))
596 operands[0] = force_reg (TImode, operands[0]);
597 ix86_compare_op0 = operands[0];
598 ix86_compare_op1 = operands[1];
602 (define_expand "cmpdi"
603 [(set (reg:CC FLAGS_REG)
604 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
605 (match_operand:DI 1 "x86_64_general_operand" "")))]
608 if (MEM_P (operands[0]) && MEM_P (operands[1]))
609 operands[0] = force_reg (DImode, operands[0]);
610 ix86_compare_op0 = operands[0];
611 ix86_compare_op1 = operands[1];
615 (define_expand "cmpsi"
616 [(set (reg:CC FLAGS_REG)
617 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
618 (match_operand:SI 1 "general_operand" "")))]
621 if (MEM_P (operands[0]) && MEM_P (operands[1]))
622 operands[0] = force_reg (SImode, operands[0]);
623 ix86_compare_op0 = operands[0];
624 ix86_compare_op1 = operands[1];
628 (define_expand "cmphi"
629 [(set (reg:CC FLAGS_REG)
630 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
631 (match_operand:HI 1 "general_operand" "")))]
634 if (MEM_P (operands[0]) && MEM_P (operands[1]))
635 operands[0] = force_reg (HImode, operands[0]);
636 ix86_compare_op0 = operands[0];
637 ix86_compare_op1 = operands[1];
641 (define_expand "cmpqi"
642 [(set (reg:CC FLAGS_REG)
643 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
644 (match_operand:QI 1 "general_operand" "")))]
647 if (MEM_P (operands[0]) && MEM_P (operands[1]))
648 operands[0] = force_reg (QImode, operands[0]);
649 ix86_compare_op0 = operands[0];
650 ix86_compare_op1 = operands[1];
654 (define_insn "cmpdi_ccno_1_rex64"
655 [(set (reg FLAGS_REG)
656 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
657 (match_operand:DI 1 "const0_operand" "n,n")))]
658 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
661 cmp{q}\t{%1, %0|%0, %1}"
662 [(set_attr "type" "test,icmp")
663 (set_attr "length_immediate" "0,1")
664 (set_attr "mode" "DI")])
666 (define_insn "*cmpdi_minus_1_rex64"
667 [(set (reg FLAGS_REG)
668 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
669 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
671 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
672 "cmp{q}\t{%1, %0|%0, %1}"
673 [(set_attr "type" "icmp")
674 (set_attr "mode" "DI")])
676 (define_expand "cmpdi_1_rex64"
677 [(set (reg:CC FLAGS_REG)
678 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
679 (match_operand:DI 1 "general_operand" "")))]
683 (define_insn "cmpdi_1_insn_rex64"
684 [(set (reg FLAGS_REG)
685 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
686 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
687 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
688 "cmp{q}\t{%1, %0|%0, %1}"
689 [(set_attr "type" "icmp")
690 (set_attr "mode" "DI")])
693 (define_insn "*cmpsi_ccno_1"
694 [(set (reg FLAGS_REG)
695 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
696 (match_operand:SI 1 "const0_operand" "n,n")))]
697 "ix86_match_ccmode (insn, CCNOmode)"
700 cmp{l}\t{%1, %0|%0, %1}"
701 [(set_attr "type" "test,icmp")
702 (set_attr "length_immediate" "0,1")
703 (set_attr "mode" "SI")])
705 (define_insn "*cmpsi_minus_1"
706 [(set (reg FLAGS_REG)
707 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
708 (match_operand:SI 1 "general_operand" "ri,mr"))
710 "ix86_match_ccmode (insn, CCGOCmode)"
711 "cmp{l}\t{%1, %0|%0, %1}"
712 [(set_attr "type" "icmp")
713 (set_attr "mode" "SI")])
715 (define_expand "cmpsi_1"
716 [(set (reg:CC FLAGS_REG)
717 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
718 (match_operand:SI 1 "general_operand" "")))]
722 (define_insn "*cmpsi_1_insn"
723 [(set (reg FLAGS_REG)
724 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
725 (match_operand:SI 1 "general_operand" "ri,mr")))]
726 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
727 && ix86_match_ccmode (insn, CCmode)"
728 "cmp{l}\t{%1, %0|%0, %1}"
729 [(set_attr "type" "icmp")
730 (set_attr "mode" "SI")])
732 (define_insn "*cmphi_ccno_1"
733 [(set (reg FLAGS_REG)
734 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
735 (match_operand:HI 1 "const0_operand" "n,n")))]
736 "ix86_match_ccmode (insn, CCNOmode)"
739 cmp{w}\t{%1, %0|%0, %1}"
740 [(set_attr "type" "test,icmp")
741 (set_attr "length_immediate" "0,1")
742 (set_attr "mode" "HI")])
744 (define_insn "*cmphi_minus_1"
745 [(set (reg FLAGS_REG)
746 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
747 (match_operand:HI 1 "general_operand" "ri,mr"))
749 "ix86_match_ccmode (insn, CCGOCmode)"
750 "cmp{w}\t{%1, %0|%0, %1}"
751 [(set_attr "type" "icmp")
752 (set_attr "mode" "HI")])
754 (define_insn "*cmphi_1"
755 [(set (reg FLAGS_REG)
756 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
757 (match_operand:HI 1 "general_operand" "ri,mr")))]
758 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
759 && ix86_match_ccmode (insn, CCmode)"
760 "cmp{w}\t{%1, %0|%0, %1}"
761 [(set_attr "type" "icmp")
762 (set_attr "mode" "HI")])
764 (define_insn "*cmpqi_ccno_1"
765 [(set (reg FLAGS_REG)
766 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
767 (match_operand:QI 1 "const0_operand" "n,n")))]
768 "ix86_match_ccmode (insn, CCNOmode)"
771 cmp{b}\t{$0, %0|%0, 0}"
772 [(set_attr "type" "test,icmp")
773 (set_attr "length_immediate" "0,1")
774 (set_attr "mode" "QI")])
776 (define_insn "*cmpqi_1"
777 [(set (reg FLAGS_REG)
778 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
779 (match_operand:QI 1 "general_operand" "qi,mq")))]
780 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
781 && ix86_match_ccmode (insn, CCmode)"
782 "cmp{b}\t{%1, %0|%0, %1}"
783 [(set_attr "type" "icmp")
784 (set_attr "mode" "QI")])
786 (define_insn "*cmpqi_minus_1"
787 [(set (reg FLAGS_REG)
788 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
789 (match_operand:QI 1 "general_operand" "qi,mq"))
791 "ix86_match_ccmode (insn, CCGOCmode)"
792 "cmp{b}\t{%1, %0|%0, %1}"
793 [(set_attr "type" "icmp")
794 (set_attr "mode" "QI")])
796 (define_insn "*cmpqi_ext_1"
797 [(set (reg FLAGS_REG)
799 (match_operand:QI 0 "general_operand" "Qm")
802 (match_operand 1 "ext_register_operand" "Q")
805 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
806 "cmp{b}\t{%h1, %0|%0, %h1}"
807 [(set_attr "type" "icmp")
808 (set_attr "mode" "QI")])
810 (define_insn "*cmpqi_ext_1_rex64"
811 [(set (reg FLAGS_REG)
813 (match_operand:QI 0 "register_operand" "Q")
816 (match_operand 1 "ext_register_operand" "Q")
819 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
820 "cmp{b}\t{%h1, %0|%0, %h1}"
821 [(set_attr "type" "icmp")
822 (set_attr "mode" "QI")])
824 (define_insn "*cmpqi_ext_2"
825 [(set (reg FLAGS_REG)
829 (match_operand 0 "ext_register_operand" "Q")
832 (match_operand:QI 1 "const0_operand" "n")))]
833 "ix86_match_ccmode (insn, CCNOmode)"
835 [(set_attr "type" "test")
836 (set_attr "length_immediate" "0")
837 (set_attr "mode" "QI")])
839 (define_expand "cmpqi_ext_3"
840 [(set (reg:CC FLAGS_REG)
844 (match_operand 0 "ext_register_operand" "")
847 (match_operand:QI 1 "general_operand" "")))]
851 (define_insn "cmpqi_ext_3_insn"
852 [(set (reg FLAGS_REG)
856 (match_operand 0 "ext_register_operand" "Q")
859 (match_operand:QI 1 "general_operand" "Qmn")))]
860 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
861 "cmp{b}\t{%1, %h0|%h0, %1}"
862 [(set_attr "type" "icmp")
863 (set_attr "mode" "QI")])
865 (define_insn "cmpqi_ext_3_insn_rex64"
866 [(set (reg FLAGS_REG)
870 (match_operand 0 "ext_register_operand" "Q")
873 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
874 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
875 "cmp{b}\t{%1, %h0|%h0, %1}"
876 [(set_attr "type" "icmp")
877 (set_attr "mode" "QI")])
879 (define_insn "*cmpqi_ext_4"
880 [(set (reg FLAGS_REG)
884 (match_operand 0 "ext_register_operand" "Q")
889 (match_operand 1 "ext_register_operand" "Q")
892 "ix86_match_ccmode (insn, CCmode)"
893 "cmp{b}\t{%h1, %h0|%h0, %h1}"
894 [(set_attr "type" "icmp")
895 (set_attr "mode" "QI")])
897 ;; These implement float point compares.
898 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
899 ;; which would allow mix and match FP modes on the compares. Which is what
900 ;; the old patterns did, but with many more of them.
902 (define_expand "cmpxf"
903 [(set (reg:CC FLAGS_REG)
904 (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
905 (match_operand:XF 1 "nonmemory_operand" "")))]
908 ix86_compare_op0 = operands[0];
909 ix86_compare_op1 = operands[1];
913 (define_expand "cmp<mode>"
914 [(set (reg:CC FLAGS_REG)
915 (compare:CC (match_operand:MODEF 0 "cmp_fp_expander_operand" "")
916 (match_operand:MODEF 1 "cmp_fp_expander_operand" "")))]
917 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
919 ix86_compare_op0 = operands[0];
920 ix86_compare_op1 = operands[1];
924 ;; FP compares, step 1:
925 ;; Set the FP condition codes.
927 ;; CCFPmode compare with exceptions
928 ;; CCFPUmode compare with no exceptions
930 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
931 ;; used to manage the reg stack popping would not be preserved.
933 (define_insn "*cmpfp_0"
934 [(set (match_operand:HI 0 "register_operand" "=a")
937 (match_operand 1 "register_operand" "f")
938 (match_operand 2 "const0_operand" "X"))]
940 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
941 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
942 "* return output_fp_compare (insn, operands, 0, 0);"
943 [(set_attr "type" "multi")
944 (set_attr "unit" "i387")
946 (cond [(match_operand:SF 1 "" "")
948 (match_operand:DF 1 "" "")
951 (const_string "XF")))])
953 (define_insn_and_split "*cmpfp_0_cc"
954 [(set (reg:CCFP FLAGS_REG)
956 (match_operand 1 "register_operand" "f")
957 (match_operand 2 "const0_operand" "X")))
958 (clobber (match_operand:HI 0 "register_operand" "=a"))]
959 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
960 && TARGET_SAHF && !TARGET_CMOVE
961 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
963 "&& reload_completed"
966 [(compare:CCFP (match_dup 1)(match_dup 2))]
968 (set (reg:CC FLAGS_REG)
969 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
971 [(set_attr "type" "multi")
972 (set_attr "unit" "i387")
974 (cond [(match_operand:SF 1 "" "")
976 (match_operand:DF 1 "" "")
979 (const_string "XF")))])
981 (define_insn "*cmpfp_xf"
982 [(set (match_operand:HI 0 "register_operand" "=a")
985 (match_operand:XF 1 "register_operand" "f")
986 (match_operand:XF 2 "register_operand" "f"))]
989 "* return output_fp_compare (insn, operands, 0, 0);"
990 [(set_attr "type" "multi")
991 (set_attr "unit" "i387")
992 (set_attr "mode" "XF")])
994 (define_insn_and_split "*cmpfp_xf_cc"
995 [(set (reg:CCFP FLAGS_REG)
997 (match_operand:XF 1 "register_operand" "f")
998 (match_operand:XF 2 "register_operand" "f")))
999 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1001 && TARGET_SAHF && !TARGET_CMOVE"
1003 "&& reload_completed"
1006 [(compare:CCFP (match_dup 1)(match_dup 2))]
1008 (set (reg:CC FLAGS_REG)
1009 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1011 [(set_attr "type" "multi")
1012 (set_attr "unit" "i387")
1013 (set_attr "mode" "XF")])
1015 (define_insn "*cmpfp_<mode>"
1016 [(set (match_operand:HI 0 "register_operand" "=a")
1019 (match_operand:MODEF 1 "register_operand" "f")
1020 (match_operand:MODEF 2 "nonimmediate_operand" "fm"))]
1023 "* return output_fp_compare (insn, operands, 0, 0);"
1024 [(set_attr "type" "multi")
1025 (set_attr "unit" "i387")
1026 (set_attr "mode" "<MODE>")])
1028 (define_insn_and_split "*cmpfp_<mode>_cc"
1029 [(set (reg:CCFP FLAGS_REG)
1031 (match_operand:MODEF 1 "register_operand" "f")
1032 (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
1033 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1035 && TARGET_SAHF && !TARGET_CMOVE"
1037 "&& reload_completed"
1040 [(compare:CCFP (match_dup 1)(match_dup 2))]
1042 (set (reg:CC FLAGS_REG)
1043 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1045 [(set_attr "type" "multi")
1046 (set_attr "unit" "i387")
1047 (set_attr "mode" "<MODE>")])
1049 (define_insn "*cmpfp_u"
1050 [(set (match_operand:HI 0 "register_operand" "=a")
1053 (match_operand 1 "register_operand" "f")
1054 (match_operand 2 "register_operand" "f"))]
1056 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1057 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1058 "* return output_fp_compare (insn, operands, 0, 1);"
1059 [(set_attr "type" "multi")
1060 (set_attr "unit" "i387")
1062 (cond [(match_operand:SF 1 "" "")
1064 (match_operand:DF 1 "" "")
1067 (const_string "XF")))])
1069 (define_insn_and_split "*cmpfp_u_cc"
1070 [(set (reg:CCFPU FLAGS_REG)
1072 (match_operand 1 "register_operand" "f")
1073 (match_operand 2 "register_operand" "f")))
1074 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1075 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1076 && TARGET_SAHF && !TARGET_CMOVE
1077 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1079 "&& reload_completed"
1082 [(compare:CCFPU (match_dup 1)(match_dup 2))]
1084 (set (reg:CC FLAGS_REG)
1085 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1087 [(set_attr "type" "multi")
1088 (set_attr "unit" "i387")
1090 (cond [(match_operand:SF 1 "" "")
1092 (match_operand:DF 1 "" "")
1095 (const_string "XF")))])
1097 (define_insn "*cmpfp_<mode>"
1098 [(set (match_operand:HI 0 "register_operand" "=a")
1101 (match_operand 1 "register_operand" "f")
1102 (match_operator 3 "float_operator"
1103 [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
1105 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1106 && TARGET_USE_<MODE>MODE_FIOP
1107 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1108 "* return output_fp_compare (insn, operands, 0, 0);"
1109 [(set_attr "type" "multi")
1110 (set_attr "unit" "i387")
1111 (set_attr "fp_int_src" "true")
1112 (set_attr "mode" "<MODE>")])
1114 (define_insn_and_split "*cmpfp_<mode>_cc"
1115 [(set (reg:CCFP FLAGS_REG)
1117 (match_operand 1 "register_operand" "f")
1118 (match_operator 3 "float_operator"
1119 [(match_operand:X87MODEI12 2 "memory_operand" "m")])))
1120 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1121 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1122 && TARGET_SAHF && !TARGET_CMOVE
1123 && TARGET_USE_<MODE>MODE_FIOP
1124 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1126 "&& reload_completed"
1131 (match_op_dup 3 [(match_dup 2)]))]
1133 (set (reg:CC FLAGS_REG)
1134 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1136 [(set_attr "type" "multi")
1137 (set_attr "unit" "i387")
1138 (set_attr "fp_int_src" "true")
1139 (set_attr "mode" "<MODE>")])
1141 ;; FP compares, step 2
1142 ;; Move the fpsw to ax.
1144 (define_insn "x86_fnstsw_1"
1145 [(set (match_operand:HI 0 "register_operand" "=a")
1146 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
1149 [(set_attr "length" "2")
1150 (set_attr "mode" "SI")
1151 (set_attr "unit" "i387")])
1153 ;; FP compares, step 3
1154 ;; Get ax into flags, general case.
1156 (define_insn "x86_sahf_1"
1157 [(set (reg:CC FLAGS_REG)
1158 (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
1162 #ifdef HAVE_AS_IX86_SAHF
1165 return ".byte\t0x9e";
1168 [(set_attr "length" "1")
1169 (set_attr "athlon_decode" "vector")
1170 (set_attr "amdfam10_decode" "direct")
1171 (set_attr "mode" "SI")])
1173 ;; Pentium Pro can do steps 1 through 3 in one go.
1174 ;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
1175 (define_insn "*cmpfp_i_mixed"
1176 [(set (reg:CCFP FLAGS_REG)
1177 (compare:CCFP (match_operand 0 "register_operand" "f,x")
1178 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1179 "TARGET_MIX_SSE_I387
1180 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1181 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1182 "* return output_fp_compare (insn, operands, 1, 0);"
1183 [(set_attr "type" "fcmp,ssecomi")
1185 (if_then_else (match_operand:SF 1 "" "")
1187 (const_string "DF")))
1188 (set_attr "athlon_decode" "vector")
1189 (set_attr "amdfam10_decode" "direct")])
1191 (define_insn "*cmpfp_i_sse"
1192 [(set (reg:CCFP FLAGS_REG)
1193 (compare:CCFP (match_operand 0 "register_operand" "x")
1194 (match_operand 1 "nonimmediate_operand" "xm")))]
1196 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1197 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1198 "* return output_fp_compare (insn, operands, 1, 0);"
1199 [(set_attr "type" "ssecomi")
1201 (if_then_else (match_operand:SF 1 "" "")
1203 (const_string "DF")))
1204 (set_attr "athlon_decode" "vector")
1205 (set_attr "amdfam10_decode" "direct")])
1207 (define_insn "*cmpfp_i_i387"
1208 [(set (reg:CCFP FLAGS_REG)
1209 (compare:CCFP (match_operand 0 "register_operand" "f")
1210 (match_operand 1 "register_operand" "f")))]
1211 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1213 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1214 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1215 "* return output_fp_compare (insn, operands, 1, 0);"
1216 [(set_attr "type" "fcmp")
1218 (cond [(match_operand:SF 1 "" "")
1220 (match_operand:DF 1 "" "")
1223 (const_string "XF")))
1224 (set_attr "athlon_decode" "vector")
1225 (set_attr "amdfam10_decode" "direct")])
1227 (define_insn "*cmpfp_iu_mixed"
1228 [(set (reg:CCFPU FLAGS_REG)
1229 (compare:CCFPU (match_operand 0 "register_operand" "f,x")
1230 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1231 "TARGET_MIX_SSE_I387
1232 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1233 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1234 "* return output_fp_compare (insn, operands, 1, 1);"
1235 [(set_attr "type" "fcmp,ssecomi")
1237 (if_then_else (match_operand:SF 1 "" "")
1239 (const_string "DF")))
1240 (set_attr "athlon_decode" "vector")
1241 (set_attr "amdfam10_decode" "direct")])
1243 (define_insn "*cmpfp_iu_sse"
1244 [(set (reg:CCFPU FLAGS_REG)
1245 (compare:CCFPU (match_operand 0 "register_operand" "x")
1246 (match_operand 1 "nonimmediate_operand" "xm")))]
1248 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1249 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1250 "* return output_fp_compare (insn, operands, 1, 1);"
1251 [(set_attr "type" "ssecomi")
1253 (if_then_else (match_operand:SF 1 "" "")
1255 (const_string "DF")))
1256 (set_attr "athlon_decode" "vector")
1257 (set_attr "amdfam10_decode" "direct")])
1259 (define_insn "*cmpfp_iu_387"
1260 [(set (reg:CCFPU FLAGS_REG)
1261 (compare:CCFPU (match_operand 0 "register_operand" "f")
1262 (match_operand 1 "register_operand" "f")))]
1263 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1265 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1266 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1267 "* return output_fp_compare (insn, operands, 1, 1);"
1268 [(set_attr "type" "fcmp")
1270 (cond [(match_operand:SF 1 "" "")
1272 (match_operand:DF 1 "" "")
1275 (const_string "XF")))
1276 (set_attr "athlon_decode" "vector")
1277 (set_attr "amdfam10_decode" "direct")])
1279 ;; Move instructions.
1281 ;; General case of fullword move.
1283 (define_expand "movsi"
1284 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1285 (match_operand:SI 1 "general_operand" ""))]
1287 "ix86_expand_move (SImode, operands); DONE;")
1289 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1292 ;; %%% We don't use a post-inc memory reference because x86 is not a
1293 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1294 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1295 ;; targets without our curiosities, and it is just as easy to represent
1296 ;; this differently.
1298 (define_insn "*pushsi2"
1299 [(set (match_operand:SI 0 "push_operand" "=<")
1300 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1303 [(set_attr "type" "push")
1304 (set_attr "mode" "SI")])
1306 ;; For 64BIT abi we always round up to 8 bytes.
1307 (define_insn "*pushsi2_rex64"
1308 [(set (match_operand:SI 0 "push_operand" "=X")
1309 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1312 [(set_attr "type" "push")
1313 (set_attr "mode" "SI")])
1315 (define_insn "*pushsi2_prologue"
1316 [(set (match_operand:SI 0 "push_operand" "=<")
1317 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1318 (clobber (mem:BLK (scratch)))]
1321 [(set_attr "type" "push")
1322 (set_attr "mode" "SI")])
1324 (define_insn "*popsi1_epilogue"
1325 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1326 (mem:SI (reg:SI SP_REG)))
1327 (set (reg:SI SP_REG)
1328 (plus:SI (reg:SI SP_REG) (const_int 4)))
1329 (clobber (mem:BLK (scratch)))]
1332 [(set_attr "type" "pop")
1333 (set_attr "mode" "SI")])
1335 (define_insn "popsi1"
1336 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1337 (mem:SI (reg:SI SP_REG)))
1338 (set (reg:SI SP_REG)
1339 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1342 [(set_attr "type" "pop")
1343 (set_attr "mode" "SI")])
1345 (define_insn "*movsi_xor"
1346 [(set (match_operand:SI 0 "register_operand" "=r")
1347 (match_operand:SI 1 "const0_operand" "i"))
1348 (clobber (reg:CC FLAGS_REG))]
1349 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1351 [(set_attr "type" "alu1")
1352 (set_attr "mode" "SI")
1353 (set_attr "length_immediate" "0")])
1355 (define_insn "*movsi_or"
1356 [(set (match_operand:SI 0 "register_operand" "=r")
1357 (match_operand:SI 1 "immediate_operand" "i"))
1358 (clobber (reg:CC FLAGS_REG))]
1360 && operands[1] == constm1_rtx
1361 && (TARGET_MOVE_M1_VIA_OR || optimize_size)"
1363 operands[1] = constm1_rtx;
1364 return "or{l}\t{%1, %0|%0, %1}";
1366 [(set_attr "type" "alu1")
1367 (set_attr "mode" "SI")
1368 (set_attr "length_immediate" "1")])
1370 (define_insn "*movsi_1"
1371 [(set (match_operand:SI 0 "nonimmediate_operand"
1372 "=r ,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
1373 (match_operand:SI 1 "general_operand"
1374 "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r ,m "))]
1375 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
1377 switch (get_attr_type (insn))
1380 if (get_attr_mode (insn) == MODE_TI)
1381 return "pxor\t%0, %0";
1382 return "xorps\t%0, %0";
1385 switch (get_attr_mode (insn))
1388 return "movdqa\t{%1, %0|%0, %1}";
1390 return "movaps\t{%1, %0|%0, %1}";
1392 return "movd\t{%1, %0|%0, %1}";
1394 return "movss\t{%1, %0|%0, %1}";
1400 return "pxor\t%0, %0";
1403 if (get_attr_mode (insn) == MODE_DI)
1404 return "movq\t{%1, %0|%0, %1}";
1405 return "movd\t{%1, %0|%0, %1}";
1408 return "lea{l}\t{%1, %0|%0, %1}";
1411 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
1412 return "mov{l}\t{%1, %0|%0, %1}";
1416 (cond [(eq_attr "alternative" "2")
1417 (const_string "mmxadd")
1418 (eq_attr "alternative" "3,4,5")
1419 (const_string "mmxmov")
1420 (eq_attr "alternative" "6")
1421 (const_string "sselog1")
1422 (eq_attr "alternative" "7,8,9,10,11")
1423 (const_string "ssemov")
1424 (match_operand:DI 1 "pic_32bit_operand" "")
1425 (const_string "lea")
1427 (const_string "imov")))
1429 (cond [(eq_attr "alternative" "2,3")
1431 (eq_attr "alternative" "6,7")
1433 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
1434 (const_string "V4SF")
1435 (const_string "TI"))
1436 (and (eq_attr "alternative" "8,9,10,11")
1437 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
1440 (const_string "SI")))])
1442 ;; Stores and loads of ax to arbitrary constant address.
1443 ;; We fake an second form of instruction to force reload to load address
1444 ;; into register when rax is not available
1445 (define_insn "*movabssi_1_rex64"
1446 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1447 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1448 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1450 movabs{l}\t{%1, %P0|%P0, %1}
1451 mov{l}\t{%1, %a0|%a0, %1}"
1452 [(set_attr "type" "imov")
1453 (set_attr "modrm" "0,*")
1454 (set_attr "length_address" "8,0")
1455 (set_attr "length_immediate" "0,*")
1456 (set_attr "memory" "store")
1457 (set_attr "mode" "SI")])
1459 (define_insn "*movabssi_2_rex64"
1460 [(set (match_operand:SI 0 "register_operand" "=a,r")
1461 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1462 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1464 movabs{l}\t{%P1, %0|%0, %P1}
1465 mov{l}\t{%a1, %0|%0, %a1}"
1466 [(set_attr "type" "imov")
1467 (set_attr "modrm" "0,*")
1468 (set_attr "length_address" "8,0")
1469 (set_attr "length_immediate" "0")
1470 (set_attr "memory" "load")
1471 (set_attr "mode" "SI")])
1473 (define_insn "*swapsi"
1474 [(set (match_operand:SI 0 "register_operand" "+r")
1475 (match_operand:SI 1 "register_operand" "+r"))
1480 [(set_attr "type" "imov")
1481 (set_attr "mode" "SI")
1482 (set_attr "pent_pair" "np")
1483 (set_attr "athlon_decode" "vector")
1484 (set_attr "amdfam10_decode" "double")])
1486 (define_expand "movhi"
1487 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1488 (match_operand:HI 1 "general_operand" ""))]
1490 "ix86_expand_move (HImode, operands); DONE;")
1492 (define_insn "*pushhi2"
1493 [(set (match_operand:HI 0 "push_operand" "=X")
1494 (match_operand:HI 1 "nonmemory_no_elim_operand" "rn"))]
1497 [(set_attr "type" "push")
1498 (set_attr "mode" "SI")])
1500 ;; For 64BIT abi we always round up to 8 bytes.
1501 (define_insn "*pushhi2_rex64"
1502 [(set (match_operand:HI 0 "push_operand" "=X")
1503 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1506 [(set_attr "type" "push")
1507 (set_attr "mode" "DI")])
1509 (define_insn "*movhi_1"
1510 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1511 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1512 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
1514 switch (get_attr_type (insn))
1517 /* movzwl is faster than movw on p2 due to partial word stalls,
1518 though not as fast as an aligned movl. */
1519 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1521 if (get_attr_mode (insn) == MODE_SI)
1522 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1524 return "mov{w}\t{%1, %0|%0, %1}";
1528 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1529 (const_string "imov")
1530 (and (eq_attr "alternative" "0")
1531 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1533 (eq (symbol_ref "TARGET_HIMODE_MATH")
1535 (const_string "imov")
1536 (and (eq_attr "alternative" "1,2")
1537 (match_operand:HI 1 "aligned_operand" ""))
1538 (const_string "imov")
1539 (and (ne (symbol_ref "TARGET_MOVX")
1541 (eq_attr "alternative" "0,2"))
1542 (const_string "imovx")
1544 (const_string "imov")))
1546 (cond [(eq_attr "type" "imovx")
1548 (and (eq_attr "alternative" "1,2")
1549 (match_operand:HI 1 "aligned_operand" ""))
1551 (and (eq_attr "alternative" "0")
1552 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1554 (eq (symbol_ref "TARGET_HIMODE_MATH")
1558 (const_string "HI")))])
1560 ;; Stores and loads of ax to arbitrary constant address.
1561 ;; We fake an second form of instruction to force reload to load address
1562 ;; into register when rax is not available
1563 (define_insn "*movabshi_1_rex64"
1564 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1565 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1566 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1568 movabs{w}\t{%1, %P0|%P0, %1}
1569 mov{w}\t{%1, %a0|%a0, %1}"
1570 [(set_attr "type" "imov")
1571 (set_attr "modrm" "0,*")
1572 (set_attr "length_address" "8,0")
1573 (set_attr "length_immediate" "0,*")
1574 (set_attr "memory" "store")
1575 (set_attr "mode" "HI")])
1577 (define_insn "*movabshi_2_rex64"
1578 [(set (match_operand:HI 0 "register_operand" "=a,r")
1579 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1580 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1582 movabs{w}\t{%P1, %0|%0, %P1}
1583 mov{w}\t{%a1, %0|%0, %a1}"
1584 [(set_attr "type" "imov")
1585 (set_attr "modrm" "0,*")
1586 (set_attr "length_address" "8,0")
1587 (set_attr "length_immediate" "0")
1588 (set_attr "memory" "load")
1589 (set_attr "mode" "HI")])
1591 (define_insn "*swaphi_1"
1592 [(set (match_operand:HI 0 "register_operand" "+r")
1593 (match_operand:HI 1 "register_operand" "+r"))
1596 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1598 [(set_attr "type" "imov")
1599 (set_attr "mode" "SI")
1600 (set_attr "pent_pair" "np")
1601 (set_attr "athlon_decode" "vector")
1602 (set_attr "amdfam10_decode" "double")])
1604 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
1605 (define_insn "*swaphi_2"
1606 [(set (match_operand:HI 0 "register_operand" "+r")
1607 (match_operand:HI 1 "register_operand" "+r"))
1610 "TARGET_PARTIAL_REG_STALL"
1612 [(set_attr "type" "imov")
1613 (set_attr "mode" "HI")
1614 (set_attr "pent_pair" "np")
1615 (set_attr "athlon_decode" "vector")])
1617 (define_expand "movstricthi"
1618 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1619 (match_operand:HI 1 "general_operand" ""))]
1620 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1622 /* Don't generate memory->memory moves, go through a register */
1623 if (MEM_P (operands[0]) && MEM_P (operands[1]))
1624 operands[1] = force_reg (HImode, operands[1]);
1627 (define_insn "*movstricthi_1"
1628 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1629 (match_operand:HI 1 "general_operand" "rn,m"))]
1630 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1631 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1632 "mov{w}\t{%1, %0|%0, %1}"
1633 [(set_attr "type" "imov")
1634 (set_attr "mode" "HI")])
1636 (define_insn "*movstricthi_xor"
1637 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1638 (match_operand:HI 1 "const0_operand" "i"))
1639 (clobber (reg:CC FLAGS_REG))]
1641 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1643 [(set_attr "type" "alu1")
1644 (set_attr "mode" "HI")
1645 (set_attr "length_immediate" "0")])
1647 (define_expand "movqi"
1648 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1649 (match_operand:QI 1 "general_operand" ""))]
1651 "ix86_expand_move (QImode, operands); DONE;")
1653 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1654 ;; "push a byte". But actually we use pushl, which has the effect
1655 ;; of rounding the amount pushed up to a word.
1657 (define_insn "*pushqi2"
1658 [(set (match_operand:QI 0 "push_operand" "=X")
1659 (match_operand:QI 1 "nonmemory_no_elim_operand" "rn"))]
1662 [(set_attr "type" "push")
1663 (set_attr "mode" "SI")])
1665 ;; For 64BIT abi we always round up to 8 bytes.
1666 (define_insn "*pushqi2_rex64"
1667 [(set (match_operand:QI 0 "push_operand" "=X")
1668 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1671 [(set_attr "type" "push")
1672 (set_attr "mode" "DI")])
1674 ;; Situation is quite tricky about when to choose full sized (SImode) move
1675 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1676 ;; partial register dependency machines (such as AMD Athlon), where QImode
1677 ;; moves issue extra dependency and for partial register stalls machines
1678 ;; that don't use QImode patterns (and QImode move cause stall on the next
1681 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1682 ;; register stall machines with, where we use QImode instructions, since
1683 ;; partial register stall can be caused there. Then we use movzx.
1684 (define_insn "*movqi_1"
1685 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1686 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1687 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
1689 switch (get_attr_type (insn))
1692 gcc_assert (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]));
1693 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1695 if (get_attr_mode (insn) == MODE_SI)
1696 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1698 return "mov{b}\t{%1, %0|%0, %1}";
1702 (cond [(and (eq_attr "alternative" "5")
1703 (not (match_operand:QI 1 "aligned_operand" "")))
1704 (const_string "imovx")
1705 (ne (symbol_ref "optimize_size") (const_int 0))
1706 (const_string "imov")
1707 (and (eq_attr "alternative" "3")
1708 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1710 (eq (symbol_ref "TARGET_QIMODE_MATH")
1712 (const_string "imov")
1713 (eq_attr "alternative" "3,5")
1714 (const_string "imovx")
1715 (and (ne (symbol_ref "TARGET_MOVX")
1717 (eq_attr "alternative" "2"))
1718 (const_string "imovx")
1720 (const_string "imov")))
1722 (cond [(eq_attr "alternative" "3,4,5")
1724 (eq_attr "alternative" "6")
1726 (eq_attr "type" "imovx")
1728 (and (eq_attr "type" "imov")
1729 (and (eq_attr "alternative" "0,1")
1730 (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1732 (and (eq (symbol_ref "optimize_size")
1734 (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1737 ;; Avoid partial register stalls when not using QImode arithmetic
1738 (and (eq_attr "type" "imov")
1739 (and (eq_attr "alternative" "0,1")
1740 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1742 (eq (symbol_ref "TARGET_QIMODE_MATH")
1746 (const_string "QI")))])
1748 (define_expand "reload_outqi"
1749 [(parallel [(match_operand:QI 0 "" "=m")
1750 (match_operand:QI 1 "register_operand" "r")
1751 (match_operand:QI 2 "register_operand" "=&q")])]
1755 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1757 gcc_assert (!reg_overlap_mentioned_p (op2, op0));
1758 if (! q_regs_operand (op1, QImode))
1760 emit_insn (gen_movqi (op2, op1));
1763 emit_insn (gen_movqi (op0, op1));
1767 (define_insn "*swapqi_1"
1768 [(set (match_operand:QI 0 "register_operand" "+r")
1769 (match_operand:QI 1 "register_operand" "+r"))
1772 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1774 [(set_attr "type" "imov")
1775 (set_attr "mode" "SI")
1776 (set_attr "pent_pair" "np")
1777 (set_attr "athlon_decode" "vector")
1778 (set_attr "amdfam10_decode" "vector")])
1780 ;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
1781 (define_insn "*swapqi_2"
1782 [(set (match_operand:QI 0 "register_operand" "+q")
1783 (match_operand:QI 1 "register_operand" "+q"))
1786 "TARGET_PARTIAL_REG_STALL"
1788 [(set_attr "type" "imov")
1789 (set_attr "mode" "QI")
1790 (set_attr "pent_pair" "np")
1791 (set_attr "athlon_decode" "vector")])
1793 (define_expand "movstrictqi"
1794 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1795 (match_operand:QI 1 "general_operand" ""))]
1796 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1798 /* Don't generate memory->memory moves, go through a register. */
1799 if (MEM_P (operands[0]) && MEM_P (operands[1]))
1800 operands[1] = force_reg (QImode, operands[1]);
1803 (define_insn "*movstrictqi_1"
1804 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1805 (match_operand:QI 1 "general_operand" "*qn,m"))]
1806 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1807 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1808 "mov{b}\t{%1, %0|%0, %1}"
1809 [(set_attr "type" "imov")
1810 (set_attr "mode" "QI")])
1812 (define_insn "*movstrictqi_xor"
1813 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1814 (match_operand:QI 1 "const0_operand" "i"))
1815 (clobber (reg:CC FLAGS_REG))]
1816 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1818 [(set_attr "type" "alu1")
1819 (set_attr "mode" "QI")
1820 (set_attr "length_immediate" "0")])
1822 (define_insn "*movsi_extv_1"
1823 [(set (match_operand:SI 0 "register_operand" "=R")
1824 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1828 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1829 [(set_attr "type" "imovx")
1830 (set_attr "mode" "SI")])
1832 (define_insn "*movhi_extv_1"
1833 [(set (match_operand:HI 0 "register_operand" "=R")
1834 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1838 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1839 [(set_attr "type" "imovx")
1840 (set_attr "mode" "SI")])
1842 (define_insn "*movqi_extv_1"
1843 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1844 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1849 switch (get_attr_type (insn))
1852 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1854 return "mov{b}\t{%h1, %0|%0, %h1}";
1858 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1859 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1860 (ne (symbol_ref "TARGET_MOVX")
1862 (const_string "imovx")
1863 (const_string "imov")))
1865 (if_then_else (eq_attr "type" "imovx")
1867 (const_string "QI")))])
1869 (define_insn "*movqi_extv_1_rex64"
1870 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1871 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1876 switch (get_attr_type (insn))
1879 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1881 return "mov{b}\t{%h1, %0|%0, %h1}";
1885 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1886 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1887 (ne (symbol_ref "TARGET_MOVX")
1889 (const_string "imovx")
1890 (const_string "imov")))
1892 (if_then_else (eq_attr "type" "imovx")
1894 (const_string "QI")))])
1896 ;; Stores and loads of ax to arbitrary constant address.
1897 ;; We fake an second form of instruction to force reload to load address
1898 ;; into register when rax is not available
1899 (define_insn "*movabsqi_1_rex64"
1900 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1901 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1902 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1904 movabs{b}\t{%1, %P0|%P0, %1}
1905 mov{b}\t{%1, %a0|%a0, %1}"
1906 [(set_attr "type" "imov")
1907 (set_attr "modrm" "0,*")
1908 (set_attr "length_address" "8,0")
1909 (set_attr "length_immediate" "0,*")
1910 (set_attr "memory" "store")
1911 (set_attr "mode" "QI")])
1913 (define_insn "*movabsqi_2_rex64"
1914 [(set (match_operand:QI 0 "register_operand" "=a,r")
1915 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1916 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1918 movabs{b}\t{%P1, %0|%0, %P1}
1919 mov{b}\t{%a1, %0|%0, %a1}"
1920 [(set_attr "type" "imov")
1921 (set_attr "modrm" "0,*")
1922 (set_attr "length_address" "8,0")
1923 (set_attr "length_immediate" "0")
1924 (set_attr "memory" "load")
1925 (set_attr "mode" "QI")])
1927 (define_insn "*movdi_extzv_1"
1928 [(set (match_operand:DI 0 "register_operand" "=R")
1929 (zero_extract:DI (match_operand 1 "ext_register_operand" "Q")
1933 "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
1934 [(set_attr "type" "imovx")
1935 (set_attr "mode" "DI")])
1937 (define_insn "*movsi_extzv_1"
1938 [(set (match_operand:SI 0 "register_operand" "=R")
1939 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1943 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1944 [(set_attr "type" "imovx")
1945 (set_attr "mode" "SI")])
1947 (define_insn "*movqi_extzv_2"
1948 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1949 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1954 switch (get_attr_type (insn))
1957 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1959 return "mov{b}\t{%h1, %0|%0, %h1}";
1963 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1964 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1965 (ne (symbol_ref "TARGET_MOVX")
1967 (const_string "imovx")
1968 (const_string "imov")))
1970 (if_then_else (eq_attr "type" "imovx")
1972 (const_string "QI")))])
1974 (define_insn "*movqi_extzv_2_rex64"
1975 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1976 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1981 switch (get_attr_type (insn))
1984 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1986 return "mov{b}\t{%h1, %0|%0, %h1}";
1990 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1991 (ne (symbol_ref "TARGET_MOVX")
1993 (const_string "imovx")
1994 (const_string "imov")))
1996 (if_then_else (eq_attr "type" "imovx")
1998 (const_string "QI")))])
2000 (define_insn "movsi_insv_1"
2001 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2004 (match_operand:SI 1 "general_operand" "Qmn"))]
2006 "mov{b}\t{%b1, %h0|%h0, %b1}"
2007 [(set_attr "type" "imov")
2008 (set_attr "mode" "QI")])
2010 (define_insn "*movsi_insv_1_rex64"
2011 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2014 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
2016 "mov{b}\t{%b1, %h0|%h0, %b1}"
2017 [(set_attr "type" "imov")
2018 (set_attr "mode" "QI")])
2020 (define_insn "movdi_insv_1_rex64"
2021 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
2024 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
2026 "mov{b}\t{%b1, %h0|%h0, %b1}"
2027 [(set_attr "type" "imov")
2028 (set_attr "mode" "QI")])
2030 (define_insn "*movqi_insv_2"
2031 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2034 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2037 "mov{b}\t{%h1, %h0|%h0, %h1}"
2038 [(set_attr "type" "imov")
2039 (set_attr "mode" "QI")])
2041 (define_expand "movdi"
2042 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2043 (match_operand:DI 1 "general_operand" ""))]
2045 "ix86_expand_move (DImode, operands); DONE;")
2047 (define_insn "*pushdi"
2048 [(set (match_operand:DI 0 "push_operand" "=<")
2049 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2053 (define_insn "*pushdi2_rex64"
2054 [(set (match_operand:DI 0 "push_operand" "=<,!<")
2055 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
2060 [(set_attr "type" "push,multi")
2061 (set_attr "mode" "DI")])
2063 ;; Convert impossible pushes of immediate to existing instructions.
2064 ;; First try to get scratch register and go through it. In case this
2065 ;; fails, push sign extended lower part first and then overwrite
2066 ;; upper part by 32bit move.
2068 [(match_scratch:DI 2 "r")
2069 (set (match_operand:DI 0 "push_operand" "")
2070 (match_operand:DI 1 "immediate_operand" ""))]
2071 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2072 && !x86_64_immediate_operand (operands[1], DImode)"
2073 [(set (match_dup 2) (match_dup 1))
2074 (set (match_dup 0) (match_dup 2))]
2077 ;; We need to define this as both peepholer and splitter for case
2078 ;; peephole2 pass is not run.
2079 ;; "&& 1" is needed to keep it from matching the previous pattern.
2081 [(set (match_operand:DI 0 "push_operand" "")
2082 (match_operand:DI 1 "immediate_operand" ""))]
2083 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2084 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2085 [(set (match_dup 0) (match_dup 1))
2086 (set (match_dup 2) (match_dup 3))]
2087 "split_di (operands + 1, 1, operands + 2, operands + 3);
2088 operands[1] = gen_lowpart (DImode, operands[2]);
2089 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2094 [(set (match_operand:DI 0 "push_operand" "")
2095 (match_operand:DI 1 "immediate_operand" ""))]
2096 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
2097 ? epilogue_completed : reload_completed)
2098 && !symbolic_operand (operands[1], DImode)
2099 && !x86_64_immediate_operand (operands[1], DImode)"
2100 [(set (match_dup 0) (match_dup 1))
2101 (set (match_dup 2) (match_dup 3))]
2102 "split_di (operands + 1, 1, operands + 2, operands + 3);
2103 operands[1] = gen_lowpart (DImode, operands[2]);
2104 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
2108 (define_insn "*pushdi2_prologue_rex64"
2109 [(set (match_operand:DI 0 "push_operand" "=<")
2110 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
2111 (clobber (mem:BLK (scratch)))]
2114 [(set_attr "type" "push")
2115 (set_attr "mode" "DI")])
2117 (define_insn "*popdi1_epilogue_rex64"
2118 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2119 (mem:DI (reg:DI SP_REG)))
2120 (set (reg:DI SP_REG)
2121 (plus:DI (reg:DI SP_REG) (const_int 8)))
2122 (clobber (mem:BLK (scratch)))]
2125 [(set_attr "type" "pop")
2126 (set_attr "mode" "DI")])
2128 (define_insn "popdi1"
2129 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
2130 (mem:DI (reg:DI SP_REG)))
2131 (set (reg:DI SP_REG)
2132 (plus:DI (reg:DI SP_REG) (const_int 8)))]
2135 [(set_attr "type" "pop")
2136 (set_attr "mode" "DI")])
2138 (define_insn "*movdi_xor_rex64"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (match_operand:DI 1 "const0_operand" "i"))
2141 (clobber (reg:CC FLAGS_REG))]
2142 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
2143 && reload_completed"
2145 [(set_attr "type" "alu1")
2146 (set_attr "mode" "SI")
2147 (set_attr "length_immediate" "0")])
2149 (define_insn "*movdi_or_rex64"
2150 [(set (match_operand:DI 0 "register_operand" "=r")
2151 (match_operand:DI 1 "const_int_operand" "i"))
2152 (clobber (reg:CC FLAGS_REG))]
2153 "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
2155 && operands[1] == constm1_rtx"
2157 operands[1] = constm1_rtx;
2158 return "or{q}\t{%1, %0|%0, %1}";
2160 [(set_attr "type" "alu1")
2161 (set_attr "mode" "DI")
2162 (set_attr "length_immediate" "1")])
2164 (define_insn "*movdi_2"
2165 [(set (match_operand:DI 0 "nonimmediate_operand"
2166 "=r ,o ,*y,m*y,*y,*Yt,m ,*Yt,*Yt,*x,m ,*x,*x")
2167 (match_operand:DI 1 "general_operand"
2168 "riFo,riF,C ,*y ,m ,C ,*Yt,*Yt,m ,C ,*x,*x,m "))]
2169 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2174 movq\t{%1, %0|%0, %1}
2175 movq\t{%1, %0|%0, %1}
2177 movq\t{%1, %0|%0, %1}
2178 movdqa\t{%1, %0|%0, %1}
2179 movq\t{%1, %0|%0, %1}
2181 movlps\t{%1, %0|%0, %1}
2182 movaps\t{%1, %0|%0, %1}
2183 movlps\t{%1, %0|%0, %1}"
2184 [(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
2185 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
2188 [(set (match_operand:DI 0 "push_operand" "")
2189 (match_operand:DI 1 "general_operand" ""))]
2190 "!TARGET_64BIT && reload_completed
2191 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2193 "ix86_split_long_move (operands); DONE;")
2195 ;; %%% This multiword shite has got to go.
2197 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2198 (match_operand:DI 1 "general_operand" ""))]
2199 "!TARGET_64BIT && reload_completed
2200 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
2201 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
2203 "ix86_split_long_move (operands); DONE;")
2205 (define_insn "*movdi_1_rex64"
2206 [(set (match_operand:DI 0 "nonimmediate_operand"
2207 "=r,r ,r,m ,!m,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym")
2208 (match_operand:DI 1 "general_operand"
2209 "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r ,m ,C ,*x,*Yi,*x,r ,m ,*Ym,*x"))]
2210 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2212 switch (get_attr_type (insn))
2215 if (SSE_REG_P (operands[0]))
2216 return "movq2dq\t{%1, %0|%0, %1}";
2218 return "movdq2q\t{%1, %0|%0, %1}";
2221 if (get_attr_mode (insn) == MODE_TI)
2222 return "movdqa\t{%1, %0|%0, %1}";
2226 /* Moves from and into integer register is done using movd
2227 opcode with REX prefix. */
2228 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
2229 return "movd\t{%1, %0|%0, %1}";
2230 return "movq\t{%1, %0|%0, %1}";
2234 return "pxor\t%0, %0";
2240 return "lea{q}\t{%a1, %0|%0, %a1}";
2243 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
2244 if (get_attr_mode (insn) == MODE_SI)
2245 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2246 else if (which_alternative == 2)
2247 return "movabs{q}\t{%1, %0|%0, %1}";
2249 return "mov{q}\t{%1, %0|%0, %1}";
2253 (cond [(eq_attr "alternative" "5")
2254 (const_string "mmxadd")
2255 (eq_attr "alternative" "6,7,8,9,10")
2256 (const_string "mmxmov")
2257 (eq_attr "alternative" "11")
2258 (const_string "sselog1")
2259 (eq_attr "alternative" "12,13,14,15,16")
2260 (const_string "ssemov")
2261 (eq_attr "alternative" "17,18")
2262 (const_string "ssecvt")
2263 (eq_attr "alternative" "4")
2264 (const_string "multi")
2265 (match_operand:DI 1 "pic_32bit_operand" "")
2266 (const_string "lea")
2268 (const_string "imov")))
2269 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
2270 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
2271 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,DI,TI,TI,DI,DI,DI,DI,DI,DI")])
2273 ;; Stores and loads of ax to arbitrary constant address.
2274 ;; We fake an second form of instruction to force reload to load address
2275 ;; into register when rax is not available
2276 (define_insn "*movabsdi_1_rex64"
2277 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2278 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2279 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2281 movabs{q}\t{%1, %P0|%P0, %1}
2282 mov{q}\t{%1, %a0|%a0, %1}"
2283 [(set_attr "type" "imov")
2284 (set_attr "modrm" "0,*")
2285 (set_attr "length_address" "8,0")
2286 (set_attr "length_immediate" "0,*")
2287 (set_attr "memory" "store")
2288 (set_attr "mode" "DI")])
2290 (define_insn "*movabsdi_2_rex64"
2291 [(set (match_operand:DI 0 "register_operand" "=a,r")
2292 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2293 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2295 movabs{q}\t{%P1, %0|%0, %P1}
2296 mov{q}\t{%a1, %0|%0, %a1}"
2297 [(set_attr "type" "imov")
2298 (set_attr "modrm" "0,*")
2299 (set_attr "length_address" "8,0")
2300 (set_attr "length_immediate" "0")
2301 (set_attr "memory" "load")
2302 (set_attr "mode" "DI")])
2304 ;; Convert impossible stores of immediate to existing instructions.
2305 ;; First try to get scratch register and go through it. In case this
2306 ;; fails, move by 32bit parts.
2308 [(match_scratch:DI 2 "r")
2309 (set (match_operand:DI 0 "memory_operand" "")
2310 (match_operand:DI 1 "immediate_operand" ""))]
2311 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2312 && !x86_64_immediate_operand (operands[1], DImode)"
2313 [(set (match_dup 2) (match_dup 1))
2314 (set (match_dup 0) (match_dup 2))]
2317 ;; We need to define this as both peepholer and splitter for case
2318 ;; peephole2 pass is not run.
2319 ;; "&& 1" is needed to keep it from matching the previous pattern.
2321 [(set (match_operand:DI 0 "memory_operand" "")
2322 (match_operand:DI 1 "immediate_operand" ""))]
2323 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2324 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2325 [(set (match_dup 2) (match_dup 3))
2326 (set (match_dup 4) (match_dup 5))]
2327 "split_di (operands, 2, operands + 2, operands + 4);")
2330 [(set (match_operand:DI 0 "memory_operand" "")
2331 (match_operand:DI 1 "immediate_operand" ""))]
2332 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
2333 ? epilogue_completed : reload_completed)
2334 && !symbolic_operand (operands[1], DImode)
2335 && !x86_64_immediate_operand (operands[1], DImode)"
2336 [(set (match_dup 2) (match_dup 3))
2337 (set (match_dup 4) (match_dup 5))]
2338 "split_di (operands, 2, operands + 2, operands + 4);")
2340 (define_insn "*swapdi_rex64"
2341 [(set (match_operand:DI 0 "register_operand" "+r")
2342 (match_operand:DI 1 "register_operand" "+r"))
2347 [(set_attr "type" "imov")
2348 (set_attr "mode" "DI")
2349 (set_attr "pent_pair" "np")
2350 (set_attr "athlon_decode" "vector")
2351 (set_attr "amdfam10_decode" "double")])
2353 (define_expand "movti"
2354 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2355 (match_operand:TI 1 "nonimmediate_operand" ""))]
2356 "TARGET_SSE || TARGET_64BIT"
2359 ix86_expand_move (TImode, operands);
2360 else if (push_operand (operands[0], TImode))
2361 ix86_expand_push (TImode, operands[1]);
2363 ix86_expand_vector_move (TImode, operands);
2367 (define_insn "*movti_internal"
2368 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
2369 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
2370 "TARGET_SSE && !TARGET_64BIT
2371 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2373 switch (which_alternative)
2376 if (get_attr_mode (insn) == MODE_V4SF)
2377 return "xorps\t%0, %0";
2379 return "pxor\t%0, %0";
2382 if (get_attr_mode (insn) == MODE_V4SF)
2383 return "movaps\t{%1, %0|%0, %1}";
2385 return "movdqa\t{%1, %0|%0, %1}";
2390 [(set_attr "type" "sselog1,ssemov,ssemov")
2392 (cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2393 (ne (symbol_ref "optimize_size") (const_int 0)))
2394 (const_string "V4SF")
2395 (and (eq_attr "alternative" "2")
2396 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
2398 (const_string "V4SF")]
2399 (const_string "TI")))])
2401 (define_insn "*movti_rex64"
2402 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
2403 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
2405 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2407 switch (which_alternative)
2413 if (get_attr_mode (insn) == MODE_V4SF)
2414 return "xorps\t%0, %0";
2416 return "pxor\t%0, %0";
2419 if (get_attr_mode (insn) == MODE_V4SF)
2420 return "movaps\t{%1, %0|%0, %1}";
2422 return "movdqa\t{%1, %0|%0, %1}";
2427 [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
2429 (cond [(eq_attr "alternative" "2,3")
2431 (ne (symbol_ref "optimize_size")
2433 (const_string "V4SF")
2434 (const_string "TI"))
2435 (eq_attr "alternative" "4")
2437 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
2439 (ne (symbol_ref "optimize_size")
2441 (const_string "V4SF")
2442 (const_string "TI"))]
2443 (const_string "DI")))])
2446 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2447 (match_operand:TI 1 "general_operand" ""))]
2448 "reload_completed && !SSE_REG_P (operands[0])
2449 && !SSE_REG_P (operands[1])"
2451 "ix86_split_long_move (operands); DONE;")
2453 ;; This expands to what emit_move_complex would generate if we didn't
2454 ;; have a movti pattern. Having this avoids problems with reload on
2455 ;; 32-bit targets when SSE is present, but doesn't seem to be harmful
2456 ;; to have around all the time.
2457 (define_expand "movcdi"
2458 [(set (match_operand:CDI 0 "nonimmediate_operand" "")
2459 (match_operand:CDI 1 "general_operand" ""))]
2462 if (push_operand (operands[0], CDImode))
2463 emit_move_complex_push (CDImode, operands[0], operands[1]);
2465 emit_move_complex_parts (operands[0], operands[1]);
2469 (define_expand "movsf"
2470 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2471 (match_operand:SF 1 "general_operand" ""))]
2473 "ix86_expand_move (SFmode, operands); DONE;")
2475 (define_insn "*pushsf"
2476 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2477 (match_operand:SF 1 "general_no_elim_operand" "f,rFm,x"))]
2480 /* Anything else should be already split before reg-stack. */
2481 gcc_assert (which_alternative == 1);
2482 return "push{l}\t%1";
2484 [(set_attr "type" "multi,push,multi")
2485 (set_attr "unit" "i387,*,*")
2486 (set_attr "mode" "SF,SI,SF")])
2488 (define_insn "*pushsf_rex64"
2489 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2490 (match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
2493 /* Anything else should be already split before reg-stack. */
2494 gcc_assert (which_alternative == 1);
2495 return "push{q}\t%q1";
2497 [(set_attr "type" "multi,push,multi")
2498 (set_attr "unit" "i387,*,*")
2499 (set_attr "mode" "SF,DI,SF")])
2502 [(set (match_operand:SF 0 "push_operand" "")
2503 (match_operand:SF 1 "memory_operand" ""))]
2505 && MEM_P (operands[1])
2506 && (operands[2] = find_constant_src (insn))"
2511 ;; %%% Kill this when call knows how to work this out.
2513 [(set (match_operand:SF 0 "push_operand" "")
2514 (match_operand:SF 1 "any_fp_register_operand" ""))]
2516 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2517 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2520 [(set (match_operand:SF 0 "push_operand" "")
2521 (match_operand:SF 1 "any_fp_register_operand" ""))]
2523 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2524 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2526 (define_insn "*movsf_1"
2527 [(set (match_operand:SF 0 "nonimmediate_operand"
2528 "=f,m,f,r ,m ,x,x,x ,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
2529 (match_operand:SF 1 "general_operand"
2530 "fm,f,G,rmF,Fr,C,x,xm,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
2531 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
2532 && (reload_in_progress || reload_completed
2533 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2534 || (!TARGET_SSE_MATH && optimize_size
2535 && standard_80387_constant_p (operands[1]))
2536 || GET_CODE (operands[1]) != CONST_DOUBLE
2537 || memory_operand (operands[0], SFmode))"
2539 switch (which_alternative)
2543 return output_387_reg_move (insn, operands);
2546 return standard_80387_constant_opcode (operands[1]);
2550 return "mov{l}\t{%1, %0|%0, %1}";
2552 if (get_attr_mode (insn) == MODE_TI)
2553 return "pxor\t%0, %0";
2555 return "xorps\t%0, %0";
2557 if (get_attr_mode (insn) == MODE_V4SF)
2558 return "movaps\t{%1, %0|%0, %1}";
2560 return "movss\t{%1, %0|%0, %1}";
2562 return "movss\t{%1, %0|%0, %1}";
2565 case 12: case 13: case 14: case 15:
2566 return "movd\t{%1, %0|%0, %1}";
2569 return "movq\t{%1, %0|%0, %1}";
2575 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sselog1,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov,ssemov,ssemov,mmxmov,mmxmov")
2577 (cond [(eq_attr "alternative" "3,4,9,10")
2579 (eq_attr "alternative" "5")
2581 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2583 (ne (symbol_ref "TARGET_SSE2")
2585 (eq (symbol_ref "optimize_size")
2588 (const_string "V4SF"))
2589 /* For architectures resolving dependencies on
2590 whole SSE registers use APS move to break dependency
2591 chains, otherwise use short move to avoid extra work.
2593 Do the same for architectures resolving dependencies on
2594 the parts. While in DF mode it is better to always handle
2595 just register parts, the SF mode is different due to lack
2596 of instructions to load just part of the register. It is
2597 better to maintain the whole registers in single format
2598 to avoid problems on using packed logical operations. */
2599 (eq_attr "alternative" "6")
2601 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2603 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2605 (const_string "V4SF")
2606 (const_string "SF"))
2607 (eq_attr "alternative" "11")
2608 (const_string "DI")]
2609 (const_string "SF")))])
2611 (define_insn "*swapsf"
2612 [(set (match_operand:SF 0 "fp_register_operand" "+f")
2613 (match_operand:SF 1 "fp_register_operand" "+f"))
2616 "reload_completed || TARGET_80387"
2618 if (STACK_TOP_P (operands[0]))
2623 [(set_attr "type" "fxch")
2624 (set_attr "mode" "SF")])
2626 (define_expand "movdf"
2627 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2628 (match_operand:DF 1 "general_operand" ""))]
2630 "ix86_expand_move (DFmode, operands); DONE;")
2632 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2633 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2634 ;; On the average, pushdf using integers can be still shorter. Allow this
2635 ;; pattern for optimize_size too.
2637 (define_insn "*pushdf_nointeger"
2638 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2639 (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Yt"))]
2640 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2642 /* This insn should be already split before reg-stack. */
2645 [(set_attr "type" "multi")
2646 (set_attr "unit" "i387,*,*,*")
2647 (set_attr "mode" "DF,SI,SI,DF")])
2649 (define_insn "*pushdf_integer"
2650 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2651 (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Yt"))]
2652 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2654 /* This insn should be already split before reg-stack. */
2657 [(set_attr "type" "multi")
2658 (set_attr "unit" "i387,*,*")
2659 (set_attr "mode" "DF,SI,DF")])
2661 ;; %%% Kill this when call knows how to work this out.
2663 [(set (match_operand:DF 0 "push_operand" "")
2664 (match_operand:DF 1 "any_fp_register_operand" ""))]
2665 "!TARGET_64BIT && reload_completed"
2666 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2667 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2671 [(set (match_operand:DF 0 "push_operand" "")
2672 (match_operand:DF 1 "any_fp_register_operand" ""))]
2673 "TARGET_64BIT && reload_completed"
2674 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2675 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2679 [(set (match_operand:DF 0 "push_operand" "")
2680 (match_operand:DF 1 "general_operand" ""))]
2683 "ix86_split_long_move (operands); DONE;")
2685 ;; Moving is usually shorter when only FP registers are used. This separate
2686 ;; movdf pattern avoids the use of integer registers for FP operations
2687 ;; when optimizing for size.
2689 (define_insn "*movdf_nointeger"
2690 [(set (match_operand:DF 0 "nonimmediate_operand"
2691 "=f,m,f,*r ,o ,Yt*x,Yt*x,Yt*x ,m ")
2692 (match_operand:DF 1 "general_operand"
2693 "fm,f,G,*roF,F*r,C ,Yt*x,mYt*x,Yt*x"))]
2694 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
2695 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2696 && (reload_in_progress || reload_completed
2697 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2698 || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
2699 && standard_80387_constant_p (operands[1]))
2700 || GET_CODE (operands[1]) != CONST_DOUBLE
2701 || memory_operand (operands[0], DFmode))"
2703 switch (which_alternative)
2707 return output_387_reg_move (insn, operands);
2710 return standard_80387_constant_opcode (operands[1]);
2716 switch (get_attr_mode (insn))
2719 return "xorps\t%0, %0";
2721 return "xorpd\t%0, %0";
2723 return "pxor\t%0, %0";
2730 switch (get_attr_mode (insn))
2733 return "movaps\t{%1, %0|%0, %1}";
2735 return "movapd\t{%1, %0|%0, %1}";
2737 return "movdqa\t{%1, %0|%0, %1}";
2739 return "movq\t{%1, %0|%0, %1}";
2741 return "movsd\t{%1, %0|%0, %1}";
2743 return "movlpd\t{%1, %0|%0, %1}";
2745 return "movlps\t{%1, %0|%0, %1}";
2754 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
2756 (cond [(eq_attr "alternative" "0,1,2")
2758 (eq_attr "alternative" "3,4")
2761 /* For SSE1, we have many fewer alternatives. */
2762 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2763 (cond [(eq_attr "alternative" "5,6")
2764 (const_string "V4SF")
2766 (const_string "V2SF"))
2768 /* xorps is one byte shorter. */
2769 (eq_attr "alternative" "5")
2770 (cond [(ne (symbol_ref "optimize_size")
2772 (const_string "V4SF")
2773 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2777 (const_string "V2DF"))
2779 /* For architectures resolving dependencies on
2780 whole SSE registers use APD move to break dependency
2781 chains, otherwise use short move to avoid extra work.
2783 movaps encodes one byte shorter. */
2784 (eq_attr "alternative" "6")
2786 [(ne (symbol_ref "optimize_size")
2788 (const_string "V4SF")
2789 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2791 (const_string "V2DF")
2793 (const_string "DF"))
2794 /* For architectures resolving dependencies on register
2795 parts we may avoid extra work to zero out upper part
2797 (eq_attr "alternative" "7")
2799 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2801 (const_string "V1DF")
2802 (const_string "DF"))
2804 (const_string "DF")))])
2806 (define_insn "*movdf_integer_rex64"
2807 [(set (match_operand:DF 0 "nonimmediate_operand"
2808 "=f,m,f,r ,m ,Yt*x,Yt*x,Yt*x,m ,Yi,r ")
2809 (match_operand:DF 1 "general_operand"
2810 "fm,f,G,rmF,Fr,C ,Yt*x,m ,Yt*x,r ,Yi"))]
2811 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2812 && (reload_in_progress || reload_completed
2813 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2814 || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
2815 && standard_80387_constant_p (operands[1]))
2816 || GET_CODE (operands[1]) != CONST_DOUBLE
2817 || memory_operand (operands[0], DFmode))"
2819 switch (which_alternative)
2823 return output_387_reg_move (insn, operands);
2826 return standard_80387_constant_opcode (operands[1]);
2833 switch (get_attr_mode (insn))
2836 return "xorps\t%0, %0";
2838 return "xorpd\t%0, %0";
2840 return "pxor\t%0, %0";
2847 switch (get_attr_mode (insn))
2850 return "movaps\t{%1, %0|%0, %1}";
2852 return "movapd\t{%1, %0|%0, %1}";
2854 return "movdqa\t{%1, %0|%0, %1}";
2856 return "movq\t{%1, %0|%0, %1}";
2858 return "movsd\t{%1, %0|%0, %1}";
2860 return "movlpd\t{%1, %0|%0, %1}";
2862 return "movlps\t{%1, %0|%0, %1}";
2869 return "movd\t{%1, %0|%0, %1}";
2875 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov,ssemov,ssemov")
2877 (cond [(eq_attr "alternative" "0,1,2")
2879 (eq_attr "alternative" "3,4,9,10")
2882 /* For SSE1, we have many fewer alternatives. */
2883 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2884 (cond [(eq_attr "alternative" "5,6")
2885 (const_string "V4SF")
2887 (const_string "V2SF"))
2889 /* xorps is one byte shorter. */
2890 (eq_attr "alternative" "5")
2891 (cond [(ne (symbol_ref "optimize_size")
2893 (const_string "V4SF")
2894 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2898 (const_string "V2DF"))
2900 /* For architectures resolving dependencies on
2901 whole SSE registers use APD move to break dependency
2902 chains, otherwise use short move to avoid extra work.
2904 movaps encodes one byte shorter. */
2905 (eq_attr "alternative" "6")
2907 [(ne (symbol_ref "optimize_size")
2909 (const_string "V4SF")
2910 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2912 (const_string "V2DF")
2914 (const_string "DF"))
2915 /* For architectures resolving dependencies on register
2916 parts we may avoid extra work to zero out upper part
2918 (eq_attr "alternative" "7")
2920 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2922 (const_string "V1DF")
2923 (const_string "DF"))
2925 (const_string "DF")))])
2927 (define_insn "*movdf_integer"
2928 [(set (match_operand:DF 0 "nonimmediate_operand"
2929 "=f,m,f,r ,o ,Yt*x,Yt*x,Yt*x,m ")
2930 (match_operand:DF 1 "general_operand"
2931 "fm,f,G,roF,Fr,C ,Yt*x,m ,Yt*x"))]
2932 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
2933 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2934 && (reload_in_progress || reload_completed
2935 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2936 || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
2937 && standard_80387_constant_p (operands[1]))
2938 || GET_CODE (operands[1]) != CONST_DOUBLE
2939 || memory_operand (operands[0], DFmode))"
2941 switch (which_alternative)
2945 return output_387_reg_move (insn, operands);
2948 return standard_80387_constant_opcode (operands[1]);
2955 switch (get_attr_mode (insn))
2958 return "xorps\t%0, %0";
2960 return "xorpd\t%0, %0";
2962 return "pxor\t%0, %0";
2969 switch (get_attr_mode (insn))
2972 return "movaps\t{%1, %0|%0, %1}";
2974 return "movapd\t{%1, %0|%0, %1}";
2976 return "movdqa\t{%1, %0|%0, %1}";
2978 return "movq\t{%1, %0|%0, %1}";
2980 return "movsd\t{%1, %0|%0, %1}";
2982 return "movlpd\t{%1, %0|%0, %1}";
2984 return "movlps\t{%1, %0|%0, %1}";
2993 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
2995 (cond [(eq_attr "alternative" "0,1,2")
2997 (eq_attr "alternative" "3,4")
3000 /* For SSE1, we have many fewer alternatives. */
3001 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
3002 (cond [(eq_attr "alternative" "5,6")
3003 (const_string "V4SF")
3005 (const_string "V2SF"))
3007 /* xorps is one byte shorter. */
3008 (eq_attr "alternative" "5")
3009 (cond [(ne (symbol_ref "optimize_size")
3011 (const_string "V4SF")
3012 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
3016 (const_string "V2DF"))
3018 /* For architectures resolving dependencies on
3019 whole SSE registers use APD move to break dependency
3020 chains, otherwise use short move to avoid extra work.
3022 movaps encodes one byte shorter. */
3023 (eq_attr "alternative" "6")
3025 [(ne (symbol_ref "optimize_size")
3027 (const_string "V4SF")
3028 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3030 (const_string "V2DF")
3032 (const_string "DF"))
3033 /* For architectures resolving dependencies on register
3034 parts we may avoid extra work to zero out upper part
3036 (eq_attr "alternative" "7")
3038 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
3040 (const_string "V1DF")
3041 (const_string "DF"))
3043 (const_string "DF")))])
3046 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3047 (match_operand:DF 1 "general_operand" ""))]
3049 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3050 && ! (ANY_FP_REG_P (operands[0]) ||
3051 (GET_CODE (operands[0]) == SUBREG
3052 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3053 && ! (ANY_FP_REG_P (operands[1]) ||
3054 (GET_CODE (operands[1]) == SUBREG
3055 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3057 "ix86_split_long_move (operands); DONE;")
3059 (define_insn "*swapdf"
3060 [(set (match_operand:DF 0 "fp_register_operand" "+f")
3061 (match_operand:DF 1 "fp_register_operand" "+f"))
3064 "reload_completed || TARGET_80387"
3066 if (STACK_TOP_P (operands[0]))
3071 [(set_attr "type" "fxch")
3072 (set_attr "mode" "DF")])
3074 (define_expand "movxf"
3075 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3076 (match_operand:XF 1 "general_operand" ""))]
3078 "ix86_expand_move (XFmode, operands); DONE;")
3080 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
3081 ;; Size of pushdf using integer instructions is 3+3*memory operand size
3082 ;; Pushing using integer instructions is longer except for constants
3083 ;; and direct memory references.
3084 ;; (assuming that any given constant is pushed only once, but this ought to be
3085 ;; handled elsewhere).
3087 (define_insn "*pushxf_nointeger"
3088 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
3089 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
3092 /* This insn should be already split before reg-stack. */
3095 [(set_attr "type" "multi")
3096 (set_attr "unit" "i387,*,*")
3097 (set_attr "mode" "XF,SI,SI")])
3099 (define_insn "*pushxf_integer"
3100 [(set (match_operand:XF 0 "push_operand" "=<,<")
3101 (match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
3104 /* This insn should be already split before reg-stack. */
3107 [(set_attr "type" "multi")
3108 (set_attr "unit" "i387,*")
3109 (set_attr "mode" "XF,SI")])
3112 [(set (match_operand 0 "push_operand" "")
3113 (match_operand 1 "general_operand" ""))]
3115 && (GET_MODE (operands[0]) == XFmode
3116 || GET_MODE (operands[0]) == DFmode)
3117 && !ANY_FP_REG_P (operands[1])"
3119 "ix86_split_long_move (operands); DONE;")
3122 [(set (match_operand:XF 0 "push_operand" "")
3123 (match_operand:XF 1 "any_fp_register_operand" ""))]
3125 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3126 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
3127 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3130 [(set (match_operand:XF 0 "push_operand" "")
3131 (match_operand:XF 1 "any_fp_register_operand" ""))]
3133 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3134 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
3135 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3137 ;; Do not use integer registers when optimizing for size
3138 (define_insn "*movxf_nointeger"
3139 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
3140 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
3142 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3143 && (reload_in_progress || reload_completed
3144 || (optimize_size && standard_80387_constant_p (operands[1]))
3145 || GET_CODE (operands[1]) != CONST_DOUBLE
3146 || memory_operand (operands[0], XFmode))"
3148 switch (which_alternative)
3152 return output_387_reg_move (insn, operands);
3155 return standard_80387_constant_opcode (operands[1]);
3163 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3164 (set_attr "mode" "XF,XF,XF,SI,SI")])
3166 (define_insn "*movxf_integer"
3167 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
3168 (match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
3170 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3171 && (reload_in_progress || reload_completed
3172 || (optimize_size && standard_80387_constant_p (operands[1]))
3173 || GET_CODE (operands[1]) != CONST_DOUBLE
3174 || memory_operand (operands[0], XFmode))"
3176 switch (which_alternative)
3180 return output_387_reg_move (insn, operands);
3183 return standard_80387_constant_opcode (operands[1]);
3192 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3193 (set_attr "mode" "XF,XF,XF,SI,SI")])
3195 (define_expand "movtf"
3196 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3197 (match_operand:TF 1 "nonimmediate_operand" ""))]
3200 ix86_expand_move (TFmode, operands);
3204 (define_insn "*movtf_internal"
3205 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
3206 (match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
3208 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3210 switch (which_alternative)
3214 if (get_attr_mode (insn) == MODE_V4SF)
3215 return "movaps\t{%1, %0|%0, %1}";
3217 return "movdqa\t{%1, %0|%0, %1}";
3219 if (get_attr_mode (insn) == MODE_V4SF)
3220 return "xorps\t%0, %0";
3222 return "pxor\t%0, %0";
3230 [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
3232 (cond [(eq_attr "alternative" "0,2")
3234 (ne (symbol_ref "optimize_size")
3236 (const_string "V4SF")
3237 (const_string "TI"))
3238 (eq_attr "alternative" "1")
3240 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
3242 (ne (symbol_ref "optimize_size")
3244 (const_string "V4SF")
3245 (const_string "TI"))]
3246 (const_string "DI")))])
3249 [(set (match_operand 0 "nonimmediate_operand" "")
3250 (match_operand 1 "general_operand" ""))]
3252 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3253 && GET_MODE (operands[0]) == XFmode
3254 && ! (ANY_FP_REG_P (operands[0]) ||
3255 (GET_CODE (operands[0]) == SUBREG
3256 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3257 && ! (ANY_FP_REG_P (operands[1]) ||
3258 (GET_CODE (operands[1]) == SUBREG
3259 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3261 "ix86_split_long_move (operands); DONE;")
3264 [(set (match_operand 0 "register_operand" "")
3265 (match_operand 1 "memory_operand" ""))]
3267 && MEM_P (operands[1])
3268 && (GET_MODE (operands[0]) == TFmode
3269 || GET_MODE (operands[0]) == XFmode
3270 || GET_MODE (operands[0]) == SFmode
3271 || GET_MODE (operands[0]) == DFmode)
3272 && (operands[2] = find_constant_src (insn))"
3273 [(set (match_dup 0) (match_dup 2))]
3275 rtx c = operands[2];
3276 rtx r = operands[0];
3278 if (GET_CODE (r) == SUBREG)
3283 if (!standard_sse_constant_p (c))
3286 else if (FP_REG_P (r))
3288 if (!standard_80387_constant_p (c))
3291 else if (MMX_REG_P (r))
3296 [(set (match_operand 0 "register_operand" "")
3297 (float_extend (match_operand 1 "memory_operand" "")))]
3299 && MEM_P (operands[1])
3300 && (GET_MODE (operands[0]) == TFmode
3301 || GET_MODE (operands[0]) == XFmode
3302 || GET_MODE (operands[0]) == SFmode
3303 || GET_MODE (operands[0]) == DFmode)
3304 && (operands[2] = find_constant_src (insn))"
3305 [(set (match_dup 0) (match_dup 2))]
3307 rtx c = operands[2];
3308 rtx r = operands[0];
3310 if (GET_CODE (r) == SUBREG)
3315 if (!standard_sse_constant_p (c))
3318 else if (FP_REG_P (r))
3320 if (!standard_80387_constant_p (c))
3323 else if (MMX_REG_P (r))
3327 (define_insn "swapxf"
3328 [(set (match_operand:XF 0 "register_operand" "+f")
3329 (match_operand:XF 1 "register_operand" "+f"))
3334 if (STACK_TOP_P (operands[0]))
3339 [(set_attr "type" "fxch")
3340 (set_attr "mode" "XF")])
3342 ;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence
3344 [(set (match_operand:X87MODEF 0 "register_operand" "")
3345 (match_operand:X87MODEF 1 "immediate_operand" ""))]
3346 "reload_completed && FP_REGNO_P (REGNO (operands[0]))
3347 && (standard_80387_constant_p (operands[1]) == 8
3348 || standard_80387_constant_p (operands[1]) == 9)"
3349 [(set (match_dup 0)(match_dup 1))
3351 (neg:X87MODEF (match_dup 0)))]
3355 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3356 if (real_isnegzero (&r))
3357 operands[1] = CONST0_RTX (<MODE>mode);
3359 operands[1] = CONST1_RTX (<MODE>mode);
3363 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3364 (match_operand:TF 1 "general_operand" ""))]
3366 && !(SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]))"
3368 "ix86_split_long_move (operands); DONE;")
3370 ;; Zero extension instructions
3372 (define_expand "zero_extendhisi2"
3373 [(set (match_operand:SI 0 "register_operand" "")
3374 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3377 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3379 operands[1] = force_reg (HImode, operands[1]);
3380 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3385 (define_insn "zero_extendhisi2_and"
3386 [(set (match_operand:SI 0 "register_operand" "=r")
3387 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3388 (clobber (reg:CC FLAGS_REG))]
3389 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3391 [(set_attr "type" "alu1")
3392 (set_attr "mode" "SI")])
3395 [(set (match_operand:SI 0 "register_operand" "")
3396 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3397 (clobber (reg:CC FLAGS_REG))]
3398 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3399 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3400 (clobber (reg:CC FLAGS_REG))])]
3403 (define_insn "*zero_extendhisi2_movzwl"
3404 [(set (match_operand:SI 0 "register_operand" "=r")
3405 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3406 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3407 "movz{wl|x}\t{%1, %0|%0, %1}"
3408 [(set_attr "type" "imovx")
3409 (set_attr "mode" "SI")])
3411 (define_expand "zero_extendqihi2"
3413 [(set (match_operand:HI 0 "register_operand" "")
3414 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3415 (clobber (reg:CC FLAGS_REG))])]
3419 (define_insn "*zero_extendqihi2_and"
3420 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3421 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3422 (clobber (reg:CC FLAGS_REG))]
3423 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3425 [(set_attr "type" "alu1")
3426 (set_attr "mode" "HI")])
3428 (define_insn "*zero_extendqihi2_movzbw_and"
3429 [(set (match_operand:HI 0 "register_operand" "=r,r")
3430 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3431 (clobber (reg:CC FLAGS_REG))]
3432 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3434 [(set_attr "type" "imovx,alu1")
3435 (set_attr "mode" "HI")])
3437 ; zero extend to SImode here to avoid partial register stalls
3438 (define_insn "*zero_extendqihi2_movzbl"
3439 [(set (match_operand:HI 0 "register_operand" "=r")
3440 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3441 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3442 "movz{bl|x}\t{%1, %k0|%k0, %k1}"
3443 [(set_attr "type" "imovx")
3444 (set_attr "mode" "SI")])
3446 ;; For the movzbw case strip only the clobber
3448 [(set (match_operand:HI 0 "register_operand" "")
3449 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3450 (clobber (reg:CC FLAGS_REG))]
3452 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3453 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3454 [(set (match_operand:HI 0 "register_operand" "")
3455 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3457 ;; When source and destination does not overlap, clear destination
3458 ;; first and then do the movb
3460 [(set (match_operand:HI 0 "register_operand" "")
3461 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3462 (clobber (reg:CC FLAGS_REG))]
3464 && ANY_QI_REG_P (operands[0])
3465 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3466 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3467 [(set (match_dup 0) (const_int 0))
3468 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3469 "operands[2] = gen_lowpart (QImode, operands[0]);")
3471 ;; Rest is handled by single and.
3473 [(set (match_operand:HI 0 "register_operand" "")
3474 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3475 (clobber (reg:CC FLAGS_REG))]
3477 && true_regnum (operands[0]) == true_regnum (operands[1])"
3478 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3479 (clobber (reg:CC FLAGS_REG))])]
3482 (define_expand "zero_extendqisi2"
3484 [(set (match_operand:SI 0 "register_operand" "")
3485 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3486 (clobber (reg:CC FLAGS_REG))])]
3490 (define_insn "*zero_extendqisi2_and"
3491 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3492 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3493 (clobber (reg:CC FLAGS_REG))]
3494 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3496 [(set_attr "type" "alu1")
3497 (set_attr "mode" "SI")])
3499 (define_insn "*zero_extendqisi2_movzbw_and"
3500 [(set (match_operand:SI 0 "register_operand" "=r,r")
3501 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3502 (clobber (reg:CC FLAGS_REG))]
3503 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3505 [(set_attr "type" "imovx,alu1")
3506 (set_attr "mode" "SI")])
3508 (define_insn "*zero_extendqisi2_movzbw"
3509 [(set (match_operand:SI 0 "register_operand" "=r")
3510 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3511 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3512 "movz{bl|x}\t{%1, %0|%0, %1}"
3513 [(set_attr "type" "imovx")
3514 (set_attr "mode" "SI")])
3516 ;; For the movzbl case strip only the clobber
3518 [(set (match_operand:SI 0 "register_operand" "")
3519 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3520 (clobber (reg:CC FLAGS_REG))]
3522 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3523 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3525 (zero_extend:SI (match_dup 1)))])
3527 ;; When source and destination does not overlap, clear destination
3528 ;; first and then do the movb
3530 [(set (match_operand:SI 0 "register_operand" "")
3531 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3532 (clobber (reg:CC FLAGS_REG))]
3534 && ANY_QI_REG_P (operands[0])
3535 && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
3536 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3537 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3538 [(set (match_dup 0) (const_int 0))
3539 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3540 "operands[2] = gen_lowpart (QImode, operands[0]);")
3542 ;; Rest is handled by single and.
3544 [(set (match_operand:SI 0 "register_operand" "")
3545 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3546 (clobber (reg:CC FLAGS_REG))]
3548 && true_regnum (operands[0]) == true_regnum (operands[1])"
3549 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3550 (clobber (reg:CC FLAGS_REG))])]
3553 ;; %%% Kill me once multi-word ops are sane.
3554 (define_expand "zero_extendsidi2"
3555 [(set (match_operand:DI 0 "register_operand" "")
3556 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3561 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3566 (define_insn "zero_extendsidi2_32"
3567 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Yt")
3569 (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
3570 (clobber (reg:CC FLAGS_REG))]
3576 movd\t{%1, %0|%0, %1}
3577 movd\t{%1, %0|%0, %1}
3578 movd\t{%1, %0|%0, %1}
3579 movd\t{%1, %0|%0, %1}"
3580 [(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")
3581 (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")])
3583 (define_insn "zero_extendsidi2_rex64"
3584 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Yt")
3586 (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
3589 mov\t{%k1, %k0|%k0, %k1}
3591 movd\t{%1, %0|%0, %1}
3592 movd\t{%1, %0|%0, %1}
3593 movd\t{%1, %0|%0, %1}
3594 movd\t{%1, %0|%0, %1}"
3595 [(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
3596 (set_attr "mode" "SI,DI,DI,DI,TI,TI")])
3599 [(set (match_operand:DI 0 "memory_operand" "")
3600 (zero_extend:DI (match_dup 0)))]
3602 [(set (match_dup 4) (const_int 0))]
3603 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3606 [(set (match_operand:DI 0 "register_operand" "")
3607 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3608 (clobber (reg:CC FLAGS_REG))]
3609 "!TARGET_64BIT && reload_completed
3610 && true_regnum (operands[0]) == true_regnum (operands[1])"
3611 [(set (match_dup 4) (const_int 0))]
3612 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3615 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3616 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3617 (clobber (reg:CC FLAGS_REG))]
3618 "!TARGET_64BIT && reload_completed
3619 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3620 [(set (match_dup 3) (match_dup 1))
3621 (set (match_dup 4) (const_int 0))]
3622 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3624 (define_insn "zero_extendhidi2"
3625 [(set (match_operand:DI 0 "register_operand" "=r")
3626 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3628 "movz{wl|x}\t{%1, %k0|%k0, %1}"
3629 [(set_attr "type" "imovx")
3630 (set_attr "mode" "DI")])
3632 (define_insn "zero_extendqidi2"
3633 [(set (match_operand:DI 0 "register_operand" "=r")
3634 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
3636 "movz{bl|x}\t{%1, %k0|%k0, %1}"
3637 [(set_attr "type" "imovx")
3638 (set_attr "mode" "DI")])
3640 ;; Sign extension instructions
3642 (define_expand "extendsidi2"
3643 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3644 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3645 (clobber (reg:CC FLAGS_REG))
3646 (clobber (match_scratch:SI 2 ""))])]
3651 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3656 (define_insn "*extendsidi2_1"
3657 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3658 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3659 (clobber (reg:CC FLAGS_REG))
3660 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3664 (define_insn "extendsidi2_rex64"
3665 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3666 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3670 movs{lq|x}\t{%1,%0|%0, %1}"
3671 [(set_attr "type" "imovx")
3672 (set_attr "mode" "DI")
3673 (set_attr "prefix_0f" "0")
3674 (set_attr "modrm" "0,1")])
3676 (define_insn "extendhidi2"
3677 [(set (match_operand:DI 0 "register_operand" "=r")
3678 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3680 "movs{wq|x}\t{%1,%0|%0, %1}"
3681 [(set_attr "type" "imovx")
3682 (set_attr "mode" "DI")])
3684 (define_insn "extendqidi2"
3685 [(set (match_operand:DI 0 "register_operand" "=r")
3686 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3688 "movs{bq|x}\t{%1,%0|%0, %1}"
3689 [(set_attr "type" "imovx")
3690 (set_attr "mode" "DI")])
3692 ;; Extend to memory case when source register does die.
3694 [(set (match_operand:DI 0 "memory_operand" "")
3695 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3696 (clobber (reg:CC FLAGS_REG))
3697 (clobber (match_operand:SI 2 "register_operand" ""))]
3699 && dead_or_set_p (insn, operands[1])
3700 && !reg_mentioned_p (operands[1], operands[0]))"
3701 [(set (match_dup 3) (match_dup 1))
3702 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3703 (clobber (reg:CC FLAGS_REG))])
3704 (set (match_dup 4) (match_dup 1))]
3705 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3707 ;; Extend to memory case when source register does not die.
3709 [(set (match_operand:DI 0 "memory_operand" "")
3710 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3711 (clobber (reg:CC FLAGS_REG))
3712 (clobber (match_operand:SI 2 "register_operand" ""))]
3716 split_di (&operands[0], 1, &operands[3], &operands[4]);
3718 emit_move_insn (operands[3], operands[1]);
3720 /* Generate a cltd if possible and doing so it profitable. */
3721 if ((optimize_size || TARGET_USE_CLTD)
3722 && true_regnum (operands[1]) == AX_REG
3723 && true_regnum (operands[2]) == DX_REG)
3725 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3729 emit_move_insn (operands[2], operands[1]);
3730 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3732 emit_move_insn (operands[4], operands[2]);
3736 ;; Extend to register case. Optimize case where source and destination
3737 ;; registers match and cases where we can use cltd.
3739 [(set (match_operand:DI 0 "register_operand" "")
3740 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3741 (clobber (reg:CC FLAGS_REG))
3742 (clobber (match_scratch:SI 2 ""))]
3746 split_di (&operands[0], 1, &operands[3], &operands[4]);
3748 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3749 emit_move_insn (operands[3], operands[1]);
3751 /* Generate a cltd if possible and doing so it profitable. */
3752 if ((optimize_size || TARGET_USE_CLTD)
3753 && true_regnum (operands[3]) == AX_REG)
3755 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3759 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3760 emit_move_insn (operands[4], operands[1]);
3762 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3766 (define_insn "extendhisi2"
3767 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3768 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3771 switch (get_attr_prefix_0f (insn))
3774 return "{cwtl|cwde}";
3776 return "movs{wl|x}\t{%1,%0|%0, %1}";
3779 [(set_attr "type" "imovx")
3780 (set_attr "mode" "SI")
3781 (set (attr "prefix_0f")
3782 ;; movsx is short decodable while cwtl is vector decoded.
3783 (if_then_else (and (eq_attr "cpu" "!k6")
3784 (eq_attr "alternative" "0"))
3786 (const_string "1")))
3788 (if_then_else (eq_attr "prefix_0f" "0")
3790 (const_string "1")))])
3792 (define_insn "*extendhisi2_zext"
3793 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3795 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3798 switch (get_attr_prefix_0f (insn))
3801 return "{cwtl|cwde}";
3803 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3806 [(set_attr "type" "imovx")
3807 (set_attr "mode" "SI")
3808 (set (attr "prefix_0f")
3809 ;; movsx is short decodable while cwtl is vector decoded.
3810 (if_then_else (and (eq_attr "cpu" "!k6")
3811 (eq_attr "alternative" "0"))
3813 (const_string "1")))
3815 (if_then_else (eq_attr "prefix_0f" "0")
3817 (const_string "1")))])
3819 (define_insn "extendqihi2"
3820 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3821 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3824 switch (get_attr_prefix_0f (insn))
3827 return "{cbtw|cbw}";
3829 return "movs{bw|x}\t{%1,%0|%0, %1}";
3832 [(set_attr "type" "imovx")
3833 (set_attr "mode" "HI")
3834 (set (attr "prefix_0f")
3835 ;; movsx is short decodable while cwtl is vector decoded.
3836 (if_then_else (and (eq_attr "cpu" "!k6")
3837 (eq_attr "alternative" "0"))
3839 (const_string "1")))
3841 (if_then_else (eq_attr "prefix_0f" "0")
3843 (const_string "1")))])
3845 (define_insn "extendqisi2"
3846 [(set (match_operand:SI 0 "register_operand" "=r")
3847 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3849 "movs{bl|x}\t{%1,%0|%0, %1}"
3850 [(set_attr "type" "imovx")
3851 (set_attr "mode" "SI")])
3853 (define_insn "*extendqisi2_zext"
3854 [(set (match_operand:DI 0 "register_operand" "=r")
3856 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3858 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3859 [(set_attr "type" "imovx")
3860 (set_attr "mode" "SI")])
3862 ;; Conversions between float and double.
3864 ;; These are all no-ops in the model used for the 80387. So just
3867 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3868 (define_insn "*dummy_extendsfdf2"
3869 [(set (match_operand:DF 0 "push_operand" "=<")
3870 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3875 [(set (match_operand:DF 0 "push_operand" "")
3876 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3878 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3879 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3882 [(set (match_operand:DF 0 "push_operand" "")
3883 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3885 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3886 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3888 (define_insn "*dummy_extendsfxf2"
3889 [(set (match_operand:XF 0 "push_operand" "=<")
3890 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3895 [(set (match_operand:XF 0 "push_operand" "")
3896 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3898 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3899 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3900 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3903 [(set (match_operand:XF 0 "push_operand" "")
3904 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3906 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3907 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3908 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3911 [(set (match_operand:XF 0 "push_operand" "")
3912 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3914 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3915 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3916 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3919 [(set (match_operand:XF 0 "push_operand" "")
3920 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3922 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3923 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3924 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3926 (define_expand "extendsfdf2"
3927 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3928 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3929 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3931 /* ??? Needed for compress_float_constant since all fp constants
3932 are LEGITIMATE_CONSTANT_P. */
3933 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3935 if ((!TARGET_SSE2 || TARGET_MIX_SSE_I387)
3936 && standard_80387_constant_p (operands[1]) > 0)
3938 operands[1] = simplify_const_unary_operation
3939 (FLOAT_EXTEND, DFmode, operands[1], SFmode);
3940 emit_move_insn_1 (operands[0], operands[1]);
3943 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3947 /* For converting SF(xmm2) to DF(xmm1), use the following code instead of
3949 unpcklps xmm2,xmm2 ; packed conversion might crash on signaling NaNs
3951 We do the conversion post reload to avoid producing of 128bit spills
3952 that might lead to ICE on 32bit target. The sequence unlikely combine
3955 [(set (match_operand:DF 0 "register_operand" "")
3957 (match_operand:SF 1 "nonimmediate_operand" "")))]
3958 "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
3959 && reload_completed && SSE_REG_P (operands[0])"
3964 (parallel [(const_int 0) (const_int 1)]))))]
3966 operands[2] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
3967 operands[3] = simplify_gen_subreg (V4SFmode, operands[0], DFmode, 0);
3968 /* Use movss for loading from memory, unpcklps reg, reg for registers.
3969 Try to avoid move when unpacking can be done in source. */
3970 if (REG_P (operands[1]))
3972 /* If it is unsafe to overwrite upper half of source, we need
3973 to move to destination and unpack there. */
3974 if ((ORIGINAL_REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3975 || PSEUDO_REGNO_BYTES (ORIGINAL_REGNO (operands[1])) > 4)
3976 && true_regnum (operands[0]) != true_regnum (operands[1]))
3978 rtx tmp = gen_rtx_REG (SFmode, true_regnum (operands[0]));
3979 emit_move_insn (tmp, operands[1]);
3982 operands[3] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
3983 emit_insn (gen_sse_unpcklps (operands[3], operands[3], operands[3]));
3986 emit_insn (gen_vec_setv4sf_0 (operands[3],
3987 CONST0_RTX (V4SFmode), operands[1]));
3990 (define_insn "*extendsfdf2_mixed"
3991 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x")
3993 (match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))]
3994 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
3996 switch (which_alternative)
4000 return output_387_reg_move (insn, operands);
4003 return "cvtss2sd\t{%1, %0|%0, %1}";
4009 [(set_attr "type" "fmov,fmov,ssecvt")
4010 (set_attr "mode" "SF,XF,DF")])
4012 (define_insn "*extendsfdf2_sse"
4013 [(set (match_operand:DF 0 "nonimmediate_operand" "=x")
4014 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4015 "TARGET_SSE2 && TARGET_SSE_MATH"
4016 "cvtss2sd\t{%1, %0|%0, %1}"
4017 [(set_attr "type" "ssecvt")
4018 (set_attr "mode" "DF")])
4020 (define_insn "*extendsfdf2_i387"
4021 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
4022 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
4024 "* return output_387_reg_move (insn, operands);"
4025 [(set_attr "type" "fmov")
4026 (set_attr "mode" "SF,XF")])
4028 (define_expand "extend<mode>xf2"
4029 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4030 (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))]
4033 /* ??? Needed for compress_float_constant since all fp constants
4034 are LEGITIMATE_CONSTANT_P. */
4035 if (GET_CODE (operands[1]) == CONST_DOUBLE)
4037 if (standard_80387_constant_p (operands[1]) > 0)
4039 operands[1] = simplify_const_unary_operation
4040 (FLOAT_EXTEND, XFmode, operands[1], <MODE>mode);
4041 emit_move_insn_1 (operands[0], operands[1]);
4044 operands[1] = validize_mem (force_const_mem (<MODE>mode, operands[1]));
4048 (define_insn "*extend<mode>xf2_i387"
4049 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
4051 (match_operand:MODEF 1 "nonimmediate_operand" "fm,f")))]
4053 "* return output_387_reg_move (insn, operands);"
4054 [(set_attr "type" "fmov")
4055 (set_attr "mode" "<MODE>,XF")])
4057 ;; %%% This seems bad bad news.
4058 ;; This cannot output into an f-reg because there is no way to be sure
4059 ;; of truncating in that case. Otherwise this is just like a simple move
4060 ;; insn. So we pretend we can output to a reg in order to get better
4061 ;; register preferencing, but we really use a stack slot.
4063 ;; Conversion from DFmode to SFmode.
4065 (define_expand "truncdfsf2"
4066 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4068 (match_operand:DF 1 "nonimmediate_operand" "")))]
4069 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4071 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
4073 else if (flag_unsafe_math_optimizations)
4077 rtx temp = assign_386_stack_local (SFmode, SLOT_VIRTUAL);
4078 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
4083 /* For converting DF(xmm2) to SF(xmm1), use the following code instead of
4085 unpcklpd xmm2,xmm2 ; packed conversion might crash on signaling NaNs
4087 We do the conversion post reload to avoid producing of 128bit spills
4088 that might lead to ICE on 32bit target. The sequence unlikely combine
4091 [(set (match_operand:SF 0 "register_operand" "")
4093 (match_operand:DF 1 "nonimmediate_operand" "")))]
4094 "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
4095 && reload_completed && SSE_REG_P (operands[0])"
4098 (float_truncate:V2SF
4102 operands[2] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4103 operands[3] = CONST0_RTX (V2SFmode);
4104 operands[4] = simplify_gen_subreg (V2DFmode, operands[0], SFmode, 0);
4105 /* Use movsd for loading from memory, unpcklpd for registers.
4106 Try to avoid move when unpacking can be done in source, or SSE3
4107 movddup is available. */
4108 if (REG_P (operands[1]))
4111 && true_regnum (operands[0]) != true_regnum (operands[1])
4112 && (ORIGINAL_REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4113 || PSEUDO_REGNO_BYTES (ORIGINAL_REGNO (operands[1])) > 8))
4115 rtx tmp = simplify_gen_subreg (DFmode, operands[0], SFmode, 0);
4116 emit_move_insn (tmp, operands[1]);
4119 else if (!TARGET_SSE3)
4120 operands[4] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4121 emit_insn (gen_vec_dupv2df (operands[4], operands[1]));
4124 emit_insn (gen_sse2_loadlpd (operands[4],
4125 CONST0_RTX (V2DFmode), operands[1]));
4128 (define_expand "truncdfsf2_with_temp"
4129 [(parallel [(set (match_operand:SF 0 "" "")
4130 (float_truncate:SF (match_operand:DF 1 "" "")))
4131 (clobber (match_operand:SF 2 "" ""))])]
4134 (define_insn "*truncdfsf_fast_mixed"
4135 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f,x")
4137 (match_operand:DF 1 "nonimmediate_operand" "f ,f,xm")))]
4138 "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
4140 switch (which_alternative)
4144 return output_387_reg_move (insn, operands);
4146 return "cvtsd2ss\t{%1, %0|%0, %1}";
4151 [(set_attr "type" "fmov,fmov,ssecvt")
4152 (set_attr "mode" "SF")])
4154 ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
4155 ;; because nothing we do here is unsafe.
4156 (define_insn "*truncdfsf_fast_sse"
4157 [(set (match_operand:SF 0 "nonimmediate_operand" "=x")
4159 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
4160 "TARGET_SSE2 && TARGET_SSE_MATH"
4161 "cvtsd2ss\t{%1, %0|%0, %1}"
4162 [(set_attr "type" "ssecvt")
4163 (set_attr "mode" "SF")])
4165 (define_insn "*truncdfsf_fast_i387"
4166 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
4168 (match_operand:DF 1 "nonimmediate_operand" "f")))]
4169 "TARGET_80387 && flag_unsafe_math_optimizations"
4170 "* return output_387_reg_move (insn, operands);"
4171 [(set_attr "type" "fmov")
4172 (set_attr "mode" "SF")])
4174 (define_insn "*truncdfsf_mixed"
4175 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Yt")
4177 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ytm")))
4178 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
4179 "TARGET_MIX_SSE_I387"
4181 switch (which_alternative)
4184 return output_387_reg_move (insn, operands);
4189 return "cvtsd2ss\t{%1, %0|%0, %1}";
4194 [(set_attr "type" "fmov,multi,ssecvt")
4195 (set_attr "unit" "*,i387,*")
4196 (set_attr "mode" "SF")])
4198 (define_insn "*truncdfsf_i387"
4199 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
4201 (match_operand:DF 1 "nonimmediate_operand" "f,f")))
4202 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
4205 switch (which_alternative)
4208 return output_387_reg_move (insn, operands);
4216 [(set_attr "type" "fmov,multi")
4217 (set_attr "unit" "*,i387")
4218 (set_attr "mode" "SF")])
4220 (define_insn "*truncdfsf2_i387_1"
4221 [(set (match_operand:SF 0 "memory_operand" "=m")
4223 (match_operand:DF 1 "register_operand" "f")))]
4225 && !(TARGET_SSE2 && TARGET_SSE_MATH)
4226 && !TARGET_MIX_SSE_I387"
4227 "* return output_387_reg_move (insn, operands);"
4228 [(set_attr "type" "fmov")
4229 (set_attr "mode" "SF")])
4232 [(set (match_operand:SF 0 "register_operand" "")
4234 (match_operand:DF 1 "fp_register_operand" "")))
4235 (clobber (match_operand 2 "" ""))]
4237 [(set (match_dup 2) (match_dup 1))
4238 (set (match_dup 0) (match_dup 2))]
4240 operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
4243 ;; Conversion from XFmode to {SF,DF}mode
4245 (define_expand "truncxf<mode>2"
4246 [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "")
4247 (float_truncate:MODEF
4248 (match_operand:XF 1 "register_operand" "")))
4249 (clobber (match_dup 2))])]
4252 if (flag_unsafe_math_optimizations)
4254 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (<MODE>mode);
4255 emit_insn (gen_truncxf<mode>2_i387_noop (reg, operands[1]));
4256 if (reg != operands[0])
4257 emit_move_insn (operands[0], reg);
4261 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_VIRTUAL);
4264 (define_insn "*truncxfsf2_mixed"
4265 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
4267 (match_operand:XF 1 "register_operand" "f,f")))
4268 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
4271 gcc_assert (!which_alternative);
4272 return output_387_reg_move (insn, operands);
4274 [(set_attr "type" "fmov,multi")
4275 (set_attr "unit" "*,i387")
4276 (set_attr "mode" "SF")])
4278 (define_insn "*truncxfdf2_mixed"
4279 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?fYt*r")
4281 (match_operand:XF 1 "register_operand" "f,f")))
4282 (clobber (match_operand:DF 2 "memory_operand" "=X,m"))]
4285 gcc_assert (!which_alternative);
4286 return output_387_reg_move (insn, operands);
4288 [(set_attr "type" "fmov,multi")
4289 (set_attr "unit" "*,i387")
4290 (set_attr "mode" "DF")])
4292 (define_insn "truncxf<mode>2_i387_noop"
4293 [(set (match_operand:MODEF 0 "register_operand" "=f")
4294 (float_truncate:MODEF
4295 (match_operand:XF 1 "register_operand" "f")))]
4296 "TARGET_80387 && flag_unsafe_math_optimizations"
4297 "* return output_387_reg_move (insn, operands);"
4298 [(set_attr "type" "fmov")
4299 (set_attr "mode" "<MODE>")])
4301 (define_insn "*truncxf<mode>2_i387"
4302 [(set (match_operand:MODEF 0 "memory_operand" "=m")
4303 (float_truncate:MODEF
4304 (match_operand:XF 1 "register_operand" "f")))]
4306 "* return output_387_reg_move (insn, operands);"
4307 [(set_attr "type" "fmov")
4308 (set_attr "mode" "<MODE>")])
4311 [(set (match_operand:MODEF 0 "register_operand" "")
4312 (float_truncate:MODEF
4313 (match_operand:XF 1 "register_operand" "")))
4314 (clobber (match_operand:MODEF 2 "memory_operand" ""))]
4315 "TARGET_80387 && reload_completed"
4316 [(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
4317 (set (match_dup 0) (match_dup 2))]
4321 [(set (match_operand:MODEF 0 "memory_operand" "")
4322 (float_truncate:MODEF
4323 (match_operand:XF 1 "register_operand" "")))
4324 (clobber (match_operand:MODEF 2 "memory_operand" ""))]
4326 [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))]
4329 ;; Signed conversion to DImode.
4331 (define_expand "fix_truncxfdi2"
4332 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4333 (fix:DI (match_operand:XF 1 "register_operand" "")))
4334 (clobber (reg:CC FLAGS_REG))])]
4339 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4344 (define_expand "fix_trunc<mode>di2"
4345 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4346 (fix:DI (match_operand:MODEF 1 "register_operand" "")))
4347 (clobber (reg:CC FLAGS_REG))])]
4348 "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
4351 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4353 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4356 if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))
4358 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4359 emit_insn (gen_fix_trunc<mode>di_sse (out, operands[1]));
4360 if (out != operands[0])
4361 emit_move_insn (operands[0], out);
4366 ;; Signed conversion to SImode.
4368 (define_expand "fix_truncxfsi2"
4369 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4370 (fix:SI (match_operand:XF 1 "register_operand" "")))
4371 (clobber (reg:CC FLAGS_REG))])]
4376 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4381 (define_expand "fix_trunc<mode>si2"
4382 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4383 (fix:SI (match_operand:MODEF 1 "register_operand" "")))
4384 (clobber (reg:CC FLAGS_REG))])]
4385 "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
4388 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4390 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4393 if (SSE_FLOAT_MODE_P (<MODE>mode))
4395 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4396 emit_insn (gen_fix_trunc<mode>si_sse (out, operands[1]));
4397 if (out != operands[0])
4398 emit_move_insn (operands[0], out);
4403 ;; Signed conversion to HImode.
4405 (define_expand "fix_trunc<mode>hi2"
4406 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4407 (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
4408 (clobber (reg:CC FLAGS_REG))])]
4410 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
4414 emit_insn (gen_fix_trunchi_fisttp_i387_1 (operands[0], operands[1]));
4419 ;; Unsigned conversion to SImode.
4421 (define_expand "fixuns_trunc<mode>si2"
4423 [(set (match_operand:SI 0 "register_operand" "")
4425 (match_operand:MODEF 1 "nonimmediate_operand" "")))
4427 (clobber (match_scratch:<ssevecmode> 3 ""))
4428 (clobber (match_scratch:<ssevecmode> 4 ""))])]
4429 "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
4431 enum machine_mode mode = <MODE>mode;
4432 enum machine_mode vecmode = <ssevecmode>mode;
4433 REAL_VALUE_TYPE TWO31r;
4436 real_ldexp (&TWO31r, &dconst1, 31);
4437 two31 = const_double_from_real_value (TWO31r, mode);
4438 two31 = ix86_build_const_vector (mode, true, two31);
4439 operands[2] = force_reg (vecmode, two31);
4442 (define_insn_and_split "*fixuns_trunc<mode>_1"
4443 [(set (match_operand:SI 0 "register_operand" "=&x,&x")
4445 (match_operand:MODEF 3 "nonimmediate_operand" "xm,xm")))
4446 (use (match_operand:<ssevecmode> 4 "nonimmediate_operand" "m,x"))
4447 (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
4448 (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
4449 "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
4451 "&& reload_completed"
4454 ix86_split_convert_uns_si_sse (operands);
4458 ;; Unsigned conversion to HImode.
4459 ;; Without these patterns, we'll try the unsigned SI conversion which
4460 ;; is complex for SSE, rather than the signed SI conversion, which isn't.
4462 (define_expand "fixuns_trunc<mode>hi2"
4464 (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "")))
4465 (set (match_operand:HI 0 "nonimmediate_operand" "")
4466 (subreg:HI (match_dup 2) 0))]
4467 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
4468 "operands[2] = gen_reg_rtx (SImode);")
4470 ;; When SSE is available, it is always faster to use it!
4471 (define_insn "fix_trunc<mode>di_sse"
4472 [(set (match_operand:DI 0 "register_operand" "=r,r")
4473 (fix:DI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
4474 "TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode)
4475 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4476 "cvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
4477 [(set_attr "type" "sseicvt")
4478 (set_attr "mode" "<MODE>")
4479 (set_attr "athlon_decode" "double,vector")
4480 (set_attr "amdfam10_decode" "double,double")])
4482 (define_insn "fix_trunc<mode>si_sse"
4483 [(set (match_operand:SI 0 "register_operand" "=r,r")
4484 (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "x,m")))]
4485 "SSE_FLOAT_MODE_P (<MODE>mode)
4486 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4487 "cvtts<ssemodefsuffix>2si\t{%1, %0|%0, %1}"
4488 [(set_attr "type" "sseicvt")
4489 (set_attr "mode" "<MODE>")
4490 (set_attr "athlon_decode" "double,vector")
4491 (set_attr "amdfam10_decode" "double,double")])
4493 ;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
4495 [(set (match_operand:MODEF 0 "register_operand" "")
4496 (match_operand:MODEF 1 "memory_operand" ""))
4497 (set (match_operand:SSEMODEI24 2 "register_operand" "")
4498 (fix:SSEMODEI24 (match_dup 0)))]
4499 "TARGET_SHORTEN_X87_SSE
4500 && peep2_reg_dead_p (2, operands[0])"
4501 [(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
4504 ;; Avoid vector decoded forms of the instruction.
4506 [(match_scratch:DF 2 "Yt")
4507 (set (match_operand:SSEMODEI24 0 "register_operand" "")
4508 (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
4509 "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
4510 [(set (match_dup 2) (match_dup 1))
4511 (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
4515 [(match_scratch:SF 2 "x")
4516 (set (match_operand:SSEMODEI24 0 "register_operand" "")
4517 (fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
4518 "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
4519 [(set (match_dup 2) (match_dup 1))
4520 (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
4523 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
4524 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
4525 (fix:X87MODEI (match_operand 1 "register_operand" "")))]
4526 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4528 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4529 && (TARGET_64BIT || <MODE>mode != DImode))
4531 && !(reload_completed || reload_in_progress)"
4536 if (memory_operand (operands[0], VOIDmode))
4537 emit_insn (gen_fix_trunc<mode>_i387_fisttp (operands[0], operands[1]));
4540 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4541 emit_insn (gen_fix_trunc<mode>_i387_fisttp_with_temp (operands[0],
4547 [(set_attr "type" "fisttp")
4548 (set_attr "mode" "<MODE>")])
4550 (define_insn "fix_trunc<mode>_i387_fisttp"
4551 [(set (match_operand:X87MODEI 0 "memory_operand" "=m")
4552 (fix:X87MODEI (match_operand 1 "register_operand" "f")))
4553 (clobber (match_scratch:XF 2 "=&1f"))]
4554 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4556 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4557 && (TARGET_64BIT || <MODE>mode != DImode))
4558 && TARGET_SSE_MATH)"
4559 "* return output_fix_trunc (insn, operands, 1);"
4560 [(set_attr "type" "fisttp")
4561 (set_attr "mode" "<MODE>")])
4563 (define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
4564 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
4565 (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
4566 (clobber (match_operand:X87MODEI 2 "memory_operand" "=m,m"))
4567 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
4568 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4570 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4571 && (TARGET_64BIT || <MODE>mode != DImode))
4572 && TARGET_SSE_MATH)"
4574 [(set_attr "type" "fisttp")
4575 (set_attr "mode" "<MODE>")])
4578 [(set (match_operand:X87MODEI 0 "register_operand" "")
4579 (fix:X87MODEI (match_operand 1 "register_operand" "")))
4580 (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
4581 (clobber (match_scratch 3 ""))]
4583 [(parallel [(set (match_dup 2) (fix:X87MODEI (match_dup 1)))
4584 (clobber (match_dup 3))])
4585 (set (match_dup 0) (match_dup 2))]
4589 [(set (match_operand:X87MODEI 0 "memory_operand" "")
4590 (fix:X87MODEI (match_operand 1 "register_operand" "")))
4591 (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
4592 (clobber (match_scratch 3 ""))]
4594 [(parallel [(set (match_dup 0) (fix:X87MODEI (match_dup 1)))
4595 (clobber (match_dup 3))])]
4598 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4599 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
4600 ;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG
4601 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
4602 ;; function in i386.c.
4603 (define_insn_and_split "*fix_trunc<mode>_i387_1"
4604 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
4605 (fix:X87MODEI (match_operand 1 "register_operand" "")))
4606 (clobber (reg:CC FLAGS_REG))]
4607 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4609 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4610 && (TARGET_64BIT || <MODE>mode != DImode))
4611 && !(reload_completed || reload_in_progress)"
4616 ix86_optimize_mode_switching[I387_TRUNC] = 1;
4618 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
4619 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
4620 if (memory_operand (operands[0], VOIDmode))
4621 emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1],
4622 operands[2], operands[3]));
4625 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4626 emit_insn (gen_fix_trunc<mode>_i387_with_temp (operands[0], operands[1],
4627 operands[2], operands[3],
4632 [(set_attr "type" "fistp")
4633 (set_attr "i387_cw" "trunc")
4634 (set_attr "mode" "<MODE>")])
4636 (define_insn "fix_truncdi_i387"
4637 [(set (match_operand:DI 0 "memory_operand" "=m")
4638 (fix:DI (match_operand 1 "register_operand" "f")))
4639 (use (match_operand:HI 2 "memory_operand" "m"))
4640 (use (match_operand:HI 3 "memory_operand" "m"))
4641 (clobber (match_scratch:XF 4 "=&1f"))]
4642 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4644 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4645 "* return output_fix_trunc (insn, operands, 0);"
4646 [(set_attr "type" "fistp")
4647 (set_attr "i387_cw" "trunc")
4648 (set_attr "mode" "DI")])
4650 (define_insn "fix_truncdi_i387_with_temp"
4651 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4652 (fix:DI (match_operand 1 "register_operand" "f,f")))
4653 (use (match_operand:HI 2 "memory_operand" "m,m"))
4654 (use (match_operand:HI 3 "memory_operand" "m,m"))
4655 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4656 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
4657 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4659 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4661 [(set_attr "type" "fistp")
4662 (set_attr "i387_cw" "trunc")
4663 (set_attr "mode" "DI")])
4666 [(set (match_operand:DI 0 "register_operand" "")
4667 (fix:DI (match_operand 1 "register_operand" "")))
4668 (use (match_operand:HI 2 "memory_operand" ""))
4669 (use (match_operand:HI 3 "memory_operand" ""))
4670 (clobber (match_operand:DI 4 "memory_operand" ""))
4671 (clobber (match_scratch 5 ""))]
4673 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4676 (clobber (match_dup 5))])
4677 (set (match_dup 0) (match_dup 4))]
4681 [(set (match_operand:DI 0 "memory_operand" "")
4682 (fix:DI (match_operand 1 "register_operand" "")))
4683 (use (match_operand:HI 2 "memory_operand" ""))
4684 (use (match_operand:HI 3 "memory_operand" ""))
4685 (clobber (match_operand:DI 4 "memory_operand" ""))
4686 (clobber (match_scratch 5 ""))]
4688 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4691 (clobber (match_dup 5))])]
4694 (define_insn "fix_trunc<mode>_i387"
4695 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
4696 (fix:X87MODEI12 (match_operand 1 "register_operand" "f")))
4697 (use (match_operand:HI 2 "memory_operand" "m"))
4698 (use (match_operand:HI 3 "memory_operand" "m"))]
4699 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4701 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4702 "* return output_fix_trunc (insn, operands, 0);"
4703 [(set_attr "type" "fistp")
4704 (set_attr "i387_cw" "trunc")
4705 (set_attr "mode" "<MODE>")])
4707 (define_insn "fix_trunc<mode>_i387_with_temp"
4708 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
4709 (fix:X87MODEI12 (match_operand 1 "register_operand" "f,f")))
4710 (use (match_operand:HI 2 "memory_operand" "m,m"))
4711 (use (match_operand:HI 3 "memory_operand" "m,m"))
4712 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
4713 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
4715 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4717 [(set_attr "type" "fistp")
4718 (set_attr "i387_cw" "trunc")
4719 (set_attr "mode" "<MODE>")])
4722 [(set (match_operand:X87MODEI12 0 "register_operand" "")
4723 (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
4724 (use (match_operand:HI 2 "memory_operand" ""))
4725 (use (match_operand:HI 3 "memory_operand" ""))
4726 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
4728 [(parallel [(set (match_dup 4) (fix:X87MODEI12 (match_dup 1)))
4730 (use (match_dup 3))])
4731 (set (match_dup 0) (match_dup 4))]
4735 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
4736 (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
4737 (use (match_operand:HI 2 "memory_operand" ""))
4738 (use (match_operand:HI 3 "memory_operand" ""))
4739 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
4741 [(parallel [(set (match_dup 0) (fix:X87MODEI12 (match_dup 1)))
4743 (use (match_dup 3))])]
4746 (define_insn "x86_fnstcw_1"
4747 [(set (match_operand:HI 0 "memory_operand" "=m")
4748 (unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
4751 [(set_attr "length" "2")
4752 (set_attr "mode" "HI")
4753 (set_attr "unit" "i387")])
4755 (define_insn "x86_fldcw_1"
4756 [(set (reg:HI FPCR_REG)
4757 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4760 [(set_attr "length" "2")
4761 (set_attr "mode" "HI")
4762 (set_attr "unit" "i387")
4763 (set_attr "athlon_decode" "vector")
4764 (set_attr "amdfam10_decode" "vector")])
4766 ;; Conversion between fixed point and floating point.
4768 ;; Even though we only accept memory inputs, the backend _really_
4769 ;; wants to be able to do this between registers.
4771 (define_expand "floathi<mode>2"
4772 [(set (match_operand:MODEF 0 "register_operand" "")
4773 (float:MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
4774 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
4776 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4779 (gen_floatsi<mode>2 (operands[0],
4780 convert_to_mode (SImode, operands[1], 0)));
4785 (define_insn "*floathi<mode>2_i387"
4786 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
4788 (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4790 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
4791 || TARGET_MIX_SSE_I387)"
4795 [(set_attr "type" "fmov,multi")
4796 (set_attr "mode" "<MODE>")
4797 (set_attr "unit" "*,i387")
4798 (set_attr "fp_int_src" "true")])
4800 (define_expand "floatsi<mode>2"
4801 [(set (match_operand:MODEF 0 "register_operand" "")
4802 (float:MODEF (match_operand:SI 1 "nonimmediate_operand" "")))]
4803 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
4805 /* When we use vector converts, we can't have input in memory. */
4806 if (GET_MODE (operands[0]) == DFmode
4807 && TARGET_USE_VECTOR_CONVERTS && !optimize_size && TARGET_SSE_MATH
4808 && SSE_FLOAT_MODE_P (DFmode))
4809 operands[1] = force_reg (SImode, operands[1]);
4810 else if (GET_MODE (operands[0]) == SFmode
4811 && !optimize_size && TARGET_USE_VECTOR_CONVERTS && TARGET_SSE_MATH
4812 && SSE_FLOAT_MODE_P (SFmode))
4814 /* When !flag_trapping_math, we handle SImode->SFmode vector
4815 conversions same way as SImode->DFmode.
4817 For flat_trapping_math we can't safely use vector conversion without
4818 clearing upper half, otherwise precision exception might occur.
4819 However we can still generate the common sequence converting value
4820 from general register to XMM register as:
4826 because we know that movd clears the upper half.
4828 Sadly in this case we can't rely on reload moving the value to XMM
4829 register, since we need to know if upper half is OK, so we need
4830 to do reloading by hand. We force operand to memory unless target
4831 supports inter unit moves. */
4832 if (!flag_trapping_math)
4833 operands[1] = force_reg (SImode, operands[1]);
4834 else if (!MEM_P (operands[1]))
4836 rtx tmp = assign_386_stack_local (SImode, SLOT_VIRTUAL);
4837 emit_move_insn (tmp, operands[1]);
4841 /* Offload operand of cvtsi2ss and cvtsi2sd into memory for
4842 !TARGET_INTER_UNIT_CONVERSIONS
4843 It is necessary for the patterns to not accept nonmemory operands
4844 as we would optimize out later. */
4845 else if (!TARGET_INTER_UNIT_CONVERSIONS
4846 && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
4848 && !MEM_P (operands[1]))
4850 rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
4851 emit_move_insn (tmp, operands[1]);
4856 (define_insn "*floatsisf2_mixed_vector"
4857 [(set (match_operand:SF 0 "register_operand" "=x,f,?f")
4858 (float:SF (match_operand:SI 1 "nonimmediate_operand" "x,m,r")))]
4859 "TARGET_MIX_SSE_I387 && !flag_trapping_math
4860 && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
4862 cvtdq2ps\t{%1, %0|%0, %1}
4865 [(set_attr "type" "sseicvt,fmov,multi")
4866 (set_attr "mode" "SF")
4867 (set_attr "unit" "*,i387,*")
4868 (set_attr "athlon_decode" "double,*,*")
4869 (set_attr "amdfam10_decode" "double,*,*")
4870 (set_attr "fp_int_src" "false,true,true")])
4872 (define_insn "*floatsisf2_mixed"
4873 [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
4874 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m")))]
4875 "TARGET_MIX_SSE_I387
4876 && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
4881 cvtsi2ss\t{%1, %0|%0, %1}
4882 cvtsi2ss\t{%1, %0|%0, %1}"
4883 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4884 (set_attr "mode" "SF")
4885 (set_attr "unit" "*,i387,*,*")
4886 (set_attr "athlon_decode" "*,*,vector,double")
4887 (set_attr "amdfam10_decode" "*,*,vector,double")
4888 (set_attr "fp_int_src" "true")])
4890 (define_insn "*floatsisf2_mixed_memory"
4891 [(set (match_operand:SF 0 "register_operand" "=f,x")
4892 (float:SF (match_operand:SI 1 "memory_operand" "m,m")))]
4893 "TARGET_MIX_SSE_I387
4894 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
4897 cvtsi2ss\t{%1, %0|%0, %1}"
4898 [(set_attr "type" "fmov,sseicvt")
4899 (set_attr "mode" "SF")
4900 (set_attr "athlon_decode" "*,double")
4901 (set_attr "amdfam10_decode" "*,double")
4902 (set_attr "fp_int_src" "true")])
4904 (define_insn "*floatsisf2_sse_vector_nointernunit"
4905 [(set (match_operand:SF 0 "register_operand" "=x")
4906 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
4907 "TARGET_SSE_MATH && flag_trapping_math
4908 && TARGET_USE_VECTOR_CONVERTS && !optimize_size
4909 && !TARGET_INTER_UNIT_MOVES"
4911 [(set_attr "type" "multi")])
4913 (define_insn "*floatsisf2_sse_vector_internunit"
4914 [(set (match_operand:SF 0 "register_operand" "=x,x")
4915 (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))]
4916 "TARGET_SSE_MATH && flag_trapping_math
4917 && TARGET_USE_VECTOR_CONVERTS && !optimize_size
4918 && TARGET_INTER_UNIT_MOVES"
4920 [(set_attr "type" "multi")])
4923 [(set (match_operand:SF 0 "register_operand" "")
4924 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4926 && TARGET_USE_VECTOR_CONVERTS && reload_completed
4927 && (TARGET_INTER_UNIT_MOVES || MEM_P (operands[1]))
4928 && !SSE_REG_P (operands[1]) && SSE_REG_P (operands[0])"
4930 (float:V4SF (match_dup 2)))]
4932 operands[2] = simplify_gen_subreg (V4SImode, operands[0], SFmode, 0);
4933 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4934 emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), operands[1]));
4938 [(set (match_operand:SF 0 "register_operand" "")
4939 (float:SF (match_operand:SI 1 "register_operand" "")))]
4941 && TARGET_USE_VECTOR_CONVERTS && reload_completed
4942 && SSE_REG_P (operands[1]) && SSE_REG_P (operands[0])"
4943 [(set (match_dup 2) (vec_duplicate:V4SI (match_dup 1)))
4945 (float:V4SF (match_dup 2)))]
4947 operands[2] = simplify_gen_subreg (V4SImode, operands[0], SFmode, 0);
4948 operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4951 (define_insn "*floatsisf2_sse_vector"
4952 [(set (match_operand:SF 0 "register_operand" "=x")
4953 (float:SF (match_operand:SI 1 "register_operand" "x")))]
4954 "TARGET_SSE_MATH && !flag_trapping_math
4955 && TARGET_USE_VECTOR_CONVERTS && !optimize_size
4956 && !TARGET_INTER_UNIT_MOVES"
4957 "cvtdq2ps\t{%1, %0|%0, %1}"
4958 [(set_attr "type" "sseicvt")
4959 (set_attr "mode" "SF")
4960 (set_attr "athlon_decode" "double")
4961 (set_attr "amdfam10_decode" "double")
4962 (set_attr "fp_int_src" "true")])
4964 (define_insn "*floatsisf2_sse"
4965 [(set (match_operand:SF 0 "register_operand" "=x,x")
4966 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
4968 && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
4970 "cvtsi2ss\t{%1, %0|%0, %1}"
4971 [(set_attr "type" "sseicvt")
4972 (set_attr "mode" "SF")
4973 (set_attr "athlon_decode" "vector,double")
4974 (set_attr "amdfam10_decode" "vector,double")
4975 (set_attr "fp_int_src" "true")])
4977 (define_insn "*floatsisf2_sse_memory"
4978 [(set (match_operand:SF 0 "register_operand" "=x")
4979 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
4981 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
4982 "cvtsi2ss\t{%1, %0|%0, %1}"
4983 [(set_attr "type" "sseicvt")
4984 (set_attr "mode" "SF")
4985 (set_attr "athlon_decode" "double")
4986 (set_attr "amdfam10_decode" "double")
4987 (set_attr "fp_int_src" "true")])
4989 (define_insn "*floatsidf2_mixed_vector"
4990 [(set (match_operand:DF 0 "register_operand" "=x,f,f")
4991 (float:DF (match_operand:SI 1 "nonimmediate_operand" "x,m,r")))]
4992 "TARGET_SSE2 && TARGET_MIX_SSE_I387
4993 && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
4995 cvtdq2pd\t{%1, %0|%0, %1}
4998 [(set_attr "type" "sseicvt,fmov,multi")
4999 (set_attr "mode" "V2DF,DF,DF")
5000 (set_attr "unit" "*,*,i387")
5001 (set_attr "athlon_decode" "double,*,*")
5002 (set_attr "amdfam10_decode" "double,*,*")
5003 (set_attr "fp_int_src" "false,true,true")])
5005 (define_insn "*floatsidf2_mixed"
5006 [(set (match_operand:DF 0 "register_operand" "=f,?f,x,x,!x")
5007 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,m,x")))]
5008 "TARGET_SSE2 && TARGET_MIX_SSE_I387
5009 && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
5014 cvtsi2sd\t{%1, %0|%0, %1}
5015 cvtsi2sd\t{%1, %0|%0, %1}
5016 cvtdq2pd\t{%1, %0|%0, %1}"
5017 [(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
5018 (set_attr "mode" "DF,DF,DF,DF,V2DF")
5019 (set_attr "unit" "*,i387,*,*,*")
5020 (set_attr "athlon_decode" "*,*,double,direct,double")
5021 (set_attr "amdfam10_decode" "*,*,vector,double,double")
5022 (set_attr "fp_int_src" "true,true,true,true,false")])
5024 (define_insn "*floatsidf2_mixed_memory"
5025 [(set (match_operand:DF 0 "register_operand" "=f,x")
5026 (float:DF (match_operand:SI 1 "memory_operand" "m,m")))]
5027 "TARGET_SSE2 && TARGET_MIX_SSE_I387
5028 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
5031 cvtsi2sd\t{%1, %0|%0, %1}"
5032 [(set_attr "type" "fmov,sseicvt")
5033 (set_attr "mode" "DF")
5034 (set_attr "athlon_decode" "*,direct")
5035 (set_attr "amdfam10_decode" "*,double")
5036 (set_attr "fp_int_src" "true")])
5038 (define_insn "*floatsidf2_sse_vector"
5039 [(set (match_operand:DF 0 "register_operand" "=x")
5040 (float:DF (match_operand:SI 1 "register_operand" "x")))]
5041 "TARGET_SSE2 && TARGET_SSE_MATH
5042 && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
5043 "cvtdq2pd\t{%1, %0|%0, %1}"
5044 [(set_attr "type" "sseicvt")
5045 (set_attr "mode" "V2DF")
5046 (set_attr "athlon_decode" "double")
5047 (set_attr "amdfam10_decode" "double")
5048 (set_attr "fp_int_src" "true")])
5051 [(set (match_operand:DF 0 "register_operand" "")
5052 (float:DF (match_operand:SI 1 "memory_operand" "")))]
5053 "TARGET_USE_VECTOR_CONVERTS && reload_completed
5054 && SSE_REG_P (operands[0])"
5059 (parallel [(const_int 0) (const_int 1)]))))]
5061 operands[2] = simplify_gen_subreg (V4SImode, operands[0], DFmode, 0);
5062 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
5063 emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), operands[1]));
5066 (define_insn "*floatsidf2_sse"
5067 [(set (match_operand:DF 0 "register_operand" "=x,x,!x")
5068 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,m,x")))]
5069 "TARGET_SSE2 && TARGET_SSE_MATH
5070 && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
5073 cvtsi2sd\t{%1, %0|%0, %1}
5074 cvtsi2sd\t{%1, %0|%0, %1}
5075 cvtdq2pd\t{%1, %0|%0, %1}"
5076 [(set_attr "type" "sseicvt")
5077 (set_attr "mode" "DF,DF,V2DF")
5078 (set_attr "athlon_decode" "double,direct,double")
5079 (set_attr "amdfam10_decode" "vector,double,double")
5080 (set_attr "fp_int_src" "true")])
5082 (define_insn "*floatsidf2_memory"
5083 [(set (match_operand:DF 0 "register_operand" "=x")
5084 (float:DF (match_operand:SI 1 "memory_operand" "x")))]
5085 "TARGET_SSE2 && TARGET_SSE_MATH
5086 && ((!TARGET_USE_VECTOR_CONVERTS && TARGET_INTER_UNIT_CONVERSIONS)
5088 "cvtsi2sd\t{%1, %0|%0, %1}"
5089 [(set_attr "type" "sseicvt")
5090 (set_attr "mode" "DF")
5091 (set_attr "athlon_decode" "direct")
5092 (set_attr "amdfam10_decode" "double")
5093 (set_attr "fp_int_src" "true")])
5095 (define_insn "*floatsi<mode>2_i387"
5096 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
5098 (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
5100 && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))"
5104 [(set_attr "type" "fmov,multi")
5105 (set_attr "mode" "<MODE>")
5106 (set_attr "unit" "*,i387")
5107 (set_attr "fp_int_src" "true")])
5109 (define_expand "floatdisf2"
5110 [(set (match_operand:SF 0 "register_operand" "")
5111 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
5112 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
5114 if (!TARGET_INTER_UNIT_CONVERSIONS && TARGET_64BIT
5115 && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (SFmode)
5117 && !MEM_P (operands[1]))
5119 rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
5120 emit_move_insn (tmp, operands[1]);
5125 (define_insn "*floatdisf2_mixed"
5126 [(set (match_operand:SF 0 "register_operand" "=f,?f,x,x")
5127 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
5128 "TARGET_64BIT && TARGET_MIX_SSE_I387
5129 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
5133 cvtsi2ss{q}\t{%1, %0|%0, %1}
5134 cvtsi2ss{q}\t{%1, %0|%0, %1}"
5135 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5136 (set_attr "mode" "SF")
5137 (set_attr "unit" "*,i387,*,*")
5138 (set_attr "athlon_decode" "*,*,vector,double")
5139 (set_attr "amdfam10_decode" "*,*,vector,double")
5140 (set_attr "fp_int_src" "true")])
5142 (define_insn "*floatdisf2_mixed"
5143 [(set (match_operand:SF 0 "register_operand" "=f,x")
5144 (float:SF (match_operand:DI 1 "memory_operand" "m,m")))]
5145 "TARGET_64BIT && TARGET_MIX_SSE_I387
5146 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
5149 cvtsi2ss{q}\t{%1, %0|%0, %1}"
5150 [(set_attr "type" "fmov,sseicvt")
5151 (set_attr "mode" "SF")
5152 (set_attr "athlon_decode" "*,double")
5153 (set_attr "amdfam10_decode" "*,double")
5154 (set_attr "fp_int_src" "true")])
5156 (define_insn "*floatdisf2_sse"
5157 [(set (match_operand:SF 0 "register_operand" "=x,x")
5158 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
5159 "TARGET_64BIT && TARGET_SSE_MATH
5160 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
5161 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
5162 [(set_attr "type" "sseicvt")
5163 (set_attr "mode" "SF")
5164 (set_attr "athlon_decode" "vector,double")
5165 (set_attr "amdfam10_decode" "vector,double")
5166 (set_attr "fp_int_src" "true")])
5168 (define_insn "*floatdisf2_memory"
5169 [(set (match_operand:SF 0 "register_operand" "=x")
5170 (float:SF (match_operand:DI 1 "memory_operand" "m")))]
5171 "TARGET_64BIT && TARGET_SSE_MATH
5172 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
5173 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
5174 [(set_attr "type" "sseicvt")
5175 (set_attr "mode" "SF")
5176 (set_attr "athlon_decode" "double")
5177 (set_attr "amdfam10_decode" "double")
5178 (set_attr "fp_int_src" "true")])
5180 (define_expand "floatdidf2"
5181 [(set (match_operand:DF 0 "register_operand" "")
5182 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5183 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
5185 if (!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)
5187 ix86_expand_convert_sign_didf_sse (operands[0], operands[1]);
5190 if (!TARGET_INTER_UNIT_CONVERSIONS && TARGET_64BIT
5191 && TARGET_SSE_MATH && SSE_FLOAT_MODE_P (DFmode)
5193 && !MEM_P (operands[1]))
5195 rtx tmp = assign_386_stack_local (GET_MODE (operands[1]), SLOT_VIRTUAL);
5196 emit_move_insn (tmp, operands[1]);
5201 (define_insn "*floatdidf2_mixed"
5202 [(set (match_operand:DF 0 "register_operand" "=f,?f,x,x")
5203 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,m")))]
5204 "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387
5205 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
5209 cvtsi2sd{q}\t{%1, %0|%0, %1}
5210 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5211 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5212 (set_attr "mode" "DF")
5213 (set_attr "unit" "*,i387,*,*")
5214 (set_attr "athlon_decode" "*,*,double,direct")
5215 (set_attr "amdfam10_decode" "*,*,vector,double")
5216 (set_attr "fp_int_src" "true")])
5218 (define_insn "*floatdidf2_mixed_memory"
5219 [(set (match_operand:DF 0 "register_operand" "=f,x")
5220 (float:DF (match_operand:DI 1 "memory_operand" "m,m")))]
5221 "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387
5222 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
5225 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5226 [(set_attr "type" "fmov,sseicvt")
5227 (set_attr "mode" "DF")
5228 (set_attr "athlon_decode" "*,direct")
5229 (set_attr "amdfam10_decode" "*,double")
5230 (set_attr "fp_int_src" "true")])
5232 (define_insn "*floatdidf2_sse"
5233 [(set (match_operand:DF 0 "register_operand" "=x,x")
5234 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,m")))]
5235 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
5236 && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
5237 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5238 [(set_attr "type" "sseicvt")
5239 (set_attr "mode" "DF")
5240 (set_attr "athlon_decode" "double,direct")
5241 (set_attr "amdfam10_decode" "vector,double")
5242 (set_attr "fp_int_src" "true")])
5244 (define_insn "*floatdidf2_sse_memory"
5245 [(set (match_operand:DF 0 "register_operand" "=x")
5246 (float:DF (match_operand:DI 1 "memory_operand" "m")))]
5247 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
5248 && !TARGET_INTER_UNIT_CONVERSIONS && !optimize_size"
5249 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5250 [(set_attr "type" "sseicvt")
5251 (set_attr "mode" "DF")
5252 (set_attr "athlon_decode" "direct")
5253 (set_attr "amdfam10_decode" "double")
5254 (set_attr "fp_int_src" "true")])
5256 (define_insn "*floatdi<mode>2_i387"
5257 [(set (match_operand:MODEF 0 "register_operand" "=f,f")
5259 (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
5261 && (!TARGET_SSE_MATH || !TARGET_64BIT
5262 || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))"
5266 [(set_attr "type" "fmov,multi")
5267 (set_attr "mode" "<MODE>")
5268 (set_attr "unit" "*,i387")
5269 (set_attr "fp_int_src" "true")])
5271 (define_insn "float<mode>xf2"
5272 [(set (match_operand:XF 0 "register_operand" "=f,f")
5273 (float:XF (match_operand:X87MODEI 1 "nonimmediate_operand" "m,?r")))]
5278 [(set_attr "type" "fmov,multi")
5279 (set_attr "mode" "XF")
5280 (set_attr "unit" "*,i387")
5281 (set_attr "fp_int_src" "true")])
5283 ;; %%% Kill these when reload knows how to do it.
5285 [(set (match_operand 0 "fp_register_operand" "")
5286 (float (match_operand 1 "register_operand" "")))]
5288 && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
5291 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5292 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5293 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5294 ix86_free_from_memory (GET_MODE (operands[1]));
5298 (define_expand "floatunssisf2"
5299 [(use (match_operand:SF 0 "register_operand" ""))
5300 (use (match_operand:SI 1 "nonimmediate_operand" ""))]
5303 if (TARGET_SSE_MATH && TARGET_SSE2)
5304 ix86_expand_convert_uns_sisf_sse (operands[0], operands[1]);
5306 x86_emit_floatuns (operands);
5310 (define_expand "floatunssidf2"
5311 [(use (match_operand:DF 0 "register_operand" ""))
5312 (use (match_operand:SI 1 "nonimmediate_operand" ""))]
5313 "!TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE2"
5314 "ix86_expand_convert_uns_sidf_sse (operands[0], operands[1]); DONE;")
5316 (define_expand "floatunsdisf2"
5317 [(use (match_operand:SF 0 "register_operand" ""))
5318 (use (match_operand:DI 1 "nonimmediate_operand" ""))]
5319 "TARGET_64BIT && TARGET_SSE_MATH"
5320 "x86_emit_floatuns (operands); DONE;")
5322 (define_expand "floatunsdidf2"
5323 [(use (match_operand:DF 0 "register_operand" ""))
5324 (use (match_operand:DI 1 "nonimmediate_operand" ""))]
5325 "TARGET_SSE_MATH && TARGET_SSE2
5326 && (TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)"
5329 x86_emit_floatuns (operands);
5331 ix86_expand_convert_uns_didf_sse (operands[0], operands[1]);
5337 ;; %%% splits for addditi3
5339 (define_expand "addti3"
5340 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5341 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5342 (match_operand:TI 2 "x86_64_general_operand" "")))
5343 (clobber (reg:CC FLAGS_REG))]
5345 "ix86_expand_binary_operator (PLUS, TImode, operands); DONE;")
5347 (define_insn "*addti3_1"
5348 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
5349 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
5350 (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
5351 (clobber (reg:CC FLAGS_REG))]
5352 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
5356 [(set (match_operand:TI 0 "nonimmediate_operand" "")
5357 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
5358 (match_operand:TI 2 "x86_64_general_operand" "")))
5359 (clobber (reg:CC FLAGS_REG))]
5360 "TARGET_64BIT && reload_completed"
5361 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
5363 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))])
5364 (parallel [(set (match_dup 3)
5365 (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
5368 (clobber (reg:CC FLAGS_REG))])]
5369 "split_ti (operands+0, 1, operands+0, operands+3);
5370 split_ti (operands+1, 1, operands+1, operands+4);
5371 split_ti (operands+2, 1, operands+2, operands+5);")
5373 ;; %%% splits for addsidi3
5374 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5375 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5376 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5378 (define_expand "adddi3"
5379 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5380 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5381 (match_operand:DI 2 "x86_64_general_operand" "")))
5382 (clobber (reg:CC FLAGS_REG))]
5384 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5386 (define_insn "*adddi3_1"
5387 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5388 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5389 (match_operand:DI 2 "general_operand" "roiF,riF")))
5390 (clobber (reg:CC FLAGS_REG))]
5391 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5395 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5396 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5397 (match_operand:DI 2 "general_operand" "")))
5398 (clobber (reg:CC FLAGS_REG))]
5399 "!TARGET_64BIT && reload_completed"
5400 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
5402 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5403 (parallel [(set (match_dup 3)
5404 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
5407 (clobber (reg:CC FLAGS_REG))])]
5408 "split_di (operands+0, 1, operands+0, operands+3);
5409 split_di (operands+1, 1, operands+1, operands+4);
5410 split_di (operands+2, 1, operands+2, operands+5);")
5412 (define_insn "adddi3_carry_rex64"
5413 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5414 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5415 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5416 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5417 (clobber (reg:CC FLAGS_REG))]
5418 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5419 "adc{q}\t{%2, %0|%0, %2}"
5420 [(set_attr "type" "alu")
5421 (set_attr "pent_pair" "pu")
5422 (set_attr "mode" "DI")])
5424 (define_insn "*adddi3_cc_rex64"
5425 [(set (reg:CC FLAGS_REG)
5426 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5427 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5429 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5430 (plus:DI (match_dup 1) (match_dup 2)))]
5431 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5432 "add{q}\t{%2, %0|%0, %2}"
5433 [(set_attr "type" "alu")
5434 (set_attr "mode" "DI")])
5436 (define_insn "*<addsub><mode>3_cc_overflow"
5437 [(set (reg:CCC FLAGS_REG)
5440 (match_operand:SWI 1 "nonimmediate_operand" "<comm>0,0")
5441 (match_operand:SWI 2 "<general_operand>" "<r><i>,<r>m"))
5443 (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
5444 (plusminus:SWI (match_dup 1) (match_dup 2)))]
5445 "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5446 "<addsub>{<imodesuffix>}\t{%2, %0|%0, %2}"
5447 [(set_attr "type" "alu")
5448 (set_attr "mode" "<MODE>")])
5450 (define_insn "*add<mode>3_cconly_overflow"
5451 [(set (reg:CCC FLAGS_REG)
5453 (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0")
5454 (match_operand:SWI 2 "<general_operand>" "<r><i>m"))
5456 (clobber (match_scratch:SWI 0 "=<r>"))]
5457 "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
5458 "add{<imodesuffix>}\t{%2, %0|%0, %2}"
5459 [(set_attr "type" "alu")
5460 (set_attr "mode" "<MODE>")])
5462 (define_insn "*sub<mode>3_cconly_overflow"
5463 [(set (reg:CCC FLAGS_REG)
5465 (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
5466 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
5469 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
5470 [(set_attr "type" "icmp")
5471 (set_attr "mode" "<MODE>")])
5473 (define_insn "*<addsub>si3_zext_cc_overflow"
5474 [(set (reg:CCC FLAGS_REG)
5476 (plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "<comm>0")
5477 (match_operand:SI 2 "general_operand" "g"))
5479 (set (match_operand:DI 0 "register_operand" "=r")
5480 (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))]
5481 "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
5482 "<addsub>{l}\t{%2, %k0|%k0, %2}"
5483 [(set_attr "type" "alu")
5484 (set_attr "mode" "SI")])
5486 (define_insn "addqi3_carry"
5487 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5488 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5489 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5490 (match_operand:QI 2 "general_operand" "qi,qm")))
5491 (clobber (reg:CC FLAGS_REG))]
5492 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5493 "adc{b}\t{%2, %0|%0, %2}"
5494 [(set_attr "type" "alu")
5495 (set_attr "pent_pair" "pu")
5496 (set_attr "mode" "QI")])
5498 (define_insn "addhi3_carry"
5499 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5500 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5501 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5502 (match_operand:HI 2 "general_operand" "ri,rm")))
5503 (clobber (reg:CC FLAGS_REG))]
5504 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5505 "adc{w}\t{%2, %0|%0, %2}"
5506 [(set_attr "type" "alu")
5507 (set_attr "pent_pair" "pu")
5508 (set_attr "mode" "HI")])
5510 (define_insn "addsi3_carry"
5511 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5512 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5513 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5514 (match_operand:SI 2 "general_operand" "ri,rm")))
5515 (clobber (reg:CC FLAGS_REG))]
5516 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5517 "adc{l}\t{%2, %0|%0, %2}"
5518 [(set_attr "type" "alu")
5519 (set_attr "pent_pair" "pu")
5520 (set_attr "mode" "SI")])
5522 (define_insn "*addsi3_carry_zext"
5523 [(set (match_operand:DI 0 "register_operand" "=r")
5525 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5526 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5527 (match_operand:SI 2 "general_operand" "g"))))
5528 (clobber (reg:CC FLAGS_REG))]
5529 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5530 "adc{l}\t{%2, %k0|%k0, %2}"
5531 [(set_attr "type" "alu")
5532 (set_attr "pent_pair" "pu")
5533 (set_attr "mode" "SI")])
5535 (define_insn "*addsi3_cc"
5536 [(set (reg:CC FLAGS_REG)
5537 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5538 (match_operand:SI 2 "general_operand" "ri,rm")]
5540 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5541 (plus:SI (match_dup 1) (match_dup 2)))]
5542 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5543 "add{l}\t{%2, %0|%0, %2}"
5544 [(set_attr "type" "alu")
5545 (set_attr "mode" "SI")])
5547 (define_insn "addqi3_cc"
5548 [(set (reg:CC FLAGS_REG)
5549 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5550 (match_operand:QI 2 "general_operand" "qi,qm")]
5552 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5553 (plus:QI (match_dup 1) (match_dup 2)))]
5554 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5555 "add{b}\t{%2, %0|%0, %2}"
5556 [(set_attr "type" "alu")
5557 (set_attr "mode" "QI")])
5559 (define_expand "addsi3"
5560 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5561 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5562 (match_operand:SI 2 "general_operand" "")))
5563 (clobber (reg:CC FLAGS_REG))])]
5565 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5567 (define_insn "*lea_1"
5568 [(set (match_operand:SI 0 "register_operand" "=r")
5569 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5571 "lea{l}\t{%a1, %0|%0, %a1}"
5572 [(set_attr "type" "lea")
5573 (set_attr "mode" "SI")])
5575 (define_insn "*lea_1_rex64"
5576 [(set (match_operand:SI 0 "register_operand" "=r")
5577 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5579 "lea{l}\t{%a1, %0|%0, %a1}"
5580 [(set_attr "type" "lea")
5581 (set_attr "mode" "SI")])
5583 (define_insn "*lea_1_zext"
5584 [(set (match_operand:DI 0 "register_operand" "=r")
5586 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5588 "lea{l}\t{%a1, %k0|%k0, %a1}"
5589 [(set_attr "type" "lea")
5590 (set_attr "mode" "SI")])
5592 (define_insn "*lea_2_rex64"
5593 [(set (match_operand:DI 0 "register_operand" "=r")
5594 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5596 "lea{q}\t{%a1, %0|%0, %a1}"
5597 [(set_attr "type" "lea")
5598 (set_attr "mode" "DI")])
5600 ;; The lea patterns for non-Pmodes needs to be matched by several
5601 ;; insns converted to real lea by splitters.
5603 (define_insn_and_split "*lea_general_1"
5604 [(set (match_operand 0 "register_operand" "=r")
5605 (plus (plus (match_operand 1 "index_register_operand" "l")
5606 (match_operand 2 "register_operand" "r"))
5607 (match_operand 3 "immediate_operand" "i")))]
5608 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5609 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5610 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5611 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5612 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5613 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5614 || GET_MODE (operands[3]) == VOIDmode)"
5616 "&& reload_completed"
5620 operands[0] = gen_lowpart (SImode, operands[0]);
5621 operands[1] = gen_lowpart (Pmode, operands[1]);
5622 operands[2] = gen_lowpart (Pmode, operands[2]);
5623 operands[3] = gen_lowpart (Pmode, operands[3]);
5624 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5626 if (Pmode != SImode)
5627 pat = gen_rtx_SUBREG (SImode, pat, 0);
5628 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5631 [(set_attr "type" "lea")
5632 (set_attr "mode" "SI")])
5634 (define_insn_and_split "*lea_general_1_zext"
5635 [(set (match_operand:DI 0 "register_operand" "=r")
5637 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
5638 (match_operand:SI 2 "register_operand" "r"))
5639 (match_operand:SI 3 "immediate_operand" "i"))))]
5642 "&& reload_completed"
5644 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5646 (match_dup 3)) 0)))]
5648 operands[1] = gen_lowpart (Pmode, operands[1]);
5649 operands[2] = gen_lowpart (Pmode, operands[2]);
5650 operands[3] = gen_lowpart (Pmode, operands[3]);
5652 [(set_attr "type" "lea")
5653 (set_attr "mode" "SI")])
5655 (define_insn_and_split "*lea_general_2"
5656 [(set (match_operand 0 "register_operand" "=r")
5657 (plus (mult (match_operand 1 "index_register_operand" "l")
5658 (match_operand 2 "const248_operand" "i"))
5659 (match_operand 3 "nonmemory_operand" "ri")))]
5660 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5661 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5662 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5663 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5664 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5665 || GET_MODE (operands[3]) == VOIDmode)"
5667 "&& reload_completed"
5671 operands[0] = gen_lowpart (SImode, operands[0]);
5672 operands[1] = gen_lowpart (Pmode, operands[1]);
5673 operands[3] = gen_lowpart (Pmode, operands[3]);
5674 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5676 if (Pmode != SImode)
5677 pat = gen_rtx_SUBREG (SImode, pat, 0);
5678 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5681 [(set_attr "type" "lea")
5682 (set_attr "mode" "SI")])
5684 (define_insn_and_split "*lea_general_2_zext"
5685 [(set (match_operand:DI 0 "register_operand" "=r")
5687 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
5688 (match_operand:SI 2 "const248_operand" "n"))
5689 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5692 "&& reload_completed"
5694 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5696 (match_dup 3)) 0)))]
5698 operands[1] = gen_lowpart (Pmode, operands[1]);
5699 operands[3] = gen_lowpart (Pmode, operands[3]);
5701 [(set_attr "type" "lea")
5702 (set_attr "mode" "SI")])
5704 (define_insn_and_split "*lea_general_3"
5705 [(set (match_operand 0 "register_operand" "=r")
5706 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
5707 (match_operand 2 "const248_operand" "i"))
5708 (match_operand 3 "register_operand" "r"))
5709 (match_operand 4 "immediate_operand" "i")))]
5710 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5711 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5712 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5713 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5714 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5716 "&& reload_completed"
5720 operands[0] = gen_lowpart (SImode, operands[0]);
5721 operands[1] = gen_lowpart (Pmode, operands[1]);
5722 operands[3] = gen_lowpart (Pmode, operands[3]);
5723 operands[4] = gen_lowpart (Pmode, operands[4]);
5724 pat = gen_rtx_PLUS (Pmode,
5725 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5729 if (Pmode != SImode)
5730 pat = gen_rtx_SUBREG (SImode, pat, 0);
5731 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5734 [(set_attr "type" "lea")
5735 (set_attr "mode" "SI")])
5737 (define_insn_and_split "*lea_general_3_zext"
5738 [(set (match_operand:DI 0 "register_operand" "=r")
5740 (plus:SI (plus:SI (mult:SI
5741 (match_operand:SI 1 "index_register_operand" "l")
5742 (match_operand:SI 2 "const248_operand" "n"))
5743 (match_operand:SI 3 "register_operand" "r"))
5744 (match_operand:SI 4 "immediate_operand" "i"))))]
5747 "&& reload_completed"
5749 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5752 (match_dup 4)) 0)))]
5754 operands[1] = gen_lowpart (Pmode, operands[1]);
5755 operands[3] = gen_lowpart (Pmode, operands[3]);
5756 operands[4] = gen_lowpart (Pmode, operands[4]);
5758 [(set_attr "type" "lea")
5759 (set_attr "mode" "SI")])
5761 (define_insn "*adddi_1_rex64"
5762 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5763 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5764 (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
5765 (clobber (reg:CC FLAGS_REG))]
5766 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5768 switch (get_attr_type (insn))
5771 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5772 return "lea{q}\t{%a2, %0|%0, %a2}";
5775 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5776 if (operands[2] == const1_rtx)
5777 return "inc{q}\t%0";
5780 gcc_assert (operands[2] == constm1_rtx);
5781 return "dec{q}\t%0";
5785 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5787 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5788 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5789 if (CONST_INT_P (operands[2])
5790 /* Avoid overflows. */
5791 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5792 && (INTVAL (operands[2]) == 128
5793 || (INTVAL (operands[2]) < 0
5794 && INTVAL (operands[2]) != -128)))
5796 operands[2] = GEN_INT (-INTVAL (operands[2]));
5797 return "sub{q}\t{%2, %0|%0, %2}";
5799 return "add{q}\t{%2, %0|%0, %2}";
5803 (cond [(eq_attr "alternative" "2")
5804 (const_string "lea")
5805 ; Current assemblers are broken and do not allow @GOTOFF in
5806 ; ought but a memory context.
5807 (match_operand:DI 2 "pic_symbolic_operand" "")
5808 (const_string "lea")
5809 (match_operand:DI 2 "incdec_operand" "")
5810 (const_string "incdec")
5812 (const_string "alu")))
5813 (set_attr "mode" "DI")])
5815 ;; Convert lea to the lea pattern to avoid flags dependency.
5817 [(set (match_operand:DI 0 "register_operand" "")
5818 (plus:DI (match_operand:DI 1 "register_operand" "")
5819 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5820 (clobber (reg:CC FLAGS_REG))]
5821 "TARGET_64BIT && reload_completed
5822 && true_regnum (operands[0]) != true_regnum (operands[1])"
5824 (plus:DI (match_dup 1)
5828 (define_insn "*adddi_2_rex64"
5829 [(set (reg FLAGS_REG)
5831 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5832 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5834 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5835 (plus:DI (match_dup 1) (match_dup 2)))]
5836 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5837 && ix86_binary_operator_ok (PLUS, DImode, operands)
5838 /* Current assemblers are broken and do not allow @GOTOFF in
5839 ought but a memory context. */
5840 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5842 switch (get_attr_type (insn))
5845 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5846 if (operands[2] == const1_rtx)
5847 return "inc{q}\t%0";
5850 gcc_assert (operands[2] == constm1_rtx);
5851 return "dec{q}\t%0";
5855 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5856 /* ???? We ought to handle there the 32bit case too
5857 - do we need new constraint? */
5858 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5859 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5860 if (CONST_INT_P (operands[2])
5861 /* Avoid overflows. */
5862 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5863 && (INTVAL (operands[2]) == 128
5864 || (INTVAL (operands[2]) < 0
5865 && INTVAL (operands[2]) != -128)))
5867 operands[2] = GEN_INT (-INTVAL (operands[2]));
5868 return "sub{q}\t{%2, %0|%0, %2}";
5870 return "add{q}\t{%2, %0|%0, %2}";
5874 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5875 (const_string "incdec")
5876 (const_string "alu")))
5877 (set_attr "mode" "DI")])
5879 (define_insn "*adddi_3_rex64"
5880 [(set (reg FLAGS_REG)
5881 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5882 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5883 (clobber (match_scratch:DI 0 "=r"))]
5885 && ix86_match_ccmode (insn, CCZmode)
5886 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
5887 /* Current assemblers are broken and do not allow @GOTOFF in
5888 ought but a memory context. */
5889 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5891 switch (get_attr_type (insn))
5894 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5895 if (operands[2] == const1_rtx)
5896 return "inc{q}\t%0";
5899 gcc_assert (operands[2] == constm1_rtx);
5900 return "dec{q}\t%0";
5904 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5905 /* ???? We ought to handle there the 32bit case too
5906 - do we need new constraint? */
5907 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5908 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5909 if (CONST_INT_P (operands[2])
5910 /* Avoid overflows. */
5911 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5912 && (INTVAL (operands[2]) == 128
5913 || (INTVAL (operands[2]) < 0
5914 && INTVAL (operands[2]) != -128)))
5916 operands[2] = GEN_INT (-INTVAL (operands[2]));
5917 return "sub{q}\t{%2, %0|%0, %2}";
5919 return "add{q}\t{%2, %0|%0, %2}";
5923 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5924 (const_string "incdec")
5925 (const_string "alu")))
5926 (set_attr "mode" "DI")])
5928 ; For comparisons against 1, -1 and 128, we may generate better code
5929 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5930 ; is matched then. We can't accept general immediate, because for
5931 ; case of overflows, the result is messed up.
5932 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5934 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5935 ; only for comparisons not depending on it.
5936 (define_insn "*adddi_4_rex64"
5937 [(set (reg FLAGS_REG)
5938 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5939 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5940 (clobber (match_scratch:DI 0 "=rm"))]
5942 && ix86_match_ccmode (insn, CCGCmode)"
5944 switch (get_attr_type (insn))
5947 if (operands[2] == constm1_rtx)
5948 return "inc{q}\t%0";
5951 gcc_assert (operands[2] == const1_rtx);
5952 return "dec{q}\t%0";
5956 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5957 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5958 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5959 if ((INTVAL (operands[2]) == -128
5960 || (INTVAL (operands[2]) > 0
5961 && INTVAL (operands[2]) != 128))
5962 /* Avoid overflows. */
5963 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5964 return "sub{q}\t{%2, %0|%0, %2}";
5965 operands[2] = GEN_INT (-INTVAL (operands[2]));
5966 return "add{q}\t{%2, %0|%0, %2}";
5970 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5971 (const_string "incdec")
5972 (const_string "alu")))
5973 (set_attr "mode" "DI")])
5975 (define_insn "*adddi_5_rex64"
5976 [(set (reg FLAGS_REG)
5978 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5979 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5981 (clobber (match_scratch:DI 0 "=r"))]
5983 && ix86_match_ccmode (insn, CCGOCmode)
5984 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
5985 /* Current assemblers are broken and do not allow @GOTOFF in
5986 ought but a memory context. */
5987 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5989 switch (get_attr_type (insn))
5992 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5993 if (operands[2] == const1_rtx)
5994 return "inc{q}\t%0";
5997 gcc_assert (operands[2] == constm1_rtx);
5998 return "dec{q}\t%0";
6002 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6003 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6004 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6005 if (CONST_INT_P (operands[2])
6006 /* Avoid overflows. */
6007 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
6008 && (INTVAL (operands[2]) == 128
6009 || (INTVAL (operands[2]) < 0
6010 && INTVAL (operands[2]) != -128)))
6012 operands[2] = GEN_INT (-INTVAL (operands[2]));
6013 return "sub{q}\t{%2, %0|%0, %2}";
6015 return "add{q}\t{%2, %0|%0, %2}";
6019 (if_then_else (match_operand:DI 2 "incdec_operand" "")
6020 (const_string "incdec")
6021 (const_string "alu")))
6022 (set_attr "mode" "DI")])
6025 (define_insn "*addsi_1"
6026 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
6027 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
6028 (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
6029 (clobber (reg:CC FLAGS_REG))]
6030 "ix86_binary_operator_ok (PLUS, SImode, operands)"
6032 switch (get_attr_type (insn))
6035 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6036 return "lea{l}\t{%a2, %0|%0, %a2}";
6039 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6040 if (operands[2] == const1_rtx)
6041 return "inc{l}\t%0";
6044 gcc_assert (operands[2] == constm1_rtx);
6045 return "dec{l}\t%0";
6049 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6051 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6052 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6053 if (CONST_INT_P (operands[2])
6054 && (INTVAL (operands[2]) == 128
6055 || (INTVAL (operands[2]) < 0
6056 && INTVAL (operands[2]) != -128)))
6058 operands[2] = GEN_INT (-INTVAL (operands[2]));
6059 return "sub{l}\t{%2, %0|%0, %2}";
6061 return "add{l}\t{%2, %0|%0, %2}";
6065 (cond [(eq_attr "alternative" "2")
6066 (const_string "lea")
6067 ; Current assemblers are broken and do not allow @GOTOFF in
6068 ; ought but a memory context.
6069 (match_operand:SI 2 "pic_symbolic_operand" "")
6070 (const_string "lea")
6071 (match_operand:SI 2 "incdec_operand" "")
6072 (const_string "incdec")
6074 (const_string "alu")))
6075 (set_attr "mode" "SI")])
6077 ;; Convert lea to the lea pattern to avoid flags dependency.
6079 [(set (match_operand 0 "register_operand" "")
6080 (plus (match_operand 1 "register_operand" "")
6081 (match_operand 2 "nonmemory_operand" "")))
6082 (clobber (reg:CC FLAGS_REG))]
6084 && true_regnum (operands[0]) != true_regnum (operands[1])"
6088 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
6089 may confuse gen_lowpart. */
6090 if (GET_MODE (operands[0]) != Pmode)
6092 operands[1] = gen_lowpart (Pmode, operands[1]);
6093 operands[2] = gen_lowpart (Pmode, operands[2]);
6095 operands[0] = gen_lowpart (SImode, operands[0]);
6096 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
6097 if (Pmode != SImode)
6098 pat = gen_rtx_SUBREG (SImode, pat, 0);
6099 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
6103 ;; It may seem that nonimmediate operand is proper one for operand 1.
6104 ;; The addsi_1 pattern allows nonimmediate operand at that place and
6105 ;; we take care in ix86_binary_operator_ok to not allow two memory
6106 ;; operands so proper swapping will be done in reload. This allow
6107 ;; patterns constructed from addsi_1 to match.
6108 (define_insn "addsi_1_zext"
6109 [(set (match_operand:DI 0 "register_operand" "=r,r")
6111 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
6112 (match_operand:SI 2 "general_operand" "rmni,lni"))))
6113 (clobber (reg:CC FLAGS_REG))]
6114 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
6116 switch (get_attr_type (insn))
6119 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
6120 return "lea{l}\t{%a2, %k0|%k0, %a2}";
6123 if (operands[2] == const1_rtx)
6124 return "inc{l}\t%k0";
6127 gcc_assert (operands[2] == constm1_rtx);
6128 return "dec{l}\t%k0";
6132 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6133 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6134 if (CONST_INT_P (operands[2])
6135 && (INTVAL (operands[2]) == 128
6136 || (INTVAL (operands[2]) < 0
6137 && INTVAL (operands[2]) != -128)))
6139 operands[2] = GEN_INT (-INTVAL (operands[2]));
6140 return "sub{l}\t{%2, %k0|%k0, %2}";
6142 return "add{l}\t{%2, %k0|%k0, %2}";
6146 (cond [(eq_attr "alternative" "1")
6147 (const_string "lea")
6148 ; Current assemblers are broken and do not allow @GOTOFF in
6149 ; ought but a memory context.
6150 (match_operand:SI 2 "pic_symbolic_operand" "")
6151 (const_string "lea")
6152 (match_operand:SI 2 "incdec_operand" "")
6153 (const_string "incdec")
6155 (const_string "alu")))
6156 (set_attr "mode" "SI")])
6158 ;; Convert lea to the lea pattern to avoid flags dependency.
6160 [(set (match_operand:DI 0 "register_operand" "")
6162 (plus:SI (match_operand:SI 1 "register_operand" "")
6163 (match_operand:SI 2 "nonmemory_operand" ""))))
6164 (clobber (reg:CC FLAGS_REG))]
6165 "TARGET_64BIT && reload_completed
6166 && true_regnum (operands[0]) != true_regnum (operands[1])"
6168 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
6170 operands[1] = gen_lowpart (Pmode, operands[1]);
6171 operands[2] = gen_lowpart (Pmode, operands[2]);
6174 (define_insn "*addsi_2"
6175 [(set (reg FLAGS_REG)
6177 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6178 (match_operand:SI 2 "general_operand" "rmni,rni"))
6180 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6181 (plus:SI (match_dup 1) (match_dup 2)))]
6182 "ix86_match_ccmode (insn, CCGOCmode)
6183 && ix86_binary_operator_ok (PLUS, SImode, operands)
6184 /* Current assemblers are broken and do not allow @GOTOFF in
6185 ought but a memory context. */
6186 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6188 switch (get_attr_type (insn))
6191 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6192 if (operands[2] == const1_rtx)
6193 return "inc{l}\t%0";
6196 gcc_assert (operands[2] == constm1_rtx);
6197 return "dec{l}\t%0";
6201 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6202 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6203 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6204 if (CONST_INT_P (operands[2])
6205 && (INTVAL (operands[2]) == 128
6206 || (INTVAL (operands[2]) < 0
6207 && INTVAL (operands[2]) != -128)))
6209 operands[2] = GEN_INT (-INTVAL (operands[2]));
6210 return "sub{l}\t{%2, %0|%0, %2}";
6212 return "add{l}\t{%2, %0|%0, %2}";
6216 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6217 (const_string "incdec")
6218 (const_string "alu")))
6219 (set_attr "mode" "SI")])
6221 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6222 (define_insn "*addsi_2_zext"
6223 [(set (reg FLAGS_REG)
6225 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6226 (match_operand:SI 2 "general_operand" "rmni"))
6228 (set (match_operand:DI 0 "register_operand" "=r")
6229 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6230 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6231 && ix86_binary_operator_ok (PLUS, SImode, operands)
6232 /* Current assemblers are broken and do not allow @GOTOFF in
6233 ought but a memory context. */
6234 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6236 switch (get_attr_type (insn))
6239 if (operands[2] == const1_rtx)
6240 return "inc{l}\t%k0";
6243 gcc_assert (operands[2] == constm1_rtx);
6244 return "dec{l}\t%k0";
6248 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6249 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6250 if (CONST_INT_P (operands[2])
6251 && (INTVAL (operands[2]) == 128
6252 || (INTVAL (operands[2]) < 0
6253 && INTVAL (operands[2]) != -128)))
6255 operands[2] = GEN_INT (-INTVAL (operands[2]));
6256 return "sub{l}\t{%2, %k0|%k0, %2}";
6258 return "add{l}\t{%2, %k0|%k0, %2}";
6262 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6263 (const_string "incdec")
6264 (const_string "alu")))
6265 (set_attr "mode" "SI")])
6267 (define_insn "*addsi_3"
6268 [(set (reg FLAGS_REG)
6269 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6270 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6271 (clobber (match_scratch:SI 0 "=r"))]
6272 "ix86_match_ccmode (insn, CCZmode)
6273 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
6274 /* Current assemblers are broken and do not allow @GOTOFF in
6275 ought but a memory context. */
6276 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6278 switch (get_attr_type (insn))
6281 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6282 if (operands[2] == const1_rtx)
6283 return "inc{l}\t%0";
6286 gcc_assert (operands[2] == constm1_rtx);
6287 return "dec{l}\t%0";
6291 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6292 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6293 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6294 if (CONST_INT_P (operands[2])
6295 && (INTVAL (operands[2]) == 128
6296 || (INTVAL (operands[2]) < 0
6297 && INTVAL (operands[2]) != -128)))
6299 operands[2] = GEN_INT (-INTVAL (operands[2]));
6300 return "sub{l}\t{%2, %0|%0, %2}";
6302 return "add{l}\t{%2, %0|%0, %2}";
6306 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6307 (const_string "incdec")
6308 (const_string "alu")))
6309 (set_attr "mode" "SI")])
6311 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6312 (define_insn "*addsi_3_zext"
6313 [(set (reg FLAGS_REG)
6314 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6315 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6316 (set (match_operand:DI 0 "register_operand" "=r")
6317 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6318 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6319 && ix86_binary_operator_ok (PLUS, SImode, operands)
6320 /* Current assemblers are broken and do not allow @GOTOFF in
6321 ought but a memory context. */
6322 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6324 switch (get_attr_type (insn))
6327 if (operands[2] == const1_rtx)
6328 return "inc{l}\t%k0";
6331 gcc_assert (operands[2] == constm1_rtx);
6332 return "dec{l}\t%k0";
6336 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6337 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6338 if (CONST_INT_P (operands[2])
6339 && (INTVAL (operands[2]) == 128
6340 || (INTVAL (operands[2]) < 0
6341 && INTVAL (operands[2]) != -128)))
6343 operands[2] = GEN_INT (-INTVAL (operands[2]));
6344 return "sub{l}\t{%2, %k0|%k0, %2}";
6346 return "add{l}\t{%2, %k0|%k0, %2}";
6350 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6351 (const_string "incdec")
6352 (const_string "alu")))
6353 (set_attr "mode" "SI")])
6355 ; For comparisons against 1, -1 and 128, we may generate better code
6356 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6357 ; is matched then. We can't accept general immediate, because for
6358 ; case of overflows, the result is messed up.
6359 ; This pattern also don't hold of 0x80000000, since the value overflows
6361 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6362 ; only for comparisons not depending on it.
6363 (define_insn "*addsi_4"
6364 [(set (reg FLAGS_REG)
6365 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6366 (match_operand:SI 2 "const_int_operand" "n")))
6367 (clobber (match_scratch:SI 0 "=rm"))]
6368 "ix86_match_ccmode (insn, CCGCmode)
6369 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6371 switch (get_attr_type (insn))
6374 if (operands[2] == constm1_rtx)
6375 return "inc{l}\t%0";
6378 gcc_assert (operands[2] == const1_rtx);
6379 return "dec{l}\t%0";
6383 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6384 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6385 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6386 if ((INTVAL (operands[2]) == -128
6387 || (INTVAL (operands[2]) > 0
6388 && INTVAL (operands[2]) != 128)))
6389 return "sub{l}\t{%2, %0|%0, %2}";
6390 operands[2] = GEN_INT (-INTVAL (operands[2]));
6391 return "add{l}\t{%2, %0|%0, %2}";
6395 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6396 (const_string "incdec")
6397 (const_string "alu")))
6398 (set_attr "mode" "SI")])
6400 (define_insn "*addsi_5"
6401 [(set (reg FLAGS_REG)
6403 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6404 (match_operand:SI 2 "general_operand" "rmni"))
6406 (clobber (match_scratch:SI 0 "=r"))]
6407 "ix86_match_ccmode (insn, CCGOCmode)
6408 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
6409 /* Current assemblers are broken and do not allow @GOTOFF in
6410 ought but a memory context. */
6411 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6413 switch (get_attr_type (insn))
6416 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6417 if (operands[2] == const1_rtx)
6418 return "inc{l}\t%0";
6421 gcc_assert (operands[2] == constm1_rtx);
6422 return "dec{l}\t%0";
6426 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6427 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6428 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6429 if (CONST_INT_P (operands[2])
6430 && (INTVAL (operands[2]) == 128
6431 || (INTVAL (operands[2]) < 0
6432 && INTVAL (operands[2]) != -128)))
6434 operands[2] = GEN_INT (-INTVAL (operands[2]));
6435 return "sub{l}\t{%2, %0|%0, %2}";
6437 return "add{l}\t{%2, %0|%0, %2}";
6441 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6442 (const_string "incdec")
6443 (const_string "alu")))
6444 (set_attr "mode" "SI")])
6446 (define_expand "addhi3"
6447 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6448 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6449 (match_operand:HI 2 "general_operand" "")))
6450 (clobber (reg:CC FLAGS_REG))])]
6451 "TARGET_HIMODE_MATH"
6452 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6454 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6455 ;; type optimizations enabled by define-splits. This is not important
6456 ;; for PII, and in fact harmful because of partial register stalls.
6458 (define_insn "*addhi_1_lea"
6459 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6460 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6461 (match_operand:HI 2 "general_operand" "ri,rm,lni")))
6462 (clobber (reg:CC FLAGS_REG))]
6463 "!TARGET_PARTIAL_REG_STALL
6464 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6466 switch (get_attr_type (insn))
6471 if (operands[2] == const1_rtx)
6472 return "inc{w}\t%0";
6475 gcc_assert (operands[2] == constm1_rtx);
6476 return "dec{w}\t%0";
6480 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6481 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6482 if (CONST_INT_P (operands[2])
6483 && (INTVAL (operands[2]) == 128
6484 || (INTVAL (operands[2]) < 0
6485 && INTVAL (operands[2]) != -128)))
6487 operands[2] = GEN_INT (-INTVAL (operands[2]));
6488 return "sub{w}\t{%2, %0|%0, %2}";
6490 return "add{w}\t{%2, %0|%0, %2}";
6494 (if_then_else (eq_attr "alternative" "2")
6495 (const_string "lea")
6496 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6497 (const_string "incdec")
6498 (const_string "alu"))))
6499 (set_attr "mode" "HI,HI,SI")])
6501 (define_insn "*addhi_1"
6502 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6503 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6504 (match_operand:HI 2 "general_operand" "ri,rm")))
6505 (clobber (reg:CC FLAGS_REG))]
6506 "TARGET_PARTIAL_REG_STALL
6507 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6509 switch (get_attr_type (insn))
6512 if (operands[2] == const1_rtx)
6513 return "inc{w}\t%0";
6516 gcc_assert (operands[2] == constm1_rtx);
6517 return "dec{w}\t%0";
6521 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6522 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6523 if (CONST_INT_P (operands[2])
6524 && (INTVAL (operands[2]) == 128
6525 || (INTVAL (operands[2]) < 0
6526 && INTVAL (operands[2]) != -128)))
6528 operands[2] = GEN_INT (-INTVAL (operands[2]));
6529 return "sub{w}\t{%2, %0|%0, %2}";
6531 return "add{w}\t{%2, %0|%0, %2}";
6535 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6536 (const_string "incdec")
6537 (const_string "alu")))
6538 (set_attr "mode" "HI")])
6540 (define_insn "*addhi_2"
6541 [(set (reg FLAGS_REG)
6543 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6544 (match_operand:HI 2 "general_operand" "rmni,rni"))
6546 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6547 (plus:HI (match_dup 1) (match_dup 2)))]
6548 "ix86_match_ccmode (insn, CCGOCmode)
6549 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6551 switch (get_attr_type (insn))
6554 if (operands[2] == const1_rtx)
6555 return "inc{w}\t%0";
6558 gcc_assert (operands[2] == constm1_rtx);
6559 return "dec{w}\t%0";
6563 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6564 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6565 if (CONST_INT_P (operands[2])
6566 && (INTVAL (operands[2]) == 128
6567 || (INTVAL (operands[2]) < 0
6568 && INTVAL (operands[2]) != -128)))
6570 operands[2] = GEN_INT (-INTVAL (operands[2]));
6571 return "sub{w}\t{%2, %0|%0, %2}";
6573 return "add{w}\t{%2, %0|%0, %2}";
6577 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6578 (const_string "incdec")
6579 (const_string "alu")))
6580 (set_attr "mode" "HI")])
6582 (define_insn "*addhi_3"
6583 [(set (reg FLAGS_REG)
6584 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6585 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6586 (clobber (match_scratch:HI 0 "=r"))]
6587 "ix86_match_ccmode (insn, CCZmode)
6588 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6590 switch (get_attr_type (insn))
6593 if (operands[2] == const1_rtx)
6594 return "inc{w}\t%0";
6597 gcc_assert (operands[2] == constm1_rtx);
6598 return "dec{w}\t%0";
6602 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6603 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6604 if (CONST_INT_P (operands[2])
6605 && (INTVAL (operands[2]) == 128
6606 || (INTVAL (operands[2]) < 0
6607 && INTVAL (operands[2]) != -128)))
6609 operands[2] = GEN_INT (-INTVAL (operands[2]));
6610 return "sub{w}\t{%2, %0|%0, %2}";
6612 return "add{w}\t{%2, %0|%0, %2}";
6616 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6617 (const_string "incdec")
6618 (const_string "alu")))
6619 (set_attr "mode" "HI")])
6621 ; See comments above addsi_4 for details.
6622 (define_insn "*addhi_4"
6623 [(set (reg FLAGS_REG)
6624 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6625 (match_operand:HI 2 "const_int_operand" "n")))
6626 (clobber (match_scratch:HI 0 "=rm"))]
6627 "ix86_match_ccmode (insn, CCGCmode)
6628 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6630 switch (get_attr_type (insn))
6633 if (operands[2] == constm1_rtx)
6634 return "inc{w}\t%0";
6637 gcc_assert (operands[2] == const1_rtx);
6638 return "dec{w}\t%0";
6642 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6643 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6644 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6645 if ((INTVAL (operands[2]) == -128
6646 || (INTVAL (operands[2]) > 0
6647 && INTVAL (operands[2]) != 128)))
6648 return "sub{w}\t{%2, %0|%0, %2}";
6649 operands[2] = GEN_INT (-INTVAL (operands[2]));
6650 return "add{w}\t{%2, %0|%0, %2}";
6654 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6655 (const_string "incdec")
6656 (const_string "alu")))
6657 (set_attr "mode" "SI")])
6660 (define_insn "*addhi_5"
6661 [(set (reg FLAGS_REG)
6663 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6664 (match_operand:HI 2 "general_operand" "rmni"))
6666 (clobber (match_scratch:HI 0 "=r"))]
6667 "ix86_match_ccmode (insn, CCGOCmode)
6668 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6670 switch (get_attr_type (insn))
6673 if (operands[2] == const1_rtx)
6674 return "inc{w}\t%0";
6677 gcc_assert (operands[2] == constm1_rtx);
6678 return "dec{w}\t%0";
6682 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6683 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6684 if (CONST_INT_P (operands[2])
6685 && (INTVAL (operands[2]) == 128
6686 || (INTVAL (operands[2]) < 0
6687 && INTVAL (operands[2]) != -128)))
6689 operands[2] = GEN_INT (-INTVAL (operands[2]));
6690 return "sub{w}\t{%2, %0|%0, %2}";
6692 return "add{w}\t{%2, %0|%0, %2}";
6696 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6697 (const_string "incdec")
6698 (const_string "alu")))
6699 (set_attr "mode" "HI")])
6701 (define_expand "addqi3"
6702 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6703 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6704 (match_operand:QI 2 "general_operand" "")))
6705 (clobber (reg:CC FLAGS_REG))])]
6706 "TARGET_QIMODE_MATH"
6707 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6709 ;; %%% Potential partial reg stall on alternative 2. What to do?
6710 (define_insn "*addqi_1_lea"
6711 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6712 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6713 (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
6714 (clobber (reg:CC FLAGS_REG))]
6715 "!TARGET_PARTIAL_REG_STALL
6716 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6718 int widen = (which_alternative == 2);
6719 switch (get_attr_type (insn))
6724 if (operands[2] == const1_rtx)
6725 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6728 gcc_assert (operands[2] == constm1_rtx);
6729 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6733 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6734 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6735 if (CONST_INT_P (operands[2])
6736 && (INTVAL (operands[2]) == 128
6737 || (INTVAL (operands[2]) < 0
6738 && INTVAL (operands[2]) != -128)))
6740 operands[2] = GEN_INT (-INTVAL (operands[2]));
6742 return "sub{l}\t{%2, %k0|%k0, %2}";
6744 return "sub{b}\t{%2, %0|%0, %2}";
6747 return "add{l}\t{%k2, %k0|%k0, %k2}";
6749 return "add{b}\t{%2, %0|%0, %2}";
6753 (if_then_else (eq_attr "alternative" "3")
6754 (const_string "lea")
6755 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6756 (const_string "incdec")
6757 (const_string "alu"))))
6758 (set_attr "mode" "QI,QI,SI,SI")])
6760 (define_insn "*addqi_1"
6761 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6762 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6763 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6764 (clobber (reg:CC FLAGS_REG))]
6765 "TARGET_PARTIAL_REG_STALL
6766 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6768 int widen = (which_alternative == 2);
6769 switch (get_attr_type (insn))
6772 if (operands[2] == const1_rtx)
6773 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6776 gcc_assert (operands[2] == constm1_rtx);
6777 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6781 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6782 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6783 if (CONST_INT_P (operands[2])
6784 && (INTVAL (operands[2]) == 128
6785 || (INTVAL (operands[2]) < 0
6786 && INTVAL (operands[2]) != -128)))
6788 operands[2] = GEN_INT (-INTVAL (operands[2]));
6790 return "sub{l}\t{%2, %k0|%k0, %2}";
6792 return "sub{b}\t{%2, %0|%0, %2}";
6795 return "add{l}\t{%k2, %k0|%k0, %k2}";
6797 return "add{b}\t{%2, %0|%0, %2}";
6801 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6802 (const_string "incdec")
6803 (const_string "alu")))
6804 (set_attr "mode" "QI,QI,SI")])
6806 (define_insn "*addqi_1_slp"
6807 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6808 (plus:QI (match_dup 0)
6809 (match_operand:QI 1 "general_operand" "qn,qnm")))
6810 (clobber (reg:CC FLAGS_REG))]
6811 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6812 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6814 switch (get_attr_type (insn))
6817 if (operands[1] == const1_rtx)
6818 return "inc{b}\t%0";
6821 gcc_assert (operands[1] == constm1_rtx);
6822 return "dec{b}\t%0";
6826 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6827 if (CONST_INT_P (operands[1])
6828 && INTVAL (operands[1]) < 0)
6830 operands[1] = GEN_INT (-INTVAL (operands[1]));
6831 return "sub{b}\t{%1, %0|%0, %1}";
6833 return "add{b}\t{%1, %0|%0, %1}";
6837 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6838 (const_string "incdec")
6839 (const_string "alu1")))
6840 (set (attr "memory")
6841 (if_then_else (match_operand 1 "memory_operand" "")
6842 (const_string "load")
6843 (const_string "none")))
6844 (set_attr "mode" "QI")])
6846 (define_insn "*addqi_2"
6847 [(set (reg FLAGS_REG)
6849 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6850 (match_operand:QI 2 "general_operand" "qmni,qni"))
6852 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6853 (plus:QI (match_dup 1) (match_dup 2)))]
6854 "ix86_match_ccmode (insn, CCGOCmode)
6855 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6857 switch (get_attr_type (insn))
6860 if (operands[2] == const1_rtx)
6861 return "inc{b}\t%0";
6864 gcc_assert (operands[2] == constm1_rtx
6865 || (CONST_INT_P (operands[2])
6866 && INTVAL (operands[2]) == 255));
6867 return "dec{b}\t%0";
6871 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6872 if (CONST_INT_P (operands[2])
6873 && INTVAL (operands[2]) < 0)
6875 operands[2] = GEN_INT (-INTVAL (operands[2]));
6876 return "sub{b}\t{%2, %0|%0, %2}";
6878 return "add{b}\t{%2, %0|%0, %2}";
6882 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6883 (const_string "incdec")
6884 (const_string "alu")))
6885 (set_attr "mode" "QI")])
6887 (define_insn "*addqi_3"
6888 [(set (reg FLAGS_REG)
6889 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6890 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6891 (clobber (match_scratch:QI 0 "=q"))]
6892 "ix86_match_ccmode (insn, CCZmode)
6893 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6895 switch (get_attr_type (insn))
6898 if (operands[2] == const1_rtx)
6899 return "inc{b}\t%0";
6902 gcc_assert (operands[2] == constm1_rtx
6903 || (CONST_INT_P (operands[2])
6904 && INTVAL (operands[2]) == 255));
6905 return "dec{b}\t%0";
6909 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6910 if (CONST_INT_P (operands[2])
6911 && INTVAL (operands[2]) < 0)
6913 operands[2] = GEN_INT (-INTVAL (operands[2]));
6914 return "sub{b}\t{%2, %0|%0, %2}";
6916 return "add{b}\t{%2, %0|%0, %2}";
6920 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6921 (const_string "incdec")
6922 (const_string "alu")))
6923 (set_attr "mode" "QI")])
6925 ; See comments above addsi_4 for details.
6926 (define_insn "*addqi_4"
6927 [(set (reg FLAGS_REG)
6928 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6929 (match_operand:QI 2 "const_int_operand" "n")))
6930 (clobber (match_scratch:QI 0 "=qm"))]
6931 "ix86_match_ccmode (insn, CCGCmode)
6932 && (INTVAL (operands[2]) & 0xff) != 0x80"
6934 switch (get_attr_type (insn))
6937 if (operands[2] == constm1_rtx
6938 || (CONST_INT_P (operands[2])
6939 && INTVAL (operands[2]) == 255))
6940 return "inc{b}\t%0";
6943 gcc_assert (operands[2] == const1_rtx);
6944 return "dec{b}\t%0";
6948 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6949 if (INTVAL (operands[2]) < 0)
6951 operands[2] = GEN_INT (-INTVAL (operands[2]));
6952 return "add{b}\t{%2, %0|%0, %2}";
6954 return "sub{b}\t{%2, %0|%0, %2}";
6958 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6959 (const_string "incdec")
6960 (const_string "alu")))
6961 (set_attr "mode" "QI")])
6964 (define_insn "*addqi_5"
6965 [(set (reg FLAGS_REG)
6967 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6968 (match_operand:QI 2 "general_operand" "qmni"))
6970 (clobber (match_scratch:QI 0 "=q"))]
6971 "ix86_match_ccmode (insn, CCGOCmode)
6972 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
6974 switch (get_attr_type (insn))
6977 if (operands[2] == const1_rtx)
6978 return "inc{b}\t%0";
6981 gcc_assert (operands[2] == constm1_rtx
6982 || (CONST_INT_P (operands[2])
6983 && INTVAL (operands[2]) == 255));
6984 return "dec{b}\t%0";
6988 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6989 if (CONST_INT_P (operands[2])
6990 && INTVAL (operands[2]) < 0)
6992 operands[2] = GEN_INT (-INTVAL (operands[2]));
6993 return "sub{b}\t{%2, %0|%0, %2}";
6995 return "add{b}\t{%2, %0|%0, %2}";
6999 (if_then_else (match_operand:QI 2 "incdec_operand" "")
7000 (const_string "incdec")
7001 (const_string "alu")))
7002 (set_attr "mode" "QI")])
7005 (define_insn "addqi_ext_1"
7006 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7011 (match_operand 1 "ext_register_operand" "0")
7014 (match_operand:QI 2 "general_operand" "Qmn")))
7015 (clobber (reg:CC FLAGS_REG))]
7018 switch (get_attr_type (insn))
7021 if (operands[2] == const1_rtx)
7022 return "inc{b}\t%h0";
7025 gcc_assert (operands[2] == constm1_rtx
7026 || (CONST_INT_P (operands[2])
7027 && INTVAL (operands[2]) == 255));
7028 return "dec{b}\t%h0";
7032 return "add{b}\t{%2, %h0|%h0, %2}";
7036 (if_then_else (match_operand:QI 2 "incdec_operand" "")
7037 (const_string "incdec")
7038 (const_string "alu")))
7039 (set_attr "mode" "QI")])
7041 (define_insn "*addqi_ext_1_rex64"
7042 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7047 (match_operand 1 "ext_register_operand" "0")
7050 (match_operand:QI 2 "nonmemory_operand" "Qn")))
7051 (clobber (reg:CC FLAGS_REG))]
7054 switch (get_attr_type (insn))
7057 if (operands[2] == const1_rtx)
7058 return "inc{b}\t%h0";
7061 gcc_assert (operands[2] == constm1_rtx
7062 || (CONST_INT_P (operands[2])
7063 && INTVAL (operands[2]) == 255));
7064 return "dec{b}\t%h0";
7068 return "add{b}\t{%2, %h0|%h0, %2}";
7072 (if_then_else (match_operand:QI 2 "incdec_operand" "")
7073 (const_string "incdec")
7074 (const_string "alu")))
7075 (set_attr "mode" "QI")])
7077 (define_insn "*addqi_ext_2"
7078 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
7083 (match_operand 1 "ext_register_operand" "%0")
7087 (match_operand 2 "ext_register_operand" "Q")
7090 (clobber (reg:CC FLAGS_REG))]
7092 "add{b}\t{%h2, %h0|%h0, %h2}"
7093 [(set_attr "type" "alu")
7094 (set_attr "mode" "QI")])
7096 ;; The patterns that match these are at the end of this file.
7098 (define_expand "addxf3"
7099 [(set (match_operand:XF 0 "register_operand" "")
7100 (plus:XF (match_operand:XF 1 "register_operand" "")
7101 (match_operand:XF 2 "register_operand" "")))]
7105 (define_expand "add<mode>3"
7106 [(set (match_operand:MODEF 0 "register_operand" "")
7107 (plus:MODEF (match_operand:MODEF 1 "register_operand" "")
7108 (match_operand:MODEF 2 "nonimmediate_operand" "")))]
7109 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
7112 ;; Subtract instructions
7114 ;; %%% splits for subditi3
7116 (define_expand "subti3"
7117 [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
7118 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
7119 (match_operand:TI 2 "x86_64_general_operand" "")))
7120 (clobber (reg:CC FLAGS_REG))])]
7122 "ix86_expand_binary_operator (MINUS, TImode, operands); DONE;")
7124 (define_insn "*subti3_1"
7125 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
7126 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
7127 (match_operand:TI 2 "x86_64_general_operand" "roe,re")))
7128 (clobber (reg:CC FLAGS_REG))]
7129 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
7133 [(set (match_operand:TI 0 "nonimmediate_operand" "")
7134 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
7135 (match_operand:TI 2 "x86_64_general_operand" "")))
7136 (clobber (reg:CC FLAGS_REG))]
7137 "TARGET_64BIT && reload_completed"
7138 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
7139 (set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))])
7140 (parallel [(set (match_dup 3)
7141 (minus:DI (match_dup 4)
7142 (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
7144 (clobber (reg:CC FLAGS_REG))])]
7145 "split_ti (operands+0, 1, operands+0, operands+3);
7146 split_ti (operands+1, 1, operands+1, operands+4);
7147 split_ti (operands+2, 1, operands+2, operands+5);")
7149 ;; %%% splits for subsidi3
7151 (define_expand "subdi3"
7152 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
7153 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
7154 (match_operand:DI 2 "x86_64_general_operand" "")))
7155 (clobber (reg:CC FLAGS_REG))])]
7157 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
7159 (define_insn "*subdi3_1"
7160 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
7161 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
7162 (match_operand:DI 2 "general_operand" "roiF,riF")))
7163 (clobber (reg:CC FLAGS_REG))]
7164 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
7168 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7169 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
7170 (match_operand:DI 2 "general_operand" "")))
7171 (clobber (reg:CC FLAGS_REG))]
7172 "!TARGET_64BIT && reload_completed"
7173 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
7174 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
7175 (parallel [(set (match_dup 3)
7176 (minus:SI (match_dup 4)
7177 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
7179 (clobber (reg:CC FLAGS_REG))])]
7180 "split_di (operands+0, 1, operands+0, operands+3);
7181 split_di (operands+1, 1, operands+1, operands+4);
7182 split_di (operands+2, 1, operands+2, operands+5);")
7184 (define_insn "subdi3_carry_rex64"
7185 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
7186 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
7187 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
7188 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
7189 (clobber (reg:CC FLAGS_REG))]
7190 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
7191 "sbb{q}\t{%2, %0|%0, %2}"
7192 [(set_attr "type" "alu")
7193 (set_attr "pent_pair" "pu")
7194 (set_attr "mode" "DI")])
7196 (define_insn "*subdi_1_rex64"
7197 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
7198 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
7199 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
7200 (clobber (reg:CC FLAGS_REG))]
7201 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
7202 "sub{q}\t{%2, %0|%0, %2}"
7203 [(set_attr "type" "alu")
7204 (set_attr "mode" "DI")])
7206 (define_insn "*subdi_2_rex64"
7207 [(set (reg FLAGS_REG)
7209 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
7210 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
7212 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
7213 (minus:DI (match_dup 1) (match_dup 2)))]
7214 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7215 && ix86_binary_operator_ok (MINUS, DImode, operands)"
7216 "sub{q}\t{%2, %0|%0, %2}"
7217 [(set_attr "type" "alu")
7218 (set_attr "mode" "DI")])
7220 (define_insn "*subdi_3_rex63"
7221 [(set (reg FLAGS_REG)
7222 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
7223 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
7224 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
7225 (minus:DI (match_dup 1) (match_dup 2)))]
7226 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7227 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7228 "sub{q}\t{%2, %0|%0, %2}"
7229 [(set_attr "type" "alu")
7230 (set_attr "mode" "DI")])
7232 (define_insn "subqi3_carry"
7233 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7234 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7235 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
7236 (match_operand:QI 2 "general_operand" "qi,qm"))))
7237 (clobber (reg:CC FLAGS_REG))]
7238 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7239 "sbb{b}\t{%2, %0|%0, %2}"
7240 [(set_attr "type" "alu")
7241 (set_attr "pent_pair" "pu")
7242 (set_attr "mode" "QI")])
7244 (define_insn "subhi3_carry"
7245 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7246 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7247 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
7248 (match_operand:HI 2 "general_operand" "ri,rm"))))
7249 (clobber (reg:CC FLAGS_REG))]
7250 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7251 "sbb{w}\t{%2, %0|%0, %2}"
7252 [(set_attr "type" "alu")
7253 (set_attr "pent_pair" "pu")
7254 (set_attr "mode" "HI")])
7256 (define_insn "subsi3_carry"
7257 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7258 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7259 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
7260 (match_operand:SI 2 "general_operand" "ri,rm"))))
7261 (clobber (reg:CC FLAGS_REG))]
7262 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7263 "sbb{l}\t{%2, %0|%0, %2}"
7264 [(set_attr "type" "alu")
7265 (set_attr "pent_pair" "pu")
7266 (set_attr "mode" "SI")])
7268 (define_insn "subsi3_carry_zext"
7269 [(set (match_operand:DI 0 "register_operand" "=r")
7271 (minus:SI (match_operand:SI 1 "register_operand" "0")
7272 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
7273 (match_operand:SI 2 "general_operand" "g")))))
7274 (clobber (reg:CC FLAGS_REG))]
7275 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7276 "sbb{l}\t{%2, %k0|%k0, %2}"
7277 [(set_attr "type" "alu")
7278 (set_attr "pent_pair" "pu")
7279 (set_attr "mode" "SI")])
7281 (define_expand "subsi3"
7282 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7283 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
7284 (match_operand:SI 2 "general_operand" "")))
7285 (clobber (reg:CC FLAGS_REG))])]
7287 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
7289 (define_insn "*subsi_1"
7290 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7291 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7292 (match_operand:SI 2 "general_operand" "ri,rm")))
7293 (clobber (reg:CC FLAGS_REG))]
7294 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7295 "sub{l}\t{%2, %0|%0, %2}"
7296 [(set_attr "type" "alu")
7297 (set_attr "mode" "SI")])
7299 (define_insn "*subsi_1_zext"
7300 [(set (match_operand:DI 0 "register_operand" "=r")
7302 (minus:SI (match_operand:SI 1 "register_operand" "0")
7303 (match_operand:SI 2 "general_operand" "g"))))
7304 (clobber (reg:CC FLAGS_REG))]
7305 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7306 "sub{l}\t{%2, %k0|%k0, %2}"
7307 [(set_attr "type" "alu")
7308 (set_attr "mode" "SI")])
7310 (define_insn "*subsi_2"
7311 [(set (reg FLAGS_REG)
7313 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7314 (match_operand:SI 2 "general_operand" "ri,rm"))
7316 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7317 (minus:SI (match_dup 1) (match_dup 2)))]
7318 "ix86_match_ccmode (insn, CCGOCmode)
7319 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7320 "sub{l}\t{%2, %0|%0, %2}"
7321 [(set_attr "type" "alu")
7322 (set_attr "mode" "SI")])
7324 (define_insn "*subsi_2_zext"
7325 [(set (reg FLAGS_REG)
7327 (minus:SI (match_operand:SI 1 "register_operand" "0")
7328 (match_operand:SI 2 "general_operand" "g"))
7330 (set (match_operand:DI 0 "register_operand" "=r")
7332 (minus:SI (match_dup 1)
7334 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7335 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7336 "sub{l}\t{%2, %k0|%k0, %2}"
7337 [(set_attr "type" "alu")
7338 (set_attr "mode" "SI")])
7340 (define_insn "*subsi_3"
7341 [(set (reg FLAGS_REG)
7342 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7343 (match_operand:SI 2 "general_operand" "ri,rm")))
7344 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7345 (minus:SI (match_dup 1) (match_dup 2)))]
7346 "ix86_match_ccmode (insn, CCmode)
7347 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7348 "sub{l}\t{%2, %0|%0, %2}"
7349 [(set_attr "type" "alu")
7350 (set_attr "mode" "SI")])
7352 (define_insn "*subsi_3_zext"
7353 [(set (reg FLAGS_REG)
7354 (compare (match_operand:SI 1 "register_operand" "0")
7355 (match_operand:SI 2 "general_operand" "g")))
7356 (set (match_operand:DI 0 "register_operand" "=r")
7358 (minus:SI (match_dup 1)
7360 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7361 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7362 "sub{l}\t{%2, %1|%1, %2}"
7363 [(set_attr "type" "alu")
7364 (set_attr "mode" "DI")])
7366 (define_expand "subhi3"
7367 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7368 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7369 (match_operand:HI 2 "general_operand" "")))
7370 (clobber (reg:CC FLAGS_REG))])]
7371 "TARGET_HIMODE_MATH"
7372 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7374 (define_insn "*subhi_1"
7375 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7376 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7377 (match_operand:HI 2 "general_operand" "ri,rm")))
7378 (clobber (reg:CC FLAGS_REG))]
7379 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7380 "sub{w}\t{%2, %0|%0, %2}"
7381 [(set_attr "type" "alu")
7382 (set_attr "mode" "HI")])
7384 (define_insn "*subhi_2"
7385 [(set (reg FLAGS_REG)
7387 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7388 (match_operand:HI 2 "general_operand" "ri,rm"))
7390 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7391 (minus:HI (match_dup 1) (match_dup 2)))]
7392 "ix86_match_ccmode (insn, CCGOCmode)
7393 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7394 "sub{w}\t{%2, %0|%0, %2}"
7395 [(set_attr "type" "alu")
7396 (set_attr "mode" "HI")])
7398 (define_insn "*subhi_3"
7399 [(set (reg FLAGS_REG)
7400 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7401 (match_operand:HI 2 "general_operand" "ri,rm")))
7402 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7403 (minus:HI (match_dup 1) (match_dup 2)))]
7404 "ix86_match_ccmode (insn, CCmode)
7405 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7406 "sub{w}\t{%2, %0|%0, %2}"
7407 [(set_attr "type" "alu")
7408 (set_attr "mode" "HI")])
7410 (define_expand "subqi3"
7411 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7412 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7413 (match_operand:QI 2 "general_operand" "")))
7414 (clobber (reg:CC FLAGS_REG))])]
7415 "TARGET_QIMODE_MATH"
7416 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7418 (define_insn "*subqi_1"
7419 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7420 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7421 (match_operand:QI 2 "general_operand" "qn,qmn")))
7422 (clobber (reg:CC FLAGS_REG))]
7423 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7424 "sub{b}\t{%2, %0|%0, %2}"
7425 [(set_attr "type" "alu")
7426 (set_attr "mode" "QI")])
7428 (define_insn "*subqi_1_slp"
7429 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7430 (minus:QI (match_dup 0)
7431 (match_operand:QI 1 "general_operand" "qn,qmn")))
7432 (clobber (reg:CC FLAGS_REG))]
7433 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
7434 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7435 "sub{b}\t{%1, %0|%0, %1}"
7436 [(set_attr "type" "alu1")
7437 (set_attr "mode" "QI")])
7439 (define_insn "*subqi_2"
7440 [(set (reg FLAGS_REG)
7442 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7443 (match_operand:QI 2 "general_operand" "qi,qm"))
7445 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7446 (minus:HI (match_dup 1) (match_dup 2)))]
7447 "ix86_match_ccmode (insn, CCGOCmode)
7448 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7449 "sub{b}\t{%2, %0|%0, %2}"
7450 [(set_attr "type" "alu")
7451 (set_attr "mode" "QI")])
7453 (define_insn "*subqi_3"
7454 [(set (reg FLAGS_REG)
7455 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7456 (match_operand:QI 2 "general_operand" "qi,qm")))
7457 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7458 (minus:HI (match_dup 1) (match_dup 2)))]
7459 "ix86_match_ccmode (insn, CCmode)
7460 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7461 "sub{b}\t{%2, %0|%0, %2}"
7462 [(set_attr "type" "alu")
7463 (set_attr "mode" "QI")])
7465 ;; The patterns that match these are at the end of this file.
7467 (define_expand "subxf3"
7468 [(set (match_operand:XF 0 "register_operand" "")
7469 (minus:XF (match_operand:XF 1 "register_operand" "")
7470 (match_operand:XF 2 "register_operand" "")))]
7474 (define_expand "sub<mode>3"
7475 [(set (match_operand:MODEF 0 "register_operand" "")
7476 (minus:MODEF (match_operand:MODEF 1 "register_operand" "")
7477 (match_operand:MODEF 2 "nonimmediate_operand" "")))]
7478 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
7481 ;; Multiply instructions
7483 (define_expand "muldi3"
7484 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7485 (mult:DI (match_operand:DI 1 "register_operand" "")
7486 (match_operand:DI 2 "x86_64_general_operand" "")))
7487 (clobber (reg:CC FLAGS_REG))])]
7492 ;; IMUL reg64, reg64, imm8 Direct
7493 ;; IMUL reg64, mem64, imm8 VectorPath
7494 ;; IMUL reg64, reg64, imm32 Direct
7495 ;; IMUL reg64, mem64, imm32 VectorPath
7496 ;; IMUL reg64, reg64 Direct
7497 ;; IMUL reg64, mem64 Direct
7499 (define_insn "*muldi3_1_rex64"
7500 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7501 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
7502 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7503 (clobber (reg:CC FLAGS_REG))]
7505 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7507 imul{q}\t{%2, %1, %0|%0, %1, %2}
7508 imul{q}\t{%2, %1, %0|%0, %1, %2}
7509 imul{q}\t{%2, %0|%0, %2}"
7510 [(set_attr "type" "imul")
7511 (set_attr "prefix_0f" "0,0,1")
7512 (set (attr "athlon_decode")
7513 (cond [(eq_attr "cpu" "athlon")
7514 (const_string "vector")
7515 (eq_attr "alternative" "1")
7516 (const_string "vector")
7517 (and (eq_attr "alternative" "2")
7518 (match_operand 1 "memory_operand" ""))
7519 (const_string "vector")]
7520 (const_string "direct")))
7521 (set (attr "amdfam10_decode")
7522 (cond [(and (eq_attr "alternative" "0,1")
7523 (match_operand 1 "memory_operand" ""))
7524 (const_string "vector")]
7525 (const_string "direct")))
7526 (set_attr "mode" "DI")])
7528 (define_expand "mulsi3"
7529 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7530 (mult:SI (match_operand:SI 1 "register_operand" "")
7531 (match_operand:SI 2 "general_operand" "")))
7532 (clobber (reg:CC FLAGS_REG))])]
7537 ;; IMUL reg32, reg32, imm8 Direct
7538 ;; IMUL reg32, mem32, imm8 VectorPath
7539 ;; IMUL reg32, reg32, imm32 Direct
7540 ;; IMUL reg32, mem32, imm32 VectorPath
7541 ;; IMUL reg32, reg32 Direct
7542 ;; IMUL reg32, mem32 Direct
7544 (define_insn "*mulsi3_1"
7545 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7546 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7547 (match_operand:SI 2 "general_operand" "K,i,mr")))
7548 (clobber (reg:CC FLAGS_REG))]
7549 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
7551 imul{l}\t{%2, %1, %0|%0, %1, %2}
7552 imul{l}\t{%2, %1, %0|%0, %1, %2}
7553 imul{l}\t{%2, %0|%0, %2}"
7554 [(set_attr "type" "imul")
7555 (set_attr "prefix_0f" "0,0,1")
7556 (set (attr "athlon_decode")
7557 (cond [(eq_attr "cpu" "athlon")
7558 (const_string "vector")
7559 (eq_attr "alternative" "1")
7560 (const_string "vector")
7561 (and (eq_attr "alternative" "2")
7562 (match_operand 1 "memory_operand" ""))
7563 (const_string "vector")]
7564 (const_string "direct")))
7565 (set (attr "amdfam10_decode")
7566 (cond [(and (eq_attr "alternative" "0,1")
7567 (match_operand 1 "memory_operand" ""))
7568 (const_string "vector")]
7569 (const_string "direct")))
7570 (set_attr "mode" "SI")])
7572 (define_insn "*mulsi3_1_zext"
7573 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7575 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7576 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7577 (clobber (reg:CC FLAGS_REG))]
7579 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7581 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7582 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7583 imul{l}\t{%2, %k0|%k0, %2}"
7584 [(set_attr "type" "imul")
7585 (set_attr "prefix_0f" "0,0,1")
7586 (set (attr "athlon_decode")
7587 (cond [(eq_attr "cpu" "athlon")
7588 (const_string "vector")
7589 (eq_attr "alternative" "1")
7590 (const_string "vector")
7591 (and (eq_attr "alternative" "2")
7592 (match_operand 1 "memory_operand" ""))
7593 (const_string "vector")]
7594 (const_string "direct")))
7595 (set (attr "amdfam10_decode")
7596 (cond [(and (eq_attr "alternative" "0,1")
7597 (match_operand 1 "memory_operand" ""))
7598 (const_string "vector")]
7599 (const_string "direct")))
7600 (set_attr "mode" "SI")])
7602 (define_expand "mulhi3"
7603 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7604 (mult:HI (match_operand:HI 1 "register_operand" "")
7605 (match_operand:HI 2 "general_operand" "")))
7606 (clobber (reg:CC FLAGS_REG))])]
7607 "TARGET_HIMODE_MATH"
7611 ;; IMUL reg16, reg16, imm8 VectorPath
7612 ;; IMUL reg16, mem16, imm8 VectorPath
7613 ;; IMUL reg16, reg16, imm16 VectorPath
7614 ;; IMUL reg16, mem16, imm16 VectorPath
7615 ;; IMUL reg16, reg16 Direct
7616 ;; IMUL reg16, mem16 Direct
7617 (define_insn "*mulhi3_1"
7618 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7619 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7620 (match_operand:HI 2 "general_operand" "K,i,mr")))
7621 (clobber (reg:CC FLAGS_REG))]
7622 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
7624 imul{w}\t{%2, %1, %0|%0, %1, %2}
7625 imul{w}\t{%2, %1, %0|%0, %1, %2}
7626 imul{w}\t{%2, %0|%0, %2}"
7627 [(set_attr "type" "imul")
7628 (set_attr "prefix_0f" "0,0,1")
7629 (set (attr "athlon_decode")
7630 (cond [(eq_attr "cpu" "athlon")
7631 (const_string "vector")
7632 (eq_attr "alternative" "1,2")
7633 (const_string "vector")]
7634 (const_string "direct")))
7635 (set (attr "amdfam10_decode")
7636 (cond [(eq_attr "alternative" "0,1")
7637 (const_string "vector")]
7638 (const_string "direct")))
7639 (set_attr "mode" "HI")])
7641 (define_expand "mulqi3"
7642 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7643 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7644 (match_operand:QI 2 "register_operand" "")))
7645 (clobber (reg:CC FLAGS_REG))])]
7646 "TARGET_QIMODE_MATH"
7653 (define_insn "*mulqi3_1"
7654 [(set (match_operand:QI 0 "register_operand" "=a")
7655 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7656 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7657 (clobber (reg:CC FLAGS_REG))]
7659 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7661 [(set_attr "type" "imul")
7662 (set_attr "length_immediate" "0")
7663 (set (attr "athlon_decode")
7664 (if_then_else (eq_attr "cpu" "athlon")
7665 (const_string "vector")
7666 (const_string "direct")))
7667 (set_attr "amdfam10_decode" "direct")
7668 (set_attr "mode" "QI")])
7670 (define_expand "umulqihi3"
7671 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7672 (mult:HI (zero_extend:HI
7673 (match_operand:QI 1 "nonimmediate_operand" ""))
7675 (match_operand:QI 2 "register_operand" ""))))
7676 (clobber (reg:CC FLAGS_REG))])]
7677 "TARGET_QIMODE_MATH"
7680 (define_insn "*umulqihi3_1"
7681 [(set (match_operand:HI 0 "register_operand" "=a")
7682 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7683 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7684 (clobber (reg:CC FLAGS_REG))]
7686 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7688 [(set_attr "type" "imul")
7689 (set_attr "length_immediate" "0")
7690 (set (attr "athlon_decode")
7691 (if_then_else (eq_attr "cpu" "athlon")
7692 (const_string "vector")
7693 (const_string "direct")))
7694 (set_attr "amdfam10_decode" "direct")
7695 (set_attr "mode" "QI")])
7697 (define_expand "mulqihi3"
7698 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7699 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7700 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7701 (clobber (reg:CC FLAGS_REG))])]
7702 "TARGET_QIMODE_MATH"
7705 (define_insn "*mulqihi3_insn"
7706 [(set (match_operand:HI 0 "register_operand" "=a")
7707 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7708 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7709 (clobber (reg:CC FLAGS_REG))]
7711 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7713 [(set_attr "type" "imul")
7714 (set_attr "length_immediate" "0")
7715 (set (attr "athlon_decode")
7716 (if_then_else (eq_attr "cpu" "athlon")
7717 (const_string "vector")
7718 (const_string "direct")))
7719 (set_attr "amdfam10_decode" "direct")
7720 (set_attr "mode" "QI")])
7722 (define_expand "umulditi3"
7723 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7724 (mult:TI (zero_extend:TI
7725 (match_operand:DI 1 "nonimmediate_operand" ""))
7727 (match_operand:DI 2 "register_operand" ""))))
7728 (clobber (reg:CC FLAGS_REG))])]
7732 (define_insn "*umulditi3_insn"
7733 [(set (match_operand:TI 0 "register_operand" "=A")
7734 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7735 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7736 (clobber (reg:CC FLAGS_REG))]
7738 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7740 [(set_attr "type" "imul")
7741 (set_attr "length_immediate" "0")
7742 (set (attr "athlon_decode")
7743 (if_then_else (eq_attr "cpu" "athlon")
7744 (const_string "vector")
7745 (const_string "double")))
7746 (set_attr "amdfam10_decode" "double")
7747 (set_attr "mode" "DI")])
7749 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7750 (define_expand "umulsidi3"
7751 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7752 (mult:DI (zero_extend:DI
7753 (match_operand:SI 1 "nonimmediate_operand" ""))
7755 (match_operand:SI 2 "register_operand" ""))))
7756 (clobber (reg:CC FLAGS_REG))])]
7760 (define_insn "*umulsidi3_insn"
7761 [(set (match_operand:DI 0 "register_operand" "=A")
7762 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7763 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7764 (clobber (reg:CC FLAGS_REG))]
7766 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7768 [(set_attr "type" "imul")
7769 (set_attr "length_immediate" "0")
7770 (set (attr "athlon_decode")
7771 (if_then_else (eq_attr "cpu" "athlon")
7772 (const_string "vector")
7773 (const_string "double")))
7774 (set_attr "amdfam10_decode" "double")
7775 (set_attr "mode" "SI")])
7777 (define_expand "mulditi3"
7778 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7779 (mult:TI (sign_extend:TI
7780 (match_operand:DI 1 "nonimmediate_operand" ""))
7782 (match_operand:DI 2 "register_operand" ""))))
7783 (clobber (reg:CC FLAGS_REG))])]
7787 (define_insn "*mulditi3_insn"
7788 [(set (match_operand:TI 0 "register_operand" "=A")
7789 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7790 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7791 (clobber (reg:CC FLAGS_REG))]
7793 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7795 [(set_attr "type" "imul")
7796 (set_attr "length_immediate" "0")
7797 (set (attr "athlon_decode")
7798 (if_then_else (eq_attr "cpu" "athlon")
7799 (const_string "vector")
7800 (const_string "double")))
7801 (set_attr "amdfam10_decode" "double")
7802 (set_attr "mode" "DI")])
7804 (define_expand "mulsidi3"
7805 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7806 (mult:DI (sign_extend:DI
7807 (match_operand:SI 1 "nonimmediate_operand" ""))
7809 (match_operand:SI 2 "register_operand" ""))))
7810 (clobber (reg:CC FLAGS_REG))])]
7814 (define_insn "*mulsidi3_insn"
7815 [(set (match_operand:DI 0 "register_operand" "=A")
7816 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7817 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7818 (clobber (reg:CC FLAGS_REG))]
7820 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7822 [(set_attr "type" "imul")
7823 (set_attr "length_immediate" "0")
7824 (set (attr "athlon_decode")
7825 (if_then_else (eq_attr "cpu" "athlon")
7826 (const_string "vector")
7827 (const_string "double")))
7828 (set_attr "amdfam10_decode" "double")
7829 (set_attr "mode" "SI")])
7831 (define_expand "umuldi3_highpart"
7832 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7835 (mult:TI (zero_extend:TI
7836 (match_operand:DI 1 "nonimmediate_operand" ""))
7838 (match_operand:DI 2 "register_operand" "")))
7840 (clobber (match_scratch:DI 3 ""))
7841 (clobber (reg:CC FLAGS_REG))])]
7845 (define_insn "*umuldi3_highpart_rex64"
7846 [(set (match_operand:DI 0 "register_operand" "=d")
7849 (mult:TI (zero_extend:TI
7850 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7852 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7854 (clobber (match_scratch:DI 3 "=1"))
7855 (clobber (reg:CC FLAGS_REG))]
7857 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7859 [(set_attr "type" "imul")
7860 (set_attr "length_immediate" "0")
7861 (set (attr "athlon_decode")
7862 (if_then_else (eq_attr "cpu" "athlon")
7863 (const_string "vector")
7864 (const_string "double")))
7865 (set_attr "amdfam10_decode" "double")
7866 (set_attr "mode" "DI")])
7868 (define_expand "umulsi3_highpart"
7869 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7872 (mult:DI (zero_extend:DI
7873 (match_operand:SI 1 "nonimmediate_operand" ""))
7875 (match_operand:SI 2 "register_operand" "")))
7877 (clobber (match_scratch:SI 3 ""))
7878 (clobber (reg:CC FLAGS_REG))])]
7882 (define_insn "*umulsi3_highpart_insn"
7883 [(set (match_operand:SI 0 "register_operand" "=d")
7886 (mult:DI (zero_extend:DI
7887 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7889 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7891 (clobber (match_scratch:SI 3 "=1"))
7892 (clobber (reg:CC FLAGS_REG))]
7893 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
7895 [(set_attr "type" "imul")
7896 (set_attr "length_immediate" "0")
7897 (set (attr "athlon_decode")
7898 (if_then_else (eq_attr "cpu" "athlon")
7899 (const_string "vector")
7900 (const_string "double")))
7901 (set_attr "amdfam10_decode" "double")
7902 (set_attr "mode" "SI")])
7904 (define_insn "*umulsi3_highpart_zext"
7905 [(set (match_operand:DI 0 "register_operand" "=d")
7906 (zero_extend:DI (truncate:SI
7908 (mult:DI (zero_extend:DI
7909 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7911 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7913 (clobber (match_scratch:SI 3 "=1"))
7914 (clobber (reg:CC FLAGS_REG))]
7916 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7918 [(set_attr "type" "imul")
7919 (set_attr "length_immediate" "0")
7920 (set (attr "athlon_decode")
7921 (if_then_else (eq_attr "cpu" "athlon")
7922 (const_string "vector")
7923 (const_string "double")))
7924 (set_attr "amdfam10_decode" "double")
7925 (set_attr "mode" "SI")])
7927 (define_expand "smuldi3_highpart"
7928 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7931 (mult:TI (sign_extend:TI
7932 (match_operand:DI 1 "nonimmediate_operand" ""))
7934 (match_operand:DI 2 "register_operand" "")))
7936 (clobber (match_scratch:DI 3 ""))
7937 (clobber (reg:CC FLAGS_REG))])]
7941 (define_insn "*smuldi3_highpart_rex64"
7942 [(set (match_operand:DI 0 "register_operand" "=d")
7945 (mult:TI (sign_extend:TI
7946 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7948 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7950 (clobber (match_scratch:DI 3 "=1"))
7951 (clobber (reg:CC FLAGS_REG))]
7953 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
7955 [(set_attr "type" "imul")
7956 (set (attr "athlon_decode")
7957 (if_then_else (eq_attr "cpu" "athlon")
7958 (const_string "vector")
7959 (const_string "double")))
7960 (set_attr "amdfam10_decode" "double")
7961 (set_attr "mode" "DI")])
7963 (define_expand "smulsi3_highpart"
7964 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7967 (mult:DI (sign_extend:DI
7968 (match_operand:SI 1 "nonimmediate_operand" ""))
7970 (match_operand:SI 2 "register_operand" "")))
7972 (clobber (match_scratch:SI 3 ""))
7973 (clobber (reg:CC FLAGS_REG))])]
7977 (define_insn "*smulsi3_highpart_insn"
7978 [(set (match_operand:SI 0 "register_operand" "=d")
7981 (mult:DI (sign_extend:DI
7982 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7984 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7986 (clobber (match_scratch:SI 3 "=1"))
7987 (clobber (reg:CC FLAGS_REG))]
7988 "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
7990 [(set_attr "type" "imul")
7991 (set (attr "athlon_decode")
7992 (if_then_else (eq_attr "cpu" "athlon")
7993 (const_string "vector")
7994 (const_string "double")))
7995 (set_attr "amdfam10_decode" "double")
7996 (set_attr "mode" "SI")])
7998 (define_insn "*smulsi3_highpart_zext"
7999 [(set (match_operand:DI 0 "register_operand" "=d")
8000 (zero_extend:DI (truncate:SI
8002 (mult:DI (sign_extend:DI
8003 (match_operand:SI 1 "nonimmediate_operand" "%a"))
8005 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8007 (clobber (match_scratch:SI 3 "=1"))
8008 (clobber (reg:CC FLAGS_REG))]
8010 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
8012 [(set_attr "type" "imul")
8013 (set (attr "athlon_decode")
8014 (if_then_else (eq_attr "cpu" "athlon")
8015 (const_string "vector")
8016 (const_string "double")))
8017 (set_attr "amdfam10_decode" "double")
8018 (set_attr "mode" "SI")])
8020 ;; The patterns that match these are at the end of this file.
8022 (define_expand "mulxf3"
8023 [(set (match_operand:XF 0 "register_operand" "")
8024 (mult:XF (match_operand:XF 1 "register_operand" "")
8025 (match_operand:XF 2 "register_operand" "")))]
8029 (define_expand "mul<mode>3"
8030 [(set (match_operand:MODEF 0 "register_operand" "")
8031 (mult:MODEF (match_operand:MODEF 1 "register_operand" "")
8032 (match_operand:MODEF 2 "nonimmediate_operand" "")))]
8033 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
8036 ;; SSE5 scalar multiply/add instructions are defined in sse.md.
8039 ;; Divide instructions
8041 (define_insn "divqi3"
8042 [(set (match_operand:QI 0 "register_operand" "=a")
8043 (div:QI (match_operand:HI 1 "register_operand" "0")
8044 (match_operand:QI 2 "nonimmediate_operand" "qm")))
8045 (clobber (reg:CC FLAGS_REG))]
8046 "TARGET_QIMODE_MATH"
8048 [(set_attr "type" "idiv")
8049 (set_attr "mode" "QI")])
8051 (define_insn "udivqi3"
8052 [(set (match_operand:QI 0 "register_operand" "=a")
8053 (udiv:QI (match_operand:HI 1 "register_operand" "0")
8054 (match_operand:QI 2 "nonimmediate_operand" "qm")))
8055 (clobber (reg:CC FLAGS_REG))]
8056 "TARGET_QIMODE_MATH"
8058 [(set_attr "type" "idiv")
8059 (set_attr "mode" "QI")])
8061 ;; The patterns that match these are at the end of this file.
8063 (define_expand "divxf3"
8064 [(set (match_operand:XF 0 "register_operand" "")
8065 (div:XF (match_operand:XF 1 "register_operand" "")
8066 (match_operand:XF 2 "register_operand" "")))]
8070 (define_expand "divdf3"
8071 [(set (match_operand:DF 0 "register_operand" "")
8072 (div:DF (match_operand:DF 1 "register_operand" "")
8073 (match_operand:DF 2 "nonimmediate_operand" "")))]
8074 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
8077 (define_expand "divsf3"
8078 [(set (match_operand:SF 0 "register_operand" "")
8079 (div:SF (match_operand:SF 1 "register_operand" "")
8080 (match_operand:SF 2 "nonimmediate_operand" "")))]
8081 "TARGET_80387 || TARGET_SSE_MATH"
8083 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
8084 && flag_finite_math_only && !flag_trapping_math
8085 && flag_unsafe_math_optimizations)
8087 ix86_emit_swdivsf (operands[0], operands[1],
8088 operands[2], SFmode);
8093 ;; Remainder instructions.
8095 (define_expand "divmoddi4"
8096 [(parallel [(set (match_operand:DI 0 "register_operand" "")
8097 (div:DI (match_operand:DI 1 "register_operand" "")
8098 (match_operand:DI 2 "nonimmediate_operand" "")))
8099 (set (match_operand:DI 3 "register_operand" "")
8100 (mod:DI (match_dup 1) (match_dup 2)))
8101 (clobber (reg:CC FLAGS_REG))])]
8105 ;; Allow to come the parameter in eax or edx to avoid extra moves.
8106 ;; Penalize eax case slightly because it results in worse scheduling
8108 (define_insn "*divmoddi4_nocltd_rex64"
8109 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
8110 (div:DI (match_operand:DI 2 "register_operand" "1,0")
8111 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
8112 (set (match_operand:DI 1 "register_operand" "=&d,&d")
8113 (mod:DI (match_dup 2) (match_dup 3)))
8114 (clobber (reg:CC FLAGS_REG))]
8115 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
8117 [(set_attr "type" "multi")])
8119 (define_insn "*divmoddi4_cltd_rex64"
8120 [(set (match_operand:DI 0 "register_operand" "=a")
8121 (div:DI (match_operand:DI 2 "register_operand" "a")
8122 (match_operand:DI 3 "nonimmediate_operand" "rm")))
8123 (set (match_operand:DI 1 "register_operand" "=&d")
8124 (mod:DI (match_dup 2) (match_dup 3)))
8125 (clobber (reg:CC FLAGS_REG))]
8126 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
8128 [(set_attr "type" "multi")])
8130 (define_insn "*divmoddi_noext_rex64"
8131 [(set (match_operand:DI 0 "register_operand" "=a")
8132 (div:DI (match_operand:DI 1 "register_operand" "0")
8133 (match_operand:DI 2 "nonimmediate_operand" "rm")))
8134 (set (match_operand:DI 3 "register_operand" "=d")
8135 (mod:DI (match_dup 1) (match_dup 2)))
8136 (use (match_operand:DI 4 "register_operand" "3"))
8137 (clobber (reg:CC FLAGS_REG))]
8140 [(set_attr "type" "idiv")
8141 (set_attr "mode" "DI")])
8144 [(set (match_operand:DI 0 "register_operand" "")
8145 (div:DI (match_operand:DI 1 "register_operand" "")
8146 (match_operand:DI 2 "nonimmediate_operand" "")))
8147 (set (match_operand:DI 3 "register_operand" "")
8148 (mod:DI (match_dup 1) (match_dup 2)))
8149 (clobber (reg:CC FLAGS_REG))]
8150 "TARGET_64BIT && reload_completed"
8151 [(parallel [(set (match_dup 3)
8152 (ashiftrt:DI (match_dup 4) (const_int 63)))
8153 (clobber (reg:CC FLAGS_REG))])
8154 (parallel [(set (match_dup 0)
8155 (div:DI (reg:DI 0) (match_dup 2)))
8157 (mod:DI (reg:DI 0) (match_dup 2)))
8159 (clobber (reg:CC FLAGS_REG))])]
8161 /* Avoid use of cltd in favor of a mov+shift. */
8162 if (!TARGET_USE_CLTD && !optimize_size)
8164 if (true_regnum (operands[1]))
8165 emit_move_insn (operands[0], operands[1]);
8167 emit_move_insn (operands[3], operands[1]);
8168 operands[4] = operands[3];
8172 gcc_assert (!true_regnum (operands[1]));
8173 operands[4] = operands[1];
8178 (define_expand "divmodsi4"
8179 [(parallel [(set (match_operand:SI 0 "register_operand" "")
8180 (div:SI (match_operand:SI 1 "register_operand" "")
8181 (match_operand:SI 2 "nonimmediate_operand" "")))
8182 (set (match_operand:SI 3 "register_operand" "")
8183 (mod:SI (match_dup 1) (match_dup 2)))
8184 (clobber (reg:CC FLAGS_REG))])]
8188 ;; Allow to come the parameter in eax or edx to avoid extra moves.
8189 ;; Penalize eax case slightly because it results in worse scheduling
8191 (define_insn "*divmodsi4_nocltd"
8192 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
8193 (div:SI (match_operand:SI 2 "register_operand" "1,0")
8194 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
8195 (set (match_operand:SI 1 "register_operand" "=&d,&d")
8196 (mod:SI (match_dup 2) (match_dup 3)))
8197 (clobber (reg:CC FLAGS_REG))]
8198 "!optimize_size && !TARGET_USE_CLTD"
8200 [(set_attr "type" "multi")])
8202 (define_insn "*divmodsi4_cltd"
8203 [(set (match_operand:SI 0 "register_operand" "=a")
8204 (div:SI (match_operand:SI 2 "register_operand" "a")
8205 (match_operand:SI 3 "nonimmediate_operand" "rm")))
8206 (set (match_operand:SI 1 "register_operand" "=&d")
8207 (mod:SI (match_dup 2) (match_dup 3)))
8208 (clobber (reg:CC FLAGS_REG))]
8209 "optimize_size || TARGET_USE_CLTD"
8211 [(set_attr "type" "multi")])
8213 (define_insn "*divmodsi_noext"
8214 [(set (match_operand:SI 0 "register_operand" "=a")
8215 (div:SI (match_operand:SI 1 "register_operand" "0")
8216 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8217 (set (match_operand:SI 3 "register_operand" "=d")
8218 (mod:SI (match_dup 1) (match_dup 2)))
8219 (use (match_operand:SI 4 "register_operand" "3"))
8220 (clobber (reg:CC FLAGS_REG))]
8223 [(set_attr "type" "idiv")
8224 (set_attr "mode" "SI")])
8227 [(set (match_operand:SI 0 "register_operand" "")
8228 (div:SI (match_operand:SI 1 "register_operand" "")
8229 (match_operand:SI 2 "nonimmediate_operand" "")))
8230 (set (match_operand:SI 3 "register_operand" "")
8231 (mod:SI (match_dup 1) (match_dup 2)))
8232 (clobber (reg:CC FLAGS_REG))]
8234 [(parallel [(set (match_dup 3)
8235 (ashiftrt:SI (match_dup 4) (const_int 31)))
8236 (clobber (reg:CC FLAGS_REG))])
8237 (parallel [(set (match_dup 0)
8238 (div:SI (reg:SI 0) (match_dup 2)))
8240 (mod:SI (reg:SI 0) (match_dup 2)))
8242 (clobber (reg:CC FLAGS_REG))])]
8244 /* Avoid use of cltd in favor of a mov+shift. */
8245 if (!TARGET_USE_CLTD && !optimize_size)
8247 if (true_regnum (operands[1]))
8248 emit_move_insn (operands[0], operands[1]);
8250 emit_move_insn (operands[3], operands[1]);
8251 operands[4] = operands[3];
8255 gcc_assert (!true_regnum (operands[1]));
8256 operands[4] = operands[1];
8260 (define_insn "divmodhi4"
8261 [(set (match_operand:HI 0 "register_operand" "=a")
8262 (div:HI (match_operand:HI 1 "register_operand" "0")
8263 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8264 (set (match_operand:HI 3 "register_operand" "=&d")
8265 (mod:HI (match_dup 1) (match_dup 2)))
8266 (clobber (reg:CC FLAGS_REG))]
8267 "TARGET_HIMODE_MATH"
8269 [(set_attr "type" "multi")
8270 (set_attr "length_immediate" "0")
8271 (set_attr "mode" "SI")])
8273 (define_insn "udivmoddi4"
8274 [(set (match_operand:DI 0 "register_operand" "=a")
8275 (udiv:DI (match_operand:DI 1 "register_operand" "0")
8276 (match_operand:DI 2 "nonimmediate_operand" "rm")))
8277 (set (match_operand:DI 3 "register_operand" "=&d")
8278 (umod:DI (match_dup 1) (match_dup 2)))
8279 (clobber (reg:CC FLAGS_REG))]
8281 "xor{q}\t%3, %3\;div{q}\t%2"
8282 [(set_attr "type" "multi")
8283 (set_attr "length_immediate" "0")
8284 (set_attr "mode" "DI")])
8286 (define_insn "*udivmoddi4_noext"
8287 [(set (match_operand:DI 0 "register_operand" "=a")
8288 (udiv:DI (match_operand:DI 1 "register_operand" "0")
8289 (match_operand:DI 2 "nonimmediate_operand" "rm")))
8290 (set (match_operand:DI 3 "register_operand" "=d")
8291 (umod:DI (match_dup 1) (match_dup 2)))
8293 (clobber (reg:CC FLAGS_REG))]
8296 [(set_attr "type" "idiv")
8297 (set_attr "mode" "DI")])
8300 [(set (match_operand:DI 0 "register_operand" "")
8301 (udiv:DI (match_operand:DI 1 "register_operand" "")
8302 (match_operand:DI 2 "nonimmediate_operand" "")))
8303 (set (match_operand:DI 3 "register_operand" "")
8304 (umod:DI (match_dup 1) (match_dup 2)))
8305 (clobber (reg:CC FLAGS_REG))]
8306 "TARGET_64BIT && reload_completed"
8307 [(set (match_dup 3) (const_int 0))
8308 (parallel [(set (match_dup 0)
8309 (udiv:DI (match_dup 1) (match_dup 2)))
8311 (umod:DI (match_dup 1) (match_dup 2)))
8313 (clobber (reg:CC FLAGS_REG))])]
8316 (define_insn "udivmodsi4"
8317 [(set (match_operand:SI 0 "register_operand" "=a")
8318 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8319 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8320 (set (match_operand:SI 3 "register_operand" "=&d")
8321 (umod:SI (match_dup 1) (match_dup 2)))
8322 (clobber (reg:CC FLAGS_REG))]
8324 "xor{l}\t%3, %3\;div{l}\t%2"
8325 [(set_attr "type" "multi")
8326 (set_attr "length_immediate" "0")
8327 (set_attr "mode" "SI")])
8329 (define_insn "*udivmodsi4_noext"
8330 [(set (match_operand:SI 0 "register_operand" "=a")
8331 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8332 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8333 (set (match_operand:SI 3 "register_operand" "=d")
8334 (umod:SI (match_dup 1) (match_dup 2)))
8336 (clobber (reg:CC FLAGS_REG))]
8339 [(set_attr "type" "idiv")
8340 (set_attr "mode" "SI")])
8343 [(set (match_operand:SI 0 "register_operand" "")
8344 (udiv:SI (match_operand:SI 1 "register_operand" "")
8345 (match_operand:SI 2 "nonimmediate_operand" "")))
8346 (set (match_operand:SI 3 "register_operand" "")
8347 (umod:SI (match_dup 1) (match_dup 2)))
8348 (clobber (reg:CC FLAGS_REG))]
8350 [(set (match_dup 3) (const_int 0))
8351 (parallel [(set (match_dup 0)
8352 (udiv:SI (match_dup 1) (match_dup 2)))
8354 (umod:SI (match_dup 1) (match_dup 2)))
8356 (clobber (reg:CC FLAGS_REG))])]
8359 (define_expand "udivmodhi4"
8360 [(set (match_dup 4) (const_int 0))
8361 (parallel [(set (match_operand:HI 0 "register_operand" "")
8362 (udiv:HI (match_operand:HI 1 "register_operand" "")
8363 (match_operand:HI 2 "nonimmediate_operand" "")))
8364 (set (match_operand:HI 3 "register_operand" "")
8365 (umod:HI (match_dup 1) (match_dup 2)))
8367 (clobber (reg:CC FLAGS_REG))])]
8368 "TARGET_HIMODE_MATH"
8369 "operands[4] = gen_reg_rtx (HImode);")
8371 (define_insn "*udivmodhi_noext"
8372 [(set (match_operand:HI 0 "register_operand" "=a")
8373 (udiv:HI (match_operand:HI 1 "register_operand" "0")
8374 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8375 (set (match_operand:HI 3 "register_operand" "=d")
8376 (umod:HI (match_dup 1) (match_dup 2)))
8377 (use (match_operand:HI 4 "register_operand" "3"))
8378 (clobber (reg:CC FLAGS_REG))]
8381 [(set_attr "type" "idiv")
8382 (set_attr "mode" "HI")])
8384 ;; We cannot use div/idiv for double division, because it causes
8385 ;; "division by zero" on the overflow and that's not what we expect
8386 ;; from truncate. Because true (non truncating) double division is
8387 ;; never generated, we can't create this insn anyway.
8390 ; [(set (match_operand:SI 0 "register_operand" "=a")
8392 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
8394 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
8395 ; (set (match_operand:SI 3 "register_operand" "=d")
8397 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
8398 ; (clobber (reg:CC FLAGS_REG))]
8400 ; "div{l}\t{%2, %0|%0, %2}"
8401 ; [(set_attr "type" "idiv")])
8403 ;;- Logical AND instructions
8405 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
8406 ;; Note that this excludes ah.
8408 (define_insn "*testdi_1_rex64"
8409 [(set (reg FLAGS_REG)
8411 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
8412 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
8414 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8415 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8417 test{l}\t{%k1, %k0|%k0, %k1}
8418 test{l}\t{%k1, %k0|%k0, %k1}
8419 test{q}\t{%1, %0|%0, %1}
8420 test{q}\t{%1, %0|%0, %1}
8421 test{q}\t{%1, %0|%0, %1}"
8422 [(set_attr "type" "test")
8423 (set_attr "modrm" "0,1,0,1,1")
8424 (set_attr "mode" "SI,SI,DI,DI,DI")
8425 (set_attr "pent_pair" "uv,np,uv,np,uv")])
8427 (define_insn "testsi_1"
8428 [(set (reg FLAGS_REG)
8430 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
8431 (match_operand:SI 1 "general_operand" "in,in,rin"))
8433 "ix86_match_ccmode (insn, CCNOmode)
8434 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8435 "test{l}\t{%1, %0|%0, %1}"
8436 [(set_attr "type" "test")
8437 (set_attr "modrm" "0,1,1")
8438 (set_attr "mode" "SI")
8439 (set_attr "pent_pair" "uv,np,uv")])
8441 (define_expand "testsi_ccno_1"
8442 [(set (reg:CCNO FLAGS_REG)
8444 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
8445 (match_operand:SI 1 "nonmemory_operand" ""))
8450 (define_insn "*testhi_1"
8451 [(set (reg FLAGS_REG)
8452 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
8453 (match_operand:HI 1 "general_operand" "n,n,rn"))
8455 "ix86_match_ccmode (insn, CCNOmode)
8456 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8457 "test{w}\t{%1, %0|%0, %1}"
8458 [(set_attr "type" "test")
8459 (set_attr "modrm" "0,1,1")
8460 (set_attr "mode" "HI")
8461 (set_attr "pent_pair" "uv,np,uv")])
8463 (define_expand "testqi_ccz_1"
8464 [(set (reg:CCZ FLAGS_REG)
8465 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8466 (match_operand:QI 1 "nonmemory_operand" ""))
8471 (define_insn "*testqi_1_maybe_si"
8472 [(set (reg FLAGS_REG)
8475 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
8476 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
8478 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
8479 && ix86_match_ccmode (insn,
8480 CONST_INT_P (operands[1])
8481 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
8483 if (which_alternative == 3)
8485 if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) < 0)
8486 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8487 return "test{l}\t{%1, %k0|%k0, %1}";
8489 return "test{b}\t{%1, %0|%0, %1}";
8491 [(set_attr "type" "test")
8492 (set_attr "modrm" "0,1,1,1")
8493 (set_attr "mode" "QI,QI,QI,SI")
8494 (set_attr "pent_pair" "uv,np,uv,np")])
8496 (define_insn "*testqi_1"
8497 [(set (reg FLAGS_REG)
8500 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
8501 (match_operand:QI 1 "general_operand" "n,n,qn"))
8503 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
8504 && ix86_match_ccmode (insn, CCNOmode)"
8505 "test{b}\t{%1, %0|%0, %1}"
8506 [(set_attr "type" "test")
8507 (set_attr "modrm" "0,1,1")
8508 (set_attr "mode" "QI")
8509 (set_attr "pent_pair" "uv,np,uv")])
8511 (define_expand "testqi_ext_ccno_0"
8512 [(set (reg:CCNO FLAGS_REG)
8516 (match_operand 0 "ext_register_operand" "")
8519 (match_operand 1 "const_int_operand" ""))
8524 (define_insn "*testqi_ext_0"
8525 [(set (reg FLAGS_REG)
8529 (match_operand 0 "ext_register_operand" "Q")
8532 (match_operand 1 "const_int_operand" "n"))
8534 "ix86_match_ccmode (insn, CCNOmode)"
8535 "test{b}\t{%1, %h0|%h0, %1}"
8536 [(set_attr "type" "test")
8537 (set_attr "mode" "QI")
8538 (set_attr "length_immediate" "1")
8539 (set_attr "pent_pair" "np")])
8541 (define_insn "*testqi_ext_1"
8542 [(set (reg FLAGS_REG)
8546 (match_operand 0 "ext_register_operand" "Q")
8550 (match_operand:QI 1 "general_operand" "Qm")))
8552 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8553 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8554 "test{b}\t{%1, %h0|%h0, %1}"
8555 [(set_attr "type" "test")
8556 (set_attr "mode" "QI")])
8558 (define_insn "*testqi_ext_1_rex64"
8559 [(set (reg FLAGS_REG)
8563 (match_operand 0 "ext_register_operand" "Q")
8567 (match_operand:QI 1 "register_operand" "Q")))
8569 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8570 "test{b}\t{%1, %h0|%h0, %1}"
8571 [(set_attr "type" "test")
8572 (set_attr "mode" "QI")])
8574 (define_insn "*testqi_ext_2"
8575 [(set (reg FLAGS_REG)
8579 (match_operand 0 "ext_register_operand" "Q")
8583 (match_operand 1 "ext_register_operand" "Q")
8587 "ix86_match_ccmode (insn, CCNOmode)"
8588 "test{b}\t{%h1, %h0|%h0, %h1}"
8589 [(set_attr "type" "test")
8590 (set_attr "mode" "QI")])
8592 ;; Combine likes to form bit extractions for some tests. Humor it.
8593 (define_insn "*testqi_ext_3"
8594 [(set (reg FLAGS_REG)
8595 (compare (zero_extract:SI
8596 (match_operand 0 "nonimmediate_operand" "rm")
8597 (match_operand:SI 1 "const_int_operand" "")
8598 (match_operand:SI 2 "const_int_operand" ""))
8600 "ix86_match_ccmode (insn, CCNOmode)
8601 && INTVAL (operands[1]) > 0
8602 && INTVAL (operands[2]) >= 0
8603 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8604 && (GET_MODE (operands[0]) == SImode
8605 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8606 || GET_MODE (operands[0]) == HImode
8607 || GET_MODE (operands[0]) == QImode)"
8610 (define_insn "*testqi_ext_3_rex64"
8611 [(set (reg FLAGS_REG)
8612 (compare (zero_extract:DI
8613 (match_operand 0 "nonimmediate_operand" "rm")
8614 (match_operand:DI 1 "const_int_operand" "")
8615 (match_operand:DI 2 "const_int_operand" ""))
8618 && ix86_match_ccmode (insn, CCNOmode)
8619 && INTVAL (operands[1]) > 0
8620 && INTVAL (operands[2]) >= 0
8621 /* Ensure that resulting mask is zero or sign extended operand. */
8622 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8623 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8624 && INTVAL (operands[1]) > 32))
8625 && (GET_MODE (operands[0]) == SImode
8626 || GET_MODE (operands[0]) == DImode
8627 || GET_MODE (operands[0]) == HImode
8628 || GET_MODE (operands[0]) == QImode)"
8632 [(set (match_operand 0 "flags_reg_operand" "")
8633 (match_operator 1 "compare_operator"
8635 (match_operand 2 "nonimmediate_operand" "")
8636 (match_operand 3 "const_int_operand" "")
8637 (match_operand 4 "const_int_operand" ""))
8639 "ix86_match_ccmode (insn, CCNOmode)"
8640 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
8642 rtx val = operands[2];
8643 HOST_WIDE_INT len = INTVAL (operands[3]);
8644 HOST_WIDE_INT pos = INTVAL (operands[4]);
8646 enum machine_mode mode, submode;
8648 mode = GET_MODE (val);
8651 /* ??? Combine likes to put non-volatile mem extractions in QImode
8652 no matter the size of the test. So find a mode that works. */
8653 if (! MEM_VOLATILE_P (val))
8655 mode = smallest_mode_for_size (pos + len, MODE_INT);
8656 val = adjust_address (val, mode, 0);
8659 else if (GET_CODE (val) == SUBREG
8660 && (submode = GET_MODE (SUBREG_REG (val)),
8661 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8662 && pos + len <= GET_MODE_BITSIZE (submode))
8664 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8666 val = SUBREG_REG (val);
8668 else if (mode == HImode && pos + len <= 8)
8670 /* Small HImode tests can be converted to QImode. */
8672 val = gen_lowpart (QImode, val);
8675 if (len == HOST_BITS_PER_WIDE_INT)
8678 mask = ((HOST_WIDE_INT)1 << len) - 1;
8681 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
8684 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8685 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8686 ;; this is relatively important trick.
8687 ;; Do the conversion only post-reload to avoid limiting of the register class
8690 [(set (match_operand 0 "flags_reg_operand" "")
8691 (match_operator 1 "compare_operator"
8692 [(and (match_operand 2 "register_operand" "")
8693 (match_operand 3 "const_int_operand" ""))
8696 && QI_REG_P (operands[2])
8697 && GET_MODE (operands[2]) != QImode
8698 && ((ix86_match_ccmode (insn, CCZmode)
8699 && !(INTVAL (operands[3]) & ~(255 << 8)))
8700 || (ix86_match_ccmode (insn, CCNOmode)
8701 && !(INTVAL (operands[3]) & ~(127 << 8))))"
8704 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
8707 "operands[2] = gen_lowpart (SImode, operands[2]);
8708 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
8711 [(set (match_operand 0 "flags_reg_operand" "")
8712 (match_operator 1 "compare_operator"
8713 [(and (match_operand 2 "nonimmediate_operand" "")
8714 (match_operand 3 "const_int_operand" ""))
8717 && GET_MODE (operands[2]) != QImode
8718 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
8719 && ((ix86_match_ccmode (insn, CCZmode)
8720 && !(INTVAL (operands[3]) & ~255))
8721 || (ix86_match_ccmode (insn, CCNOmode)
8722 && !(INTVAL (operands[3]) & ~127)))"
8724 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
8726 "operands[2] = gen_lowpart (QImode, operands[2]);
8727 operands[3] = gen_lowpart (QImode, operands[3]);")
8730 ;; %%% This used to optimize known byte-wide and operations to memory,
8731 ;; and sometimes to QImode registers. If this is considered useful,
8732 ;; it should be done with splitters.
8734 (define_expand "anddi3"
8735 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8736 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8737 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8738 (clobber (reg:CC FLAGS_REG))]
8740 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8742 (define_insn "*anddi_1_rex64"
8743 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8744 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8745 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8746 (clobber (reg:CC FLAGS_REG))]
8747 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8749 switch (get_attr_type (insn))
8753 enum machine_mode mode;
8755 gcc_assert (CONST_INT_P (operands[2]));
8756 if (INTVAL (operands[2]) == 0xff)
8760 gcc_assert (INTVAL (operands[2]) == 0xffff);
8764 operands[1] = gen_lowpart (mode, operands[1]);
8766 return "movz{bq|x}\t{%1,%0|%0, %1}";
8768 return "movz{wq|x}\t{%1,%0|%0, %1}";
8772 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8773 if (get_attr_mode (insn) == MODE_SI)
8774 return "and{l}\t{%k2, %k0|%k0, %k2}";
8776 return "and{q}\t{%2, %0|%0, %2}";
8779 [(set_attr "type" "alu,alu,alu,imovx")
8780 (set_attr "length_immediate" "*,*,*,0")
8781 (set_attr "mode" "SI,DI,DI,DI")])
8783 (define_insn "*anddi_2"
8784 [(set (reg FLAGS_REG)
8785 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8786 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8788 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8789 (and:DI (match_dup 1) (match_dup 2)))]
8790 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8791 && ix86_binary_operator_ok (AND, DImode, operands)"
8793 and{l}\t{%k2, %k0|%k0, %k2}
8794 and{q}\t{%2, %0|%0, %2}
8795 and{q}\t{%2, %0|%0, %2}"
8796 [(set_attr "type" "alu")
8797 (set_attr "mode" "SI,DI,DI")])
8799 (define_expand "andsi3"
8800 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8801 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8802 (match_operand:SI 2 "general_operand" "")))
8803 (clobber (reg:CC FLAGS_REG))]
8805 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8807 (define_insn "*andsi_1"
8808 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8809 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8810 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8811 (clobber (reg:CC FLAGS_REG))]
8812 "ix86_binary_operator_ok (AND, SImode, operands)"
8814 switch (get_attr_type (insn))
8818 enum machine_mode mode;
8820 gcc_assert (CONST_INT_P (operands[2]));
8821 if (INTVAL (operands[2]) == 0xff)
8825 gcc_assert (INTVAL (operands[2]) == 0xffff);
8829 operands[1] = gen_lowpart (mode, operands[1]);
8831 return "movz{bl|x}\t{%1,%0|%0, %1}";
8833 return "movz{wl|x}\t{%1,%0|%0, %1}";
8837 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8838 return "and{l}\t{%2, %0|%0, %2}";
8841 [(set_attr "type" "alu,alu,imovx")
8842 (set_attr "length_immediate" "*,*,0")
8843 (set_attr "mode" "SI")])
8846 [(set (match_operand 0 "register_operand" "")
8848 (const_int -65536)))
8849 (clobber (reg:CC FLAGS_REG))]
8850 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8851 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8852 "operands[1] = gen_lowpart (HImode, operands[0]);")
8855 [(set (match_operand 0 "ext_register_operand" "")
8858 (clobber (reg:CC FLAGS_REG))]
8859 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8860 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8861 "operands[1] = gen_lowpart (QImode, operands[0]);")
8864 [(set (match_operand 0 "ext_register_operand" "")
8866 (const_int -65281)))
8867 (clobber (reg:CC FLAGS_REG))]
8868 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8869 [(parallel [(set (zero_extract:SI (match_dup 0)
8873 (zero_extract:SI (match_dup 0)
8876 (zero_extract:SI (match_dup 0)
8879 (clobber (reg:CC FLAGS_REG))])]
8880 "operands[0] = gen_lowpart (SImode, operands[0]);")
8882 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8883 (define_insn "*andsi_1_zext"
8884 [(set (match_operand:DI 0 "register_operand" "=r")
8886 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8887 (match_operand:SI 2 "general_operand" "g"))))
8888 (clobber (reg:CC FLAGS_REG))]
8889 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8890 "and{l}\t{%2, %k0|%k0, %2}"
8891 [(set_attr "type" "alu")
8892 (set_attr "mode" "SI")])
8894 (define_insn "*andsi_2"
8895 [(set (reg FLAGS_REG)
8896 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8897 (match_operand:SI 2 "general_operand" "g,ri"))
8899 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8900 (and:SI (match_dup 1) (match_dup 2)))]
8901 "ix86_match_ccmode (insn, CCNOmode)
8902 && ix86_binary_operator_ok (AND, SImode, operands)"
8903 "and{l}\t{%2, %0|%0, %2}"
8904 [(set_attr "type" "alu")
8905 (set_attr "mode" "SI")])
8907 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8908 (define_insn "*andsi_2_zext"
8909 [(set (reg FLAGS_REG)
8910 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8911 (match_operand:SI 2 "general_operand" "g"))
8913 (set (match_operand:DI 0 "register_operand" "=r")
8914 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8915 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8916 && ix86_binary_operator_ok (AND, SImode, operands)"
8917 "and{l}\t{%2, %k0|%k0, %2}"
8918 [(set_attr "type" "alu")
8919 (set_attr "mode" "SI")])
8921 (define_expand "andhi3"
8922 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8923 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8924 (match_operand:HI 2 "general_operand" "")))
8925 (clobber (reg:CC FLAGS_REG))]
8926 "TARGET_HIMODE_MATH"
8927 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8929 (define_insn "*andhi_1"
8930 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8931 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8932 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8933 (clobber (reg:CC FLAGS_REG))]
8934 "ix86_binary_operator_ok (AND, HImode, operands)"
8936 switch (get_attr_type (insn))
8939 gcc_assert (CONST_INT_P (operands[2]));
8940 gcc_assert (INTVAL (operands[2]) == 0xff);
8941 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8944 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8946 return "and{w}\t{%2, %0|%0, %2}";
8949 [(set_attr "type" "alu,alu,imovx")
8950 (set_attr "length_immediate" "*,*,0")
8951 (set_attr "mode" "HI,HI,SI")])
8953 (define_insn "*andhi_2"
8954 [(set (reg FLAGS_REG)
8955 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8956 (match_operand:HI 2 "general_operand" "g,ri"))
8958 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8959 (and:HI (match_dup 1) (match_dup 2)))]
8960 "ix86_match_ccmode (insn, CCNOmode)
8961 && ix86_binary_operator_ok (AND, HImode, operands)"
8962 "and{w}\t{%2, %0|%0, %2}"
8963 [(set_attr "type" "alu")
8964 (set_attr "mode" "HI")])
8966 (define_expand "andqi3"
8967 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8968 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8969 (match_operand:QI 2 "general_operand" "")))
8970 (clobber (reg:CC FLAGS_REG))]
8971 "TARGET_QIMODE_MATH"
8972 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8974 ;; %%% Potential partial reg stall on alternative 2. What to do?
8975 (define_insn "*andqi_1"
8976 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8977 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8978 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8979 (clobber (reg:CC FLAGS_REG))]
8980 "ix86_binary_operator_ok (AND, QImode, operands)"
8982 and{b}\t{%2, %0|%0, %2}
8983 and{b}\t{%2, %0|%0, %2}
8984 and{l}\t{%k2, %k0|%k0, %k2}"
8985 [(set_attr "type" "alu")
8986 (set_attr "mode" "QI,QI,SI")])
8988 (define_insn "*andqi_1_slp"
8989 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8990 (and:QI (match_dup 0)
8991 (match_operand:QI 1 "general_operand" "qi,qmi")))
8992 (clobber (reg:CC FLAGS_REG))]
8993 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8994 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
8995 "and{b}\t{%1, %0|%0, %1}"
8996 [(set_attr "type" "alu1")
8997 (set_attr "mode" "QI")])
8999 (define_insn "*andqi_2_maybe_si"
9000 [(set (reg FLAGS_REG)
9002 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9003 (match_operand:QI 2 "general_operand" "qim,qi,i"))
9005 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
9006 (and:QI (match_dup 1) (match_dup 2)))]
9007 "ix86_binary_operator_ok (AND, QImode, operands)
9008 && ix86_match_ccmode (insn,
9009 CONST_INT_P (operands[2])
9010 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
9012 if (which_alternative == 2)
9014 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
9015 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
9016 return "and{l}\t{%2, %k0|%k0, %2}";
9018 return "and{b}\t{%2, %0|%0, %2}";
9020 [(set_attr "type" "alu")
9021 (set_attr "mode" "QI,QI,SI")])
9023 (define_insn "*andqi_2"
9024 [(set (reg FLAGS_REG)
9026 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9027 (match_operand:QI 2 "general_operand" "qim,qi"))
9029 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9030 (and:QI (match_dup 1) (match_dup 2)))]
9031 "ix86_match_ccmode (insn, CCNOmode)
9032 && ix86_binary_operator_ok (AND, QImode, operands)"
9033 "and{b}\t{%2, %0|%0, %2}"
9034 [(set_attr "type" "alu")
9035 (set_attr "mode" "QI")])
9037 (define_insn "*andqi_2_slp"
9038 [(set (reg FLAGS_REG)
9040 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9041 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
9043 (set (strict_low_part (match_dup 0))
9044 (and:QI (match_dup 0) (match_dup 1)))]
9045 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9046 && ix86_match_ccmode (insn, CCNOmode)
9047 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
9048 "and{b}\t{%1, %0|%0, %1}"
9049 [(set_attr "type" "alu1")
9050 (set_attr "mode" "QI")])
9052 ;; ??? A bug in recog prevents it from recognizing a const_int as an
9053 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
9054 ;; for a QImode operand, which of course failed.
9056 (define_insn "andqi_ext_0"
9057 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9062 (match_operand 1 "ext_register_operand" "0")
9065 (match_operand 2 "const_int_operand" "n")))
9066 (clobber (reg:CC FLAGS_REG))]
9068 "and{b}\t{%2, %h0|%h0, %2}"
9069 [(set_attr "type" "alu")
9070 (set_attr "length_immediate" "1")
9071 (set_attr "mode" "QI")])
9073 ;; Generated by peephole translating test to and. This shows up
9074 ;; often in fp comparisons.
9076 (define_insn "*andqi_ext_0_cc"
9077 [(set (reg FLAGS_REG)
9081 (match_operand 1 "ext_register_operand" "0")
9084 (match_operand 2 "const_int_operand" "n"))
9086 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9095 "ix86_match_ccmode (insn, CCNOmode)"
9096 "and{b}\t{%2, %h0|%h0, %2}"
9097 [(set_attr "type" "alu")
9098 (set_attr "length_immediate" "1")
9099 (set_attr "mode" "QI")])
9101 (define_insn "*andqi_ext_1"
9102 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9107 (match_operand 1 "ext_register_operand" "0")
9111 (match_operand:QI 2 "general_operand" "Qm"))))
9112 (clobber (reg:CC FLAGS_REG))]
9114 "and{b}\t{%2, %h0|%h0, %2}"
9115 [(set_attr "type" "alu")
9116 (set_attr "length_immediate" "0")
9117 (set_attr "mode" "QI")])
9119 (define_insn "*andqi_ext_1_rex64"
9120 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9125 (match_operand 1 "ext_register_operand" "0")
9129 (match_operand 2 "ext_register_operand" "Q"))))
9130 (clobber (reg:CC FLAGS_REG))]
9132 "and{b}\t{%2, %h0|%h0, %2}"
9133 [(set_attr "type" "alu")
9134 (set_attr "length_immediate" "0")
9135 (set_attr "mode" "QI")])
9137 (define_insn "*andqi_ext_2"
9138 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9143 (match_operand 1 "ext_register_operand" "%0")
9147 (match_operand 2 "ext_register_operand" "Q")
9150 (clobber (reg:CC FLAGS_REG))]
9152 "and{b}\t{%h2, %h0|%h0, %h2}"
9153 [(set_attr "type" "alu")
9154 (set_attr "length_immediate" "0")
9155 (set_attr "mode" "QI")])
9157 ;; Convert wide AND instructions with immediate operand to shorter QImode
9158 ;; equivalents when possible.
9159 ;; Don't do the splitting with memory operands, since it introduces risk
9160 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
9161 ;; for size, but that can (should?) be handled by generic code instead.
9163 [(set (match_operand 0 "register_operand" "")
9164 (and (match_operand 1 "register_operand" "")
9165 (match_operand 2 "const_int_operand" "")))
9166 (clobber (reg:CC FLAGS_REG))]
9168 && QI_REG_P (operands[0])
9169 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9170 && !(~INTVAL (operands[2]) & ~(255 << 8))
9171 && GET_MODE (operands[0]) != QImode"
9172 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9173 (and:SI (zero_extract:SI (match_dup 1)
9174 (const_int 8) (const_int 8))
9176 (clobber (reg:CC FLAGS_REG))])]
9177 "operands[0] = gen_lowpart (SImode, operands[0]);
9178 operands[1] = gen_lowpart (SImode, operands[1]);
9179 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9181 ;; Since AND can be encoded with sign extended immediate, this is only
9182 ;; profitable when 7th bit is not set.
9184 [(set (match_operand 0 "register_operand" "")
9185 (and (match_operand 1 "general_operand" "")
9186 (match_operand 2 "const_int_operand" "")))
9187 (clobber (reg:CC FLAGS_REG))]
9189 && ANY_QI_REG_P (operands[0])
9190 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9191 && !(~INTVAL (operands[2]) & ~255)
9192 && !(INTVAL (operands[2]) & 128)
9193 && GET_MODE (operands[0]) != QImode"
9194 [(parallel [(set (strict_low_part (match_dup 0))
9195 (and:QI (match_dup 1)
9197 (clobber (reg:CC FLAGS_REG))])]
9198 "operands[0] = gen_lowpart (QImode, operands[0]);
9199 operands[1] = gen_lowpart (QImode, operands[1]);
9200 operands[2] = gen_lowpart (QImode, operands[2]);")
9202 ;; Logical inclusive OR instructions
9204 ;; %%% This used to optimize known byte-wide and operations to memory.
9205 ;; If this is considered useful, it should be done with splitters.
9207 (define_expand "iordi3"
9208 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9209 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
9210 (match_operand:DI 2 "x86_64_general_operand" "")))
9211 (clobber (reg:CC FLAGS_REG))]
9213 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
9215 (define_insn "*iordi_1_rex64"
9216 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9217 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9218 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
9219 (clobber (reg:CC FLAGS_REG))]
9221 && ix86_binary_operator_ok (IOR, DImode, operands)"
9222 "or{q}\t{%2, %0|%0, %2}"
9223 [(set_attr "type" "alu")
9224 (set_attr "mode" "DI")])
9226 (define_insn "*iordi_2_rex64"
9227 [(set (reg FLAGS_REG)
9228 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9229 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9231 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9232 (ior:DI (match_dup 1) (match_dup 2)))]
9234 && ix86_match_ccmode (insn, CCNOmode)
9235 && ix86_binary_operator_ok (IOR, DImode, operands)"
9236 "or{q}\t{%2, %0|%0, %2}"
9237 [(set_attr "type" "alu")
9238 (set_attr "mode" "DI")])
9240 (define_insn "*iordi_3_rex64"
9241 [(set (reg FLAGS_REG)
9242 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9243 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9245 (clobber (match_scratch:DI 0 "=r"))]
9247 && ix86_match_ccmode (insn, CCNOmode)
9248 && ix86_binary_operator_ok (IOR, DImode, operands)"
9249 "or{q}\t{%2, %0|%0, %2}"
9250 [(set_attr "type" "alu")
9251 (set_attr "mode" "DI")])
9254 (define_expand "iorsi3"
9255 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9256 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
9257 (match_operand:SI 2 "general_operand" "")))
9258 (clobber (reg:CC FLAGS_REG))]
9260 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
9262 (define_insn "*iorsi_1"
9263 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9264 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9265 (match_operand:SI 2 "general_operand" "ri,g")))
9266 (clobber (reg:CC FLAGS_REG))]
9267 "ix86_binary_operator_ok (IOR, SImode, operands)"
9268 "or{l}\t{%2, %0|%0, %2}"
9269 [(set_attr "type" "alu")
9270 (set_attr "mode" "SI")])
9272 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9273 (define_insn "*iorsi_1_zext"
9274 [(set (match_operand:DI 0 "register_operand" "=r")
9276 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9277 (match_operand:SI 2 "general_operand" "g"))))
9278 (clobber (reg:CC FLAGS_REG))]
9279 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
9280 "or{l}\t{%2, %k0|%k0, %2}"
9281 [(set_attr "type" "alu")
9282 (set_attr "mode" "SI")])
9284 (define_insn "*iorsi_1_zext_imm"
9285 [(set (match_operand:DI 0 "register_operand" "=r")
9286 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9287 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9288 (clobber (reg:CC FLAGS_REG))]
9290 "or{l}\t{%2, %k0|%k0, %2}"
9291 [(set_attr "type" "alu")
9292 (set_attr "mode" "SI")])
9294 (define_insn "*iorsi_2"
9295 [(set (reg FLAGS_REG)
9296 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9297 (match_operand:SI 2 "general_operand" "g,ri"))
9299 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9300 (ior:SI (match_dup 1) (match_dup 2)))]
9301 "ix86_match_ccmode (insn, CCNOmode)
9302 && ix86_binary_operator_ok (IOR, SImode, operands)"
9303 "or{l}\t{%2, %0|%0, %2}"
9304 [(set_attr "type" "alu")
9305 (set_attr "mode" "SI")])
9307 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9308 ;; ??? Special case for immediate operand is missing - it is tricky.
9309 (define_insn "*iorsi_2_zext"
9310 [(set (reg FLAGS_REG)
9311 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9312 (match_operand:SI 2 "general_operand" "g"))
9314 (set (match_operand:DI 0 "register_operand" "=r")
9315 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
9316 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9317 && ix86_binary_operator_ok (IOR, SImode, operands)"
9318 "or{l}\t{%2, %k0|%k0, %2}"
9319 [(set_attr "type" "alu")
9320 (set_attr "mode" "SI")])
9322 (define_insn "*iorsi_2_zext_imm"
9323 [(set (reg FLAGS_REG)
9324 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9325 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9327 (set (match_operand:DI 0 "register_operand" "=r")
9328 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9329 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9330 && ix86_binary_operator_ok (IOR, SImode, operands)"
9331 "or{l}\t{%2, %k0|%k0, %2}"
9332 [(set_attr "type" "alu")
9333 (set_attr "mode" "SI")])
9335 (define_insn "*iorsi_3"
9336 [(set (reg FLAGS_REG)
9337 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9338 (match_operand:SI 2 "general_operand" "g"))
9340 (clobber (match_scratch:SI 0 "=r"))]
9341 "ix86_match_ccmode (insn, CCNOmode)
9342 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9343 "or{l}\t{%2, %0|%0, %2}"
9344 [(set_attr "type" "alu")
9345 (set_attr "mode" "SI")])
9347 (define_expand "iorhi3"
9348 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9349 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
9350 (match_operand:HI 2 "general_operand" "")))
9351 (clobber (reg:CC FLAGS_REG))]
9352 "TARGET_HIMODE_MATH"
9353 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
9355 (define_insn "*iorhi_1"
9356 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9357 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9358 (match_operand:HI 2 "general_operand" "g,ri")))
9359 (clobber (reg:CC FLAGS_REG))]
9360 "ix86_binary_operator_ok (IOR, HImode, operands)"
9361 "or{w}\t{%2, %0|%0, %2}"
9362 [(set_attr "type" "alu")
9363 (set_attr "mode" "HI")])
9365 (define_insn "*iorhi_2"
9366 [(set (reg FLAGS_REG)
9367 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9368 (match_operand:HI 2 "general_operand" "g,ri"))
9370 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9371 (ior:HI (match_dup 1) (match_dup 2)))]
9372 "ix86_match_ccmode (insn, CCNOmode)
9373 && ix86_binary_operator_ok (IOR, HImode, operands)"
9374 "or{w}\t{%2, %0|%0, %2}"
9375 [(set_attr "type" "alu")
9376 (set_attr "mode" "HI")])
9378 (define_insn "*iorhi_3"
9379 [(set (reg FLAGS_REG)
9380 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9381 (match_operand:HI 2 "general_operand" "g"))
9383 (clobber (match_scratch:HI 0 "=r"))]
9384 "ix86_match_ccmode (insn, CCNOmode)
9385 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9386 "or{w}\t{%2, %0|%0, %2}"
9387 [(set_attr "type" "alu")
9388 (set_attr "mode" "HI")])
9390 (define_expand "iorqi3"
9391 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9392 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
9393 (match_operand:QI 2 "general_operand" "")))
9394 (clobber (reg:CC FLAGS_REG))]
9395 "TARGET_QIMODE_MATH"
9396 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
9398 ;; %%% Potential partial reg stall on alternative 2. What to do?
9399 (define_insn "*iorqi_1"
9400 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9401 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9402 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9403 (clobber (reg:CC FLAGS_REG))]
9404 "ix86_binary_operator_ok (IOR, QImode, operands)"
9406 or{b}\t{%2, %0|%0, %2}
9407 or{b}\t{%2, %0|%0, %2}
9408 or{l}\t{%k2, %k0|%k0, %k2}"
9409 [(set_attr "type" "alu")
9410 (set_attr "mode" "QI,QI,SI")])
9412 (define_insn "*iorqi_1_slp"
9413 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
9414 (ior:QI (match_dup 0)
9415 (match_operand:QI 1 "general_operand" "qmi,qi")))
9416 (clobber (reg:CC FLAGS_REG))]
9417 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9418 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
9419 "or{b}\t{%1, %0|%0, %1}"
9420 [(set_attr "type" "alu1")
9421 (set_attr "mode" "QI")])
9423 (define_insn "*iorqi_2"
9424 [(set (reg FLAGS_REG)
9425 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9426 (match_operand:QI 2 "general_operand" "qim,qi"))
9428 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9429 (ior:QI (match_dup 1) (match_dup 2)))]
9430 "ix86_match_ccmode (insn, CCNOmode)
9431 && ix86_binary_operator_ok (IOR, QImode, operands)"
9432 "or{b}\t{%2, %0|%0, %2}"
9433 [(set_attr "type" "alu")
9434 (set_attr "mode" "QI")])
9436 (define_insn "*iorqi_2_slp"
9437 [(set (reg FLAGS_REG)
9438 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9439 (match_operand:QI 1 "general_operand" "qim,qi"))
9441 (set (strict_low_part (match_dup 0))
9442 (ior:QI (match_dup 0) (match_dup 1)))]
9443 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9444 && ix86_match_ccmode (insn, CCNOmode)
9445 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
9446 "or{b}\t{%1, %0|%0, %1}"
9447 [(set_attr "type" "alu1")
9448 (set_attr "mode" "QI")])
9450 (define_insn "*iorqi_3"
9451 [(set (reg FLAGS_REG)
9452 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9453 (match_operand:QI 2 "general_operand" "qim"))
9455 (clobber (match_scratch:QI 0 "=q"))]
9456 "ix86_match_ccmode (insn, CCNOmode)
9457 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9458 "or{b}\t{%2, %0|%0, %2}"
9459 [(set_attr "type" "alu")
9460 (set_attr "mode" "QI")])
9462 (define_insn "iorqi_ext_0"
9463 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9468 (match_operand 1 "ext_register_operand" "0")
9471 (match_operand 2 "const_int_operand" "n")))
9472 (clobber (reg:CC FLAGS_REG))]
9473 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9474 "or{b}\t{%2, %h0|%h0, %2}"
9475 [(set_attr "type" "alu")
9476 (set_attr "length_immediate" "1")
9477 (set_attr "mode" "QI")])
9479 (define_insn "*iorqi_ext_1"
9480 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9485 (match_operand 1 "ext_register_operand" "0")
9489 (match_operand:QI 2 "general_operand" "Qm"))))
9490 (clobber (reg:CC FLAGS_REG))]
9492 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9493 "or{b}\t{%2, %h0|%h0, %2}"
9494 [(set_attr "type" "alu")
9495 (set_attr "length_immediate" "0")
9496 (set_attr "mode" "QI")])
9498 (define_insn "*iorqi_ext_1_rex64"
9499 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9504 (match_operand 1 "ext_register_operand" "0")
9508 (match_operand 2 "ext_register_operand" "Q"))))
9509 (clobber (reg:CC FLAGS_REG))]
9511 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9512 "or{b}\t{%2, %h0|%h0, %2}"
9513 [(set_attr "type" "alu")
9514 (set_attr "length_immediate" "0")
9515 (set_attr "mode" "QI")])
9517 (define_insn "*iorqi_ext_2"
9518 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9522 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9525 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9528 (clobber (reg:CC FLAGS_REG))]
9529 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9530 "ior{b}\t{%h2, %h0|%h0, %h2}"
9531 [(set_attr "type" "alu")
9532 (set_attr "length_immediate" "0")
9533 (set_attr "mode" "QI")])
9536 [(set (match_operand 0 "register_operand" "")
9537 (ior (match_operand 1 "register_operand" "")
9538 (match_operand 2 "const_int_operand" "")))
9539 (clobber (reg:CC FLAGS_REG))]
9541 && QI_REG_P (operands[0])
9542 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9543 && !(INTVAL (operands[2]) & ~(255 << 8))
9544 && GET_MODE (operands[0]) != QImode"
9545 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9546 (ior:SI (zero_extract:SI (match_dup 1)
9547 (const_int 8) (const_int 8))
9549 (clobber (reg:CC FLAGS_REG))])]
9550 "operands[0] = gen_lowpart (SImode, operands[0]);
9551 operands[1] = gen_lowpart (SImode, operands[1]);
9552 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9554 ;; Since OR can be encoded with sign extended immediate, this is only
9555 ;; profitable when 7th bit is set.
9557 [(set (match_operand 0 "register_operand" "")
9558 (ior (match_operand 1 "general_operand" "")
9559 (match_operand 2 "const_int_operand" "")))
9560 (clobber (reg:CC FLAGS_REG))]
9562 && ANY_QI_REG_P (operands[0])
9563 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9564 && !(INTVAL (operands[2]) & ~255)
9565 && (INTVAL (operands[2]) & 128)
9566 && GET_MODE (operands[0]) != QImode"
9567 [(parallel [(set (strict_low_part (match_dup 0))
9568 (ior:QI (match_dup 1)
9570 (clobber (reg:CC FLAGS_REG))])]
9571 "operands[0] = gen_lowpart (QImode, operands[0]);
9572 operands[1] = gen_lowpart (QImode, operands[1]);
9573 operands[2] = gen_lowpart (QImode, operands[2]);")
9575 ;; Logical XOR instructions
9577 ;; %%% This used to optimize known byte-wide and operations to memory.
9578 ;; If this is considered useful, it should be done with splitters.
9580 (define_expand "xordi3"
9581 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9582 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9583 (match_operand:DI 2 "x86_64_general_operand" "")))
9584 (clobber (reg:CC FLAGS_REG))]
9586 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9588 (define_insn "*xordi_1_rex64"
9589 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9590 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9591 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9592 (clobber (reg:CC FLAGS_REG))]
9594 && ix86_binary_operator_ok (XOR, DImode, operands)"
9596 xor{q}\t{%2, %0|%0, %2}
9597 xor{q}\t{%2, %0|%0, %2}"
9598 [(set_attr "type" "alu")
9599 (set_attr "mode" "DI,DI")])
9601 (define_insn "*xordi_2_rex64"
9602 [(set (reg FLAGS_REG)
9603 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9604 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9606 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9607 (xor:DI (match_dup 1) (match_dup 2)))]
9609 && ix86_match_ccmode (insn, CCNOmode)
9610 && ix86_binary_operator_ok (XOR, DImode, operands)"
9612 xor{q}\t{%2, %0|%0, %2}
9613 xor{q}\t{%2, %0|%0, %2}"
9614 [(set_attr "type" "alu")
9615 (set_attr "mode" "DI,DI")])
9617 (define_insn "*xordi_3_rex64"
9618 [(set (reg FLAGS_REG)
9619 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9620 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9622 (clobber (match_scratch:DI 0 "=r"))]
9624 && ix86_match_ccmode (insn, CCNOmode)
9625 && ix86_binary_operator_ok (XOR, DImode, operands)"
9626 "xor{q}\t{%2, %0|%0, %2}"
9627 [(set_attr "type" "alu")
9628 (set_attr "mode" "DI")])
9630 (define_expand "xorsi3"
9631 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9632 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9633 (match_operand:SI 2 "general_operand" "")))
9634 (clobber (reg:CC FLAGS_REG))]
9636 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9638 (define_insn "*xorsi_1"
9639 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9640 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9641 (match_operand:SI 2 "general_operand" "ri,rm")))
9642 (clobber (reg:CC FLAGS_REG))]
9643 "ix86_binary_operator_ok (XOR, SImode, operands)"
9644 "xor{l}\t{%2, %0|%0, %2}"
9645 [(set_attr "type" "alu")
9646 (set_attr "mode" "SI")])
9648 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9649 ;; Add speccase for immediates
9650 (define_insn "*xorsi_1_zext"
9651 [(set (match_operand:DI 0 "register_operand" "=r")
9653 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9654 (match_operand:SI 2 "general_operand" "g"))))
9655 (clobber (reg:CC FLAGS_REG))]
9656 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9657 "xor{l}\t{%2, %k0|%k0, %2}"
9658 [(set_attr "type" "alu")
9659 (set_attr "mode" "SI")])
9661 (define_insn "*xorsi_1_zext_imm"
9662 [(set (match_operand:DI 0 "register_operand" "=r")
9663 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9664 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9665 (clobber (reg:CC FLAGS_REG))]
9666 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9667 "xor{l}\t{%2, %k0|%k0, %2}"
9668 [(set_attr "type" "alu")
9669 (set_attr "mode" "SI")])
9671 (define_insn "*xorsi_2"
9672 [(set (reg FLAGS_REG)
9673 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9674 (match_operand:SI 2 "general_operand" "g,ri"))
9676 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9677 (xor:SI (match_dup 1) (match_dup 2)))]
9678 "ix86_match_ccmode (insn, CCNOmode)
9679 && ix86_binary_operator_ok (XOR, SImode, operands)"
9680 "xor{l}\t{%2, %0|%0, %2}"
9681 [(set_attr "type" "alu")
9682 (set_attr "mode" "SI")])
9684 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9685 ;; ??? Special case for immediate operand is missing - it is tricky.
9686 (define_insn "*xorsi_2_zext"
9687 [(set (reg FLAGS_REG)
9688 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9689 (match_operand:SI 2 "general_operand" "g"))
9691 (set (match_operand:DI 0 "register_operand" "=r")
9692 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9693 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9694 && ix86_binary_operator_ok (XOR, SImode, operands)"
9695 "xor{l}\t{%2, %k0|%k0, %2}"
9696 [(set_attr "type" "alu")
9697 (set_attr "mode" "SI")])
9699 (define_insn "*xorsi_2_zext_imm"
9700 [(set (reg FLAGS_REG)
9701 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9702 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9704 (set (match_operand:DI 0 "register_operand" "=r")
9705 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9706 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9707 && ix86_binary_operator_ok (XOR, SImode, operands)"
9708 "xor{l}\t{%2, %k0|%k0, %2}"
9709 [(set_attr "type" "alu")
9710 (set_attr "mode" "SI")])
9712 (define_insn "*xorsi_3"
9713 [(set (reg FLAGS_REG)
9714 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9715 (match_operand:SI 2 "general_operand" "g"))
9717 (clobber (match_scratch:SI 0 "=r"))]
9718 "ix86_match_ccmode (insn, CCNOmode)
9719 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9720 "xor{l}\t{%2, %0|%0, %2}"
9721 [(set_attr "type" "alu")
9722 (set_attr "mode" "SI")])
9724 (define_expand "xorhi3"
9725 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9726 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9727 (match_operand:HI 2 "general_operand" "")))
9728 (clobber (reg:CC FLAGS_REG))]
9729 "TARGET_HIMODE_MATH"
9730 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9732 (define_insn "*xorhi_1"
9733 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9734 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9735 (match_operand:HI 2 "general_operand" "g,ri")))
9736 (clobber (reg:CC FLAGS_REG))]
9737 "ix86_binary_operator_ok (XOR, HImode, operands)"
9738 "xor{w}\t{%2, %0|%0, %2}"
9739 [(set_attr "type" "alu")
9740 (set_attr "mode" "HI")])
9742 (define_insn "*xorhi_2"
9743 [(set (reg FLAGS_REG)
9744 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9745 (match_operand:HI 2 "general_operand" "g,ri"))
9747 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9748 (xor:HI (match_dup 1) (match_dup 2)))]
9749 "ix86_match_ccmode (insn, CCNOmode)
9750 && ix86_binary_operator_ok (XOR, HImode, operands)"
9751 "xor{w}\t{%2, %0|%0, %2}"
9752 [(set_attr "type" "alu")
9753 (set_attr "mode" "HI")])
9755 (define_insn "*xorhi_3"
9756 [(set (reg FLAGS_REG)
9757 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9758 (match_operand:HI 2 "general_operand" "g"))
9760 (clobber (match_scratch:HI 0 "=r"))]
9761 "ix86_match_ccmode (insn, CCNOmode)
9762 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9763 "xor{w}\t{%2, %0|%0, %2}"
9764 [(set_attr "type" "alu")
9765 (set_attr "mode" "HI")])
9767 (define_expand "xorqi3"
9768 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9769 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9770 (match_operand:QI 2 "general_operand" "")))
9771 (clobber (reg:CC FLAGS_REG))]
9772 "TARGET_QIMODE_MATH"
9773 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9775 ;; %%% Potential partial reg stall on alternative 2. What to do?
9776 (define_insn "*xorqi_1"
9777 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9778 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9779 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9780 (clobber (reg:CC FLAGS_REG))]
9781 "ix86_binary_operator_ok (XOR, QImode, operands)"
9783 xor{b}\t{%2, %0|%0, %2}
9784 xor{b}\t{%2, %0|%0, %2}
9785 xor{l}\t{%k2, %k0|%k0, %k2}"
9786 [(set_attr "type" "alu")
9787 (set_attr "mode" "QI,QI,SI")])
9789 (define_insn "*xorqi_1_slp"
9790 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9791 (xor:QI (match_dup 0)
9792 (match_operand:QI 1 "general_operand" "qi,qmi")))
9793 (clobber (reg:CC FLAGS_REG))]
9794 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9795 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
9796 "xor{b}\t{%1, %0|%0, %1}"
9797 [(set_attr "type" "alu1")
9798 (set_attr "mode" "QI")])
9800 (define_insn "xorqi_ext_0"
9801 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9806 (match_operand 1 "ext_register_operand" "0")
9809 (match_operand 2 "const_int_operand" "n")))
9810 (clobber (reg:CC FLAGS_REG))]
9811 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9812 "xor{b}\t{%2, %h0|%h0, %2}"
9813 [(set_attr "type" "alu")
9814 (set_attr "length_immediate" "1")
9815 (set_attr "mode" "QI")])
9817 (define_insn "*xorqi_ext_1"
9818 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9823 (match_operand 1 "ext_register_operand" "0")
9827 (match_operand:QI 2 "general_operand" "Qm"))))
9828 (clobber (reg:CC FLAGS_REG))]
9830 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9831 "xor{b}\t{%2, %h0|%h0, %2}"
9832 [(set_attr "type" "alu")
9833 (set_attr "length_immediate" "0")
9834 (set_attr "mode" "QI")])
9836 (define_insn "*xorqi_ext_1_rex64"
9837 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9842 (match_operand 1 "ext_register_operand" "0")
9846 (match_operand 2 "ext_register_operand" "Q"))))
9847 (clobber (reg:CC FLAGS_REG))]
9849 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9850 "xor{b}\t{%2, %h0|%h0, %2}"
9851 [(set_attr "type" "alu")
9852 (set_attr "length_immediate" "0")
9853 (set_attr "mode" "QI")])
9855 (define_insn "*xorqi_ext_2"
9856 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9860 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9863 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9866 (clobber (reg:CC FLAGS_REG))]
9867 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9868 "xor{b}\t{%h2, %h0|%h0, %h2}"
9869 [(set_attr "type" "alu")
9870 (set_attr "length_immediate" "0")
9871 (set_attr "mode" "QI")])
9873 (define_insn "*xorqi_cc_1"
9874 [(set (reg FLAGS_REG)
9876 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9877 (match_operand:QI 2 "general_operand" "qim,qi"))
9879 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9880 (xor:QI (match_dup 1) (match_dup 2)))]
9881 "ix86_match_ccmode (insn, CCNOmode)
9882 && ix86_binary_operator_ok (XOR, QImode, operands)"
9883 "xor{b}\t{%2, %0|%0, %2}"
9884 [(set_attr "type" "alu")
9885 (set_attr "mode" "QI")])
9887 (define_insn "*xorqi_2_slp"
9888 [(set (reg FLAGS_REG)
9889 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9890 (match_operand:QI 1 "general_operand" "qim,qi"))
9892 (set (strict_low_part (match_dup 0))
9893 (xor:QI (match_dup 0) (match_dup 1)))]
9894 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9895 && ix86_match_ccmode (insn, CCNOmode)
9896 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
9897 "xor{b}\t{%1, %0|%0, %1}"
9898 [(set_attr "type" "alu1")
9899 (set_attr "mode" "QI")])
9901 (define_insn "*xorqi_cc_2"
9902 [(set (reg FLAGS_REG)
9904 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9905 (match_operand:QI 2 "general_operand" "qim"))
9907 (clobber (match_scratch:QI 0 "=q"))]
9908 "ix86_match_ccmode (insn, CCNOmode)
9909 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
9910 "xor{b}\t{%2, %0|%0, %2}"
9911 [(set_attr "type" "alu")
9912 (set_attr "mode" "QI")])
9914 (define_insn "*xorqi_cc_ext_1"
9915 [(set (reg FLAGS_REG)
9919 (match_operand 1 "ext_register_operand" "0")
9922 (match_operand:QI 2 "general_operand" "qmn"))
9924 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9928 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9930 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9931 "xor{b}\t{%2, %h0|%h0, %2}"
9932 [(set_attr "type" "alu")
9933 (set_attr "mode" "QI")])
9935 (define_insn "*xorqi_cc_ext_1_rex64"
9936 [(set (reg FLAGS_REG)
9940 (match_operand 1 "ext_register_operand" "0")
9943 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9945 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9949 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9951 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9952 "xor{b}\t{%2, %h0|%h0, %2}"
9953 [(set_attr "type" "alu")
9954 (set_attr "mode" "QI")])
9956 (define_expand "xorqi_cc_ext_1"
9958 (set (reg:CCNO FLAGS_REG)
9962 (match_operand 1 "ext_register_operand" "")
9965 (match_operand:QI 2 "general_operand" ""))
9967 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9971 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9977 [(set (match_operand 0 "register_operand" "")
9978 (xor (match_operand 1 "register_operand" "")
9979 (match_operand 2 "const_int_operand" "")))
9980 (clobber (reg:CC FLAGS_REG))]
9982 && QI_REG_P (operands[0])
9983 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9984 && !(INTVAL (operands[2]) & ~(255 << 8))
9985 && GET_MODE (operands[0]) != QImode"
9986 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9987 (xor:SI (zero_extract:SI (match_dup 1)
9988 (const_int 8) (const_int 8))
9990 (clobber (reg:CC FLAGS_REG))])]
9991 "operands[0] = gen_lowpart (SImode, operands[0]);
9992 operands[1] = gen_lowpart (SImode, operands[1]);
9993 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9995 ;; Since XOR can be encoded with sign extended immediate, this is only
9996 ;; profitable when 7th bit is set.
9998 [(set (match_operand 0 "register_operand" "")
9999 (xor (match_operand 1 "general_operand" "")
10000 (match_operand 2 "const_int_operand" "")))
10001 (clobber (reg:CC FLAGS_REG))]
10003 && ANY_QI_REG_P (operands[0])
10004 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
10005 && !(INTVAL (operands[2]) & ~255)
10006 && (INTVAL (operands[2]) & 128)
10007 && GET_MODE (operands[0]) != QImode"
10008 [(parallel [(set (strict_low_part (match_dup 0))
10009 (xor:QI (match_dup 1)
10011 (clobber (reg:CC FLAGS_REG))])]
10012 "operands[0] = gen_lowpart (QImode, operands[0]);
10013 operands[1] = gen_lowpart (QImode, operands[1]);
10014 operands[2] = gen_lowpart (QImode, operands[2]);")
10016 ;; Negation instructions
10018 (define_expand "negti2"
10019 [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
10020 (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
10021 (clobber (reg:CC FLAGS_REG))])]
10023 "ix86_expand_unary_operator (NEG, TImode, operands); DONE;")
10025 (define_insn "*negti2_1"
10026 [(set (match_operand:TI 0 "nonimmediate_operand" "=ro")
10027 (neg:TI (match_operand:TI 1 "nonimmediate_operand" "0")))
10028 (clobber (reg:CC FLAGS_REG))]
10030 && ix86_unary_operator_ok (NEG, TImode, operands)"
10034 [(set (match_operand:TI 0 "nonimmediate_operand" "")
10035 (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
10036 (clobber (reg:CC FLAGS_REG))]
10037 "TARGET_64BIT && reload_completed"
10039 [(set (reg:CCZ FLAGS_REG)
10040 (compare:CCZ (neg:DI (match_dup 2)) (const_int 0)))
10041 (set (match_dup 0) (neg:DI (match_dup 2)))])
10043 [(set (match_dup 1)
10044 (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
10047 (clobber (reg:CC FLAGS_REG))])
10049 [(set (match_dup 1)
10050 (neg:DI (match_dup 1)))
10051 (clobber (reg:CC FLAGS_REG))])]
10052 "split_ti (operands+1, 1, operands+2, operands+3);
10053 split_ti (operands+0, 1, operands+0, operands+1);")
10055 (define_expand "negdi2"
10056 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
10057 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
10058 (clobber (reg:CC FLAGS_REG))])]
10060 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
10062 (define_insn "*negdi2_1"
10063 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
10064 (neg:DI (match_operand:DI 1 "general_operand" "0")))
10065 (clobber (reg:CC FLAGS_REG))]
10067 && ix86_unary_operator_ok (NEG, DImode, operands)"
10071 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10072 (neg:DI (match_operand:DI 1 "general_operand" "")))
10073 (clobber (reg:CC FLAGS_REG))]
10074 "!TARGET_64BIT && reload_completed"
10076 [(set (reg:CCZ FLAGS_REG)
10077 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
10078 (set (match_dup 0) (neg:SI (match_dup 2)))])
10080 [(set (match_dup 1)
10081 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
10084 (clobber (reg:CC FLAGS_REG))])
10086 [(set (match_dup 1)
10087 (neg:SI (match_dup 1)))
10088 (clobber (reg:CC FLAGS_REG))])]
10089 "split_di (operands+1, 1, operands+2, operands+3);
10090 split_di (operands+0, 1, operands+0, operands+1);")
10092 (define_insn "*negdi2_1_rex64"
10093 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10094 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
10095 (clobber (reg:CC FLAGS_REG))]
10096 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
10098 [(set_attr "type" "negnot")
10099 (set_attr "mode" "DI")])
10101 ;; The problem with neg is that it does not perform (compare x 0),
10102 ;; it really performs (compare 0 x), which leaves us with the zero
10103 ;; flag being the only useful item.
10105 (define_insn "*negdi2_cmpz_rex64"
10106 [(set (reg:CCZ FLAGS_REG)
10107 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10109 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10110 (neg:DI (match_dup 1)))]
10111 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
10113 [(set_attr "type" "negnot")
10114 (set_attr "mode" "DI")])
10117 (define_expand "negsi2"
10118 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
10119 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
10120 (clobber (reg:CC FLAGS_REG))])]
10122 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
10124 (define_insn "*negsi2_1"
10125 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10126 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
10127 (clobber (reg:CC FLAGS_REG))]
10128 "ix86_unary_operator_ok (NEG, SImode, operands)"
10130 [(set_attr "type" "negnot")
10131 (set_attr "mode" "SI")])
10133 ;; Combine is quite creative about this pattern.
10134 (define_insn "*negsi2_1_zext"
10135 [(set (match_operand:DI 0 "register_operand" "=r")
10136 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
10139 (clobber (reg:CC FLAGS_REG))]
10140 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
10142 [(set_attr "type" "negnot")
10143 (set_attr "mode" "SI")])
10145 ;; The problem with neg is that it does not perform (compare x 0),
10146 ;; it really performs (compare 0 x), which leaves us with the zero
10147 ;; flag being the only useful item.
10149 (define_insn "*negsi2_cmpz"
10150 [(set (reg:CCZ FLAGS_REG)
10151 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10153 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10154 (neg:SI (match_dup 1)))]
10155 "ix86_unary_operator_ok (NEG, SImode, operands)"
10157 [(set_attr "type" "negnot")
10158 (set_attr "mode" "SI")])
10160 (define_insn "*negsi2_cmpz_zext"
10161 [(set (reg:CCZ FLAGS_REG)
10162 (compare:CCZ (lshiftrt:DI
10164 (match_operand:DI 1 "register_operand" "0")
10168 (set (match_operand:DI 0 "register_operand" "=r")
10169 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
10172 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
10174 [(set_attr "type" "negnot")
10175 (set_attr "mode" "SI")])
10177 (define_expand "neghi2"
10178 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
10179 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
10180 (clobber (reg:CC FLAGS_REG))])]
10181 "TARGET_HIMODE_MATH"
10182 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
10184 (define_insn "*neghi2_1"
10185 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10186 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
10187 (clobber (reg:CC FLAGS_REG))]
10188 "ix86_unary_operator_ok (NEG, HImode, operands)"
10190 [(set_attr "type" "negnot")
10191 (set_attr "mode" "HI")])
10193 (define_insn "*neghi2_cmpz"
10194 [(set (reg:CCZ FLAGS_REG)
10195 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10197 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10198 (neg:HI (match_dup 1)))]
10199 "ix86_unary_operator_ok (NEG, HImode, operands)"
10201 [(set_attr "type" "negnot")
10202 (set_attr "mode" "HI")])
10204 (define_expand "negqi2"
10205 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
10206 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
10207 (clobber (reg:CC FLAGS_REG))])]
10208 "TARGET_QIMODE_MATH"
10209 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
10211 (define_insn "*negqi2_1"
10212 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10213 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
10214 (clobber (reg:CC FLAGS_REG))]
10215 "ix86_unary_operator_ok (NEG, QImode, operands)"
10217 [(set_attr "type" "negnot")
10218 (set_attr "mode" "QI")])
10220 (define_insn "*negqi2_cmpz"
10221 [(set (reg:CCZ FLAGS_REG)
10222 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10224 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10225 (neg:QI (match_dup 1)))]
10226 "ix86_unary_operator_ok (NEG, QImode, operands)"
10228 [(set_attr "type" "negnot")
10229 (set_attr "mode" "QI")])
10231 ;; Changing of sign for FP values is doable using integer unit too.
10233 (define_expand "negsf2"
10234 [(set (match_operand:SF 0 "nonimmediate_operand" "")
10235 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
10236 "TARGET_80387 || TARGET_SSE_MATH"
10237 "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
10239 (define_expand "abssf2"
10240 [(set (match_operand:SF 0 "nonimmediate_operand" "")
10241 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
10242 "TARGET_80387 || TARGET_SSE_MATH"
10243 "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
10245 (define_insn "*absnegsf2_mixed"
10246 [(set (match_operand:SF 0 "nonimmediate_operand" "=x ,x,f,rm")
10247 (match_operator:SF 3 "absneg_operator"
10248 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0,0 ")]))
10249 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0,X,X "))
10250 (clobber (reg:CC FLAGS_REG))]
10251 "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
10252 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
10255 (define_insn "*absnegsf2_sse"
10256 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,rm")
10257 (match_operator:SF 3 "absneg_operator"
10258 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0")]))
10259 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,X"))
10260 (clobber (reg:CC FLAGS_REG))]
10262 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
10265 (define_insn "*absnegsf2_i387"
10266 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,rm")
10267 (match_operator:SF 3 "absneg_operator"
10268 [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
10269 (use (match_operand 2 "" ""))
10270 (clobber (reg:CC FLAGS_REG))]
10271 "TARGET_80387 && !TARGET_SSE_MATH
10272 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
10275 (define_expand "negdf2"
10276 [(set (match_operand:DF 0 "nonimmediate_operand" "")
10277 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
10278 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
10279 "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
10281 (define_expand "absdf2"
10282 [(set (match_operand:DF 0 "nonimmediate_operand" "")
10283 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
10284 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
10285 "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
10287 (define_insn "*absnegdf2_mixed"
10288 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,x,f,rm")
10289 (match_operator:DF 3 "absneg_operator"
10290 [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0,0")]))
10291 (use (match_operand:V2DF 2 "nonimmediate_operand" "xm,0,X,X"))
10292 (clobber (reg:CC FLAGS_REG))]
10293 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
10294 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
10297 (define_insn "*absnegdf2_sse"
10298 [(set (match_operand:DF 0 "nonimmediate_operand" "=x,x,rm")
10299 (match_operator:DF 3 "absneg_operator"
10300 [(match_operand:DF 1 "nonimmediate_operand" "0 ,x,0 ")]))
10301 (use (match_operand:V2DF 2 "nonimmediate_operand" "xm,0,X "))
10302 (clobber (reg:CC FLAGS_REG))]
10303 "TARGET_SSE2 && TARGET_SSE_MATH
10304 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
10307 (define_insn "*absnegdf2_i387"
10308 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,rm")
10309 (match_operator:DF 3 "absneg_operator"
10310 [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
10311 (use (match_operand 2 "" ""))
10312 (clobber (reg:CC FLAGS_REG))]
10313 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
10314 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
10317 (define_expand "negxf2"
10318 [(set (match_operand:XF 0 "nonimmediate_operand" "")
10319 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
10321 "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
10323 (define_expand "absxf2"
10324 [(set (match_operand:XF 0 "nonimmediate_operand" "")
10325 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
10327 "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
10329 (define_insn "*absnegxf2_i387"
10330 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,?rm")
10331 (match_operator:XF 3 "absneg_operator"
10332 [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
10333 (use (match_operand 2 "" ""))
10334 (clobber (reg:CC FLAGS_REG))]
10336 && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
10339 (define_expand "negtf2"
10340 [(set (match_operand:TF 0 "nonimmediate_operand" "")
10341 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
10343 "ix86_expand_fp_absneg_operator (NEG, TFmode, operands); DONE;")
10345 (define_expand "abstf2"
10346 [(set (match_operand:TF 0 "nonimmediate_operand" "")
10347 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "")))]
10349 "ix86_expand_fp_absneg_operator (ABS, TFmode, operands); DONE;")
10351 (define_insn "*absnegtf2_sse"
10352 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,x,m")
10353 (match_operator:TF 3 "absneg_operator"
10354 [(match_operand:TF 1 "nonimmediate_operand" "0, x,0")]))
10355 (use (match_operand:TF 2 "nonimmediate_operand" "xm,0,X"))
10356 (clobber (reg:CC FLAGS_REG))]
10358 && ix86_unary_operator_ok (GET_CODE (operands[3]), TFmode, operands)"
10361 ;; Splitters for fp abs and neg.
10364 [(set (match_operand 0 "fp_register_operand" "")
10365 (match_operator 1 "absneg_operator" [(match_dup 0)]))
10366 (use (match_operand 2 "" ""))
10367 (clobber (reg:CC FLAGS_REG))]
10369 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
10372 [(set (match_operand 0 "register_operand" "")
10373 (match_operator 3 "absneg_operator"
10374 [(match_operand 1 "register_operand" "")]))
10375 (use (match_operand 2 "nonimmediate_operand" ""))
10376 (clobber (reg:CC FLAGS_REG))]
10377 "reload_completed && SSE_REG_P (operands[0])"
10378 [(set (match_dup 0) (match_dup 3))]
10380 enum machine_mode mode = GET_MODE (operands[0]);
10381 enum machine_mode vmode = GET_MODE (operands[2]);
10384 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
10385 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
10386 if (operands_match_p (operands[0], operands[2]))
10389 operands[1] = operands[2];
10392 if (GET_CODE (operands[3]) == ABS)
10393 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
10395 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
10400 [(set (match_operand:SF 0 "register_operand" "")
10401 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
10402 (use (match_operand:V4SF 2 "" ""))
10403 (clobber (reg:CC FLAGS_REG))]
10405 [(parallel [(set (match_dup 0) (match_dup 1))
10406 (clobber (reg:CC FLAGS_REG))])]
10409 operands[0] = gen_lowpart (SImode, operands[0]);
10410 if (GET_CODE (operands[1]) == ABS)
10412 tmp = gen_int_mode (0x7fffffff, SImode);
10413 tmp = gen_rtx_AND (SImode, operands[0], tmp);
10417 tmp = gen_int_mode (0x80000000, SImode);
10418 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
10424 [(set (match_operand:DF 0 "register_operand" "")
10425 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
10426 (use (match_operand 2 "" ""))
10427 (clobber (reg:CC FLAGS_REG))]
10429 [(parallel [(set (match_dup 0) (match_dup 1))
10430 (clobber (reg:CC FLAGS_REG))])]
10435 tmp = gen_lowpart (DImode, operands[0]);
10436 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
10439 if (GET_CODE (operands[1]) == ABS)
10442 tmp = gen_rtx_NOT (DImode, tmp);
10446 operands[0] = gen_highpart (SImode, operands[0]);
10447 if (GET_CODE (operands[1]) == ABS)
10449 tmp = gen_int_mode (0x7fffffff, SImode);
10450 tmp = gen_rtx_AND (SImode, operands[0], tmp);
10454 tmp = gen_int_mode (0x80000000, SImode);
10455 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
10462 [(set (match_operand:XF 0 "register_operand" "")
10463 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
10464 (use (match_operand 2 "" ""))
10465 (clobber (reg:CC FLAGS_REG))]
10467 [(parallel [(set (match_dup 0) (match_dup 1))
10468 (clobber (reg:CC FLAGS_REG))])]
10471 operands[0] = gen_rtx_REG (SImode,
10472 true_regnum (operands[0])
10473 + (TARGET_64BIT ? 1 : 2));
10474 if (GET_CODE (operands[1]) == ABS)
10476 tmp = GEN_INT (0x7fff);
10477 tmp = gen_rtx_AND (SImode, operands[0], tmp);
10481 tmp = GEN_INT (0x8000);
10482 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
10488 [(set (match_operand 0 "memory_operand" "")
10489 (match_operator 1 "absneg_operator" [(match_dup 0)]))
10490 (use (match_operand 2 "" ""))
10491 (clobber (reg:CC FLAGS_REG))]
10493 [(parallel [(set (match_dup 0) (match_dup 1))
10494 (clobber (reg:CC FLAGS_REG))])]
10496 enum machine_mode mode = GET_MODE (operands[0]);
10497 int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
10500 operands[0] = adjust_address (operands[0], QImode, size - 1);
10501 if (GET_CODE (operands[1]) == ABS)
10503 tmp = gen_int_mode (0x7f, QImode);
10504 tmp = gen_rtx_AND (QImode, operands[0], tmp);
10508 tmp = gen_int_mode (0x80, QImode);
10509 tmp = gen_rtx_XOR (QImode, operands[0], tmp);
10514 ;; Conditionalize these after reload. If they match before reload, we
10515 ;; lose the clobber and ability to use integer instructions.
10517 (define_insn "*negsf2_1"
10518 [(set (match_operand:SF 0 "register_operand" "=f")
10519 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10520 "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
10522 [(set_attr "type" "fsgn")
10523 (set_attr "mode" "SF")])
10525 (define_insn "*negdf2_1"
10526 [(set (match_operand:DF 0 "register_operand" "=f")
10527 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10528 "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
10530 [(set_attr "type" "fsgn")
10531 (set_attr "mode" "DF")])
10533 (define_insn "*negxf2_1"
10534 [(set (match_operand:XF 0 "register_operand" "=f")
10535 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10538 [(set_attr "type" "fsgn")
10539 (set_attr "mode" "XF")])
10541 (define_insn "*abssf2_1"
10542 [(set (match_operand:SF 0 "register_operand" "=f")
10543 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10544 "TARGET_80387 && (reload_completed || !TARGET_SSE_MATH)"
10546 [(set_attr "type" "fsgn")
10547 (set_attr "mode" "SF")])
10549 (define_insn "*absdf2_1"
10550 [(set (match_operand:DF 0 "register_operand" "=f")
10551 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10552 "TARGET_80387 && (reload_completed || !(TARGET_SSE2 && TARGET_SSE_MATH))"
10554 [(set_attr "type" "fsgn")
10555 (set_attr "mode" "DF")])
10557 (define_insn "*absxf2_1"
10558 [(set (match_operand:XF 0 "register_operand" "=f")
10559 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10562 [(set_attr "type" "fsgn")
10563 (set_attr "mode" "DF")])
10565 (define_insn "*negextendsfdf2"
10566 [(set (match_operand:DF 0 "register_operand" "=f")
10567 (neg:DF (float_extend:DF
10568 (match_operand:SF 1 "register_operand" "0"))))]
10569 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
10571 [(set_attr "type" "fsgn")
10572 (set_attr "mode" "DF")])
10574 (define_insn "*negextenddfxf2"
10575 [(set (match_operand:XF 0 "register_operand" "=f")
10576 (neg:XF (float_extend:XF
10577 (match_operand:DF 1 "register_operand" "0"))))]
10580 [(set_attr "type" "fsgn")
10581 (set_attr "mode" "XF")])
10583 (define_insn "*negextendsfxf2"
10584 [(set (match_operand:XF 0 "register_operand" "=f")
10585 (neg:XF (float_extend:XF
10586 (match_operand:SF 1 "register_operand" "0"))))]
10589 [(set_attr "type" "fsgn")
10590 (set_attr "mode" "XF")])
10592 (define_insn "*absextendsfdf2"
10593 [(set (match_operand:DF 0 "register_operand" "=f")
10594 (abs:DF (float_extend:DF
10595 (match_operand:SF 1 "register_operand" "0"))))]
10596 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
10598 [(set_attr "type" "fsgn")
10599 (set_attr "mode" "DF")])
10601 (define_insn "*absextenddfxf2"
10602 [(set (match_operand:XF 0 "register_operand" "=f")
10603 (abs:XF (float_extend:XF
10604 (match_operand:DF 1 "register_operand" "0"))))]
10607 [(set_attr "type" "fsgn")
10608 (set_attr "mode" "XF")])
10610 (define_insn "*absextendsfxf2"
10611 [(set (match_operand:XF 0 "register_operand" "=f")
10612 (abs:XF (float_extend:XF
10613 (match_operand:SF 1 "register_operand" "0"))))]
10616 [(set_attr "type" "fsgn")
10617 (set_attr "mode" "XF")])
10619 ;; Copysign instructions
10621 (define_mode_iterator CSGNMODE [SF DF TF])
10622 (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
10624 (define_expand "copysign<mode>3"
10625 [(match_operand:CSGNMODE 0 "register_operand" "")
10626 (match_operand:CSGNMODE 1 "nonmemory_operand" "")
10627 (match_operand:CSGNMODE 2 "register_operand" "")]
10628 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
10629 || (TARGET_64BIT && (<MODE>mode == TFmode))"
10631 ix86_expand_copysign (operands);
10635 (define_insn_and_split "copysign<mode>3_const"
10636 [(set (match_operand:CSGNMODE 0 "register_operand" "=x")
10638 [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "xmC")
10639 (match_operand:CSGNMODE 2 "register_operand" "0")
10640 (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
10642 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
10643 || (TARGET_64BIT && (<MODE>mode == TFmode))"
10645 "&& reload_completed"
10648 ix86_split_copysign_const (operands);
10652 (define_insn "copysign<mode>3_var"
10653 [(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x")
10655 [(match_operand:CSGNMODE 2 "register_operand" "x,0,0,x,x")
10656 (match_operand:CSGNMODE 3 "register_operand" "1,1,x,1,x")
10657 (match_operand:<CSGNVMODE> 4 "nonimmediate_operand" "X,xm,xm,0,0")
10658 (match_operand:<CSGNVMODE> 5 "nonimmediate_operand" "0,xm,1,xm,1")]
10660 (clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
10661 "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
10662 || (TARGET_64BIT && (<MODE>mode == TFmode))"
10666 [(set (match_operand:CSGNMODE 0 "register_operand" "")
10668 [(match_operand:CSGNMODE 2 "register_operand" "")
10669 (match_operand:CSGNMODE 3 "register_operand" "")
10670 (match_operand:<CSGNVMODE> 4 "" "")
10671 (match_operand:<CSGNVMODE> 5 "" "")]
10673 (clobber (match_scratch:<CSGNVMODE> 1 ""))]
10674 "((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
10675 || (TARGET_64BIT && (<MODE>mode == TFmode)))
10676 && reload_completed"
10679 ix86_split_copysign_var (operands);
10683 ;; One complement instructions
10685 (define_expand "one_cmpldi2"
10686 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10687 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10689 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10691 (define_insn "*one_cmpldi2_1_rex64"
10692 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10693 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10694 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10696 [(set_attr "type" "negnot")
10697 (set_attr "mode" "DI")])
10699 (define_insn "*one_cmpldi2_2_rex64"
10700 [(set (reg FLAGS_REG)
10701 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10703 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10704 (not:DI (match_dup 1)))]
10705 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10706 && ix86_unary_operator_ok (NOT, DImode, operands)"
10708 [(set_attr "type" "alu1")
10709 (set_attr "mode" "DI")])
10712 [(set (match_operand 0 "flags_reg_operand" "")
10713 (match_operator 2 "compare_operator"
10714 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
10716 (set (match_operand:DI 1 "nonimmediate_operand" "")
10717 (not:DI (match_dup 3)))]
10718 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10719 [(parallel [(set (match_dup 0)
10721 [(xor:DI (match_dup 3) (const_int -1))
10724 (xor:DI (match_dup 3) (const_int -1)))])]
10727 (define_expand "one_cmplsi2"
10728 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10729 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10731 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10733 (define_insn "*one_cmplsi2_1"
10734 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10735 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10736 "ix86_unary_operator_ok (NOT, SImode, operands)"
10738 [(set_attr "type" "negnot")
10739 (set_attr "mode" "SI")])
10741 ;; ??? Currently never generated - xor is used instead.
10742 (define_insn "*one_cmplsi2_1_zext"
10743 [(set (match_operand:DI 0 "register_operand" "=r")
10744 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10745 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10747 [(set_attr "type" "negnot")
10748 (set_attr "mode" "SI")])
10750 (define_insn "*one_cmplsi2_2"
10751 [(set (reg FLAGS_REG)
10752 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10754 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10755 (not:SI (match_dup 1)))]
10756 "ix86_match_ccmode (insn, CCNOmode)
10757 && ix86_unary_operator_ok (NOT, SImode, operands)"
10759 [(set_attr "type" "alu1")
10760 (set_attr "mode" "SI")])
10763 [(set (match_operand 0 "flags_reg_operand" "")
10764 (match_operator 2 "compare_operator"
10765 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
10767 (set (match_operand:SI 1 "nonimmediate_operand" "")
10768 (not:SI (match_dup 3)))]
10769 "ix86_match_ccmode (insn, CCNOmode)"
10770 [(parallel [(set (match_dup 0)
10771 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10774 (xor:SI (match_dup 3) (const_int -1)))])]
10777 ;; ??? Currently never generated - xor is used instead.
10778 (define_insn "*one_cmplsi2_2_zext"
10779 [(set (reg FLAGS_REG)
10780 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10782 (set (match_operand:DI 0 "register_operand" "=r")
10783 (zero_extend:DI (not:SI (match_dup 1))))]
10784 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10785 && ix86_unary_operator_ok (NOT, SImode, operands)"
10787 [(set_attr "type" "alu1")
10788 (set_attr "mode" "SI")])
10791 [(set (match_operand 0 "flags_reg_operand" "")
10792 (match_operator 2 "compare_operator"
10793 [(not:SI (match_operand:SI 3 "register_operand" ""))
10795 (set (match_operand:DI 1 "register_operand" "")
10796 (zero_extend:DI (not:SI (match_dup 3))))]
10797 "ix86_match_ccmode (insn, CCNOmode)"
10798 [(parallel [(set (match_dup 0)
10799 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10802 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10805 (define_expand "one_cmplhi2"
10806 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10807 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10808 "TARGET_HIMODE_MATH"
10809 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10811 (define_insn "*one_cmplhi2_1"
10812 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10813 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10814 "ix86_unary_operator_ok (NOT, HImode, operands)"
10816 [(set_attr "type" "negnot")
10817 (set_attr "mode" "HI")])
10819 (define_insn "*one_cmplhi2_2"
10820 [(set (reg FLAGS_REG)
10821 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10823 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10824 (not:HI (match_dup 1)))]
10825 "ix86_match_ccmode (insn, CCNOmode)
10826 && ix86_unary_operator_ok (NEG, HImode, operands)"
10828 [(set_attr "type" "alu1")
10829 (set_attr "mode" "HI")])
10832 [(set (match_operand 0 "flags_reg_operand" "")
10833 (match_operator 2 "compare_operator"
10834 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10836 (set (match_operand:HI 1 "nonimmediate_operand" "")
10837 (not:HI (match_dup 3)))]
10838 "ix86_match_ccmode (insn, CCNOmode)"
10839 [(parallel [(set (match_dup 0)
10840 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10843 (xor:HI (match_dup 3) (const_int -1)))])]
10846 ;; %%% Potential partial reg stall on alternative 1. What to do?
10847 (define_expand "one_cmplqi2"
10848 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10849 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10850 "TARGET_QIMODE_MATH"
10851 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10853 (define_insn "*one_cmplqi2_1"
10854 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10855 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10856 "ix86_unary_operator_ok (NOT, QImode, operands)"
10860 [(set_attr "type" "negnot")
10861 (set_attr "mode" "QI,SI")])
10863 (define_insn "*one_cmplqi2_2"
10864 [(set (reg FLAGS_REG)
10865 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10867 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10868 (not:QI (match_dup 1)))]
10869 "ix86_match_ccmode (insn, CCNOmode)
10870 && ix86_unary_operator_ok (NOT, QImode, operands)"
10872 [(set_attr "type" "alu1")
10873 (set_attr "mode" "QI")])
10876 [(set (match_operand 0 "flags_reg_operand" "")
10877 (match_operator 2 "compare_operator"
10878 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10880 (set (match_operand:QI 1 "nonimmediate_operand" "")
10881 (not:QI (match_dup 3)))]
10882 "ix86_match_ccmode (insn, CCNOmode)"
10883 [(parallel [(set (match_dup 0)
10884 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10887 (xor:QI (match_dup 3) (const_int -1)))])]
10890 ;; Arithmetic shift instructions
10892 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10893 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10894 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10895 ;; from the assembler input.
10897 ;; This instruction shifts the target reg/mem as usual, but instead of
10898 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10899 ;; is a left shift double, bits are taken from the high order bits of
10900 ;; reg, else if the insn is a shift right double, bits are taken from the
10901 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10902 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10904 ;; Since sh[lr]d does not change the `reg' operand, that is done
10905 ;; separately, making all shifts emit pairs of shift double and normal
10906 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10907 ;; support a 63 bit shift, each shift where the count is in a reg expands
10908 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10910 ;; If the shift count is a constant, we need never emit more than one
10911 ;; shift pair, instead using moves and sign extension for counts greater
10914 (define_expand "ashlti3"
10915 [(parallel [(set (match_operand:TI 0 "register_operand" "")
10916 (ashift:TI (match_operand:TI 1 "register_operand" "")
10917 (match_operand:QI 2 "nonmemory_operand" "")))
10918 (clobber (reg:CC FLAGS_REG))])]
10921 if (! immediate_operand (operands[2], QImode))
10923 emit_insn (gen_ashlti3_1 (operands[0], operands[1], operands[2]));
10926 ix86_expand_binary_operator (ASHIFT, TImode, operands);
10930 (define_insn "ashlti3_1"
10931 [(set (match_operand:TI 0 "register_operand" "=r")
10932 (ashift:TI (match_operand:TI 1 "register_operand" "0")
10933 (match_operand:QI 2 "register_operand" "c")))
10934 (clobber (match_scratch:DI 3 "=&r"))
10935 (clobber (reg:CC FLAGS_REG))]
10938 [(set_attr "type" "multi")])
10940 ;; This pattern must be defined before *ashlti3_2 to prevent
10941 ;; combine pass from converting sse2_ashlti3 to *ashlti3_2.
10943 (define_insn "sse2_ashlti3"
10944 [(set (match_operand:TI 0 "register_operand" "=x")
10945 (ashift:TI (match_operand:TI 1 "register_operand" "0")
10946 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
10949 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
10950 return "pslldq\t{%2, %0|%0, %2}";
10952 [(set_attr "type" "sseishft")
10953 (set_attr "prefix_data16" "1")
10954 (set_attr "mode" "TI")])
10956 (define_insn "*ashlti3_2"
10957 [(set (match_operand:TI 0 "register_operand" "=r")
10958 (ashift:TI (match_operand:TI 1 "register_operand" "0")
10959 (match_operand:QI 2 "immediate_operand" "O")))
10960 (clobber (reg:CC FLAGS_REG))]
10963 [(set_attr "type" "multi")])
10966 [(set (match_operand:TI 0 "register_operand" "")
10967 (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
10968 (match_operand:QI 2 "register_operand" "")))
10969 (clobber (match_scratch:DI 3 ""))
10970 (clobber (reg:CC FLAGS_REG))]
10971 "TARGET_64BIT && reload_completed"
10973 "ix86_split_ashl (operands, operands[3], TImode); DONE;")
10976 [(set (match_operand:TI 0 "register_operand" "")
10977 (ashift:TI (match_operand:TI 1 "register_operand" "")
10978 (match_operand:QI 2 "immediate_operand" "")))
10979 (clobber (reg:CC FLAGS_REG))]
10980 "TARGET_64BIT && reload_completed"
10982 "ix86_split_ashl (operands, NULL_RTX, TImode); DONE;")
10984 (define_insn "x86_64_shld"
10985 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
10986 (ior:DI (ashift:DI (match_dup 0)
10987 (match_operand:QI 2 "nonmemory_operand" "J,c"))
10988 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
10989 (minus:QI (const_int 64) (match_dup 2)))))
10990 (clobber (reg:CC FLAGS_REG))]
10993 shld{q}\t{%2, %1, %0|%0, %1, %2}
10994 shld{q}\t{%s2%1, %0|%0, %1, %2}"
10995 [(set_attr "type" "ishift")
10996 (set_attr "prefix_0f" "1")
10997 (set_attr "mode" "DI")
10998 (set_attr "athlon_decode" "vector")
10999 (set_attr "amdfam10_decode" "vector")])
11001 (define_expand "x86_64_shift_adj"
11002 [(set (reg:CCZ FLAGS_REG)
11003 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11006 (set (match_operand:DI 0 "register_operand" "")
11007 (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
11008 (match_operand:DI 1 "register_operand" "")
11011 (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
11012 (match_operand:DI 3 "register_operand" "r")
11017 (define_expand "ashldi3"
11018 [(set (match_operand:DI 0 "shiftdi_operand" "")
11019 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
11020 (match_operand:QI 2 "nonmemory_operand" "")))]
11022 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
11024 (define_insn "*ashldi3_1_rex64"
11025 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
11026 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
11027 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
11028 (clobber (reg:CC FLAGS_REG))]
11029 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11031 switch (get_attr_type (insn))
11034 gcc_assert (operands[2] == const1_rtx);
11035 gcc_assert (rtx_equal_p (operands[0], operands[1]));
11036 return "add{q}\t%0, %0";
11039 gcc_assert (CONST_INT_P (operands[2]));
11040 gcc_assert ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) <= 3);
11041 operands[1] = gen_rtx_MULT (DImode, operands[1],
11042 GEN_INT (1 << INTVAL (operands[2])));
11043 return "lea{q}\t{%a1, %0|%0, %a1}";
11046 if (REG_P (operands[2]))
11047 return "sal{q}\t{%b2, %0|%0, %b2}";
11048 else if (operands[2] == const1_rtx
11049 && (TARGET_SHIFT1 || optimize_size))
11050 return "sal{q}\t%0";
11052 return "sal{q}\t{%2, %0|%0, %2}";
11055 [(set (attr "type")
11056 (cond [(eq_attr "alternative" "1")
11057 (const_string "lea")
11058 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11060 (match_operand 0 "register_operand" ""))
11061 (match_operand 2 "const1_operand" ""))
11062 (const_string "alu")
11064 (const_string "ishift")))
11065 (set_attr "mode" "DI")])
11067 ;; Convert lea to the lea pattern to avoid flags dependency.
11069 [(set (match_operand:DI 0 "register_operand" "")
11070 (ashift:DI (match_operand:DI 1 "index_register_operand" "")
11071 (match_operand:QI 2 "immediate_operand" "")))
11072 (clobber (reg:CC FLAGS_REG))]
11073 "TARGET_64BIT && reload_completed
11074 && true_regnum (operands[0]) != true_regnum (operands[1])"
11075 [(set (match_dup 0)
11076 (mult:DI (match_dup 1)
11078 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
11080 ;; This pattern can't accept a variable shift count, since shifts by
11081 ;; zero don't affect the flags. We assume that shifts by constant
11082 ;; zero are optimized away.
11083 (define_insn "*ashldi3_cmp_rex64"
11084 [(set (reg FLAGS_REG)
11086 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11087 (match_operand:QI 2 "immediate_operand" "e"))
11089 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11090 (ashift:DI (match_dup 1) (match_dup 2)))]
11093 || !TARGET_PARTIAL_FLAG_REG_STALL
11094 || (operands[2] == const1_rtx
11096 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
11097 && ix86_match_ccmode (insn, CCGOCmode)
11098 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11100 switch (get_attr_type (insn))
11103 gcc_assert (operands[2] == const1_rtx);
11104 return "add{q}\t%0, %0";
11107 if (REG_P (operands[2]))
11108 return "sal{q}\t{%b2, %0|%0, %b2}";
11109 else if (operands[2] == const1_rtx
11110 && (TARGET_SHIFT1 || optimize_size))
11111 return "sal{q}\t%0";
11113 return "sal{q}\t{%2, %0|%0, %2}";
11116 [(set (attr "type")
11117 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11119 (match_operand 0 "register_operand" ""))
11120 (match_operand 2 "const1_operand" ""))
11121 (const_string "alu")
11123 (const_string "ishift")))
11124 (set_attr "mode" "DI")])
11126 (define_insn "*ashldi3_cconly_rex64"
11127 [(set (reg FLAGS_REG)
11129 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11130 (match_operand:QI 2 "immediate_operand" "e"))
11132 (clobber (match_scratch:DI 0 "=r"))]
11135 || !TARGET_PARTIAL_FLAG_REG_STALL
11136 || (operands[2] == const1_rtx
11138 || TARGET_DOUBLE_WITH_ADD)))
11139 && ix86_match_ccmode (insn, CCGOCmode)
11140 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11142 switch (get_attr_type (insn))
11145 gcc_assert (operands[2] == const1_rtx);
11146 return "add{q}\t%0, %0";
11149 if (REG_P (operands[2]))
11150 return "sal{q}\t{%b2, %0|%0, %b2}";
11151 else if (operands[2] == const1_rtx
11152 && (TARGET_SHIFT1 || optimize_size))
11153 return "sal{q}\t%0";
11155 return "sal{q}\t{%2, %0|%0, %2}";
11158 [(set (attr "type")
11159 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11161 (match_operand 0 "register_operand" ""))
11162 (match_operand 2 "const1_operand" ""))
11163 (const_string "alu")
11165 (const_string "ishift")))
11166 (set_attr "mode" "DI")])
11168 (define_insn "*ashldi3_1"
11169 [(set (match_operand:DI 0 "register_operand" "=&r,r")
11170 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
11171 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
11172 (clobber (reg:CC FLAGS_REG))]
11175 [(set_attr "type" "multi")])
11177 ;; By default we don't ask for a scratch register, because when DImode
11178 ;; values are manipulated, registers are already at a premium. But if
11179 ;; we have one handy, we won't turn it away.
11181 [(match_scratch:SI 3 "r")
11182 (parallel [(set (match_operand:DI 0 "register_operand" "")
11183 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
11184 (match_operand:QI 2 "nonmemory_operand" "")))
11185 (clobber (reg:CC FLAGS_REG))])
11187 "!TARGET_64BIT && TARGET_CMOVE"
11189 "ix86_split_ashl (operands, operands[3], DImode); DONE;")
11192 [(set (match_operand:DI 0 "register_operand" "")
11193 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
11194 (match_operand:QI 2 "nonmemory_operand" "")))
11195 (clobber (reg:CC FLAGS_REG))]
11196 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
11197 ? epilogue_completed : reload_completed)"
11199 "ix86_split_ashl (operands, NULL_RTX, DImode); DONE;")
11201 (define_insn "x86_shld_1"
11202 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11203 (ior:SI (ashift:SI (match_dup 0)
11204 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11205 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
11206 (minus:QI (const_int 32) (match_dup 2)))))
11207 (clobber (reg:CC FLAGS_REG))]
11210 shld{l}\t{%2, %1, %0|%0, %1, %2}
11211 shld{l}\t{%s2%1, %0|%0, %1, %2}"
11212 [(set_attr "type" "ishift")
11213 (set_attr "prefix_0f" "1")
11214 (set_attr "mode" "SI")
11215 (set_attr "pent_pair" "np")
11216 (set_attr "athlon_decode" "vector")
11217 (set_attr "amdfam10_decode" "vector")])
11219 (define_expand "x86_shift_adj_1"
11220 [(set (reg:CCZ FLAGS_REG)
11221 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11224 (set (match_operand:SI 0 "register_operand" "")
11225 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
11226 (match_operand:SI 1 "register_operand" "")
11229 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
11230 (match_operand:SI 3 "register_operand" "r")
11235 (define_expand "x86_shift_adj_2"
11236 [(use (match_operand:SI 0 "register_operand" ""))
11237 (use (match_operand:SI 1 "register_operand" ""))
11238 (use (match_operand:QI 2 "register_operand" ""))]
11241 rtx label = gen_label_rtx ();
11244 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11246 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11247 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11248 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11249 gen_rtx_LABEL_REF (VOIDmode, label),
11251 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11252 JUMP_LABEL (tmp) = label;
11254 emit_move_insn (operands[0], operands[1]);
11255 ix86_expand_clear (operands[1]);
11257 emit_label (label);
11258 LABEL_NUSES (label) = 1;
11263 (define_expand "ashlsi3"
11264 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11265 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
11266 (match_operand:QI 2 "nonmemory_operand" "")))
11267 (clobber (reg:CC FLAGS_REG))]
11269 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
11271 (define_insn "*ashlsi3_1"
11272 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
11273 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
11274 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11275 (clobber (reg:CC FLAGS_REG))]
11276 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11278 switch (get_attr_type (insn))
11281 gcc_assert (operands[2] == const1_rtx);
11282 gcc_assert (rtx_equal_p (operands[0], operands[1]));
11283 return "add{l}\t%0, %0";
11289 if (REG_P (operands[2]))
11290 return "sal{l}\t{%b2, %0|%0, %b2}";
11291 else if (operands[2] == const1_rtx
11292 && (TARGET_SHIFT1 || optimize_size))
11293 return "sal{l}\t%0";
11295 return "sal{l}\t{%2, %0|%0, %2}";
11298 [(set (attr "type")
11299 (cond [(eq_attr "alternative" "1")
11300 (const_string "lea")
11301 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11303 (match_operand 0 "register_operand" ""))
11304 (match_operand 2 "const1_operand" ""))
11305 (const_string "alu")
11307 (const_string "ishift")))
11308 (set_attr "mode" "SI")])
11310 ;; Convert lea to the lea pattern to avoid flags dependency.
11312 [(set (match_operand 0 "register_operand" "")
11313 (ashift (match_operand 1 "index_register_operand" "")
11314 (match_operand:QI 2 "const_int_operand" "")))
11315 (clobber (reg:CC FLAGS_REG))]
11317 && true_regnum (operands[0]) != true_regnum (operands[1])
11318 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
11322 enum machine_mode mode = GET_MODE (operands[0]);
11324 if (GET_MODE_SIZE (mode) < 4)
11325 operands[0] = gen_lowpart (SImode, operands[0]);
11327 operands[1] = gen_lowpart (Pmode, operands[1]);
11328 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11330 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11331 if (Pmode != SImode)
11332 pat = gen_rtx_SUBREG (SImode, pat, 0);
11333 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11337 ;; Rare case of shifting RSP is handled by generating move and shift
11339 [(set (match_operand 0 "register_operand" "")
11340 (ashift (match_operand 1 "register_operand" "")
11341 (match_operand:QI 2 "const_int_operand" "")))
11342 (clobber (reg:CC FLAGS_REG))]
11344 && true_regnum (operands[0]) != true_regnum (operands[1])"
11348 emit_move_insn (operands[0], operands[1]);
11349 pat = gen_rtx_SET (VOIDmode, operands[0],
11350 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11351 operands[0], operands[2]));
11352 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11353 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11357 (define_insn "*ashlsi3_1_zext"
11358 [(set (match_operand:DI 0 "register_operand" "=r,r")
11359 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
11360 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11361 (clobber (reg:CC FLAGS_REG))]
11362 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11364 switch (get_attr_type (insn))
11367 gcc_assert (operands[2] == const1_rtx);
11368 return "add{l}\t%k0, %k0";
11374 if (REG_P (operands[2]))
11375 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11376 else if (operands[2] == const1_rtx
11377 && (TARGET_SHIFT1 || optimize_size))
11378 return "sal{l}\t%k0";
11380 return "sal{l}\t{%2, %k0|%k0, %2}";
11383 [(set (attr "type")
11384 (cond [(eq_attr "alternative" "1")
11385 (const_string "lea")
11386 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11388 (match_operand 2 "const1_operand" ""))
11389 (const_string "alu")
11391 (const_string "ishift")))
11392 (set_attr "mode" "SI")])
11394 ;; Convert lea to the lea pattern to avoid flags dependency.
11396 [(set (match_operand:DI 0 "register_operand" "")
11397 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11398 (match_operand:QI 2 "const_int_operand" ""))))
11399 (clobber (reg:CC FLAGS_REG))]
11400 "TARGET_64BIT && reload_completed
11401 && true_regnum (operands[0]) != true_regnum (operands[1])"
11402 [(set (match_dup 0) (zero_extend:DI
11403 (subreg:SI (mult:SI (match_dup 1)
11404 (match_dup 2)) 0)))]
11406 operands[1] = gen_lowpart (Pmode, operands[1]);
11407 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11410 ;; This pattern can't accept a variable shift count, since shifts by
11411 ;; zero don't affect the flags. We assume that shifts by constant
11412 ;; zero are optimized away.
11413 (define_insn "*ashlsi3_cmp"
11414 [(set (reg FLAGS_REG)
11416 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11417 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11419 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11420 (ashift:SI (match_dup 1) (match_dup 2)))]
11422 || !TARGET_PARTIAL_FLAG_REG_STALL
11423 || (operands[2] == const1_rtx
11425 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
11426 && ix86_match_ccmode (insn, CCGOCmode)
11427 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11429 switch (get_attr_type (insn))
11432 gcc_assert (operands[2] == const1_rtx);
11433 return "add{l}\t%0, %0";
11436 if (REG_P (operands[2]))
11437 return "sal{l}\t{%b2, %0|%0, %b2}";
11438 else if (operands[2] == const1_rtx
11439 && (TARGET_SHIFT1 || optimize_size))
11440 return "sal{l}\t%0";
11442 return "sal{l}\t{%2, %0|%0, %2}";
11445 [(set (attr "type")
11446 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11448 (match_operand 0 "register_operand" ""))
11449 (match_operand 2 "const1_operand" ""))
11450 (const_string "alu")
11452 (const_string "ishift")))
11453 (set_attr "mode" "SI")])
11455 (define_insn "*ashlsi3_cconly"
11456 [(set (reg FLAGS_REG)
11458 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11459 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11461 (clobber (match_scratch:SI 0 "=r"))]
11463 || !TARGET_PARTIAL_FLAG_REG_STALL
11464 || (operands[2] == const1_rtx
11466 || TARGET_DOUBLE_WITH_ADD)))
11467 && ix86_match_ccmode (insn, CCGOCmode)
11468 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11470 switch (get_attr_type (insn))
11473 gcc_assert (operands[2] == const1_rtx);
11474 return "add{l}\t%0, %0";
11477 if (REG_P (operands[2]))
11478 return "sal{l}\t{%b2, %0|%0, %b2}";
11479 else if (operands[2] == const1_rtx
11480 && (TARGET_SHIFT1 || optimize_size))
11481 return "sal{l}\t%0";
11483 return "sal{l}\t{%2, %0|%0, %2}";
11486 [(set (attr "type")
11487 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11489 (match_operand 0 "register_operand" ""))
11490 (match_operand 2 "const1_operand" ""))
11491 (const_string "alu")
11493 (const_string "ishift")))
11494 (set_attr "mode" "SI")])
11496 (define_insn "*ashlsi3_cmp_zext"
11497 [(set (reg FLAGS_REG)
11499 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11500 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11502 (set (match_operand:DI 0 "register_operand" "=r")
11503 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11506 || !TARGET_PARTIAL_FLAG_REG_STALL
11507 || (operands[2] == const1_rtx
11509 || TARGET_DOUBLE_WITH_ADD)))
11510 && ix86_match_ccmode (insn, CCGOCmode)
11511 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11513 switch (get_attr_type (insn))
11516 gcc_assert (operands[2] == const1_rtx);
11517 return "add{l}\t%k0, %k0";
11520 if (REG_P (operands[2]))
11521 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11522 else if (operands[2] == const1_rtx
11523 && (TARGET_SHIFT1 || optimize_size))
11524 return "sal{l}\t%k0";
11526 return "sal{l}\t{%2, %k0|%k0, %2}";
11529 [(set (attr "type")
11530 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11532 (match_operand 2 "const1_operand" ""))
11533 (const_string "alu")
11535 (const_string "ishift")))
11536 (set_attr "mode" "SI")])
11538 (define_expand "ashlhi3"
11539 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11540 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11541 (match_operand:QI 2 "nonmemory_operand" "")))
11542 (clobber (reg:CC FLAGS_REG))]
11543 "TARGET_HIMODE_MATH"
11544 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11546 (define_insn "*ashlhi3_1_lea"
11547 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11548 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
11549 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11550 (clobber (reg:CC FLAGS_REG))]
11551 "!TARGET_PARTIAL_REG_STALL
11552 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11554 switch (get_attr_type (insn))
11559 gcc_assert (operands[2] == const1_rtx);
11560 return "add{w}\t%0, %0";
11563 if (REG_P (operands[2]))
11564 return "sal{w}\t{%b2, %0|%0, %b2}";
11565 else if (operands[2] == const1_rtx
11566 && (TARGET_SHIFT1 || optimize_size))
11567 return "sal{w}\t%0";
11569 return "sal{w}\t{%2, %0|%0, %2}";
11572 [(set (attr "type")
11573 (cond [(eq_attr "alternative" "1")
11574 (const_string "lea")
11575 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11577 (match_operand 0 "register_operand" ""))
11578 (match_operand 2 "const1_operand" ""))
11579 (const_string "alu")
11581 (const_string "ishift")))
11582 (set_attr "mode" "HI,SI")])
11584 (define_insn "*ashlhi3_1"
11585 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11586 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11587 (match_operand:QI 2 "nonmemory_operand" "cI")))
11588 (clobber (reg:CC FLAGS_REG))]
11589 "TARGET_PARTIAL_REG_STALL
11590 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11592 switch (get_attr_type (insn))
11595 gcc_assert (operands[2] == const1_rtx);
11596 return "add{w}\t%0, %0";
11599 if (REG_P (operands[2]))
11600 return "sal{w}\t{%b2, %0|%0, %b2}";
11601 else if (operands[2] == const1_rtx
11602 && (TARGET_SHIFT1 || optimize_size))
11603 return "sal{w}\t%0";
11605 return "sal{w}\t{%2, %0|%0, %2}";
11608 [(set (attr "type")
11609 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11611 (match_operand 0 "register_operand" ""))
11612 (match_operand 2 "const1_operand" ""))
11613 (const_string "alu")
11615 (const_string "ishift")))
11616 (set_attr "mode" "HI")])
11618 ;; This pattern can't accept a variable shift count, since shifts by
11619 ;; zero don't affect the flags. We assume that shifts by constant
11620 ;; zero are optimized away.
11621 (define_insn "*ashlhi3_cmp"
11622 [(set (reg FLAGS_REG)
11624 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11625 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11627 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11628 (ashift:HI (match_dup 1) (match_dup 2)))]
11630 || !TARGET_PARTIAL_FLAG_REG_STALL
11631 || (operands[2] == const1_rtx
11633 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
11634 && ix86_match_ccmode (insn, CCGOCmode)
11635 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11637 switch (get_attr_type (insn))
11640 gcc_assert (operands[2] == const1_rtx);
11641 return "add{w}\t%0, %0";
11644 if (REG_P (operands[2]))
11645 return "sal{w}\t{%b2, %0|%0, %b2}";
11646 else if (operands[2] == const1_rtx
11647 && (TARGET_SHIFT1 || optimize_size))
11648 return "sal{w}\t%0";
11650 return "sal{w}\t{%2, %0|%0, %2}";
11653 [(set (attr "type")
11654 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11656 (match_operand 0 "register_operand" ""))
11657 (match_operand 2 "const1_operand" ""))
11658 (const_string "alu")
11660 (const_string "ishift")))
11661 (set_attr "mode" "HI")])
11663 (define_insn "*ashlhi3_cconly"
11664 [(set (reg FLAGS_REG)
11666 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11667 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11669 (clobber (match_scratch:HI 0 "=r"))]
11671 || !TARGET_PARTIAL_FLAG_REG_STALL
11672 || (operands[2] == const1_rtx
11674 || TARGET_DOUBLE_WITH_ADD)))
11675 && ix86_match_ccmode (insn, CCGOCmode)
11676 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11678 switch (get_attr_type (insn))
11681 gcc_assert (operands[2] == const1_rtx);
11682 return "add{w}\t%0, %0";
11685 if (REG_P (operands[2]))
11686 return "sal{w}\t{%b2, %0|%0, %b2}";
11687 else if (operands[2] == const1_rtx
11688 && (TARGET_SHIFT1 || optimize_size))
11689 return "sal{w}\t%0";
11691 return "sal{w}\t{%2, %0|%0, %2}";
11694 [(set (attr "type")
11695 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11697 (match_operand 0 "register_operand" ""))
11698 (match_operand 2 "const1_operand" ""))
11699 (const_string "alu")
11701 (const_string "ishift")))
11702 (set_attr "mode" "HI")])
11704 (define_expand "ashlqi3"
11705 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11706 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11707 (match_operand:QI 2 "nonmemory_operand" "")))
11708 (clobber (reg:CC FLAGS_REG))]
11709 "TARGET_QIMODE_MATH"
11710 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11712 ;; %%% Potential partial reg stall on alternative 2. What to do?
11714 (define_insn "*ashlqi3_1_lea"
11715 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11716 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
11717 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11718 (clobber (reg:CC FLAGS_REG))]
11719 "!TARGET_PARTIAL_REG_STALL
11720 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11722 switch (get_attr_type (insn))
11727 gcc_assert (operands[2] == const1_rtx);
11728 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11729 return "add{l}\t%k0, %k0";
11731 return "add{b}\t%0, %0";
11734 if (REG_P (operands[2]))
11736 if (get_attr_mode (insn) == MODE_SI)
11737 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11739 return "sal{b}\t{%b2, %0|%0, %b2}";
11741 else if (operands[2] == const1_rtx
11742 && (TARGET_SHIFT1 || optimize_size))
11744 if (get_attr_mode (insn) == MODE_SI)
11745 return "sal{l}\t%0";
11747 return "sal{b}\t%0";
11751 if (get_attr_mode (insn) == MODE_SI)
11752 return "sal{l}\t{%2, %k0|%k0, %2}";
11754 return "sal{b}\t{%2, %0|%0, %2}";
11758 [(set (attr "type")
11759 (cond [(eq_attr "alternative" "2")
11760 (const_string "lea")
11761 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11763 (match_operand 0 "register_operand" ""))
11764 (match_operand 2 "const1_operand" ""))
11765 (const_string "alu")
11767 (const_string "ishift")))
11768 (set_attr "mode" "QI,SI,SI")])
11770 (define_insn "*ashlqi3_1"
11771 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11772 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11773 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11774 (clobber (reg:CC FLAGS_REG))]
11775 "TARGET_PARTIAL_REG_STALL
11776 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11778 switch (get_attr_type (insn))
11781 gcc_assert (operands[2] == const1_rtx);
11782 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11783 return "add{l}\t%k0, %k0";
11785 return "add{b}\t%0, %0";
11788 if (REG_P (operands[2]))
11790 if (get_attr_mode (insn) == MODE_SI)
11791 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11793 return "sal{b}\t{%b2, %0|%0, %b2}";
11795 else if (operands[2] == const1_rtx
11796 && (TARGET_SHIFT1 || optimize_size))
11798 if (get_attr_mode (insn) == MODE_SI)
11799 return "sal{l}\t%0";
11801 return "sal{b}\t%0";
11805 if (get_attr_mode (insn) == MODE_SI)
11806 return "sal{l}\t{%2, %k0|%k0, %2}";
11808 return "sal{b}\t{%2, %0|%0, %2}";
11812 [(set (attr "type")
11813 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11815 (match_operand 0 "register_operand" ""))
11816 (match_operand 2 "const1_operand" ""))
11817 (const_string "alu")
11819 (const_string "ishift")))
11820 (set_attr "mode" "QI,SI")])
11822 ;; This pattern can't accept a variable shift count, since shifts by
11823 ;; zero don't affect the flags. We assume that shifts by constant
11824 ;; zero are optimized away.
11825 (define_insn "*ashlqi3_cmp"
11826 [(set (reg FLAGS_REG)
11828 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11829 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11831 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11832 (ashift:QI (match_dup 1) (match_dup 2)))]
11834 || !TARGET_PARTIAL_FLAG_REG_STALL
11835 || (operands[2] == const1_rtx
11837 || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
11838 && ix86_match_ccmode (insn, CCGOCmode)
11839 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11841 switch (get_attr_type (insn))
11844 gcc_assert (operands[2] == const1_rtx);
11845 return "add{b}\t%0, %0";
11848 if (REG_P (operands[2]))
11849 return "sal{b}\t{%b2, %0|%0, %b2}";
11850 else if (operands[2] == const1_rtx
11851 && (TARGET_SHIFT1 || optimize_size))
11852 return "sal{b}\t%0";
11854 return "sal{b}\t{%2, %0|%0, %2}";
11857 [(set (attr "type")
11858 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11860 (match_operand 0 "register_operand" ""))
11861 (match_operand 2 "const1_operand" ""))
11862 (const_string "alu")
11864 (const_string "ishift")))
11865 (set_attr "mode" "QI")])
11867 (define_insn "*ashlqi3_cconly"
11868 [(set (reg FLAGS_REG)
11870 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11871 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11873 (clobber (match_scratch:QI 0 "=q"))]
11875 || !TARGET_PARTIAL_FLAG_REG_STALL
11876 || (operands[2] == const1_rtx
11878 || TARGET_DOUBLE_WITH_ADD)))
11879 && ix86_match_ccmode (insn, CCGOCmode)
11880 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11882 switch (get_attr_type (insn))
11885 gcc_assert (operands[2] == const1_rtx);
11886 return "add{b}\t%0, %0";
11889 if (REG_P (operands[2]))
11890 return "sal{b}\t{%b2, %0|%0, %b2}";
11891 else if (operands[2] == const1_rtx
11892 && (TARGET_SHIFT1 || optimize_size))
11893 return "sal{b}\t%0";
11895 return "sal{b}\t{%2, %0|%0, %2}";
11898 [(set (attr "type")
11899 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11901 (match_operand 0 "register_operand" ""))
11902 (match_operand 2 "const1_operand" ""))
11903 (const_string "alu")
11905 (const_string "ishift")))
11906 (set_attr "mode" "QI")])
11908 ;; See comment above `ashldi3' about how this works.
11910 (define_expand "ashrti3"
11911 [(parallel [(set (match_operand:TI 0 "register_operand" "")
11912 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
11913 (match_operand:QI 2 "nonmemory_operand" "")))
11914 (clobber (reg:CC FLAGS_REG))])]
11917 if (! immediate_operand (operands[2], QImode))
11919 emit_insn (gen_ashrti3_1 (operands[0], operands[1], operands[2]));
11922 ix86_expand_binary_operator (ASHIFTRT, TImode, operands);
11926 (define_insn "ashrti3_1"
11927 [(set (match_operand:TI 0 "register_operand" "=r")
11928 (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
11929 (match_operand:QI 2 "register_operand" "c")))
11930 (clobber (match_scratch:DI 3 "=&r"))
11931 (clobber (reg:CC FLAGS_REG))]
11934 [(set_attr "type" "multi")])
11936 (define_insn "*ashrti3_2"
11937 [(set (match_operand:TI 0 "register_operand" "=r")
11938 (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
11939 (match_operand:QI 2 "immediate_operand" "O")))
11940 (clobber (reg:CC FLAGS_REG))]
11943 [(set_attr "type" "multi")])
11946 [(set (match_operand:TI 0 "register_operand" "")
11947 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
11948 (match_operand:QI 2 "register_operand" "")))
11949 (clobber (match_scratch:DI 3 ""))
11950 (clobber (reg:CC FLAGS_REG))]
11951 "TARGET_64BIT && reload_completed"
11953 "ix86_split_ashr (operands, operands[3], TImode); DONE;")
11956 [(set (match_operand:TI 0 "register_operand" "")
11957 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
11958 (match_operand:QI 2 "immediate_operand" "")))
11959 (clobber (reg:CC FLAGS_REG))]
11960 "TARGET_64BIT && reload_completed"
11962 "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
11964 (define_insn "x86_64_shrd"
11965 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
11966 (ior:DI (ashiftrt:DI (match_dup 0)
11967 (match_operand:QI 2 "nonmemory_operand" "J,c"))
11968 (ashift:DI (match_operand:DI 1 "register_operand" "r,r")
11969 (minus:QI (const_int 64) (match_dup 2)))))
11970 (clobber (reg:CC FLAGS_REG))]
11973 shrd{q}\t{%2, %1, %0|%0, %1, %2}
11974 shrd{q}\t{%s2%1, %0|%0, %1, %2}"
11975 [(set_attr "type" "ishift")
11976 (set_attr "prefix_0f" "1")
11977 (set_attr "mode" "DI")
11978 (set_attr "athlon_decode" "vector")
11979 (set_attr "amdfam10_decode" "vector")])
11981 (define_expand "ashrdi3"
11982 [(set (match_operand:DI 0 "shiftdi_operand" "")
11983 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11984 (match_operand:QI 2 "nonmemory_operand" "")))]
11986 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
11988 (define_insn "*ashrdi3_63_rex64"
11989 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11990 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11991 (match_operand:DI 2 "const_int_operand" "i,i")))
11992 (clobber (reg:CC FLAGS_REG))]
11993 "TARGET_64BIT && INTVAL (operands[2]) == 63
11994 && (TARGET_USE_CLTD || optimize_size)
11995 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11998 sar{q}\t{%2, %0|%0, %2}"
11999 [(set_attr "type" "imovx,ishift")
12000 (set_attr "prefix_0f" "0,*")
12001 (set_attr "length_immediate" "0,*")
12002 (set_attr "modrm" "0,1")
12003 (set_attr "mode" "DI")])
12005 (define_insn "*ashrdi3_1_one_bit_rex64"
12006 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12007 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12008 (match_operand:QI 2 "const1_operand" "")))
12009 (clobber (reg:CC FLAGS_REG))]
12011 && (TARGET_SHIFT1 || optimize_size)
12012 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12014 [(set_attr "type" "ishift")
12015 (set (attr "length")
12016 (if_then_else (match_operand:DI 0 "register_operand" "")
12018 (const_string "*")))])
12020 (define_insn "*ashrdi3_1_rex64"
12021 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12022 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12023 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12024 (clobber (reg:CC FLAGS_REG))]
12025 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12027 sar{q}\t{%2, %0|%0, %2}
12028 sar{q}\t{%b2, %0|%0, %b2}"
12029 [(set_attr "type" "ishift")
12030 (set_attr "mode" "DI")])
12032 ;; This pattern can't accept a variable shift count, since shifts by
12033 ;; zero don't affect the flags. We assume that shifts by constant
12034 ;; zero are optimized away.
12035 (define_insn "*ashrdi3_one_bit_cmp_rex64"
12036 [(set (reg FLAGS_REG)
12038 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12039 (match_operand:QI 2 "const1_operand" ""))
12041 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12042 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
12044 && (TARGET_SHIFT1 || optimize_size)
12045 && ix86_match_ccmode (insn, CCGOCmode)
12046 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12048 [(set_attr "type" "ishift")
12049 (set (attr "length")
12050 (if_then_else (match_operand:DI 0 "register_operand" "")
12052 (const_string "*")))])
12054 (define_insn "*ashrdi3_one_bit_cconly_rex64"
12055 [(set (reg FLAGS_REG)
12057 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12058 (match_operand:QI 2 "const1_operand" ""))
12060 (clobber (match_scratch:DI 0 "=r"))]
12062 && (TARGET_SHIFT1 || optimize_size)
12063 && ix86_match_ccmode (insn, CCGOCmode)
12064 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12066 [(set_attr "type" "ishift")
12067 (set_attr "length" "2")])
12069 ;; This pattern can't accept a variable shift count, since shifts by
12070 ;; zero don't affect the flags. We assume that shifts by constant
12071 ;; zero are optimized away.
12072 (define_insn "*ashrdi3_cmp_rex64"
12073 [(set (reg FLAGS_REG)
12075 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12076 (match_operand:QI 2 "const_int_operand" "n"))
12078 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12079 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
12081 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12082 && ix86_match_ccmode (insn, CCGOCmode)
12083 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12084 "sar{q}\t{%2, %0|%0, %2}"
12085 [(set_attr "type" "ishift")
12086 (set_attr "mode" "DI")])
12088 (define_insn "*ashrdi3_cconly_rex64"
12089 [(set (reg FLAGS_REG)
12091 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12092 (match_operand:QI 2 "const_int_operand" "n"))
12094 (clobber (match_scratch:DI 0 "=r"))]
12096 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12097 && ix86_match_ccmode (insn, CCGOCmode)
12098 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
12099 "sar{q}\t{%2, %0|%0, %2}"
12100 [(set_attr "type" "ishift")
12101 (set_attr "mode" "DI")])
12103 (define_insn "*ashrdi3_1"
12104 [(set (match_operand:DI 0 "register_operand" "=r")
12105 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
12106 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12107 (clobber (reg:CC FLAGS_REG))]
12110 [(set_attr "type" "multi")])
12112 ;; By default we don't ask for a scratch register, because when DImode
12113 ;; values are manipulated, registers are already at a premium. But if
12114 ;; we have one handy, we won't turn it away.
12116 [(match_scratch:SI 3 "r")
12117 (parallel [(set (match_operand:DI 0 "register_operand" "")
12118 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
12119 (match_operand:QI 2 "nonmemory_operand" "")))
12120 (clobber (reg:CC FLAGS_REG))])
12122 "!TARGET_64BIT && TARGET_CMOVE"
12124 "ix86_split_ashr (operands, operands[3], DImode); DONE;")
12127 [(set (match_operand:DI 0 "register_operand" "")
12128 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
12129 (match_operand:QI 2 "nonmemory_operand" "")))
12130 (clobber (reg:CC FLAGS_REG))]
12131 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
12132 ? epilogue_completed : reload_completed)"
12134 "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
12136 (define_insn "x86_shrd_1"
12137 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
12138 (ior:SI (ashiftrt:SI (match_dup 0)
12139 (match_operand:QI 2 "nonmemory_operand" "I,c"))
12140 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
12141 (minus:QI (const_int 32) (match_dup 2)))))
12142 (clobber (reg:CC FLAGS_REG))]
12145 shrd{l}\t{%2, %1, %0|%0, %1, %2}
12146 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
12147 [(set_attr "type" "ishift")
12148 (set_attr "prefix_0f" "1")
12149 (set_attr "pent_pair" "np")
12150 (set_attr "mode" "SI")])
12152 (define_expand "x86_shift_adj_3"
12153 [(use (match_operand:SI 0 "register_operand" ""))
12154 (use (match_operand:SI 1 "register_operand" ""))
12155 (use (match_operand:QI 2 "register_operand" ""))]
12158 rtx label = gen_label_rtx ();
12161 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
12163 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
12164 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
12165 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12166 gen_rtx_LABEL_REF (VOIDmode, label),
12168 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12169 JUMP_LABEL (tmp) = label;
12171 emit_move_insn (operands[0], operands[1]);
12172 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
12174 emit_label (label);
12175 LABEL_NUSES (label) = 1;
12180 (define_insn "ashrsi3_31"
12181 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
12182 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
12183 (match_operand:SI 2 "const_int_operand" "i,i")))
12184 (clobber (reg:CC FLAGS_REG))]
12185 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
12186 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12189 sar{l}\t{%2, %0|%0, %2}"
12190 [(set_attr "type" "imovx,ishift")
12191 (set_attr "prefix_0f" "0,*")
12192 (set_attr "length_immediate" "0,*")
12193 (set_attr "modrm" "0,1")
12194 (set_attr "mode" "SI")])
12196 (define_insn "*ashrsi3_31_zext"
12197 [(set (match_operand:DI 0 "register_operand" "=*d,r")
12198 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
12199 (match_operand:SI 2 "const_int_operand" "i,i"))))
12200 (clobber (reg:CC FLAGS_REG))]
12201 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
12202 && INTVAL (operands[2]) == 31
12203 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12206 sar{l}\t{%2, %k0|%k0, %2}"
12207 [(set_attr "type" "imovx,ishift")
12208 (set_attr "prefix_0f" "0,*")
12209 (set_attr "length_immediate" "0,*")
12210 (set_attr "modrm" "0,1")
12211 (set_attr "mode" "SI")])
12213 (define_expand "ashrsi3"
12214 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12215 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12216 (match_operand:QI 2 "nonmemory_operand" "")))
12217 (clobber (reg:CC FLAGS_REG))]
12219 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
12221 (define_insn "*ashrsi3_1_one_bit"
12222 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12223 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12224 (match_operand:QI 2 "const1_operand" "")))
12225 (clobber (reg:CC FLAGS_REG))]
12226 "(TARGET_SHIFT1 || optimize_size)
12227 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12229 [(set_attr "type" "ishift")
12230 (set (attr "length")
12231 (if_then_else (match_operand:SI 0 "register_operand" "")
12233 (const_string "*")))])
12235 (define_insn "*ashrsi3_1_one_bit_zext"
12236 [(set (match_operand:DI 0 "register_operand" "=r")
12237 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12238 (match_operand:QI 2 "const1_operand" ""))))
12239 (clobber (reg:CC FLAGS_REG))]
12241 && (TARGET_SHIFT1 || optimize_size)
12242 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12244 [(set_attr "type" "ishift")
12245 (set_attr "length" "2")])
12247 (define_insn "*ashrsi3_1"
12248 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12249 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12250 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12251 (clobber (reg:CC FLAGS_REG))]
12252 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12254 sar{l}\t{%2, %0|%0, %2}
12255 sar{l}\t{%b2, %0|%0, %b2}"
12256 [(set_attr "type" "ishift")
12257 (set_attr "mode" "SI")])
12259 (define_insn "*ashrsi3_1_zext"
12260 [(set (match_operand:DI 0 "register_operand" "=r,r")
12261 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
12262 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12263 (clobber (reg:CC FLAGS_REG))]
12264 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12266 sar{l}\t{%2, %k0|%k0, %2}
12267 sar{l}\t{%b2, %k0|%k0, %b2}"
12268 [(set_attr "type" "ishift")
12269 (set_attr "mode" "SI")])
12271 ;; This pattern can't accept a variable shift count, since shifts by
12272 ;; zero don't affect the flags. We assume that shifts by constant
12273 ;; zero are optimized away.
12274 (define_insn "*ashrsi3_one_bit_cmp"
12275 [(set (reg FLAGS_REG)
12277 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12278 (match_operand:QI 2 "const1_operand" ""))
12280 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12281 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12282 "(TARGET_SHIFT1 || optimize_size)
12283 && ix86_match_ccmode (insn, CCGOCmode)
12284 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12286 [(set_attr "type" "ishift")
12287 (set (attr "length")
12288 (if_then_else (match_operand:SI 0 "register_operand" "")
12290 (const_string "*")))])
12292 (define_insn "*ashrsi3_one_bit_cconly"
12293 [(set (reg FLAGS_REG)
12295 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12296 (match_operand:QI 2 "const1_operand" ""))
12298 (clobber (match_scratch:SI 0 "=r"))]
12299 "(TARGET_SHIFT1 || optimize_size)
12300 && ix86_match_ccmode (insn, CCGOCmode)
12301 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12303 [(set_attr "type" "ishift")
12304 (set_attr "length" "2")])
12306 (define_insn "*ashrsi3_one_bit_cmp_zext"
12307 [(set (reg FLAGS_REG)
12309 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12310 (match_operand:QI 2 "const1_operand" ""))
12312 (set (match_operand:DI 0 "register_operand" "=r")
12313 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12315 && (TARGET_SHIFT1 || optimize_size)
12316 && ix86_match_ccmode (insn, CCmode)
12317 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12319 [(set_attr "type" "ishift")
12320 (set_attr "length" "2")])
12322 ;; This pattern can't accept a variable shift count, since shifts by
12323 ;; zero don't affect the flags. We assume that shifts by constant
12324 ;; zero are optimized away.
12325 (define_insn "*ashrsi3_cmp"
12326 [(set (reg FLAGS_REG)
12328 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12329 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12331 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12332 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12333 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12334 && ix86_match_ccmode (insn, CCGOCmode)
12335 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12336 "sar{l}\t{%2, %0|%0, %2}"
12337 [(set_attr "type" "ishift")
12338 (set_attr "mode" "SI")])
12340 (define_insn "*ashrsi3_cconly"
12341 [(set (reg FLAGS_REG)
12343 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12344 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12346 (clobber (match_scratch:SI 0 "=r"))]
12347 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12348 && ix86_match_ccmode (insn, CCGOCmode)
12349 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12350 "sar{l}\t{%2, %0|%0, %2}"
12351 [(set_attr "type" "ishift")
12352 (set_attr "mode" "SI")])
12354 (define_insn "*ashrsi3_cmp_zext"
12355 [(set (reg FLAGS_REG)
12357 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12358 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12360 (set (match_operand:DI 0 "register_operand" "=r")
12361 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12363 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12364 && ix86_match_ccmode (insn, CCGOCmode)
12365 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12366 "sar{l}\t{%2, %k0|%k0, %2}"
12367 [(set_attr "type" "ishift")
12368 (set_attr "mode" "SI")])
12370 (define_expand "ashrhi3"
12371 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12372 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12373 (match_operand:QI 2 "nonmemory_operand" "")))
12374 (clobber (reg:CC FLAGS_REG))]
12375 "TARGET_HIMODE_MATH"
12376 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
12378 (define_insn "*ashrhi3_1_one_bit"
12379 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12380 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12381 (match_operand:QI 2 "const1_operand" "")))
12382 (clobber (reg:CC FLAGS_REG))]
12383 "(TARGET_SHIFT1 || optimize_size)
12384 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12386 [(set_attr "type" "ishift")
12387 (set (attr "length")
12388 (if_then_else (match_operand 0 "register_operand" "")
12390 (const_string "*")))])
12392 (define_insn "*ashrhi3_1"
12393 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12394 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12395 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12396 (clobber (reg:CC FLAGS_REG))]
12397 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12399 sar{w}\t{%2, %0|%0, %2}
12400 sar{w}\t{%b2, %0|%0, %b2}"
12401 [(set_attr "type" "ishift")
12402 (set_attr "mode" "HI")])
12404 ;; This pattern can't accept a variable shift count, since shifts by
12405 ;; zero don't affect the flags. We assume that shifts by constant
12406 ;; zero are optimized away.
12407 (define_insn "*ashrhi3_one_bit_cmp"
12408 [(set (reg FLAGS_REG)
12410 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12411 (match_operand:QI 2 "const1_operand" ""))
12413 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12414 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12415 "(TARGET_SHIFT1 || optimize_size)
12416 && ix86_match_ccmode (insn, CCGOCmode)
12417 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12419 [(set_attr "type" "ishift")
12420 (set (attr "length")
12421 (if_then_else (match_operand 0 "register_operand" "")
12423 (const_string "*")))])
12425 (define_insn "*ashrhi3_one_bit_cconly"
12426 [(set (reg FLAGS_REG)
12428 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12429 (match_operand:QI 2 "const1_operand" ""))
12431 (clobber (match_scratch:HI 0 "=r"))]
12432 "(TARGET_SHIFT1 || optimize_size)
12433 && ix86_match_ccmode (insn, CCGOCmode)
12434 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12436 [(set_attr "type" "ishift")
12437 (set_attr "length" "2")])
12439 ;; This pattern can't accept a variable shift count, since shifts by
12440 ;; zero don't affect the flags. We assume that shifts by constant
12441 ;; zero are optimized away.
12442 (define_insn "*ashrhi3_cmp"
12443 [(set (reg FLAGS_REG)
12445 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12446 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12448 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12449 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12450 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12451 && ix86_match_ccmode (insn, CCGOCmode)
12452 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12453 "sar{w}\t{%2, %0|%0, %2}"
12454 [(set_attr "type" "ishift")
12455 (set_attr "mode" "HI")])
12457 (define_insn "*ashrhi3_cconly"
12458 [(set (reg FLAGS_REG)
12460 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12461 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12463 (clobber (match_scratch:HI 0 "=r"))]
12464 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12465 && ix86_match_ccmode (insn, CCGOCmode)
12466 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12467 "sar{w}\t{%2, %0|%0, %2}"
12468 [(set_attr "type" "ishift")
12469 (set_attr "mode" "HI")])
12471 (define_expand "ashrqi3"
12472 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12473 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12474 (match_operand:QI 2 "nonmemory_operand" "")))
12475 (clobber (reg:CC FLAGS_REG))]
12476 "TARGET_QIMODE_MATH"
12477 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
12479 (define_insn "*ashrqi3_1_one_bit"
12480 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12481 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12482 (match_operand:QI 2 "const1_operand" "")))
12483 (clobber (reg:CC FLAGS_REG))]
12484 "(TARGET_SHIFT1 || optimize_size)
12485 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12487 [(set_attr "type" "ishift")
12488 (set (attr "length")
12489 (if_then_else (match_operand 0 "register_operand" "")
12491 (const_string "*")))])
12493 (define_insn "*ashrqi3_1_one_bit_slp"
12494 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12495 (ashiftrt:QI (match_dup 0)
12496 (match_operand:QI 1 "const1_operand" "")))
12497 (clobber (reg:CC FLAGS_REG))]
12498 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12499 && (TARGET_SHIFT1 || optimize_size)
12500 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12502 [(set_attr "type" "ishift1")
12503 (set (attr "length")
12504 (if_then_else (match_operand 0 "register_operand" "")
12506 (const_string "*")))])
12508 (define_insn "*ashrqi3_1"
12509 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12510 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12511 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12512 (clobber (reg:CC FLAGS_REG))]
12513 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12515 sar{b}\t{%2, %0|%0, %2}
12516 sar{b}\t{%b2, %0|%0, %b2}"
12517 [(set_attr "type" "ishift")
12518 (set_attr "mode" "QI")])
12520 (define_insn "*ashrqi3_1_slp"
12521 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12522 (ashiftrt:QI (match_dup 0)
12523 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12524 (clobber (reg:CC FLAGS_REG))]
12525 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12526 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
12528 sar{b}\t{%1, %0|%0, %1}
12529 sar{b}\t{%b1, %0|%0, %b1}"
12530 [(set_attr "type" "ishift1")
12531 (set_attr "mode" "QI")])
12533 ;; This pattern can't accept a variable shift count, since shifts by
12534 ;; zero don't affect the flags. We assume that shifts by constant
12535 ;; zero are optimized away.
12536 (define_insn "*ashrqi3_one_bit_cmp"
12537 [(set (reg FLAGS_REG)
12539 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12540 (match_operand:QI 2 "const1_operand" "I"))
12542 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12543 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12544 "(TARGET_SHIFT1 || optimize_size)
12545 && ix86_match_ccmode (insn, CCGOCmode)
12546 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12548 [(set_attr "type" "ishift")
12549 (set (attr "length")
12550 (if_then_else (match_operand 0 "register_operand" "")
12552 (const_string "*")))])
12554 (define_insn "*ashrqi3_one_bit_cconly"
12555 [(set (reg FLAGS_REG)
12557 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12558 (match_operand:QI 2 "const1_operand" "I"))
12560 (clobber (match_scratch:QI 0 "=q"))]
12561 "(TARGET_SHIFT1 || optimize_size)
12562 && ix86_match_ccmode (insn, CCGOCmode)
12563 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12565 [(set_attr "type" "ishift")
12566 (set_attr "length" "2")])
12568 ;; This pattern can't accept a variable shift count, since shifts by
12569 ;; zero don't affect the flags. We assume that shifts by constant
12570 ;; zero are optimized away.
12571 (define_insn "*ashrqi3_cmp"
12572 [(set (reg FLAGS_REG)
12574 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12575 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12577 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12578 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12579 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12580 && ix86_match_ccmode (insn, CCGOCmode)
12581 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12582 "sar{b}\t{%2, %0|%0, %2}"
12583 [(set_attr "type" "ishift")
12584 (set_attr "mode" "QI")])
12586 (define_insn "*ashrqi3_cconly"
12587 [(set (reg FLAGS_REG)
12589 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12590 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12592 (clobber (match_scratch:QI 0 "=q"))]
12593 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12594 && ix86_match_ccmode (insn, CCGOCmode)
12595 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12596 "sar{b}\t{%2, %0|%0, %2}"
12597 [(set_attr "type" "ishift")
12598 (set_attr "mode" "QI")])
12601 ;; Logical shift instructions
12603 ;; See comment above `ashldi3' about how this works.
12605 (define_expand "lshrti3"
12606 [(parallel [(set (match_operand:TI 0 "register_operand" "")
12607 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
12608 (match_operand:QI 2 "nonmemory_operand" "")))
12609 (clobber (reg:CC FLAGS_REG))])]
12612 if (! immediate_operand (operands[2], QImode))
12614 emit_insn (gen_lshrti3_1 (operands[0], operands[1], operands[2]));
12617 ix86_expand_binary_operator (LSHIFTRT, TImode, operands);
12621 (define_insn "lshrti3_1"
12622 [(set (match_operand:TI 0 "register_operand" "=r")
12623 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
12624 (match_operand:QI 2 "register_operand" "c")))
12625 (clobber (match_scratch:DI 3 "=&r"))
12626 (clobber (reg:CC FLAGS_REG))]
12629 [(set_attr "type" "multi")])
12631 ;; This pattern must be defined before *lshrti3_2 to prevent
12632 ;; combine pass from converting sse2_lshrti3 to *lshrti3_2.
12634 (define_insn "sse2_lshrti3"
12635 [(set (match_operand:TI 0 "register_operand" "=x")
12636 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
12637 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
12640 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
12641 return "psrldq\t{%2, %0|%0, %2}";
12643 [(set_attr "type" "sseishft")
12644 (set_attr "prefix_data16" "1")
12645 (set_attr "mode" "TI")])
12647 (define_insn "*lshrti3_2"
12648 [(set (match_operand:TI 0 "register_operand" "=r")
12649 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
12650 (match_operand:QI 2 "immediate_operand" "O")))
12651 (clobber (reg:CC FLAGS_REG))]
12654 [(set_attr "type" "multi")])
12657 [(set (match_operand:TI 0 "register_operand" "")
12658 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
12659 (match_operand:QI 2 "register_operand" "")))
12660 (clobber (match_scratch:DI 3 ""))
12661 (clobber (reg:CC FLAGS_REG))]
12662 "TARGET_64BIT && reload_completed"
12664 "ix86_split_lshr (operands, operands[3], TImode); DONE;")
12667 [(set (match_operand:TI 0 "register_operand" "")
12668 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
12669 (match_operand:QI 2 "immediate_operand" "")))
12670 (clobber (reg:CC FLAGS_REG))]
12671 "TARGET_64BIT && reload_completed"
12673 "ix86_split_lshr (operands, NULL_RTX, TImode); DONE;")
12675 (define_expand "lshrdi3"
12676 [(set (match_operand:DI 0 "shiftdi_operand" "")
12677 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12678 (match_operand:QI 2 "nonmemory_operand" "")))]
12680 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
12682 (define_insn "*lshrdi3_1_one_bit_rex64"
12683 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12684 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12685 (match_operand:QI 2 "const1_operand" "")))
12686 (clobber (reg:CC FLAGS_REG))]
12688 && (TARGET_SHIFT1 || optimize_size)
12689 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12691 [(set_attr "type" "ishift")
12692 (set (attr "length")
12693 (if_then_else (match_operand:DI 0 "register_operand" "")
12695 (const_string "*")))])
12697 (define_insn "*lshrdi3_1_rex64"
12698 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12699 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12700 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12701 (clobber (reg:CC FLAGS_REG))]
12702 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12704 shr{q}\t{%2, %0|%0, %2}
12705 shr{q}\t{%b2, %0|%0, %b2}"
12706 [(set_attr "type" "ishift")
12707 (set_attr "mode" "DI")])
12709 ;; This pattern can't accept a variable shift count, since shifts by
12710 ;; zero don't affect the flags. We assume that shifts by constant
12711 ;; zero are optimized away.
12712 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12713 [(set (reg FLAGS_REG)
12715 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12716 (match_operand:QI 2 "const1_operand" ""))
12718 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12719 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12721 && (TARGET_SHIFT1 || optimize_size)
12722 && ix86_match_ccmode (insn, CCGOCmode)
12723 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12725 [(set_attr "type" "ishift")
12726 (set (attr "length")
12727 (if_then_else (match_operand:DI 0 "register_operand" "")
12729 (const_string "*")))])
12731 (define_insn "*lshrdi3_cconly_one_bit_rex64"
12732 [(set (reg FLAGS_REG)
12734 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12735 (match_operand:QI 2 "const1_operand" ""))
12737 (clobber (match_scratch:DI 0 "=r"))]
12739 && (TARGET_SHIFT1 || optimize_size)
12740 && ix86_match_ccmode (insn, CCGOCmode)
12741 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12743 [(set_attr "type" "ishift")
12744 (set_attr "length" "2")])
12746 ;; This pattern can't accept a variable shift count, since shifts by
12747 ;; zero don't affect the flags. We assume that shifts by constant
12748 ;; zero are optimized away.
12749 (define_insn "*lshrdi3_cmp_rex64"
12750 [(set (reg FLAGS_REG)
12752 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12753 (match_operand:QI 2 "const_int_operand" "e"))
12755 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12756 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12758 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12759 && ix86_match_ccmode (insn, CCGOCmode)
12760 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12761 "shr{q}\t{%2, %0|%0, %2}"
12762 [(set_attr "type" "ishift")
12763 (set_attr "mode" "DI")])
12765 (define_insn "*lshrdi3_cconly_rex64"
12766 [(set (reg FLAGS_REG)
12768 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12769 (match_operand:QI 2 "const_int_operand" "e"))
12771 (clobber (match_scratch:DI 0 "=r"))]
12773 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12774 && ix86_match_ccmode (insn, CCGOCmode)
12775 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12776 "shr{q}\t{%2, %0|%0, %2}"
12777 [(set_attr "type" "ishift")
12778 (set_attr "mode" "DI")])
12780 (define_insn "*lshrdi3_1"
12781 [(set (match_operand:DI 0 "register_operand" "=r")
12782 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12783 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12784 (clobber (reg:CC FLAGS_REG))]
12787 [(set_attr "type" "multi")])
12789 ;; By default we don't ask for a scratch register, because when DImode
12790 ;; values are manipulated, registers are already at a premium. But if
12791 ;; we have one handy, we won't turn it away.
12793 [(match_scratch:SI 3 "r")
12794 (parallel [(set (match_operand:DI 0 "register_operand" "")
12795 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12796 (match_operand:QI 2 "nonmemory_operand" "")))
12797 (clobber (reg:CC FLAGS_REG))])
12799 "!TARGET_64BIT && TARGET_CMOVE"
12801 "ix86_split_lshr (operands, operands[3], DImode); DONE;")
12804 [(set (match_operand:DI 0 "register_operand" "")
12805 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12806 (match_operand:QI 2 "nonmemory_operand" "")))
12807 (clobber (reg:CC FLAGS_REG))]
12808 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
12809 ? epilogue_completed : reload_completed)"
12811 "ix86_split_lshr (operands, NULL_RTX, DImode); DONE;")
12813 (define_expand "lshrsi3"
12814 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12815 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12816 (match_operand:QI 2 "nonmemory_operand" "")))
12817 (clobber (reg:CC FLAGS_REG))]
12819 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12821 (define_insn "*lshrsi3_1_one_bit"
12822 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12823 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12824 (match_operand:QI 2 "const1_operand" "")))
12825 (clobber (reg:CC FLAGS_REG))]
12826 "(TARGET_SHIFT1 || optimize_size)
12827 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12829 [(set_attr "type" "ishift")
12830 (set (attr "length")
12831 (if_then_else (match_operand:SI 0 "register_operand" "")
12833 (const_string "*")))])
12835 (define_insn "*lshrsi3_1_one_bit_zext"
12836 [(set (match_operand:DI 0 "register_operand" "=r")
12837 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12838 (match_operand:QI 2 "const1_operand" "")))
12839 (clobber (reg:CC FLAGS_REG))]
12841 && (TARGET_SHIFT1 || optimize_size)
12842 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12844 [(set_attr "type" "ishift")
12845 (set_attr "length" "2")])
12847 (define_insn "*lshrsi3_1"
12848 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12849 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12850 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12851 (clobber (reg:CC FLAGS_REG))]
12852 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12854 shr{l}\t{%2, %0|%0, %2}
12855 shr{l}\t{%b2, %0|%0, %b2}"
12856 [(set_attr "type" "ishift")
12857 (set_attr "mode" "SI")])
12859 (define_insn "*lshrsi3_1_zext"
12860 [(set (match_operand:DI 0 "register_operand" "=r,r")
12862 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12863 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12864 (clobber (reg:CC FLAGS_REG))]
12865 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12867 shr{l}\t{%2, %k0|%k0, %2}
12868 shr{l}\t{%b2, %k0|%k0, %b2}"
12869 [(set_attr "type" "ishift")
12870 (set_attr "mode" "SI")])
12872 ;; This pattern can't accept a variable shift count, since shifts by
12873 ;; zero don't affect the flags. We assume that shifts by constant
12874 ;; zero are optimized away.
12875 (define_insn "*lshrsi3_one_bit_cmp"
12876 [(set (reg FLAGS_REG)
12878 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12879 (match_operand:QI 2 "const1_operand" ""))
12881 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12882 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12883 "(TARGET_SHIFT1 || optimize_size)
12884 && ix86_match_ccmode (insn, CCGOCmode)
12885 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12887 [(set_attr "type" "ishift")
12888 (set (attr "length")
12889 (if_then_else (match_operand:SI 0 "register_operand" "")
12891 (const_string "*")))])
12893 (define_insn "*lshrsi3_one_bit_cconly"
12894 [(set (reg FLAGS_REG)
12896 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12897 (match_operand:QI 2 "const1_operand" ""))
12899 (clobber (match_scratch:SI 0 "=r"))]
12900 "(TARGET_SHIFT1 || optimize_size)
12901 && ix86_match_ccmode (insn, CCGOCmode)
12902 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12904 [(set_attr "type" "ishift")
12905 (set_attr "length" "2")])
12907 (define_insn "*lshrsi3_cmp_one_bit_zext"
12908 [(set (reg FLAGS_REG)
12910 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12911 (match_operand:QI 2 "const1_operand" ""))
12913 (set (match_operand:DI 0 "register_operand" "=r")
12914 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12916 && (TARGET_SHIFT1 || optimize_size)
12917 && ix86_match_ccmode (insn, CCGOCmode)
12918 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12920 [(set_attr "type" "ishift")
12921 (set_attr "length" "2")])
12923 ;; This pattern can't accept a variable shift count, since shifts by
12924 ;; zero don't affect the flags. We assume that shifts by constant
12925 ;; zero are optimized away.
12926 (define_insn "*lshrsi3_cmp"
12927 [(set (reg FLAGS_REG)
12929 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12930 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12932 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12933 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12934 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12935 && ix86_match_ccmode (insn, CCGOCmode)
12936 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12937 "shr{l}\t{%2, %0|%0, %2}"
12938 [(set_attr "type" "ishift")
12939 (set_attr "mode" "SI")])
12941 (define_insn "*lshrsi3_cconly"
12942 [(set (reg FLAGS_REG)
12944 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12945 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12947 (clobber (match_scratch:SI 0 "=r"))]
12948 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12949 && ix86_match_ccmode (insn, CCGOCmode)
12950 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12951 "shr{l}\t{%2, %0|%0, %2}"
12952 [(set_attr "type" "ishift")
12953 (set_attr "mode" "SI")])
12955 (define_insn "*lshrsi3_cmp_zext"
12956 [(set (reg FLAGS_REG)
12958 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12959 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12961 (set (match_operand:DI 0 "register_operand" "=r")
12962 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12964 && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
12965 && ix86_match_ccmode (insn, CCGOCmode)
12966 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12967 "shr{l}\t{%2, %k0|%k0, %2}"
12968 [(set_attr "type" "ishift")
12969 (set_attr "mode" "SI")])
12971 (define_expand "lshrhi3"
12972 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12973 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12974 (match_operand:QI 2 "nonmemory_operand" "")))
12975 (clobber (reg:CC FLAGS_REG))]
12976 "TARGET_HIMODE_MATH"
12977 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12979 (define_insn "*lshrhi3_1_one_bit"
12980 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12981 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12982 (match_operand:QI 2 "const1_operand" "")))
12983 (clobber (reg:CC FLAGS_REG))]
12984 "(TARGET_SHIFT1 || optimize_size)
12985 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12987 [(set_attr "type" "ishift")
12988 (set (attr "length")
12989 (if_then_else (match_operand 0 "register_operand" "")
12991 (const_string "*")))])
12993 (define_insn "*lshrhi3_1"
12994 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12995 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12996 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12997 (clobber (reg:CC FLAGS_REG))]
12998 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
13000 shr{w}\t{%2, %0|%0, %2}
13001 shr{w}\t{%b2, %0|%0, %b2}"
13002 [(set_attr "type" "ishift")
13003 (set_attr "mode" "HI")])
13005 ;; This pattern can't accept a variable shift count, since shifts by
13006 ;; zero don't affect the flags. We assume that shifts by constant
13007 ;; zero are optimized away.
13008 (define_insn "*lshrhi3_one_bit_cmp"
13009 [(set (reg FLAGS_REG)
13011 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13012 (match_operand:QI 2 "const1_operand" ""))
13014 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13015 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
13016 "(TARGET_SHIFT1 || optimize_size)
13017 && ix86_match_ccmode (insn, CCGOCmode)
13018 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
13020 [(set_attr "type" "ishift")
13021 (set (attr "length")
13022 (if_then_else (match_operand:SI 0 "register_operand" "")
13024 (const_string "*")))])
13026 (define_insn "*lshrhi3_one_bit_cconly"
13027 [(set (reg FLAGS_REG)
13029 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13030 (match_operand:QI 2 "const1_operand" ""))
13032 (clobber (match_scratch:HI 0 "=r"))]
13033 "(TARGET_SHIFT1 || optimize_size)
13034 && ix86_match_ccmode (insn, CCGOCmode)
13035 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
13037 [(set_attr "type" "ishift")
13038 (set_attr "length" "2")])
13040 ;; This pattern can't accept a variable shift count, since shifts by
13041 ;; zero don't affect the flags. We assume that shifts by constant
13042 ;; zero are optimized away.
13043 (define_insn "*lshrhi3_cmp"
13044 [(set (reg FLAGS_REG)
13046 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13047 (match_operand:QI 2 "const_1_to_31_operand" "I"))
13049 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13050 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
13051 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
13052 && ix86_match_ccmode (insn, CCGOCmode)
13053 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
13054 "shr{w}\t{%2, %0|%0, %2}"
13055 [(set_attr "type" "ishift")
13056 (set_attr "mode" "HI")])
13058 (define_insn "*lshrhi3_cconly"
13059 [(set (reg FLAGS_REG)
13061 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13062 (match_operand:QI 2 "const_1_to_31_operand" "I"))
13064 (clobber (match_scratch:HI 0 "=r"))]
13065 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
13066 && ix86_match_ccmode (insn, CCGOCmode)
13067 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
13068 "shr{w}\t{%2, %0|%0, %2}"
13069 [(set_attr "type" "ishift")
13070 (set_attr "mode" "HI")])
13072 (define_expand "lshrqi3"
13073 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13074 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
13075 (match_operand:QI 2 "nonmemory_operand" "")))
13076 (clobber (reg:CC FLAGS_REG))]
13077 "TARGET_QIMODE_MATH"
13078 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
13080 (define_insn "*lshrqi3_1_one_bit"
13081 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13082 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13083 (match_operand:QI 2 "const1_operand" "")))
13084 (clobber (reg:CC FLAGS_REG))]
13085 "(TARGET_SHIFT1 || optimize_size)
13086 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13088 [(set_attr "type" "ishift")
13089 (set (attr "length")
13090 (if_then_else (match_operand 0 "register_operand" "")
13092 (const_string "*")))])
13094 (define_insn "*lshrqi3_1_one_bit_slp"
13095 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13096 (lshiftrt:QI (match_dup 0)
13097 (match_operand:QI 1 "const1_operand" "")))
13098 (clobber (reg:CC FLAGS_REG))]
13099 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13100 && (TARGET_SHIFT1 || optimize_size)"
13102 [(set_attr "type" "ishift1")
13103 (set (attr "length")
13104 (if_then_else (match_operand 0 "register_operand" "")
13106 (const_string "*")))])
13108 (define_insn "*lshrqi3_1"
13109 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13110 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13111 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13112 (clobber (reg:CC FLAGS_REG))]
13113 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13115 shr{b}\t{%2, %0|%0, %2}
13116 shr{b}\t{%b2, %0|%0, %b2}"
13117 [(set_attr "type" "ishift")
13118 (set_attr "mode" "QI")])
13120 (define_insn "*lshrqi3_1_slp"
13121 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13122 (lshiftrt:QI (match_dup 0)
13123 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13124 (clobber (reg:CC FLAGS_REG))]
13125 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13126 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13128 shr{b}\t{%1, %0|%0, %1}
13129 shr{b}\t{%b1, %0|%0, %b1}"
13130 [(set_attr "type" "ishift1")
13131 (set_attr "mode" "QI")])
13133 ;; This pattern can't accept a variable shift count, since shifts by
13134 ;; zero don't affect the flags. We assume that shifts by constant
13135 ;; zero are optimized away.
13136 (define_insn "*lshrqi2_one_bit_cmp"
13137 [(set (reg FLAGS_REG)
13139 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13140 (match_operand:QI 2 "const1_operand" ""))
13142 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13143 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
13144 "(TARGET_SHIFT1 || optimize_size)
13145 && ix86_match_ccmode (insn, CCGOCmode)
13146 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13148 [(set_attr "type" "ishift")
13149 (set (attr "length")
13150 (if_then_else (match_operand:SI 0 "register_operand" "")
13152 (const_string "*")))])
13154 (define_insn "*lshrqi2_one_bit_cconly"
13155 [(set (reg FLAGS_REG)
13157 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13158 (match_operand:QI 2 "const1_operand" ""))
13160 (clobber (match_scratch:QI 0 "=q"))]
13161 "(TARGET_SHIFT1 || optimize_size)
13162 && ix86_match_ccmode (insn, CCGOCmode)
13163 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13165 [(set_attr "type" "ishift")
13166 (set_attr "length" "2")])
13168 ;; This pattern can't accept a variable shift count, since shifts by
13169 ;; zero don't affect the flags. We assume that shifts by constant
13170 ;; zero are optimized away.
13171 (define_insn "*lshrqi2_cmp"
13172 [(set (reg FLAGS_REG)
13174 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13175 (match_operand:QI 2 "const_1_to_31_operand" "I"))
13177 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13178 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
13179 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
13180 && ix86_match_ccmode (insn, CCGOCmode)
13181 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13182 "shr{b}\t{%2, %0|%0, %2}"
13183 [(set_attr "type" "ishift")
13184 (set_attr "mode" "QI")])
13186 (define_insn "*lshrqi2_cconly"
13187 [(set (reg FLAGS_REG)
13189 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13190 (match_operand:QI 2 "const_1_to_31_operand" "I"))
13192 (clobber (match_scratch:QI 0 "=q"))]
13193 "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
13194 && ix86_match_ccmode (insn, CCGOCmode)
13195 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
13196 "shr{b}\t{%2, %0|%0, %2}"
13197 [(set_attr "type" "ishift")
13198 (set_attr "mode" "QI")])
13200 ;; Rotate instructions
13202 (define_expand "rotldi3"
13203 [(set (match_operand:DI 0 "shiftdi_operand" "")
13204 (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
13205 (match_operand:QI 2 "nonmemory_operand" "")))
13206 (clobber (reg:CC FLAGS_REG))]
13211 ix86_expand_binary_operator (ROTATE, DImode, operands);
13214 if (!const_1_to_31_operand (operands[2], VOIDmode))
13216 emit_insn (gen_ix86_rotldi3 (operands[0], operands[1], operands[2]));
13220 ;; Implement rotation using two double-precision shift instructions
13221 ;; and a scratch register.
13222 (define_insn_and_split "ix86_rotldi3"
13223 [(set (match_operand:DI 0 "register_operand" "=r")
13224 (rotate:DI (match_operand:DI 1 "register_operand" "0")
13225 (match_operand:QI 2 "const_1_to_31_operand" "I")))
13226 (clobber (reg:CC FLAGS_REG))
13227 (clobber (match_scratch:SI 3 "=&r"))]
13230 "&& reload_completed"
13231 [(set (match_dup 3) (match_dup 4))
13233 [(set (match_dup 4)
13234 (ior:SI (ashift:SI (match_dup 4) (match_dup 2))
13235 (lshiftrt:SI (match_dup 5)
13236 (minus:QI (const_int 32) (match_dup 2)))))
13237 (clobber (reg:CC FLAGS_REG))])
13239 [(set (match_dup 5)
13240 (ior:SI (ashift:SI (match_dup 5) (match_dup 2))
13241 (lshiftrt:SI (match_dup 3)
13242 (minus:QI (const_int 32) (match_dup 2)))))
13243 (clobber (reg:CC FLAGS_REG))])]
13244 "split_di (operands, 1, operands + 4, operands + 5);")
13246 (define_insn "*rotlsi3_1_one_bit_rex64"
13247 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
13248 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
13249 (match_operand:QI 2 "const1_operand" "")))
13250 (clobber (reg:CC FLAGS_REG))]
13252 && (TARGET_SHIFT1 || optimize_size)
13253 && ix86_binary_operator_ok (ROTATE, DImode, operands)"
13255 [(set_attr "type" "rotate")
13256 (set (attr "length")
13257 (if_then_else (match_operand:DI 0 "register_operand" "")
13259 (const_string "*")))])
13261 (define_insn "*rotldi3_1_rex64"
13262 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
13263 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
13264 (match_operand:QI 2 "nonmemory_operand" "e,c")))
13265 (clobber (reg:CC FLAGS_REG))]
13266 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
13268 rol{q}\t{%2, %0|%0, %2}
13269 rol{q}\t{%b2, %0|%0, %b2}"
13270 [(set_attr "type" "rotate")
13271 (set_attr "mode" "DI")])
13273 (define_expand "rotlsi3"
13274 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13275 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
13276 (match_operand:QI 2 "nonmemory_operand" "")))
13277 (clobber (reg:CC FLAGS_REG))]
13279 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
13281 (define_insn "*rotlsi3_1_one_bit"
13282 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
13283 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
13284 (match_operand:QI 2 "const1_operand" "")))
13285 (clobber (reg:CC FLAGS_REG))]
13286 "(TARGET_SHIFT1 || optimize_size)
13287 && ix86_binary_operator_ok (ROTATE, SImode, operands)"
13289 [(set_attr "type" "rotate")
13290 (set (attr "length")
13291 (if_then_else (match_operand:SI 0 "register_operand" "")
13293 (const_string "*")))])
13295 (define_insn "*rotlsi3_1_one_bit_zext"
13296 [(set (match_operand:DI 0 "register_operand" "=r")
13298 (rotate:SI (match_operand:SI 1 "register_operand" "0")
13299 (match_operand:QI 2 "const1_operand" ""))))
13300 (clobber (reg:CC FLAGS_REG))]
13302 && (TARGET_SHIFT1 || optimize_size)
13303 && ix86_binary_operator_ok (ROTATE, SImode, operands)"
13305 [(set_attr "type" "rotate")
13306 (set_attr "length" "2")])
13308 (define_insn "*rotlsi3_1"
13309 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
13310 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
13311 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13312 (clobber (reg:CC FLAGS_REG))]
13313 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
13315 rol{l}\t{%2, %0|%0, %2}
13316 rol{l}\t{%b2, %0|%0, %b2}"
13317 [(set_attr "type" "rotate")
13318 (set_attr "mode" "SI")])
13320 (define_insn "*rotlsi3_1_zext"
13321 [(set (match_operand:DI 0 "register_operand" "=r,r")
13323 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
13324 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
13325 (clobber (reg:CC FLAGS_REG))]
13326 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
13328 rol{l}\t{%2, %k0|%k0, %2}
13329 rol{l}\t{%b2, %k0|%k0, %b2}"
13330 [(set_attr "type" "rotate")
13331 (set_attr "mode" "SI")])
13333 (define_expand "rotlhi3"
13334 [(set (match_operand:HI 0 "nonimmediate_operand" "")
13335 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
13336 (match_operand:QI 2 "nonmemory_operand" "")))
13337 (clobber (reg:CC FLAGS_REG))]
13338 "TARGET_HIMODE_MATH"
13339 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
13341 (define_insn "*rotlhi3_1_one_bit"
13342 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13343 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13344 (match_operand:QI 2 "const1_operand" "")))
13345 (clobber (reg:CC FLAGS_REG))]
13346 "(TARGET_SHIFT1 || optimize_size)
13347 && ix86_binary_operator_ok (ROTATE, HImode, operands)"
13349 [(set_attr "type" "rotate")
13350 (set (attr "length")
13351 (if_then_else (match_operand 0 "register_operand" "")
13353 (const_string "*")))])
13355 (define_insn "*rotlhi3_1"
13356 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
13357 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
13358 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13359 (clobber (reg:CC FLAGS_REG))]
13360 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
13362 rol{w}\t{%2, %0|%0, %2}
13363 rol{w}\t{%b2, %0|%0, %b2}"
13364 [(set_attr "type" "rotate")
13365 (set_attr "mode" "HI")])
13368 [(set (match_operand:HI 0 "register_operand" "")
13369 (rotate:HI (match_dup 0) (const_int 8)))
13370 (clobber (reg:CC FLAGS_REG))]
13372 [(parallel [(set (strict_low_part (match_dup 0))
13373 (bswap:HI (match_dup 0)))
13374 (clobber (reg:CC FLAGS_REG))])]
13377 (define_expand "rotlqi3"
13378 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13379 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
13380 (match_operand:QI 2 "nonmemory_operand" "")))
13381 (clobber (reg:CC FLAGS_REG))]
13382 "TARGET_QIMODE_MATH"
13383 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
13385 (define_insn "*rotlqi3_1_one_bit_slp"
13386 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13387 (rotate:QI (match_dup 0)
13388 (match_operand:QI 1 "const1_operand" "")))
13389 (clobber (reg:CC FLAGS_REG))]
13390 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13391 && (TARGET_SHIFT1 || optimize_size)"
13393 [(set_attr "type" "rotate1")
13394 (set (attr "length")
13395 (if_then_else (match_operand 0 "register_operand" "")
13397 (const_string "*")))])
13399 (define_insn "*rotlqi3_1_one_bit"
13400 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13401 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13402 (match_operand:QI 2 "const1_operand" "")))
13403 (clobber (reg:CC FLAGS_REG))]
13404 "(TARGET_SHIFT1 || optimize_size)
13405 && ix86_binary_operator_ok (ROTATE, QImode, operands)"
13407 [(set_attr "type" "rotate")
13408 (set (attr "length")
13409 (if_then_else (match_operand 0 "register_operand" "")
13411 (const_string "*")))])
13413 (define_insn "*rotlqi3_1_slp"
13414 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13415 (rotate:QI (match_dup 0)
13416 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13417 (clobber (reg:CC FLAGS_REG))]
13418 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13419 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13421 rol{b}\t{%1, %0|%0, %1}
13422 rol{b}\t{%b1, %0|%0, %b1}"
13423 [(set_attr "type" "rotate1")
13424 (set_attr "mode" "QI")])
13426 (define_insn "*rotlqi3_1"
13427 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13428 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13429 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13430 (clobber (reg:CC FLAGS_REG))]
13431 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
13433 rol{b}\t{%2, %0|%0, %2}
13434 rol{b}\t{%b2, %0|%0, %b2}"
13435 [(set_attr "type" "rotate")
13436 (set_attr "mode" "QI")])
13438 (define_expand "rotrdi3"
13439 [(set (match_operand:DI 0 "shiftdi_operand" "")
13440 (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
13441 (match_operand:QI 2 "nonmemory_operand" "")))
13442 (clobber (reg:CC FLAGS_REG))]
13447 ix86_expand_binary_operator (ROTATERT, DImode, operands);
13450 if (!const_1_to_31_operand (operands[2], VOIDmode))
13452 emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
13456 ;; Implement rotation using two double-precision shift instructions
13457 ;; and a scratch register.
13458 (define_insn_and_split "ix86_rotrdi3"
13459 [(set (match_operand:DI 0 "register_operand" "=r")
13460 (rotatert:DI (match_operand:DI 1 "register_operand" "0")
13461 (match_operand:QI 2 "const_1_to_31_operand" "I")))
13462 (clobber (reg:CC FLAGS_REG))
13463 (clobber (match_scratch:SI 3 "=&r"))]
13466 "&& reload_completed"
13467 [(set (match_dup 3) (match_dup 4))
13469 [(set (match_dup 4)
13470 (ior:SI (ashiftrt:SI (match_dup 4) (match_dup 2))
13471 (ashift:SI (match_dup 5)
13472 (minus:QI (const_int 32) (match_dup 2)))))
13473 (clobber (reg:CC FLAGS_REG))])
13475 [(set (match_dup 5)
13476 (ior:SI (ashiftrt:SI (match_dup 5) (match_dup 2))
13477 (ashift:SI (match_dup 3)
13478 (minus:QI (const_int 32) (match_dup 2)))))
13479 (clobber (reg:CC FLAGS_REG))])]
13480 "split_di (operands, 1, operands + 4, operands + 5);")
13482 (define_insn "*rotrdi3_1_one_bit_rex64"
13483 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
13484 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
13485 (match_operand:QI 2 "const1_operand" "")))
13486 (clobber (reg:CC FLAGS_REG))]
13488 && (TARGET_SHIFT1 || optimize_size)
13489 && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
13491 [(set_attr "type" "rotate")
13492 (set (attr "length")
13493 (if_then_else (match_operand:DI 0 "register_operand" "")
13495 (const_string "*")))])
13497 (define_insn "*rotrdi3_1_rex64"
13498 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
13499 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
13500 (match_operand:QI 2 "nonmemory_operand" "J,c")))
13501 (clobber (reg:CC FLAGS_REG))]
13502 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
13504 ror{q}\t{%2, %0|%0, %2}
13505 ror{q}\t{%b2, %0|%0, %b2}"
13506 [(set_attr "type" "rotate")
13507 (set_attr "mode" "DI")])
13509 (define_expand "rotrsi3"
13510 [(set (match_operand:SI 0 "nonimmediate_operand" "")
13511 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
13512 (match_operand:QI 2 "nonmemory_operand" "")))
13513 (clobber (reg:CC FLAGS_REG))]
13515 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
13517 (define_insn "*rotrsi3_1_one_bit"
13518 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
13519 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
13520 (match_operand:QI 2 "const1_operand" "")))
13521 (clobber (reg:CC FLAGS_REG))]
13522 "(TARGET_SHIFT1 || optimize_size)
13523 && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
13525 [(set_attr "type" "rotate")
13526 (set (attr "length")
13527 (if_then_else (match_operand:SI 0 "register_operand" "")
13529 (const_string "*")))])
13531 (define_insn "*rotrsi3_1_one_bit_zext"
13532 [(set (match_operand:DI 0 "register_operand" "=r")
13534 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
13535 (match_operand:QI 2 "const1_operand" ""))))
13536 (clobber (reg:CC FLAGS_REG))]
13538 && (TARGET_SHIFT1 || optimize_size)
13539 && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
13541 [(set_attr "type" "rotate")
13542 (set (attr "length")
13543 (if_then_else (match_operand:SI 0 "register_operand" "")
13545 (const_string "*")))])
13547 (define_insn "*rotrsi3_1"
13548 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
13549 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
13550 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13551 (clobber (reg:CC FLAGS_REG))]
13552 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
13554 ror{l}\t{%2, %0|%0, %2}
13555 ror{l}\t{%b2, %0|%0, %b2}"
13556 [(set_attr "type" "rotate")
13557 (set_attr "mode" "SI")])
13559 (define_insn "*rotrsi3_1_zext"
13560 [(set (match_operand:DI 0 "register_operand" "=r,r")
13562 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
13563 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
13564 (clobber (reg:CC FLAGS_REG))]
13565 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
13567 ror{l}\t{%2, %k0|%k0, %2}
13568 ror{l}\t{%b2, %k0|%k0, %b2}"
13569 [(set_attr "type" "rotate")
13570 (set_attr "mode" "SI")])
13572 (define_expand "rotrhi3"
13573 [(set (match_operand:HI 0 "nonimmediate_operand" "")
13574 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
13575 (match_operand:QI 2 "nonmemory_operand" "")))
13576 (clobber (reg:CC FLAGS_REG))]
13577 "TARGET_HIMODE_MATH"
13578 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
13580 (define_insn "*rotrhi3_one_bit"
13581 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13582 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
13583 (match_operand:QI 2 "const1_operand" "")))
13584 (clobber (reg:CC FLAGS_REG))]
13585 "(TARGET_SHIFT1 || optimize_size)
13586 && ix86_binary_operator_ok (ROTATERT, HImode, operands)"
13588 [(set_attr "type" "rotate")
13589 (set (attr "length")
13590 (if_then_else (match_operand 0 "register_operand" "")
13592 (const_string "*")))])
13594 (define_insn "*rotrhi3_1"
13595 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
13596 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
13597 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13598 (clobber (reg:CC FLAGS_REG))]
13599 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
13601 ror{w}\t{%2, %0|%0, %2}
13602 ror{w}\t{%b2, %0|%0, %b2}"
13603 [(set_attr "type" "rotate")
13604 (set_attr "mode" "HI")])
13607 [(set (match_operand:HI 0 "register_operand" "")
13608 (rotatert:HI (match_dup 0) (const_int 8)))
13609 (clobber (reg:CC FLAGS_REG))]
13611 [(parallel [(set (strict_low_part (match_dup 0))
13612 (bswap:HI (match_dup 0)))
13613 (clobber (reg:CC FLAGS_REG))])]
13616 (define_expand "rotrqi3"
13617 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13618 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
13619 (match_operand:QI 2 "nonmemory_operand" "")))
13620 (clobber (reg:CC FLAGS_REG))]
13621 "TARGET_QIMODE_MATH"
13622 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
13624 (define_insn "*rotrqi3_1_one_bit"
13625 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13626 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
13627 (match_operand:QI 2 "const1_operand" "")))
13628 (clobber (reg:CC FLAGS_REG))]
13629 "(TARGET_SHIFT1 || optimize_size)
13630 && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13632 [(set_attr "type" "rotate")
13633 (set (attr "length")
13634 (if_then_else (match_operand 0 "register_operand" "")
13636 (const_string "*")))])
13638 (define_insn "*rotrqi3_1_one_bit_slp"
13639 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13640 (rotatert:QI (match_dup 0)
13641 (match_operand:QI 1 "const1_operand" "")))
13642 (clobber (reg:CC FLAGS_REG))]
13643 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13644 && (TARGET_SHIFT1 || optimize_size)"
13646 [(set_attr "type" "rotate1")
13647 (set (attr "length")
13648 (if_then_else (match_operand 0 "register_operand" "")
13650 (const_string "*")))])
13652 (define_insn "*rotrqi3_1"
13653 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13654 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13655 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13656 (clobber (reg:CC FLAGS_REG))]
13657 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13659 ror{b}\t{%2, %0|%0, %2}
13660 ror{b}\t{%b2, %0|%0, %b2}"
13661 [(set_attr "type" "rotate")
13662 (set_attr "mode" "QI")])
13664 (define_insn "*rotrqi3_1_slp"
13665 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13666 (rotatert:QI (match_dup 0)
13667 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13668 (clobber (reg:CC FLAGS_REG))]
13669 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13670 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13672 ror{b}\t{%1, %0|%0, %1}
13673 ror{b}\t{%b1, %0|%0, %b1}"
13674 [(set_attr "type" "rotate1")
13675 (set_attr "mode" "QI")])
13677 ;; Bit set / bit test instructions
13679 (define_expand "extv"
13680 [(set (match_operand:SI 0 "register_operand" "")
13681 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
13682 (match_operand:SI 2 "const8_operand" "")
13683 (match_operand:SI 3 "const8_operand" "")))]
13686 /* Handle extractions from %ah et al. */
13687 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13690 /* From mips.md: extract_bit_field doesn't verify that our source
13691 matches the predicate, so check it again here. */
13692 if (! ext_register_operand (operands[1], VOIDmode))
13696 (define_expand "extzv"
13697 [(set (match_operand:SI 0 "register_operand" "")
13698 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
13699 (match_operand:SI 2 "const8_operand" "")
13700 (match_operand:SI 3 "const8_operand" "")))]
13703 /* Handle extractions from %ah et al. */
13704 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13707 /* From mips.md: extract_bit_field doesn't verify that our source
13708 matches the predicate, so check it again here. */
13709 if (! ext_register_operand (operands[1], VOIDmode))
13713 (define_expand "insv"
13714 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
13715 (match_operand 1 "const8_operand" "")
13716 (match_operand 2 "const8_operand" ""))
13717 (match_operand 3 "register_operand" ""))]
13720 /* Handle insertions to %ah et al. */
13721 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
13724 /* From mips.md: insert_bit_field doesn't verify that our source
13725 matches the predicate, so check it again here. */
13726 if (! ext_register_operand (operands[0], VOIDmode))
13730 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
13732 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
13737 ;; %%% bts, btr, btc, bt.
13738 ;; In general these instructions are *slow* when applied to memory,
13739 ;; since they enforce atomic operation. When applied to registers,
13740 ;; it depends on the cpu implementation. They're never faster than
13741 ;; the corresponding and/ior/xor operations, so with 32-bit there's
13742 ;; no point. But in 64-bit, we can't hold the relevant immediates
13743 ;; within the instruction itself, so operating on bits in the high
13744 ;; 32-bits of a register becomes easier.
13746 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
13747 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
13748 ;; negdf respectively, so they can never be disabled entirely.
13750 (define_insn "*btsq"
13751 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
13753 (match_operand:DI 1 "const_0_to_63_operand" ""))
13755 (clobber (reg:CC FLAGS_REG))]
13756 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
13758 [(set_attr "type" "alu1")])
13760 (define_insn "*btrq"
13761 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
13763 (match_operand:DI 1 "const_0_to_63_operand" ""))
13765 (clobber (reg:CC FLAGS_REG))]
13766 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
13768 [(set_attr "type" "alu1")])
13770 (define_insn "*btcq"
13771 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
13773 (match_operand:DI 1 "const_0_to_63_operand" ""))
13774 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
13775 (clobber (reg:CC FLAGS_REG))]
13776 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
13778 [(set_attr "type" "alu1")])
13780 ;; Allow Nocona to avoid these instructions if a register is available.
13783 [(match_scratch:DI 2 "r")
13784 (parallel [(set (zero_extract:DI
13785 (match_operand:DI 0 "register_operand" "")
13787 (match_operand:DI 1 "const_0_to_63_operand" ""))
13789 (clobber (reg:CC FLAGS_REG))])]
13790 "TARGET_64BIT && !TARGET_USE_BT"
13793 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
13796 if (HOST_BITS_PER_WIDE_INT >= 64)
13797 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13798 else if (i < HOST_BITS_PER_WIDE_INT)
13799 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13801 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
13803 op1 = immed_double_const (lo, hi, DImode);
13806 emit_move_insn (operands[2], op1);
13810 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
13815 [(match_scratch:DI 2 "r")
13816 (parallel [(set (zero_extract:DI
13817 (match_operand:DI 0 "register_operand" "")
13819 (match_operand:DI 1 "const_0_to_63_operand" ""))
13821 (clobber (reg:CC FLAGS_REG))])]
13822 "TARGET_64BIT && !TARGET_USE_BT"
13825 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
13828 if (HOST_BITS_PER_WIDE_INT >= 64)
13829 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13830 else if (i < HOST_BITS_PER_WIDE_INT)
13831 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13833 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
13835 op1 = immed_double_const (~lo, ~hi, DImode);
13838 emit_move_insn (operands[2], op1);
13842 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
13847 [(match_scratch:DI 2 "r")
13848 (parallel [(set (zero_extract:DI
13849 (match_operand:DI 0 "register_operand" "")
13851 (match_operand:DI 1 "const_0_to_63_operand" ""))
13852 (not:DI (zero_extract:DI
13853 (match_dup 0) (const_int 1) (match_dup 1))))
13854 (clobber (reg:CC FLAGS_REG))])]
13855 "TARGET_64BIT && !TARGET_USE_BT"
13858 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
13861 if (HOST_BITS_PER_WIDE_INT >= 64)
13862 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13863 else if (i < HOST_BITS_PER_WIDE_INT)
13864 lo = (HOST_WIDE_INT)1 << i, hi = 0;
13866 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
13868 op1 = immed_double_const (lo, hi, DImode);
13871 emit_move_insn (operands[2], op1);
13875 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
13879 ;; Store-flag instructions.
13881 ;; For all sCOND expanders, also expand the compare or test insn that
13882 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
13884 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
13885 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
13886 ;; way, which can later delete the movzx if only QImode is needed.
13888 (define_expand "seq"
13889 [(set (match_operand:QI 0 "register_operand" "")
13890 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
13892 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
13894 (define_expand "sne"
13895 [(set (match_operand:QI 0 "register_operand" "")
13896 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
13898 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
13900 (define_expand "sgt"
13901 [(set (match_operand:QI 0 "register_operand" "")
13902 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
13904 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
13906 (define_expand "sgtu"
13907 [(set (match_operand:QI 0 "register_operand" "")
13908 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
13910 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
13912 (define_expand "slt"
13913 [(set (match_operand:QI 0 "register_operand" "")
13914 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
13916 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
13918 (define_expand "sltu"
13919 [(set (match_operand:QI 0 "register_operand" "")
13920 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
13922 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
13924 (define_expand "sge"
13925 [(set (match_operand:QI 0 "register_operand" "")
13926 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
13928 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
13930 (define_expand "sgeu"
13931 [(set (match_operand:QI 0 "register_operand" "")
13932 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
13934 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
13936 (define_expand "sle"
13937 [(set (match_operand:QI 0 "register_operand" "")
13938 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
13940 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
13942 (define_expand "sleu"
13943 [(set (match_operand:QI 0 "register_operand" "")
13944 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
13946 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
13948 (define_expand "sunordered"
13949 [(set (match_operand:QI 0 "register_operand" "")
13950 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
13951 "TARGET_80387 || TARGET_SSE"
13952 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
13954 (define_expand "sordered"
13955 [(set (match_operand:QI 0 "register_operand" "")
13956 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
13958 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
13960 (define_expand "suneq"
13961 [(set (match_operand:QI 0 "register_operand" "")
13962 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
13963 "TARGET_80387 || TARGET_SSE"
13964 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
13966 (define_expand "sunge"
13967 [(set (match_operand:QI 0 "register_operand" "")
13968 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
13969 "TARGET_80387 || TARGET_SSE"
13970 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
13972 (define_expand "sungt"
13973 [(set (match_operand:QI 0 "register_operand" "")
13974 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
13975 "TARGET_80387 || TARGET_SSE"
13976 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
13978 (define_expand "sunle"
13979 [(set (match_operand:QI 0 "register_operand" "")
13980 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
13981 "TARGET_80387 || TARGET_SSE"
13982 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
13984 (define_expand "sunlt"
13985 [(set (match_operand:QI 0 "register_operand" "")
13986 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
13987 "TARGET_80387 || TARGET_SSE"
13988 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
13990 (define_expand "sltgt"
13991 [(set (match_operand:QI 0 "register_operand" "")
13992 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
13993 "TARGET_80387 || TARGET_SSE"
13994 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
13996 (define_insn "*setcc_1"
13997 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13998 (match_operator:QI 1 "ix86_comparison_operator"
13999 [(reg FLAGS_REG) (const_int 0)]))]
14002 [(set_attr "type" "setcc")
14003 (set_attr "mode" "QI")])
14005 (define_insn "*setcc_2"
14006 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
14007 (match_operator:QI 1 "ix86_comparison_operator"
14008 [(reg FLAGS_REG) (const_int 0)]))]
14011 [(set_attr "type" "setcc")
14012 (set_attr "mode" "QI")])
14014 ;; In general it is not safe to assume too much about CCmode registers,
14015 ;; so simplify-rtx stops when it sees a second one. Under certain
14016 ;; conditions this is safe on x86, so help combine not create
14023 [(set (match_operand:QI 0 "nonimmediate_operand" "")
14024 (ne:QI (match_operator 1 "ix86_comparison_operator"
14025 [(reg FLAGS_REG) (const_int 0)])
14028 [(set (match_dup 0) (match_dup 1))]
14030 PUT_MODE (operands[1], QImode);
14034 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
14035 (ne:QI (match_operator 1 "ix86_comparison_operator"
14036 [(reg FLAGS_REG) (const_int 0)])
14039 [(set (match_dup 0) (match_dup 1))]
14041 PUT_MODE (operands[1], QImode);
14045 [(set (match_operand:QI 0 "nonimmediate_operand" "")
14046 (eq:QI (match_operator 1 "ix86_comparison_operator"
14047 [(reg FLAGS_REG) (const_int 0)])
14050 [(set (match_dup 0) (match_dup 1))]
14052 rtx new_op1 = copy_rtx (operands[1]);
14053 operands[1] = new_op1;
14054 PUT_MODE (new_op1, QImode);
14055 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
14056 GET_MODE (XEXP (new_op1, 0))));
14058 /* Make sure that (a) the CCmode we have for the flags is strong
14059 enough for the reversed compare or (b) we have a valid FP compare. */
14060 if (! ix86_comparison_operator (new_op1, VOIDmode))
14065 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
14066 (eq:QI (match_operator 1 "ix86_comparison_operator"
14067 [(reg FLAGS_REG) (const_int 0)])
14070 [(set (match_dup 0) (match_dup 1))]
14072 rtx new_op1 = copy_rtx (operands[1]);
14073 operands[1] = new_op1;
14074 PUT_MODE (new_op1, QImode);
14075 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
14076 GET_MODE (XEXP (new_op1, 0))));
14078 /* Make sure that (a) the CCmode we have for the flags is strong
14079 enough for the reversed compare or (b) we have a valid FP compare. */
14080 if (! ix86_comparison_operator (new_op1, VOIDmode))
14084 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
14085 ;; subsequent logical operations are used to imitate conditional moves.
14086 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
14089 (define_insn "*sse_setccsf"
14090 [(set (match_operand:SF 0 "register_operand" "=x")
14091 (match_operator:SF 1 "sse_comparison_operator"
14092 [(match_operand:SF 2 "register_operand" "0")
14093 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
14094 "TARGET_SSE && !TARGET_SSE5"
14095 "cmp%D1ss\t{%3, %0|%0, %3}"
14096 [(set_attr "type" "ssecmp")
14097 (set_attr "mode" "SF")])
14099 (define_insn "*sse_setccdf"
14100 [(set (match_operand:DF 0 "register_operand" "=x")
14101 (match_operator:DF 1 "sse_comparison_operator"
14102 [(match_operand:DF 2 "register_operand" "0")
14103 (match_operand:DF 3 "nonimmediate_operand" "xm")]))]
14104 "TARGET_SSE2 && !TARGET_SSE5"
14105 "cmp%D1sd\t{%3, %0|%0, %3}"
14106 [(set_attr "type" "ssecmp")
14107 (set_attr "mode" "DF")])
14109 (define_insn "*sse5_setcc<mode>"
14110 [(set (match_operand:MODEF 0 "register_operand" "=x")
14111 (match_operator:MODEF 1 "sse5_comparison_float_operator"
14112 [(match_operand:MODEF 2 "register_operand" "x")
14113 (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
14115 "com%Y1ss\t{%3, %2, %0|%0, %2, %3}"
14116 [(set_attr "type" "sse4arg")
14117 (set_attr "mode" "<MODE>")])
14120 ;; Basic conditional jump instructions.
14121 ;; We ignore the overflow flag for signed branch instructions.
14123 ;; For all bCOND expanders, also expand the compare or test insn that
14124 ;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
14126 (define_expand "beq"
14128 (if_then_else (match_dup 1)
14129 (label_ref (match_operand 0 "" ""))
14132 "ix86_expand_branch (EQ, operands[0]); DONE;")
14134 (define_expand "bne"
14136 (if_then_else (match_dup 1)
14137 (label_ref (match_operand 0 "" ""))
14140 "ix86_expand_branch (NE, operands[0]); DONE;")
14142 (define_expand "bgt"
14144 (if_then_else (match_dup 1)
14145 (label_ref (match_operand 0 "" ""))
14148 "ix86_expand_branch (GT, operands[0]); DONE;")
14150 (define_expand "bgtu"
14152 (if_then_else (match_dup 1)
14153 (label_ref (match_operand 0 "" ""))
14156 "ix86_expand_branch (GTU, operands[0]); DONE;")
14158 (define_expand "blt"
14160 (if_then_else (match_dup 1)
14161 (label_ref (match_operand 0 "" ""))
14164 "ix86_expand_branch (LT, operands[0]); DONE;")
14166 (define_expand "bltu"
14168 (if_then_else (match_dup 1)
14169 (label_ref (match_operand 0 "" ""))
14172 "ix86_expand_branch (LTU, operands[0]); DONE;")
14174 (define_expand "bge"
14176 (if_then_else (match_dup 1)
14177 (label_ref (match_operand 0 "" ""))
14180 "ix86_expand_branch (GE, operands[0]); DONE;")
14182 (define_expand "bgeu"
14184 (if_then_else (match_dup 1)
14185 (label_ref (match_operand 0 "" ""))
14188 "ix86_expand_branch (GEU, operands[0]); DONE;")
14190 (define_expand "ble"
14192 (if_then_else (match_dup 1)
14193 (label_ref (match_operand 0 "" ""))
14196 "ix86_expand_branch (LE, operands[0]); DONE;")
14198 (define_expand "bleu"
14200 (if_then_else (match_dup 1)
14201 (label_ref (match_operand 0 "" ""))
14204 "ix86_expand_branch (LEU, operands[0]); DONE;")
14206 (define_expand "bunordered"
14208 (if_then_else (match_dup 1)
14209 (label_ref (match_operand 0 "" ""))
14211 "TARGET_80387 || TARGET_SSE_MATH"
14212 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
14214 (define_expand "bordered"
14216 (if_then_else (match_dup 1)
14217 (label_ref (match_operand 0 "" ""))
14219 "TARGET_80387 || TARGET_SSE_MATH"
14220 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
14222 (define_expand "buneq"
14224 (if_then_else (match_dup 1)
14225 (label_ref (match_operand 0 "" ""))
14227 "TARGET_80387 || TARGET_SSE_MATH"
14228 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
14230 (define_expand "bunge"
14232 (if_then_else (match_dup 1)
14233 (label_ref (match_operand 0 "" ""))
14235 "TARGET_80387 || TARGET_SSE_MATH"
14236 "ix86_expand_branch (UNGE, operands[0]); DONE;")
14238 (define_expand "bungt"
14240 (if_then_else (match_dup 1)
14241 (label_ref (match_operand 0 "" ""))
14243 "TARGET_80387 || TARGET_SSE_MATH"
14244 "ix86_expand_branch (UNGT, operands[0]); DONE;")
14246 (define_expand "bunle"
14248 (if_then_else (match_dup 1)
14249 (label_ref (match_operand 0 "" ""))
14251 "TARGET_80387 || TARGET_SSE_MATH"
14252 "ix86_expand_branch (UNLE, operands[0]); DONE;")
14254 (define_expand "bunlt"
14256 (if_then_else (match_dup 1)
14257 (label_ref (match_operand 0 "" ""))
14259 "TARGET_80387 || TARGET_SSE_MATH"
14260 "ix86_expand_branch (UNLT, operands[0]); DONE;")
14262 (define_expand "bltgt"
14264 (if_then_else (match_dup 1)
14265 (label_ref (match_operand 0 "" ""))
14267 "TARGET_80387 || TARGET_SSE_MATH"
14268 "ix86_expand_branch (LTGT, operands[0]); DONE;")
14270 (define_insn "*jcc_1"
14272 (if_then_else (match_operator 1 "ix86_comparison_operator"
14273 [(reg FLAGS_REG) (const_int 0)])
14274 (label_ref (match_operand 0 "" ""))
14278 [(set_attr "type" "ibr")
14279 (set_attr "modrm" "0")
14280 (set (attr "length")
14281 (if_then_else (and (ge (minus (match_dup 0) (pc))
14283 (lt (minus (match_dup 0) (pc))
14288 (define_insn "*jcc_2"
14290 (if_then_else (match_operator 1 "ix86_comparison_operator"
14291 [(reg FLAGS_REG) (const_int 0)])
14293 (label_ref (match_operand 0 "" ""))))]
14296 [(set_attr "type" "ibr")
14297 (set_attr "modrm" "0")
14298 (set (attr "length")
14299 (if_then_else (and (ge (minus (match_dup 0) (pc))
14301 (lt (minus (match_dup 0) (pc))
14306 ;; In general it is not safe to assume too much about CCmode registers,
14307 ;; so simplify-rtx stops when it sees a second one. Under certain
14308 ;; conditions this is safe on x86, so help combine not create
14316 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
14317 [(reg FLAGS_REG) (const_int 0)])
14319 (label_ref (match_operand 1 "" ""))
14323 (if_then_else (match_dup 0)
14324 (label_ref (match_dup 1))
14327 PUT_MODE (operands[0], VOIDmode);
14332 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
14333 [(reg FLAGS_REG) (const_int 0)])
14335 (label_ref (match_operand 1 "" ""))
14339 (if_then_else (match_dup 0)
14340 (label_ref (match_dup 1))
14343 rtx new_op0 = copy_rtx (operands[0]);
14344 operands[0] = new_op0;
14345 PUT_MODE (new_op0, VOIDmode);
14346 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
14347 GET_MODE (XEXP (new_op0, 0))));
14349 /* Make sure that (a) the CCmode we have for the flags is strong
14350 enough for the reversed compare or (b) we have a valid FP compare. */
14351 if (! ix86_comparison_operator (new_op0, VOIDmode))
14355 ;; Define combination compare-and-branch fp compare instructions to use
14356 ;; during early optimization. Splitting the operation apart early makes
14357 ;; for bad code when we want to reverse the operation.
14359 (define_insn "*fp_jcc_1_mixed"
14361 (if_then_else (match_operator 0 "comparison_operator"
14362 [(match_operand 1 "register_operand" "f,x")
14363 (match_operand 2 "nonimmediate_operand" "f,xm")])
14364 (label_ref (match_operand 3 "" ""))
14366 (clobber (reg:CCFP FPSR_REG))
14367 (clobber (reg:CCFP FLAGS_REG))]
14368 "TARGET_MIX_SSE_I387
14369 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
14370 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14371 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14374 (define_insn "*fp_jcc_1_sse"
14376 (if_then_else (match_operator 0 "comparison_operator"
14377 [(match_operand 1 "register_operand" "x")
14378 (match_operand 2 "nonimmediate_operand" "xm")])
14379 (label_ref (match_operand 3 "" ""))
14381 (clobber (reg:CCFP FPSR_REG))
14382 (clobber (reg:CCFP FLAGS_REG))]
14384 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
14385 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14386 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14389 (define_insn "*fp_jcc_1_387"
14391 (if_then_else (match_operator 0 "comparison_operator"
14392 [(match_operand 1 "register_operand" "f")
14393 (match_operand 2 "register_operand" "f")])
14394 (label_ref (match_operand 3 "" ""))
14396 (clobber (reg:CCFP FPSR_REG))
14397 (clobber (reg:CCFP FLAGS_REG))]
14398 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
14400 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14401 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14404 (define_insn "*fp_jcc_2_mixed"
14406 (if_then_else (match_operator 0 "comparison_operator"
14407 [(match_operand 1 "register_operand" "f,x")
14408 (match_operand 2 "nonimmediate_operand" "f,xm")])
14410 (label_ref (match_operand 3 "" ""))))
14411 (clobber (reg:CCFP FPSR_REG))
14412 (clobber (reg:CCFP FLAGS_REG))]
14413 "TARGET_MIX_SSE_I387
14414 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
14415 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14416 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14419 (define_insn "*fp_jcc_2_sse"
14421 (if_then_else (match_operator 0 "comparison_operator"
14422 [(match_operand 1 "register_operand" "x")
14423 (match_operand 2 "nonimmediate_operand" "xm")])
14425 (label_ref (match_operand 3 "" ""))))
14426 (clobber (reg:CCFP FPSR_REG))
14427 (clobber (reg:CCFP FLAGS_REG))]
14429 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
14430 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14431 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14434 (define_insn "*fp_jcc_2_387"
14436 (if_then_else (match_operator 0 "comparison_operator"
14437 [(match_operand 1 "register_operand" "f")
14438 (match_operand 2 "register_operand" "f")])
14440 (label_ref (match_operand 3 "" ""))))
14441 (clobber (reg:CCFP FPSR_REG))
14442 (clobber (reg:CCFP FLAGS_REG))]
14443 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
14445 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14446 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14449 (define_insn "*fp_jcc_3_387"
14451 (if_then_else (match_operator 0 "comparison_operator"
14452 [(match_operand 1 "register_operand" "f")
14453 (match_operand 2 "nonimmediate_operand" "fm")])
14454 (label_ref (match_operand 3 "" ""))
14456 (clobber (reg:CCFP FPSR_REG))
14457 (clobber (reg:CCFP FLAGS_REG))
14458 (clobber (match_scratch:HI 4 "=a"))]
14460 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
14461 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14462 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
14463 && SELECT_CC_MODE (GET_CODE (operands[0]),
14464 operands[1], operands[2]) == CCFPmode
14465 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14468 (define_insn "*fp_jcc_4_387"
14470 (if_then_else (match_operator 0 "comparison_operator"
14471 [(match_operand 1 "register_operand" "f")
14472 (match_operand 2 "nonimmediate_operand" "fm")])
14474 (label_ref (match_operand 3 "" ""))))
14475 (clobber (reg:CCFP FPSR_REG))
14476 (clobber (reg:CCFP FLAGS_REG))
14477 (clobber (match_scratch:HI 4 "=a"))]
14479 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
14480 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14481 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
14482 && SELECT_CC_MODE (GET_CODE (operands[0]),
14483 operands[1], operands[2]) == CCFPmode
14484 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14487 (define_insn "*fp_jcc_5_387"
14489 (if_then_else (match_operator 0 "comparison_operator"
14490 [(match_operand 1 "register_operand" "f")
14491 (match_operand 2 "register_operand" "f")])
14492 (label_ref (match_operand 3 "" ""))
14494 (clobber (reg:CCFP FPSR_REG))
14495 (clobber (reg:CCFP FLAGS_REG))
14496 (clobber (match_scratch:HI 4 "=a"))]
14497 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
14498 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14499 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14502 (define_insn "*fp_jcc_6_387"
14504 (if_then_else (match_operator 0 "comparison_operator"
14505 [(match_operand 1 "register_operand" "f")
14506 (match_operand 2 "register_operand" "f")])
14508 (label_ref (match_operand 3 "" ""))))
14509 (clobber (reg:CCFP FPSR_REG))
14510 (clobber (reg:CCFP FLAGS_REG))
14511 (clobber (match_scratch:HI 4 "=a"))]
14512 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
14513 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14514 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14517 (define_insn "*fp_jcc_7_387"
14519 (if_then_else (match_operator 0 "comparison_operator"
14520 [(match_operand 1 "register_operand" "f")
14521 (match_operand 2 "const0_operand" "X")])
14522 (label_ref (match_operand 3 "" ""))
14524 (clobber (reg:CCFP FPSR_REG))
14525 (clobber (reg:CCFP FLAGS_REG))
14526 (clobber (match_scratch:HI 4 "=a"))]
14527 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
14528 && GET_MODE (operands[1]) == GET_MODE (operands[2])
14529 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
14530 && SELECT_CC_MODE (GET_CODE (operands[0]),
14531 operands[1], operands[2]) == CCFPmode
14532 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
14535 ;; The order of operands in *fp_jcc_8_387 is forced by combine in
14536 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
14537 ;; with a precedence over other operators and is always put in the first
14538 ;; place. Swap condition and operands to match ficom instruction.
14540 (define_insn "*fp_jcc_8<mode>_387"
14542 (if_then_else (match_operator 0 "comparison_operator"
14543 [(match_operator 1 "float_operator"
14544 [(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
14545 (match_operand 3 "register_operand" "f,f")])
14546 (label_ref (match_operand 4 "" ""))
14548 (clobber (reg:CCFP FPSR_REG))
14549 (clobber (reg:CCFP FLAGS_REG))
14550 (clobber (match_scratch:HI 5 "=a,a"))]
14551 "X87_FLOAT_MODE_P (GET_MODE (operands[3]))
14552 && TARGET_USE_<MODE>MODE_FIOP
14553 && GET_MODE (operands[1]) == GET_MODE (operands[3])
14554 && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
14555 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
14556 && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
14561 (if_then_else (match_operator 0 "comparison_operator"
14562 [(match_operand 1 "register_operand" "")
14563 (match_operand 2 "nonimmediate_operand" "")])
14564 (match_operand 3 "" "")
14565 (match_operand 4 "" "")))
14566 (clobber (reg:CCFP FPSR_REG))
14567 (clobber (reg:CCFP FLAGS_REG))]
14571 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
14572 operands[3], operands[4], NULL_RTX, NULL_RTX);
14578 (if_then_else (match_operator 0 "comparison_operator"
14579 [(match_operand 1 "register_operand" "")
14580 (match_operand 2 "general_operand" "")])
14581 (match_operand 3 "" "")
14582 (match_operand 4 "" "")))
14583 (clobber (reg:CCFP FPSR_REG))
14584 (clobber (reg:CCFP FLAGS_REG))
14585 (clobber (match_scratch:HI 5 "=a"))]
14589 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
14590 operands[3], operands[4], operands[5], NULL_RTX);
14596 (if_then_else (match_operator 0 "comparison_operator"
14597 [(match_operator 1 "float_operator"
14598 [(match_operand:X87MODEI12 2 "memory_operand" "")])
14599 (match_operand 3 "register_operand" "")])
14600 (match_operand 4 "" "")
14601 (match_operand 5 "" "")))
14602 (clobber (reg:CCFP FPSR_REG))
14603 (clobber (reg:CCFP FLAGS_REG))
14604 (clobber (match_scratch:HI 6 "=a"))]
14608 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
14609 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
14610 operands[3], operands[7],
14611 operands[4], operands[5], operands[6], NULL_RTX);
14615 ;; %%% Kill this when reload knows how to do it.
14618 (if_then_else (match_operator 0 "comparison_operator"
14619 [(match_operator 1 "float_operator"
14620 [(match_operand:X87MODEI12 2 "register_operand" "")])
14621 (match_operand 3 "register_operand" "")])
14622 (match_operand 4 "" "")
14623 (match_operand 5 "" "")))
14624 (clobber (reg:CCFP FPSR_REG))
14625 (clobber (reg:CCFP FLAGS_REG))
14626 (clobber (match_scratch:HI 6 "=a"))]
14630 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14631 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
14632 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
14633 operands[3], operands[7],
14634 operands[4], operands[5], operands[6], operands[2]);
14638 ;; Unconditional and other jump instructions
14640 (define_insn "jump"
14642 (label_ref (match_operand 0 "" "")))]
14645 [(set_attr "type" "ibr")
14646 (set (attr "length")
14647 (if_then_else (and (ge (minus (match_dup 0) (pc))
14649 (lt (minus (match_dup 0) (pc))
14653 (set_attr "modrm" "0")])
14655 (define_expand "indirect_jump"
14656 [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
14660 (define_insn "*indirect_jump"
14661 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
14664 [(set_attr "type" "ibr")
14665 (set_attr "length_immediate" "0")])
14667 (define_insn "*indirect_jump_rtx64"
14668 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
14671 [(set_attr "type" "ibr")
14672 (set_attr "length_immediate" "0")])
14674 (define_expand "tablejump"
14675 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" ""))
14676 (use (label_ref (match_operand 1 "" "")))])]
14679 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
14680 relative. Convert the relative address to an absolute address. */
14684 enum rtx_code code;
14686 /* We can't use @GOTOFF for text labels on VxWorks;
14687 see gotoff_operand. */
14688 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
14692 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
14694 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
14698 op1 = pic_offset_table_rtx;
14703 op0 = pic_offset_table_rtx;
14707 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
14712 (define_insn "*tablejump_1"
14713 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
14714 (use (label_ref (match_operand 1 "" "")))]
14717 [(set_attr "type" "ibr")
14718 (set_attr "length_immediate" "0")])
14720 (define_insn "*tablejump_1_rtx64"
14721 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
14722 (use (label_ref (match_operand 1 "" "")))]
14725 [(set_attr "type" "ibr")
14726 (set_attr "length_immediate" "0")])
14728 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
14731 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
14732 (set (match_operand:QI 1 "register_operand" "")
14733 (match_operator:QI 2 "ix86_comparison_operator"
14734 [(reg FLAGS_REG) (const_int 0)]))
14735 (set (match_operand 3 "q_regs_operand" "")
14736 (zero_extend (match_dup 1)))]
14737 "(peep2_reg_dead_p (3, operands[1])
14738 || operands_match_p (operands[1], operands[3]))
14739 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
14740 [(set (match_dup 4) (match_dup 0))
14741 (set (strict_low_part (match_dup 5))
14744 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
14745 operands[5] = gen_lowpart (QImode, operands[3]);
14746 ix86_expand_clear (operands[3]);
14749 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
14752 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
14753 (set (match_operand:QI 1 "register_operand" "")
14754 (match_operator:QI 2 "ix86_comparison_operator"
14755 [(reg FLAGS_REG) (const_int 0)]))
14756 (parallel [(set (match_operand 3 "q_regs_operand" "")
14757 (zero_extend (match_dup 1)))
14758 (clobber (reg:CC FLAGS_REG))])]
14759 "(peep2_reg_dead_p (3, operands[1])
14760 || operands_match_p (operands[1], operands[3]))
14761 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
14762 [(set (match_dup 4) (match_dup 0))
14763 (set (strict_low_part (match_dup 5))
14766 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
14767 operands[5] = gen_lowpart (QImode, operands[3]);
14768 ix86_expand_clear (operands[3]);
14771 ;; Call instructions.
14773 ;; The predicates normally associated with named expanders are not properly
14774 ;; checked for calls. This is a bug in the generic code, but it isn't that
14775 ;; easy to fix. Ignore it for now and be prepared to fix things up.
14777 ;; Call subroutine returning no value.
14779 (define_expand "call_pop"
14780 [(parallel [(call (match_operand:QI 0 "" "")
14781 (match_operand:SI 1 "" ""))
14782 (set (reg:SI SP_REG)
14783 (plus:SI (reg:SI SP_REG)
14784 (match_operand:SI 3 "" "")))])]
14787 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
14791 (define_insn "*call_pop_0"
14792 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
14793 (match_operand:SI 1 "" ""))
14794 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
14795 (match_operand:SI 2 "immediate_operand" "")))]
14798 if (SIBLING_CALL_P (insn))
14801 return "call\t%P0";
14803 [(set_attr "type" "call")])
14805 (define_insn "*call_pop_1"
14806 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14807 (match_operand:SI 1 "" ""))
14808 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
14809 (match_operand:SI 2 "immediate_operand" "i")))]
14812 if (constant_call_address_operand (operands[0], Pmode))
14814 if (SIBLING_CALL_P (insn))
14817 return "call\t%P0";
14819 if (SIBLING_CALL_P (insn))
14822 return "call\t%A0";
14824 [(set_attr "type" "call")])
14826 (define_expand "call"
14827 [(call (match_operand:QI 0 "" "")
14828 (match_operand 1 "" ""))
14829 (use (match_operand 2 "" ""))]
14832 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
14836 (define_expand "sibcall"
14837 [(call (match_operand:QI 0 "" "")
14838 (match_operand 1 "" ""))
14839 (use (match_operand 2 "" ""))]
14842 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
14846 (define_insn "*call_0"
14847 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
14848 (match_operand 1 "" ""))]
14851 if (SIBLING_CALL_P (insn))
14854 return "call\t%P0";
14856 [(set_attr "type" "call")])
14858 (define_insn "*call_1"
14859 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14860 (match_operand 1 "" ""))]
14861 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
14863 if (constant_call_address_operand (operands[0], Pmode))
14864 return "call\t%P0";
14865 return "call\t%A0";
14867 [(set_attr "type" "call")])
14869 (define_insn "*sibcall_1"
14870 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
14871 (match_operand 1 "" ""))]
14872 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
14874 if (constant_call_address_operand (operands[0], Pmode))
14878 [(set_attr "type" "call")])
14880 (define_insn "*call_1_rex64"
14881 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
14882 (match_operand 1 "" ""))]
14883 "!SIBLING_CALL_P (insn) && TARGET_64BIT
14884 && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
14886 if (constant_call_address_operand (operands[0], Pmode))
14887 return "call\t%P0";
14888 return "call\t%A0";
14890 [(set_attr "type" "call")])
14892 (define_insn "*call_1_rex64_large"
14893 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rm"))
14894 (match_operand 1 "" ""))]
14895 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
14897 [(set_attr "type" "call")])
14899 (define_insn "*sibcall_1_rex64"
14900 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
14901 (match_operand 1 "" ""))]
14902 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14904 [(set_attr "type" "call")])
14906 (define_insn "*sibcall_1_rex64_v"
14907 [(call (mem:QI (reg:DI R11_REG))
14908 (match_operand 0 "" ""))]
14909 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14911 [(set_attr "type" "call")])
14914 ;; Call subroutine, returning value in operand 0
14916 (define_expand "call_value_pop"
14917 [(parallel [(set (match_operand 0 "" "")
14918 (call (match_operand:QI 1 "" "")
14919 (match_operand:SI 2 "" "")))
14920 (set (reg:SI SP_REG)
14921 (plus:SI (reg:SI SP_REG)
14922 (match_operand:SI 4 "" "")))])]
14925 ix86_expand_call (operands[0], operands[1], operands[2],
14926 operands[3], operands[4], 0);
14930 (define_expand "call_value"
14931 [(set (match_operand 0 "" "")
14932 (call (match_operand:QI 1 "" "")
14933 (match_operand:SI 2 "" "")))
14934 (use (match_operand:SI 3 "" ""))]
14935 ;; Operand 2 not used on the i386.
14938 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
14942 (define_expand "sibcall_value"
14943 [(set (match_operand 0 "" "")
14944 (call (match_operand:QI 1 "" "")
14945 (match_operand:SI 2 "" "")))
14946 (use (match_operand:SI 3 "" ""))]
14947 ;; Operand 2 not used on the i386.
14950 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
14954 ;; Call subroutine returning any type.
14956 (define_expand "untyped_call"
14957 [(parallel [(call (match_operand 0 "" "")
14959 (match_operand 1 "" "")
14960 (match_operand 2 "" "")])]
14965 /* In order to give reg-stack an easier job in validating two
14966 coprocessor registers as containing a possible return value,
14967 simply pretend the untyped call returns a complex long double
14970 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
14971 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
14972 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
14975 for (i = 0; i < XVECLEN (operands[2], 0); i++)
14977 rtx set = XVECEXP (operands[2], 0, i);
14978 emit_move_insn (SET_DEST (set), SET_SRC (set));
14981 /* The optimizer does not know that the call sets the function value
14982 registers we stored in the result block. We avoid problems by
14983 claiming that all hard registers are used and clobbered at this
14985 emit_insn (gen_blockage ());
14990 ;; Prologue and epilogue instructions
14992 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
14993 ;; all of memory. This blocks insns from being moved across this point.
14995 (define_insn "blockage"
14996 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
14999 [(set_attr "length" "0")])
15001 ;; As USE insns aren't meaningful after reload, this is used instead
15002 ;; to prevent deleting instructions setting registers for PIC code
15003 (define_insn "prologue_use"
15004 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)]
15007 [(set_attr "length" "0")])
15009 ;; Insn emitted into the body of a function to return from a function.
15010 ;; This is only done if the function's epilogue is known to be simple.
15011 ;; See comments for ix86_can_use_return_insn_p in i386.c.
15013 (define_expand "return"
15015 "ix86_can_use_return_insn_p ()"
15017 if (current_function_pops_args)
15019 rtx popc = GEN_INT (current_function_pops_args);
15020 emit_jump_insn (gen_return_pop_internal (popc));
15025 (define_insn "return_internal"
15029 [(set_attr "length" "1")
15030 (set_attr "length_immediate" "0")
15031 (set_attr "modrm" "0")])
15033 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
15034 ;; instruction Athlon and K8 have.
15036 (define_insn "return_internal_long"
15038 (unspec [(const_int 0)] UNSPEC_REP)]
15041 [(set_attr "length" "1")
15042 (set_attr "length_immediate" "0")
15043 (set_attr "prefix_rep" "1")
15044 (set_attr "modrm" "0")])
15046 (define_insn "return_pop_internal"
15048 (use (match_operand:SI 0 "const_int_operand" ""))]
15051 [(set_attr "length" "3")
15052 (set_attr "length_immediate" "2")
15053 (set_attr "modrm" "0")])
15055 (define_insn "return_indirect_internal"
15057 (use (match_operand:SI 0 "register_operand" "r"))]
15060 [(set_attr "type" "ibr")
15061 (set_attr "length_immediate" "0")])
15067 [(set_attr "length" "1")
15068 (set_attr "length_immediate" "0")
15069 (set_attr "modrm" "0")])
15071 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
15072 ;; branch prediction penalty for the third jump in a 16-byte
15075 (define_insn "align"
15076 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
15079 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
15080 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
15082 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
15083 The align insn is used to avoid 3 jump instructions in the row to improve
15084 branch prediction and the benefits hardly outweigh the cost of extra 8
15085 nops on the average inserted by full alignment pseudo operation. */
15089 [(set_attr "length" "16")])
15091 (define_expand "prologue"
15094 "ix86_expand_prologue (); DONE;")
15096 (define_insn "set_got"
15097 [(set (match_operand:SI 0 "register_operand" "=r")
15098 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
15099 (clobber (reg:CC FLAGS_REG))]
15101 { return output_set_got (operands[0], NULL_RTX); }
15102 [(set_attr "type" "multi")
15103 (set_attr "length" "12")])
15105 (define_insn "set_got_labelled"
15106 [(set (match_operand:SI 0 "register_operand" "=r")
15107 (unspec:SI [(label_ref (match_operand 1 "" ""))]
15109 (clobber (reg:CC FLAGS_REG))]
15111 { return output_set_got (operands[0], operands[1]); }
15112 [(set_attr "type" "multi")
15113 (set_attr "length" "12")])
15115 (define_insn "set_got_rex64"
15116 [(set (match_operand:DI 0 "register_operand" "=r")
15117 (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
15119 "lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
15120 [(set_attr "type" "lea")
15121 (set_attr "length" "6")])
15123 (define_insn "set_rip_rex64"
15124 [(set (match_operand:DI 0 "register_operand" "=r")
15125 (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
15127 "lea{q}\t%l1(%%rip), %0"
15128 [(set_attr "type" "lea")
15129 (set_attr "length" "6")])
15131 (define_insn "set_got_offset_rex64"
15132 [(set (match_operand:DI 0 "register_operand" "=r")
15133 (unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
15135 "movabs{q}\t$_GLOBAL_OFFSET_TABLE_-%l1, %0"
15136 [(set_attr "type" "imov")
15137 (set_attr "length" "11")])
15139 (define_expand "epilogue"
15142 "ix86_expand_epilogue (1); DONE;")
15144 (define_expand "sibcall_epilogue"
15147 "ix86_expand_epilogue (0); DONE;")
15149 (define_expand "eh_return"
15150 [(use (match_operand 0 "register_operand" ""))]
15153 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
15155 /* Tricky bit: we write the address of the handler to which we will
15156 be returning into someone else's stack frame, one word below the
15157 stack address we wish to restore. */
15158 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
15159 tmp = plus_constant (tmp, -UNITS_PER_WORD);
15160 tmp = gen_rtx_MEM (Pmode, tmp);
15161 emit_move_insn (tmp, ra);
15163 if (Pmode == SImode)
15164 emit_jump_insn (gen_eh_return_si (sa));
15166 emit_jump_insn (gen_eh_return_di (sa));
15171 (define_insn_and_split "eh_return_si"
15173 (unspec [(match_operand:SI 0 "register_operand" "c")]
15174 UNSPEC_EH_RETURN))]
15179 "ix86_expand_epilogue (2); DONE;")
15181 (define_insn_and_split "eh_return_di"
15183 (unspec [(match_operand:DI 0 "register_operand" "c")]
15184 UNSPEC_EH_RETURN))]
15189 "ix86_expand_epilogue (2); DONE;")
15191 (define_insn "leave"
15192 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
15193 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
15194 (clobber (mem:BLK (scratch)))]
15197 [(set_attr "type" "leave")])
15199 (define_insn "leave_rex64"
15200 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
15201 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
15202 (clobber (mem:BLK (scratch)))]
15205 [(set_attr "type" "leave")])
15207 (define_expand "ffssi2"
15209 [(set (match_operand:SI 0 "register_operand" "")
15210 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
15211 (clobber (match_scratch:SI 2 ""))
15212 (clobber (reg:CC FLAGS_REG))])]
15217 emit_insn (gen_ffs_cmove (operands[0], operands[1]));
15222 (define_expand "ffs_cmove"
15223 [(set (match_dup 2) (const_int -1))
15224 (parallel [(set (reg:CCZ FLAGS_REG)
15225 (compare:CCZ (match_operand:SI 1 "register_operand" "")
15227 (set (match_operand:SI 0 "nonimmediate_operand" "")
15228 (ctz:SI (match_dup 1)))])
15229 (set (match_dup 0) (if_then_else:SI
15230 (eq (reg:CCZ FLAGS_REG) (const_int 0))
15233 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15234 (clobber (reg:CC FLAGS_REG))])]
15236 "operands[2] = gen_reg_rtx (SImode);")
15238 (define_insn_and_split "*ffs_no_cmove"
15239 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
15240 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
15241 (clobber (match_scratch:SI 2 "=&q"))
15242 (clobber (reg:CC FLAGS_REG))]
15245 "&& reload_completed"
15246 [(parallel [(set (reg:CCZ FLAGS_REG)
15247 (compare:CCZ (match_dup 1) (const_int 0)))
15248 (set (match_dup 0) (ctz:SI (match_dup 1)))])
15249 (set (strict_low_part (match_dup 3))
15250 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
15251 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
15252 (clobber (reg:CC FLAGS_REG))])
15253 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
15254 (clobber (reg:CC FLAGS_REG))])
15255 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15256 (clobber (reg:CC FLAGS_REG))])]
15258 operands[3] = gen_lowpart (QImode, operands[2]);
15259 ix86_expand_clear (operands[2]);
15262 (define_insn "*ffssi_1"
15263 [(set (reg:CCZ FLAGS_REG)
15264 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
15266 (set (match_operand:SI 0 "register_operand" "=r")
15267 (ctz:SI (match_dup 1)))]
15269 "bsf{l}\t{%1, %0|%0, %1}"
15270 [(set_attr "prefix_0f" "1")])
15272 (define_expand "ffsdi2"
15273 [(set (match_dup 2) (const_int -1))
15274 (parallel [(set (reg:CCZ FLAGS_REG)
15275 (compare:CCZ (match_operand:DI 1 "register_operand" "")
15277 (set (match_operand:DI 0 "nonimmediate_operand" "")
15278 (ctz:DI (match_dup 1)))])
15279 (set (match_dup 0) (if_then_else:DI
15280 (eq (reg:CCZ FLAGS_REG) (const_int 0))
15283 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15284 (clobber (reg:CC FLAGS_REG))])]
15286 "operands[2] = gen_reg_rtx (DImode);")
15288 (define_insn "*ffsdi_1"
15289 [(set (reg:CCZ FLAGS_REG)
15290 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
15292 (set (match_operand:DI 0 "register_operand" "=r")
15293 (ctz:DI (match_dup 1)))]
15295 "bsf{q}\t{%1, %0|%0, %1}"
15296 [(set_attr "prefix_0f" "1")])
15298 (define_insn "ctzsi2"
15299 [(set (match_operand:SI 0 "register_operand" "=r")
15300 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
15301 (clobber (reg:CC FLAGS_REG))]
15303 "bsf{l}\t{%1, %0|%0, %1}"
15304 [(set_attr "prefix_0f" "1")])
15306 (define_insn "ctzdi2"
15307 [(set (match_operand:DI 0 "register_operand" "=r")
15308 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
15309 (clobber (reg:CC FLAGS_REG))]
15311 "bsf{q}\t{%1, %0|%0, %1}"
15312 [(set_attr "prefix_0f" "1")])
15314 (define_expand "clzsi2"
15316 [(set (match_operand:SI 0 "register_operand" "")
15317 (minus:SI (const_int 31)
15318 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
15319 (clobber (reg:CC FLAGS_REG))])
15321 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
15322 (clobber (reg:CC FLAGS_REG))])]
15327 emit_insn (gen_clzsi2_abm (operands[0], operands[1]));
15332 (define_insn "clzsi2_abm"
15333 [(set (match_operand:SI 0 "register_operand" "=r")
15334 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))
15335 (clobber (reg:CC FLAGS_REG))]
15337 "lzcnt{l}\t{%1, %0|%0, %1}"
15338 [(set_attr "prefix_rep" "1")
15339 (set_attr "type" "bitmanip")
15340 (set_attr "mode" "SI")])
15342 (define_insn "*bsr"
15343 [(set (match_operand:SI 0 "register_operand" "=r")
15344 (minus:SI (const_int 31)
15345 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
15346 (clobber (reg:CC FLAGS_REG))]
15348 "bsr{l}\t{%1, %0|%0, %1}"
15349 [(set_attr "prefix_0f" "1")
15350 (set_attr "mode" "SI")])
15352 (define_insn "popcountsi2"
15353 [(set (match_operand:SI 0 "register_operand" "=r")
15354 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "")))
15355 (clobber (reg:CC FLAGS_REG))]
15357 "popcnt{l}\t{%1, %0|%0, %1}"
15358 [(set_attr "prefix_rep" "1")
15359 (set_attr "type" "bitmanip")
15360 (set_attr "mode" "SI")])
15362 (define_insn "*popcountsi2_cmp"
15363 [(set (reg FLAGS_REG)
15365 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
15367 (set (match_operand:SI 0 "register_operand" "=r")
15368 (popcount:SI (match_dup 1)))]
15369 "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
15370 "popcnt{l}\t{%1, %0|%0, %1}"
15371 [(set_attr "prefix_rep" "1")
15372 (set_attr "type" "bitmanip")
15373 (set_attr "mode" "SI")])
15375 (define_insn "*popcountsi2_cmp_zext"
15376 [(set (reg FLAGS_REG)
15378 (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
15380 (set (match_operand:DI 0 "register_operand" "=r")
15381 (zero_extend:DI(popcount:SI (match_dup 1))))]
15382 "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
15383 "popcnt{l}\t{%1, %0|%0, %1}"
15384 [(set_attr "prefix_rep" "1")
15385 (set_attr "type" "bitmanip")
15386 (set_attr "mode" "SI")])
15388 (define_expand "bswapsi2"
15389 [(set (match_operand:SI 0 "register_operand" "")
15390 (bswap:SI (match_operand:SI 1 "register_operand" "")))]
15395 rtx x = operands[0];
15397 emit_move_insn (x, operands[1]);
15398 emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
15399 emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
15400 emit_insn (gen_bswaphi_lowpart (gen_lowpart (HImode, x)));
15405 (define_insn "*bswapsi_1"
15406 [(set (match_operand:SI 0 "register_operand" "=r")
15407 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
15410 [(set_attr "prefix_0f" "1")
15411 (set_attr "length" "2")])
15413 (define_insn "*bswaphi_lowpart_1"
15414 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
15415 (bswap:HI (match_dup 0)))
15416 (clobber (reg:CC FLAGS_REG))]
15417 "TARGET_USE_XCHGB || optimize_size"
15419 xchg{b}\t{%h0, %b0|%b0, %h0}
15420 rol{w}\t{$8, %0|%0, 8}"
15421 [(set_attr "length" "2,4")
15422 (set_attr "mode" "QI,HI")])
15424 (define_insn "bswaphi_lowpart"
15425 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
15426 (bswap:HI (match_dup 0)))
15427 (clobber (reg:CC FLAGS_REG))]
15429 "rol{w}\t{$8, %0|%0, 8}"
15430 [(set_attr "length" "4")
15431 (set_attr "mode" "HI")])
15433 (define_insn "bswapdi2"
15434 [(set (match_operand:DI 0 "register_operand" "=r")
15435 (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
15438 [(set_attr "prefix_0f" "1")
15439 (set_attr "length" "3")])
15441 (define_expand "clzdi2"
15443 [(set (match_operand:DI 0 "register_operand" "")
15444 (minus:DI (const_int 63)
15445 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
15446 (clobber (reg:CC FLAGS_REG))])
15448 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
15449 (clobber (reg:CC FLAGS_REG))])]
15454 emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
15459 (define_insn "clzdi2_abm"
15460 [(set (match_operand:DI 0 "register_operand" "=r")
15461 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))
15462 (clobber (reg:CC FLAGS_REG))]
15463 "TARGET_64BIT && TARGET_ABM"
15464 "lzcnt{q}\t{%1, %0|%0, %1}"
15465 [(set_attr "prefix_rep" "1")
15466 (set_attr "type" "bitmanip")
15467 (set_attr "mode" "DI")])
15469 (define_insn "*bsr_rex64"
15470 [(set (match_operand:DI 0 "register_operand" "=r")
15471 (minus:DI (const_int 63)
15472 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
15473 (clobber (reg:CC FLAGS_REG))]
15475 "bsr{q}\t{%1, %0|%0, %1}"
15476 [(set_attr "prefix_0f" "1")
15477 (set_attr "mode" "DI")])
15479 (define_insn "popcountdi2"
15480 [(set (match_operand:DI 0 "register_operand" "=r")
15481 (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "")))
15482 (clobber (reg:CC FLAGS_REG))]
15483 "TARGET_64BIT && TARGET_POPCNT"
15484 "popcnt{q}\t{%1, %0|%0, %1}"
15485 [(set_attr "prefix_rep" "1")
15486 (set_attr "type" "bitmanip")
15487 (set_attr "mode" "DI")])
15489 (define_insn "*popcountdi2_cmp"
15490 [(set (reg FLAGS_REG)
15492 (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
15494 (set (match_operand:DI 0 "register_operand" "=r")
15495 (popcount:DI (match_dup 1)))]
15496 "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
15497 "popcnt{q}\t{%1, %0|%0, %1}"
15498 [(set_attr "prefix_rep" "1")
15499 (set_attr "type" "bitmanip")
15500 (set_attr "mode" "DI")])
15502 (define_expand "clzhi2"
15504 [(set (match_operand:HI 0 "register_operand" "")
15505 (minus:HI (const_int 15)
15506 (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
15507 (clobber (reg:CC FLAGS_REG))])
15509 [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
15510 (clobber (reg:CC FLAGS_REG))])]
15515 emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
15520 (define_insn "clzhi2_abm"
15521 [(set (match_operand:HI 0 "register_operand" "=r")
15522 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))
15523 (clobber (reg:CC FLAGS_REG))]
15525 "lzcnt{w}\t{%1, %0|%0, %1}"
15526 [(set_attr "prefix_rep" "1")
15527 (set_attr "type" "bitmanip")
15528 (set_attr "mode" "HI")])
15530 (define_insn "*bsrhi"
15531 [(set (match_operand:HI 0 "register_operand" "=r")
15532 (minus:HI (const_int 15)
15533 (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
15534 (clobber (reg:CC FLAGS_REG))]
15536 "bsr{w}\t{%1, %0|%0, %1}"
15537 [(set_attr "prefix_0f" "1")
15538 (set_attr "mode" "HI")])
15540 (define_insn "popcounthi2"
15541 [(set (match_operand:HI 0 "register_operand" "=r")
15542 (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "")))
15543 (clobber (reg:CC FLAGS_REG))]
15545 "popcnt{w}\t{%1, %0|%0, %1}"
15546 [(set_attr "prefix_rep" "1")
15547 (set_attr "type" "bitmanip")
15548 (set_attr "mode" "HI")])
15550 (define_insn "*popcounthi2_cmp"
15551 [(set (reg FLAGS_REG)
15553 (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
15555 (set (match_operand:HI 0 "register_operand" "=r")
15556 (popcount:HI (match_dup 1)))]
15557 "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
15558 "popcnt{w}\t{%1, %0|%0, %1}"
15559 [(set_attr "prefix_rep" "1")
15560 (set_attr "type" "bitmanip")
15561 (set_attr "mode" "HI")])
15563 (define_expand "paritydi2"
15564 [(set (match_operand:DI 0 "register_operand" "")
15565 (parity:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
15568 rtx scratch = gen_reg_rtx (QImode);
15571 emit_insn (gen_paritydi2_cmp (NULL_RTX, NULL_RTX,
15572 NULL_RTX, operands[1]));
15574 cond = gen_rtx_fmt_ee (ORDERED, QImode,
15575 gen_rtx_REG (CCmode, FLAGS_REG),
15577 emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
15580 emit_insn (gen_zero_extendqidi2 (operands[0], scratch));
15583 rtx tmp = gen_reg_rtx (SImode);
15585 emit_insn (gen_zero_extendqisi2 (tmp, scratch));
15586 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
15591 (define_insn_and_split "paritydi2_cmp"
15592 [(set (reg:CC FLAGS_REG)
15593 (parity:CC (match_operand:DI 3 "nonimmediate_operand" "0,m")))
15594 (clobber (match_scratch:DI 0 "=r,X"))
15595 (clobber (match_scratch:SI 1 "=r,r"))
15596 (clobber (match_scratch:HI 2 "=Q,Q"))]
15599 "&& reload_completed"
15601 [(set (match_dup 1)
15602 (xor:SI (match_dup 1) (match_dup 4)))
15603 (clobber (reg:CC FLAGS_REG))])
15605 [(set (reg:CC FLAGS_REG)
15606 (parity:CC (match_dup 1)))
15607 (clobber (match_dup 1))
15608 (clobber (match_dup 2))])]
15610 operands[4] = gen_lowpart (SImode, operands[3]);
15612 if (MEM_P (operands[3]))
15613 emit_move_insn (operands[1], gen_highpart (SImode, operands[3]));
15614 else if (! TARGET_64BIT)
15615 operands[1] = gen_highpart (SImode, operands[3]);
15618 emit_move_insn (operands[1], gen_lowpart (SImode, operands[3]));
15619 emit_insn (gen_lshrdi3 (operands[3], operands[3], GEN_INT (32)));
15623 (define_expand "paritysi2"
15624 [(set (match_operand:SI 0 "register_operand" "")
15625 (parity:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
15628 rtx scratch = gen_reg_rtx (QImode);
15631 emit_insn (gen_paritysi2_cmp (NULL_RTX, NULL_RTX, operands[1]));
15633 cond = gen_rtx_fmt_ee (ORDERED, QImode,
15634 gen_rtx_REG (CCmode, FLAGS_REG),
15636 emit_insn (gen_rtx_SET (VOIDmode, scratch, cond));
15638 emit_insn (gen_zero_extendqisi2 (operands[0], scratch));
15642 (define_insn_and_split "paritysi2_cmp"
15643 [(set (reg:CC FLAGS_REG)
15644 (parity:CC (match_operand:SI 2 "nonimmediate_operand" "0,m")))
15645 (clobber (match_scratch:SI 0 "=r,X"))
15646 (clobber (match_scratch:HI 1 "=Q,Q"))]
15649 "&& reload_completed"
15651 [(set (match_dup 1)
15652 (xor:HI (match_dup 1) (match_dup 3)))
15653 (clobber (reg:CC FLAGS_REG))])
15655 [(set (reg:CC FLAGS_REG)
15656 (parity:CC (match_dup 1)))
15657 (clobber (match_dup 1))])]
15659 operands[3] = gen_lowpart (HImode, operands[2]);
15661 if (MEM_P (operands[2]))
15662 emit_move_insn (operands[1], gen_highpart (HImode, operands[2]));
15665 emit_move_insn (operands[1], gen_lowpart (HImode, operands[2]));
15666 emit_insn (gen_lshrsi3 (operands[2], operands[2], GEN_INT (16)));
15670 (define_insn "*parityhi2_cmp"
15671 [(set (reg:CC FLAGS_REG)
15672 (parity:CC (match_operand:HI 1 "register_operand" "0")))
15673 (clobber (match_scratch:HI 0 "=Q"))]
15675 "xor{b}\t{%h0, %b0|%b0, %h0}"
15676 [(set_attr "length" "2")
15677 (set_attr "mode" "HI")])
15679 (define_insn "*parityqi2_cmp"
15680 [(set (reg:CC FLAGS_REG)
15681 (parity:CC (match_operand:QI 0 "register_operand" "q")))]
15684 [(set_attr "length" "2")
15685 (set_attr "mode" "QI")])
15687 ;; Thread-local storage patterns for ELF.
15689 ;; Note that these code sequences must appear exactly as shown
15690 ;; in order to allow linker relaxation.
15692 (define_insn "*tls_global_dynamic_32_gnu"
15693 [(set (match_operand:SI 0 "register_operand" "=a")
15694 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
15695 (match_operand:SI 2 "tls_symbolic_operand" "")
15696 (match_operand:SI 3 "call_insn_operand" "")]
15698 (clobber (match_scratch:SI 4 "=d"))
15699 (clobber (match_scratch:SI 5 "=c"))
15700 (clobber (reg:CC FLAGS_REG))]
15701 "!TARGET_64BIT && TARGET_GNU_TLS"
15702 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
15703 [(set_attr "type" "multi")
15704 (set_attr "length" "12")])
15706 (define_insn "*tls_global_dynamic_32_sun"
15707 [(set (match_operand:SI 0 "register_operand" "=a")
15708 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
15709 (match_operand:SI 2 "tls_symbolic_operand" "")
15710 (match_operand:SI 3 "call_insn_operand" "")]
15712 (clobber (match_scratch:SI 4 "=d"))
15713 (clobber (match_scratch:SI 5 "=c"))
15714 (clobber (reg:CC FLAGS_REG))]
15715 "!TARGET_64BIT && TARGET_SUN_TLS"
15716 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
15717 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
15718 [(set_attr "type" "multi")
15719 (set_attr "length" "14")])
15721 (define_expand "tls_global_dynamic_32"
15722 [(parallel [(set (match_operand:SI 0 "register_operand" "")
15725 (match_operand:SI 1 "tls_symbolic_operand" "")
15728 (clobber (match_scratch:SI 4 ""))
15729 (clobber (match_scratch:SI 5 ""))
15730 (clobber (reg:CC FLAGS_REG))])]
15734 operands[2] = pic_offset_table_rtx;
15737 operands[2] = gen_reg_rtx (Pmode);
15738 emit_insn (gen_set_got (operands[2]));
15740 if (TARGET_GNU2_TLS)
15742 emit_insn (gen_tls_dynamic_gnu2_32
15743 (operands[0], operands[1], operands[2]));
15746 operands[3] = ix86_tls_get_addr ();
15749 (define_insn "*tls_global_dynamic_64"
15750 [(set (match_operand:DI 0 "register_operand" "=a")
15751 (call:DI (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
15752 (match_operand:DI 3 "" "")))
15753 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
15756 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
15757 [(set_attr "type" "multi")
15758 (set_attr "length" "16")])
15760 (define_expand "tls_global_dynamic_64"
15761 [(parallel [(set (match_operand:DI 0 "register_operand" "")
15762 (call:DI (mem:QI (match_dup 2)) (const_int 0)))
15763 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
15767 if (TARGET_GNU2_TLS)
15769 emit_insn (gen_tls_dynamic_gnu2_64
15770 (operands[0], operands[1]));
15773 operands[2] = ix86_tls_get_addr ();
15776 (define_insn "*tls_local_dynamic_base_32_gnu"
15777 [(set (match_operand:SI 0 "register_operand" "=a")
15778 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
15779 (match_operand:SI 2 "call_insn_operand" "")]
15780 UNSPEC_TLS_LD_BASE))
15781 (clobber (match_scratch:SI 3 "=d"))
15782 (clobber (match_scratch:SI 4 "=c"))
15783 (clobber (reg:CC FLAGS_REG))]
15784 "!TARGET_64BIT && TARGET_GNU_TLS"
15785 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
15786 [(set_attr "type" "multi")
15787 (set_attr "length" "11")])
15789 (define_insn "*tls_local_dynamic_base_32_sun"
15790 [(set (match_operand:SI 0 "register_operand" "=a")
15791 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
15792 (match_operand:SI 2 "call_insn_operand" "")]
15793 UNSPEC_TLS_LD_BASE))
15794 (clobber (match_scratch:SI 3 "=d"))
15795 (clobber (match_scratch:SI 4 "=c"))
15796 (clobber (reg:CC FLAGS_REG))]
15797 "!TARGET_64BIT && TARGET_SUN_TLS"
15798 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
15799 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
15800 [(set_attr "type" "multi")
15801 (set_attr "length" "13")])
15803 (define_expand "tls_local_dynamic_base_32"
15804 [(parallel [(set (match_operand:SI 0 "register_operand" "")
15805 (unspec:SI [(match_dup 1) (match_dup 2)]
15806 UNSPEC_TLS_LD_BASE))
15807 (clobber (match_scratch:SI 3 ""))
15808 (clobber (match_scratch:SI 4 ""))
15809 (clobber (reg:CC FLAGS_REG))])]
15813 operands[1] = pic_offset_table_rtx;
15816 operands[1] = gen_reg_rtx (Pmode);
15817 emit_insn (gen_set_got (operands[1]));
15819 if (TARGET_GNU2_TLS)
15821 emit_insn (gen_tls_dynamic_gnu2_32
15822 (operands[0], ix86_tls_module_base (), operands[1]));
15825 operands[2] = ix86_tls_get_addr ();
15828 (define_insn "*tls_local_dynamic_base_64"
15829 [(set (match_operand:DI 0 "register_operand" "=a")
15830 (call:DI (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
15831 (match_operand:DI 2 "" "")))
15832 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
15834 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
15835 [(set_attr "type" "multi")
15836 (set_attr "length" "12")])
15838 (define_expand "tls_local_dynamic_base_64"
15839 [(parallel [(set (match_operand:DI 0 "register_operand" "")
15840 (call:DI (mem:QI (match_dup 1)) (const_int 0)))
15841 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
15844 if (TARGET_GNU2_TLS)
15846 emit_insn (gen_tls_dynamic_gnu2_64
15847 (operands[0], ix86_tls_module_base ()));
15850 operands[1] = ix86_tls_get_addr ();
15853 ;; Local dynamic of a single variable is a lose. Show combine how
15854 ;; to convert that back to global dynamic.
15856 (define_insn_and_split "*tls_local_dynamic_32_once"
15857 [(set (match_operand:SI 0 "register_operand" "=a")
15858 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
15859 (match_operand:SI 2 "call_insn_operand" "")]
15860 UNSPEC_TLS_LD_BASE)
15861 (const:SI (unspec:SI
15862 [(match_operand:SI 3 "tls_symbolic_operand" "")]
15864 (clobber (match_scratch:SI 4 "=d"))
15865 (clobber (match_scratch:SI 5 "=c"))
15866 (clobber (reg:CC FLAGS_REG))]
15870 [(parallel [(set (match_dup 0)
15871 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
15873 (clobber (match_dup 4))
15874 (clobber (match_dup 5))
15875 (clobber (reg:CC FLAGS_REG))])]
15878 ;; Load and add the thread base pointer from %gs:0.
15880 (define_insn "*load_tp_si"
15881 [(set (match_operand:SI 0 "register_operand" "=r")
15882 (unspec:SI [(const_int 0)] UNSPEC_TP))]
15884 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
15885 [(set_attr "type" "imov")
15886 (set_attr "modrm" "0")
15887 (set_attr "length" "7")
15888 (set_attr "memory" "load")
15889 (set_attr "imm_disp" "false")])
15891 (define_insn "*add_tp_si"
15892 [(set (match_operand:SI 0 "register_operand" "=r")
15893 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
15894 (match_operand:SI 1 "register_operand" "0")))
15895 (clobber (reg:CC FLAGS_REG))]
15897 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
15898 [(set_attr "type" "alu")
15899 (set_attr "modrm" "0")
15900 (set_attr "length" "7")
15901 (set_attr "memory" "load")
15902 (set_attr "imm_disp" "false")])
15904 (define_insn "*load_tp_di"
15905 [(set (match_operand:DI 0 "register_operand" "=r")
15906 (unspec:DI [(const_int 0)] UNSPEC_TP))]
15908 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
15909 [(set_attr "type" "imov")
15910 (set_attr "modrm" "0")
15911 (set_attr "length" "7")
15912 (set_attr "memory" "load")
15913 (set_attr "imm_disp" "false")])
15915 (define_insn "*add_tp_di"
15916 [(set (match_operand:DI 0 "register_operand" "=r")
15917 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
15918 (match_operand:DI 1 "register_operand" "0")))
15919 (clobber (reg:CC FLAGS_REG))]
15921 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
15922 [(set_attr "type" "alu")
15923 (set_attr "modrm" "0")
15924 (set_attr "length" "7")
15925 (set_attr "memory" "load")
15926 (set_attr "imm_disp" "false")])
15928 ;; GNU2 TLS patterns can be split.
15930 (define_expand "tls_dynamic_gnu2_32"
15931 [(set (match_dup 3)
15932 (plus:SI (match_operand:SI 2 "register_operand" "")
15934 (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")]
15937 [(set (match_operand:SI 0 "register_operand" "")
15938 (unspec:SI [(match_dup 1) (match_dup 3)
15939 (match_dup 2) (reg:SI SP_REG)]
15941 (clobber (reg:CC FLAGS_REG))])]
15942 "!TARGET_64BIT && TARGET_GNU2_TLS"
15944 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
15945 ix86_tls_descriptor_calls_expanded_in_cfun = true;
15948 (define_insn "*tls_dynamic_lea_32"
15949 [(set (match_operand:SI 0 "register_operand" "=r")
15950 (plus:SI (match_operand:SI 1 "register_operand" "b")
15952 (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
15953 UNSPEC_TLSDESC))))]
15954 "!TARGET_64BIT && TARGET_GNU2_TLS"
15955 "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}"
15956 [(set_attr "type" "lea")
15957 (set_attr "mode" "SI")
15958 (set_attr "length" "6")
15959 (set_attr "length_address" "4")])
15961 (define_insn "*tls_dynamic_call_32"
15962 [(set (match_operand:SI 0 "register_operand" "=a")
15963 (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")
15964 (match_operand:SI 2 "register_operand" "0")
15965 ;; we have to make sure %ebx still points to the GOT
15966 (match_operand:SI 3 "register_operand" "b")
15969 (clobber (reg:CC FLAGS_REG))]
15970 "!TARGET_64BIT && TARGET_GNU2_TLS"
15971 "call\t{*%a1@TLSCALL(%2)|[DWORD PTR [%2+%a1@TLSCALL]]}"
15972 [(set_attr "type" "call")
15973 (set_attr "length" "2")
15974 (set_attr "length_address" "0")])
15976 (define_insn_and_split "*tls_dynamic_gnu2_combine_32"
15977 [(set (match_operand:SI 0 "register_operand" "=&a")
15979 (unspec:SI [(match_operand:SI 3 "tls_modbase_operand" "")
15980 (match_operand:SI 4 "" "")
15981 (match_operand:SI 2 "register_operand" "b")
15984 (const:SI (unspec:SI
15985 [(match_operand:SI 1 "tls_symbolic_operand" "")]
15987 (clobber (reg:CC FLAGS_REG))]
15988 "!TARGET_64BIT && TARGET_GNU2_TLS"
15991 [(set (match_dup 0) (match_dup 5))]
15993 operands[5] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
15994 emit_insn (gen_tls_dynamic_gnu2_32 (operands[5], operands[1], operands[2]));
15997 (define_expand "tls_dynamic_gnu2_64"
15998 [(set (match_dup 2)
15999 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
16002 [(set (match_operand:DI 0 "register_operand" "")
16003 (unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)]
16005 (clobber (reg:CC FLAGS_REG))])]
16006 "TARGET_64BIT && TARGET_GNU2_TLS"
16008 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
16009 ix86_tls_descriptor_calls_expanded_in_cfun = true;
16012 (define_insn "*tls_dynamic_lea_64"
16013 [(set (match_operand:DI 0 "register_operand" "=r")
16014 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
16016 "TARGET_64BIT && TARGET_GNU2_TLS"
16017 "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[%%rip]}"
16018 [(set_attr "type" "lea")
16019 (set_attr "mode" "DI")
16020 (set_attr "length" "7")
16021 (set_attr "length_address" "4")])
16023 (define_insn "*tls_dynamic_call_64"
16024 [(set (match_operand:DI 0 "register_operand" "=a")
16025 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")
16026 (match_operand:DI 2 "register_operand" "0")
16029 (clobber (reg:CC FLAGS_REG))]
16030 "TARGET_64BIT && TARGET_GNU2_TLS"
16031 "call\t{*%a1@TLSCALL(%2)|[QWORD PTR [%2+%a1@TLSCALL]]}"
16032 [(set_attr "type" "call")
16033 (set_attr "length" "2")
16034 (set_attr "length_address" "0")])
16036 (define_insn_and_split "*tls_dynamic_gnu2_combine_64"
16037 [(set (match_operand:DI 0 "register_operand" "=&a")
16039 (unspec:DI [(match_operand:DI 2 "tls_modbase_operand" "")
16040 (match_operand:DI 3 "" "")
16043 (const:DI (unspec:DI
16044 [(match_operand:DI 1 "tls_symbolic_operand" "")]
16046 (clobber (reg:CC FLAGS_REG))]
16047 "TARGET_64BIT && TARGET_GNU2_TLS"
16050 [(set (match_dup 0) (match_dup 4))]
16052 operands[4] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
16053 emit_insn (gen_tls_dynamic_gnu2_64 (operands[4], operands[1]));
16058 ;; These patterns match the binary 387 instructions for addM3, subM3,
16059 ;; mulM3 and divM3. There are three patterns for each of DFmode and
16060 ;; SFmode. The first is the normal insn, the second the same insn but
16061 ;; with one operand a conversion, and the third the same insn but with
16062 ;; the other operand a conversion. The conversion may be SFmode or
16063 ;; SImode if the target mode DFmode, but only SImode if the target mode
16066 ;; Gcc is slightly more smart about handling normal two address instructions
16067 ;; so use special patterns for add and mull.
16069 (define_insn "*fop_sf_comm_mixed"
16070 [(set (match_operand:SF 0 "register_operand" "=f,x")
16071 (match_operator:SF 3 "binary_fp_operator"
16072 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
16073 (match_operand:SF 2 "nonimmediate_operand" "fm,xm")]))]
16074 "TARGET_MIX_SSE_I387
16075 && COMMUTATIVE_ARITH_P (operands[3])
16076 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16077 "* return output_387_binary_op (insn, operands);"
16078 [(set (attr "type")
16079 (if_then_else (eq_attr "alternative" "1")
16080 (if_then_else (match_operand:SF 3 "mult_operator" "")
16081 (const_string "ssemul")
16082 (const_string "sseadd"))
16083 (if_then_else (match_operand:SF 3 "mult_operator" "")
16084 (const_string "fmul")
16085 (const_string "fop"))))
16086 (set_attr "mode" "SF")])
16088 (define_insn "*fop_sf_comm_sse"
16089 [(set (match_operand:SF 0 "register_operand" "=x")
16090 (match_operator:SF 3 "binary_fp_operator"
16091 [(match_operand:SF 1 "nonimmediate_operand" "%0")
16092 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
16094 && COMMUTATIVE_ARITH_P (operands[3])
16095 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16096 "* return output_387_binary_op (insn, operands);"
16097 [(set (attr "type")
16098 (if_then_else (match_operand:SF 3 "mult_operator" "")
16099 (const_string "ssemul")
16100 (const_string "sseadd")))
16101 (set_attr "mode" "SF")])
16103 (define_insn "*fop_sf_comm_i387"
16104 [(set (match_operand:SF 0 "register_operand" "=f")
16105 (match_operator:SF 3 "binary_fp_operator"
16106 [(match_operand:SF 1 "nonimmediate_operand" "%0")
16107 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
16109 && COMMUTATIVE_ARITH_P (operands[3])
16110 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16111 "* return output_387_binary_op (insn, operands);"
16112 [(set (attr "type")
16113 (if_then_else (match_operand:SF 3 "mult_operator" "")
16114 (const_string "fmul")
16115 (const_string "fop")))
16116 (set_attr "mode" "SF")])
16118 (define_insn "*fop_sf_1_mixed"
16119 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
16120 (match_operator:SF 3 "binary_fp_operator"
16121 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
16122 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm")]))]
16123 "TARGET_MIX_SSE_I387
16124 && !COMMUTATIVE_ARITH_P (operands[3])
16125 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16126 "* return output_387_binary_op (insn, operands);"
16127 [(set (attr "type")
16128 (cond [(and (eq_attr "alternative" "2")
16129 (match_operand:SF 3 "mult_operator" ""))
16130 (const_string "ssemul")
16131 (and (eq_attr "alternative" "2")
16132 (match_operand:SF 3 "div_operator" ""))
16133 (const_string "ssediv")
16134 (eq_attr "alternative" "2")
16135 (const_string "sseadd")
16136 (match_operand:SF 3 "mult_operator" "")
16137 (const_string "fmul")
16138 (match_operand:SF 3 "div_operator" "")
16139 (const_string "fdiv")
16141 (const_string "fop")))
16142 (set_attr "mode" "SF")])
16144 (define_insn "*rcpsf2_sse"
16145 [(set (match_operand:SF 0 "register_operand" "=x")
16146 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
16149 "rcpss\t{%1, %0|%0, %1}"
16150 [(set_attr "type" "sse")
16151 (set_attr "mode" "SF")])
16153 (define_insn "*fop_sf_1_sse"
16154 [(set (match_operand:SF 0 "register_operand" "=x")
16155 (match_operator:SF 3 "binary_fp_operator"
16156 [(match_operand:SF 1 "register_operand" "0")
16157 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
16159 && !COMMUTATIVE_ARITH_P (operands[3])"
16160 "* return output_387_binary_op (insn, operands);"
16161 [(set (attr "type")
16162 (cond [(match_operand:SF 3 "mult_operator" "")
16163 (const_string "ssemul")
16164 (match_operand:SF 3 "div_operator" "")
16165 (const_string "ssediv")
16167 (const_string "sseadd")))
16168 (set_attr "mode" "SF")])
16170 ;; This pattern is not fully shadowed by the pattern above.
16171 (define_insn "*fop_sf_1_i387"
16172 [(set (match_operand:SF 0 "register_operand" "=f,f")
16173 (match_operator:SF 3 "binary_fp_operator"
16174 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
16175 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
16176 "TARGET_80387 && !TARGET_SSE_MATH
16177 && !COMMUTATIVE_ARITH_P (operands[3])
16178 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16179 "* return output_387_binary_op (insn, operands);"
16180 [(set (attr "type")
16181 (cond [(match_operand:SF 3 "mult_operator" "")
16182 (const_string "fmul")
16183 (match_operand:SF 3 "div_operator" "")
16184 (const_string "fdiv")
16186 (const_string "fop")))
16187 (set_attr "mode" "SF")])
16189 ;; ??? Add SSE splitters for these!
16190 (define_insn "*fop_sf_2<mode>_i387"
16191 [(set (match_operand:SF 0 "register_operand" "=f,f")
16192 (match_operator:SF 3 "binary_fp_operator"
16193 [(float:SF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
16194 (match_operand:SF 2 "register_operand" "0,0")]))]
16195 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
16196 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16197 [(set (attr "type")
16198 (cond [(match_operand:SF 3 "mult_operator" "")
16199 (const_string "fmul")
16200 (match_operand:SF 3 "div_operator" "")
16201 (const_string "fdiv")
16203 (const_string "fop")))
16204 (set_attr "fp_int_src" "true")
16205 (set_attr "mode" "<MODE>")])
16207 (define_insn "*fop_sf_3<mode>_i387"
16208 [(set (match_operand:SF 0 "register_operand" "=f,f")
16209 (match_operator:SF 3 "binary_fp_operator"
16210 [(match_operand:SF 1 "register_operand" "0,0")
16211 (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
16212 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
16213 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16214 [(set (attr "type")
16215 (cond [(match_operand:SF 3 "mult_operator" "")
16216 (const_string "fmul")
16217 (match_operand:SF 3 "div_operator" "")
16218 (const_string "fdiv")
16220 (const_string "fop")))
16221 (set_attr "fp_int_src" "true")
16222 (set_attr "mode" "<MODE>")])
16224 (define_insn "*fop_df_comm_mixed"
16225 [(set (match_operand:DF 0 "register_operand" "=f,x")
16226 (match_operator:DF 3 "binary_fp_operator"
16227 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
16228 (match_operand:DF 2 "nonimmediate_operand" "fm,xm")]))]
16229 "TARGET_SSE2 && TARGET_MIX_SSE_I387
16230 && COMMUTATIVE_ARITH_P (operands[3])
16231 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16232 "* return output_387_binary_op (insn, operands);"
16233 [(set (attr "type")
16234 (if_then_else (eq_attr "alternative" "1")
16235 (if_then_else (match_operand:DF 3 "mult_operator" "")
16236 (const_string "ssemul")
16237 (const_string "sseadd"))
16238 (if_then_else (match_operand:DF 3 "mult_operator" "")
16239 (const_string "fmul")
16240 (const_string "fop"))))
16241 (set_attr "mode" "DF")])
16243 (define_insn "*fop_df_comm_sse"
16244 [(set (match_operand:DF 0 "register_operand" "=x")
16245 (match_operator:DF 3 "binary_fp_operator"
16246 [(match_operand:DF 1 "nonimmediate_operand" "%0")
16247 (match_operand:DF 2 "nonimmediate_operand" "xm")]))]
16248 "TARGET_SSE2 && TARGET_SSE_MATH
16249 && COMMUTATIVE_ARITH_P (operands[3])
16250 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16251 "* return output_387_binary_op (insn, operands);"
16252 [(set (attr "type")
16253 (if_then_else (match_operand:DF 3 "mult_operator" "")
16254 (const_string "ssemul")
16255 (const_string "sseadd")))
16256 (set_attr "mode" "DF")])
16258 (define_insn "*fop_df_comm_i387"
16259 [(set (match_operand:DF 0 "register_operand" "=f")
16260 (match_operator:DF 3 "binary_fp_operator"
16261 [(match_operand:DF 1 "nonimmediate_operand" "%0")
16262 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
16264 && COMMUTATIVE_ARITH_P (operands[3])
16265 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16266 "* return output_387_binary_op (insn, operands);"
16267 [(set (attr "type")
16268 (if_then_else (match_operand:DF 3 "mult_operator" "")
16269 (const_string "fmul")
16270 (const_string "fop")))
16271 (set_attr "mode" "DF")])
16273 (define_insn "*fop_df_1_mixed"
16274 [(set (match_operand:DF 0 "register_operand" "=f,f,x")
16275 (match_operator:DF 3 "binary_fp_operator"
16276 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
16277 (match_operand:DF 2 "nonimmediate_operand" "fm,0,xm")]))]
16278 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
16279 && !COMMUTATIVE_ARITH_P (operands[3])
16280 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16281 "* return output_387_binary_op (insn, operands);"
16282 [(set (attr "type")
16283 (cond [(and (eq_attr "alternative" "2")
16284 (match_operand:DF 3 "mult_operator" ""))
16285 (const_string "ssemul")
16286 (and (eq_attr "alternative" "2")
16287 (match_operand:DF 3 "div_operator" ""))
16288 (const_string "ssediv")
16289 (eq_attr "alternative" "2")
16290 (const_string "sseadd")
16291 (match_operand:DF 3 "mult_operator" "")
16292 (const_string "fmul")
16293 (match_operand:DF 3 "div_operator" "")
16294 (const_string "fdiv")
16296 (const_string "fop")))
16297 (set_attr "mode" "DF")])
16299 (define_insn "*fop_df_1_sse"
16300 [(set (match_operand:DF 0 "register_operand" "=x")
16301 (match_operator:DF 3 "binary_fp_operator"
16302 [(match_operand:DF 1 "register_operand" "0")
16303 (match_operand:DF 2 "nonimmediate_operand" "xm")]))]
16304 "TARGET_SSE2 && TARGET_SSE_MATH
16305 && !COMMUTATIVE_ARITH_P (operands[3])"
16306 "* return output_387_binary_op (insn, operands);"
16307 [(set_attr "mode" "DF")
16309 (cond [(match_operand:DF 3 "mult_operator" "")
16310 (const_string "ssemul")
16311 (match_operand:DF 3 "div_operator" "")
16312 (const_string "ssediv")
16314 (const_string "sseadd")))])
16316 ;; This pattern is not fully shadowed by the pattern above.
16317 (define_insn "*fop_df_1_i387"
16318 [(set (match_operand:DF 0 "register_operand" "=f,f")
16319 (match_operator:DF 3 "binary_fp_operator"
16320 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
16321 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
16322 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
16323 && !COMMUTATIVE_ARITH_P (operands[3])
16324 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16325 "* return output_387_binary_op (insn, operands);"
16326 [(set (attr "type")
16327 (cond [(match_operand:DF 3 "mult_operator" "")
16328 (const_string "fmul")
16329 (match_operand:DF 3 "div_operator" "")
16330 (const_string "fdiv")
16332 (const_string "fop")))
16333 (set_attr "mode" "DF")])
16335 ;; ??? Add SSE splitters for these!
16336 (define_insn "*fop_df_2<mode>_i387"
16337 [(set (match_operand:DF 0 "register_operand" "=f,f")
16338 (match_operator:DF 3 "binary_fp_operator"
16339 [(float:DF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
16340 (match_operand:DF 2 "register_operand" "0,0")]))]
16341 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
16342 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
16343 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16344 [(set (attr "type")
16345 (cond [(match_operand:DF 3 "mult_operator" "")
16346 (const_string "fmul")
16347 (match_operand:DF 3 "div_operator" "")
16348 (const_string "fdiv")
16350 (const_string "fop")))
16351 (set_attr "fp_int_src" "true")
16352 (set_attr "mode" "<MODE>")])
16354 (define_insn "*fop_df_3<mode>_i387"
16355 [(set (match_operand:DF 0 "register_operand" "=f,f")
16356 (match_operator:DF 3 "binary_fp_operator"
16357 [(match_operand:DF 1 "register_operand" "0,0")
16358 (float:DF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
16359 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
16360 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
16361 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16362 [(set (attr "type")
16363 (cond [(match_operand:DF 3 "mult_operator" "")
16364 (const_string "fmul")
16365 (match_operand:DF 3 "div_operator" "")
16366 (const_string "fdiv")
16368 (const_string "fop")))
16369 (set_attr "fp_int_src" "true")
16370 (set_attr "mode" "<MODE>")])
16372 (define_insn "*fop_df_4_i387"
16373 [(set (match_operand:DF 0 "register_operand" "=f,f")
16374 (match_operator:DF 3 "binary_fp_operator"
16375 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
16376 (match_operand:DF 2 "register_operand" "0,f")]))]
16377 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
16378 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
16379 "* return output_387_binary_op (insn, operands);"
16380 [(set (attr "type")
16381 (cond [(match_operand:DF 3 "mult_operator" "")
16382 (const_string "fmul")
16383 (match_operand:DF 3 "div_operator" "")
16384 (const_string "fdiv")
16386 (const_string "fop")))
16387 (set_attr "mode" "SF")])
16389 (define_insn "*fop_df_5_i387"
16390 [(set (match_operand:DF 0 "register_operand" "=f,f")
16391 (match_operator:DF 3 "binary_fp_operator"
16392 [(match_operand:DF 1 "register_operand" "0,f")
16394 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
16395 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
16396 "* return output_387_binary_op (insn, operands);"
16397 [(set (attr "type")
16398 (cond [(match_operand:DF 3 "mult_operator" "")
16399 (const_string "fmul")
16400 (match_operand:DF 3 "div_operator" "")
16401 (const_string "fdiv")
16403 (const_string "fop")))
16404 (set_attr "mode" "SF")])
16406 (define_insn "*fop_df_6_i387"
16407 [(set (match_operand:DF 0 "register_operand" "=f,f")
16408 (match_operator:DF 3 "binary_fp_operator"
16410 (match_operand:SF 1 "register_operand" "0,f"))
16412 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
16413 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
16414 "* return output_387_binary_op (insn, operands);"
16415 [(set (attr "type")
16416 (cond [(match_operand:DF 3 "mult_operator" "")
16417 (const_string "fmul")
16418 (match_operand:DF 3 "div_operator" "")
16419 (const_string "fdiv")
16421 (const_string "fop")))
16422 (set_attr "mode" "SF")])
16424 (define_insn "*fop_xf_comm_i387"
16425 [(set (match_operand:XF 0 "register_operand" "=f")
16426 (match_operator:XF 3 "binary_fp_operator"
16427 [(match_operand:XF 1 "register_operand" "%0")
16428 (match_operand:XF 2 "register_operand" "f")]))]
16430 && COMMUTATIVE_ARITH_P (operands[3])"
16431 "* return output_387_binary_op (insn, operands);"
16432 [(set (attr "type")
16433 (if_then_else (match_operand:XF 3 "mult_operator" "")
16434 (const_string "fmul")
16435 (const_string "fop")))
16436 (set_attr "mode" "XF")])
16438 (define_insn "*fop_xf_1_i387"
16439 [(set (match_operand:XF 0 "register_operand" "=f,f")
16440 (match_operator:XF 3 "binary_fp_operator"
16441 [(match_operand:XF 1 "register_operand" "0,f")
16442 (match_operand:XF 2 "register_operand" "f,0")]))]
16444 && !COMMUTATIVE_ARITH_P (operands[3])"
16445 "* return output_387_binary_op (insn, operands);"
16446 [(set (attr "type")
16447 (cond [(match_operand:XF 3 "mult_operator" "")
16448 (const_string "fmul")
16449 (match_operand:XF 3 "div_operator" "")
16450 (const_string "fdiv")
16452 (const_string "fop")))
16453 (set_attr "mode" "XF")])
16455 (define_insn "*fop_xf_2<mode>_i387"
16456 [(set (match_operand:XF 0 "register_operand" "=f,f")
16457 (match_operator:XF 3 "binary_fp_operator"
16458 [(float:XF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
16459 (match_operand:XF 2 "register_operand" "0,0")]))]
16460 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
16461 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16462 [(set (attr "type")
16463 (cond [(match_operand:XF 3 "mult_operator" "")
16464 (const_string "fmul")
16465 (match_operand:XF 3 "div_operator" "")
16466 (const_string "fdiv")
16468 (const_string "fop")))
16469 (set_attr "fp_int_src" "true")
16470 (set_attr "mode" "<MODE>")])
16472 (define_insn "*fop_xf_3<mode>_i387"
16473 [(set (match_operand:XF 0 "register_operand" "=f,f")
16474 (match_operator:XF 3 "binary_fp_operator"
16475 [(match_operand:XF 1 "register_operand" "0,0")
16476 (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
16477 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
16478 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
16479 [(set (attr "type")
16480 (cond [(match_operand:XF 3 "mult_operator" "")
16481 (const_string "fmul")
16482 (match_operand:XF 3 "div_operator" "")
16483 (const_string "fdiv")
16485 (const_string "fop")))
16486 (set_attr "fp_int_src" "true")
16487 (set_attr "mode" "<MODE>")])
16489 (define_insn "*fop_xf_4_i387"
16490 [(set (match_operand:XF 0 "register_operand" "=f,f")
16491 (match_operator:XF 3 "binary_fp_operator"
16493 (match_operand:MODEF 1 "nonimmediate_operand" "fm,0"))
16494 (match_operand:XF 2 "register_operand" "0,f")]))]
16496 "* return output_387_binary_op (insn, operands);"
16497 [(set (attr "type")
16498 (cond [(match_operand:XF 3 "mult_operator" "")
16499 (const_string "fmul")
16500 (match_operand:XF 3 "div_operator" "")
16501 (const_string "fdiv")
16503 (const_string "fop")))
16504 (set_attr "mode" "SF")])
16506 (define_insn "*fop_xf_5_i387"
16507 [(set (match_operand:XF 0 "register_operand" "=f,f")
16508 (match_operator:XF 3 "binary_fp_operator"
16509 [(match_operand:XF 1 "register_operand" "0,f")
16511 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
16513 "* return output_387_binary_op (insn, operands);"
16514 [(set (attr "type")
16515 (cond [(match_operand:XF 3 "mult_operator" "")
16516 (const_string "fmul")
16517 (match_operand:XF 3 "div_operator" "")
16518 (const_string "fdiv")
16520 (const_string "fop")))
16521 (set_attr "mode" "SF")])
16523 (define_insn "*fop_xf_6_i387"
16524 [(set (match_operand:XF 0 "register_operand" "=f,f")
16525 (match_operator:XF 3 "binary_fp_operator"
16527 (match_operand:MODEF 1 "register_operand" "0,f"))
16529 (match_operand:MODEF 2 "nonimmediate_operand" "fm,0"))]))]
16531 "* return output_387_binary_op (insn, operands);"
16532 [(set (attr "type")
16533 (cond [(match_operand:XF 3 "mult_operator" "")
16534 (const_string "fmul")
16535 (match_operand:XF 3 "div_operator" "")
16536 (const_string "fdiv")
16538 (const_string "fop")))
16539 (set_attr "mode" "SF")])
16542 [(set (match_operand 0 "register_operand" "")
16543 (match_operator 3 "binary_fp_operator"
16544 [(float (match_operand:X87MODEI12 1 "register_operand" ""))
16545 (match_operand 2 "register_operand" "")]))]
16547 && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
16550 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
16551 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
16552 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16553 gen_rtx_fmt_ee (GET_CODE (operands[3]),
16554 GET_MODE (operands[3]),
16557 ix86_free_from_memory (GET_MODE (operands[1]));
16562 [(set (match_operand 0 "register_operand" "")
16563 (match_operator 3 "binary_fp_operator"
16564 [(match_operand 1 "register_operand" "")
16565 (float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
16567 && X87_FLOAT_MODE_P (GET_MODE (operands[0]))"
16570 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
16571 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
16572 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
16573 gen_rtx_fmt_ee (GET_CODE (operands[3]),
16574 GET_MODE (operands[3]),
16577 ix86_free_from_memory (GET_MODE (operands[2]));
16581 ;; FPU special functions.
16583 ;; This pattern implements a no-op XFmode truncation for
16584 ;; all fancy i386 XFmode math functions.
16586 (define_insn "truncxf<mode>2_i387_noop_unspec"
16587 [(set (match_operand:MODEF 0 "register_operand" "=f")
16588 (unspec:MODEF [(match_operand:XF 1 "register_operand" "f")]
16589 UNSPEC_TRUNC_NOOP))]
16590 "TARGET_USE_FANCY_MATH_387"
16591 "* return output_387_reg_move (insn, operands);"
16592 [(set_attr "type" "fmov")
16593 (set_attr "mode" "<MODE>")])
16595 (define_insn "sqrtxf2"
16596 [(set (match_operand:XF 0 "register_operand" "=f")
16597 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
16598 "TARGET_USE_FANCY_MATH_387"
16600 [(set_attr "type" "fpspc")
16601 (set_attr "mode" "XF")
16602 (set_attr "athlon_decode" "direct")
16603 (set_attr "amdfam10_decode" "direct")])
16605 (define_insn "sqrt_extend<mode>xf2_i387"
16606 [(set (match_operand:XF 0 "register_operand" "=f")
16609 (match_operand:MODEF 1 "register_operand" "0"))))]
16610 "TARGET_USE_FANCY_MATH_387"
16612 [(set_attr "type" "fpspc")
16613 (set_attr "mode" "XF")
16614 (set_attr "athlon_decode" "direct")
16615 (set_attr "amdfam10_decode" "direct")])
16617 (define_insn "*rsqrtsf2_sse"
16618 [(set (match_operand:SF 0 "register_operand" "=x")
16619 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
16622 "rsqrtss\t{%1, %0|%0, %1}"
16623 [(set_attr "type" "sse")
16624 (set_attr "mode" "SF")])
16626 (define_expand "rsqrtsf2"
16627 [(set (match_operand:SF 0 "register_operand" "")
16628 (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
16630 "TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
16631 && flag_finite_math_only && !flag_trapping_math
16632 && flag_unsafe_math_optimizations"
16634 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
16638 (define_insn "*sqrt<mode>2_sse"
16639 [(set (match_operand:MODEF 0 "register_operand" "=x")
16641 (match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
16642 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
16643 "sqrts<ssemodefsuffix>\t{%1, %0|%0, %1}"
16644 [(set_attr "type" "sse")
16645 (set_attr "mode" "<MODE>")
16646 (set_attr "athlon_decode" "*")
16647 (set_attr "amdfam10_decode" "*")])
16649 (define_expand "sqrt<mode>2"
16650 [(set (match_operand:MODEF 0 "register_operand" "")
16652 (match_operand:MODEF 1 "nonimmediate_operand" "")))]
16653 "TARGET_USE_FANCY_MATH_387
16654 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
16656 if (<MODE>mode == SFmode
16657 && TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
16658 && flag_finite_math_only && !flag_trapping_math
16659 && flag_unsafe_math_optimizations)
16661 ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 0);
16665 if (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
16667 rtx op0 = gen_reg_rtx (XFmode);
16668 rtx op1 = force_reg (<MODE>mode, operands[1]);
16670 emit_insn (gen_sqrt_extend<mode>xf2_i387 (op0, op1));
16671 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op0));
16676 (define_insn "fpremxf4_i387"
16677 [(set (match_operand:XF 0 "register_operand" "=f")
16678 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
16679 (match_operand:XF 3 "register_operand" "1")]
16681 (set (match_operand:XF 1 "register_operand" "=u")
16682 (unspec:XF [(match_dup 2) (match_dup 3)]
16684 (set (reg:CCFP FPSR_REG)
16685 (unspec:CCFP [(match_dup 2) (match_dup 3)]
16687 "TARGET_USE_FANCY_MATH_387"
16689 [(set_attr "type" "fpspc")
16690 (set_attr "mode" "XF")])
16692 (define_expand "fmodxf3"
16693 [(use (match_operand:XF 0 "register_operand" ""))
16694 (use (match_operand:XF 1 "register_operand" ""))
16695 (use (match_operand:XF 2 "register_operand" ""))]
16696 "TARGET_USE_FANCY_MATH_387"
16698 rtx label = gen_label_rtx ();
16702 if (rtx_equal_p (operands[1], operands[2]))
16704 op2 = gen_reg_rtx (XFmode);
16705 emit_move_insn (op2, operands[2]);
16710 emit_label (label);
16711 emit_insn (gen_fpremxf4_i387 (operands[1], op2, operands[1], op2));
16712 ix86_emit_fp_unordered_jump (label);
16713 LABEL_NUSES (label) = 1;
16715 emit_move_insn (operands[0], operands[1]);
16719 (define_expand "fmod<mode>3"
16720 [(use (match_operand:MODEF 0 "register_operand" ""))
16721 (use (match_operand:MODEF 1 "general_operand" ""))
16722 (use (match_operand:MODEF 2 "general_operand" ""))]
16723 "TARGET_USE_FANCY_MATH_387"
16725 rtx label = gen_label_rtx ();
16727 rtx op1 = gen_reg_rtx (XFmode);
16728 rtx op2 = gen_reg_rtx (XFmode);
16730 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16731 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
16733 emit_label (label);
16734 emit_insn (gen_fpremxf4_i387 (op1, op2, op1, op2));
16735 ix86_emit_fp_unordered_jump (label);
16736 LABEL_NUSES (label) = 1;
16738 /* Truncate the result properly for strict SSE math. */
16739 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16740 && !TARGET_MIX_SSE_I387)
16741 emit_insn (gen_truncxf<mode>2 (operands[0], op1));
16743 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op1));
16748 (define_insn "fprem1xf4_i387"
16749 [(set (match_operand:XF 0 "register_operand" "=f")
16750 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
16751 (match_operand:XF 3 "register_operand" "1")]
16753 (set (match_operand:XF 1 "register_operand" "=u")
16754 (unspec:XF [(match_dup 2) (match_dup 3)]
16756 (set (reg:CCFP FPSR_REG)
16757 (unspec:CCFP [(match_dup 2) (match_dup 3)]
16759 "TARGET_USE_FANCY_MATH_387"
16761 [(set_attr "type" "fpspc")
16762 (set_attr "mode" "XF")])
16764 (define_expand "remainderxf3"
16765 [(use (match_operand:XF 0 "register_operand" ""))
16766 (use (match_operand:XF 1 "register_operand" ""))
16767 (use (match_operand:XF 2 "register_operand" ""))]
16768 "TARGET_USE_FANCY_MATH_387"
16770 rtx label = gen_label_rtx ();
16774 if (rtx_equal_p (operands[1], operands[2]))
16776 op2 = gen_reg_rtx (XFmode);
16777 emit_move_insn (op2, operands[2]);
16782 emit_label (label);
16783 emit_insn (gen_fprem1xf4_i387 (operands[1], op2, operands[1], op2));
16784 ix86_emit_fp_unordered_jump (label);
16785 LABEL_NUSES (label) = 1;
16787 emit_move_insn (operands[0], operands[1]);
16791 (define_expand "remainder<mode>3"
16792 [(use (match_operand:MODEF 0 "register_operand" ""))
16793 (use (match_operand:MODEF 1 "general_operand" ""))
16794 (use (match_operand:MODEF 2 "general_operand" ""))]
16795 "TARGET_USE_FANCY_MATH_387"
16797 rtx label = gen_label_rtx ();
16799 rtx op1 = gen_reg_rtx (XFmode);
16800 rtx op2 = gen_reg_rtx (XFmode);
16802 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
16803 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
16805 emit_label (label);
16807 emit_insn (gen_fprem1xf4_i387 (op1, op2, op1, op2));
16808 ix86_emit_fp_unordered_jump (label);
16809 LABEL_NUSES (label) = 1;
16811 /* Truncate the result properly for strict SSE math. */
16812 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
16813 && !TARGET_MIX_SSE_I387)
16814 emit_insn (gen_truncxf<mode>2 (operands[0], op1));
16816 emit_insn (gen_truncxf<mode>2_i387_noop_unspec (operands[0], op1));
16821 (define_insn "*sinxf2_i387"
16822 [(set (match_operand:XF 0 "register_operand" "=f")
16823 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
16824 "TARGET_USE_FANCY_MATH_387
16825 && flag_unsafe_math_optimizations"
16827 [(set_attr "type" "fpspc")
16828 (set_attr "mode" "XF")])
16830 (define_insn "*sin_extend<mode>xf2_i387"
16831 [(set (match_operand:XF 0 "register_operand" "=f")
16832 (unspec:XF [(float_extend:XF
16833 (match_operand:MODEF 1 "register_operand" "0"))]
16835 "TARGET_USE_FANCY_MATH_387
16836 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16837 || TARGET_MIX_SSE_I387)
16838 && flag_unsafe_math_optimizations"
16840 [(set_attr "type" "fpspc")
16841 (set_attr "mode" "XF")])
16843 (define_insn "*cosxf2_i387"
16844 [(set (match_operand:XF 0 "register_operand" "=f")
16845 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
16846 "TARGET_USE_FANCY_MATH_387
16847 && flag_unsafe_math_optimizations"
16849 [(set_attr "type" "fpspc")
16850 (set_attr "mode" "XF")])
16852 (define_insn "*cos_extend<mode>xf2_i387"
16853 [(set (match_operand:XF 0 "register_operand" "=f")
16854 (unspec:XF [(float_extend:XF
16855 (match_operand:MODEF 1 "register_operand" "0"))]
16857 "TARGET_USE_FANCY_MATH_387
16858 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16859 || TARGET_MIX_SSE_I387)
16860 && flag_unsafe_math_optimizations"
16862 [(set_attr "type" "fpspc")
16863 (set_attr "mode" "XF")])
16865 ;; When sincos pattern is defined, sin and cos builtin functions will be
16866 ;; expanded to sincos pattern with one of its outputs left unused.
16867 ;; CSE pass will figure out if two sincos patterns can be combined,
16868 ;; otherwise sincos pattern will be split back to sin or cos pattern,
16869 ;; depending on the unused output.
16871 (define_insn "sincosxf3"
16872 [(set (match_operand:XF 0 "register_operand" "=f")
16873 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
16874 UNSPEC_SINCOS_COS))
16875 (set (match_operand:XF 1 "register_operand" "=u")
16876 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
16877 "TARGET_USE_FANCY_MATH_387
16878 && flag_unsafe_math_optimizations"
16880 [(set_attr "type" "fpspc")
16881 (set_attr "mode" "XF")])
16884 [(set (match_operand:XF 0 "register_operand" "")
16885 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
16886 UNSPEC_SINCOS_COS))
16887 (set (match_operand:XF 1 "register_operand" "")
16888 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
16889 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
16890 && !(reload_completed || reload_in_progress)"
16891 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
16895 [(set (match_operand:XF 0 "register_operand" "")
16896 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
16897 UNSPEC_SINCOS_COS))
16898 (set (match_operand:XF 1 "register_operand" "")
16899 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
16900 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
16901 && !(reload_completed || reload_in_progress)"
16902 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
16905 (define_insn "sincos_extend<mode>xf3_i387"
16906 [(set (match_operand:XF 0 "register_operand" "=f")
16907 (unspec:XF [(float_extend:XF
16908 (match_operand:MODEF 2 "register_operand" "0"))]
16909 UNSPEC_SINCOS_COS))
16910 (set (match_operand:XF 1 "register_operand" "=u")
16911 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
16912 "TARGET_USE_FANCY_MATH_387
16913 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16914 || TARGET_MIX_SSE_I387)
16915 && flag_unsafe_math_optimizations"
16917 [(set_attr "type" "fpspc")
16918 (set_attr "mode" "XF")])
16921 [(set (match_operand:XF 0 "register_operand" "")
16922 (unspec:XF [(float_extend:XF
16923 (match_operand:MODEF 2 "register_operand" ""))]
16924 UNSPEC_SINCOS_COS))
16925 (set (match_operand:XF 1 "register_operand" "")
16926 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
16927 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
16928 && !(reload_completed || reload_in_progress)"
16929 [(set (match_dup 1) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]
16933 [(set (match_operand:XF 0 "register_operand" "")
16934 (unspec:XF [(float_extend:XF
16935 (match_operand:MODEF 2 "register_operand" ""))]
16936 UNSPEC_SINCOS_COS))
16937 (set (match_operand:XF 1 "register_operand" "")
16938 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
16939 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
16940 && !(reload_completed || reload_in_progress)"
16941 [(set (match_dup 0) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]
16944 (define_expand "sincos<mode>3"
16945 [(use (match_operand:MODEF 0 "register_operand" ""))
16946 (use (match_operand:MODEF 1 "register_operand" ""))
16947 (use (match_operand:MODEF 2 "register_operand" ""))]
16948 "TARGET_USE_FANCY_MATH_387
16949 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16950 || TARGET_MIX_SSE_I387)
16951 && flag_unsafe_math_optimizations"
16953 rtx op0 = gen_reg_rtx (XFmode);
16954 rtx op1 = gen_reg_rtx (XFmode);
16956 emit_insn (gen_sincos_extend<mode>xf3_i387 (op0, op1, operands[2]));
16957 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
16958 emit_insn (gen_truncxf<mode>2_i387_noop (operands[1], op1));
16962 (define_insn "fptanxf4_i387"
16963 [(set (match_operand:XF 0 "register_operand" "=f")
16964 (match_operand:XF 3 "const_double_operand" "F"))
16965 (set (match_operand:XF 1 "register_operand" "=u")
16966 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
16968 "TARGET_USE_FANCY_MATH_387
16969 && flag_unsafe_math_optimizations
16970 && standard_80387_constant_p (operands[3]) == 2"
16972 [(set_attr "type" "fpspc")
16973 (set_attr "mode" "XF")])
16975 (define_insn "fptan_extend<mode>xf4_i387"
16976 [(set (match_operand:MODEF 0 "register_operand" "=f")
16977 (match_operand:MODEF 3 "const_double_operand" "F"))
16978 (set (match_operand:XF 1 "register_operand" "=u")
16979 (unspec:XF [(float_extend:XF
16980 (match_operand:MODEF 2 "register_operand" "0"))]
16982 "TARGET_USE_FANCY_MATH_387
16983 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
16984 || TARGET_MIX_SSE_I387)
16985 && flag_unsafe_math_optimizations
16986 && standard_80387_constant_p (operands[3]) == 2"
16988 [(set_attr "type" "fpspc")
16989 (set_attr "mode" "XF")])
16991 (define_expand "tanxf2"
16992 [(use (match_operand:XF 0 "register_operand" ""))
16993 (use (match_operand:XF 1 "register_operand" ""))]
16994 "TARGET_USE_FANCY_MATH_387
16995 && flag_unsafe_math_optimizations"
16997 rtx one = gen_reg_rtx (XFmode);
16998 rtx op2 = CONST1_RTX (XFmode); /* fld1 */
17000 emit_insn (gen_fptanxf4_i387 (one, operands[0], operands[1], op2));
17004 (define_expand "tan<mode>2"
17005 [(use (match_operand:MODEF 0 "register_operand" ""))
17006 (use (match_operand:MODEF 1 "register_operand" ""))]
17007 "TARGET_USE_FANCY_MATH_387
17008 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17009 || TARGET_MIX_SSE_I387)
17010 && flag_unsafe_math_optimizations"
17012 rtx op0 = gen_reg_rtx (XFmode);
17014 rtx one = gen_reg_rtx (<MODE>mode);
17015 rtx op2 = CONST1_RTX (<MODE>mode); /* fld1 */
17017 emit_insn (gen_fptan_extend<mode>xf4_i387 (one, op0,
17018 operands[1], op2));
17019 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17023 (define_insn "*fpatanxf3_i387"
17024 [(set (match_operand:XF 0 "register_operand" "=f")
17025 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
17026 (match_operand:XF 2 "register_operand" "u")]
17028 (clobber (match_scratch:XF 3 "=2"))]
17029 "TARGET_USE_FANCY_MATH_387
17030 && flag_unsafe_math_optimizations"
17032 [(set_attr "type" "fpspc")
17033 (set_attr "mode" "XF")])
17035 (define_insn "fpatan_extend<mode>xf3_i387"
17036 [(set (match_operand:XF 0 "register_operand" "=f")
17037 (unspec:XF [(float_extend:XF
17038 (match_operand:MODEF 1 "register_operand" "0"))
17040 (match_operand:MODEF 2 "register_operand" "u"))]
17042 (clobber (match_scratch:XF 3 "=2"))]
17043 "TARGET_USE_FANCY_MATH_387
17044 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17045 || TARGET_MIX_SSE_I387)
17046 && flag_unsafe_math_optimizations"
17048 [(set_attr "type" "fpspc")
17049 (set_attr "mode" "XF")])
17051 (define_expand "atan2xf3"
17052 [(parallel [(set (match_operand:XF 0 "register_operand" "")
17053 (unspec:XF [(match_operand:XF 2 "register_operand" "")
17054 (match_operand:XF 1 "register_operand" "")]
17056 (clobber (match_scratch:XF 3 ""))])]
17057 "TARGET_USE_FANCY_MATH_387
17058 && flag_unsafe_math_optimizations"
17061 (define_expand "atan2<mode>3"
17062 [(use (match_operand:MODEF 0 "register_operand" ""))
17063 (use (match_operand:MODEF 1 "register_operand" ""))
17064 (use (match_operand:MODEF 2 "register_operand" ""))]
17065 "TARGET_USE_FANCY_MATH_387
17066 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17067 || TARGET_MIX_SSE_I387)
17068 && flag_unsafe_math_optimizations"
17070 rtx op0 = gen_reg_rtx (XFmode);
17072 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, operands[2], operands[1]));
17073 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17077 (define_expand "atanxf2"
17078 [(parallel [(set (match_operand:XF 0 "register_operand" "")
17079 (unspec:XF [(match_dup 2)
17080 (match_operand:XF 1 "register_operand" "")]
17082 (clobber (match_scratch:XF 3 ""))])]
17083 "TARGET_USE_FANCY_MATH_387
17084 && flag_unsafe_math_optimizations"
17086 operands[2] = gen_reg_rtx (XFmode);
17087 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
17090 (define_expand "atan<mode>2"
17091 [(use (match_operand:MODEF 0 "register_operand" ""))
17092 (use (match_operand:MODEF 1 "register_operand" ""))]
17093 "TARGET_USE_FANCY_MATH_387
17094 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17095 || TARGET_MIX_SSE_I387)
17096 && flag_unsafe_math_optimizations"
17098 rtx op0 = gen_reg_rtx (XFmode);
17100 rtx op2 = gen_reg_rtx (<MODE>mode);
17101 emit_move_insn (op2, CONST1_RTX (<MODE>mode)); /* fld1 */
17103 emit_insn (gen_fpatan_extend<mode>xf3_i387 (op0, op2, operands[1]));
17104 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17108 (define_expand "asinxf2"
17109 [(set (match_dup 2)
17110 (mult:XF (match_operand:XF 1 "register_operand" "")
17112 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
17113 (set (match_dup 5) (sqrt:XF (match_dup 4)))
17114 (parallel [(set (match_operand:XF 0 "register_operand" "")
17115 (unspec:XF [(match_dup 5) (match_dup 1)]
17117 (clobber (match_scratch:XF 6 ""))])]
17118 "TARGET_USE_FANCY_MATH_387
17119 && flag_unsafe_math_optimizations && !optimize_size"
17123 for (i = 2; i < 6; i++)
17124 operands[i] = gen_reg_rtx (XFmode);
17126 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
17129 (define_expand "asin<mode>2"
17130 [(use (match_operand:MODEF 0 "register_operand" ""))
17131 (use (match_operand:MODEF 1 "general_operand" ""))]
17132 "TARGET_USE_FANCY_MATH_387
17133 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17134 || TARGET_MIX_SSE_I387)
17135 && flag_unsafe_math_optimizations && !optimize_size"
17137 rtx op0 = gen_reg_rtx (XFmode);
17138 rtx op1 = gen_reg_rtx (XFmode);
17140 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17141 emit_insn (gen_asinxf2 (op0, op1));
17142 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17146 (define_expand "acosxf2"
17147 [(set (match_dup 2)
17148 (mult:XF (match_operand:XF 1 "register_operand" "")
17150 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
17151 (set (match_dup 5) (sqrt:XF (match_dup 4)))
17152 (parallel [(set (match_operand:XF 0 "register_operand" "")
17153 (unspec:XF [(match_dup 1) (match_dup 5)]
17155 (clobber (match_scratch:XF 6 ""))])]
17156 "TARGET_USE_FANCY_MATH_387
17157 && flag_unsafe_math_optimizations && !optimize_size"
17161 for (i = 2; i < 6; i++)
17162 operands[i] = gen_reg_rtx (XFmode);
17164 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
17167 (define_expand "acos<mode>2"
17168 [(use (match_operand:MODEF 0 "register_operand" ""))
17169 (use (match_operand:MODEF 1 "general_operand" ""))]
17170 "TARGET_USE_FANCY_MATH_387
17171 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17172 || TARGET_MIX_SSE_I387)
17173 && flag_unsafe_math_optimizations && !optimize_size"
17175 rtx op0 = gen_reg_rtx (XFmode);
17176 rtx op1 = gen_reg_rtx (XFmode);
17178 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17179 emit_insn (gen_acosxf2 (op0, op1));
17180 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17184 (define_insn "fyl2xxf3_i387"
17185 [(set (match_operand:XF 0 "register_operand" "=f")
17186 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
17187 (match_operand:XF 2 "register_operand" "u")]
17189 (clobber (match_scratch:XF 3 "=2"))]
17190 "TARGET_USE_FANCY_MATH_387
17191 && flag_unsafe_math_optimizations"
17193 [(set_attr "type" "fpspc")
17194 (set_attr "mode" "XF")])
17196 (define_insn "fyl2x_extend<mode>xf3_i387"
17197 [(set (match_operand:XF 0 "register_operand" "=f")
17198 (unspec:XF [(float_extend:XF
17199 (match_operand:MODEF 1 "register_operand" "0"))
17200 (match_operand:XF 2 "register_operand" "u")]
17202 (clobber (match_scratch:XF 3 "=2"))]
17203 "TARGET_USE_FANCY_MATH_387
17204 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17205 || TARGET_MIX_SSE_I387)
17206 && flag_unsafe_math_optimizations"
17208 [(set_attr "type" "fpspc")
17209 (set_attr "mode" "XF")])
17211 (define_expand "logxf2"
17212 [(parallel [(set (match_operand:XF 0 "register_operand" "")
17213 (unspec:XF [(match_operand:XF 1 "register_operand" "")
17214 (match_dup 2)] UNSPEC_FYL2X))
17215 (clobber (match_scratch:XF 3 ""))])]
17216 "TARGET_USE_FANCY_MATH_387
17217 && flag_unsafe_math_optimizations"
17219 operands[2] = gen_reg_rtx (XFmode);
17220 emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */
17223 (define_expand "log<mode>2"
17224 [(use (match_operand:MODEF 0 "register_operand" ""))
17225 (use (match_operand:MODEF 1 "register_operand" ""))]
17226 "TARGET_USE_FANCY_MATH_387
17227 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17228 || TARGET_MIX_SSE_I387)
17229 && flag_unsafe_math_optimizations"
17231 rtx op0 = gen_reg_rtx (XFmode);
17233 rtx op2 = gen_reg_rtx (XFmode);
17234 emit_move_insn (op2, standard_80387_constant_rtx (4)); /* fldln2 */
17236 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
17237 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17241 (define_expand "log10xf2"
17242 [(parallel [(set (match_operand:XF 0 "register_operand" "")
17243 (unspec:XF [(match_operand:XF 1 "register_operand" "")
17244 (match_dup 2)] UNSPEC_FYL2X))
17245 (clobber (match_scratch:XF 3 ""))])]
17246 "TARGET_USE_FANCY_MATH_387
17247 && flag_unsafe_math_optimizations"
17249 operands[2] = gen_reg_rtx (XFmode);
17250 emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */
17253 (define_expand "log10<mode>2"
17254 [(use (match_operand:MODEF 0 "register_operand" ""))
17255 (use (match_operand:MODEF 1 "register_operand" ""))]
17256 "TARGET_USE_FANCY_MATH_387
17257 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17258 || TARGET_MIX_SSE_I387)
17259 && flag_unsafe_math_optimizations"
17261 rtx op0 = gen_reg_rtx (XFmode);
17263 rtx op2 = gen_reg_rtx (XFmode);
17264 emit_move_insn (op2, standard_80387_constant_rtx (3)); /* fldlg2 */
17266 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
17267 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17271 (define_expand "log2xf2"
17272 [(parallel [(set (match_operand:XF 0 "register_operand" "")
17273 (unspec:XF [(match_operand:XF 1 "register_operand" "")
17274 (match_dup 2)] UNSPEC_FYL2X))
17275 (clobber (match_scratch:XF 3 ""))])]
17276 "TARGET_USE_FANCY_MATH_387
17277 && flag_unsafe_math_optimizations"
17279 operands[2] = gen_reg_rtx (XFmode);
17280 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
17283 (define_expand "log2<mode>2"
17284 [(use (match_operand:MODEF 0 "register_operand" ""))
17285 (use (match_operand:MODEF 1 "register_operand" ""))]
17286 "TARGET_USE_FANCY_MATH_387
17287 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17288 || TARGET_MIX_SSE_I387)
17289 && flag_unsafe_math_optimizations"
17291 rtx op0 = gen_reg_rtx (XFmode);
17293 rtx op2 = gen_reg_rtx (XFmode);
17294 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
17296 emit_insn (gen_fyl2x_extend<mode>xf3_i387 (op0, operands[1], op2));
17297 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17301 (define_insn "fyl2xp1xf3_i387"
17302 [(set (match_operand:XF 0 "register_operand" "=f")
17303 (unspec:XF [(match_operand:XF 1 "register_operand" "0")
17304 (match_operand:XF 2 "register_operand" "u")]
17306 (clobber (match_scratch:XF 3 "=2"))]
17307 "TARGET_USE_FANCY_MATH_387
17308 && flag_unsafe_math_optimizations"
17310 [(set_attr "type" "fpspc")
17311 (set_attr "mode" "XF")])
17313 (define_insn "fyl2xp1_extend<mode>xf3_i387"
17314 [(set (match_operand:XF 0 "register_operand" "=f")
17315 (unspec:XF [(float_extend:XF
17316 (match_operand:MODEF 1 "register_operand" "0"))
17317 (match_operand:XF 2 "register_operand" "u")]
17319 (clobber (match_scratch:XF 3 "=2"))]
17320 "TARGET_USE_FANCY_MATH_387
17321 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17322 || TARGET_MIX_SSE_I387)
17323 && flag_unsafe_math_optimizations"
17325 [(set_attr "type" "fpspc")
17326 (set_attr "mode" "XF")])
17328 (define_expand "log1pxf2"
17329 [(use (match_operand:XF 0 "register_operand" ""))
17330 (use (match_operand:XF 1 "register_operand" ""))]
17331 "TARGET_USE_FANCY_MATH_387
17332 && flag_unsafe_math_optimizations && !optimize_size"
17334 ix86_emit_i387_log1p (operands[0], operands[1]);
17338 (define_expand "log1p<mode>2"
17339 [(use (match_operand:MODEF 0 "register_operand" ""))
17340 (use (match_operand:MODEF 1 "register_operand" ""))]
17341 "TARGET_USE_FANCY_MATH_387
17342 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17343 || TARGET_MIX_SSE_I387)
17344 && flag_unsafe_math_optimizations && !optimize_size"
17346 rtx op0 = gen_reg_rtx (XFmode);
17348 operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]);
17350 ix86_emit_i387_log1p (op0, operands[1]);
17351 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17355 (define_insn "fxtractxf3_i387"
17356 [(set (match_operand:XF 0 "register_operand" "=f")
17357 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
17358 UNSPEC_XTRACT_FRACT))
17359 (set (match_operand:XF 1 "register_operand" "=u")
17360 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
17361 "TARGET_USE_FANCY_MATH_387
17362 && flag_unsafe_math_optimizations"
17364 [(set_attr "type" "fpspc")
17365 (set_attr "mode" "XF")])
17367 (define_insn "fxtract_extend<mode>xf3_i387"
17368 [(set (match_operand:XF 0 "register_operand" "=f")
17369 (unspec:XF [(float_extend:XF
17370 (match_operand:MODEF 2 "register_operand" "0"))]
17371 UNSPEC_XTRACT_FRACT))
17372 (set (match_operand:XF 1 "register_operand" "=u")
17373 (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))]
17374 "TARGET_USE_FANCY_MATH_387
17375 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17376 || TARGET_MIX_SSE_I387)
17377 && flag_unsafe_math_optimizations"
17379 [(set_attr "type" "fpspc")
17380 (set_attr "mode" "XF")])
17382 (define_expand "logbxf2"
17383 [(parallel [(set (match_dup 2)
17384 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
17385 UNSPEC_XTRACT_FRACT))
17386 (set (match_operand:XF 0 "register_operand" "")
17387 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
17388 "TARGET_USE_FANCY_MATH_387
17389 && flag_unsafe_math_optimizations"
17391 operands[2] = gen_reg_rtx (XFmode);
17394 (define_expand "logb<mode>2"
17395 [(use (match_operand:MODEF 0 "register_operand" ""))
17396 (use (match_operand:MODEF 1 "register_operand" ""))]
17397 "TARGET_USE_FANCY_MATH_387
17398 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17399 || TARGET_MIX_SSE_I387)
17400 && flag_unsafe_math_optimizations"
17402 rtx op0 = gen_reg_rtx (XFmode);
17403 rtx op1 = gen_reg_rtx (XFmode);
17405 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
17406 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op1));
17410 (define_expand "ilogbxf2"
17411 [(use (match_operand:SI 0 "register_operand" ""))
17412 (use (match_operand:XF 1 "register_operand" ""))]
17413 "TARGET_USE_FANCY_MATH_387
17414 && flag_unsafe_math_optimizations && !optimize_size"
17416 rtx op0 = gen_reg_rtx (XFmode);
17417 rtx op1 = gen_reg_rtx (XFmode);
17419 emit_insn (gen_fxtractxf3_i387 (op0, op1, operands[1]));
17420 emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
17424 (define_expand "ilogb<mode>2"
17425 [(use (match_operand:SI 0 "register_operand" ""))
17426 (use (match_operand:MODEF 1 "register_operand" ""))]
17427 "TARGET_USE_FANCY_MATH_387
17428 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17429 || TARGET_MIX_SSE_I387)
17430 && flag_unsafe_math_optimizations && !optimize_size"
17432 rtx op0 = gen_reg_rtx (XFmode);
17433 rtx op1 = gen_reg_rtx (XFmode);
17435 emit_insn (gen_fxtract_extend<mode>xf3_i387 (op0, op1, operands[1]));
17436 emit_insn (gen_fix_truncxfsi2 (operands[0], op1));
17440 (define_insn "*f2xm1xf2_i387"
17441 [(set (match_operand:XF 0 "register_operand" "=f")
17442 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17444 "TARGET_USE_FANCY_MATH_387
17445 && flag_unsafe_math_optimizations"
17447 [(set_attr "type" "fpspc")
17448 (set_attr "mode" "XF")])
17450 (define_insn "*fscalexf4_i387"
17451 [(set (match_operand:XF 0 "register_operand" "=f")
17452 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
17453 (match_operand:XF 3 "register_operand" "1")]
17454 UNSPEC_FSCALE_FRACT))
17455 (set (match_operand:XF 1 "register_operand" "=u")
17456 (unspec:XF [(match_dup 2) (match_dup 3)]
17457 UNSPEC_FSCALE_EXP))]
17458 "TARGET_USE_FANCY_MATH_387
17459 && flag_unsafe_math_optimizations"
17461 [(set_attr "type" "fpspc")
17462 (set_attr "mode" "XF")])
17464 (define_expand "expNcorexf3"
17465 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
17466 (match_operand:XF 2 "register_operand" "")))
17467 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
17468 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
17469 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
17470 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
17471 (parallel [(set (match_operand:XF 0 "register_operand" "")
17472 (unspec:XF [(match_dup 8) (match_dup 4)]
17473 UNSPEC_FSCALE_FRACT))
17475 (unspec:XF [(match_dup 8) (match_dup 4)]
17476 UNSPEC_FSCALE_EXP))])]
17477 "TARGET_USE_FANCY_MATH_387
17478 && flag_unsafe_math_optimizations && !optimize_size"
17482 for (i = 3; i < 10; i++)
17483 operands[i] = gen_reg_rtx (XFmode);
17485 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
17488 (define_expand "expxf2"
17489 [(use (match_operand:XF 0 "register_operand" ""))
17490 (use (match_operand:XF 1 "register_operand" ""))]
17491 "TARGET_USE_FANCY_MATH_387
17492 && flag_unsafe_math_optimizations && !optimize_size"
17494 rtx op2 = gen_reg_rtx (XFmode);
17495 emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */
17497 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
17501 (define_expand "exp<mode>2"
17502 [(use (match_operand:MODEF 0 "register_operand" ""))
17503 (use (match_operand:MODEF 1 "general_operand" ""))]
17504 "TARGET_USE_FANCY_MATH_387
17505 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17506 || TARGET_MIX_SSE_I387)
17507 && flag_unsafe_math_optimizations && !optimize_size"
17509 rtx op0 = gen_reg_rtx (XFmode);
17510 rtx op1 = gen_reg_rtx (XFmode);
17512 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17513 emit_insn (gen_expxf2 (op0, op1));
17514 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17518 (define_expand "exp10xf2"
17519 [(use (match_operand:XF 0 "register_operand" ""))
17520 (use (match_operand:XF 1 "register_operand" ""))]
17521 "TARGET_USE_FANCY_MATH_387
17522 && flag_unsafe_math_optimizations && !optimize_size"
17524 rtx op2 = gen_reg_rtx (XFmode);
17525 emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */
17527 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
17531 (define_expand "exp10<mode>2"
17532 [(use (match_operand:MODEF 0 "register_operand" ""))
17533 (use (match_operand:MODEF 1 "general_operand" ""))]
17534 "TARGET_USE_FANCY_MATH_387
17535 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17536 || TARGET_MIX_SSE_I387)
17537 && flag_unsafe_math_optimizations && !optimize_size"
17539 rtx op0 = gen_reg_rtx (XFmode);
17540 rtx op1 = gen_reg_rtx (XFmode);
17542 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17543 emit_insn (gen_exp10xf2 (op0, op1));
17544 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17548 (define_expand "exp2xf2"
17549 [(use (match_operand:XF 0 "register_operand" ""))
17550 (use (match_operand:XF 1 "register_operand" ""))]
17551 "TARGET_USE_FANCY_MATH_387
17552 && flag_unsafe_math_optimizations && !optimize_size"
17554 rtx op2 = gen_reg_rtx (XFmode);
17555 emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */
17557 emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2));
17561 (define_expand "exp2<mode>2"
17562 [(use (match_operand:MODEF 0 "register_operand" ""))
17563 (use (match_operand:MODEF 1 "general_operand" ""))]
17564 "TARGET_USE_FANCY_MATH_387
17565 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17566 || TARGET_MIX_SSE_I387)
17567 && flag_unsafe_math_optimizations && !optimize_size"
17569 rtx op0 = gen_reg_rtx (XFmode);
17570 rtx op1 = gen_reg_rtx (XFmode);
17572 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17573 emit_insn (gen_exp2xf2 (op0, op1));
17574 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17578 (define_expand "expm1xf2"
17579 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
17581 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
17582 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
17583 (set (match_dup 9) (float_extend:XF (match_dup 13)))
17584 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
17585 (parallel [(set (match_dup 7)
17586 (unspec:XF [(match_dup 6) (match_dup 4)]
17587 UNSPEC_FSCALE_FRACT))
17589 (unspec:XF [(match_dup 6) (match_dup 4)]
17590 UNSPEC_FSCALE_EXP))])
17591 (parallel [(set (match_dup 10)
17592 (unspec:XF [(match_dup 9) (match_dup 8)]
17593 UNSPEC_FSCALE_FRACT))
17594 (set (match_dup 11)
17595 (unspec:XF [(match_dup 9) (match_dup 8)]
17596 UNSPEC_FSCALE_EXP))])
17597 (set (match_dup 12) (minus:XF (match_dup 10)
17598 (float_extend:XF (match_dup 13))))
17599 (set (match_operand:XF 0 "register_operand" "")
17600 (plus:XF (match_dup 12) (match_dup 7)))]
17601 "TARGET_USE_FANCY_MATH_387
17602 && flag_unsafe_math_optimizations && !optimize_size"
17606 for (i = 2; i < 13; i++)
17607 operands[i] = gen_reg_rtx (XFmode);
17610 = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */
17612 emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */
17615 (define_expand "expm1<mode>2"
17616 [(use (match_operand:MODEF 0 "register_operand" ""))
17617 (use (match_operand:MODEF 1 "general_operand" ""))]
17618 "TARGET_USE_FANCY_MATH_387
17619 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17620 || TARGET_MIX_SSE_I387)
17621 && flag_unsafe_math_optimizations && !optimize_size"
17623 rtx op0 = gen_reg_rtx (XFmode);
17624 rtx op1 = gen_reg_rtx (XFmode);
17626 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17627 emit_insn (gen_expm1xf2 (op0, op1));
17628 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17632 (define_expand "ldexpxf3"
17633 [(set (match_dup 3)
17634 (float:XF (match_operand:SI 2 "register_operand" "")))
17635 (parallel [(set (match_operand:XF 0 " register_operand" "")
17636 (unspec:XF [(match_operand:XF 1 "register_operand" "")
17638 UNSPEC_FSCALE_FRACT))
17640 (unspec:XF [(match_dup 1) (match_dup 3)]
17641 UNSPEC_FSCALE_EXP))])]
17642 "TARGET_USE_FANCY_MATH_387
17643 && flag_unsafe_math_optimizations && !optimize_size"
17645 operands[3] = gen_reg_rtx (XFmode);
17646 operands[4] = gen_reg_rtx (XFmode);
17649 (define_expand "ldexp<mode>3"
17650 [(use (match_operand:MODEF 0 "register_operand" ""))
17651 (use (match_operand:MODEF 1 "general_operand" ""))
17652 (use (match_operand:SI 2 "register_operand" ""))]
17653 "TARGET_USE_FANCY_MATH_387
17654 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17655 || TARGET_MIX_SSE_I387)
17656 && flag_unsafe_math_optimizations && !optimize_size"
17658 rtx op0 = gen_reg_rtx (XFmode);
17659 rtx op1 = gen_reg_rtx (XFmode);
17661 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17662 emit_insn (gen_ldexpxf3 (op0, op1, operands[2]));
17663 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17667 (define_expand "scalbxf3"
17668 [(parallel [(set (match_operand:XF 0 " register_operand" "")
17669 (unspec:XF [(match_operand:XF 1 "register_operand" "")
17670 (match_operand:XF 2 "register_operand" "")]
17671 UNSPEC_FSCALE_FRACT))
17673 (unspec:XF [(match_dup 1) (match_dup 2)]
17674 UNSPEC_FSCALE_EXP))])]
17675 "TARGET_USE_FANCY_MATH_387
17676 && flag_unsafe_math_optimizations && !optimize_size"
17678 operands[3] = gen_reg_rtx (XFmode);
17681 (define_expand "scalb<mode>3"
17682 [(use (match_operand:MODEF 0 "register_operand" ""))
17683 (use (match_operand:MODEF 1 "general_operand" ""))
17684 (use (match_operand:MODEF 2 "register_operand" ""))]
17685 "TARGET_USE_FANCY_MATH_387
17686 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17687 || TARGET_MIX_SSE_I387)
17688 && flag_unsafe_math_optimizations && !optimize_size"
17690 rtx op0 = gen_reg_rtx (XFmode);
17691 rtx op1 = gen_reg_rtx (XFmode);
17692 rtx op2 = gen_reg_rtx (XFmode);
17694 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17695 emit_insn (gen_extend<mode>xf2 (op2, operands[2]));
17696 emit_insn (gen_scalbxf3 (op0, op1, op2));
17697 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17702 (define_insn "sse4_1_round<mode>2"
17703 [(set (match_operand:MODEF 0 "register_operand" "=x")
17704 (unspec:MODEF [(match_operand:MODEF 1 "register_operand" "x")
17705 (match_operand:SI 2 "const_0_to_15_operand" "n")]
17708 "rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
17709 [(set_attr "type" "ssecvt")
17710 (set_attr "prefix_extra" "1")
17711 (set_attr "mode" "<MODE>")])
17713 (define_insn "rintxf2"
17714 [(set (match_operand:XF 0 "register_operand" "=f")
17715 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17717 "TARGET_USE_FANCY_MATH_387
17718 && flag_unsafe_math_optimizations"
17720 [(set_attr "type" "fpspc")
17721 (set_attr "mode" "XF")])
17723 (define_expand "rint<mode>2"
17724 [(use (match_operand:MODEF 0 "register_operand" ""))
17725 (use (match_operand:MODEF 1 "register_operand" ""))]
17726 "(TARGET_USE_FANCY_MATH_387
17727 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17728 || TARGET_MIX_SSE_I387)
17729 && flag_unsafe_math_optimizations)
17730 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
17731 && !flag_trapping_math
17732 && (TARGET_ROUND || !optimize_size))"
17734 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
17735 && !flag_trapping_math
17736 && (TARGET_ROUND || !optimize_size))
17739 emit_insn (gen_sse4_1_round<mode>2
17740 (operands[0], operands[1], GEN_INT (0x04)));
17742 ix86_expand_rint (operand0, operand1);
17746 rtx op0 = gen_reg_rtx (XFmode);
17747 rtx op1 = gen_reg_rtx (XFmode);
17749 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17750 emit_insn (gen_rintxf2 (op0, op1));
17752 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
17757 (define_expand "round<mode>2"
17758 [(match_operand:MODEF 0 "register_operand" "")
17759 (match_operand:MODEF 1 "nonimmediate_operand" "")]
17760 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
17761 && !flag_trapping_math && !flag_rounding_math
17764 if (TARGET_64BIT || (<MODE>mode != DFmode))
17765 ix86_expand_round (operand0, operand1);
17767 ix86_expand_rounddf_32 (operand0, operand1);
17771 (define_insn_and_split "*fistdi2_1"
17772 [(set (match_operand:DI 0 "nonimmediate_operand" "")
17773 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
17775 "TARGET_USE_FANCY_MATH_387
17776 && !(reload_completed || reload_in_progress)"
17781 if (memory_operand (operands[0], VOIDmode))
17782 emit_insn (gen_fistdi2 (operands[0], operands[1]));
17785 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
17786 emit_insn (gen_fistdi2_with_temp (operands[0], operands[1],
17791 [(set_attr "type" "fpspc")
17792 (set_attr "mode" "DI")])
17794 (define_insn "fistdi2"
17795 [(set (match_operand:DI 0 "memory_operand" "=m")
17796 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
17798 (clobber (match_scratch:XF 2 "=&1f"))]
17799 "TARGET_USE_FANCY_MATH_387"
17800 "* return output_fix_trunc (insn, operands, 0);"
17801 [(set_attr "type" "fpspc")
17802 (set_attr "mode" "DI")])
17804 (define_insn "fistdi2_with_temp"
17805 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
17806 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
17808 (clobber (match_operand:DI 2 "memory_operand" "=m,m"))
17809 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
17810 "TARGET_USE_FANCY_MATH_387"
17812 [(set_attr "type" "fpspc")
17813 (set_attr "mode" "DI")])
17816 [(set (match_operand:DI 0 "register_operand" "")
17817 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
17819 (clobber (match_operand:DI 2 "memory_operand" ""))
17820 (clobber (match_scratch 3 ""))]
17822 [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
17823 (clobber (match_dup 3))])
17824 (set (match_dup 0) (match_dup 2))]
17828 [(set (match_operand:DI 0 "memory_operand" "")
17829 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
17831 (clobber (match_operand:DI 2 "memory_operand" ""))
17832 (clobber (match_scratch 3 ""))]
17834 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
17835 (clobber (match_dup 3))])]
17838 (define_insn_and_split "*fist<mode>2_1"
17839 [(set (match_operand:X87MODEI12 0 "register_operand" "")
17840 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
17842 "TARGET_USE_FANCY_MATH_387
17843 && !(reload_completed || reload_in_progress)"
17848 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
17849 emit_insn (gen_fist<mode>2_with_temp (operands[0], operands[1],
17853 [(set_attr "type" "fpspc")
17854 (set_attr "mode" "<MODE>")])
17856 (define_insn "fist<mode>2"
17857 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
17858 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
17860 "TARGET_USE_FANCY_MATH_387"
17861 "* return output_fix_trunc (insn, operands, 0);"
17862 [(set_attr "type" "fpspc")
17863 (set_attr "mode" "<MODE>")])
17865 (define_insn "fist<mode>2_with_temp"
17866 [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
17867 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
17869 (clobber (match_operand:X87MODEI12 2 "memory_operand" "=m"))]
17870 "TARGET_USE_FANCY_MATH_387"
17872 [(set_attr "type" "fpspc")
17873 (set_attr "mode" "<MODE>")])
17876 [(set (match_operand:X87MODEI12 0 "register_operand" "")
17877 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
17879 (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
17881 [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))
17882 (set (match_dup 0) (match_dup 2))]
17886 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
17887 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
17889 (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
17891 [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))]
17894 (define_expand "lrintxf<mode>2"
17895 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
17896 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
17898 "TARGET_USE_FANCY_MATH_387"
17901 (define_expand "lrint<MODEF:mode><SSEMODEI24:mode>2"
17902 [(set (match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
17903 (unspec:SSEMODEI24 [(match_operand:MODEF 1 "register_operand" "")]
17904 UNSPEC_FIX_NOTRUNC))]
17905 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
17906 && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)"
17909 (define_expand "lround<MODEF:mode><SSEMODEI24:mode>2"
17910 [(match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
17911 (match_operand:MODEF 1 "register_operand" "")]
17912 "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
17913 && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)
17914 && !flag_trapping_math && !flag_rounding_math
17917 ix86_expand_lround (operand0, operand1);
17921 ;; Rounding mode control word calculation could clobber FLAGS_REG.
17922 (define_insn_and_split "frndintxf2_floor"
17923 [(set (match_operand:XF 0 "register_operand" "")
17924 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
17925 UNSPEC_FRNDINT_FLOOR))
17926 (clobber (reg:CC FLAGS_REG))]
17927 "TARGET_USE_FANCY_MATH_387
17928 && flag_unsafe_math_optimizations
17929 && !(reload_completed || reload_in_progress)"
17934 ix86_optimize_mode_switching[I387_FLOOR] = 1;
17936 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
17937 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
17939 emit_insn (gen_frndintxf2_floor_i387 (operands[0], operands[1],
17940 operands[2], operands[3]));
17943 [(set_attr "type" "frndint")
17944 (set_attr "i387_cw" "floor")
17945 (set_attr "mode" "XF")])
17947 (define_insn "frndintxf2_floor_i387"
17948 [(set (match_operand:XF 0 "register_operand" "=f")
17949 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17950 UNSPEC_FRNDINT_FLOOR))
17951 (use (match_operand:HI 2 "memory_operand" "m"))
17952 (use (match_operand:HI 3 "memory_operand" "m"))]
17953 "TARGET_USE_FANCY_MATH_387
17954 && flag_unsafe_math_optimizations"
17955 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
17956 [(set_attr "type" "frndint")
17957 (set_attr "i387_cw" "floor")
17958 (set_attr "mode" "XF")])
17960 (define_expand "floorxf2"
17961 [(use (match_operand:XF 0 "register_operand" ""))
17962 (use (match_operand:XF 1 "register_operand" ""))]
17963 "TARGET_USE_FANCY_MATH_387
17964 && flag_unsafe_math_optimizations && !optimize_size"
17966 emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
17970 (define_expand "floor<mode>2"
17971 [(use (match_operand:MODEF 0 "register_operand" ""))
17972 (use (match_operand:MODEF 1 "register_operand" ""))]
17973 "(TARGET_USE_FANCY_MATH_387
17974 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
17975 || TARGET_MIX_SSE_I387)
17976 && flag_unsafe_math_optimizations && !optimize_size)
17977 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
17978 && !flag_trapping_math
17979 && (TARGET_ROUND || !optimize_size))"
17981 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
17982 && !flag_trapping_math
17983 && (TARGET_ROUND || !optimize_size))
17986 emit_insn (gen_sse4_1_round<mode>2
17987 (operands[0], operands[1], GEN_INT (0x01)));
17988 else if (TARGET_64BIT || (<MODE>mode != DFmode))
17989 ix86_expand_floorceil (operand0, operand1, true);
17991 ix86_expand_floorceildf_32 (operand0, operand1, true);
17995 rtx op0 = gen_reg_rtx (XFmode);
17996 rtx op1 = gen_reg_rtx (XFmode);
17998 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
17999 emit_insn (gen_frndintxf2_floor (op0, op1));
18001 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
18006 (define_insn_and_split "*fist<mode>2_floor_1"
18007 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
18008 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
18009 UNSPEC_FIST_FLOOR))
18010 (clobber (reg:CC FLAGS_REG))]
18011 "TARGET_USE_FANCY_MATH_387
18012 && flag_unsafe_math_optimizations
18013 && !(reload_completed || reload_in_progress)"
18018 ix86_optimize_mode_switching[I387_FLOOR] = 1;
18020 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
18021 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
18022 if (memory_operand (operands[0], VOIDmode))
18023 emit_insn (gen_fist<mode>2_floor (operands[0], operands[1],
18024 operands[2], operands[3]));
18027 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
18028 emit_insn (gen_fist<mode>2_floor_with_temp (operands[0], operands[1],
18029 operands[2], operands[3],
18034 [(set_attr "type" "fistp")
18035 (set_attr "i387_cw" "floor")
18036 (set_attr "mode" "<MODE>")])
18038 (define_insn "fistdi2_floor"
18039 [(set (match_operand:DI 0 "memory_operand" "=m")
18040 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
18041 UNSPEC_FIST_FLOOR))
18042 (use (match_operand:HI 2 "memory_operand" "m"))
18043 (use (match_operand:HI 3 "memory_operand" "m"))
18044 (clobber (match_scratch:XF 4 "=&1f"))]
18045 "TARGET_USE_FANCY_MATH_387
18046 && flag_unsafe_math_optimizations"
18047 "* return output_fix_trunc (insn, operands, 0);"
18048 [(set_attr "type" "fistp")
18049 (set_attr "i387_cw" "floor")
18050 (set_attr "mode" "DI")])
18052 (define_insn "fistdi2_floor_with_temp"
18053 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
18054 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
18055 UNSPEC_FIST_FLOOR))
18056 (use (match_operand:HI 2 "memory_operand" "m,m"))
18057 (use (match_operand:HI 3 "memory_operand" "m,m"))
18058 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
18059 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
18060 "TARGET_USE_FANCY_MATH_387
18061 && flag_unsafe_math_optimizations"
18063 [(set_attr "type" "fistp")
18064 (set_attr "i387_cw" "floor")
18065 (set_attr "mode" "DI")])
18068 [(set (match_operand:DI 0 "register_operand" "")
18069 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
18070 UNSPEC_FIST_FLOOR))
18071 (use (match_operand:HI 2 "memory_operand" ""))
18072 (use (match_operand:HI 3 "memory_operand" ""))
18073 (clobber (match_operand:DI 4 "memory_operand" ""))
18074 (clobber (match_scratch 5 ""))]
18076 [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
18077 (use (match_dup 2))
18078 (use (match_dup 3))
18079 (clobber (match_dup 5))])
18080 (set (match_dup 0) (match_dup 4))]
18084 [(set (match_operand:DI 0 "memory_operand" "")
18085 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
18086 UNSPEC_FIST_FLOOR))
18087 (use (match_operand:HI 2 "memory_operand" ""))
18088 (use (match_operand:HI 3 "memory_operand" ""))
18089 (clobber (match_operand:DI 4 "memory_operand" ""))
18090 (clobber (match_scratch 5 ""))]
18092 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
18093 (use (match_dup 2))
18094 (use (match_dup 3))
18095 (clobber (match_dup 5))])]
18098 (define_insn "fist<mode>2_floor"
18099 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
18100 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
18101 UNSPEC_FIST_FLOOR))
18102 (use (match_operand:HI 2 "memory_operand" "m"))
18103 (use (match_operand:HI 3 "memory_operand" "m"))]
18104 "TARGET_USE_FANCY_MATH_387
18105 && flag_unsafe_math_optimizations"
18106 "* return output_fix_trunc (insn, operands, 0);"
18107 [(set_attr "type" "fistp")
18108 (set_attr "i387_cw" "floor")
18109 (set_attr "mode" "<MODE>")])
18111 (define_insn "fist<mode>2_floor_with_temp"
18112 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
18113 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
18114 UNSPEC_FIST_FLOOR))
18115 (use (match_operand:HI 2 "memory_operand" "m,m"))
18116 (use (match_operand:HI 3 "memory_operand" "m,m"))
18117 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
18118 "TARGET_USE_FANCY_MATH_387
18119 && flag_unsafe_math_optimizations"
18121 [(set_attr "type" "fistp")
18122 (set_attr "i387_cw" "floor")
18123 (set_attr "mode" "<MODE>")])
18126 [(set (match_operand:X87MODEI12 0 "register_operand" "")
18127 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
18128 UNSPEC_FIST_FLOOR))
18129 (use (match_operand:HI 2 "memory_operand" ""))
18130 (use (match_operand:HI 3 "memory_operand" ""))
18131 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
18133 [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
18134 UNSPEC_FIST_FLOOR))
18135 (use (match_dup 2))
18136 (use (match_dup 3))])
18137 (set (match_dup 0) (match_dup 4))]
18141 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
18142 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
18143 UNSPEC_FIST_FLOOR))
18144 (use (match_operand:HI 2 "memory_operand" ""))
18145 (use (match_operand:HI 3 "memory_operand" ""))
18146 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
18148 [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
18149 UNSPEC_FIST_FLOOR))
18150 (use (match_dup 2))
18151 (use (match_dup 3))])]
18154 (define_expand "lfloorxf<mode>2"
18155 [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
18156 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
18157 UNSPEC_FIST_FLOOR))
18158 (clobber (reg:CC FLAGS_REG))])]
18159 "TARGET_USE_FANCY_MATH_387
18160 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
18161 && flag_unsafe_math_optimizations"
18164 (define_expand "lfloor<mode>di2"
18165 [(match_operand:DI 0 "nonimmediate_operand" "")
18166 (match_operand:MODEF 1 "register_operand" "")]
18167 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
18168 && !flag_trapping_math
18171 ix86_expand_lfloorceil (operand0, operand1, true);
18175 (define_expand "lfloor<mode>si2"
18176 [(match_operand:SI 0 "nonimmediate_operand" "")
18177 (match_operand:MODEF 1 "register_operand" "")]
18178 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18179 && !flag_trapping_math
18180 && (!optimize_size || !TARGET_64BIT)"
18182 ix86_expand_lfloorceil (operand0, operand1, true);
18186 ;; Rounding mode control word calculation could clobber FLAGS_REG.
18187 (define_insn_and_split "frndintxf2_ceil"
18188 [(set (match_operand:XF 0 "register_operand" "")
18189 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
18190 UNSPEC_FRNDINT_CEIL))
18191 (clobber (reg:CC FLAGS_REG))]
18192 "TARGET_USE_FANCY_MATH_387
18193 && flag_unsafe_math_optimizations
18194 && !(reload_completed || reload_in_progress)"
18199 ix86_optimize_mode_switching[I387_CEIL] = 1;
18201 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
18202 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
18204 emit_insn (gen_frndintxf2_ceil_i387 (operands[0], operands[1],
18205 operands[2], operands[3]));
18208 [(set_attr "type" "frndint")
18209 (set_attr "i387_cw" "ceil")
18210 (set_attr "mode" "XF")])
18212 (define_insn "frndintxf2_ceil_i387"
18213 [(set (match_operand:XF 0 "register_operand" "=f")
18214 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
18215 UNSPEC_FRNDINT_CEIL))
18216 (use (match_operand:HI 2 "memory_operand" "m"))
18217 (use (match_operand:HI 3 "memory_operand" "m"))]
18218 "TARGET_USE_FANCY_MATH_387
18219 && flag_unsafe_math_optimizations"
18220 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
18221 [(set_attr "type" "frndint")
18222 (set_attr "i387_cw" "ceil")
18223 (set_attr "mode" "XF")])
18225 (define_expand "ceilxf2"
18226 [(use (match_operand:XF 0 "register_operand" ""))
18227 (use (match_operand:XF 1 "register_operand" ""))]
18228 "TARGET_USE_FANCY_MATH_387
18229 && flag_unsafe_math_optimizations && !optimize_size"
18231 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
18235 (define_expand "ceil<mode>2"
18236 [(use (match_operand:MODEF 0 "register_operand" ""))
18237 (use (match_operand:MODEF 1 "register_operand" ""))]
18238 "(TARGET_USE_FANCY_MATH_387
18239 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
18240 || TARGET_MIX_SSE_I387)
18241 && flag_unsafe_math_optimizations && !optimize_size)
18242 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18243 && !flag_trapping_math
18244 && (TARGET_ROUND || !optimize_size))"
18246 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18247 && !flag_trapping_math
18248 && (TARGET_ROUND || !optimize_size))
18251 emit_insn (gen_sse4_1_round<mode>2
18252 (operands[0], operands[1], GEN_INT (0x02)));
18253 else if (TARGET_64BIT || (<MODE>mode != DFmode))
18254 ix86_expand_floorceil (operand0, operand1, false);
18256 ix86_expand_floorceildf_32 (operand0, operand1, false);
18260 rtx op0 = gen_reg_rtx (XFmode);
18261 rtx op1 = gen_reg_rtx (XFmode);
18263 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
18264 emit_insn (gen_frndintxf2_ceil (op0, op1));
18266 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
18271 (define_insn_and_split "*fist<mode>2_ceil_1"
18272 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
18273 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
18275 (clobber (reg:CC FLAGS_REG))]
18276 "TARGET_USE_FANCY_MATH_387
18277 && flag_unsafe_math_optimizations
18278 && !(reload_completed || reload_in_progress)"
18283 ix86_optimize_mode_switching[I387_CEIL] = 1;
18285 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
18286 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
18287 if (memory_operand (operands[0], VOIDmode))
18288 emit_insn (gen_fist<mode>2_ceil (operands[0], operands[1],
18289 operands[2], operands[3]));
18292 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
18293 emit_insn (gen_fist<mode>2_ceil_with_temp (operands[0], operands[1],
18294 operands[2], operands[3],
18299 [(set_attr "type" "fistp")
18300 (set_attr "i387_cw" "ceil")
18301 (set_attr "mode" "<MODE>")])
18303 (define_insn "fistdi2_ceil"
18304 [(set (match_operand:DI 0 "memory_operand" "=m")
18305 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
18307 (use (match_operand:HI 2 "memory_operand" "m"))
18308 (use (match_operand:HI 3 "memory_operand" "m"))
18309 (clobber (match_scratch:XF 4 "=&1f"))]
18310 "TARGET_USE_FANCY_MATH_387
18311 && flag_unsafe_math_optimizations"
18312 "* return output_fix_trunc (insn, operands, 0);"
18313 [(set_attr "type" "fistp")
18314 (set_attr "i387_cw" "ceil")
18315 (set_attr "mode" "DI")])
18317 (define_insn "fistdi2_ceil_with_temp"
18318 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
18319 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
18321 (use (match_operand:HI 2 "memory_operand" "m,m"))
18322 (use (match_operand:HI 3 "memory_operand" "m,m"))
18323 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
18324 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
18325 "TARGET_USE_FANCY_MATH_387
18326 && flag_unsafe_math_optimizations"
18328 [(set_attr "type" "fistp")
18329 (set_attr "i387_cw" "ceil")
18330 (set_attr "mode" "DI")])
18333 [(set (match_operand:DI 0 "register_operand" "")
18334 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
18336 (use (match_operand:HI 2 "memory_operand" ""))
18337 (use (match_operand:HI 3 "memory_operand" ""))
18338 (clobber (match_operand:DI 4 "memory_operand" ""))
18339 (clobber (match_scratch 5 ""))]
18341 [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
18342 (use (match_dup 2))
18343 (use (match_dup 3))
18344 (clobber (match_dup 5))])
18345 (set (match_dup 0) (match_dup 4))]
18349 [(set (match_operand:DI 0 "memory_operand" "")
18350 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
18352 (use (match_operand:HI 2 "memory_operand" ""))
18353 (use (match_operand:HI 3 "memory_operand" ""))
18354 (clobber (match_operand:DI 4 "memory_operand" ""))
18355 (clobber (match_scratch 5 ""))]
18357 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
18358 (use (match_dup 2))
18359 (use (match_dup 3))
18360 (clobber (match_dup 5))])]
18363 (define_insn "fist<mode>2_ceil"
18364 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
18365 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
18367 (use (match_operand:HI 2 "memory_operand" "m"))
18368 (use (match_operand:HI 3 "memory_operand" "m"))]
18369 "TARGET_USE_FANCY_MATH_387
18370 && flag_unsafe_math_optimizations"
18371 "* return output_fix_trunc (insn, operands, 0);"
18372 [(set_attr "type" "fistp")
18373 (set_attr "i387_cw" "ceil")
18374 (set_attr "mode" "<MODE>")])
18376 (define_insn "fist<mode>2_ceil_with_temp"
18377 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
18378 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
18380 (use (match_operand:HI 2 "memory_operand" "m,m"))
18381 (use (match_operand:HI 3 "memory_operand" "m,m"))
18382 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
18383 "TARGET_USE_FANCY_MATH_387
18384 && flag_unsafe_math_optimizations"
18386 [(set_attr "type" "fistp")
18387 (set_attr "i387_cw" "ceil")
18388 (set_attr "mode" "<MODE>")])
18391 [(set (match_operand:X87MODEI12 0 "register_operand" "")
18392 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
18394 (use (match_operand:HI 2 "memory_operand" ""))
18395 (use (match_operand:HI 3 "memory_operand" ""))
18396 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
18398 [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
18400 (use (match_dup 2))
18401 (use (match_dup 3))])
18402 (set (match_dup 0) (match_dup 4))]
18406 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
18407 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
18409 (use (match_operand:HI 2 "memory_operand" ""))
18410 (use (match_operand:HI 3 "memory_operand" ""))
18411 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
18413 [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
18415 (use (match_dup 2))
18416 (use (match_dup 3))])]
18419 (define_expand "lceilxf<mode>2"
18420 [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
18421 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
18423 (clobber (reg:CC FLAGS_REG))])]
18424 "TARGET_USE_FANCY_MATH_387
18425 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
18426 && flag_unsafe_math_optimizations"
18429 (define_expand "lceil<mode>di2"
18430 [(match_operand:DI 0 "nonimmediate_operand" "")
18431 (match_operand:MODEF 1 "register_operand" "")]
18432 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH && TARGET_64BIT
18433 && !flag_trapping_math"
18435 ix86_expand_lfloorceil (operand0, operand1, false);
18439 (define_expand "lceil<mode>si2"
18440 [(match_operand:SI 0 "nonimmediate_operand" "")
18441 (match_operand:MODEF 1 "register_operand" "")]
18442 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18443 && !flag_trapping_math"
18445 ix86_expand_lfloorceil (operand0, operand1, false);
18449 ;; Rounding mode control word calculation could clobber FLAGS_REG.
18450 (define_insn_and_split "frndintxf2_trunc"
18451 [(set (match_operand:XF 0 "register_operand" "")
18452 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
18453 UNSPEC_FRNDINT_TRUNC))
18454 (clobber (reg:CC FLAGS_REG))]
18455 "TARGET_USE_FANCY_MATH_387
18456 && flag_unsafe_math_optimizations
18457 && !(reload_completed || reload_in_progress)"
18462 ix86_optimize_mode_switching[I387_TRUNC] = 1;
18464 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
18465 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
18467 emit_insn (gen_frndintxf2_trunc_i387 (operands[0], operands[1],
18468 operands[2], operands[3]));
18471 [(set_attr "type" "frndint")
18472 (set_attr "i387_cw" "trunc")
18473 (set_attr "mode" "XF")])
18475 (define_insn "frndintxf2_trunc_i387"
18476 [(set (match_operand:XF 0 "register_operand" "=f")
18477 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
18478 UNSPEC_FRNDINT_TRUNC))
18479 (use (match_operand:HI 2 "memory_operand" "m"))
18480 (use (match_operand:HI 3 "memory_operand" "m"))]
18481 "TARGET_USE_FANCY_MATH_387
18482 && flag_unsafe_math_optimizations"
18483 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
18484 [(set_attr "type" "frndint")
18485 (set_attr "i387_cw" "trunc")
18486 (set_attr "mode" "XF")])
18488 (define_expand "btruncxf2"
18489 [(use (match_operand:XF 0 "register_operand" ""))
18490 (use (match_operand:XF 1 "register_operand" ""))]
18491 "TARGET_USE_FANCY_MATH_387
18492 && flag_unsafe_math_optimizations && !optimize_size"
18494 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
18498 (define_expand "btrunc<mode>2"
18499 [(use (match_operand:MODEF 0 "register_operand" ""))
18500 (use (match_operand:MODEF 1 "register_operand" ""))]
18501 "(TARGET_USE_FANCY_MATH_387
18502 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
18503 || TARGET_MIX_SSE_I387)
18504 && flag_unsafe_math_optimizations && !optimize_size)
18505 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18506 && !flag_trapping_math
18507 && (TARGET_ROUND || !optimize_size))"
18509 if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
18510 && !flag_trapping_math
18511 && (TARGET_ROUND || !optimize_size))
18514 emit_insn (gen_sse4_1_round<mode>2
18515 (operands[0], operands[1], GEN_INT (0x03)));
18516 else if (TARGET_64BIT || (<MODE>mode != DFmode))
18517 ix86_expand_trunc (operand0, operand1);
18519 ix86_expand_truncdf_32 (operand0, operand1);
18523 rtx op0 = gen_reg_rtx (XFmode);
18524 rtx op1 = gen_reg_rtx (XFmode);
18526 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
18527 emit_insn (gen_frndintxf2_trunc (op0, op1));
18529 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
18534 ;; Rounding mode control word calculation could clobber FLAGS_REG.
18535 (define_insn_and_split "frndintxf2_mask_pm"
18536 [(set (match_operand:XF 0 "register_operand" "")
18537 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
18538 UNSPEC_FRNDINT_MASK_PM))
18539 (clobber (reg:CC FLAGS_REG))]
18540 "TARGET_USE_FANCY_MATH_387
18541 && flag_unsafe_math_optimizations
18542 && !(reload_completed || reload_in_progress)"
18547 ix86_optimize_mode_switching[I387_MASK_PM] = 1;
18549 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
18550 operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
18552 emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
18553 operands[2], operands[3]));
18556 [(set_attr "type" "frndint")
18557 (set_attr "i387_cw" "mask_pm")
18558 (set_attr "mode" "XF")])
18560 (define_insn "frndintxf2_mask_pm_i387"
18561 [(set (match_operand:XF 0 "register_operand" "=f")
18562 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
18563 UNSPEC_FRNDINT_MASK_PM))
18564 (use (match_operand:HI 2 "memory_operand" "m"))
18565 (use (match_operand:HI 3 "memory_operand" "m"))]
18566 "TARGET_USE_FANCY_MATH_387
18567 && flag_unsafe_math_optimizations"
18568 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
18569 [(set_attr "type" "frndint")
18570 (set_attr "i387_cw" "mask_pm")
18571 (set_attr "mode" "XF")])
18573 (define_expand "nearbyintxf2"
18574 [(use (match_operand:XF 0 "register_operand" ""))
18575 (use (match_operand:XF 1 "register_operand" ""))]
18576 "TARGET_USE_FANCY_MATH_387
18577 && flag_unsafe_math_optimizations"
18579 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
18584 (define_expand "nearbyint<mode>2"
18585 [(use (match_operand:MODEF 0 "register_operand" ""))
18586 (use (match_operand:MODEF 1 "register_operand" ""))]
18587 "TARGET_USE_FANCY_MATH_387
18588 && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
18589 || TARGET_MIX_SSE_I387)
18590 && flag_unsafe_math_optimizations"
18592 rtx op0 = gen_reg_rtx (XFmode);
18593 rtx op1 = gen_reg_rtx (XFmode);
18595 emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
18596 emit_insn (gen_frndintxf2_mask_pm (op0, op1));
18598 emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
18602 (define_insn "fxam<mode>2_i387"
18603 [(set (match_operand:HI 0 "register_operand" "=a")
18605 [(match_operand:X87MODEF 1 "register_operand" "f")]
18607 "TARGET_USE_FANCY_MATH_387"
18608 "fxam\n\tfnstsw\t%0"
18609 [(set_attr "type" "multi")
18610 (set_attr "unit" "i387")
18611 (set_attr "mode" "<MODE>")])
18613 (define_expand "isinf<mode>2"
18614 [(use (match_operand:SI 0 "register_operand" ""))
18615 (use (match_operand:X87MODEF 1 "register_operand" ""))]
18616 "TARGET_USE_FANCY_MATH_387
18617 && TARGET_C99_FUNCTIONS
18618 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
18620 rtx mask = GEN_INT (0x45);
18621 rtx val = GEN_INT (0x05);
18625 rtx scratch = gen_reg_rtx (HImode);
18626 rtx res = gen_reg_rtx (QImode);
18628 emit_insn (gen_fxam<mode>2_i387 (scratch, operands[1]));
18629 emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
18630 emit_insn (gen_cmpqi_ext_3 (scratch, val));
18631 cond = gen_rtx_fmt_ee (EQ, QImode,
18632 gen_rtx_REG (CCmode, FLAGS_REG),
18634 emit_insn (gen_rtx_SET (VOIDmode, res, cond));
18635 emit_insn (gen_zero_extendqisi2 (operands[0], res));
18639 (define_expand "signbit<mode>2"
18640 [(use (match_operand:SI 0 "register_operand" ""))
18641 (use (match_operand:X87MODEF 1 "register_operand" ""))]
18642 "TARGET_USE_FANCY_MATH_387
18643 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
18645 rtx mask = GEN_INT (0x0200);
18647 rtx scratch = gen_reg_rtx (HImode);
18649 emit_insn (gen_fxam<mode>2_i387 (scratch, operands[1]));
18650 emit_insn (gen_andsi3 (operands[0], gen_lowpart (SImode, scratch), mask));
18654 ;; Block operation instructions
18656 (define_expand "movmemsi"
18657 [(use (match_operand:BLK 0 "memory_operand" ""))
18658 (use (match_operand:BLK 1 "memory_operand" ""))
18659 (use (match_operand:SI 2 "nonmemory_operand" ""))
18660 (use (match_operand:SI 3 "const_int_operand" ""))
18661 (use (match_operand:SI 4 "const_int_operand" ""))
18662 (use (match_operand:SI 5 "const_int_operand" ""))]
18665 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3],
18666 operands[4], operands[5]))
18672 (define_expand "movmemdi"
18673 [(use (match_operand:BLK 0 "memory_operand" ""))
18674 (use (match_operand:BLK 1 "memory_operand" ""))
18675 (use (match_operand:DI 2 "nonmemory_operand" ""))
18676 (use (match_operand:DI 3 "const_int_operand" ""))
18677 (use (match_operand:SI 4 "const_int_operand" ""))
18678 (use (match_operand:SI 5 "const_int_operand" ""))]
18681 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3],
18682 operands[4], operands[5]))
18688 ;; Most CPUs don't like single string operations
18689 ;; Handle this case here to simplify previous expander.
18691 (define_expand "strmov"
18692 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
18693 (set (match_operand 1 "memory_operand" "") (match_dup 4))
18694 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
18695 (clobber (reg:CC FLAGS_REG))])
18696 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
18697 (clobber (reg:CC FLAGS_REG))])]
18700 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
18702 /* If .md ever supports :P for Pmode, these can be directly
18703 in the pattern above. */
18704 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
18705 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
18707 /* Can't use this if the user has appropriated esi or edi. */
18708 if ((TARGET_SINGLE_STRINGOP || optimize_size)
18709 && !(global_regs[SI_REG] || global_regs[DI_REG]))
18711 emit_insn (gen_strmov_singleop (operands[0], operands[1],
18712 operands[2], operands[3],
18713 operands[5], operands[6]));
18717 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
18720 (define_expand "strmov_singleop"
18721 [(parallel [(set (match_operand 1 "memory_operand" "")
18722 (match_operand 3 "memory_operand" ""))
18723 (set (match_operand 0 "register_operand" "")
18724 (match_operand 4 "" ""))
18725 (set (match_operand 2 "register_operand" "")
18726 (match_operand 5 "" ""))])]
18727 "TARGET_SINGLE_STRINGOP || optimize_size"
18730 (define_insn "*strmovdi_rex_1"
18731 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
18732 (mem:DI (match_operand:DI 3 "register_operand" "1")))
18733 (set (match_operand:DI 0 "register_operand" "=D")
18734 (plus:DI (match_dup 2)
18736 (set (match_operand:DI 1 "register_operand" "=S")
18737 (plus:DI (match_dup 3)
18739 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18741 [(set_attr "type" "str")
18742 (set_attr "mode" "DI")
18743 (set_attr "memory" "both")])
18745 (define_insn "*strmovsi_1"
18746 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
18747 (mem:SI (match_operand:SI 3 "register_operand" "1")))
18748 (set (match_operand:SI 0 "register_operand" "=D")
18749 (plus:SI (match_dup 2)
18751 (set (match_operand:SI 1 "register_operand" "=S")
18752 (plus:SI (match_dup 3)
18754 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18756 [(set_attr "type" "str")
18757 (set_attr "mode" "SI")
18758 (set_attr "memory" "both")])
18760 (define_insn "*strmovsi_rex_1"
18761 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
18762 (mem:SI (match_operand:DI 3 "register_operand" "1")))
18763 (set (match_operand:DI 0 "register_operand" "=D")
18764 (plus:DI (match_dup 2)
18766 (set (match_operand:DI 1 "register_operand" "=S")
18767 (plus:DI (match_dup 3)
18769 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18771 [(set_attr "type" "str")
18772 (set_attr "mode" "SI")
18773 (set_attr "memory" "both")])
18775 (define_insn "*strmovhi_1"
18776 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
18777 (mem:HI (match_operand:SI 3 "register_operand" "1")))
18778 (set (match_operand:SI 0 "register_operand" "=D")
18779 (plus:SI (match_dup 2)
18781 (set (match_operand:SI 1 "register_operand" "=S")
18782 (plus:SI (match_dup 3)
18784 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18786 [(set_attr "type" "str")
18787 (set_attr "memory" "both")
18788 (set_attr "mode" "HI")])
18790 (define_insn "*strmovhi_rex_1"
18791 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
18792 (mem:HI (match_operand:DI 3 "register_operand" "1")))
18793 (set (match_operand:DI 0 "register_operand" "=D")
18794 (plus:DI (match_dup 2)
18796 (set (match_operand:DI 1 "register_operand" "=S")
18797 (plus:DI (match_dup 3)
18799 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18801 [(set_attr "type" "str")
18802 (set_attr "memory" "both")
18803 (set_attr "mode" "HI")])
18805 (define_insn "*strmovqi_1"
18806 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
18807 (mem:QI (match_operand:SI 3 "register_operand" "1")))
18808 (set (match_operand:SI 0 "register_operand" "=D")
18809 (plus:SI (match_dup 2)
18811 (set (match_operand:SI 1 "register_operand" "=S")
18812 (plus:SI (match_dup 3)
18814 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18816 [(set_attr "type" "str")
18817 (set_attr "memory" "both")
18818 (set_attr "mode" "QI")])
18820 (define_insn "*strmovqi_rex_1"
18821 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
18822 (mem:QI (match_operand:DI 3 "register_operand" "1")))
18823 (set (match_operand:DI 0 "register_operand" "=D")
18824 (plus:DI (match_dup 2)
18826 (set (match_operand:DI 1 "register_operand" "=S")
18827 (plus:DI (match_dup 3)
18829 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
18831 [(set_attr "type" "str")
18832 (set_attr "memory" "both")
18833 (set_attr "mode" "QI")])
18835 (define_expand "rep_mov"
18836 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
18837 (set (match_operand 0 "register_operand" "")
18838 (match_operand 5 "" ""))
18839 (set (match_operand 2 "register_operand" "")
18840 (match_operand 6 "" ""))
18841 (set (match_operand 1 "memory_operand" "")
18842 (match_operand 3 "memory_operand" ""))
18843 (use (match_dup 4))])]
18847 (define_insn "*rep_movdi_rex64"
18848 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
18849 (set (match_operand:DI 0 "register_operand" "=D")
18850 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
18852 (match_operand:DI 3 "register_operand" "0")))
18853 (set (match_operand:DI 1 "register_operand" "=S")
18854 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
18855 (match_operand:DI 4 "register_operand" "1")))
18856 (set (mem:BLK (match_dup 3))
18857 (mem:BLK (match_dup 4)))
18858 (use (match_dup 5))]
18861 [(set_attr "type" "str")
18862 (set_attr "prefix_rep" "1")
18863 (set_attr "memory" "both")
18864 (set_attr "mode" "DI")])
18866 (define_insn "*rep_movsi"
18867 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
18868 (set (match_operand:SI 0 "register_operand" "=D")
18869 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
18871 (match_operand:SI 3 "register_operand" "0")))
18872 (set (match_operand:SI 1 "register_operand" "=S")
18873 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
18874 (match_operand:SI 4 "register_operand" "1")))
18875 (set (mem:BLK (match_dup 3))
18876 (mem:BLK (match_dup 4)))
18877 (use (match_dup 5))]
18880 [(set_attr "type" "str")
18881 (set_attr "prefix_rep" "1")
18882 (set_attr "memory" "both")
18883 (set_attr "mode" "SI")])
18885 (define_insn "*rep_movsi_rex64"
18886 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
18887 (set (match_operand:DI 0 "register_operand" "=D")
18888 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
18890 (match_operand:DI 3 "register_operand" "0")))
18891 (set (match_operand:DI 1 "register_operand" "=S")
18892 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
18893 (match_operand:DI 4 "register_operand" "1")))
18894 (set (mem:BLK (match_dup 3))
18895 (mem:BLK (match_dup 4)))
18896 (use (match_dup 5))]
18899 [(set_attr "type" "str")
18900 (set_attr "prefix_rep" "1")
18901 (set_attr "memory" "both")
18902 (set_attr "mode" "SI")])
18904 (define_insn "*rep_movqi"
18905 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
18906 (set (match_operand:SI 0 "register_operand" "=D")
18907 (plus:SI (match_operand:SI 3 "register_operand" "0")
18908 (match_operand:SI 5 "register_operand" "2")))
18909 (set (match_operand:SI 1 "register_operand" "=S")
18910 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
18911 (set (mem:BLK (match_dup 3))
18912 (mem:BLK (match_dup 4)))
18913 (use (match_dup 5))]
18916 [(set_attr "type" "str")
18917 (set_attr "prefix_rep" "1")
18918 (set_attr "memory" "both")
18919 (set_attr "mode" "SI")])
18921 (define_insn "*rep_movqi_rex64"
18922 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
18923 (set (match_operand:DI 0 "register_operand" "=D")
18924 (plus:DI (match_operand:DI 3 "register_operand" "0")
18925 (match_operand:DI 5 "register_operand" "2")))
18926 (set (match_operand:DI 1 "register_operand" "=S")
18927 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
18928 (set (mem:BLK (match_dup 3))
18929 (mem:BLK (match_dup 4)))
18930 (use (match_dup 5))]
18933 [(set_attr "type" "str")
18934 (set_attr "prefix_rep" "1")
18935 (set_attr "memory" "both")
18936 (set_attr "mode" "SI")])
18938 (define_expand "setmemsi"
18939 [(use (match_operand:BLK 0 "memory_operand" ""))
18940 (use (match_operand:SI 1 "nonmemory_operand" ""))
18941 (use (match_operand 2 "const_int_operand" ""))
18942 (use (match_operand 3 "const_int_operand" ""))
18943 (use (match_operand:SI 4 "const_int_operand" ""))
18944 (use (match_operand:SI 5 "const_int_operand" ""))]
18947 if (ix86_expand_setmem (operands[0], operands[1],
18948 operands[2], operands[3],
18949 operands[4], operands[5]))
18955 (define_expand "setmemdi"
18956 [(use (match_operand:BLK 0 "memory_operand" ""))
18957 (use (match_operand:DI 1 "nonmemory_operand" ""))
18958 (use (match_operand 2 "const_int_operand" ""))
18959 (use (match_operand 3 "const_int_operand" ""))
18960 (use (match_operand 4 "const_int_operand" ""))
18961 (use (match_operand 5 "const_int_operand" ""))]
18964 if (ix86_expand_setmem (operands[0], operands[1],
18965 operands[2], operands[3],
18966 operands[4], operands[5]))
18972 ;; Most CPUs don't like single string operations
18973 ;; Handle this case here to simplify previous expander.
18975 (define_expand "strset"
18976 [(set (match_operand 1 "memory_operand" "")
18977 (match_operand 2 "register_operand" ""))
18978 (parallel [(set (match_operand 0 "register_operand" "")
18980 (clobber (reg:CC FLAGS_REG))])]
18983 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
18984 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
18986 /* If .md ever supports :P for Pmode, this can be directly
18987 in the pattern above. */
18988 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
18989 GEN_INT (GET_MODE_SIZE (GET_MODE
18991 if (TARGET_SINGLE_STRINGOP || optimize_size)
18993 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
18999 (define_expand "strset_singleop"
19000 [(parallel [(set (match_operand 1 "memory_operand" "")
19001 (match_operand 2 "register_operand" ""))
19002 (set (match_operand 0 "register_operand" "")
19003 (match_operand 3 "" ""))])]
19004 "TARGET_SINGLE_STRINGOP || optimize_size"
19007 (define_insn "*strsetdi_rex_1"
19008 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
19009 (match_operand:DI 2 "register_operand" "a"))
19010 (set (match_operand:DI 0 "register_operand" "=D")
19011 (plus:DI (match_dup 1)
19013 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19015 [(set_attr "type" "str")
19016 (set_attr "memory" "store")
19017 (set_attr "mode" "DI")])
19019 (define_insn "*strsetsi_1"
19020 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
19021 (match_operand:SI 2 "register_operand" "a"))
19022 (set (match_operand:SI 0 "register_operand" "=D")
19023 (plus:SI (match_dup 1)
19025 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19027 [(set_attr "type" "str")
19028 (set_attr "memory" "store")
19029 (set_attr "mode" "SI")])
19031 (define_insn "*strsetsi_rex_1"
19032 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
19033 (match_operand:SI 2 "register_operand" "a"))
19034 (set (match_operand:DI 0 "register_operand" "=D")
19035 (plus:DI (match_dup 1)
19037 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19039 [(set_attr "type" "str")
19040 (set_attr "memory" "store")
19041 (set_attr "mode" "SI")])
19043 (define_insn "*strsethi_1"
19044 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
19045 (match_operand:HI 2 "register_operand" "a"))
19046 (set (match_operand:SI 0 "register_operand" "=D")
19047 (plus:SI (match_dup 1)
19049 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19051 [(set_attr "type" "str")
19052 (set_attr "memory" "store")
19053 (set_attr "mode" "HI")])
19055 (define_insn "*strsethi_rex_1"
19056 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
19057 (match_operand:HI 2 "register_operand" "a"))
19058 (set (match_operand:DI 0 "register_operand" "=D")
19059 (plus:DI (match_dup 1)
19061 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19063 [(set_attr "type" "str")
19064 (set_attr "memory" "store")
19065 (set_attr "mode" "HI")])
19067 (define_insn "*strsetqi_1"
19068 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
19069 (match_operand:QI 2 "register_operand" "a"))
19070 (set (match_operand:SI 0 "register_operand" "=D")
19071 (plus:SI (match_dup 1)
19073 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19075 [(set_attr "type" "str")
19076 (set_attr "memory" "store")
19077 (set_attr "mode" "QI")])
19079 (define_insn "*strsetqi_rex_1"
19080 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
19081 (match_operand:QI 2 "register_operand" "a"))
19082 (set (match_operand:DI 0 "register_operand" "=D")
19083 (plus:DI (match_dup 1)
19085 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
19087 [(set_attr "type" "str")
19088 (set_attr "memory" "store")
19089 (set_attr "mode" "QI")])
19091 (define_expand "rep_stos"
19092 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
19093 (set (match_operand 0 "register_operand" "")
19094 (match_operand 4 "" ""))
19095 (set (match_operand 2 "memory_operand" "") (const_int 0))
19096 (use (match_operand 3 "register_operand" ""))
19097 (use (match_dup 1))])]
19101 (define_insn "*rep_stosdi_rex64"
19102 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
19103 (set (match_operand:DI 0 "register_operand" "=D")
19104 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
19106 (match_operand:DI 3 "register_operand" "0")))
19107 (set (mem:BLK (match_dup 3))
19109 (use (match_operand:DI 2 "register_operand" "a"))
19110 (use (match_dup 4))]
19113 [(set_attr "type" "str")
19114 (set_attr "prefix_rep" "1")
19115 (set_attr "memory" "store")
19116 (set_attr "mode" "DI")])
19118 (define_insn "*rep_stossi"
19119 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
19120 (set (match_operand:SI 0 "register_operand" "=D")
19121 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
19123 (match_operand:SI 3 "register_operand" "0")))
19124 (set (mem:BLK (match_dup 3))
19126 (use (match_operand:SI 2 "register_operand" "a"))
19127 (use (match_dup 4))]
19130 [(set_attr "type" "str")
19131 (set_attr "prefix_rep" "1")
19132 (set_attr "memory" "store")
19133 (set_attr "mode" "SI")])
19135 (define_insn "*rep_stossi_rex64"
19136 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
19137 (set (match_operand:DI 0 "register_operand" "=D")
19138 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
19140 (match_operand:DI 3 "register_operand" "0")))
19141 (set (mem:BLK (match_dup 3))
19143 (use (match_operand:SI 2 "register_operand" "a"))
19144 (use (match_dup 4))]
19147 [(set_attr "type" "str")
19148 (set_attr "prefix_rep" "1")
19149 (set_attr "memory" "store")
19150 (set_attr "mode" "SI")])
19152 (define_insn "*rep_stosqi"
19153 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
19154 (set (match_operand:SI 0 "register_operand" "=D")
19155 (plus:SI (match_operand:SI 3 "register_operand" "0")
19156 (match_operand:SI 4 "register_operand" "1")))
19157 (set (mem:BLK (match_dup 3))
19159 (use (match_operand:QI 2 "register_operand" "a"))
19160 (use (match_dup 4))]
19163 [(set_attr "type" "str")
19164 (set_attr "prefix_rep" "1")
19165 (set_attr "memory" "store")
19166 (set_attr "mode" "QI")])
19168 (define_insn "*rep_stosqi_rex64"
19169 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
19170 (set (match_operand:DI 0 "register_operand" "=D")
19171 (plus:DI (match_operand:DI 3 "register_operand" "0")
19172 (match_operand:DI 4 "register_operand" "1")))
19173 (set (mem:BLK (match_dup 3))
19175 (use (match_operand:QI 2 "register_operand" "a"))
19176 (use (match_dup 4))]
19179 [(set_attr "type" "str")
19180 (set_attr "prefix_rep" "1")
19181 (set_attr "memory" "store")
19182 (set_attr "mode" "QI")])
19184 (define_expand "cmpstrnsi"
19185 [(set (match_operand:SI 0 "register_operand" "")
19186 (compare:SI (match_operand:BLK 1 "general_operand" "")
19187 (match_operand:BLK 2 "general_operand" "")))
19188 (use (match_operand 3 "general_operand" ""))
19189 (use (match_operand 4 "immediate_operand" ""))]
19190 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
19192 rtx addr1, addr2, out, outlow, count, countreg, align;
19194 /* Can't use this if the user has appropriated esi or edi. */
19195 if (global_regs[SI_REG] || global_regs[DI_REG])
19200 out = gen_reg_rtx (SImode);
19202 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
19203 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
19204 if (addr1 != XEXP (operands[1], 0))
19205 operands[1] = replace_equiv_address_nv (operands[1], addr1);
19206 if (addr2 != XEXP (operands[2], 0))
19207 operands[2] = replace_equiv_address_nv (operands[2], addr2);
19209 count = operands[3];
19210 countreg = ix86_zero_extend_to_Pmode (count);
19212 /* %%% Iff we are testing strict equality, we can use known alignment
19213 to good advantage. This may be possible with combine, particularly
19214 once cc0 is dead. */
19215 align = operands[4];
19217 if (CONST_INT_P (count))
19219 if (INTVAL (count) == 0)
19221 emit_move_insn (operands[0], const0_rtx);
19224 emit_insn (gen_cmpstrnqi_nz_1 (addr1, addr2, countreg, align,
19225 operands[1], operands[2]));
19230 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
19232 emit_insn (gen_cmpsi_1 (countreg, countreg));
19233 emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align,
19234 operands[1], operands[2]));
19237 outlow = gen_lowpart (QImode, out);
19238 emit_insn (gen_cmpintqi (outlow));
19239 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
19241 if (operands[0] != out)
19242 emit_move_insn (operands[0], out);
19247 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
19249 (define_expand "cmpintqi"
19250 [(set (match_dup 1)
19251 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
19253 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
19254 (parallel [(set (match_operand:QI 0 "register_operand" "")
19255 (minus:QI (match_dup 1)
19257 (clobber (reg:CC FLAGS_REG))])]
19259 "operands[1] = gen_reg_rtx (QImode);
19260 operands[2] = gen_reg_rtx (QImode);")
19262 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
19263 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
19265 (define_expand "cmpstrnqi_nz_1"
19266 [(parallel [(set (reg:CC FLAGS_REG)
19267 (compare:CC (match_operand 4 "memory_operand" "")
19268 (match_operand 5 "memory_operand" "")))
19269 (use (match_operand 2 "register_operand" ""))
19270 (use (match_operand:SI 3 "immediate_operand" ""))
19271 (clobber (match_operand 0 "register_operand" ""))
19272 (clobber (match_operand 1 "register_operand" ""))
19273 (clobber (match_dup 2))])]
19277 (define_insn "*cmpstrnqi_nz_1"
19278 [(set (reg:CC FLAGS_REG)
19279 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
19280 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
19281 (use (match_operand:SI 6 "register_operand" "2"))
19282 (use (match_operand:SI 3 "immediate_operand" "i"))
19283 (clobber (match_operand:SI 0 "register_operand" "=S"))
19284 (clobber (match_operand:SI 1 "register_operand" "=D"))
19285 (clobber (match_operand:SI 2 "register_operand" "=c"))]
19288 [(set_attr "type" "str")
19289 (set_attr "mode" "QI")
19290 (set_attr "prefix_rep" "1")])
19292 (define_insn "*cmpstrnqi_nz_rex_1"
19293 [(set (reg:CC FLAGS_REG)
19294 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
19295 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
19296 (use (match_operand:DI 6 "register_operand" "2"))
19297 (use (match_operand:SI 3 "immediate_operand" "i"))
19298 (clobber (match_operand:DI 0 "register_operand" "=S"))
19299 (clobber (match_operand:DI 1 "register_operand" "=D"))
19300 (clobber (match_operand:DI 2 "register_operand" "=c"))]
19303 [(set_attr "type" "str")
19304 (set_attr "mode" "QI")
19305 (set_attr "prefix_rep" "1")])
19307 ;; The same, but the count is not known to not be zero.
19309 (define_expand "cmpstrnqi_1"
19310 [(parallel [(set (reg:CC FLAGS_REG)
19311 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
19313 (compare:CC (match_operand 4 "memory_operand" "")
19314 (match_operand 5 "memory_operand" ""))
19316 (use (match_operand:SI 3 "immediate_operand" ""))
19317 (use (reg:CC FLAGS_REG))
19318 (clobber (match_operand 0 "register_operand" ""))
19319 (clobber (match_operand 1 "register_operand" ""))
19320 (clobber (match_dup 2))])]
19324 (define_insn "*cmpstrnqi_1"
19325 [(set (reg:CC FLAGS_REG)
19326 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
19328 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
19329 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
19331 (use (match_operand:SI 3 "immediate_operand" "i"))
19332 (use (reg:CC FLAGS_REG))
19333 (clobber (match_operand:SI 0 "register_operand" "=S"))
19334 (clobber (match_operand:SI 1 "register_operand" "=D"))
19335 (clobber (match_operand:SI 2 "register_operand" "=c"))]
19338 [(set_attr "type" "str")
19339 (set_attr "mode" "QI")
19340 (set_attr "prefix_rep" "1")])
19342 (define_insn "*cmpstrnqi_rex_1"
19343 [(set (reg:CC FLAGS_REG)
19344 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
19346 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
19347 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
19349 (use (match_operand:SI 3 "immediate_operand" "i"))
19350 (use (reg:CC FLAGS_REG))
19351 (clobber (match_operand:DI 0 "register_operand" "=S"))
19352 (clobber (match_operand:DI 1 "register_operand" "=D"))
19353 (clobber (match_operand:DI 2 "register_operand" "=c"))]
19356 [(set_attr "type" "str")
19357 (set_attr "mode" "QI")
19358 (set_attr "prefix_rep" "1")])
19360 (define_expand "strlensi"
19361 [(set (match_operand:SI 0 "register_operand" "")
19362 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
19363 (match_operand:QI 2 "immediate_operand" "")
19364 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
19367 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
19373 (define_expand "strlendi"
19374 [(set (match_operand:DI 0 "register_operand" "")
19375 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
19376 (match_operand:QI 2 "immediate_operand" "")
19377 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
19380 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
19386 (define_expand "strlenqi_1"
19387 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
19388 (clobber (match_operand 1 "register_operand" ""))
19389 (clobber (reg:CC FLAGS_REG))])]
19393 (define_insn "*strlenqi_1"
19394 [(set (match_operand:SI 0 "register_operand" "=&c")
19395 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
19396 (match_operand:QI 2 "register_operand" "a")
19397 (match_operand:SI 3 "immediate_operand" "i")
19398 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
19399 (clobber (match_operand:SI 1 "register_operand" "=D"))
19400 (clobber (reg:CC FLAGS_REG))]
19403 [(set_attr "type" "str")
19404 (set_attr "mode" "QI")
19405 (set_attr "prefix_rep" "1")])
19407 (define_insn "*strlenqi_rex_1"
19408 [(set (match_operand:DI 0 "register_operand" "=&c")
19409 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
19410 (match_operand:QI 2 "register_operand" "a")
19411 (match_operand:DI 3 "immediate_operand" "i")
19412 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
19413 (clobber (match_operand:DI 1 "register_operand" "=D"))
19414 (clobber (reg:CC FLAGS_REG))]
19417 [(set_attr "type" "str")
19418 (set_attr "mode" "QI")
19419 (set_attr "prefix_rep" "1")])
19421 ;; Peephole optimizations to clean up after cmpstrn*. This should be
19422 ;; handled in combine, but it is not currently up to the task.
19423 ;; When used for their truth value, the cmpstrn* expanders generate
19432 ;; The intermediate three instructions are unnecessary.
19434 ;; This one handles cmpstrn*_nz_1...
19437 (set (reg:CC FLAGS_REG)
19438 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
19439 (mem:BLK (match_operand 5 "register_operand" ""))))
19440 (use (match_operand 6 "register_operand" ""))
19441 (use (match_operand:SI 3 "immediate_operand" ""))
19442 (clobber (match_operand 0 "register_operand" ""))
19443 (clobber (match_operand 1 "register_operand" ""))
19444 (clobber (match_operand 2 "register_operand" ""))])
19445 (set (match_operand:QI 7 "register_operand" "")
19446 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
19447 (set (match_operand:QI 8 "register_operand" "")
19448 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
19449 (set (reg FLAGS_REG)
19450 (compare (match_dup 7) (match_dup 8)))
19452 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
19454 (set (reg:CC FLAGS_REG)
19455 (compare:CC (mem:BLK (match_dup 4))
19456 (mem:BLK (match_dup 5))))
19457 (use (match_dup 6))
19458 (use (match_dup 3))
19459 (clobber (match_dup 0))
19460 (clobber (match_dup 1))
19461 (clobber (match_dup 2))])]
19464 ;; ...and this one handles cmpstrn*_1.
19467 (set (reg:CC FLAGS_REG)
19468 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
19470 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
19471 (mem:BLK (match_operand 5 "register_operand" "")))
19473 (use (match_operand:SI 3 "immediate_operand" ""))
19474 (use (reg:CC FLAGS_REG))
19475 (clobber (match_operand 0 "register_operand" ""))
19476 (clobber (match_operand 1 "register_operand" ""))
19477 (clobber (match_operand 2 "register_operand" ""))])
19478 (set (match_operand:QI 7 "register_operand" "")
19479 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
19480 (set (match_operand:QI 8 "register_operand" "")
19481 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
19482 (set (reg FLAGS_REG)
19483 (compare (match_dup 7) (match_dup 8)))
19485 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
19487 (set (reg:CC FLAGS_REG)
19488 (if_then_else:CC (ne (match_dup 6)
19490 (compare:CC (mem:BLK (match_dup 4))
19491 (mem:BLK (match_dup 5)))
19493 (use (match_dup 3))
19494 (use (reg:CC FLAGS_REG))
19495 (clobber (match_dup 0))
19496 (clobber (match_dup 1))
19497 (clobber (match_dup 2))])]
19502 ;; Conditional move instructions.
19504 (define_expand "movdicc"
19505 [(set (match_operand:DI 0 "register_operand" "")
19506 (if_then_else:DI (match_operand 1 "comparison_operator" "")
19507 (match_operand:DI 2 "general_operand" "")
19508 (match_operand:DI 3 "general_operand" "")))]
19510 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
19512 (define_insn "x86_movdicc_0_m1_rex64"
19513 [(set (match_operand:DI 0 "register_operand" "=r")
19514 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
19517 (clobber (reg:CC FLAGS_REG))]
19520 ; Since we don't have the proper number of operands for an alu insn,
19521 ; fill in all the blanks.
19522 [(set_attr "type" "alu")
19523 (set_attr "pent_pair" "pu")
19524 (set_attr "memory" "none")
19525 (set_attr "imm_disp" "false")
19526 (set_attr "mode" "DI")
19527 (set_attr "length_immediate" "0")])
19529 (define_insn "*movdicc_c_rex64"
19530 [(set (match_operand:DI 0 "register_operand" "=r,r")
19531 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
19532 [(reg FLAGS_REG) (const_int 0)])
19533 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
19534 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
19535 "TARGET_64BIT && TARGET_CMOVE
19536 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19538 cmov%O2%C1\t{%2, %0|%0, %2}
19539 cmov%O2%c1\t{%3, %0|%0, %3}"
19540 [(set_attr "type" "icmov")
19541 (set_attr "mode" "DI")])
19543 (define_expand "movsicc"
19544 [(set (match_operand:SI 0 "register_operand" "")
19545 (if_then_else:SI (match_operand 1 "comparison_operator" "")
19546 (match_operand:SI 2 "general_operand" "")
19547 (match_operand:SI 3 "general_operand" "")))]
19549 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
19551 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
19552 ;; the register first winds up with `sbbl $0,reg', which is also weird.
19553 ;; So just document what we're doing explicitly.
19555 (define_insn "x86_movsicc_0_m1"
19556 [(set (match_operand:SI 0 "register_operand" "=r")
19557 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
19560 (clobber (reg:CC FLAGS_REG))]
19563 ; Since we don't have the proper number of operands for an alu insn,
19564 ; fill in all the blanks.
19565 [(set_attr "type" "alu")
19566 (set_attr "pent_pair" "pu")
19567 (set_attr "memory" "none")
19568 (set_attr "imm_disp" "false")
19569 (set_attr "mode" "SI")
19570 (set_attr "length_immediate" "0")])
19572 (define_insn "*movsicc_noc"
19573 [(set (match_operand:SI 0 "register_operand" "=r,r")
19574 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
19575 [(reg FLAGS_REG) (const_int 0)])
19576 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
19577 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
19579 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19581 cmov%O2%C1\t{%2, %0|%0, %2}
19582 cmov%O2%c1\t{%3, %0|%0, %3}"
19583 [(set_attr "type" "icmov")
19584 (set_attr "mode" "SI")])
19586 (define_expand "movhicc"
19587 [(set (match_operand:HI 0 "register_operand" "")
19588 (if_then_else:HI (match_operand 1 "comparison_operator" "")
19589 (match_operand:HI 2 "general_operand" "")
19590 (match_operand:HI 3 "general_operand" "")))]
19591 "TARGET_HIMODE_MATH"
19592 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
19594 (define_insn "*movhicc_noc"
19595 [(set (match_operand:HI 0 "register_operand" "=r,r")
19596 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
19597 [(reg FLAGS_REG) (const_int 0)])
19598 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
19599 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
19601 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19603 cmov%O2%C1\t{%2, %0|%0, %2}
19604 cmov%O2%c1\t{%3, %0|%0, %3}"
19605 [(set_attr "type" "icmov")
19606 (set_attr "mode" "HI")])
19608 (define_expand "movqicc"
19609 [(set (match_operand:QI 0 "register_operand" "")
19610 (if_then_else:QI (match_operand 1 "comparison_operator" "")
19611 (match_operand:QI 2 "general_operand" "")
19612 (match_operand:QI 3 "general_operand" "")))]
19613 "TARGET_QIMODE_MATH"
19614 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
19616 (define_insn_and_split "*movqicc_noc"
19617 [(set (match_operand:QI 0 "register_operand" "=r,r")
19618 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
19619 [(match_operand 4 "flags_reg_operand" "")
19621 (match_operand:QI 2 "register_operand" "r,0")
19622 (match_operand:QI 3 "register_operand" "0,r")))]
19623 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
19625 "&& reload_completed"
19626 [(set (match_dup 0)
19627 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
19630 "operands[0] = gen_lowpart (SImode, operands[0]);
19631 operands[2] = gen_lowpart (SImode, operands[2]);
19632 operands[3] = gen_lowpart (SImode, operands[3]);"
19633 [(set_attr "type" "icmov")
19634 (set_attr "mode" "SI")])
19636 (define_expand "movsfcc"
19637 [(set (match_operand:SF 0 "register_operand" "")
19638 (if_then_else:SF (match_operand 1 "comparison_operator" "")
19639 (match_operand:SF 2 "register_operand" "")
19640 (match_operand:SF 3 "register_operand" "")))]
19641 "(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
19642 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
19644 (define_insn "*movsfcc_1_387"
19645 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
19646 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
19647 [(reg FLAGS_REG) (const_int 0)])
19648 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
19649 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
19650 "TARGET_80387 && TARGET_CMOVE
19651 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19653 fcmov%F1\t{%2, %0|%0, %2}
19654 fcmov%f1\t{%3, %0|%0, %3}
19655 cmov%O2%C1\t{%2, %0|%0, %2}
19656 cmov%O2%c1\t{%3, %0|%0, %3}"
19657 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
19658 (set_attr "mode" "SF,SF,SI,SI")])
19660 (define_expand "movdfcc"
19661 [(set (match_operand:DF 0 "register_operand" "")
19662 (if_then_else:DF (match_operand 1 "comparison_operator" "")
19663 (match_operand:DF 2 "register_operand" "")
19664 (match_operand:DF 3 "register_operand" "")))]
19665 "(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
19666 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
19668 (define_insn "*movdfcc_1"
19669 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
19670 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
19671 [(reg FLAGS_REG) (const_int 0)])
19672 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
19673 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
19674 "!TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
19675 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19677 fcmov%F1\t{%2, %0|%0, %2}
19678 fcmov%f1\t{%3, %0|%0, %3}
19681 [(set_attr "type" "fcmov,fcmov,multi,multi")
19682 (set_attr "mode" "DF")])
19684 (define_insn "*movdfcc_1_rex64"
19685 [(set (match_operand:DF 0 "register_operand" "=f,f,r,r")
19686 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
19687 [(reg FLAGS_REG) (const_int 0)])
19688 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
19689 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
19690 "TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
19691 && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
19693 fcmov%F1\t{%2, %0|%0, %2}
19694 fcmov%f1\t{%3, %0|%0, %3}
19695 cmov%O2%C1\t{%2, %0|%0, %2}
19696 cmov%O2%c1\t{%3, %0|%0, %3}"
19697 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
19698 (set_attr "mode" "DF")])
19701 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
19702 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
19703 [(match_operand 4 "flags_reg_operand" "")
19705 (match_operand:DF 2 "nonimmediate_operand" "")
19706 (match_operand:DF 3 "nonimmediate_operand" "")))]
19707 "!TARGET_64BIT && reload_completed"
19708 [(set (match_dup 2)
19709 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
19713 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
19716 "split_di (operands+2, 1, operands+5, operands+6);
19717 split_di (operands+3, 1, operands+7, operands+8);
19718 split_di (operands, 1, operands+2, operands+3);")
19720 (define_expand "movxfcc"
19721 [(set (match_operand:XF 0 "register_operand" "")
19722 (if_then_else:XF (match_operand 1 "comparison_operator" "")
19723 (match_operand:XF 2 "register_operand" "")
19724 (match_operand:XF 3 "register_operand" "")))]
19725 "TARGET_80387 && TARGET_CMOVE"
19726 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
19728 (define_insn "*movxfcc_1"
19729 [(set (match_operand:XF 0 "register_operand" "=f,f")
19730 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
19731 [(reg FLAGS_REG) (const_int 0)])
19732 (match_operand:XF 2 "register_operand" "f,0")
19733 (match_operand:XF 3 "register_operand" "0,f")))]
19734 "TARGET_80387 && TARGET_CMOVE"
19736 fcmov%F1\t{%2, %0|%0, %2}
19737 fcmov%f1\t{%3, %0|%0, %3}"
19738 [(set_attr "type" "fcmov")
19739 (set_attr "mode" "XF")])
19741 ;; SSE5 conditional move
19742 (define_insn "*sse5_pcmov_<mode>"
19743 [(set (match_operand:MODEF 0 "register_operand" "=x,x,x,x")
19744 (if_then_else:MODEF
19745 (match_operand:MODEF 1 "nonimmediate_operand" "xm,x,0,0")
19746 (match_operand:MODEF 2 "nonimmediate_operand" "0,0,x,xm")
19747 (match_operand:MODEF 3 "vector_move_operand" "x,xm,xm,x")))]
19748 "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1)"
19749 "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
19750 [(set_attr "type" "sse4arg")])
19752 ;; These versions of the min/max patterns are intentionally ignorant of
19753 ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
19754 ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
19755 ;; are undefined in this condition, we're certain this is correct.
19757 (define_insn "sminsf3"
19758 [(set (match_operand:SF 0 "register_operand" "=x")
19759 (smin:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
19760 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
19762 "minss\t{%2, %0|%0, %2}"
19763 [(set_attr "type" "sseadd")
19764 (set_attr "mode" "SF")])
19766 (define_insn "smaxsf3"
19767 [(set (match_operand:SF 0 "register_operand" "=x")
19768 (smax:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
19769 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
19771 "maxss\t{%2, %0|%0, %2}"
19772 [(set_attr "type" "sseadd")
19773 (set_attr "mode" "SF")])
19775 (define_insn "smindf3"
19776 [(set (match_operand:DF 0 "register_operand" "=x")
19777 (smin:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
19778 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
19779 "TARGET_SSE2 && TARGET_SSE_MATH"
19780 "minsd\t{%2, %0|%0, %2}"
19781 [(set_attr "type" "sseadd")
19782 (set_attr "mode" "DF")])
19784 (define_insn "smaxdf3"
19785 [(set (match_operand:DF 0 "register_operand" "=x")
19786 (smax:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
19787 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
19788 "TARGET_SSE2 && TARGET_SSE_MATH"
19789 "maxsd\t{%2, %0|%0, %2}"
19790 [(set_attr "type" "sseadd")
19791 (set_attr "mode" "DF")])
19793 ;; These versions of the min/max patterns implement exactly the operations
19794 ;; min = (op1 < op2 ? op1 : op2)
19795 ;; max = (!(op1 < op2) ? op1 : op2)
19796 ;; Their operands are not commutative, and thus they may be used in the
19797 ;; presence of -0.0 and NaN.
19799 (define_insn "*ieee_sminsf3"
19800 [(set (match_operand:SF 0 "register_operand" "=x")
19801 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
19802 (match_operand:SF 2 "nonimmediate_operand" "xm")]
19805 "minss\t{%2, %0|%0, %2}"
19806 [(set_attr "type" "sseadd")
19807 (set_attr "mode" "SF")])
19809 (define_insn "*ieee_smaxsf3"
19810 [(set (match_operand:SF 0 "register_operand" "=x")
19811 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
19812 (match_operand:SF 2 "nonimmediate_operand" "xm")]
19815 "maxss\t{%2, %0|%0, %2}"
19816 [(set_attr "type" "sseadd")
19817 (set_attr "mode" "SF")])
19819 (define_insn "*ieee_smindf3"
19820 [(set (match_operand:DF 0 "register_operand" "=x")
19821 (unspec:DF [(match_operand:DF 1 "register_operand" "0")
19822 (match_operand:DF 2 "nonimmediate_operand" "xm")]
19824 "TARGET_SSE2 && TARGET_SSE_MATH"
19825 "minsd\t{%2, %0|%0, %2}"
19826 [(set_attr "type" "sseadd")
19827 (set_attr "mode" "DF")])
19829 (define_insn "*ieee_smaxdf3"
19830 [(set (match_operand:DF 0 "register_operand" "=x")
19831 (unspec:DF [(match_operand:DF 1 "register_operand" "0")
19832 (match_operand:DF 2 "nonimmediate_operand" "xm")]
19834 "TARGET_SSE2 && TARGET_SSE_MATH"
19835 "maxsd\t{%2, %0|%0, %2}"
19836 [(set_attr "type" "sseadd")
19837 (set_attr "mode" "DF")])
19839 ;; Make two stack loads independent:
19841 ;; fld %st(0) -> fld bb
19842 ;; fmul bb fmul %st(1), %st
19844 ;; Actually we only match the last two instructions for simplicity.
19846 [(set (match_operand 0 "fp_register_operand" "")
19847 (match_operand 1 "fp_register_operand" ""))
19849 (match_operator 2 "binary_fp_operator"
19851 (match_operand 3 "memory_operand" "")]))]
19852 "REGNO (operands[0]) != REGNO (operands[1])"
19853 [(set (match_dup 0) (match_dup 3))
19854 (set (match_dup 0) (match_dup 4))]
19856 ;; The % modifier is not operational anymore in peephole2's, so we have to
19857 ;; swap the operands manually in the case of addition and multiplication.
19858 "if (COMMUTATIVE_ARITH_P (operands[2]))
19859 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
19860 operands[0], operands[1]);
19862 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
19863 operands[1], operands[0]);")
19865 ;; Conditional addition patterns
19866 (define_expand "addqicc"
19867 [(match_operand:QI 0 "register_operand" "")
19868 (match_operand 1 "comparison_operator" "")
19869 (match_operand:QI 2 "register_operand" "")
19870 (match_operand:QI 3 "const_int_operand" "")]
19872 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
19874 (define_expand "addhicc"
19875 [(match_operand:HI 0 "register_operand" "")
19876 (match_operand 1 "comparison_operator" "")
19877 (match_operand:HI 2 "register_operand" "")
19878 (match_operand:HI 3 "const_int_operand" "")]
19880 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
19882 (define_expand "addsicc"
19883 [(match_operand:SI 0 "register_operand" "")
19884 (match_operand 1 "comparison_operator" "")
19885 (match_operand:SI 2 "register_operand" "")
19886 (match_operand:SI 3 "const_int_operand" "")]
19888 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
19890 (define_expand "adddicc"
19891 [(match_operand:DI 0 "register_operand" "")
19892 (match_operand 1 "comparison_operator" "")
19893 (match_operand:DI 2 "register_operand" "")
19894 (match_operand:DI 3 "const_int_operand" "")]
19896 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
19899 ;; Misc patterns (?)
19901 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
19902 ;; Otherwise there will be nothing to keep
19904 ;; [(set (reg ebp) (reg esp))]
19905 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
19906 ;; (clobber (eflags)]
19907 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
19909 ;; in proper program order.
19910 (define_insn "pro_epilogue_adjust_stack_1"
19911 [(set (match_operand:SI 0 "register_operand" "=r,r")
19912 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
19913 (match_operand:SI 2 "immediate_operand" "i,i")))
19914 (clobber (reg:CC FLAGS_REG))
19915 (clobber (mem:BLK (scratch)))]
19918 switch (get_attr_type (insn))
19921 return "mov{l}\t{%1, %0|%0, %1}";
19924 if (CONST_INT_P (operands[2])
19925 && (INTVAL (operands[2]) == 128
19926 || (INTVAL (operands[2]) < 0
19927 && INTVAL (operands[2]) != -128)))
19929 operands[2] = GEN_INT (-INTVAL (operands[2]));
19930 return "sub{l}\t{%2, %0|%0, %2}";
19932 return "add{l}\t{%2, %0|%0, %2}";
19935 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
19936 return "lea{l}\t{%a2, %0|%0, %a2}";
19939 gcc_unreachable ();
19942 [(set (attr "type")
19943 (cond [(eq_attr "alternative" "0")
19944 (const_string "alu")
19945 (match_operand:SI 2 "const0_operand" "")
19946 (const_string "imov")
19948 (const_string "lea")))
19949 (set_attr "mode" "SI")])
19951 (define_insn "pro_epilogue_adjust_stack_rex64"
19952 [(set (match_operand:DI 0 "register_operand" "=r,r")
19953 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
19954 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
19955 (clobber (reg:CC FLAGS_REG))
19956 (clobber (mem:BLK (scratch)))]
19959 switch (get_attr_type (insn))
19962 return "mov{q}\t{%1, %0|%0, %1}";
19965 if (CONST_INT_P (operands[2])
19966 /* Avoid overflows. */
19967 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
19968 && (INTVAL (operands[2]) == 128
19969 || (INTVAL (operands[2]) < 0
19970 && INTVAL (operands[2]) != -128)))
19972 operands[2] = GEN_INT (-INTVAL (operands[2]));
19973 return "sub{q}\t{%2, %0|%0, %2}";
19975 return "add{q}\t{%2, %0|%0, %2}";
19978 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
19979 return "lea{q}\t{%a2, %0|%0, %a2}";
19982 gcc_unreachable ();
19985 [(set (attr "type")
19986 (cond [(eq_attr "alternative" "0")
19987 (const_string "alu")
19988 (match_operand:DI 2 "const0_operand" "")
19989 (const_string "imov")
19991 (const_string "lea")))
19992 (set_attr "mode" "DI")])
19994 (define_insn "pro_epilogue_adjust_stack_rex64_2"
19995 [(set (match_operand:DI 0 "register_operand" "=r,r")
19996 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
19997 (match_operand:DI 3 "immediate_operand" "i,i")))
19998 (use (match_operand:DI 2 "register_operand" "r,r"))
19999 (clobber (reg:CC FLAGS_REG))
20000 (clobber (mem:BLK (scratch)))]
20003 switch (get_attr_type (insn))
20006 return "add{q}\t{%2, %0|%0, %2}";
20009 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
20010 return "lea{q}\t{%a2, %0|%0, %a2}";
20013 gcc_unreachable ();
20016 [(set_attr "type" "alu,lea")
20017 (set_attr "mode" "DI")])
20019 (define_insn "allocate_stack_worker_32"
20020 [(set (match_operand:SI 0 "register_operand" "+a")
20021 (unspec_volatile:SI [(match_dup 0)] UNSPECV_STACK_PROBE))
20022 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
20023 (clobber (reg:CC FLAGS_REG))]
20024 "!TARGET_64BIT && TARGET_STACK_PROBE"
20026 [(set_attr "type" "multi")
20027 (set_attr "length" "5")])
20029 (define_insn "allocate_stack_worker_64"
20030 [(set (match_operand:DI 0 "register_operand" "=a")
20031 (unspec_volatile:DI [(match_dup 0)] UNSPECV_STACK_PROBE))
20032 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
20033 (clobber (reg:DI R10_REG))
20034 (clobber (reg:DI R11_REG))
20035 (clobber (reg:CC FLAGS_REG))]
20036 "TARGET_64BIT && TARGET_STACK_PROBE"
20038 [(set_attr "type" "multi")
20039 (set_attr "length" "5")])
20041 (define_expand "allocate_stack"
20042 [(match_operand 0 "register_operand" "")
20043 (match_operand 1 "general_operand" "")]
20044 "TARGET_STACK_PROBE"
20048 #ifndef CHECK_STACK_LIMIT
20049 #define CHECK_STACK_LIMIT 0
20052 if (CHECK_STACK_LIMIT && CONST_INT_P (operands[1])
20053 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
20055 x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, operands[1],
20056 stack_pointer_rtx, 0, OPTAB_DIRECT);
20057 if (x != stack_pointer_rtx)
20058 emit_move_insn (stack_pointer_rtx, x);
20062 x = copy_to_mode_reg (Pmode, operands[1]);
20064 x = gen_allocate_stack_worker_64 (x);
20066 x = gen_allocate_stack_worker_32 (x);
20070 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
20074 (define_expand "builtin_setjmp_receiver"
20075 [(label_ref (match_operand 0 "" ""))]
20076 "!TARGET_64BIT && flag_pic"
20081 rtx picreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
20082 rtx label_rtx = gen_label_rtx ();
20083 emit_insn (gen_set_got_labelled (pic_offset_table_rtx, label_rtx));
20084 xops[0] = xops[1] = picreg;
20085 xops[2] = gen_rtx_CONST (SImode,
20086 gen_rtx_MINUS (SImode,
20087 gen_rtx_LABEL_REF (SImode, label_rtx),
20088 gen_rtx_SYMBOL_REF (SImode, GOT_SYMBOL_NAME)));
20089 ix86_expand_binary_operator (MINUS, SImode, xops);
20092 emit_insn (gen_set_got (pic_offset_table_rtx));
20096 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
20099 [(set (match_operand 0 "register_operand" "")
20100 (match_operator 3 "promotable_binary_operator"
20101 [(match_operand 1 "register_operand" "")
20102 (match_operand 2 "aligned_operand" "")]))
20103 (clobber (reg:CC FLAGS_REG))]
20104 "! TARGET_PARTIAL_REG_STALL && reload_completed
20105 && ((GET_MODE (operands[0]) == HImode
20106 && ((!optimize_size && !TARGET_FAST_PREFIX)
20107 /* ??? next two lines just !satisfies_constraint_K (...) */
20108 || !CONST_INT_P (operands[2])
20109 || satisfies_constraint_K (operands[2])))
20110 || (GET_MODE (operands[0]) == QImode
20111 && (TARGET_PROMOTE_QImode || optimize_size)))"
20112 [(parallel [(set (match_dup 0)
20113 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
20114 (clobber (reg:CC FLAGS_REG))])]
20115 "operands[0] = gen_lowpart (SImode, operands[0]);
20116 operands[1] = gen_lowpart (SImode, operands[1]);
20117 if (GET_CODE (operands[3]) != ASHIFT)
20118 operands[2] = gen_lowpart (SImode, operands[2]);
20119 PUT_MODE (operands[3], SImode);")
20121 ; Promote the QImode tests, as i386 has encoding of the AND
20122 ; instruction with 32-bit sign-extended immediate and thus the
20123 ; instruction size is unchanged, except in the %eax case for
20124 ; which it is increased by one byte, hence the ! optimize_size.
20126 [(set (match_operand 0 "flags_reg_operand" "")
20127 (match_operator 2 "compare_operator"
20128 [(and (match_operand 3 "aligned_operand" "")
20129 (match_operand 4 "const_int_operand" ""))
20131 (set (match_operand 1 "register_operand" "")
20132 (and (match_dup 3) (match_dup 4)))]
20133 "! TARGET_PARTIAL_REG_STALL && reload_completed
20135 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
20136 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))
20137 /* Ensure that the operand will remain sign-extended immediate. */
20138 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)"
20139 [(parallel [(set (match_dup 0)
20140 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
20143 (and:SI (match_dup 3) (match_dup 4)))])]
20146 = gen_int_mode (INTVAL (operands[4])
20147 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
20148 operands[1] = gen_lowpart (SImode, operands[1]);
20149 operands[3] = gen_lowpart (SImode, operands[3]);
20152 ; Don't promote the QImode tests, as i386 doesn't have encoding of
20153 ; the TEST instruction with 32-bit sign-extended immediate and thus
20154 ; the instruction size would at least double, which is not what we
20155 ; want even with ! optimize_size.
20157 [(set (match_operand 0 "flags_reg_operand" "")
20158 (match_operator 1 "compare_operator"
20159 [(and (match_operand:HI 2 "aligned_operand" "")
20160 (match_operand:HI 3 "const_int_operand" ""))
20162 "! TARGET_PARTIAL_REG_STALL && reload_completed
20163 && ! TARGET_FAST_PREFIX
20165 /* Ensure that the operand will remain sign-extended immediate. */
20166 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)"
20167 [(set (match_dup 0)
20168 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
20172 = gen_int_mode (INTVAL (operands[3])
20173 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
20174 operands[2] = gen_lowpart (SImode, operands[2]);
20178 [(set (match_operand 0 "register_operand" "")
20179 (neg (match_operand 1 "register_operand" "")))
20180 (clobber (reg:CC FLAGS_REG))]
20181 "! TARGET_PARTIAL_REG_STALL && reload_completed
20182 && (GET_MODE (operands[0]) == HImode
20183 || (GET_MODE (operands[0]) == QImode
20184 && (TARGET_PROMOTE_QImode || optimize_size)))"
20185 [(parallel [(set (match_dup 0)
20186 (neg:SI (match_dup 1)))
20187 (clobber (reg:CC FLAGS_REG))])]
20188 "operands[0] = gen_lowpart (SImode, operands[0]);
20189 operands[1] = gen_lowpart (SImode, operands[1]);")
20192 [(set (match_operand 0 "register_operand" "")
20193 (not (match_operand 1 "register_operand" "")))]
20194 "! TARGET_PARTIAL_REG_STALL && reload_completed
20195 && (GET_MODE (operands[0]) == HImode
20196 || (GET_MODE (operands[0]) == QImode
20197 && (TARGET_PROMOTE_QImode || optimize_size)))"
20198 [(set (match_dup 0)
20199 (not:SI (match_dup 1)))]
20200 "operands[0] = gen_lowpart (SImode, operands[0]);
20201 operands[1] = gen_lowpart (SImode, operands[1]);")
20204 [(set (match_operand 0 "register_operand" "")
20205 (if_then_else (match_operator 1 "comparison_operator"
20206 [(reg FLAGS_REG) (const_int 0)])
20207 (match_operand 2 "register_operand" "")
20208 (match_operand 3 "register_operand" "")))]
20209 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
20210 && (GET_MODE (operands[0]) == HImode
20211 || (GET_MODE (operands[0]) == QImode
20212 && (TARGET_PROMOTE_QImode || optimize_size)))"
20213 [(set (match_dup 0)
20214 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
20215 "operands[0] = gen_lowpart (SImode, operands[0]);
20216 operands[2] = gen_lowpart (SImode, operands[2]);
20217 operands[3] = gen_lowpart (SImode, operands[3]);")
20220 ;; RTL Peephole optimizations, run before sched2. These primarily look to
20221 ;; transform a complex memory operation into two memory to register operations.
20223 ;; Don't push memory operands
20225 [(set (match_operand:SI 0 "push_operand" "")
20226 (match_operand:SI 1 "memory_operand" ""))
20227 (match_scratch:SI 2 "r")]
20228 "!optimize_size && !TARGET_PUSH_MEMORY
20229 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
20230 [(set (match_dup 2) (match_dup 1))
20231 (set (match_dup 0) (match_dup 2))]
20235 [(set (match_operand:DI 0 "push_operand" "")
20236 (match_operand:DI 1 "memory_operand" ""))
20237 (match_scratch:DI 2 "r")]
20238 "!optimize_size && !TARGET_PUSH_MEMORY
20239 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
20240 [(set (match_dup 2) (match_dup 1))
20241 (set (match_dup 0) (match_dup 2))]
20244 ;; We need to handle SFmode only, because DFmode and XFmode is split to
20247 [(set (match_operand:SF 0 "push_operand" "")
20248 (match_operand:SF 1 "memory_operand" ""))
20249 (match_scratch:SF 2 "r")]
20250 "!optimize_size && !TARGET_PUSH_MEMORY
20251 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
20252 [(set (match_dup 2) (match_dup 1))
20253 (set (match_dup 0) (match_dup 2))]
20257 [(set (match_operand:HI 0 "push_operand" "")
20258 (match_operand:HI 1 "memory_operand" ""))
20259 (match_scratch:HI 2 "r")]
20260 "!optimize_size && !TARGET_PUSH_MEMORY
20261 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
20262 [(set (match_dup 2) (match_dup 1))
20263 (set (match_dup 0) (match_dup 2))]
20267 [(set (match_operand:QI 0 "push_operand" "")
20268 (match_operand:QI 1 "memory_operand" ""))
20269 (match_scratch:QI 2 "q")]
20270 "!optimize_size && !TARGET_PUSH_MEMORY
20271 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
20272 [(set (match_dup 2) (match_dup 1))
20273 (set (match_dup 0) (match_dup 2))]
20276 ;; Don't move an immediate directly to memory when the instruction
20279 [(match_scratch:SI 1 "r")
20280 (set (match_operand:SI 0 "memory_operand" "")
20283 && ! TARGET_USE_MOV0
20284 && TARGET_SPLIT_LONG_MOVES
20285 && get_attr_length (insn) >= ix86_cost->large_insn
20286 && peep2_regno_dead_p (0, FLAGS_REG)"
20287 [(parallel [(set (match_dup 1) (const_int 0))
20288 (clobber (reg:CC FLAGS_REG))])
20289 (set (match_dup 0) (match_dup 1))]
20293 [(match_scratch:HI 1 "r")
20294 (set (match_operand:HI 0 "memory_operand" "")
20297 && ! TARGET_USE_MOV0
20298 && TARGET_SPLIT_LONG_MOVES
20299 && get_attr_length (insn) >= ix86_cost->large_insn
20300 && peep2_regno_dead_p (0, FLAGS_REG)"
20301 [(parallel [(set (match_dup 2) (const_int 0))
20302 (clobber (reg:CC FLAGS_REG))])
20303 (set (match_dup 0) (match_dup 1))]
20304 "operands[2] = gen_lowpart (SImode, operands[1]);")
20307 [(match_scratch:QI 1 "q")
20308 (set (match_operand:QI 0 "memory_operand" "")
20311 && ! TARGET_USE_MOV0
20312 && TARGET_SPLIT_LONG_MOVES
20313 && get_attr_length (insn) >= ix86_cost->large_insn
20314 && peep2_regno_dead_p (0, FLAGS_REG)"
20315 [(parallel [(set (match_dup 2) (const_int 0))
20316 (clobber (reg:CC FLAGS_REG))])
20317 (set (match_dup 0) (match_dup 1))]
20318 "operands[2] = gen_lowpart (SImode, operands[1]);")
20321 [(match_scratch:SI 2 "r")
20322 (set (match_operand:SI 0 "memory_operand" "")
20323 (match_operand:SI 1 "immediate_operand" ""))]
20325 && TARGET_SPLIT_LONG_MOVES
20326 && get_attr_length (insn) >= ix86_cost->large_insn"
20327 [(set (match_dup 2) (match_dup 1))
20328 (set (match_dup 0) (match_dup 2))]
20332 [(match_scratch:HI 2 "r")
20333 (set (match_operand:HI 0 "memory_operand" "")
20334 (match_operand:HI 1 "immediate_operand" ""))]
20336 && TARGET_SPLIT_LONG_MOVES
20337 && get_attr_length (insn) >= ix86_cost->large_insn"
20338 [(set (match_dup 2) (match_dup 1))
20339 (set (match_dup 0) (match_dup 2))]
20343 [(match_scratch:QI 2 "q")
20344 (set (match_operand:QI 0 "memory_operand" "")
20345 (match_operand:QI 1 "immediate_operand" ""))]
20347 && TARGET_SPLIT_LONG_MOVES
20348 && get_attr_length (insn) >= ix86_cost->large_insn"
20349 [(set (match_dup 2) (match_dup 1))
20350 (set (match_dup 0) (match_dup 2))]
20353 ;; Don't compare memory with zero, load and use a test instead.
20355 [(set (match_operand 0 "flags_reg_operand" "")
20356 (match_operator 1 "compare_operator"
20357 [(match_operand:SI 2 "memory_operand" "")
20359 (match_scratch:SI 3 "r")]
20360 " ! optimize_size && ix86_match_ccmode (insn, CCNOmode)"
20361 [(set (match_dup 3) (match_dup 2))
20362 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
20365 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
20366 ;; Don't split NOTs with a displacement operand, because resulting XOR
20367 ;; will not be pairable anyway.
20369 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
20370 ;; represented using a modRM byte. The XOR replacement is long decoded,
20371 ;; so this split helps here as well.
20373 ;; Note: Can't do this as a regular split because we can't get proper
20374 ;; lifetime information then.
20377 [(set (match_operand:SI 0 "nonimmediate_operand" "")
20378 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
20380 && ((TARGET_NOT_UNPAIRABLE
20381 && (!MEM_P (operands[0])
20382 || !memory_displacement_operand (operands[0], SImode)))
20383 || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], SImode)))
20384 && peep2_regno_dead_p (0, FLAGS_REG)"
20385 [(parallel [(set (match_dup 0)
20386 (xor:SI (match_dup 1) (const_int -1)))
20387 (clobber (reg:CC FLAGS_REG))])]
20391 [(set (match_operand:HI 0 "nonimmediate_operand" "")
20392 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
20394 && ((TARGET_NOT_UNPAIRABLE
20395 && (!MEM_P (operands[0])
20396 || !memory_displacement_operand (operands[0], HImode)))
20397 || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], HImode)))
20398 && peep2_regno_dead_p (0, FLAGS_REG)"
20399 [(parallel [(set (match_dup 0)
20400 (xor:HI (match_dup 1) (const_int -1)))
20401 (clobber (reg:CC FLAGS_REG))])]
20405 [(set (match_operand:QI 0 "nonimmediate_operand" "")
20406 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
20408 && ((TARGET_NOT_UNPAIRABLE
20409 && (!MEM_P (operands[0])
20410 || !memory_displacement_operand (operands[0], QImode)))
20411 || (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], QImode)))
20412 && peep2_regno_dead_p (0, FLAGS_REG)"
20413 [(parallel [(set (match_dup 0)
20414 (xor:QI (match_dup 1) (const_int -1)))
20415 (clobber (reg:CC FLAGS_REG))])]
20418 ;; Non pairable "test imm, reg" instructions can be translated to
20419 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
20420 ;; byte opcode instead of two, have a short form for byte operands),
20421 ;; so do it for other CPUs as well. Given that the value was dead,
20422 ;; this should not create any new dependencies. Pass on the sub-word
20423 ;; versions if we're concerned about partial register stalls.
20426 [(set (match_operand 0 "flags_reg_operand" "")
20427 (match_operator 1 "compare_operator"
20428 [(and:SI (match_operand:SI 2 "register_operand" "")
20429 (match_operand:SI 3 "immediate_operand" ""))
20431 "ix86_match_ccmode (insn, CCNOmode)
20432 && (true_regnum (operands[2]) != AX_REG
20433 || satisfies_constraint_K (operands[3]))
20434 && peep2_reg_dead_p (1, operands[2])"
20436 [(set (match_dup 0)
20437 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
20440 (and:SI (match_dup 2) (match_dup 3)))])]
20443 ;; We don't need to handle HImode case, because it will be promoted to SImode
20444 ;; on ! TARGET_PARTIAL_REG_STALL
20447 [(set (match_operand 0 "flags_reg_operand" "")
20448 (match_operator 1 "compare_operator"
20449 [(and:QI (match_operand:QI 2 "register_operand" "")
20450 (match_operand:QI 3 "immediate_operand" ""))
20452 "! TARGET_PARTIAL_REG_STALL
20453 && ix86_match_ccmode (insn, CCNOmode)
20454 && true_regnum (operands[2]) != AX_REG
20455 && peep2_reg_dead_p (1, operands[2])"
20457 [(set (match_dup 0)
20458 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
20461 (and:QI (match_dup 2) (match_dup 3)))])]
20465 [(set (match_operand 0 "flags_reg_operand" "")
20466 (match_operator 1 "compare_operator"
20469 (match_operand 2 "ext_register_operand" "")
20472 (match_operand 3 "const_int_operand" ""))
20474 "! TARGET_PARTIAL_REG_STALL
20475 && ix86_match_ccmode (insn, CCNOmode)
20476 && true_regnum (operands[2]) != AX_REG
20477 && peep2_reg_dead_p (1, operands[2])"
20478 [(parallel [(set (match_dup 0)
20487 (set (zero_extract:SI (match_dup 2)
20498 ;; Don't do logical operations with memory inputs.
20500 [(match_scratch:SI 2 "r")
20501 (parallel [(set (match_operand:SI 0 "register_operand" "")
20502 (match_operator:SI 3 "arith_or_logical_operator"
20504 (match_operand:SI 1 "memory_operand" "")]))
20505 (clobber (reg:CC FLAGS_REG))])]
20506 "! optimize_size && ! TARGET_READ_MODIFY"
20507 [(set (match_dup 2) (match_dup 1))
20508 (parallel [(set (match_dup 0)
20509 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
20510 (clobber (reg:CC FLAGS_REG))])]
20514 [(match_scratch:SI 2 "r")
20515 (parallel [(set (match_operand:SI 0 "register_operand" "")
20516 (match_operator:SI 3 "arith_or_logical_operator"
20517 [(match_operand:SI 1 "memory_operand" "")
20519 (clobber (reg:CC FLAGS_REG))])]
20520 "! optimize_size && ! TARGET_READ_MODIFY"
20521 [(set (match_dup 2) (match_dup 1))
20522 (parallel [(set (match_dup 0)
20523 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
20524 (clobber (reg:CC FLAGS_REG))])]
20527 ; Don't do logical operations with memory outputs
20529 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
20530 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
20531 ; the same decoder scheduling characteristics as the original.
20534 [(match_scratch:SI 2 "r")
20535 (parallel [(set (match_operand:SI 0 "memory_operand" "")
20536 (match_operator:SI 3 "arith_or_logical_operator"
20538 (match_operand:SI 1 "nonmemory_operand" "")]))
20539 (clobber (reg:CC FLAGS_REG))])]
20540 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
20541 [(set (match_dup 2) (match_dup 0))
20542 (parallel [(set (match_dup 2)
20543 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
20544 (clobber (reg:CC FLAGS_REG))])
20545 (set (match_dup 0) (match_dup 2))]
20549 [(match_scratch:SI 2 "r")
20550 (parallel [(set (match_operand:SI 0 "memory_operand" "")
20551 (match_operator:SI 3 "arith_or_logical_operator"
20552 [(match_operand:SI 1 "nonmemory_operand" "")
20554 (clobber (reg:CC FLAGS_REG))])]
20555 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
20556 [(set (match_dup 2) (match_dup 0))
20557 (parallel [(set (match_dup 2)
20558 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
20559 (clobber (reg:CC FLAGS_REG))])
20560 (set (match_dup 0) (match_dup 2))]
20563 ;; Attempt to always use XOR for zeroing registers.
20565 [(set (match_operand 0 "register_operand" "")
20566 (match_operand 1 "const0_operand" ""))]
20567 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
20568 && (! TARGET_USE_MOV0 || optimize_size)
20569 && GENERAL_REG_P (operands[0])
20570 && peep2_regno_dead_p (0, FLAGS_REG)"
20571 [(parallel [(set (match_dup 0) (const_int 0))
20572 (clobber (reg:CC FLAGS_REG))])]
20574 operands[0] = gen_lowpart (word_mode, operands[0]);
20578 [(set (strict_low_part (match_operand 0 "register_operand" ""))
20580 "(GET_MODE (operands[0]) == QImode
20581 || GET_MODE (operands[0]) == HImode)
20582 && (! TARGET_USE_MOV0 || optimize_size)
20583 && peep2_regno_dead_p (0, FLAGS_REG)"
20584 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
20585 (clobber (reg:CC FLAGS_REG))])])
20587 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
20589 [(set (match_operand 0 "register_operand" "")
20591 "(GET_MODE (operands[0]) == HImode
20592 || GET_MODE (operands[0]) == SImode
20593 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
20594 && (optimize_size || TARGET_MOVE_M1_VIA_OR)
20595 && peep2_regno_dead_p (0, FLAGS_REG)"
20596 [(parallel [(set (match_dup 0) (const_int -1))
20597 (clobber (reg:CC FLAGS_REG))])]
20598 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
20601 ;; Attempt to convert simple leas to adds. These can be created by
20604 [(set (match_operand:SI 0 "register_operand" "")
20605 (plus:SI (match_dup 0)
20606 (match_operand:SI 1 "nonmemory_operand" "")))]
20607 "peep2_regno_dead_p (0, FLAGS_REG)"
20608 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
20609 (clobber (reg:CC FLAGS_REG))])]
20613 [(set (match_operand:SI 0 "register_operand" "")
20614 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
20615 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
20616 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
20617 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
20618 (clobber (reg:CC FLAGS_REG))])]
20619 "operands[2] = gen_lowpart (SImode, operands[2]);")
20622 [(set (match_operand:DI 0 "register_operand" "")
20623 (plus:DI (match_dup 0)
20624 (match_operand:DI 1 "x86_64_general_operand" "")))]
20625 "peep2_regno_dead_p (0, FLAGS_REG)"
20626 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
20627 (clobber (reg:CC FLAGS_REG))])]
20631 [(set (match_operand:SI 0 "register_operand" "")
20632 (mult:SI (match_dup 0)
20633 (match_operand:SI 1 "const_int_operand" "")))]
20634 "exact_log2 (INTVAL (operands[1])) >= 0
20635 && peep2_regno_dead_p (0, FLAGS_REG)"
20636 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
20637 (clobber (reg:CC FLAGS_REG))])]
20638 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
20641 [(set (match_operand:DI 0 "register_operand" "")
20642 (mult:DI (match_dup 0)
20643 (match_operand:DI 1 "const_int_operand" "")))]
20644 "exact_log2 (INTVAL (operands[1])) >= 0
20645 && peep2_regno_dead_p (0, FLAGS_REG)"
20646 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
20647 (clobber (reg:CC FLAGS_REG))])]
20648 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
20651 [(set (match_operand:SI 0 "register_operand" "")
20652 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
20653 (match_operand:DI 2 "const_int_operand" "")) 0))]
20654 "exact_log2 (INTVAL (operands[2])) >= 0
20655 && REGNO (operands[0]) == REGNO (operands[1])
20656 && peep2_regno_dead_p (0, FLAGS_REG)"
20657 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
20658 (clobber (reg:CC FLAGS_REG))])]
20659 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
20661 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
20662 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
20663 ;; many CPUs it is also faster, since special hardware to avoid esp
20664 ;; dependencies is present.
20666 ;; While some of these conversions may be done using splitters, we use peepholes
20667 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
20669 ;; Convert prologue esp subtractions to push.
20670 ;; We need register to push. In order to keep verify_flow_info happy we have
20672 ;; - use scratch and clobber it in order to avoid dependencies
20673 ;; - use already live register
20674 ;; We can't use the second way right now, since there is no reliable way how to
20675 ;; verify that given register is live. First choice will also most likely in
20676 ;; fewer dependencies. On the place of esp adjustments it is very likely that
20677 ;; call clobbered registers are dead. We may want to use base pointer as an
20678 ;; alternative when no register is available later.
20681 [(match_scratch:SI 0 "r")
20682 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
20683 (clobber (reg:CC FLAGS_REG))
20684 (clobber (mem:BLK (scratch)))])]
20685 "optimize_size || !TARGET_SUB_ESP_4"
20686 [(clobber (match_dup 0))
20687 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
20688 (clobber (mem:BLK (scratch)))])])
20691 [(match_scratch:SI 0 "r")
20692 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
20693 (clobber (reg:CC FLAGS_REG))
20694 (clobber (mem:BLK (scratch)))])]
20695 "optimize_size || !TARGET_SUB_ESP_8"
20696 [(clobber (match_dup 0))
20697 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
20698 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
20699 (clobber (mem:BLK (scratch)))])])
20701 ;; Convert esp subtractions to push.
20703 [(match_scratch:SI 0 "r")
20704 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
20705 (clobber (reg:CC FLAGS_REG))])]
20706 "optimize_size || !TARGET_SUB_ESP_4"
20707 [(clobber (match_dup 0))
20708 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
20711 [(match_scratch:SI 0 "r")
20712 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
20713 (clobber (reg:CC FLAGS_REG))])]
20714 "optimize_size || !TARGET_SUB_ESP_8"
20715 [(clobber (match_dup 0))
20716 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
20717 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
20719 ;; Convert epilogue deallocator to pop.
20721 [(match_scratch:SI 0 "r")
20722 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
20723 (clobber (reg:CC FLAGS_REG))
20724 (clobber (mem:BLK (scratch)))])]
20725 "optimize_size || !TARGET_ADD_ESP_4"
20726 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20727 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
20728 (clobber (mem:BLK (scratch)))])]
20731 ;; Two pops case is tricky, since pop causes dependency on destination register.
20732 ;; We use two registers if available.
20734 [(match_scratch:SI 0 "r")
20735 (match_scratch:SI 1 "r")
20736 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
20737 (clobber (reg:CC FLAGS_REG))
20738 (clobber (mem:BLK (scratch)))])]
20739 "optimize_size || !TARGET_ADD_ESP_8"
20740 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20741 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
20742 (clobber (mem:BLK (scratch)))])
20743 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
20744 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
20748 [(match_scratch:SI 0 "r")
20749 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
20750 (clobber (reg:CC FLAGS_REG))
20751 (clobber (mem:BLK (scratch)))])]
20753 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20754 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
20755 (clobber (mem:BLK (scratch)))])
20756 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20757 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
20760 ;; Convert esp additions to pop.
20762 [(match_scratch:SI 0 "r")
20763 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
20764 (clobber (reg:CC FLAGS_REG))])]
20766 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20767 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
20770 ;; Two pops case is tricky, since pop causes dependency on destination register.
20771 ;; We use two registers if available.
20773 [(match_scratch:SI 0 "r")
20774 (match_scratch:SI 1 "r")
20775 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
20776 (clobber (reg:CC FLAGS_REG))])]
20778 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20779 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
20780 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
20781 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
20785 [(match_scratch:SI 0 "r")
20786 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
20787 (clobber (reg:CC FLAGS_REG))])]
20789 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20790 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
20791 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
20792 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
20795 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
20796 ;; required and register dies. Similarly for 128 to plus -128.
20798 [(set (match_operand 0 "flags_reg_operand" "")
20799 (match_operator 1 "compare_operator"
20800 [(match_operand 2 "register_operand" "")
20801 (match_operand 3 "const_int_operand" "")]))]
20802 "(INTVAL (operands[3]) == -1
20803 || INTVAL (operands[3]) == 1
20804 || INTVAL (operands[3]) == 128)
20805 && ix86_match_ccmode (insn, CCGCmode)
20806 && peep2_reg_dead_p (1, operands[2])"
20807 [(parallel [(set (match_dup 0)
20808 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
20809 (clobber (match_dup 2))])]
20813 [(match_scratch:DI 0 "r")
20814 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
20815 (clobber (reg:CC FLAGS_REG))
20816 (clobber (mem:BLK (scratch)))])]
20817 "optimize_size || !TARGET_SUB_ESP_4"
20818 [(clobber (match_dup 0))
20819 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
20820 (clobber (mem:BLK (scratch)))])])
20823 [(match_scratch:DI 0 "r")
20824 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
20825 (clobber (reg:CC FLAGS_REG))
20826 (clobber (mem:BLK (scratch)))])]
20827 "optimize_size || !TARGET_SUB_ESP_8"
20828 [(clobber (match_dup 0))
20829 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
20830 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
20831 (clobber (mem:BLK (scratch)))])])
20833 ;; Convert esp subtractions to push.
20835 [(match_scratch:DI 0 "r")
20836 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
20837 (clobber (reg:CC FLAGS_REG))])]
20838 "optimize_size || !TARGET_SUB_ESP_4"
20839 [(clobber (match_dup 0))
20840 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
20843 [(match_scratch:DI 0 "r")
20844 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
20845 (clobber (reg:CC FLAGS_REG))])]
20846 "optimize_size || !TARGET_SUB_ESP_8"
20847 [(clobber (match_dup 0))
20848 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
20849 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
20851 ;; Convert epilogue deallocator to pop.
20853 [(match_scratch:DI 0 "r")
20854 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
20855 (clobber (reg:CC FLAGS_REG))
20856 (clobber (mem:BLK (scratch)))])]
20857 "optimize_size || !TARGET_ADD_ESP_4"
20858 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20859 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
20860 (clobber (mem:BLK (scratch)))])]
20863 ;; Two pops case is tricky, since pop causes dependency on destination register.
20864 ;; We use two registers if available.
20866 [(match_scratch:DI 0 "r")
20867 (match_scratch:DI 1 "r")
20868 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
20869 (clobber (reg:CC FLAGS_REG))
20870 (clobber (mem:BLK (scratch)))])]
20871 "optimize_size || !TARGET_ADD_ESP_8"
20872 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20873 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
20874 (clobber (mem:BLK (scratch)))])
20875 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
20876 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
20880 [(match_scratch:DI 0 "r")
20881 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
20882 (clobber (reg:CC FLAGS_REG))
20883 (clobber (mem:BLK (scratch)))])]
20885 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20886 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
20887 (clobber (mem:BLK (scratch)))])
20888 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20889 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
20892 ;; Convert esp additions to pop.
20894 [(match_scratch:DI 0 "r")
20895 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
20896 (clobber (reg:CC FLAGS_REG))])]
20898 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20899 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
20902 ;; Two pops case is tricky, since pop causes dependency on destination register.
20903 ;; We use two registers if available.
20905 [(match_scratch:DI 0 "r")
20906 (match_scratch:DI 1 "r")
20907 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
20908 (clobber (reg:CC FLAGS_REG))])]
20910 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20911 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
20912 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
20913 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
20917 [(match_scratch:DI 0 "r")
20918 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
20919 (clobber (reg:CC FLAGS_REG))])]
20921 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20922 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
20923 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
20924 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
20927 ;; Convert imul by three, five and nine into lea
20930 [(set (match_operand:SI 0 "register_operand" "")
20931 (mult:SI (match_operand:SI 1 "register_operand" "")
20932 (match_operand:SI 2 "const_int_operand" "")))
20933 (clobber (reg:CC FLAGS_REG))])]
20934 "INTVAL (operands[2]) == 3
20935 || INTVAL (operands[2]) == 5
20936 || INTVAL (operands[2]) == 9"
20937 [(set (match_dup 0)
20938 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
20940 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
20944 [(set (match_operand:SI 0 "register_operand" "")
20945 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
20946 (match_operand:SI 2 "const_int_operand" "")))
20947 (clobber (reg:CC FLAGS_REG))])]
20949 && (INTVAL (operands[2]) == 3
20950 || INTVAL (operands[2]) == 5
20951 || INTVAL (operands[2]) == 9)"
20952 [(set (match_dup 0) (match_dup 1))
20954 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
20956 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
20960 [(set (match_operand:DI 0 "register_operand" "")
20961 (mult:DI (match_operand:DI 1 "register_operand" "")
20962 (match_operand:DI 2 "const_int_operand" "")))
20963 (clobber (reg:CC FLAGS_REG))])]
20965 && (INTVAL (operands[2]) == 3
20966 || INTVAL (operands[2]) == 5
20967 || INTVAL (operands[2]) == 9)"
20968 [(set (match_dup 0)
20969 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
20971 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
20975 [(set (match_operand:DI 0 "register_operand" "")
20976 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
20977 (match_operand:DI 2 "const_int_operand" "")))
20978 (clobber (reg:CC FLAGS_REG))])]
20981 && (INTVAL (operands[2]) == 3
20982 || INTVAL (operands[2]) == 5
20983 || INTVAL (operands[2]) == 9)"
20984 [(set (match_dup 0) (match_dup 1))
20986 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
20988 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
20990 ;; Imul $32bit_imm, mem, reg is vector decoded, while
20991 ;; imul $32bit_imm, reg, reg is direct decoded.
20993 [(match_scratch:DI 3 "r")
20994 (parallel [(set (match_operand:DI 0 "register_operand" "")
20995 (mult:DI (match_operand:DI 1 "memory_operand" "")
20996 (match_operand:DI 2 "immediate_operand" "")))
20997 (clobber (reg:CC FLAGS_REG))])]
20998 "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
20999 && !satisfies_constraint_K (operands[2])"
21000 [(set (match_dup 3) (match_dup 1))
21001 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
21002 (clobber (reg:CC FLAGS_REG))])]
21006 [(match_scratch:SI 3 "r")
21007 (parallel [(set (match_operand:SI 0 "register_operand" "")
21008 (mult:SI (match_operand:SI 1 "memory_operand" "")
21009 (match_operand:SI 2 "immediate_operand" "")))
21010 (clobber (reg:CC FLAGS_REG))])]
21011 "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
21012 && !satisfies_constraint_K (operands[2])"
21013 [(set (match_dup 3) (match_dup 1))
21014 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
21015 (clobber (reg:CC FLAGS_REG))])]
21019 [(match_scratch:SI 3 "r")
21020 (parallel [(set (match_operand:DI 0 "register_operand" "")
21022 (mult:SI (match_operand:SI 1 "memory_operand" "")
21023 (match_operand:SI 2 "immediate_operand" ""))))
21024 (clobber (reg:CC FLAGS_REG))])]
21025 "TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
21026 && !satisfies_constraint_K (operands[2])"
21027 [(set (match_dup 3) (match_dup 1))
21028 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
21029 (clobber (reg:CC FLAGS_REG))])]
21032 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
21033 ;; Convert it into imul reg, reg
21034 ;; It would be better to force assembler to encode instruction using long
21035 ;; immediate, but there is apparently no way to do so.
21037 [(parallel [(set (match_operand:DI 0 "register_operand" "")
21038 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
21039 (match_operand:DI 2 "const_int_operand" "")))
21040 (clobber (reg:CC FLAGS_REG))])
21041 (match_scratch:DI 3 "r")]
21042 "TARGET_SLOW_IMUL_IMM8 && !optimize_size
21043 && satisfies_constraint_K (operands[2])"
21044 [(set (match_dup 3) (match_dup 2))
21045 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
21046 (clobber (reg:CC FLAGS_REG))])]
21048 if (!rtx_equal_p (operands[0], operands[1]))
21049 emit_move_insn (operands[0], operands[1]);
21053 [(parallel [(set (match_operand:SI 0 "register_operand" "")
21054 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
21055 (match_operand:SI 2 "const_int_operand" "")))
21056 (clobber (reg:CC FLAGS_REG))])
21057 (match_scratch:SI 3 "r")]
21058 "TARGET_SLOW_IMUL_IMM8 && !optimize_size
21059 && satisfies_constraint_K (operands[2])"
21060 [(set (match_dup 3) (match_dup 2))
21061 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
21062 (clobber (reg:CC FLAGS_REG))])]
21064 if (!rtx_equal_p (operands[0], operands[1]))
21065 emit_move_insn (operands[0], operands[1]);
21069 [(parallel [(set (match_operand:HI 0 "register_operand" "")
21070 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
21071 (match_operand:HI 2 "immediate_operand" "")))
21072 (clobber (reg:CC FLAGS_REG))])
21073 (match_scratch:HI 3 "r")]
21074 "TARGET_SLOW_IMUL_IMM8 && !optimize_size"
21075 [(set (match_dup 3) (match_dup 2))
21076 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
21077 (clobber (reg:CC FLAGS_REG))])]
21079 if (!rtx_equal_p (operands[0], operands[1]))
21080 emit_move_insn (operands[0], operands[1]);
21083 ;; After splitting up read-modify operations, array accesses with memory
21084 ;; operands might end up in form:
21086 ;; movl 4(%esp), %edx
21088 ;; instead of pre-splitting:
21090 ;; addl 4(%esp), %eax
21092 ;; movl 4(%esp), %edx
21093 ;; leal (%edx,%eax,4), %eax
21096 [(parallel [(set (match_operand 0 "register_operand" "")
21097 (ashift (match_operand 1 "register_operand" "")
21098 (match_operand 2 "const_int_operand" "")))
21099 (clobber (reg:CC FLAGS_REG))])
21100 (set (match_operand 3 "register_operand")
21101 (match_operand 4 "x86_64_general_operand" ""))
21102 (parallel [(set (match_operand 5 "register_operand" "")
21103 (plus (match_operand 6 "register_operand" "")
21104 (match_operand 7 "register_operand" "")))
21105 (clobber (reg:CC FLAGS_REG))])]
21106 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
21107 /* Validate MODE for lea. */
21108 && ((!TARGET_PARTIAL_REG_STALL
21109 && (GET_MODE (operands[0]) == QImode
21110 || GET_MODE (operands[0]) == HImode))
21111 || GET_MODE (operands[0]) == SImode
21112 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
21113 /* We reorder load and the shift. */
21114 && !rtx_equal_p (operands[1], operands[3])
21115 && !reg_overlap_mentioned_p (operands[0], operands[4])
21116 /* Last PLUS must consist of operand 0 and 3. */
21117 && !rtx_equal_p (operands[0], operands[3])
21118 && (rtx_equal_p (operands[3], operands[6])
21119 || rtx_equal_p (operands[3], operands[7]))
21120 && (rtx_equal_p (operands[0], operands[6])
21121 || rtx_equal_p (operands[0], operands[7]))
21122 /* The intermediate operand 0 must die or be same as output. */
21123 && (rtx_equal_p (operands[0], operands[5])
21124 || peep2_reg_dead_p (3, operands[0]))"
21125 [(set (match_dup 3) (match_dup 4))
21126 (set (match_dup 0) (match_dup 1))]
21128 enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode;
21129 int scale = 1 << INTVAL (operands[2]);
21130 rtx index = gen_lowpart (Pmode, operands[1]);
21131 rtx base = gen_lowpart (Pmode, operands[3]);
21132 rtx dest = gen_lowpart (mode, operands[5]);
21134 operands[1] = gen_rtx_PLUS (Pmode, base,
21135 gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
21137 operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
21138 operands[0] = dest;
21141 ;; Call-value patterns last so that the wildcard operand does not
21142 ;; disrupt insn-recog's switch tables.
21144 (define_insn "*call_value_pop_0"
21145 [(set (match_operand 0 "" "")
21146 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
21147 (match_operand:SI 2 "" "")))
21148 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
21149 (match_operand:SI 3 "immediate_operand" "")))]
21152 if (SIBLING_CALL_P (insn))
21155 return "call\t%P1";
21157 [(set_attr "type" "callv")])
21159 (define_insn "*call_value_pop_1"
21160 [(set (match_operand 0 "" "")
21161 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
21162 (match_operand:SI 2 "" "")))
21163 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
21164 (match_operand:SI 3 "immediate_operand" "i")))]
21167 if (constant_call_address_operand (operands[1], Pmode))
21169 if (SIBLING_CALL_P (insn))
21172 return "call\t%P1";
21174 if (SIBLING_CALL_P (insn))
21177 return "call\t%A1";
21179 [(set_attr "type" "callv")])
21181 (define_insn "*call_value_0"
21182 [(set (match_operand 0 "" "")
21183 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
21184 (match_operand:SI 2 "" "")))]
21187 if (SIBLING_CALL_P (insn))
21190 return "call\t%P1";
21192 [(set_attr "type" "callv")])
21194 (define_insn "*call_value_0_rex64"
21195 [(set (match_operand 0 "" "")
21196 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
21197 (match_operand:DI 2 "const_int_operand" "")))]
21200 if (SIBLING_CALL_P (insn))
21203 return "call\t%P1";
21205 [(set_attr "type" "callv")])
21207 (define_insn "*call_value_1"
21208 [(set (match_operand 0 "" "")
21209 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
21210 (match_operand:SI 2 "" "")))]
21211 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
21213 if (constant_call_address_operand (operands[1], Pmode))
21214 return "call\t%P1";
21215 return "call\t%A1";
21217 [(set_attr "type" "callv")])
21219 (define_insn "*sibcall_value_1"
21220 [(set (match_operand 0 "" "")
21221 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
21222 (match_operand:SI 2 "" "")))]
21223 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
21225 if (constant_call_address_operand (operands[1], Pmode))
21229 [(set_attr "type" "callv")])
21231 (define_insn "*call_value_1_rex64"
21232 [(set (match_operand 0 "" "")
21233 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
21234 (match_operand:DI 2 "" "")))]
21235 "!SIBLING_CALL_P (insn) && TARGET_64BIT
21236 && ix86_cmodel != CM_LARGE && ix86_cmodel != CM_LARGE_PIC"
21238 if (constant_call_address_operand (operands[1], Pmode))
21239 return "call\t%P1";
21240 return "call\t%A1";
21242 [(set_attr "type" "callv")])
21244 (define_insn "*call_value_1_rex64_large"
21245 [(set (match_operand 0 "" "")
21246 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rm"))
21247 (match_operand:DI 2 "" "")))]
21248 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
21250 [(set_attr "type" "callv")])
21252 (define_insn "*sibcall_value_1_rex64"
21253 [(set (match_operand 0 "" "")
21254 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
21255 (match_operand:DI 2 "" "")))]
21256 "SIBLING_CALL_P (insn) && TARGET_64BIT"
21258 [(set_attr "type" "callv")])
21260 (define_insn "*sibcall_value_1_rex64_v"
21261 [(set (match_operand 0 "" "")
21262 (call (mem:QI (reg:DI R11_REG))
21263 (match_operand:DI 1 "" "")))]
21264 "SIBLING_CALL_P (insn) && TARGET_64BIT"
21266 [(set_attr "type" "callv")])
21268 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
21269 ;; That, however, is usually mapped by the OS to SIGSEGV, which is often
21270 ;; caught for use by garbage collectors and the like. Using an insn that
21271 ;; maps to SIGILL makes it more likely the program will rightfully die.
21272 ;; Keeping with tradition, "6" is in honor of #UD.
21273 (define_insn "trap"
21274 [(trap_if (const_int 1) (const_int 6))]
21276 { return ASM_SHORT "0x0b0f"; }
21277 [(set_attr "length" "2")])
21279 (define_expand "sse_prologue_save"
21280 [(parallel [(set (match_operand:BLK 0 "" "")
21281 (unspec:BLK [(reg:DI 21)
21288 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21289 (use (match_operand:DI 1 "register_operand" ""))
21290 (use (match_operand:DI 2 "immediate_operand" ""))
21291 (use (label_ref:DI (match_operand 3 "" "")))])]
21295 (define_insn "*sse_prologue_save_insn"
21296 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21297 (match_operand:DI 4 "const_int_operand" "n")))
21298 (unspec:BLK [(reg:DI 21)
21305 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21306 (use (match_operand:DI 1 "register_operand" "r"))
21307 (use (match_operand:DI 2 "const_int_operand" "i"))
21308 (use (label_ref:DI (match_operand 3 "" "X")))]
21310 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21311 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21315 operands[0] = gen_rtx_MEM (Pmode,
21316 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21317 output_asm_insn (\"jmp\\t%A1\", operands);
21318 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21320 operands[4] = adjust_address (operands[0], DImode, i*16);
21321 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21322 PUT_MODE (operands[4], TImode);
21323 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21324 output_asm_insn (\"rex\", operands);
21325 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21327 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21328 CODE_LABEL_NUMBER (operands[3]));
21332 [(set_attr "type" "other")
21333 (set_attr "length_immediate" "0")
21334 (set_attr "length_address" "0")
21335 (set_attr "length" "135")
21336 (set_attr "memory" "store")
21337 (set_attr "modrm" "0")
21338 (set_attr "mode" "DI")])
21340 (define_expand "prefetch"
21341 [(prefetch (match_operand 0 "address_operand" "")
21342 (match_operand:SI 1 "const_int_operand" "")
21343 (match_operand:SI 2 "const_int_operand" ""))]
21344 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21346 int rw = INTVAL (operands[1]);
21347 int locality = INTVAL (operands[2]);
21349 gcc_assert (rw == 0 || rw == 1);
21350 gcc_assert (locality >= 0 && locality <= 3);
21351 gcc_assert (GET_MODE (operands[0]) == Pmode
21352 || GET_MODE (operands[0]) == VOIDmode);
21354 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21355 supported by SSE counterpart or the SSE prefetch is not available
21356 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21358 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21359 operands[2] = GEN_INT (3);
21361 operands[1] = const0_rtx;
21364 (define_insn "*prefetch_sse"
21365 [(prefetch (match_operand:SI 0 "address_operand" "p")
21367 (match_operand:SI 1 "const_int_operand" ""))]
21368 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21370 static const char * const patterns[4] = {
21371 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21374 int locality = INTVAL (operands[1]);
21375 gcc_assert (locality >= 0 && locality <= 3);
21377 return patterns[locality];
21379 [(set_attr "type" "sse")
21380 (set_attr "memory" "none")])
21382 (define_insn "*prefetch_sse_rex"
21383 [(prefetch (match_operand:DI 0 "address_operand" "p")
21385 (match_operand:SI 1 "const_int_operand" ""))]
21386 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21388 static const char * const patterns[4] = {
21389 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21392 int locality = INTVAL (operands[1]);
21393 gcc_assert (locality >= 0 && locality <= 3);
21395 return patterns[locality];
21397 [(set_attr "type" "sse")
21398 (set_attr "memory" "none")])
21400 (define_insn "*prefetch_3dnow"
21401 [(prefetch (match_operand:SI 0 "address_operand" "p")
21402 (match_operand:SI 1 "const_int_operand" "n")
21404 "TARGET_3DNOW && !TARGET_64BIT"
21406 if (INTVAL (operands[1]) == 0)
21407 return "prefetch\t%a0";
21409 return "prefetchw\t%a0";
21411 [(set_attr "type" "mmx")
21412 (set_attr "memory" "none")])
21414 (define_insn "*prefetch_3dnow_rex"
21415 [(prefetch (match_operand:DI 0 "address_operand" "p")
21416 (match_operand:SI 1 "const_int_operand" "n")
21418 "TARGET_3DNOW && TARGET_64BIT"
21420 if (INTVAL (operands[1]) == 0)
21421 return "prefetch\t%a0";
21423 return "prefetchw\t%a0";
21425 [(set_attr "type" "mmx")
21426 (set_attr "memory" "none")])
21428 (define_expand "stack_protect_set"
21429 [(match_operand 0 "memory_operand" "")
21430 (match_operand 1 "memory_operand" "")]
21433 #ifdef TARGET_THREAD_SSP_OFFSET
21435 emit_insn (gen_stack_tls_protect_set_di (operands[0],
21436 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
21438 emit_insn (gen_stack_tls_protect_set_si (operands[0],
21439 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
21442 emit_insn (gen_stack_protect_set_di (operands[0], operands[1]));
21444 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
21449 (define_insn "stack_protect_set_si"
21450 [(set (match_operand:SI 0 "memory_operand" "=m")
21451 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
21452 (set (match_scratch:SI 2 "=&r") (const_int 0))
21453 (clobber (reg:CC FLAGS_REG))]
21455 "mov{l}\t{%1, %2|%2, %1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
21456 [(set_attr "type" "multi")])
21458 (define_insn "stack_protect_set_di"
21459 [(set (match_operand:DI 0 "memory_operand" "=m")
21460 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
21461 (set (match_scratch:DI 2 "=&r") (const_int 0))
21462 (clobber (reg:CC FLAGS_REG))]
21464 "mov{q}\t{%1, %2|%2, %1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
21465 [(set_attr "type" "multi")])
21467 (define_insn "stack_tls_protect_set_si"
21468 [(set (match_operand:SI 0 "memory_operand" "=m")
21469 (unspec:SI [(match_operand:SI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
21470 (set (match_scratch:SI 2 "=&r") (const_int 0))
21471 (clobber (reg:CC FLAGS_REG))]
21473 "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
21474 [(set_attr "type" "multi")])
21476 (define_insn "stack_tls_protect_set_di"
21477 [(set (match_operand:DI 0 "memory_operand" "=m")
21478 (unspec:DI [(match_operand:DI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
21479 (set (match_scratch:DI 2 "=&r") (const_int 0))
21480 (clobber (reg:CC FLAGS_REG))]
21483 /* The kernel uses a different segment register for performance reasons; a
21484 system call would not have to trash the userspace segment register,
21485 which would be expensive */
21486 if (ix86_cmodel != CM_KERNEL)
21487 return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
21489 return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR %%gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
21491 [(set_attr "type" "multi")])
21493 (define_expand "stack_protect_test"
21494 [(match_operand 0 "memory_operand" "")
21495 (match_operand 1 "memory_operand" "")
21496 (match_operand 2 "" "")]
21499 rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
21500 ix86_compare_op0 = operands[0];
21501 ix86_compare_op1 = operands[1];
21502 ix86_compare_emitted = flags;
21504 #ifdef TARGET_THREAD_SSP_OFFSET
21506 emit_insn (gen_stack_tls_protect_test_di (flags, operands[0],
21507 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
21509 emit_insn (gen_stack_tls_protect_test_si (flags, operands[0],
21510 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
21513 emit_insn (gen_stack_protect_test_di (flags, operands[0], operands[1]));
21515 emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
21517 emit_jump_insn (gen_beq (operands[2]));
21521 (define_insn "stack_protect_test_si"
21522 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
21523 (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
21524 (match_operand:SI 2 "memory_operand" "m")]
21526 (clobber (match_scratch:SI 3 "=&r"))]
21528 "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%2, %3|%3, %2}"
21529 [(set_attr "type" "multi")])
21531 (define_insn "stack_protect_test_di"
21532 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
21533 (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
21534 (match_operand:DI 2 "memory_operand" "m")]
21536 (clobber (match_scratch:DI 3 "=&r"))]
21538 "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%2, %3|%3, %2}"
21539 [(set_attr "type" "multi")])
21541 (define_insn "stack_tls_protect_test_si"
21542 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
21543 (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
21544 (match_operand:SI 2 "const_int_operand" "i")]
21545 UNSPEC_SP_TLS_TEST))
21546 (clobber (match_scratch:SI 3 "=r"))]
21548 "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
21549 [(set_attr "type" "multi")])
21551 (define_insn "stack_tls_protect_test_di"
21552 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
21553 (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
21554 (match_operand:DI 2 "const_int_operand" "i")]
21555 UNSPEC_SP_TLS_TEST))
21556 (clobber (match_scratch:DI 3 "=r"))]
21559 /* The kernel uses a different segment register for performance reasons; a
21560 system call would not have to trash the userspace segment register,
21561 which would be expensive */
21562 if (ix86_cmodel != CM_KERNEL)
21563 return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}";
21565 return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR %%gs:%P2}";
21567 [(set_attr "type" "multi")])
21569 (define_mode_iterator CRC32MODE [QI HI SI])
21570 (define_mode_attr crc32modesuffix [(QI "b") (HI "w") (SI "l")])
21571 (define_mode_attr crc32modeconstraint [(QI "qm") (HI "rm") (SI "rm")])
21573 (define_insn "sse4_2_crc32<mode>"
21574 [(set (match_operand:SI 0 "register_operand" "=r")
21576 [(match_operand:SI 1 "register_operand" "0")
21577 (match_operand:CRC32MODE 2 "nonimmediate_operand" "<crc32modeconstraint>")]
21580 "crc32<crc32modesuffix>\t{%2, %0|%0, %2}"
21581 [(set_attr "type" "sselog1")
21582 (set_attr "prefix_rep" "1")
21583 (set_attr "prefix_extra" "1")
21584 (set_attr "mode" "SI")])
21586 (define_insn "sse4_2_crc32di"
21587 [(set (match_operand:DI 0 "register_operand" "=r")
21589 [(match_operand:DI 1 "register_operand" "0")
21590 (match_operand:DI 2 "nonimmediate_operand" "rm")]
21592 "TARGET_SSE4_2 && TARGET_64BIT"
21593 "crc32q\t{%2, %0|%0, %2}"
21594 [(set_attr "type" "sselog1")
21595 (set_attr "prefix_rep" "1")
21596 (set_attr "prefix_extra" "1")
21597 (set_attr "mode" "DI")])
21601 (include "sync.md")