1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
31 ;; updates for most instructions.
33 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
34 ;; constraint letters.
36 ;; The special asm out single letter directives following a '%' are:
37 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
39 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
40 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
41 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
42 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
43 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
44 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
45 ;; 'J' Print the appropriate jump operand.
47 ;; 'b' Print the QImode name of the register for the indicated operand.
48 ;; %b0 would print %al if operands[0] is reg 0.
49 ;; 'w' Likewise, print the HImode name of the register.
50 ;; 'k' Likewise, print the SImode name of the register.
51 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52 ;; 'y' Print "st(0)" instead of "st" as a register.
57 [; Relocation specifiers
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
77 (UNSPEC_TLS_LD_BASE 17)
79 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
118 [(UNSPECV_BLOCKAGE 0)
119 (UNSPECV_EH_RETURN 13)
127 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
130 ;; In C guard expressions, put expressions which may be compile-time
131 ;; constants first. This allows for better optimization. For
132 ;; example, write "TARGET_64BIT && reload_completed", not
133 ;; "reload_completed && TARGET_64BIT".
136 ;; Processor type. This attribute must exactly match the processor_type
137 ;; enumeration in i386.h.
138 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
139 (const (symbol_ref "ix86_tune")))
141 ;; A basic instruction type. Refinements due to arguments to be
142 ;; provided in other attributes.
145 alu,alu1,negnot,imov,imovx,lea,
146 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
147 icmp,test,ibr,setcc,icmov,
148 push,pop,call,callv,leave,
150 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
151 sselog,sseiadd,sseishft,sseimul,
152 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
153 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
154 (const_string "other"))
156 ;; Main data type used by the insn
158 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
159 (const_string "unknown"))
161 ;; The CPU unit operations uses.
162 (define_attr "unit" "integer,i387,sse,mmx,unknown"
163 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
164 (const_string "i387")
165 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
166 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
168 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
170 (eq_attr "type" "other")
171 (const_string "unknown")]
172 (const_string "integer")))
174 ;; The (bounding maximum) length of an instruction immediate.
175 (define_attr "length_immediate" ""
176 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
178 (eq_attr "unit" "i387,sse,mmx")
180 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
182 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
183 (eq_attr "type" "imov,test")
184 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
185 (eq_attr "type" "call")
186 (if_then_else (match_operand 0 "constant_call_address_operand" "")
189 (eq_attr "type" "callv")
190 (if_then_else (match_operand 1 "constant_call_address_operand" "")
193 ;; We don't know the size before shorten_branches. Expect
194 ;; the instruction to fit for better scheduling.
195 (eq_attr "type" "ibr")
198 (symbol_ref "/* Update immediate_length and other attributes! */
201 ;; The (bounding maximum) length of an instruction address.
202 (define_attr "length_address" ""
203 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
205 (and (eq_attr "type" "call")
206 (match_operand 0 "constant_call_address_operand" ""))
208 (and (eq_attr "type" "callv")
209 (match_operand 1 "constant_call_address_operand" ""))
212 (symbol_ref "ix86_attr_length_address_default (insn)")))
214 ;; Set when length prefix is used.
215 (define_attr "prefix_data16" ""
216 (if_then_else (ior (eq_attr "mode" "HI")
217 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
221 ;; Set when string REP prefix is used.
222 (define_attr "prefix_rep" ""
223 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
227 ;; Set when 0f opcode prefix is used.
228 (define_attr "prefix_0f" ""
230 (ior (eq_attr "type" "imovx,setcc,icmov")
231 (eq_attr "unit" "sse,mmx"))
235 ;; Set when 0f opcode prefix is used.
236 (define_attr "prefix_rex" ""
237 (cond [(and (eq_attr "mode" "DI")
238 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
240 (and (eq_attr "mode" "QI")
241 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
244 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
250 ;; Set when modrm byte is used.
251 (define_attr "modrm" ""
252 (cond [(eq_attr "type" "str,cld,leave")
254 (eq_attr "unit" "i387")
256 (and (eq_attr "type" "incdec")
257 (ior (match_operand:SI 1 "register_operand" "")
258 (match_operand:HI 1 "register_operand" "")))
260 (and (eq_attr "type" "push")
261 (not (match_operand 1 "memory_operand" "")))
263 (and (eq_attr "type" "pop")
264 (not (match_operand 0 "memory_operand" "")))
266 (and (eq_attr "type" "imov")
267 (and (match_operand 0 "register_operand" "")
268 (match_operand 1 "immediate_operand" "")))
270 (and (eq_attr "type" "call")
271 (match_operand 0 "constant_call_address_operand" ""))
273 (and (eq_attr "type" "callv")
274 (match_operand 1 "constant_call_address_operand" ""))
279 ;; The (bounding maximum) length of an instruction in bytes.
280 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
281 ;; to split it and compute proper length as for other insns.
282 (define_attr "length" ""
283 (cond [(eq_attr "type" "other,multi,fistp")
285 (eq_attr "unit" "i387")
287 (plus (attr "prefix_data16")
288 (attr "length_address")))]
289 (plus (plus (attr "modrm")
290 (plus (attr "prefix_0f")
291 (plus (attr "prefix_rex")
293 (plus (attr "prefix_rep")
294 (plus (attr "prefix_data16")
295 (plus (attr "length_immediate")
296 (attr "length_address")))))))
298 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
299 ;; `store' if there is a simple memory reference therein, or `unknown'
300 ;; if the instruction is complex.
302 (define_attr "memory" "none,load,store,both,unknown"
303 (cond [(eq_attr "type" "other,multi,str")
304 (const_string "unknown")
305 (eq_attr "type" "lea,fcmov,fpspc,cld")
306 (const_string "none")
307 (eq_attr "type" "fistp,leave")
308 (const_string "both")
309 (eq_attr "type" "push")
310 (if_then_else (match_operand 1 "memory_operand" "")
311 (const_string "both")
312 (const_string "store"))
313 (eq_attr "type" "pop")
314 (if_then_else (match_operand 0 "memory_operand" "")
315 (const_string "both")
316 (const_string "load"))
317 (eq_attr "type" "setcc")
318 (if_then_else (match_operand 0 "memory_operand" "")
319 (const_string "store")
320 (const_string "none"))
321 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
322 (if_then_else (ior (match_operand 0 "memory_operand" "")
323 (match_operand 1 "memory_operand" ""))
324 (const_string "load")
325 (const_string "none"))
326 (eq_attr "type" "ibr")
327 (if_then_else (match_operand 0 "memory_operand" "")
328 (const_string "load")
329 (const_string "none"))
330 (eq_attr "type" "call")
331 (if_then_else (match_operand 0 "constant_call_address_operand" "")
332 (const_string "none")
333 (const_string "load"))
334 (eq_attr "type" "callv")
335 (if_then_else (match_operand 1 "constant_call_address_operand" "")
336 (const_string "none")
337 (const_string "load"))
338 (and (eq_attr "type" "alu1,negnot")
339 (match_operand 1 "memory_operand" ""))
340 (const_string "both")
341 (and (match_operand 0 "memory_operand" "")
342 (match_operand 1 "memory_operand" ""))
343 (const_string "both")
344 (match_operand 0 "memory_operand" "")
345 (const_string "store")
346 (match_operand 1 "memory_operand" "")
347 (const_string "load")
350 imov,imovx,icmp,test,
352 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
353 mmx,mmxmov,mmxcmp,mmxcvt")
354 (match_operand 2 "memory_operand" ""))
355 (const_string "load")
356 (and (eq_attr "type" "icmov")
357 (match_operand 3 "memory_operand" ""))
358 (const_string "load")
360 (const_string "none")))
362 ;; Indicates if an instruction has both an immediate and a displacement.
364 (define_attr "imm_disp" "false,true,unknown"
365 (cond [(eq_attr "type" "other,multi")
366 (const_string "unknown")
367 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
368 (and (match_operand 0 "memory_displacement_operand" "")
369 (match_operand 1 "immediate_operand" "")))
370 (const_string "true")
371 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
372 (and (match_operand 0 "memory_displacement_operand" "")
373 (match_operand 2 "immediate_operand" "")))
374 (const_string "true")
376 (const_string "false")))
378 ;; Indicates if an FP operation has an integer source.
380 (define_attr "fp_int_src" "false,true"
381 (const_string "false"))
383 ;; Describe a user's asm statement.
384 (define_asm_attributes
385 [(set_attr "length" "128")
386 (set_attr "type" "multi")])
388 (include "pentium.md")
391 (include "athlon.md")
393 ;; Compare instructions.
395 ;; All compare insns have expanders that save the operands away without
396 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
397 ;; after the cmp) will actually emit the cmpM.
399 (define_expand "cmpdi"
401 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
402 (match_operand:DI 1 "x86_64_general_operand" "")))]
405 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
406 operands[0] = force_reg (DImode, operands[0]);
407 ix86_compare_op0 = operands[0];
408 ix86_compare_op1 = operands[1];
412 (define_expand "cmpsi"
414 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
415 (match_operand:SI 1 "general_operand" "")))]
418 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
419 operands[0] = force_reg (SImode, operands[0]);
420 ix86_compare_op0 = operands[0];
421 ix86_compare_op1 = operands[1];
425 (define_expand "cmphi"
427 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
428 (match_operand:HI 1 "general_operand" "")))]
431 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
432 operands[0] = force_reg (HImode, operands[0]);
433 ix86_compare_op0 = operands[0];
434 ix86_compare_op1 = operands[1];
438 (define_expand "cmpqi"
440 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
441 (match_operand:QI 1 "general_operand" "")))]
444 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
445 operands[0] = force_reg (QImode, operands[0]);
446 ix86_compare_op0 = operands[0];
447 ix86_compare_op1 = operands[1];
451 (define_insn "cmpdi_ccno_1_rex64"
453 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
454 (match_operand:DI 1 "const0_operand" "n,n")))]
455 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
457 test{q}\t{%0, %0|%0, %0}
458 cmp{q}\t{%1, %0|%0, %1}"
459 [(set_attr "type" "test,icmp")
460 (set_attr "length_immediate" "0,1")
461 (set_attr "mode" "DI")])
463 (define_insn "*cmpdi_minus_1_rex64"
465 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
466 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
468 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
469 "cmp{q}\t{%1, %0|%0, %1}"
470 [(set_attr "type" "icmp")
471 (set_attr "mode" "DI")])
473 (define_expand "cmpdi_1_rex64"
475 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
476 (match_operand:DI 1 "general_operand" "")))]
480 (define_insn "cmpdi_1_insn_rex64"
482 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
483 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
484 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
485 "cmp{q}\t{%1, %0|%0, %1}"
486 [(set_attr "type" "icmp")
487 (set_attr "mode" "DI")])
490 (define_insn "*cmpsi_ccno_1"
492 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
493 (match_operand:SI 1 "const0_operand" "n,n")))]
494 "ix86_match_ccmode (insn, CCNOmode)"
496 test{l}\t{%0, %0|%0, %0}
497 cmp{l}\t{%1, %0|%0, %1}"
498 [(set_attr "type" "test,icmp")
499 (set_attr "length_immediate" "0,1")
500 (set_attr "mode" "SI")])
502 (define_insn "*cmpsi_minus_1"
504 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
505 (match_operand:SI 1 "general_operand" "ri,mr"))
507 "ix86_match_ccmode (insn, CCGOCmode)"
508 "cmp{l}\t{%1, %0|%0, %1}"
509 [(set_attr "type" "icmp")
510 (set_attr "mode" "SI")])
512 (define_expand "cmpsi_1"
514 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
515 (match_operand:SI 1 "general_operand" "ri,mr")))]
519 (define_insn "*cmpsi_1_insn"
521 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
522 (match_operand:SI 1 "general_operand" "ri,mr")))]
523 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
524 && ix86_match_ccmode (insn, CCmode)"
525 "cmp{l}\t{%1, %0|%0, %1}"
526 [(set_attr "type" "icmp")
527 (set_attr "mode" "SI")])
529 (define_insn "*cmphi_ccno_1"
531 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
532 (match_operand:HI 1 "const0_operand" "n,n")))]
533 "ix86_match_ccmode (insn, CCNOmode)"
535 test{w}\t{%0, %0|%0, %0}
536 cmp{w}\t{%1, %0|%0, %1}"
537 [(set_attr "type" "test,icmp")
538 (set_attr "length_immediate" "0,1")
539 (set_attr "mode" "HI")])
541 (define_insn "*cmphi_minus_1"
543 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
544 (match_operand:HI 1 "general_operand" "ri,mr"))
546 "ix86_match_ccmode (insn, CCGOCmode)"
547 "cmp{w}\t{%1, %0|%0, %1}"
548 [(set_attr "type" "icmp")
549 (set_attr "mode" "HI")])
551 (define_insn "*cmphi_1"
553 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
554 (match_operand:HI 1 "general_operand" "ri,mr")))]
555 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
556 && ix86_match_ccmode (insn, CCmode)"
557 "cmp{w}\t{%1, %0|%0, %1}"
558 [(set_attr "type" "icmp")
559 (set_attr "mode" "HI")])
561 (define_insn "*cmpqi_ccno_1"
563 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
564 (match_operand:QI 1 "const0_operand" "n,n")))]
565 "ix86_match_ccmode (insn, CCNOmode)"
567 test{b}\t{%0, %0|%0, %0}
568 cmp{b}\t{$0, %0|%0, 0}"
569 [(set_attr "type" "test,icmp")
570 (set_attr "length_immediate" "0,1")
571 (set_attr "mode" "QI")])
573 (define_insn "*cmpqi_1"
575 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
576 (match_operand:QI 1 "general_operand" "qi,mq")))]
577 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
578 && ix86_match_ccmode (insn, CCmode)"
579 "cmp{b}\t{%1, %0|%0, %1}"
580 [(set_attr "type" "icmp")
581 (set_attr "mode" "QI")])
583 (define_insn "*cmpqi_minus_1"
585 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
586 (match_operand:QI 1 "general_operand" "qi,mq"))
588 "ix86_match_ccmode (insn, CCGOCmode)"
589 "cmp{b}\t{%1, %0|%0, %1}"
590 [(set_attr "type" "icmp")
591 (set_attr "mode" "QI")])
593 (define_insn "*cmpqi_ext_1"
596 (match_operand:QI 0 "general_operand" "Qm")
599 (match_operand 1 "ext_register_operand" "Q")
602 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
603 "cmp{b}\t{%h1, %0|%0, %h1}"
604 [(set_attr "type" "icmp")
605 (set_attr "mode" "QI")])
607 (define_insn "*cmpqi_ext_1_rex64"
610 (match_operand:QI 0 "register_operand" "Q")
613 (match_operand 1 "ext_register_operand" "Q")
616 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
617 "cmp{b}\t{%h1, %0|%0, %h1}"
618 [(set_attr "type" "icmp")
619 (set_attr "mode" "QI")])
621 (define_insn "*cmpqi_ext_2"
626 (match_operand 0 "ext_register_operand" "Q")
629 (match_operand:QI 1 "const0_operand" "n")))]
630 "ix86_match_ccmode (insn, CCNOmode)"
632 [(set_attr "type" "test")
633 (set_attr "length_immediate" "0")
634 (set_attr "mode" "QI")])
636 (define_expand "cmpqi_ext_3"
641 (match_operand 0 "ext_register_operand" "")
644 (match_operand:QI 1 "general_operand" "")))]
648 (define_insn "cmpqi_ext_3_insn"
653 (match_operand 0 "ext_register_operand" "Q")
656 (match_operand:QI 1 "general_operand" "Qmn")))]
657 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
658 "cmp{b}\t{%1, %h0|%h0, %1}"
659 [(set_attr "type" "icmp")
660 (set_attr "mode" "QI")])
662 (define_insn "cmpqi_ext_3_insn_rex64"
667 (match_operand 0 "ext_register_operand" "Q")
670 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
671 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
672 "cmp{b}\t{%1, %h0|%h0, %1}"
673 [(set_attr "type" "icmp")
674 (set_attr "mode" "QI")])
676 (define_insn "*cmpqi_ext_4"
681 (match_operand 0 "ext_register_operand" "Q")
686 (match_operand 1 "ext_register_operand" "Q")
689 "ix86_match_ccmode (insn, CCmode)"
690 "cmp{b}\t{%h1, %h0|%h0, %h1}"
691 [(set_attr "type" "icmp")
692 (set_attr "mode" "QI")])
694 ;; These implement float point compares.
695 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
696 ;; which would allow mix and match FP modes on the compares. Which is what
697 ;; the old patterns did, but with many more of them.
699 (define_expand "cmpxf"
701 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
702 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
703 "!TARGET_64BIT && TARGET_80387"
705 ix86_compare_op0 = operands[0];
706 ix86_compare_op1 = operands[1];
710 (define_expand "cmptf"
712 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
713 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
716 ix86_compare_op0 = operands[0];
717 ix86_compare_op1 = operands[1];
721 (define_expand "cmpdf"
723 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
724 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
725 "TARGET_80387 || TARGET_SSE2"
727 ix86_compare_op0 = operands[0];
728 ix86_compare_op1 = operands[1];
732 (define_expand "cmpsf"
734 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
735 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
736 "TARGET_80387 || TARGET_SSE"
738 ix86_compare_op0 = operands[0];
739 ix86_compare_op1 = operands[1];
743 ;; FP compares, step 1:
744 ;; Set the FP condition codes.
746 ;; CCFPmode compare with exceptions
747 ;; CCFPUmode compare with no exceptions
749 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
750 ;; and that fp moves clobber the condition codes, and that there is
751 ;; currently no way to describe this fact to reg-stack. So there are
752 ;; no splitters yet for this.
754 ;; %%% YIKES! This scheme does not retain a strong connection between
755 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
756 ;; work! Only allow tos/mem with tos in op 0.
758 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
759 ;; things aren't as bad as they sound...
761 (define_insn "*cmpfp_0"
762 [(set (match_operand:HI 0 "register_operand" "=a")
764 [(compare:CCFP (match_operand 1 "register_operand" "f")
765 (match_operand 2 "const0_operand" "X"))]
768 && FLOAT_MODE_P (GET_MODE (operands[1]))
769 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
771 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
772 return "ftst\;fnstsw\t%0\;fstp\t%y0";
774 return "ftst\;fnstsw\t%0";
776 [(set_attr "type" "multi")
778 (cond [(match_operand:SF 1 "" "")
780 (match_operand:DF 1 "" "")
783 (const_string "XF")))])
785 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
786 ;; used to manage the reg stack popping would not be preserved.
788 (define_insn "*cmpfp_2_sf"
791 (match_operand:SF 0 "register_operand" "f")
792 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
794 "* return output_fp_compare (insn, operands, 0, 0);"
795 [(set_attr "type" "fcmp")
796 (set_attr "mode" "SF")])
798 (define_insn "*cmpfp_2_sf_1"
799 [(set (match_operand:HI 0 "register_operand" "=a")
802 (match_operand:SF 1 "register_operand" "f")
803 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
806 "* return output_fp_compare (insn, operands, 2, 0);"
807 [(set_attr "type" "fcmp")
808 (set_attr "mode" "SF")])
810 (define_insn "*cmpfp_2_df"
813 (match_operand:DF 0 "register_operand" "f")
814 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
816 "* return output_fp_compare (insn, operands, 0, 0);"
817 [(set_attr "type" "fcmp")
818 (set_attr "mode" "DF")])
820 (define_insn "*cmpfp_2_df_1"
821 [(set (match_operand:HI 0 "register_operand" "=a")
824 (match_operand:DF 1 "register_operand" "f")
825 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
828 "* return output_fp_compare (insn, operands, 2, 0);"
829 [(set_attr "type" "multi")
830 (set_attr "mode" "DF")])
832 (define_insn "*cmpfp_2_xf"
835 (match_operand:XF 0 "register_operand" "f")
836 (match_operand:XF 1 "register_operand" "f")))]
837 "!TARGET_64BIT && TARGET_80387"
838 "* return output_fp_compare (insn, operands, 0, 0);"
839 [(set_attr "type" "fcmp")
840 (set_attr "mode" "XF")])
842 (define_insn "*cmpfp_2_tf"
845 (match_operand:TF 0 "register_operand" "f")
846 (match_operand:TF 1 "register_operand" "f")))]
848 "* return output_fp_compare (insn, operands, 0, 0);"
849 [(set_attr "type" "fcmp")
850 (set_attr "mode" "XF")])
852 (define_insn "*cmpfp_2_xf_1"
853 [(set (match_operand:HI 0 "register_operand" "=a")
856 (match_operand:XF 1 "register_operand" "f")
857 (match_operand:XF 2 "register_operand" "f"))]
859 "!TARGET_64BIT && TARGET_80387"
860 "* return output_fp_compare (insn, operands, 2, 0);"
861 [(set_attr "type" "multi")
862 (set_attr "mode" "XF")])
864 (define_insn "*cmpfp_2_tf_1"
865 [(set (match_operand:HI 0 "register_operand" "=a")
868 (match_operand:TF 1 "register_operand" "f")
869 (match_operand:TF 2 "register_operand" "f"))]
872 "* return output_fp_compare (insn, operands, 2, 0);"
873 [(set_attr "type" "multi")
874 (set_attr "mode" "XF")])
876 (define_insn "*cmpfp_2u"
879 (match_operand 0 "register_operand" "f")
880 (match_operand 1 "register_operand" "f")))]
882 && FLOAT_MODE_P (GET_MODE (operands[0]))
883 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
884 "* return output_fp_compare (insn, operands, 0, 1);"
885 [(set_attr "type" "fcmp")
887 (cond [(match_operand:SF 1 "" "")
889 (match_operand:DF 1 "" "")
892 (const_string "XF")))])
894 (define_insn "*cmpfp_2u_1"
895 [(set (match_operand:HI 0 "register_operand" "=a")
898 (match_operand 1 "register_operand" "f")
899 (match_operand 2 "register_operand" "f"))]
902 && FLOAT_MODE_P (GET_MODE (operands[1]))
903 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
904 "* return output_fp_compare (insn, operands, 2, 1);"
905 [(set_attr "type" "multi")
907 (cond [(match_operand:SF 1 "" "")
909 (match_operand:DF 1 "" "")
912 (const_string "XF")))])
914 ;; Patterns to match the SImode-in-memory ficom instructions.
916 ;; %%% Play games with accepting gp registers, as otherwise we have to
917 ;; force them to memory during rtl generation, which is no good. We
918 ;; can get rid of this once we teach reload to do memory input reloads
921 (define_insn "*ficom_1"
924 (match_operand 0 "register_operand" "f,f")
925 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
926 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
927 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
930 ;; Split the not-really-implemented gp register case into a
931 ;; push-op-pop sequence.
933 ;; %%% This is most efficient, but am I gonna get in trouble
934 ;; for separating cc0_setter and cc0_user?
939 (match_operand:SF 0 "register_operand" "")
940 (float (match_operand:SI 1 "register_operand" ""))))]
941 "0 && TARGET_80387 && reload_completed"
942 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
943 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
944 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
945 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
946 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
947 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
949 ;; FP compares, step 2
950 ;; Move the fpsw to ax.
952 (define_insn "*x86_fnstsw_1"
953 [(set (match_operand:HI 0 "register_operand" "=a")
954 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
957 [(set_attr "length" "2")
958 (set_attr "mode" "SI")
959 (set_attr "unit" "i387")
960 (set_attr "ppro_uops" "few")])
962 ;; FP compares, step 3
963 ;; Get ax into flags, general case.
965 (define_insn "x86_sahf_1"
967 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
970 [(set_attr "length" "1")
971 (set_attr "athlon_decode" "vector")
972 (set_attr "mode" "SI")
973 (set_attr "ppro_uops" "one")])
975 ;; Pentium Pro can do steps 1 through 3 in one go.
977 (define_insn "*cmpfp_i"
979 (compare:CCFP (match_operand 0 "register_operand" "f")
980 (match_operand 1 "register_operand" "f")))]
981 "TARGET_80387 && TARGET_CMOVE
982 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
983 && FLOAT_MODE_P (GET_MODE (operands[0]))
984 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
985 "* return output_fp_compare (insn, operands, 1, 0);"
986 [(set_attr "type" "fcmp")
988 (cond [(match_operand:SF 1 "" "")
990 (match_operand:DF 1 "" "")
993 (const_string "XF")))
994 (set_attr "athlon_decode" "vector")])
996 (define_insn "*cmpfp_i_sse"
998 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
999 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1001 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1002 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1003 "* return output_fp_compare (insn, operands, 1, 0);"
1004 [(set_attr "type" "fcmp,ssecomi")
1006 (if_then_else (match_operand:SF 1 "" "")
1008 (const_string "DF")))
1009 (set_attr "athlon_decode" "vector")])
1011 (define_insn "*cmpfp_i_sse_only"
1013 (compare:CCFP (match_operand 0 "register_operand" "x")
1014 (match_operand 1 "nonimmediate_operand" "xm")))]
1015 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1016 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1017 "* return output_fp_compare (insn, operands, 1, 0);"
1018 [(set_attr "type" "ssecomi")
1020 (if_then_else (match_operand:SF 1 "" "")
1022 (const_string "DF")))
1023 (set_attr "athlon_decode" "vector")])
1025 (define_insn "*cmpfp_iu"
1026 [(set (reg:CCFPU 17)
1027 (compare:CCFPU (match_operand 0 "register_operand" "f")
1028 (match_operand 1 "register_operand" "f")))]
1029 "TARGET_80387 && TARGET_CMOVE
1030 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1031 && FLOAT_MODE_P (GET_MODE (operands[0]))
1032 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1033 "* return output_fp_compare (insn, operands, 1, 1);"
1034 [(set_attr "type" "fcmp")
1036 (cond [(match_operand:SF 1 "" "")
1038 (match_operand:DF 1 "" "")
1041 (const_string "XF")))
1042 (set_attr "athlon_decode" "vector")])
1044 (define_insn "*cmpfp_iu_sse"
1045 [(set (reg:CCFPU 17)
1046 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1047 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1049 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1050 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1051 "* return output_fp_compare (insn, operands, 1, 1);"
1052 [(set_attr "type" "fcmp,ssecomi")
1054 (if_then_else (match_operand:SF 1 "" "")
1056 (const_string "DF")))
1057 (set_attr "athlon_decode" "vector")])
1059 (define_insn "*cmpfp_iu_sse_only"
1060 [(set (reg:CCFPU 17)
1061 (compare:CCFPU (match_operand 0 "register_operand" "x")
1062 (match_operand 1 "nonimmediate_operand" "xm")))]
1063 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1064 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1065 "* return output_fp_compare (insn, operands, 1, 1);"
1066 [(set_attr "type" "ssecomi")
1068 (if_then_else (match_operand:SF 1 "" "")
1070 (const_string "DF")))
1071 (set_attr "athlon_decode" "vector")])
1073 ;; Move instructions.
1075 ;; General case of fullword move.
1077 (define_expand "movsi"
1078 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1079 (match_operand:SI 1 "general_operand" ""))]
1081 "ix86_expand_move (SImode, operands); DONE;")
1083 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1086 ;; %%% We don't use a post-inc memory reference because x86 is not a
1087 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1088 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1089 ;; targets without our curiosities, and it is just as easy to represent
1090 ;; this differently.
1092 (define_insn "*pushsi2"
1093 [(set (match_operand:SI 0 "push_operand" "=<")
1094 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1097 [(set_attr "type" "push")
1098 (set_attr "mode" "SI")])
1100 ;; For 64BIT abi we always round up to 8 bytes.
1101 (define_insn "*pushsi2_rex64"
1102 [(set (match_operand:SI 0 "push_operand" "=X")
1103 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1106 [(set_attr "type" "push")
1107 (set_attr "mode" "SI")])
1109 (define_insn "*pushsi2_prologue"
1110 [(set (match_operand:SI 0 "push_operand" "=<")
1111 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1112 (clobber (mem:BLK (scratch)))]
1115 [(set_attr "type" "push")
1116 (set_attr "mode" "SI")])
1118 (define_insn "*popsi1_epilogue"
1119 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1120 (mem:SI (reg:SI 7)))
1122 (plus:SI (reg:SI 7) (const_int 4)))
1123 (clobber (mem:BLK (scratch)))]
1126 [(set_attr "type" "pop")
1127 (set_attr "mode" "SI")])
1129 (define_insn "popsi1"
1130 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1131 (mem:SI (reg:SI 7)))
1133 (plus:SI (reg:SI 7) (const_int 4)))]
1136 [(set_attr "type" "pop")
1137 (set_attr "mode" "SI")])
1139 (define_insn "*movsi_xor"
1140 [(set (match_operand:SI 0 "register_operand" "=r")
1141 (match_operand:SI 1 "const0_operand" "i"))
1142 (clobber (reg:CC 17))]
1143 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1144 "xor{l}\t{%0, %0|%0, %0}"
1145 [(set_attr "type" "alu1")
1146 (set_attr "mode" "SI")
1147 (set_attr "length_immediate" "0")])
1149 (define_insn "*movsi_or"
1150 [(set (match_operand:SI 0 "register_operand" "=r")
1151 (match_operand:SI 1 "immediate_operand" "i"))
1152 (clobber (reg:CC 17))]
1153 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1154 && INTVAL (operands[1]) == -1
1155 && (TARGET_PENTIUM || optimize_size)"
1157 operands[1] = constm1_rtx;
1158 return "or{l}\t{%1, %0|%0, %1}";
1160 [(set_attr "type" "alu1")
1161 (set_attr "mode" "SI")
1162 (set_attr "length_immediate" "1")])
1164 (define_insn "*movsi_1"
1165 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1166 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1167 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1168 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1170 switch (get_attr_type (insn))
1173 if (get_attr_mode (insn) == MODE_TI)
1174 return "movdqa\t{%1, %0|%0, %1}";
1175 return "movd\t{%1, %0|%0, %1}";
1178 if (get_attr_mode (insn) == MODE_DI)
1179 return "movq\t{%1, %0|%0, %1}";
1180 return "movd\t{%1, %0|%0, %1}";
1183 return "lea{l}\t{%1, %0|%0, %1}";
1186 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1188 return "mov{l}\t{%1, %0|%0, %1}";
1192 (cond [(eq_attr "alternative" "2,3,4")
1193 (const_string "mmxmov")
1194 (eq_attr "alternative" "5,6,7")
1195 (const_string "ssemov")
1196 (and (ne (symbol_ref "flag_pic") (const_int 0))
1197 (match_operand:SI 1 "symbolic_operand" ""))
1198 (const_string "lea")
1200 (const_string "imov")))
1201 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1203 (define_insn "*movsi_1_nointernunit"
1204 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1205 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1206 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1207 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1209 switch (get_attr_type (insn))
1212 if (get_attr_mode (insn) == MODE_TI)
1213 return "movdqa\t{%1, %0|%0, %1}";
1214 return "movd\t{%1, %0|%0, %1}";
1217 if (get_attr_mode (insn) == MODE_DI)
1218 return "movq\t{%1, %0|%0, %1}";
1219 return "movd\t{%1, %0|%0, %1}";
1222 return "lea{l}\t{%1, %0|%0, %1}";
1225 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1227 return "mov{l}\t{%1, %0|%0, %1}";
1231 (cond [(eq_attr "alternative" "2,3,4")
1232 (const_string "mmxmov")
1233 (eq_attr "alternative" "5,6,7")
1234 (const_string "ssemov")
1235 (and (ne (symbol_ref "flag_pic") (const_int 0))
1236 (match_operand:SI 1 "symbolic_operand" ""))
1237 (const_string "lea")
1239 (const_string "imov")))
1240 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1242 ;; Stores and loads of ax to arbitrary constant address.
1243 ;; We fake an second form of instruction to force reload to load address
1244 ;; into register when rax is not available
1245 (define_insn "*movabssi_1_rex64"
1246 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1247 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1250 movabs{l}\t{%1, %P0|%P0, %1}
1251 mov{l}\t{%1, %a0|%a0, %1}
1252 movabs{l}\t{%1, %a0|%a0, %1}"
1253 [(set_attr "type" "imov")
1254 (set_attr "modrm" "0,*,*")
1255 (set_attr "length_address" "8,0,0")
1256 (set_attr "length_immediate" "0,*,*")
1257 (set_attr "memory" "store")
1258 (set_attr "mode" "SI")])
1260 (define_insn "*movabssi_2_rex64"
1261 [(set (match_operand:SI 0 "register_operand" "=a,r")
1262 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1265 movabs{l}\t{%P1, %0|%0, %P1}
1266 mov{l}\t{%a1, %0|%0, %a1}"
1267 [(set_attr "type" "imov")
1268 (set_attr "modrm" "0,*")
1269 (set_attr "length_address" "8,0")
1270 (set_attr "length_immediate" "0")
1271 (set_attr "memory" "load")
1272 (set_attr "mode" "SI")])
1274 (define_insn "*swapsi"
1275 [(set (match_operand:SI 0 "register_operand" "+r")
1276 (match_operand:SI 1 "register_operand" "+r"))
1281 [(set_attr "type" "imov")
1282 (set_attr "pent_pair" "np")
1283 (set_attr "athlon_decode" "vector")
1284 (set_attr "mode" "SI")
1285 (set_attr "modrm" "0")
1286 (set_attr "ppro_uops" "few")])
1288 (define_expand "movhi"
1289 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1290 (match_operand:HI 1 "general_operand" ""))]
1292 "ix86_expand_move (HImode, operands); DONE;")
1294 (define_insn "*pushhi2"
1295 [(set (match_operand:HI 0 "push_operand" "=<,<")
1296 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1299 push{w}\t{|WORD PTR }%1
1301 [(set_attr "type" "push")
1302 (set_attr "mode" "HI")])
1304 ;; For 64BIT abi we always round up to 8 bytes.
1305 (define_insn "*pushhi2_rex64"
1306 [(set (match_operand:HI 0 "push_operand" "=X")
1307 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1310 [(set_attr "type" "push")
1311 (set_attr "mode" "QI")])
1313 (define_insn "*movhi_1"
1314 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1315 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1316 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1318 switch (get_attr_type (insn))
1321 /* movzwl is faster than movw on p2 due to partial word stalls,
1322 though not as fast as an aligned movl. */
1323 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1325 if (get_attr_mode (insn) == MODE_SI)
1326 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1328 return "mov{w}\t{%1, %0|%0, %1}";
1332 (cond [(and (eq_attr "alternative" "0")
1333 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1335 (eq (symbol_ref "TARGET_HIMODE_MATH")
1337 (const_string "imov")
1338 (and (eq_attr "alternative" "1,2")
1339 (match_operand:HI 1 "aligned_operand" ""))
1340 (const_string "imov")
1341 (and (ne (symbol_ref "TARGET_MOVX")
1343 (eq_attr "alternative" "0,2"))
1344 (const_string "imovx")
1346 (const_string "imov")))
1348 (cond [(eq_attr "type" "imovx")
1350 (and (eq_attr "alternative" "1,2")
1351 (match_operand:HI 1 "aligned_operand" ""))
1353 (and (eq_attr "alternative" "0")
1354 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1356 (eq (symbol_ref "TARGET_HIMODE_MATH")
1360 (const_string "HI")))])
1362 ;; Stores and loads of ax to arbitrary constant address.
1363 ;; We fake an second form of instruction to force reload to load address
1364 ;; into register when rax is not available
1365 (define_insn "*movabshi_1_rex64"
1366 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1367 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1370 movabs{w}\t{%1, %P0|%P0, %1}
1371 mov{w}\t{%1, %a0|%a0, %1}
1372 movabs{w}\t{%1, %a0|%a0, %1}"
1373 [(set_attr "type" "imov")
1374 (set_attr "modrm" "0,*,*")
1375 (set_attr "length_address" "8,0,0")
1376 (set_attr "length_immediate" "0,*,*")
1377 (set_attr "memory" "store")
1378 (set_attr "mode" "HI")])
1380 (define_insn "*movabshi_2_rex64"
1381 [(set (match_operand:HI 0 "register_operand" "=a,r")
1382 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1385 movabs{w}\t{%P1, %0|%0, %P1}
1386 mov{w}\t{%a1, %0|%0, %a1}"
1387 [(set_attr "type" "imov")
1388 (set_attr "modrm" "0,*")
1389 (set_attr "length_address" "8,0")
1390 (set_attr "length_immediate" "0")
1391 (set_attr "memory" "load")
1392 (set_attr "mode" "HI")])
1394 (define_insn "*swaphi_1"
1395 [(set (match_operand:HI 0 "register_operand" "+r")
1396 (match_operand:HI 1 "register_operand" "+r"))
1399 "TARGET_PARTIAL_REG_STALL"
1401 [(set_attr "type" "imov")
1402 (set_attr "pent_pair" "np")
1403 (set_attr "mode" "HI")
1404 (set_attr "modrm" "0")
1405 (set_attr "ppro_uops" "few")])
1407 (define_insn "*swaphi_2"
1408 [(set (match_operand:HI 0 "register_operand" "+r")
1409 (match_operand:HI 1 "register_operand" "+r"))
1412 "! TARGET_PARTIAL_REG_STALL"
1414 [(set_attr "type" "imov")
1415 (set_attr "pent_pair" "np")
1416 (set_attr "mode" "SI")
1417 (set_attr "modrm" "0")
1418 (set_attr "ppro_uops" "few")])
1420 (define_expand "movstricthi"
1421 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1422 (match_operand:HI 1 "general_operand" ""))]
1423 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1425 /* Don't generate memory->memory moves, go through a register */
1426 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1427 operands[1] = force_reg (HImode, operands[1]);
1430 (define_insn "*movstricthi_1"
1431 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1432 (match_operand:HI 1 "general_operand" "rn,m"))]
1433 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1434 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1435 "mov{w}\t{%1, %0|%0, %1}"
1436 [(set_attr "type" "imov")
1437 (set_attr "mode" "HI")])
1439 (define_insn "*movstricthi_xor"
1440 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1441 (match_operand:HI 1 "const0_operand" "i"))
1442 (clobber (reg:CC 17))]
1444 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1445 "xor{w}\t{%0, %0|%0, %0}"
1446 [(set_attr "type" "alu1")
1447 (set_attr "mode" "HI")
1448 (set_attr "length_immediate" "0")])
1450 (define_expand "movqi"
1451 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1452 (match_operand:QI 1 "general_operand" ""))]
1454 "ix86_expand_move (QImode, operands); DONE;")
1456 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1457 ;; "push a byte". But actually we use pushw, which has the effect
1458 ;; of rounding the amount pushed up to a halfword.
1460 (define_insn "*pushqi2"
1461 [(set (match_operand:QI 0 "push_operand" "=X,X")
1462 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1465 push{w}\t{|word ptr }%1
1467 [(set_attr "type" "push")
1468 (set_attr "mode" "HI")])
1470 ;; For 64BIT abi we always round up to 8 bytes.
1471 (define_insn "*pushqi2_rex64"
1472 [(set (match_operand:QI 0 "push_operand" "=X")
1473 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1476 [(set_attr "type" "push")
1477 (set_attr "mode" "QI")])
1479 ;; Situation is quite tricky about when to choose full sized (SImode) move
1480 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1481 ;; partial register dependency machines (such as AMD Athlon), where QImode
1482 ;; moves issue extra dependency and for partial register stalls machines
1483 ;; that don't use QImode patterns (and QImode move cause stall on the next
1486 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1487 ;; register stall machines with, where we use QImode instructions, since
1488 ;; partial register stall can be caused there. Then we use movzx.
1489 (define_insn "*movqi_1"
1490 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1491 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1492 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1494 switch (get_attr_type (insn))
1497 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1499 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1501 if (get_attr_mode (insn) == MODE_SI)
1502 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1504 return "mov{b}\t{%1, %0|%0, %1}";
1508 (cond [(and (eq_attr "alternative" "3")
1509 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1511 (eq (symbol_ref "TARGET_QIMODE_MATH")
1513 (const_string "imov")
1514 (eq_attr "alternative" "3,5")
1515 (const_string "imovx")
1516 (and (ne (symbol_ref "TARGET_MOVX")
1518 (eq_attr "alternative" "2"))
1519 (const_string "imovx")
1521 (const_string "imov")))
1523 (cond [(eq_attr "alternative" "3,4,5")
1525 (eq_attr "alternative" "6")
1527 (eq_attr "type" "imovx")
1529 (and (eq_attr "type" "imov")
1530 (and (eq_attr "alternative" "0,1,2")
1531 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1534 ;; Avoid partial register stalls when not using QImode arithmetic
1535 (and (eq_attr "type" "imov")
1536 (and (eq_attr "alternative" "0,1,2")
1537 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1539 (eq (symbol_ref "TARGET_QIMODE_MATH")
1543 (const_string "QI")))])
1545 (define_expand "reload_outqi"
1546 [(parallel [(match_operand:QI 0 "" "=m")
1547 (match_operand:QI 1 "register_operand" "r")
1548 (match_operand:QI 2 "register_operand" "=&q")])]
1552 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1554 if (reg_overlap_mentioned_p (op2, op0))
1556 if (! q_regs_operand (op1, QImode))
1558 emit_insn (gen_movqi (op2, op1));
1561 emit_insn (gen_movqi (op0, op1));
1565 (define_insn "*swapqi"
1566 [(set (match_operand:QI 0 "register_operand" "+r")
1567 (match_operand:QI 1 "register_operand" "+r"))
1572 [(set_attr "type" "imov")
1573 (set_attr "pent_pair" "np")
1574 (set_attr "mode" "QI")
1575 (set_attr "modrm" "0")
1576 (set_attr "ppro_uops" "few")])
1578 (define_expand "movstrictqi"
1579 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1580 (match_operand:QI 1 "general_operand" ""))]
1581 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1583 /* Don't generate memory->memory moves, go through a register. */
1584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1585 operands[1] = force_reg (QImode, operands[1]);
1588 (define_insn "*movstrictqi_1"
1589 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1590 (match_operand:QI 1 "general_operand" "*qn,m"))]
1591 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1592 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1593 "mov{b}\t{%1, %0|%0, %1}"
1594 [(set_attr "type" "imov")
1595 (set_attr "mode" "QI")])
1597 (define_insn "*movstrictqi_xor"
1598 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1599 (match_operand:QI 1 "const0_operand" "i"))
1600 (clobber (reg:CC 17))]
1601 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1602 "xor{b}\t{%0, %0|%0, %0}"
1603 [(set_attr "type" "alu1")
1604 (set_attr "mode" "QI")
1605 (set_attr "length_immediate" "0")])
1607 (define_insn "*movsi_extv_1"
1608 [(set (match_operand:SI 0 "register_operand" "=R")
1609 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1613 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1614 [(set_attr "type" "imovx")
1615 (set_attr "mode" "SI")])
1617 (define_insn "*movhi_extv_1"
1618 [(set (match_operand:HI 0 "register_operand" "=R")
1619 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1623 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1624 [(set_attr "type" "imovx")
1625 (set_attr "mode" "SI")])
1627 (define_insn "*movqi_extv_1"
1628 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1629 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1634 switch (get_attr_type (insn))
1637 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1639 return "mov{b}\t{%h1, %0|%0, %h1}";
1643 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1644 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1645 (ne (symbol_ref "TARGET_MOVX")
1647 (const_string "imovx")
1648 (const_string "imov")))
1650 (if_then_else (eq_attr "type" "imovx")
1652 (const_string "QI")))])
1654 (define_insn "*movqi_extv_1_rex64"
1655 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1656 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1661 switch (get_attr_type (insn))
1664 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1666 return "mov{b}\t{%h1, %0|%0, %h1}";
1670 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1671 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1672 (ne (symbol_ref "TARGET_MOVX")
1674 (const_string "imovx")
1675 (const_string "imov")))
1677 (if_then_else (eq_attr "type" "imovx")
1679 (const_string "QI")))])
1681 ;; Stores and loads of ax to arbitrary constant address.
1682 ;; We fake an second form of instruction to force reload to load address
1683 ;; into register when rax is not available
1684 (define_insn "*movabsqi_1_rex64"
1685 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1686 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1689 movabs{b}\t{%1, %P0|%P0, %1}
1690 mov{b}\t{%1, %a0|%a0, %1}
1691 movabs{b}\t{%1, %a0|%a0, %1}"
1692 [(set_attr "type" "imov")
1693 (set_attr "modrm" "0,*,*")
1694 (set_attr "length_address" "8,0,0")
1695 (set_attr "length_immediate" "0,*,*")
1696 (set_attr "memory" "store")
1697 (set_attr "mode" "QI")])
1699 (define_insn "*movabsqi_2_rex64"
1700 [(set (match_operand:QI 0 "register_operand" "=a,r")
1701 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1704 movabs{b}\t{%P1, %0|%0, %P1}
1705 mov{b}\t{%a1, %0|%0, %a1}"
1706 [(set_attr "type" "imov")
1707 (set_attr "modrm" "0,*")
1708 (set_attr "length_address" "8,0")
1709 (set_attr "length_immediate" "0")
1710 (set_attr "memory" "load")
1711 (set_attr "mode" "QI")])
1713 (define_insn "*movsi_extzv_1"
1714 [(set (match_operand:SI 0 "register_operand" "=R")
1715 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1719 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1720 [(set_attr "type" "imovx")
1721 (set_attr "mode" "SI")])
1723 (define_insn "*movqi_extzv_2"
1724 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1725 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1730 switch (get_attr_type (insn))
1733 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1735 return "mov{b}\t{%h1, %0|%0, %h1}";
1739 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1740 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1741 (ne (symbol_ref "TARGET_MOVX")
1743 (const_string "imovx")
1744 (const_string "imov")))
1746 (if_then_else (eq_attr "type" "imovx")
1748 (const_string "QI")))])
1750 (define_insn "*movqi_extzv_2_rex64"
1751 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1752 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1757 switch (get_attr_type (insn))
1760 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1762 return "mov{b}\t{%h1, %0|%0, %h1}";
1766 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1767 (ne (symbol_ref "TARGET_MOVX")
1769 (const_string "imovx")
1770 (const_string "imov")))
1772 (if_then_else (eq_attr "type" "imovx")
1774 (const_string "QI")))])
1776 (define_insn "movsi_insv_1"
1777 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1780 (match_operand:SI 1 "general_operand" "Qmn"))]
1782 "mov{b}\t{%b1, %h0|%h0, %b1}"
1783 [(set_attr "type" "imov")
1784 (set_attr "mode" "QI")])
1786 (define_insn "*movsi_insv_1_rex64"
1787 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1790 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1792 "mov{b}\t{%b1, %h0|%h0, %b1}"
1793 [(set_attr "type" "imov")
1794 (set_attr "mode" "QI")])
1796 (define_insn "*movqi_insv_2"
1797 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1800 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1804 "mov{b}\t{%h1, %h0|%h0, %h1}"
1805 [(set_attr "type" "imov")
1806 (set_attr "mode" "QI")])
1808 (define_expand "movdi"
1809 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1810 (match_operand:DI 1 "general_operand" ""))]
1812 "ix86_expand_move (DImode, operands); DONE;")
1814 (define_insn "*pushdi"
1815 [(set (match_operand:DI 0 "push_operand" "=<")
1816 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1820 (define_insn "pushdi2_rex64"
1821 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1822 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1827 [(set_attr "type" "push,multi")
1828 (set_attr "mode" "DI")])
1830 ;; Convert impossible pushes of immediate to existing instructions.
1831 ;; First try to get scratch register and go through it. In case this
1832 ;; fails, push sign extended lower part first and then overwrite
1833 ;; upper part by 32bit move.
1835 [(match_scratch:DI 2 "r")
1836 (set (match_operand:DI 0 "push_operand" "")
1837 (match_operand:DI 1 "immediate_operand" ""))]
1838 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1839 && !x86_64_immediate_operand (operands[1], DImode)"
1840 [(set (match_dup 2) (match_dup 1))
1841 (set (match_dup 0) (match_dup 2))]
1844 ;; We need to define this as both peepholer and splitter for case
1845 ;; peephole2 pass is not run.
1847 [(set (match_operand:DI 0 "push_operand" "")
1848 (match_operand:DI 1 "immediate_operand" ""))]
1849 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1850 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1851 [(set (match_dup 0) (match_dup 1))
1852 (set (match_dup 2) (match_dup 3))]
1853 "split_di (operands + 1, 1, operands + 2, operands + 3);
1854 operands[1] = gen_lowpart (DImode, operands[2]);
1855 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1860 [(set (match_operand:DI 0 "push_operand" "")
1861 (match_operand:DI 1 "immediate_operand" ""))]
1862 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1863 && !symbolic_operand (operands[1], DImode)
1864 && !x86_64_immediate_operand (operands[1], DImode)"
1865 [(set (match_dup 0) (match_dup 1))
1866 (set (match_dup 2) (match_dup 3))]
1867 "split_di (operands + 1, 1, operands + 2, operands + 3);
1868 operands[1] = gen_lowpart (DImode, operands[2]);
1869 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1873 (define_insn "*pushdi2_prologue_rex64"
1874 [(set (match_operand:DI 0 "push_operand" "=<")
1875 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1876 (clobber (mem:BLK (scratch)))]
1879 [(set_attr "type" "push")
1880 (set_attr "mode" "DI")])
1882 (define_insn "*popdi1_epilogue_rex64"
1883 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1884 (mem:DI (reg:DI 7)))
1886 (plus:DI (reg:DI 7) (const_int 8)))
1887 (clobber (mem:BLK (scratch)))]
1890 [(set_attr "type" "pop")
1891 (set_attr "mode" "DI")])
1893 (define_insn "popdi1"
1894 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1895 (mem:DI (reg:DI 7)))
1897 (plus:DI (reg:DI 7) (const_int 8)))]
1900 [(set_attr "type" "pop")
1901 (set_attr "mode" "DI")])
1903 (define_insn "*movdi_xor_rex64"
1904 [(set (match_operand:DI 0 "register_operand" "=r")
1905 (match_operand:DI 1 "const0_operand" "i"))
1906 (clobber (reg:CC 17))]
1907 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1908 && reload_completed"
1909 "xor{l}\t{%k0, %k0|%k0, %k0}"
1910 [(set_attr "type" "alu1")
1911 (set_attr "mode" "SI")
1912 (set_attr "length_immediate" "0")])
1914 (define_insn "*movdi_or_rex64"
1915 [(set (match_operand:DI 0 "register_operand" "=r")
1916 (match_operand:DI 1 "const_int_operand" "i"))
1917 (clobber (reg:CC 17))]
1918 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1920 && GET_CODE (operands[1]) == CONST_INT
1921 && INTVAL (operands[1]) == -1"
1923 operands[1] = constm1_rtx;
1924 return "or{q}\t{%1, %0|%0, %1}";
1926 [(set_attr "type" "alu1")
1927 (set_attr "mode" "DI")
1928 (set_attr "length_immediate" "1")])
1930 (define_insn "*movdi_2"
1931 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1932 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1934 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1938 movq\t{%1, %0|%0, %1}
1939 movq\t{%1, %0|%0, %1}
1940 movq\t{%1, %0|%0, %1}
1941 movdqa\t{%1, %0|%0, %1}
1942 movq\t{%1, %0|%0, %1}"
1943 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1944 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1947 [(set (match_operand:DI 0 "push_operand" "")
1948 (match_operand:DI 1 "general_operand" ""))]
1949 "!TARGET_64BIT && reload_completed
1950 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1952 "ix86_split_long_move (operands); DONE;")
1954 ;; %%% This multiword shite has got to go.
1956 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1957 (match_operand:DI 1 "general_operand" ""))]
1958 "!TARGET_64BIT && reload_completed
1959 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1960 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1962 "ix86_split_long_move (operands); DONE;")
1964 (define_insn "*movdi_1_rex64"
1965 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1966 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1968 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1969 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1971 switch (get_attr_type (insn))
1974 if (get_attr_mode (insn) == MODE_TI)
1975 return "movdqa\t{%1, %0|%0, %1}";
1978 /* Moves from and into integer register is done using movd opcode with
1980 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1981 return "movd\t{%1, %0|%0, %1}";
1982 return "movq\t{%1, %0|%0, %1}";
1986 return "lea{q}\t{%a1, %0|%0, %a1}";
1988 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1990 if (get_attr_mode (insn) == MODE_SI)
1991 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1992 else if (which_alternative == 2)
1993 return "movabs{q}\t{%1, %0|%0, %1}";
1995 return "mov{q}\t{%1, %0|%0, %1}";
1999 (cond [(eq_attr "alternative" "5,6,7")
2000 (const_string "mmxmov")
2001 (eq_attr "alternative" "8,9,10")
2002 (const_string "ssemov")
2003 (eq_attr "alternative" "4")
2004 (const_string "multi")
2005 (and (ne (symbol_ref "flag_pic") (const_int 0))
2006 (match_operand:DI 1 "symbolic_operand" ""))
2007 (const_string "lea")
2009 (const_string "imov")))
2010 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2011 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2012 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2014 (define_insn "*movdi_1_rex64_nointerunit"
2015 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2016 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2018 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2019 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2021 switch (get_attr_type (insn))
2024 if (get_attr_mode (insn) == MODE_TI)
2025 return "movdqa\t{%1, %0|%0, %1}";
2028 return "movq\t{%1, %0|%0, %1}";
2032 return "lea{q}\t{%a1, %0|%0, %a1}";
2034 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2036 if (get_attr_mode (insn) == MODE_SI)
2037 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2038 else if (which_alternative == 2)
2039 return "movabs{q}\t{%1, %0|%0, %1}";
2041 return "mov{q}\t{%1, %0|%0, %1}";
2045 (cond [(eq_attr "alternative" "5,6,7")
2046 (const_string "mmxmov")
2047 (eq_attr "alternative" "8,9,10")
2048 (const_string "ssemov")
2049 (eq_attr "alternative" "4")
2050 (const_string "multi")
2051 (and (ne (symbol_ref "flag_pic") (const_int 0))
2052 (match_operand:DI 1 "symbolic_operand" ""))
2053 (const_string "lea")
2055 (const_string "imov")))
2056 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2057 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2058 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2060 ;; Stores and loads of ax to arbitrary constant address.
2061 ;; We fake an second form of instruction to force reload to load address
2062 ;; into register when rax is not available
2063 (define_insn "*movabsdi_1_rex64"
2064 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2065 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2068 movabs{q}\t{%1, %P0|%P0, %1}
2069 mov{q}\t{%1, %a0|%a0, %1}
2070 movabs{q}\t{%1, %a0|%a0, %1}"
2071 [(set_attr "type" "imov")
2072 (set_attr "modrm" "0,*,*")
2073 (set_attr "length_address" "8,0,0")
2074 (set_attr "length_immediate" "0,*,*")
2075 (set_attr "memory" "store")
2076 (set_attr "mode" "DI")])
2078 (define_insn "*movabsdi_2_rex64"
2079 [(set (match_operand:DI 0 "register_operand" "=a,r")
2080 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2083 movabs{q}\t{%P1, %0|%0, %P1}
2084 mov{q}\t{%a1, %0|%0, %a1}"
2085 [(set_attr "type" "imov")
2086 (set_attr "modrm" "0,*")
2087 (set_attr "length_address" "8,0")
2088 (set_attr "length_immediate" "0")
2089 (set_attr "memory" "load")
2090 (set_attr "mode" "DI")])
2092 ;; Convert impossible stores of immediate to existing instructions.
2093 ;; First try to get scratch register and go through it. In case this
2094 ;; fails, move by 32bit parts.
2096 [(match_scratch:DI 2 "r")
2097 (set (match_operand:DI 0 "memory_operand" "")
2098 (match_operand:DI 1 "immediate_operand" ""))]
2099 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2100 && !x86_64_immediate_operand (operands[1], DImode)"
2101 [(set (match_dup 2) (match_dup 1))
2102 (set (match_dup 0) (match_dup 2))]
2105 ;; We need to define this as both peepholer and splitter for case
2106 ;; peephole2 pass is not run.
2108 [(set (match_operand:DI 0 "memory_operand" "")
2109 (match_operand:DI 1 "immediate_operand" ""))]
2110 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2111 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2112 [(set (match_dup 2) (match_dup 3))
2113 (set (match_dup 4) (match_dup 5))]
2114 "split_di (operands, 2, operands + 2, operands + 4);")
2117 [(set (match_operand:DI 0 "memory_operand" "")
2118 (match_operand:DI 1 "immediate_operand" ""))]
2119 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2120 && !symbolic_operand (operands[1], DImode)
2121 && !x86_64_immediate_operand (operands[1], DImode)"
2122 [(set (match_dup 2) (match_dup 3))
2123 (set (match_dup 4) (match_dup 5))]
2124 "split_di (operands, 2, operands + 2, operands + 4);")
2126 (define_insn "*swapdi_rex64"
2127 [(set (match_operand:DI 0 "register_operand" "+r")
2128 (match_operand:DI 1 "register_operand" "+r"))
2133 [(set_attr "type" "imov")
2134 (set_attr "pent_pair" "np")
2135 (set_attr "athlon_decode" "vector")
2136 (set_attr "mode" "DI")
2137 (set_attr "modrm" "0")
2138 (set_attr "ppro_uops" "few")])
2141 (define_expand "movsf"
2142 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2143 (match_operand:SF 1 "general_operand" ""))]
2145 "ix86_expand_move (SFmode, operands); DONE;")
2147 (define_insn "*pushsf"
2148 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2149 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2152 switch (which_alternative)
2155 return "push{l}\t%1";
2158 /* This insn should be already splitted before reg-stack. */
2162 [(set_attr "type" "multi,push,multi")
2163 (set_attr "mode" "SF,SI,SF")])
2165 (define_insn "*pushsf_rex64"
2166 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2167 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2170 switch (which_alternative)
2173 return "push{q}\t%q1";
2176 /* This insn should be already splitted before reg-stack. */
2180 [(set_attr "type" "multi,push,multi")
2181 (set_attr "mode" "SF,DI,SF")])
2184 [(set (match_operand:SF 0 "push_operand" "")
2185 (match_operand:SF 1 "memory_operand" ""))]
2187 && GET_CODE (operands[1]) == MEM
2188 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2189 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2192 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2195 ;; %%% Kill this when call knows how to work this out.
2197 [(set (match_operand:SF 0 "push_operand" "")
2198 (match_operand:SF 1 "any_fp_register_operand" ""))]
2200 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2201 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2204 [(set (match_operand:SF 0 "push_operand" "")
2205 (match_operand:SF 1 "any_fp_register_operand" ""))]
2207 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2208 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2210 (define_insn "*movsf_1"
2211 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2212 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2213 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2214 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2215 && (reload_in_progress || reload_completed
2216 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2217 || GET_CODE (operands[1]) != CONST_DOUBLE
2218 || memory_operand (operands[0], SFmode))"
2220 switch (which_alternative)
2223 if (REG_P (operands[1])
2224 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2226 else if (STACK_TOP_P (operands[0]))
2227 return "fld%z1\t%y1";
2232 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2233 return "fstp%z0\t%y0";
2235 return "fst%z0\t%y0";
2238 return standard_80387_constant_opcode (operands[1]);
2242 return "mov{l}\t{%1, %0|%0, %1}";
2244 if (get_attr_mode (insn) == MODE_TI)
2245 return "pxor\t%0, %0";
2247 return "xorps\t%0, %0";
2249 if (get_attr_mode (insn) == MODE_V4SF)
2250 return "movaps\t{%1, %0|%0, %1}";
2252 return "movss\t{%1, %0|%0, %1}";
2255 return "movss\t{%1, %0|%0, %1}";
2259 return "movd\t{%1, %0|%0, %1}";
2262 return "movq\t{%1, %0|%0, %1}";
2268 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2270 (cond [(eq_attr "alternative" "3,4,9,10")
2272 (eq_attr "alternative" "5")
2274 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2276 (ne (symbol_ref "TARGET_SSE2")
2278 (eq (symbol_ref "optimize_size")
2281 (const_string "V4SF"))
2282 /* For architectures resolving dependencies on
2283 whole SSE registers use APS move to break dependency
2284 chains, otherwise use short move to avoid extra work.
2286 Do the same for architectures resolving dependencies on
2287 the parts. While in DF mode it is better to always handle
2288 just register parts, the SF mode is different due to lack
2289 of instructions to load just part of the register. It is
2290 better to maintain the whole registers in single format
2291 to avoid problems on using packed logical operations. */
2292 (eq_attr "alternative" "6")
2294 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2296 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2298 (const_string "V4SF")
2299 (const_string "SF"))
2300 (eq_attr "alternative" "11")
2301 (const_string "DI")]
2302 (const_string "SF")))])
2304 (define_insn "*movsf_1_nointerunit"
2305 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2306 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2307 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2308 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2309 && (reload_in_progress || reload_completed
2310 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2311 || GET_CODE (operands[1]) != CONST_DOUBLE
2312 || memory_operand (operands[0], SFmode))"
2314 switch (which_alternative)
2317 if (REG_P (operands[1])
2318 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2320 if (REGNO (operands[0]) == FIRST_STACK_REG
2321 && TARGET_USE_FFREEP)
2322 return "ffreep\t%y0";
2325 else if (STACK_TOP_P (operands[0]))
2326 return "fld%z1\t%y1";
2331 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2332 return "fstp%z0\t%y0";
2334 return "fst%z0\t%y0";
2337 return standard_80387_constant_opcode (operands[1]);
2341 return "mov{l}\t{%1, %0|%0, %1}";
2343 if (get_attr_mode (insn) == MODE_TI)
2344 return "pxor\t%0, %0";
2346 return "xorps\t%0, %0";
2348 if (get_attr_mode (insn) == MODE_V4SF)
2349 return "movaps\t{%1, %0|%0, %1}";
2351 return "movss\t{%1, %0|%0, %1}";
2354 return "movss\t{%1, %0|%0, %1}";
2358 return "movd\t{%1, %0|%0, %1}";
2361 return "movq\t{%1, %0|%0, %1}";
2367 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2369 (cond [(eq_attr "alternative" "3,4,9,10")
2371 (eq_attr "alternative" "5")
2373 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2375 (ne (symbol_ref "TARGET_SSE2")
2377 (eq (symbol_ref "optimize_size")
2380 (const_string "V4SF"))
2381 /* For architectures resolving dependencies on
2382 whole SSE registers use APS move to break dependency
2383 chains, otherwise use short move to avoid extra work.
2385 Do the same for architectures resolving dependencies on
2386 the parts. While in DF mode it is better to always handle
2387 just register parts, the SF mode is different due to lack
2388 of instructions to load just part of the register. It is
2389 better to maintain the whole registers in single format
2390 to avoid problems on using packed logical operations. */
2391 (eq_attr "alternative" "6")
2393 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2395 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2397 (const_string "V4SF")
2398 (const_string "SF"))
2399 (eq_attr "alternative" "11")
2400 (const_string "DI")]
2401 (const_string "SF")))])
2403 (define_insn "*swapsf"
2404 [(set (match_operand:SF 0 "register_operand" "+f")
2405 (match_operand:SF 1 "register_operand" "+f"))
2408 "reload_completed || !TARGET_SSE"
2410 if (STACK_TOP_P (operands[0]))
2415 [(set_attr "type" "fxch")
2416 (set_attr "mode" "SF")])
2418 (define_expand "movdf"
2419 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2420 (match_operand:DF 1 "general_operand" ""))]
2422 "ix86_expand_move (DFmode, operands); DONE;")
2424 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2425 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2426 ;; On the average, pushdf using integers can be still shorter. Allow this
2427 ;; pattern for optimize_size too.
2429 (define_insn "*pushdf_nointeger"
2430 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2431 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2432 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2434 /* This insn should be already splitted before reg-stack. */
2437 [(set_attr "type" "multi")
2438 (set_attr "mode" "DF,SI,SI,DF")])
2440 (define_insn "*pushdf_integer"
2441 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2442 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2443 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2445 /* This insn should be already splitted before reg-stack. */
2448 [(set_attr "type" "multi")
2449 (set_attr "mode" "DF,SI,DF")])
2451 ;; %%% Kill this when call knows how to work this out.
2453 [(set (match_operand:DF 0 "push_operand" "")
2454 (match_operand:DF 1 "any_fp_register_operand" ""))]
2455 "!TARGET_64BIT && reload_completed"
2456 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2457 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2461 [(set (match_operand:DF 0 "push_operand" "")
2462 (match_operand:DF 1 "any_fp_register_operand" ""))]
2463 "TARGET_64BIT && reload_completed"
2464 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2465 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2469 [(set (match_operand:DF 0 "push_operand" "")
2470 (match_operand:DF 1 "general_operand" ""))]
2473 "ix86_split_long_move (operands); DONE;")
2475 ;; Moving is usually shorter when only FP registers are used. This separate
2476 ;; movdf pattern avoids the use of integer registers for FP operations
2477 ;; when optimizing for size.
2479 (define_insn "*movdf_nointeger"
2480 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2481 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2482 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2483 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2484 && (reload_in_progress || reload_completed
2485 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2486 || GET_CODE (operands[1]) != CONST_DOUBLE
2487 || memory_operand (operands[0], DFmode))"
2489 switch (which_alternative)
2492 if (REG_P (operands[1])
2493 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2495 if (REGNO (operands[0]) == FIRST_STACK_REG
2496 && TARGET_USE_FFREEP)
2497 return "ffreep\t%y0";
2500 else if (STACK_TOP_P (operands[0]))
2501 return "fld%z1\t%y1";
2506 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2507 return "fstp%z0\t%y0";
2509 return "fst%z0\t%y0";
2512 return standard_80387_constant_opcode (operands[1]);
2518 switch (get_attr_mode (insn))
2521 return "xorps\t%0, %0";
2523 return "xorpd\t%0, %0";
2525 return "pxor\t%0, %0";
2530 switch (get_attr_mode (insn))
2533 return "movaps\t{%1, %0|%0, %1}";
2535 return "movapd\t{%1, %0|%0, %1}";
2537 return "movsd\t{%1, %0|%0, %1}";
2542 if (get_attr_mode (insn) == MODE_V2DF)
2543 return "movlpd\t{%1, %0|%0, %1}";
2545 return "movsd\t{%1, %0|%0, %1}";
2547 return "movsd\t{%1, %0|%0, %1}";
2553 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2555 (cond [(eq_attr "alternative" "3,4")
2557 /* xorps is one byte shorter. */
2558 (eq_attr "alternative" "5")
2559 (cond [(ne (symbol_ref "optimize_size")
2561 (const_string "V4SF")
2562 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2564 (const_string "TI")]
2565 (const_string "V2DF"))
2566 /* For architectures resolving dependencies on
2567 whole SSE registers use APD move to break dependency
2568 chains, otherwise use short move to avoid extra work.
2570 movaps encodes one byte shorter. */
2571 (eq_attr "alternative" "6")
2573 [(ne (symbol_ref "optimize_size")
2575 (const_string "V4SF")
2576 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2578 (const_string "V2DF")]
2579 (const_string "DF"))
2580 /* For architectures resolving dependencies on register
2581 parts we may avoid extra work to zero out upper part
2583 (eq_attr "alternative" "7")
2585 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2587 (const_string "V2DF")
2588 (const_string "DF"))]
2589 (const_string "DF")))])
2591 (define_insn "*movdf_integer"
2592 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2593 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2594 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2595 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2596 && (reload_in_progress || reload_completed
2597 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2598 || GET_CODE (operands[1]) != CONST_DOUBLE
2599 || memory_operand (operands[0], DFmode))"
2601 switch (which_alternative)
2604 if (REG_P (operands[1])
2605 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2607 if (REGNO (operands[0]) == FIRST_STACK_REG
2608 && TARGET_USE_FFREEP)
2609 return "ffreep\t%y0";
2612 else if (STACK_TOP_P (operands[0]))
2613 return "fld%z1\t%y1";
2618 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2619 return "fstp%z0\t%y0";
2621 return "fst%z0\t%y0";
2624 return standard_80387_constant_opcode (operands[1]);
2631 switch (get_attr_mode (insn))
2634 return "xorps\t%0, %0";
2636 return "xorpd\t%0, %0";
2638 return "pxor\t%0, %0";
2643 switch (get_attr_mode (insn))
2646 return "movaps\t{%1, %0|%0, %1}";
2648 return "movapd\t{%1, %0|%0, %1}";
2650 return "movsd\t{%1, %0|%0, %1}";
2655 if (get_attr_mode (insn) == MODE_V2DF)
2656 return "movlpd\t{%1, %0|%0, %1}";
2658 return "movsd\t{%1, %0|%0, %1}";
2660 return "movsd\t{%1, %0|%0, %1}";
2666 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2668 (cond [(eq_attr "alternative" "3,4")
2670 /* xorps is one byte shorter. */
2671 (eq_attr "alternative" "5")
2672 (cond [(ne (symbol_ref "optimize_size")
2674 (const_string "V4SF")
2675 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2677 (const_string "TI")]
2678 (const_string "V2DF"))
2679 /* For architectures resolving dependencies on
2680 whole SSE registers use APD move to break dependency
2681 chains, otherwise use short move to avoid extra work.
2683 movaps encodes one byte shorter. */
2684 (eq_attr "alternative" "6")
2686 [(ne (symbol_ref "optimize_size")
2688 (const_string "V4SF")
2689 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2691 (const_string "V2DF")]
2692 (const_string "DF"))
2693 /* For architectures resolving dependencies on register
2694 parts we may avoid extra work to zero out upper part
2696 (eq_attr "alternative" "7")
2698 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2700 (const_string "V2DF")
2701 (const_string "DF"))]
2702 (const_string "DF")))])
2705 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2706 (match_operand:DF 1 "general_operand" ""))]
2708 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2709 && ! (ANY_FP_REG_P (operands[0]) ||
2710 (GET_CODE (operands[0]) == SUBREG
2711 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2712 && ! (ANY_FP_REG_P (operands[1]) ||
2713 (GET_CODE (operands[1]) == SUBREG
2714 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2716 "ix86_split_long_move (operands); DONE;")
2718 (define_insn "*swapdf"
2719 [(set (match_operand:DF 0 "register_operand" "+f")
2720 (match_operand:DF 1 "register_operand" "+f"))
2723 "reload_completed || !TARGET_SSE2"
2725 if (STACK_TOP_P (operands[0]))
2730 [(set_attr "type" "fxch")
2731 (set_attr "mode" "DF")])
2733 (define_expand "movxf"
2734 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2735 (match_operand:XF 1 "general_operand" ""))]
2737 "ix86_expand_move (XFmode, operands); DONE;")
2739 (define_expand "movtf"
2740 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2741 (match_operand:TF 1 "general_operand" ""))]
2743 "ix86_expand_move (TFmode, operands); DONE;")
2745 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2746 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2747 ;; Pushing using integer instructions is longer except for constants
2748 ;; and direct memory references.
2749 ;; (assuming that any given constant is pushed only once, but this ought to be
2750 ;; handled elsewhere).
2752 (define_insn "*pushxf_nointeger"
2753 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2754 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2755 "!TARGET_64BIT && optimize_size"
2757 /* This insn should be already splitted before reg-stack. */
2760 [(set_attr "type" "multi")
2761 (set_attr "mode" "XF,SI,SI")])
2763 (define_insn "*pushtf_nointeger"
2764 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2765 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2768 /* This insn should be already splitted before reg-stack. */
2771 [(set_attr "type" "multi")
2772 (set_attr "mode" "XF,SI,SI")])
2774 (define_insn "*pushxf_integer"
2775 [(set (match_operand:XF 0 "push_operand" "=<,<")
2776 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2777 "!TARGET_64BIT && !optimize_size"
2779 /* This insn should be already splitted before reg-stack. */
2782 [(set_attr "type" "multi")
2783 (set_attr "mode" "XF,SI")])
2785 (define_insn "*pushtf_integer"
2786 [(set (match_operand:TF 0 "push_operand" "=<,<")
2787 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2790 /* This insn should be already splitted before reg-stack. */
2793 [(set_attr "type" "multi")
2794 (set_attr "mode" "XF,SI")])
2797 [(set (match_operand 0 "push_operand" "")
2798 (match_operand 1 "general_operand" ""))]
2800 && (GET_MODE (operands[0]) == XFmode
2801 || GET_MODE (operands[0]) == TFmode
2802 || GET_MODE (operands[0]) == DFmode)
2803 && !ANY_FP_REG_P (operands[1])"
2805 "ix86_split_long_move (operands); DONE;")
2808 [(set (match_operand:XF 0 "push_operand" "")
2809 (match_operand:XF 1 "any_fp_register_operand" ""))]
2811 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2812 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2815 [(set (match_operand:TF 0 "push_operand" "")
2816 (match_operand:TF 1 "any_fp_register_operand" ""))]
2818 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2819 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2822 [(set (match_operand:TF 0 "push_operand" "")
2823 (match_operand:TF 1 "any_fp_register_operand" ""))]
2825 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2826 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2828 ;; Do not use integer registers when optimizing for size
2829 (define_insn "*movxf_nointeger"
2830 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2831 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2834 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2835 && (reload_in_progress || reload_completed
2836 || GET_CODE (operands[1]) != CONST_DOUBLE
2837 || memory_operand (operands[0], XFmode))"
2839 switch (which_alternative)
2842 if (REG_P (operands[1])
2843 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2845 if (REGNO (operands[0]) == FIRST_STACK_REG
2846 && TARGET_USE_FFREEP)
2847 return "ffreep\t%y0";
2850 else if (STACK_TOP_P (operands[0]))
2851 return "fld%z1\t%y1";
2856 /* There is no non-popping store to memory for XFmode. So if
2857 we need one, follow the store with a load. */
2858 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2859 return "fstp%z0\t%y0\;fld%z0\t%y0";
2861 return "fstp%z0\t%y0";
2864 return standard_80387_constant_opcode (operands[1]);
2871 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2872 (set_attr "mode" "XF,XF,XF,SI,SI")])
2874 (define_insn "*movtf_nointeger"
2875 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2876 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2877 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2879 && (reload_in_progress || reload_completed
2880 || GET_CODE (operands[1]) != CONST_DOUBLE
2881 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2882 || memory_operand (operands[0], TFmode))"
2884 switch (which_alternative)
2887 if (REG_P (operands[1])
2888 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2890 if (REGNO (operands[0]) == FIRST_STACK_REG
2891 && TARGET_USE_FFREEP)
2892 return "ffreep\t%y0";
2895 else if (STACK_TOP_P (operands[0]))
2896 return "fld%z1\t%y1";
2901 /* There is no non-popping store to memory for XFmode. So if
2902 we need one, follow the store with a load. */
2903 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2904 return "fstp%z0\t%y0\;fld%z0\t%y0";
2906 return "fstp%z0\t%y0";
2909 return standard_80387_constant_opcode (operands[1]);
2916 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2917 (set_attr "mode" "XF,XF,XF,SI,SI")])
2919 (define_insn "*movxf_integer"
2920 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2921 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2924 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2925 && (reload_in_progress || reload_completed
2926 || GET_CODE (operands[1]) != CONST_DOUBLE
2927 || memory_operand (operands[0], XFmode))"
2929 switch (which_alternative)
2932 if (REG_P (operands[1])
2933 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2935 if (REGNO (operands[0]) == FIRST_STACK_REG
2936 && TARGET_USE_FFREEP)
2937 return "ffreep\t%y0";
2940 else if (STACK_TOP_P (operands[0]))
2941 return "fld%z1\t%y1";
2946 /* There is no non-popping store to memory for XFmode. So if
2947 we need one, follow the store with a load. */
2948 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2949 return "fstp%z0\t%y0\;fld%z0\t%y0";
2951 return "fstp%z0\t%y0";
2954 return standard_80387_constant_opcode (operands[1]);
2961 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2962 (set_attr "mode" "XF,XF,XF,SI,SI")])
2964 (define_insn "*movtf_integer"
2965 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2966 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2967 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2969 && (reload_in_progress || reload_completed
2970 || GET_CODE (operands[1]) != CONST_DOUBLE
2971 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2972 || memory_operand (operands[0], TFmode))"
2974 switch (which_alternative)
2977 if (REG_P (operands[1])
2978 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2980 if (REGNO (operands[0]) == FIRST_STACK_REG
2981 && TARGET_USE_FFREEP)
2982 return "ffreep\t%y0";
2985 else if (STACK_TOP_P (operands[0]))
2986 return "fld%z1\t%y1";
2991 /* There is no non-popping store to memory for XFmode. So if
2992 we need one, follow the store with a load. */
2993 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2994 return "fstp%z0\t%y0\;fld%z0\t%y0";
2996 return "fstp%z0\t%y0";
2999 return standard_80387_constant_opcode (operands[1]);
3006 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3007 (set_attr "mode" "XF,XF,XF,SI,SI")])
3010 [(set (match_operand 0 "nonimmediate_operand" "")
3011 (match_operand 1 "general_operand" ""))]
3013 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3014 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3015 && ! (ANY_FP_REG_P (operands[0]) ||
3016 (GET_CODE (operands[0]) == SUBREG
3017 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3018 && ! (ANY_FP_REG_P (operands[1]) ||
3019 (GET_CODE (operands[1]) == SUBREG
3020 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3022 "ix86_split_long_move (operands); DONE;")
3025 [(set (match_operand 0 "register_operand" "")
3026 (match_operand 1 "memory_operand" ""))]
3028 && GET_CODE (operands[1]) == MEM
3029 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3030 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3031 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3032 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3033 && (!(SSE_REG_P (operands[0]) ||
3034 (GET_CODE (operands[0]) == SUBREG
3035 && SSE_REG_P (SUBREG_REG (operands[0]))))
3036 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3037 && (!(FP_REG_P (operands[0]) ||
3038 (GET_CODE (operands[0]) == SUBREG
3039 && FP_REG_P (SUBREG_REG (operands[0]))))
3040 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3043 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3045 (define_insn "swapxf"
3046 [(set (match_operand:XF 0 "register_operand" "+f")
3047 (match_operand:XF 1 "register_operand" "+f"))
3052 if (STACK_TOP_P (operands[0]))
3057 [(set_attr "type" "fxch")
3058 (set_attr "mode" "XF")])
3060 (define_insn "swaptf"
3061 [(set (match_operand:TF 0 "register_operand" "+f")
3062 (match_operand:TF 1 "register_operand" "+f"))
3067 if (STACK_TOP_P (operands[0]))
3072 [(set_attr "type" "fxch")
3073 (set_attr "mode" "XF")])
3075 ;; Zero extension instructions
3077 (define_expand "zero_extendhisi2"
3078 [(set (match_operand:SI 0 "register_operand" "")
3079 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3082 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3084 operands[1] = force_reg (HImode, operands[1]);
3085 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3090 (define_insn "zero_extendhisi2_and"
3091 [(set (match_operand:SI 0 "register_operand" "=r")
3092 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3093 (clobber (reg:CC 17))]
3094 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3096 [(set_attr "type" "alu1")
3097 (set_attr "mode" "SI")])
3100 [(set (match_operand:SI 0 "register_operand" "")
3101 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3102 (clobber (reg:CC 17))]
3103 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3104 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3105 (clobber (reg:CC 17))])]
3108 (define_insn "*zero_extendhisi2_movzwl"
3109 [(set (match_operand:SI 0 "register_operand" "=r")
3110 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3111 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3112 "movz{wl|x}\t{%1, %0|%0, %1}"
3113 [(set_attr "type" "imovx")
3114 (set_attr "mode" "SI")])
3116 (define_expand "zero_extendqihi2"
3118 [(set (match_operand:HI 0 "register_operand" "")
3119 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3120 (clobber (reg:CC 17))])]
3124 (define_insn "*zero_extendqihi2_and"
3125 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3126 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3127 (clobber (reg:CC 17))]
3128 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3130 [(set_attr "type" "alu1")
3131 (set_attr "mode" "HI")])
3133 (define_insn "*zero_extendqihi2_movzbw_and"
3134 [(set (match_operand:HI 0 "register_operand" "=r,r")
3135 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3136 (clobber (reg:CC 17))]
3137 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3139 [(set_attr "type" "imovx,alu1")
3140 (set_attr "mode" "HI")])
3142 (define_insn "*zero_extendqihi2_movzbw"
3143 [(set (match_operand:HI 0 "register_operand" "=r")
3144 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3145 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3146 "movz{bw|x}\t{%1, %0|%0, %1}"
3147 [(set_attr "type" "imovx")
3148 (set_attr "mode" "HI")])
3150 ;; For the movzbw case strip only the clobber
3152 [(set (match_operand:HI 0 "register_operand" "")
3153 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3154 (clobber (reg:CC 17))]
3156 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3157 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3158 [(set (match_operand:HI 0 "register_operand" "")
3159 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3161 ;; When source and destination does not overlap, clear destination
3162 ;; first and then do the movb
3164 [(set (match_operand:HI 0 "register_operand" "")
3165 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3166 (clobber (reg:CC 17))]
3168 && ANY_QI_REG_P (operands[0])
3169 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3170 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3171 [(set (match_dup 0) (const_int 0))
3172 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3173 "operands[2] = gen_lowpart (QImode, operands[0]);")
3175 ;; Rest is handled by single and.
3177 [(set (match_operand:HI 0 "register_operand" "")
3178 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3179 (clobber (reg:CC 17))]
3181 && true_regnum (operands[0]) == true_regnum (operands[1])"
3182 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3183 (clobber (reg:CC 17))])]
3186 (define_expand "zero_extendqisi2"
3188 [(set (match_operand:SI 0 "register_operand" "")
3189 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3190 (clobber (reg:CC 17))])]
3194 (define_insn "*zero_extendqisi2_and"
3195 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3196 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3197 (clobber (reg:CC 17))]
3198 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3200 [(set_attr "type" "alu1")
3201 (set_attr "mode" "SI")])
3203 (define_insn "*zero_extendqisi2_movzbw_and"
3204 [(set (match_operand:SI 0 "register_operand" "=r,r")
3205 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3206 (clobber (reg:CC 17))]
3207 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3209 [(set_attr "type" "imovx,alu1")
3210 (set_attr "mode" "SI")])
3212 (define_insn "*zero_extendqisi2_movzbw"
3213 [(set (match_operand:SI 0 "register_operand" "=r")
3214 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3215 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3216 "movz{bl|x}\t{%1, %0|%0, %1}"
3217 [(set_attr "type" "imovx")
3218 (set_attr "mode" "SI")])
3220 ;; For the movzbl case strip only the clobber
3222 [(set (match_operand:SI 0 "register_operand" "")
3223 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3224 (clobber (reg:CC 17))]
3226 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3227 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3229 (zero_extend:SI (match_dup 1)))])
3231 ;; When source and destination does not overlap, clear destination
3232 ;; first and then do the movb
3234 [(set (match_operand:SI 0 "register_operand" "")
3235 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3236 (clobber (reg:CC 17))]
3238 && ANY_QI_REG_P (operands[0])
3239 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3240 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3241 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3242 [(set (match_dup 0) (const_int 0))
3243 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3244 "operands[2] = gen_lowpart (QImode, operands[0]);")
3246 ;; Rest is handled by single and.
3248 [(set (match_operand:SI 0 "register_operand" "")
3249 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3250 (clobber (reg:CC 17))]
3252 && true_regnum (operands[0]) == true_regnum (operands[1])"
3253 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3254 (clobber (reg:CC 17))])]
3257 ;; %%% Kill me once multi-word ops are sane.
3258 (define_expand "zero_extendsidi2"
3259 [(set (match_operand:DI 0 "register_operand" "=r")
3260 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3264 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3269 (define_insn "zero_extendsidi2_32"
3270 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3271 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3272 (clobber (reg:CC 17))]
3275 [(set_attr "mode" "SI")])
3277 (define_insn "zero_extendsidi2_rex64"
3278 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3279 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3282 mov\t{%k1, %k0|%k0, %k1}
3284 [(set_attr "type" "imovx,imov")
3285 (set_attr "mode" "SI,DI")])
3288 [(set (match_operand:DI 0 "memory_operand" "")
3289 (zero_extend:DI (match_dup 0)))]
3291 [(set (match_dup 4) (const_int 0))]
3292 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3295 [(set (match_operand:DI 0 "register_operand" "")
3296 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3297 (clobber (reg:CC 17))]
3298 "!TARGET_64BIT && reload_completed
3299 && true_regnum (operands[0]) == true_regnum (operands[1])"
3300 [(set (match_dup 4) (const_int 0))]
3301 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3304 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3305 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3306 (clobber (reg:CC 17))]
3307 "!TARGET_64BIT && reload_completed"
3308 [(set (match_dup 3) (match_dup 1))
3309 (set (match_dup 4) (const_int 0))]
3310 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3312 (define_insn "zero_extendhidi2"
3313 [(set (match_operand:DI 0 "register_operand" "=r,r")
3314 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3317 movz{wl|x}\t{%1, %k0|%k0, %1}
3318 movz{wq|x}\t{%1, %0|%0, %1}"
3319 [(set_attr "type" "imovx")
3320 (set_attr "mode" "SI,DI")])
3322 (define_insn "zero_extendqidi2"
3323 [(set (match_operand:DI 0 "register_operand" "=r,r")
3324 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3327 movz{bl|x}\t{%1, %k0|%k0, %1}
3328 movz{bq|x}\t{%1, %0|%0, %1}"
3329 [(set_attr "type" "imovx")
3330 (set_attr "mode" "SI,DI")])
3332 ;; Sign extension instructions
3334 (define_expand "extendsidi2"
3335 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3336 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3337 (clobber (reg:CC 17))
3338 (clobber (match_scratch:SI 2 ""))])]
3343 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3348 (define_insn "*extendsidi2_1"
3349 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3350 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3351 (clobber (reg:CC 17))
3352 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3356 (define_insn "extendsidi2_rex64"
3357 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3358 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3362 movs{lq|x}\t{%1,%0|%0, %1}"
3363 [(set_attr "type" "imovx")
3364 (set_attr "mode" "DI")
3365 (set_attr "prefix_0f" "0")
3366 (set_attr "modrm" "0,1")])
3368 (define_insn "extendhidi2"
3369 [(set (match_operand:DI 0 "register_operand" "=r")
3370 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3372 "movs{wq|x}\t{%1,%0|%0, %1}"
3373 [(set_attr "type" "imovx")
3374 (set_attr "mode" "DI")])
3376 (define_insn "extendqidi2"
3377 [(set (match_operand:DI 0 "register_operand" "=r")
3378 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3380 "movs{bq|x}\t{%1,%0|%0, %1}"
3381 [(set_attr "type" "imovx")
3382 (set_attr "mode" "DI")])
3384 ;; Extend to memory case when source register does die.
3386 [(set (match_operand:DI 0 "memory_operand" "")
3387 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3388 (clobber (reg:CC 17))
3389 (clobber (match_operand:SI 2 "register_operand" ""))]
3391 && dead_or_set_p (insn, operands[1])
3392 && !reg_mentioned_p (operands[1], operands[0]))"
3393 [(set (match_dup 3) (match_dup 1))
3394 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3395 (clobber (reg:CC 17))])
3396 (set (match_dup 4) (match_dup 1))]
3397 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3399 ;; Extend to memory case when source register does not die.
3401 [(set (match_operand:DI 0 "memory_operand" "")
3402 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3403 (clobber (reg:CC 17))
3404 (clobber (match_operand:SI 2 "register_operand" ""))]
3408 split_di (&operands[0], 1, &operands[3], &operands[4]);
3410 emit_move_insn (operands[3], operands[1]);
3412 /* Generate a cltd if possible and doing so it profitable. */
3413 if (true_regnum (operands[1]) == 0
3414 && true_regnum (operands[2]) == 1
3415 && (optimize_size || TARGET_USE_CLTD))
3417 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3421 emit_move_insn (operands[2], operands[1]);
3422 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3424 emit_move_insn (operands[4], operands[2]);
3428 ;; Extend to register case. Optimize case where source and destination
3429 ;; registers match and cases where we can use cltd.
3431 [(set (match_operand:DI 0 "register_operand" "")
3432 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3433 (clobber (reg:CC 17))
3434 (clobber (match_scratch:SI 2 ""))]
3438 split_di (&operands[0], 1, &operands[3], &operands[4]);
3440 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3441 emit_move_insn (operands[3], operands[1]);
3443 /* Generate a cltd if possible and doing so it profitable. */
3444 if (true_regnum (operands[3]) == 0
3445 && (optimize_size || TARGET_USE_CLTD))
3447 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3451 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3452 emit_move_insn (operands[4], operands[1]);
3454 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3458 (define_insn "extendhisi2"
3459 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3460 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3463 switch (get_attr_prefix_0f (insn))
3466 return "{cwtl|cwde}";
3468 return "movs{wl|x}\t{%1,%0|%0, %1}";
3471 [(set_attr "type" "imovx")
3472 (set_attr "mode" "SI")
3473 (set (attr "prefix_0f")
3474 ;; movsx is short decodable while cwtl is vector decoded.
3475 (if_then_else (and (eq_attr "cpu" "!k6")
3476 (eq_attr "alternative" "0"))
3478 (const_string "1")))
3480 (if_then_else (eq_attr "prefix_0f" "0")
3482 (const_string "1")))])
3484 (define_insn "*extendhisi2_zext"
3485 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3487 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3490 switch (get_attr_prefix_0f (insn))
3493 return "{cwtl|cwde}";
3495 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3498 [(set_attr "type" "imovx")
3499 (set_attr "mode" "SI")
3500 (set (attr "prefix_0f")
3501 ;; movsx is short decodable while cwtl is vector decoded.
3502 (if_then_else (and (eq_attr "cpu" "!k6")
3503 (eq_attr "alternative" "0"))
3505 (const_string "1")))
3507 (if_then_else (eq_attr "prefix_0f" "0")
3509 (const_string "1")))])
3511 (define_insn "extendqihi2"
3512 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3513 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3516 switch (get_attr_prefix_0f (insn))
3519 return "{cbtw|cbw}";
3521 return "movs{bw|x}\t{%1,%0|%0, %1}";
3524 [(set_attr "type" "imovx")
3525 (set_attr "mode" "HI")
3526 (set (attr "prefix_0f")
3527 ;; movsx is short decodable while cwtl is vector decoded.
3528 (if_then_else (and (eq_attr "cpu" "!k6")
3529 (eq_attr "alternative" "0"))
3531 (const_string "1")))
3533 (if_then_else (eq_attr "prefix_0f" "0")
3535 (const_string "1")))])
3537 (define_insn "extendqisi2"
3538 [(set (match_operand:SI 0 "register_operand" "=r")
3539 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3541 "movs{bl|x}\t{%1,%0|%0, %1}"
3542 [(set_attr "type" "imovx")
3543 (set_attr "mode" "SI")])
3545 (define_insn "*extendqisi2_zext"
3546 [(set (match_operand:DI 0 "register_operand" "=r")
3548 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3550 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3551 [(set_attr "type" "imovx")
3552 (set_attr "mode" "SI")])
3554 ;; Conversions between float and double.
3556 ;; These are all no-ops in the model used for the 80387. So just
3559 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3560 (define_insn "*dummy_extendsfdf2"
3561 [(set (match_operand:DF 0 "push_operand" "=<")
3562 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3567 [(set (match_operand:DF 0 "push_operand" "")
3568 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3570 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3571 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3574 [(set (match_operand:DF 0 "push_operand" "")
3575 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3577 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3578 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3580 (define_insn "*dummy_extendsfxf2"
3581 [(set (match_operand:XF 0 "push_operand" "=<")
3582 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3587 [(set (match_operand:XF 0 "push_operand" "")
3588 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3590 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3591 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3593 (define_insn "*dummy_extendsftf2"
3594 [(set (match_operand:TF 0 "push_operand" "=<")
3595 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3600 [(set (match_operand:TF 0 "push_operand" "")
3601 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3603 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3604 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3607 [(set (match_operand:TF 0 "push_operand" "")
3608 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3610 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3611 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3613 (define_insn "*dummy_extenddfxf2"
3614 [(set (match_operand:XF 0 "push_operand" "=<")
3615 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3620 [(set (match_operand:XF 0 "push_operand" "")
3621 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3623 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3624 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3626 (define_insn "*dummy_extenddftf2"
3627 [(set (match_operand:TF 0 "push_operand" "=<")
3628 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3633 [(set (match_operand:TF 0 "push_operand" "")
3634 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3636 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3637 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3640 [(set (match_operand:TF 0 "push_operand" "")
3641 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3643 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3644 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3646 (define_expand "extendsfdf2"
3647 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3648 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3649 "TARGET_80387 || TARGET_SSE2"
3651 /* ??? Needed for compress_float_constant since all fp constants
3652 are LEGITIMATE_CONSTANT_P. */
3653 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3654 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3655 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3656 operands[1] = force_reg (SFmode, operands[1]);
3659 (define_insn "*extendsfdf2_1"
3660 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3661 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3662 "(TARGET_80387 || TARGET_SSE2)
3663 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3665 switch (which_alternative)
3668 if (REG_P (operands[1])
3669 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3671 else if (STACK_TOP_P (operands[0]))
3672 return "fld%z1\t%y1";
3677 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3678 return "fstp%z0\t%y0";
3681 return "fst%z0\t%y0";
3683 return "cvtss2sd\t{%1, %0|%0, %1}";
3689 [(set_attr "type" "fmov,fmov,ssecvt")
3690 (set_attr "mode" "SF,XF,DF")])
3692 (define_insn "*extendsfdf2_1_sse_only"
3693 [(set (match_operand:DF 0 "register_operand" "=Y")
3694 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3695 "!TARGET_80387 && TARGET_SSE2
3696 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3697 "cvtss2sd\t{%1, %0|%0, %1}"
3698 [(set_attr "type" "ssecvt")
3699 (set_attr "mode" "DF")])
3701 (define_expand "extendsfxf2"
3702 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3703 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3704 "!TARGET_64BIT && TARGET_80387"
3706 /* ??? Needed for compress_float_constant since all fp constants
3707 are LEGITIMATE_CONSTANT_P. */
3708 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3709 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3710 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3711 operands[1] = force_reg (SFmode, operands[1]);
3714 (define_insn "*extendsfxf2_1"
3715 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3716 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3717 "!TARGET_64BIT && TARGET_80387
3718 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3720 switch (which_alternative)
3723 if (REG_P (operands[1])
3724 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3726 else if (STACK_TOP_P (operands[0]))
3727 return "fld%z1\t%y1";
3732 /* There is no non-popping store to memory for XFmode. So if
3733 we need one, follow the store with a load. */
3734 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3735 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3737 return "fstp%z0\t%y0";
3743 [(set_attr "type" "fmov")
3744 (set_attr "mode" "SF,XF")])
3746 (define_expand "extendsftf2"
3747 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3748 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3751 /* ??? Needed for compress_float_constant since all fp constants
3752 are LEGITIMATE_CONSTANT_P. */
3753 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3754 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3755 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3756 operands[1] = force_reg (SFmode, operands[1]);
3759 (define_insn "*extendsftf2_1"
3760 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3761 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3763 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3765 switch (which_alternative)
3768 if (REG_P (operands[1])
3769 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3771 else if (STACK_TOP_P (operands[0]))
3772 return "fld%z1\t%y1";
3777 /* There is no non-popping store to memory for XFmode. So if
3778 we need one, follow the store with a load. */
3779 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3780 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3782 return "fstp%z0\t%y0";
3788 [(set_attr "type" "fmov")
3789 (set_attr "mode" "SF,XF")])
3791 (define_expand "extenddfxf2"
3792 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3793 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3794 "!TARGET_64BIT && TARGET_80387"
3796 /* ??? Needed for compress_float_constant since all fp constants
3797 are LEGITIMATE_CONSTANT_P. */
3798 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3799 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3800 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3801 operands[1] = force_reg (DFmode, operands[1]);
3804 (define_insn "*extenddfxf2_1"
3805 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3806 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3807 "!TARGET_64BIT && TARGET_80387
3808 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3810 switch (which_alternative)
3813 if (REG_P (operands[1])
3814 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3816 else if (STACK_TOP_P (operands[0]))
3817 return "fld%z1\t%y1";
3822 /* There is no non-popping store to memory for XFmode. So if
3823 we need one, follow the store with a load. */
3824 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3825 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3827 return "fstp%z0\t%y0";
3833 [(set_attr "type" "fmov")
3834 (set_attr "mode" "DF,XF")])
3836 (define_expand "extenddftf2"
3837 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3838 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3841 /* ??? Needed for compress_float_constant since all fp constants
3842 are LEGITIMATE_CONSTANT_P. */
3843 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3844 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3845 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3846 operands[1] = force_reg (DFmode, operands[1]);
3849 (define_insn "*extenddftf2_1"
3850 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3851 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3853 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3855 switch (which_alternative)
3858 if (REG_P (operands[1])
3859 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3861 else if (STACK_TOP_P (operands[0]))
3862 return "fld%z1\t%y1";
3867 /* There is no non-popping store to memory for XFmode. So if
3868 we need one, follow the store with a load. */
3869 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3870 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3872 return "fstp%z0\t%y0";
3878 [(set_attr "type" "fmov")
3879 (set_attr "mode" "DF,XF")])
3881 ;; %%% This seems bad bad news.
3882 ;; This cannot output into an f-reg because there is no way to be sure
3883 ;; of truncating in that case. Otherwise this is just like a simple move
3884 ;; insn. So we pretend we can output to a reg in order to get better
3885 ;; register preferencing, but we really use a stack slot.
3887 (define_expand "truncdfsf2"
3888 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3890 (match_operand:DF 1 "register_operand" "")))
3891 (clobber (match_dup 2))])]
3892 "TARGET_80387 || TARGET_SSE2"
3895 operands[2] = assign_386_stack_local (SFmode, 0);
3898 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3903 (define_insn "*truncdfsf2_1"
3904 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3906 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3907 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3908 "TARGET_80387 && !TARGET_SSE2"
3910 switch (which_alternative)
3913 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3914 return "fstp%z0\t%y0";
3916 return "fst%z0\t%y0";
3921 [(set_attr "type" "fmov,multi,multi,multi")
3922 (set_attr "mode" "SF,SF,SF,SF")])
3924 (define_insn "*truncdfsf2_1_sse"
3925 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3927 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3928 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3929 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3931 switch (which_alternative)
3934 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3935 return "fstp%z0\t%y0";
3937 return "fst%z0\t%y0";
3944 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3945 (set_attr "mode" "SF,SF,SF,SF,DF")])
3947 (define_insn "*truncdfsf2_1_sse_nooverlap"
3948 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3950 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3951 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3952 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3954 switch (which_alternative)
3957 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3958 return "fstp%z0\t%y0";
3960 return "fst%z0\t%y0";
3967 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3968 (set_attr "mode" "SF,SF,SF,SF,DF")])
3970 (define_insn "*truncdfsf2_2"
3971 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3973 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3974 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3975 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3977 switch (which_alternative)
3981 return "cvtsd2ss\t{%1, %0|%0, %1}";
3983 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3984 return "fstp%z0\t%y0";
3986 return "fst%z0\t%y0";
3991 [(set_attr "type" "ssecvt,ssecvt,fmov")
3992 (set_attr "athlon_decode" "vector,double,*")
3993 (set_attr "mode" "SF,SF,SF")])
3995 (define_insn "*truncdfsf2_2_nooverlap"
3996 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
3998 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3999 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
4000 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4002 switch (which_alternative)
4007 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4008 return "fstp%z0\t%y0";
4010 return "fst%z0\t%y0";
4015 [(set_attr "type" "ssecvt,fmov")
4016 (set_attr "mode" "DF,SF")])
4018 (define_insn "*truncdfsf2_3"
4019 [(set (match_operand:SF 0 "memory_operand" "=m")
4021 (match_operand:DF 1 "register_operand" "f")))]
4024 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4025 return "fstp%z0\t%y0";
4027 return "fst%z0\t%y0";
4029 [(set_attr "type" "fmov")
4030 (set_attr "mode" "SF")])
4032 (define_insn "truncdfsf2_sse_only"
4033 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
4035 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
4036 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4037 "cvtsd2ss\t{%1, %0|%0, %1}"
4038 [(set_attr "type" "ssecvt")
4039 (set_attr "athlon_decode" "vector,double")
4040 (set_attr "mode" "SF")])
4042 (define_insn "*truncdfsf2_sse_only_nooverlap"
4043 [(set (match_operand:SF 0 "register_operand" "=&Y")
4045 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4046 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4048 [(set_attr "type" "ssecvt")
4049 (set_attr "mode" "DF")])
4052 [(set (match_operand:SF 0 "memory_operand" "")
4054 (match_operand:DF 1 "register_operand" "")))
4055 (clobber (match_operand:SF 2 "memory_operand" ""))]
4057 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4060 ; Avoid possible reformatting penalty on the destination by first
4063 [(set (match_operand:SF 0 "register_operand" "")
4065 (match_operand:DF 1 "nonimmediate_operand" "")))
4066 (clobber (match_operand 2 "" ""))]
4067 "TARGET_80387 && reload_completed
4068 && SSE_REG_P (operands[0])
4069 && !STACK_REG_P (operands[1])"
4073 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
4074 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4077 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4078 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4079 /* simplify_gen_subreg refuses to widen memory references. */
4080 if (GET_CODE (src) == SUBREG)
4081 alter_subreg (&src);
4082 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4084 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4085 emit_insn (gen_cvtsd2ss (dest, dest, src));
4091 [(set (match_operand:SF 0 "register_operand" "")
4093 (match_operand:DF 1 "nonimmediate_operand" "")))]
4094 "TARGET_80387 && reload_completed
4095 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4099 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4100 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4101 /* simplify_gen_subreg refuses to widen memory references. */
4102 if (GET_CODE (src) == SUBREG)
4103 alter_subreg (&src);
4104 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4106 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4107 emit_insn (gen_cvtsd2ss (dest, dest, src));
4112 [(set (match_operand:SF 0 "register_operand" "")
4114 (match_operand:DF 1 "fp_register_operand" "")))
4115 (clobber (match_operand:SF 2 "memory_operand" ""))]
4116 "TARGET_80387 && reload_completed"
4117 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4118 (set (match_dup 0) (match_dup 2))]
4121 (define_expand "truncxfsf2"
4122 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4124 (match_operand:XF 1 "register_operand" "")))
4125 (clobber (match_dup 2))])]
4126 "!TARGET_64BIT && TARGET_80387"
4127 "operands[2] = assign_386_stack_local (SFmode, 0);")
4129 (define_insn "*truncxfsf2_1"
4130 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4132 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4133 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4134 "!TARGET_64BIT && TARGET_80387"
4136 switch (which_alternative)
4139 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4140 return "fstp%z0\t%y0";
4142 return "fst%z0\t%y0";
4147 [(set_attr "type" "fmov,multi,multi,multi")
4148 (set_attr "mode" "SF")])
4150 (define_insn "*truncxfsf2_2"
4151 [(set (match_operand:SF 0 "memory_operand" "=m")
4153 (match_operand:XF 1 "register_operand" "f")))]
4154 "!TARGET_64BIT && TARGET_80387"
4156 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4157 return "fstp%z0\t%y0";
4159 return "fst%z0\t%y0";
4161 [(set_attr "type" "fmov")
4162 (set_attr "mode" "SF")])
4165 [(set (match_operand:SF 0 "memory_operand" "")
4167 (match_operand:XF 1 "register_operand" "")))
4168 (clobber (match_operand:SF 2 "memory_operand" ""))]
4170 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4174 [(set (match_operand:SF 0 "register_operand" "")
4176 (match_operand:XF 1 "register_operand" "")))
4177 (clobber (match_operand:SF 2 "memory_operand" ""))]
4178 "TARGET_80387 && reload_completed"
4179 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4180 (set (match_dup 0) (match_dup 2))]
4183 (define_expand "trunctfsf2"
4184 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4186 (match_operand:TF 1 "register_operand" "")))
4187 (clobber (match_dup 2))])]
4189 "operands[2] = assign_386_stack_local (SFmode, 0);")
4191 (define_insn "*trunctfsf2_1"
4192 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4194 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4195 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4198 switch (which_alternative)
4201 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4202 return "fstp%z0\t%y0";
4204 return "fst%z0\t%y0";
4209 [(set_attr "type" "fmov,multi,multi,multi")
4210 (set_attr "mode" "SF")])
4212 (define_insn "*trunctfsf2_2"
4213 [(set (match_operand:SF 0 "memory_operand" "=m")
4215 (match_operand:TF 1 "register_operand" "f")))]
4218 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4219 return "fstp%z0\t%y0";
4221 return "fst%z0\t%y0";
4223 [(set_attr "type" "fmov")
4224 (set_attr "mode" "SF")])
4227 [(set (match_operand:SF 0 "memory_operand" "")
4229 (match_operand:TF 1 "register_operand" "")))
4230 (clobber (match_operand:SF 2 "memory_operand" ""))]
4232 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4236 [(set (match_operand:SF 0 "register_operand" "")
4238 (match_operand:TF 1 "register_operand" "")))
4239 (clobber (match_operand:SF 2 "memory_operand" ""))]
4240 "TARGET_80387 && reload_completed"
4241 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4242 (set (match_dup 0) (match_dup 2))]
4246 (define_expand "truncxfdf2"
4247 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4249 (match_operand:XF 1 "register_operand" "")))
4250 (clobber (match_dup 2))])]
4251 "!TARGET_64BIT && TARGET_80387"
4252 "operands[2] = assign_386_stack_local (DFmode, 0);")
4254 (define_insn "*truncxfdf2_1"
4255 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4257 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4258 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4259 "!TARGET_64BIT && TARGET_80387"
4261 switch (which_alternative)
4264 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4265 return "fstp%z0\t%y0";
4267 return "fst%z0\t%y0";
4273 [(set_attr "type" "fmov,multi,multi,multi")
4274 (set_attr "mode" "DF")])
4276 (define_insn "*truncxfdf2_2"
4277 [(set (match_operand:DF 0 "memory_operand" "=m")
4279 (match_operand:XF 1 "register_operand" "f")))]
4280 "!TARGET_64BIT && TARGET_80387"
4282 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4283 return "fstp%z0\t%y0";
4285 return "fst%z0\t%y0";
4287 [(set_attr "type" "fmov")
4288 (set_attr "mode" "DF")])
4291 [(set (match_operand:DF 0 "memory_operand" "")
4293 (match_operand:XF 1 "register_operand" "")))
4294 (clobber (match_operand:DF 2 "memory_operand" ""))]
4296 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4300 [(set (match_operand:DF 0 "register_operand" "")
4302 (match_operand:XF 1 "register_operand" "")))
4303 (clobber (match_operand:DF 2 "memory_operand" ""))]
4304 "TARGET_80387 && reload_completed"
4305 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4306 (set (match_dup 0) (match_dup 2))]
4309 (define_expand "trunctfdf2"
4310 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4312 (match_operand:TF 1 "register_operand" "")))
4313 (clobber (match_dup 2))])]
4315 "operands[2] = assign_386_stack_local (DFmode, 0);")
4317 (define_insn "*trunctfdf2_1"
4318 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4320 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4321 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4324 switch (which_alternative)
4327 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4328 return "fstp%z0\t%y0";
4330 return "fst%z0\t%y0";
4336 [(set_attr "type" "fmov,multi,multi,multi")
4337 (set_attr "mode" "DF")])
4339 (define_insn "*trunctfdf2_2"
4340 [(set (match_operand:DF 0 "memory_operand" "=m")
4342 (match_operand:TF 1 "register_operand" "f")))]
4345 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4346 return "fstp%z0\t%y0";
4348 return "fst%z0\t%y0";
4350 [(set_attr "type" "fmov")
4351 (set_attr "mode" "DF")])
4354 [(set (match_operand:DF 0 "memory_operand" "")
4356 (match_operand:TF 1 "register_operand" "")))
4357 (clobber (match_operand:DF 2 "memory_operand" ""))]
4359 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4363 [(set (match_operand:DF 0 "register_operand" "")
4365 (match_operand:TF 1 "register_operand" "")))
4366 (clobber (match_operand:DF 2 "memory_operand" ""))]
4367 "TARGET_80387 && reload_completed"
4368 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4369 (set (match_dup 0) (match_dup 2))]
4373 ;; %%% Break up all these bad boys.
4375 ;; Signed conversion to DImode.
4377 (define_expand "fix_truncxfdi2"
4378 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4379 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4380 "!TARGET_64BIT && TARGET_80387"
4383 (define_expand "fix_trunctfdi2"
4384 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4385 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4389 (define_expand "fix_truncdfdi2"
4390 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4391 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4392 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4394 if (TARGET_64BIT && TARGET_SSE2)
4396 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4397 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4398 if (out != operands[0])
4399 emit_move_insn (operands[0], out);
4404 (define_expand "fix_truncsfdi2"
4405 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4406 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4407 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4409 if (TARGET_SSE && TARGET_64BIT)
4411 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4412 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4413 if (out != operands[0])
4414 emit_move_insn (operands[0], out);
4419 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4420 ;; of the machinery.
4421 (define_insn_and_split "*fix_truncdi_1"
4422 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4423 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4424 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4425 && !reload_completed && !reload_in_progress
4426 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4431 ix86_optimize_mode_switching = 1;
4432 operands[2] = assign_386_stack_local (HImode, 1);
4433 operands[3] = assign_386_stack_local (HImode, 2);
4434 if (memory_operand (operands[0], VOIDmode))
4435 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4436 operands[2], operands[3]));
4439 operands[4] = assign_386_stack_local (DImode, 0);
4440 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4441 operands[2], operands[3],
4446 [(set_attr "type" "fistp")
4447 (set_attr "mode" "DI")])
4449 (define_insn "fix_truncdi_nomemory"
4450 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4451 (fix:DI (match_operand 1 "register_operand" "f,f")))
4452 (use (match_operand:HI 2 "memory_operand" "m,m"))
4453 (use (match_operand:HI 3 "memory_operand" "m,m"))
4454 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4455 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4456 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4457 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4459 [(set_attr "type" "fistp")
4460 (set_attr "mode" "DI")])
4462 (define_insn "fix_truncdi_memory"
4463 [(set (match_operand:DI 0 "memory_operand" "=m")
4464 (fix:DI (match_operand 1 "register_operand" "f")))
4465 (use (match_operand:HI 2 "memory_operand" "m"))
4466 (use (match_operand:HI 3 "memory_operand" "m"))
4467 (clobber (match_scratch:DF 4 "=&1f"))]
4468 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4469 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4470 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4471 [(set_attr "type" "fistp")
4472 (set_attr "mode" "DI")])
4475 [(set (match_operand:DI 0 "register_operand" "")
4476 (fix:DI (match_operand 1 "register_operand" "")))
4477 (use (match_operand:HI 2 "memory_operand" ""))
4478 (use (match_operand:HI 3 "memory_operand" ""))
4479 (clobber (match_operand:DI 4 "memory_operand" ""))
4480 (clobber (match_scratch 5 ""))]
4482 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4485 (clobber (match_dup 5))])
4486 (set (match_dup 0) (match_dup 4))]
4490 [(set (match_operand:DI 0 "memory_operand" "")
4491 (fix:DI (match_operand 1 "register_operand" "")))
4492 (use (match_operand:HI 2 "memory_operand" ""))
4493 (use (match_operand:HI 3 "memory_operand" ""))
4494 (clobber (match_operand:DI 4 "memory_operand" ""))
4495 (clobber (match_scratch 5 ""))]
4497 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4500 (clobber (match_dup 5))])]
4503 ;; When SSE available, it is always faster to use it!
4504 (define_insn "fix_truncsfdi_sse"
4505 [(set (match_operand:DI 0 "register_operand" "=r,r")
4506 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4507 "TARGET_64BIT && TARGET_SSE"
4508 "cvttss2si{q}\t{%1, %0|%0, %1}"
4509 [(set_attr "type" "sseicvt")
4510 (set_attr "mode" "SF")
4511 (set_attr "athlon_decode" "double,vector")])
4513 ;; Avoid vector decoded form of the instruction.
4515 [(match_scratch:SF 2 "x")
4516 (set (match_operand:DI 0 "register_operand" "")
4517 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4518 "TARGET_K8 && !optimize_size"
4519 [(set (match_dup 2) (match_dup 1))
4520 (set (match_dup 0) (fix:DI (match_dup 2)))]
4523 (define_insn "fix_truncdfdi_sse"
4524 [(set (match_operand:DI 0 "register_operand" "=r,r")
4525 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4526 "TARGET_64BIT && TARGET_SSE2"
4527 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4528 [(set_attr "type" "sseicvt,sseicvt")
4529 (set_attr "mode" "DF")
4530 (set_attr "athlon_decode" "double,vector")])
4532 ;; Avoid vector decoded form of the instruction.
4534 [(match_scratch:DF 2 "Y")
4535 (set (match_operand:DI 0 "register_operand" "")
4536 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4537 "TARGET_K8 && !optimize_size"
4538 [(set (match_dup 2) (match_dup 1))
4539 (set (match_dup 0) (fix:DI (match_dup 2)))]
4542 ;; Signed conversion to SImode.
4544 (define_expand "fix_truncxfsi2"
4545 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4546 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4547 "!TARGET_64BIT && TARGET_80387"
4550 (define_expand "fix_trunctfsi2"
4551 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4552 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4556 (define_expand "fix_truncdfsi2"
4557 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4558 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4559 "TARGET_80387 || TARGET_SSE2"
4563 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4564 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4565 if (out != operands[0])
4566 emit_move_insn (operands[0], out);
4571 (define_expand "fix_truncsfsi2"
4572 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4573 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4574 "TARGET_80387 || TARGET_SSE"
4578 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4579 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4580 if (out != operands[0])
4581 emit_move_insn (operands[0], out);
4586 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4587 ;; of the machinery.
4588 (define_insn_and_split "*fix_truncsi_1"
4589 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4590 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4591 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4592 && !reload_completed && !reload_in_progress
4593 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4598 ix86_optimize_mode_switching = 1;
4599 operands[2] = assign_386_stack_local (HImode, 1);
4600 operands[3] = assign_386_stack_local (HImode, 2);
4601 if (memory_operand (operands[0], VOIDmode))
4602 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4603 operands[2], operands[3]));
4606 operands[4] = assign_386_stack_local (SImode, 0);
4607 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4608 operands[2], operands[3],
4613 [(set_attr "type" "fistp")
4614 (set_attr "mode" "SI")])
4616 (define_insn "fix_truncsi_nomemory"
4617 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4618 (fix:SI (match_operand 1 "register_operand" "f,f")))
4619 (use (match_operand:HI 2 "memory_operand" "m,m"))
4620 (use (match_operand:HI 3 "memory_operand" "m,m"))
4621 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4622 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4623 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4625 [(set_attr "type" "fistp")
4626 (set_attr "mode" "SI")])
4628 (define_insn "fix_truncsi_memory"
4629 [(set (match_operand:SI 0 "memory_operand" "=m")
4630 (fix:SI (match_operand 1 "register_operand" "f")))
4631 (use (match_operand:HI 2 "memory_operand" "m"))
4632 (use (match_operand:HI 3 "memory_operand" "m"))]
4633 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4634 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4635 "* return output_fix_trunc (insn, operands);"
4636 [(set_attr "type" "fistp")
4637 (set_attr "mode" "SI")])
4639 ;; When SSE available, it is always faster to use it!
4640 (define_insn "fix_truncsfsi_sse"
4641 [(set (match_operand:SI 0 "register_operand" "=r,r")
4642 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4644 "cvttss2si\t{%1, %0|%0, %1}"
4645 [(set_attr "type" "sseicvt")
4646 (set_attr "mode" "DF")
4647 (set_attr "athlon_decode" "double,vector")])
4649 ;; Avoid vector decoded form of the instruction.
4651 [(match_scratch:SF 2 "x")
4652 (set (match_operand:SI 0 "register_operand" "")
4653 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4654 "TARGET_K8 && !optimize_size"
4655 [(set (match_dup 2) (match_dup 1))
4656 (set (match_dup 0) (fix:SI (match_dup 2)))]
4659 (define_insn "fix_truncdfsi_sse"
4660 [(set (match_operand:SI 0 "register_operand" "=r,r")
4661 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4663 "cvttsd2si\t{%1, %0|%0, %1}"
4664 [(set_attr "type" "sseicvt")
4665 (set_attr "mode" "DF")
4666 (set_attr "athlon_decode" "double,vector")])
4668 ;; Avoid vector decoded form of the instruction.
4670 [(match_scratch:DF 2 "Y")
4671 (set (match_operand:SI 0 "register_operand" "")
4672 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4673 "TARGET_K8 && !optimize_size"
4674 [(set (match_dup 2) (match_dup 1))
4675 (set (match_dup 0) (fix:SI (match_dup 2)))]
4679 [(set (match_operand:SI 0 "register_operand" "")
4680 (fix:SI (match_operand 1 "register_operand" "")))
4681 (use (match_operand:HI 2 "memory_operand" ""))
4682 (use (match_operand:HI 3 "memory_operand" ""))
4683 (clobber (match_operand:SI 4 "memory_operand" ""))]
4685 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4687 (use (match_dup 3))])
4688 (set (match_dup 0) (match_dup 4))]
4692 [(set (match_operand:SI 0 "memory_operand" "")
4693 (fix:SI (match_operand 1 "register_operand" "")))
4694 (use (match_operand:HI 2 "memory_operand" ""))
4695 (use (match_operand:HI 3 "memory_operand" ""))
4696 (clobber (match_operand:SI 4 "memory_operand" ""))]
4698 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4700 (use (match_dup 3))])]
4703 ;; Signed conversion to HImode.
4705 (define_expand "fix_truncxfhi2"
4706 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4707 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4708 "!TARGET_64BIT && TARGET_80387"
4711 (define_expand "fix_trunctfhi2"
4712 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4713 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4717 (define_expand "fix_truncdfhi2"
4718 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4719 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4720 "TARGET_80387 && !TARGET_SSE2"
4723 (define_expand "fix_truncsfhi2"
4724 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4725 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4726 "TARGET_80387 && !TARGET_SSE"
4729 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4730 ;; of the machinery.
4731 (define_insn_and_split "*fix_trunchi_1"
4732 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4733 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4734 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4735 && !reload_completed && !reload_in_progress
4736 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4741 ix86_optimize_mode_switching = 1;
4742 operands[2] = assign_386_stack_local (HImode, 1);
4743 operands[3] = assign_386_stack_local (HImode, 2);
4744 if (memory_operand (operands[0], VOIDmode))
4745 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4746 operands[2], operands[3]));
4749 operands[4] = assign_386_stack_local (HImode, 0);
4750 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4751 operands[2], operands[3],
4756 [(set_attr "type" "fistp")
4757 (set_attr "mode" "HI")])
4759 (define_insn "fix_trunchi_nomemory"
4760 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4761 (fix:HI (match_operand 1 "register_operand" "f,f")))
4762 (use (match_operand:HI 2 "memory_operand" "m,m"))
4763 (use (match_operand:HI 3 "memory_operand" "m,m"))
4764 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4765 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4766 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4768 [(set_attr "type" "fistp")
4769 (set_attr "mode" "HI")])
4771 (define_insn "fix_trunchi_memory"
4772 [(set (match_operand:HI 0 "memory_operand" "=m")
4773 (fix:HI (match_operand 1 "register_operand" "f")))
4774 (use (match_operand:HI 2 "memory_operand" "m"))
4775 (use (match_operand:HI 3 "memory_operand" "m"))]
4776 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4777 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4778 "* return output_fix_trunc (insn, operands);"
4779 [(set_attr "type" "fistp")
4780 (set_attr "mode" "HI")])
4783 [(set (match_operand:HI 0 "memory_operand" "")
4784 (fix:HI (match_operand 1 "register_operand" "")))
4785 (use (match_operand:HI 2 "memory_operand" ""))
4786 (use (match_operand:HI 3 "memory_operand" ""))
4787 (clobber (match_operand:HI 4 "memory_operand" ""))]
4789 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4791 (use (match_dup 3))])]
4795 [(set (match_operand:HI 0 "register_operand" "")
4796 (fix:HI (match_operand 1 "register_operand" "")))
4797 (use (match_operand:HI 2 "memory_operand" ""))
4798 (use (match_operand:HI 3 "memory_operand" ""))
4799 (clobber (match_operand:HI 4 "memory_operand" ""))]
4801 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4804 (clobber (match_dup 4))])
4805 (set (match_dup 0) (match_dup 4))]
4809 (define_insn "x86_fnstcw_1"
4810 [(set (match_operand:HI 0 "memory_operand" "=m")
4811 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4814 [(set_attr "length" "2")
4815 (set_attr "mode" "HI")
4816 (set_attr "unit" "i387")
4817 (set_attr "ppro_uops" "few")])
4819 (define_insn "x86_fldcw_1"
4821 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4824 [(set_attr "length" "2")
4825 (set_attr "mode" "HI")
4826 (set_attr "unit" "i387")
4827 (set_attr "athlon_decode" "vector")
4828 (set_attr "ppro_uops" "few")])
4830 ;; Conversion between fixed point and floating point.
4832 ;; Even though we only accept memory inputs, the backend _really_
4833 ;; wants to be able to do this between registers.
4835 (define_expand "floathisf2"
4836 [(set (match_operand:SF 0 "register_operand" "")
4837 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4838 "TARGET_SSE || TARGET_80387"
4840 if (TARGET_SSE && TARGET_SSE_MATH)
4842 emit_insn (gen_floatsisf2 (operands[0],
4843 convert_to_mode (SImode, operands[1], 0)));
4848 (define_insn "*floathisf2_1"
4849 [(set (match_operand:SF 0 "register_operand" "=f,f")
4850 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4851 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4855 [(set_attr "type" "fmov,multi")
4856 (set_attr "mode" "SF")
4857 (set_attr "fp_int_src" "true")])
4859 (define_expand "floatsisf2"
4860 [(set (match_operand:SF 0 "register_operand" "")
4861 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4862 "TARGET_SSE || TARGET_80387"
4865 (define_insn "*floatsisf2_i387"
4866 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4867 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4868 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4872 cvtsi2ss\t{%1, %0|%0, %1}
4873 cvtsi2ss\t{%1, %0|%0, %1}"
4874 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4875 (set_attr "mode" "SF")
4876 (set_attr "athlon_decode" "*,*,vector,double")
4877 (set_attr "fp_int_src" "true")])
4879 (define_insn "*floatsisf2_sse"
4880 [(set (match_operand:SF 0 "register_operand" "=x,x")
4881 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4883 "cvtsi2ss\t{%1, %0|%0, %1}"
4884 [(set_attr "type" "sseicvt")
4885 (set_attr "mode" "SF")
4886 (set_attr "athlon_decode" "vector,double")
4887 (set_attr "fp_int_src" "true")])
4889 ; Avoid possible reformatting penalty on the destination by first
4892 [(set (match_operand:SF 0 "register_operand" "")
4893 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4894 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4895 && SSE_REG_P (operands[0])"
4899 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4900 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4901 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4905 (define_expand "floatdisf2"
4906 [(set (match_operand:SF 0 "register_operand" "")
4907 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4908 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4911 (define_insn "*floatdisf2_i387_only"
4912 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4913 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4914 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4918 [(set_attr "type" "fmov,multi")
4919 (set_attr "mode" "SF")
4920 (set_attr "fp_int_src" "true")])
4922 (define_insn "*floatdisf2_i387"
4923 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4924 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4925 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4929 cvtsi2ss{q}\t{%1, %0|%0, %1}
4930 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4931 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4932 (set_attr "mode" "SF")
4933 (set_attr "athlon_decode" "*,*,vector,double")
4934 (set_attr "fp_int_src" "true")])
4936 (define_insn "*floatdisf2_sse"
4937 [(set (match_operand:SF 0 "register_operand" "=x,x")
4938 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4939 "TARGET_64BIT && TARGET_SSE"
4940 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4941 [(set_attr "type" "sseicvt")
4942 (set_attr "mode" "SF")
4943 (set_attr "athlon_decode" "vector,double")
4944 (set_attr "fp_int_src" "true")])
4946 ; Avoid possible reformatting penalty on the destination by first
4949 [(set (match_operand:SF 0 "register_operand" "")
4950 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4951 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4952 && SSE_REG_P (operands[0])"
4956 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4957 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4958 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4962 (define_expand "floathidf2"
4963 [(set (match_operand:DF 0 "register_operand" "")
4964 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4965 "TARGET_SSE2 || TARGET_80387"
4967 if (TARGET_SSE && TARGET_SSE_MATH)
4969 emit_insn (gen_floatsidf2 (operands[0],
4970 convert_to_mode (SImode, operands[1], 0)));
4975 (define_insn "*floathidf2_1"
4976 [(set (match_operand:DF 0 "register_operand" "=f,f")
4977 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4978 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4982 [(set_attr "type" "fmov,multi")
4983 (set_attr "mode" "DF")
4984 (set_attr "fp_int_src" "true")])
4986 (define_expand "floatsidf2"
4987 [(set (match_operand:DF 0 "register_operand" "")
4988 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4989 "TARGET_80387 || TARGET_SSE2"
4992 (define_insn "*floatsidf2_i387"
4993 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4994 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4995 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4999 cvtsi2sd\t{%1, %0|%0, %1}
5000 cvtsi2sd\t{%1, %0|%0, %1}"
5001 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5002 (set_attr "mode" "DF")
5003 (set_attr "athlon_decode" "*,*,double,direct")
5004 (set_attr "fp_int_src" "true")])
5006 (define_insn "*floatsidf2_sse"
5007 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5008 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
5010 "cvtsi2sd\t{%1, %0|%0, %1}"
5011 [(set_attr "type" "sseicvt")
5012 (set_attr "mode" "DF")
5013 (set_attr "athlon_decode" "double,direct")
5014 (set_attr "fp_int_src" "true")])
5016 (define_expand "floatdidf2"
5017 [(set (match_operand:DF 0 "register_operand" "")
5018 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5019 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
5022 (define_insn "*floatdidf2_i387_only"
5023 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5024 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5025 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5029 [(set_attr "type" "fmov,multi")
5030 (set_attr "mode" "DF")
5031 (set_attr "fp_int_src" "true")])
5033 (define_insn "*floatdidf2_i387"
5034 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5035 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
5036 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5040 cvtsi2sd{q}\t{%1, %0|%0, %1}
5041 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5042 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5043 (set_attr "mode" "DF")
5044 (set_attr "athlon_decode" "*,*,double,direct")
5045 (set_attr "fp_int_src" "true")])
5047 (define_insn "*floatdidf2_sse"
5048 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5049 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
5051 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5052 [(set_attr "type" "sseicvt")
5053 (set_attr "mode" "DF")
5054 (set_attr "athlon_decode" "double,direct")
5055 (set_attr "fp_int_src" "true")])
5057 (define_insn "floathixf2"
5058 [(set (match_operand:XF 0 "register_operand" "=f,f")
5059 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5060 "!TARGET_64BIT && TARGET_80387"
5064 [(set_attr "type" "fmov,multi")
5065 (set_attr "mode" "XF")
5066 (set_attr "fp_int_src" "true")])
5068 (define_insn "floathitf2"
5069 [(set (match_operand:TF 0 "register_operand" "=f,f")
5070 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5075 [(set_attr "type" "fmov,multi")
5076 (set_attr "mode" "XF")
5077 (set_attr "fp_int_src" "true")])
5079 (define_insn "floatsixf2"
5080 [(set (match_operand:XF 0 "register_operand" "=f,f")
5081 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5082 "!TARGET_64BIT && TARGET_80387"
5086 [(set_attr "type" "fmov,multi")
5087 (set_attr "mode" "XF")
5088 (set_attr "fp_int_src" "true")])
5090 (define_insn "floatsitf2"
5091 [(set (match_operand:TF 0 "register_operand" "=f,f")
5092 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5097 [(set_attr "type" "fmov,multi")
5098 (set_attr "mode" "XF")
5099 (set_attr "fp_int_src" "true")])
5101 (define_insn "floatdixf2"
5102 [(set (match_operand:XF 0 "register_operand" "=f,f")
5103 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5104 "!TARGET_64BIT && TARGET_80387"
5108 [(set_attr "type" "fmov,multi")
5109 (set_attr "mode" "XF")
5110 (set_attr "fp_int_src" "true")])
5112 (define_insn "floatditf2"
5113 [(set (match_operand:TF 0 "register_operand" "=f,f")
5114 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5119 [(set_attr "type" "fmov,multi")
5120 (set_attr "mode" "XF")
5121 (set_attr "fp_int_src" "true")])
5123 ;; %%% Kill these when reload knows how to do it.
5125 [(set (match_operand 0 "fp_register_operand" "")
5126 (float (match_operand 1 "register_operand" "")))]
5127 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
5130 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5131 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5132 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5133 ix86_free_from_memory (GET_MODE (operands[1]));
5137 (define_expand "floatunssisf2"
5138 [(use (match_operand:SF 0 "register_operand" ""))
5139 (use (match_operand:SI 1 "register_operand" ""))]
5140 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
5141 "x86_emit_floatuns (operands); DONE;")
5143 (define_expand "floatunsdisf2"
5144 [(use (match_operand:SF 0 "register_operand" ""))
5145 (use (match_operand:DI 1 "register_operand" ""))]
5146 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
5147 "x86_emit_floatuns (operands); DONE;")
5149 (define_expand "floatunsdidf2"
5150 [(use (match_operand:DF 0 "register_operand" ""))
5151 (use (match_operand:DI 1 "register_operand" ""))]
5152 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
5153 "x86_emit_floatuns (operands); DONE;")
5157 ;; %%% splits for addsidi3
5158 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5159 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5160 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5162 (define_expand "adddi3"
5163 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5164 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5165 (match_operand:DI 2 "x86_64_general_operand" "")))
5166 (clobber (reg:CC 17))]
5168 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5170 (define_insn "*adddi3_1"
5171 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5172 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5173 (match_operand:DI 2 "general_operand" "roiF,riF")))
5174 (clobber (reg:CC 17))]
5175 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5179 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5180 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5181 (match_operand:DI 2 "general_operand" "")))
5182 (clobber (reg:CC 17))]
5183 "!TARGET_64BIT && reload_completed"
5184 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
5186 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5187 (parallel [(set (match_dup 3)
5188 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5191 (clobber (reg:CC 17))])]
5192 "split_di (operands+0, 1, operands+0, operands+3);
5193 split_di (operands+1, 1, operands+1, operands+4);
5194 split_di (operands+2, 1, operands+2, operands+5);")
5196 (define_insn "adddi3_carry_rex64"
5197 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5198 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5199 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5200 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5201 (clobber (reg:CC 17))]
5202 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5203 "adc{q}\t{%2, %0|%0, %2}"
5204 [(set_attr "type" "alu")
5205 (set_attr "pent_pair" "pu")
5206 (set_attr "mode" "DI")
5207 (set_attr "ppro_uops" "few")])
5209 (define_insn "*adddi3_cc_rex64"
5211 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5212 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5214 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5215 (plus:DI (match_dup 1) (match_dup 2)))]
5216 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5217 "add{q}\t{%2, %0|%0, %2}"
5218 [(set_attr "type" "alu")
5219 (set_attr "mode" "DI")])
5221 (define_insn "addqi3_carry"
5222 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
5223 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5224 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5225 (match_operand:QI 2 "general_operand" "ri,rm")))
5226 (clobber (reg:CC 17))]
5227 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5228 "adc{b}\t{%2, %0|%0, %2}"
5229 [(set_attr "type" "alu")
5230 (set_attr "pent_pair" "pu")
5231 (set_attr "mode" "QI")
5232 (set_attr "ppro_uops" "few")])
5234 (define_insn "addhi3_carry"
5235 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5236 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5237 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5238 (match_operand:HI 2 "general_operand" "ri,rm")))
5239 (clobber (reg:CC 17))]
5240 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5241 "adc{w}\t{%2, %0|%0, %2}"
5242 [(set_attr "type" "alu")
5243 (set_attr "pent_pair" "pu")
5244 (set_attr "mode" "HI")
5245 (set_attr "ppro_uops" "few")])
5247 (define_insn "addsi3_carry"
5248 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5249 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5250 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5251 (match_operand:SI 2 "general_operand" "ri,rm")))
5252 (clobber (reg:CC 17))]
5253 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5254 "adc{l}\t{%2, %0|%0, %2}"
5255 [(set_attr "type" "alu")
5256 (set_attr "pent_pair" "pu")
5257 (set_attr "mode" "SI")
5258 (set_attr "ppro_uops" "few")])
5260 (define_insn "*addsi3_carry_zext"
5261 [(set (match_operand:DI 0 "register_operand" "=r")
5263 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5264 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5265 (match_operand:SI 2 "general_operand" "rim"))))
5266 (clobber (reg:CC 17))]
5267 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5268 "adc{l}\t{%2, %k0|%k0, %2}"
5269 [(set_attr "type" "alu")
5270 (set_attr "pent_pair" "pu")
5271 (set_attr "mode" "SI")
5272 (set_attr "ppro_uops" "few")])
5274 (define_insn "*addsi3_cc"
5276 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5277 (match_operand:SI 2 "general_operand" "ri,rm")]
5279 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5280 (plus:SI (match_dup 1) (match_dup 2)))]
5281 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5282 "add{l}\t{%2, %0|%0, %2}"
5283 [(set_attr "type" "alu")
5284 (set_attr "mode" "SI")])
5286 (define_insn "addqi3_cc"
5288 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5289 (match_operand:QI 2 "general_operand" "qi,qm")]
5291 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5292 (plus:QI (match_dup 1) (match_dup 2)))]
5293 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5294 "add{b}\t{%2, %0|%0, %2}"
5295 [(set_attr "type" "alu")
5296 (set_attr "mode" "QI")])
5298 (define_expand "addsi3"
5299 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5300 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5301 (match_operand:SI 2 "general_operand" "")))
5302 (clobber (reg:CC 17))])]
5304 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5306 (define_insn "*lea_1"
5307 [(set (match_operand:SI 0 "register_operand" "=r")
5308 (match_operand:SI 1 "address_operand" "p"))]
5310 "lea{l}\t{%a1, %0|%0, %a1}"
5311 [(set_attr "type" "lea")
5312 (set_attr "mode" "SI")])
5314 (define_insn "*lea_1_rex64"
5315 [(set (match_operand:SI 0 "register_operand" "=r")
5316 (subreg:SI (match_operand:DI 1 "address_operand" "p") 0))]
5318 "lea{l}\t{%a1, %0|%0, %a1}"
5319 [(set_attr "type" "lea")
5320 (set_attr "mode" "SI")])
5322 (define_insn "*lea_1_zext"
5323 [(set (match_operand:DI 0 "register_operand" "=r")
5324 (zero_extend:DI (subreg:SI (match_operand:DI 1 "address_operand" "p") 0)))]
5326 "lea{l}\t{%a1, %k0|%k0, %a1}"
5327 [(set_attr "type" "lea")
5328 (set_attr "mode" "SI")])
5330 (define_insn "*lea_2_rex64"
5331 [(set (match_operand:DI 0 "register_operand" "=r")
5332 (match_operand:DI 1 "address_operand" "p"))]
5334 "lea{q}\t{%a1, %0|%0, %a1}"
5335 [(set_attr "type" "lea")
5336 (set_attr "mode" "DI")])
5338 ;; The lea patterns for non-Pmodes needs to be matched by several
5339 ;; insns converted to real lea by splitters.
5341 (define_insn_and_split "*lea_general_1"
5342 [(set (match_operand 0 "register_operand" "=r")
5343 (plus (plus (match_operand 1 "index_register_operand" "r")
5344 (match_operand 2 "register_operand" "r"))
5345 (match_operand 3 "immediate_operand" "i")))]
5346 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5347 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5348 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5349 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5350 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5351 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5352 || GET_MODE (operands[3]) == VOIDmode)"
5354 "&& reload_completed"
5358 operands[0] = gen_lowpart (SImode, operands[0]);
5359 operands[1] = gen_lowpart (Pmode, operands[1]);
5360 operands[2] = gen_lowpart (Pmode, operands[2]);
5361 operands[3] = gen_lowpart (Pmode, operands[3]);
5362 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5364 if (Pmode != SImode)
5365 pat = gen_rtx_SUBREG (SImode, pat, 0);
5366 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5369 [(set_attr "type" "lea")
5370 (set_attr "mode" "SI")])
5372 (define_insn_and_split "*lea_general_1_zext"
5373 [(set (match_operand:DI 0 "register_operand" "=r")
5375 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5376 (match_operand:SI 2 "register_operand" "r"))
5377 (match_operand:SI 3 "immediate_operand" "i"))))]
5380 "&& reload_completed"
5382 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5384 (match_dup 3)) 0)))]
5386 operands[1] = gen_lowpart (Pmode, operands[1]);
5387 operands[2] = gen_lowpart (Pmode, operands[2]);
5388 operands[3] = gen_lowpart (Pmode, operands[3]);
5390 [(set_attr "type" "lea")
5391 (set_attr "mode" "SI")])
5393 (define_insn_and_split "*lea_general_2"
5394 [(set (match_operand 0 "register_operand" "=r")
5395 (plus (mult (match_operand 1 "index_register_operand" "r")
5396 (match_operand 2 "const248_operand" "i"))
5397 (match_operand 3 "nonmemory_operand" "ri")))]
5398 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5399 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5400 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5401 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5402 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5403 || GET_MODE (operands[3]) == VOIDmode)"
5405 "&& reload_completed"
5409 operands[0] = gen_lowpart (SImode, operands[0]);
5410 operands[1] = gen_lowpart (Pmode, operands[1]);
5411 operands[3] = gen_lowpart (Pmode, operands[3]);
5412 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5414 if (Pmode != SImode)
5415 pat = gen_rtx_SUBREG (SImode, pat, 0);
5416 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5419 [(set_attr "type" "lea")
5420 (set_attr "mode" "SI")])
5422 (define_insn_and_split "*lea_general_2_zext"
5423 [(set (match_operand:DI 0 "register_operand" "=r")
5425 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5426 (match_operand:SI 2 "const248_operand" "n"))
5427 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5430 "&& reload_completed"
5432 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5434 (match_dup 3)) 0)))]
5436 operands[1] = gen_lowpart (Pmode, operands[1]);
5437 operands[3] = gen_lowpart (Pmode, operands[3]);
5439 [(set_attr "type" "lea")
5440 (set_attr "mode" "SI")])
5442 (define_insn_and_split "*lea_general_3"
5443 [(set (match_operand 0 "register_operand" "=r")
5444 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5445 (match_operand 2 "const248_operand" "i"))
5446 (match_operand 3 "register_operand" "r"))
5447 (match_operand 4 "immediate_operand" "i")))]
5448 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5449 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5450 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5451 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5452 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5454 "&& reload_completed"
5458 operands[0] = gen_lowpart (SImode, operands[0]);
5459 operands[1] = gen_lowpart (Pmode, operands[1]);
5460 operands[3] = gen_lowpart (Pmode, operands[3]);
5461 operands[4] = gen_lowpart (Pmode, operands[4]);
5462 pat = gen_rtx_PLUS (Pmode,
5463 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5467 if (Pmode != SImode)
5468 pat = gen_rtx_SUBREG (SImode, pat, 0);
5469 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5472 [(set_attr "type" "lea")
5473 (set_attr "mode" "SI")])
5475 (define_insn_and_split "*lea_general_3_zext"
5476 [(set (match_operand:DI 0 "register_operand" "=r")
5478 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5479 (match_operand:SI 2 "const248_operand" "n"))
5480 (match_operand:SI 3 "register_operand" "r"))
5481 (match_operand:SI 4 "immediate_operand" "i"))))]
5484 "&& reload_completed"
5486 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5489 (match_dup 4)) 0)))]
5491 operands[1] = gen_lowpart (Pmode, operands[1]);
5492 operands[3] = gen_lowpart (Pmode, operands[3]);
5493 operands[4] = gen_lowpart (Pmode, operands[4]);
5495 [(set_attr "type" "lea")
5496 (set_attr "mode" "SI")])
5498 (define_insn "*adddi_1_rex64"
5499 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5500 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5501 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5502 (clobber (reg:CC 17))]
5503 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5505 switch (get_attr_type (insn))
5508 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5509 return "lea{q}\t{%a2, %0|%0, %a2}";
5512 if (! rtx_equal_p (operands[0], operands[1]))
5514 if (operands[2] == const1_rtx)
5515 return "inc{q}\t%0";
5516 else if (operands[2] == constm1_rtx)
5517 return "dec{q}\t%0";
5522 if (! rtx_equal_p (operands[0], operands[1]))
5525 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5526 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5527 if (GET_CODE (operands[2]) == CONST_INT
5528 /* Avoid overflows. */
5529 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5530 && (INTVAL (operands[2]) == 128
5531 || (INTVAL (operands[2]) < 0
5532 && INTVAL (operands[2]) != -128)))
5534 operands[2] = GEN_INT (-INTVAL (operands[2]));
5535 return "sub{q}\t{%2, %0|%0, %2}";
5537 return "add{q}\t{%2, %0|%0, %2}";
5541 (cond [(eq_attr "alternative" "2")
5542 (const_string "lea")
5543 ; Current assemblers are broken and do not allow @GOTOFF in
5544 ; ought but a memory context.
5545 (match_operand:DI 2 "pic_symbolic_operand" "")
5546 (const_string "lea")
5547 (match_operand:DI 2 "incdec_operand" "")
5548 (const_string "incdec")
5550 (const_string "alu")))
5551 (set_attr "mode" "DI")])
5553 ;; Convert lea to the lea pattern to avoid flags dependency.
5555 [(set (match_operand:DI 0 "register_operand" "")
5556 (plus:DI (match_operand:DI 1 "register_operand" "")
5557 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5558 (clobber (reg:CC 17))]
5559 "TARGET_64BIT && reload_completed
5560 && true_regnum (operands[0]) != true_regnum (operands[1])"
5562 (plus:DI (match_dup 1)
5566 (define_insn "*adddi_2_rex64"
5569 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5570 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5572 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5573 (plus:DI (match_dup 1) (match_dup 2)))]
5574 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5575 && ix86_binary_operator_ok (PLUS, DImode, operands)
5576 /* Current assemblers are broken and do not allow @GOTOFF in
5577 ought but a memory context. */
5578 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5580 switch (get_attr_type (insn))
5583 if (! rtx_equal_p (operands[0], operands[1]))
5585 if (operands[2] == const1_rtx)
5586 return "inc{q}\t%0";
5587 else if (operands[2] == constm1_rtx)
5588 return "dec{q}\t%0";
5593 if (! rtx_equal_p (operands[0], operands[1]))
5595 /* ???? We ought to handle there the 32bit case too
5596 - do we need new constraint? */
5597 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5598 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5599 if (GET_CODE (operands[2]) == CONST_INT
5600 /* Avoid overflows. */
5601 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5602 && (INTVAL (operands[2]) == 128
5603 || (INTVAL (operands[2]) < 0
5604 && INTVAL (operands[2]) != -128)))
5606 operands[2] = GEN_INT (-INTVAL (operands[2]));
5607 return "sub{q}\t{%2, %0|%0, %2}";
5609 return "add{q}\t{%2, %0|%0, %2}";
5613 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5614 (const_string "incdec")
5615 (const_string "alu")))
5616 (set_attr "mode" "DI")])
5618 (define_insn "*adddi_3_rex64"
5620 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5621 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5622 (clobber (match_scratch:DI 0 "=r"))]
5624 && ix86_match_ccmode (insn, CCZmode)
5625 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5626 /* Current assemblers are broken and do not allow @GOTOFF in
5627 ought but a memory context. */
5628 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5630 switch (get_attr_type (insn))
5633 if (! rtx_equal_p (operands[0], operands[1]))
5635 if (operands[2] == const1_rtx)
5636 return "inc{q}\t%0";
5637 else if (operands[2] == constm1_rtx)
5638 return "dec{q}\t%0";
5643 if (! rtx_equal_p (operands[0], operands[1]))
5645 /* ???? We ought to handle there the 32bit case too
5646 - do we need new constraint? */
5647 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5648 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5649 if (GET_CODE (operands[2]) == CONST_INT
5650 /* Avoid overflows. */
5651 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5652 && (INTVAL (operands[2]) == 128
5653 || (INTVAL (operands[2]) < 0
5654 && INTVAL (operands[2]) != -128)))
5656 operands[2] = GEN_INT (-INTVAL (operands[2]));
5657 return "sub{q}\t{%2, %0|%0, %2}";
5659 return "add{q}\t{%2, %0|%0, %2}";
5663 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5664 (const_string "incdec")
5665 (const_string "alu")))
5666 (set_attr "mode" "DI")])
5668 ; For comparisons against 1, -1 and 128, we may generate better code
5669 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5670 ; is matched then. We can't accept general immediate, because for
5671 ; case of overflows, the result is messed up.
5672 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5674 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5675 ; only for comparisons not depending on it.
5676 (define_insn "*adddi_4_rex64"
5678 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5679 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5680 (clobber (match_scratch:DI 0 "=rm"))]
5682 && ix86_match_ccmode (insn, CCGCmode)"
5684 switch (get_attr_type (insn))
5687 if (operands[2] == constm1_rtx)
5688 return "inc{q}\t%0";
5689 else if (operands[2] == const1_rtx)
5690 return "dec{q}\t%0";
5695 if (! rtx_equal_p (operands[0], operands[1]))
5697 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5698 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5699 if ((INTVAL (operands[2]) == -128
5700 || (INTVAL (operands[2]) > 0
5701 && INTVAL (operands[2]) != 128))
5702 /* Avoid overflows. */
5703 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5704 return "sub{q}\t{%2, %0|%0, %2}";
5705 operands[2] = GEN_INT (-INTVAL (operands[2]));
5706 return "add{q}\t{%2, %0|%0, %2}";
5710 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5711 (const_string "incdec")
5712 (const_string "alu")))
5713 (set_attr "mode" "DI")])
5715 (define_insn "*adddi_5_rex64"
5718 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5719 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5721 (clobber (match_scratch:DI 0 "=r"))]
5723 && ix86_match_ccmode (insn, CCGOCmode)
5724 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5725 /* Current assemblers are broken and do not allow @GOTOFF in
5726 ought but a memory context. */
5727 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5729 switch (get_attr_type (insn))
5732 if (! rtx_equal_p (operands[0], operands[1]))
5734 if (operands[2] == const1_rtx)
5735 return "inc{q}\t%0";
5736 else if (operands[2] == constm1_rtx)
5737 return "dec{q}\t%0";
5742 if (! rtx_equal_p (operands[0], operands[1]))
5744 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5745 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5746 if (GET_CODE (operands[2]) == CONST_INT
5747 /* Avoid overflows. */
5748 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5749 && (INTVAL (operands[2]) == 128
5750 || (INTVAL (operands[2]) < 0
5751 && INTVAL (operands[2]) != -128)))
5753 operands[2] = GEN_INT (-INTVAL (operands[2]));
5754 return "sub{q}\t{%2, %0|%0, %2}";
5756 return "add{q}\t{%2, %0|%0, %2}";
5760 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5761 (const_string "incdec")
5762 (const_string "alu")))
5763 (set_attr "mode" "DI")])
5766 (define_insn "*addsi_1"
5767 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5768 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5769 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5770 (clobber (reg:CC 17))]
5771 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5773 switch (get_attr_type (insn))
5776 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5777 return "lea{l}\t{%a2, %0|%0, %a2}";
5780 if (! rtx_equal_p (operands[0], operands[1]))
5782 if (operands[2] == const1_rtx)
5783 return "inc{l}\t%0";
5784 else if (operands[2] == constm1_rtx)
5785 return "dec{l}\t%0";
5790 if (! rtx_equal_p (operands[0], operands[1]))
5793 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5794 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5795 if (GET_CODE (operands[2]) == CONST_INT
5796 && (INTVAL (operands[2]) == 128
5797 || (INTVAL (operands[2]) < 0
5798 && INTVAL (operands[2]) != -128)))
5800 operands[2] = GEN_INT (-INTVAL (operands[2]));
5801 return "sub{l}\t{%2, %0|%0, %2}";
5803 return "add{l}\t{%2, %0|%0, %2}";
5807 (cond [(eq_attr "alternative" "2")
5808 (const_string "lea")
5809 ; Current assemblers are broken and do not allow @GOTOFF in
5810 ; ought but a memory context.
5811 (match_operand:SI 2 "pic_symbolic_operand" "")
5812 (const_string "lea")
5813 (match_operand:SI 2 "incdec_operand" "")
5814 (const_string "incdec")
5816 (const_string "alu")))
5817 (set_attr "mode" "SI")])
5819 ;; Convert lea to the lea pattern to avoid flags dependency.
5821 [(set (match_operand 0 "register_operand" "")
5822 (plus (match_operand 1 "register_operand" "")
5823 (match_operand 2 "nonmemory_operand" "")))
5824 (clobber (reg:CC 17))]
5826 && true_regnum (operands[0]) != true_regnum (operands[1])"
5830 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5831 may confuse gen_lowpart. */
5832 if (GET_MODE (operands[0]) != Pmode)
5834 operands[1] = gen_lowpart (Pmode, operands[1]);
5835 operands[2] = gen_lowpart (Pmode, operands[2]);
5837 operands[0] = gen_lowpart (SImode, operands[0]);
5838 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5839 if (Pmode != SImode)
5840 pat = gen_rtx_SUBREG (SImode, pat, 0);
5841 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5845 ;; It may seem that nonimmediate operand is proper one for operand 1.
5846 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5847 ;; we take care in ix86_binary_operator_ok to not allow two memory
5848 ;; operands so proper swapping will be done in reload. This allow
5849 ;; patterns constructed from addsi_1 to match.
5850 (define_insn "addsi_1_zext"
5851 [(set (match_operand:DI 0 "register_operand" "=r,r")
5853 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5854 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5855 (clobber (reg:CC 17))]
5856 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5858 switch (get_attr_type (insn))
5861 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5862 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5865 if (operands[2] == const1_rtx)
5866 return "inc{l}\t%k0";
5867 else if (operands[2] == constm1_rtx)
5868 return "dec{l}\t%k0";
5873 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5874 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5875 if (GET_CODE (operands[2]) == CONST_INT
5876 && (INTVAL (operands[2]) == 128
5877 || (INTVAL (operands[2]) < 0
5878 && INTVAL (operands[2]) != -128)))
5880 operands[2] = GEN_INT (-INTVAL (operands[2]));
5881 return "sub{l}\t{%2, %k0|%k0, %2}";
5883 return "add{l}\t{%2, %k0|%k0, %2}";
5887 (cond [(eq_attr "alternative" "1")
5888 (const_string "lea")
5889 ; Current assemblers are broken and do not allow @GOTOFF in
5890 ; ought but a memory context.
5891 (match_operand:SI 2 "pic_symbolic_operand" "")
5892 (const_string "lea")
5893 (match_operand:SI 2 "incdec_operand" "")
5894 (const_string "incdec")
5896 (const_string "alu")))
5897 (set_attr "mode" "SI")])
5899 ;; Convert lea to the lea pattern to avoid flags dependency.
5901 [(set (match_operand:DI 0 "register_operand" "")
5903 (plus:SI (match_operand:SI 1 "register_operand" "")
5904 (match_operand:SI 2 "nonmemory_operand" ""))))
5905 (clobber (reg:CC 17))]
5906 "TARGET_64BIT && reload_completed
5907 && true_regnum (operands[0]) != true_regnum (operands[1])"
5909 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5911 operands[1] = gen_lowpart (Pmode, operands[1]);
5912 operands[2] = gen_lowpart (Pmode, operands[2]);
5915 (define_insn "*addsi_2"
5918 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5919 (match_operand:SI 2 "general_operand" "rmni,rni"))
5921 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5922 (plus:SI (match_dup 1) (match_dup 2)))]
5923 "ix86_match_ccmode (insn, CCGOCmode)
5924 && ix86_binary_operator_ok (PLUS, SImode, operands)
5925 /* Current assemblers are broken and do not allow @GOTOFF in
5926 ought but a memory context. */
5927 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5929 switch (get_attr_type (insn))
5932 if (! rtx_equal_p (operands[0], operands[1]))
5934 if (operands[2] == const1_rtx)
5935 return "inc{l}\t%0";
5936 else if (operands[2] == constm1_rtx)
5937 return "dec{l}\t%0";
5942 if (! rtx_equal_p (operands[0], operands[1]))
5944 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5945 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5946 if (GET_CODE (operands[2]) == CONST_INT
5947 && (INTVAL (operands[2]) == 128
5948 || (INTVAL (operands[2]) < 0
5949 && INTVAL (operands[2]) != -128)))
5951 operands[2] = GEN_INT (-INTVAL (operands[2]));
5952 return "sub{l}\t{%2, %0|%0, %2}";
5954 return "add{l}\t{%2, %0|%0, %2}";
5958 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5959 (const_string "incdec")
5960 (const_string "alu")))
5961 (set_attr "mode" "SI")])
5963 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5964 (define_insn "*addsi_2_zext"
5967 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5968 (match_operand:SI 2 "general_operand" "rmni"))
5970 (set (match_operand:DI 0 "register_operand" "=r")
5971 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5972 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5973 && ix86_binary_operator_ok (PLUS, SImode, operands)
5974 /* Current assemblers are broken and do not allow @GOTOFF in
5975 ought but a memory context. */
5976 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5978 switch (get_attr_type (insn))
5981 if (operands[2] == const1_rtx)
5982 return "inc{l}\t%k0";
5983 else if (operands[2] == constm1_rtx)
5984 return "dec{l}\t%k0";
5989 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5990 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5991 if (GET_CODE (operands[2]) == CONST_INT
5992 && (INTVAL (operands[2]) == 128
5993 || (INTVAL (operands[2]) < 0
5994 && INTVAL (operands[2]) != -128)))
5996 operands[2] = GEN_INT (-INTVAL (operands[2]));
5997 return "sub{l}\t{%2, %k0|%k0, %2}";
5999 return "add{l}\t{%2, %k0|%k0, %2}";
6003 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6004 (const_string "incdec")
6005 (const_string "alu")))
6006 (set_attr "mode" "SI")])
6008 (define_insn "*addsi_3"
6010 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6011 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6012 (clobber (match_scratch:SI 0 "=r"))]
6013 "ix86_match_ccmode (insn, CCZmode)
6014 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6015 /* Current assemblers are broken and do not allow @GOTOFF in
6016 ought but a memory context. */
6017 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6019 switch (get_attr_type (insn))
6022 if (! rtx_equal_p (operands[0], operands[1]))
6024 if (operands[2] == const1_rtx)
6025 return "inc{l}\t%0";
6026 else if (operands[2] == constm1_rtx)
6027 return "dec{l}\t%0";
6032 if (! rtx_equal_p (operands[0], operands[1]))
6034 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6035 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6036 if (GET_CODE (operands[2]) == CONST_INT
6037 && (INTVAL (operands[2]) == 128
6038 || (INTVAL (operands[2]) < 0
6039 && INTVAL (operands[2]) != -128)))
6041 operands[2] = GEN_INT (-INTVAL (operands[2]));
6042 return "sub{l}\t{%2, %0|%0, %2}";
6044 return "add{l}\t{%2, %0|%0, %2}";
6048 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6049 (const_string "incdec")
6050 (const_string "alu")))
6051 (set_attr "mode" "SI")])
6053 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6054 (define_insn "*addsi_3_zext"
6056 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6057 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6058 (set (match_operand:DI 0 "register_operand" "=r")
6059 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6060 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6061 && ix86_binary_operator_ok (PLUS, SImode, operands)
6062 /* Current assemblers are broken and do not allow @GOTOFF in
6063 ought but a memory context. */
6064 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6066 switch (get_attr_type (insn))
6069 if (operands[2] == const1_rtx)
6070 return "inc{l}\t%k0";
6071 else if (operands[2] == constm1_rtx)
6072 return "dec{l}\t%k0";
6077 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6078 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6079 if (GET_CODE (operands[2]) == CONST_INT
6080 && (INTVAL (operands[2]) == 128
6081 || (INTVAL (operands[2]) < 0
6082 && INTVAL (operands[2]) != -128)))
6084 operands[2] = GEN_INT (-INTVAL (operands[2]));
6085 return "sub{l}\t{%2, %k0|%k0, %2}";
6087 return "add{l}\t{%2, %k0|%k0, %2}";
6091 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6092 (const_string "incdec")
6093 (const_string "alu")))
6094 (set_attr "mode" "SI")])
6096 ; For comparisons against 1, -1 and 128, we may generate better code
6097 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6098 ; is matched then. We can't accept general immediate, because for
6099 ; case of overflows, the result is messed up.
6100 ; This pattern also don't hold of 0x80000000, since the value overflows
6102 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6103 ; only for comparisons not depending on it.
6104 (define_insn "*addsi_4"
6106 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6107 (match_operand:SI 2 "const_int_operand" "n")))
6108 (clobber (match_scratch:SI 0 "=rm"))]
6109 "ix86_match_ccmode (insn, CCGCmode)
6110 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6112 switch (get_attr_type (insn))
6115 if (operands[2] == constm1_rtx)
6116 return "inc{l}\t%0";
6117 else if (operands[2] == const1_rtx)
6118 return "dec{l}\t%0";
6123 if (! rtx_equal_p (operands[0], operands[1]))
6125 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6126 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6127 if ((INTVAL (operands[2]) == -128
6128 || (INTVAL (operands[2]) > 0
6129 && INTVAL (operands[2]) != 128)))
6130 return "sub{l}\t{%2, %0|%0, %2}";
6131 operands[2] = GEN_INT (-INTVAL (operands[2]));
6132 return "add{l}\t{%2, %0|%0, %2}";
6136 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6137 (const_string "incdec")
6138 (const_string "alu")))
6139 (set_attr "mode" "SI")])
6141 (define_insn "*addsi_5"
6144 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6145 (match_operand:SI 2 "general_operand" "rmni"))
6147 (clobber (match_scratch:SI 0 "=r"))]
6148 "ix86_match_ccmode (insn, CCGOCmode)
6149 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6150 /* Current assemblers are broken and do not allow @GOTOFF in
6151 ought but a memory context. */
6152 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6154 switch (get_attr_type (insn))
6157 if (! rtx_equal_p (operands[0], operands[1]))
6159 if (operands[2] == const1_rtx)
6160 return "inc{l}\t%0";
6161 else if (operands[2] == constm1_rtx)
6162 return "dec{l}\t%0";
6167 if (! rtx_equal_p (operands[0], operands[1]))
6169 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6170 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6171 if (GET_CODE (operands[2]) == CONST_INT
6172 && (INTVAL (operands[2]) == 128
6173 || (INTVAL (operands[2]) < 0
6174 && INTVAL (operands[2]) != -128)))
6176 operands[2] = GEN_INT (-INTVAL (operands[2]));
6177 return "sub{l}\t{%2, %0|%0, %2}";
6179 return "add{l}\t{%2, %0|%0, %2}";
6183 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6184 (const_string "incdec")
6185 (const_string "alu")))
6186 (set_attr "mode" "SI")])
6188 (define_expand "addhi3"
6189 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6190 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6191 (match_operand:HI 2 "general_operand" "")))
6192 (clobber (reg:CC 17))])]
6193 "TARGET_HIMODE_MATH"
6194 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6196 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6197 ;; type optimizations enabled by define-splits. This is not important
6198 ;; for PII, and in fact harmful because of partial register stalls.
6200 (define_insn "*addhi_1_lea"
6201 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6202 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6203 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6204 (clobber (reg:CC 17))]
6205 "!TARGET_PARTIAL_REG_STALL
6206 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6208 switch (get_attr_type (insn))
6213 if (operands[2] == const1_rtx)
6214 return "inc{w}\t%0";
6215 else if (operands[2] == constm1_rtx)
6216 return "dec{w}\t%0";
6220 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6221 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6222 if (GET_CODE (operands[2]) == CONST_INT
6223 && (INTVAL (operands[2]) == 128
6224 || (INTVAL (operands[2]) < 0
6225 && INTVAL (operands[2]) != -128)))
6227 operands[2] = GEN_INT (-INTVAL (operands[2]));
6228 return "sub{w}\t{%2, %0|%0, %2}";
6230 return "add{w}\t{%2, %0|%0, %2}";
6234 (if_then_else (eq_attr "alternative" "2")
6235 (const_string "lea")
6236 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6237 (const_string "incdec")
6238 (const_string "alu"))))
6239 (set_attr "mode" "HI,HI,SI")])
6241 (define_insn "*addhi_1"
6242 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6243 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6244 (match_operand:HI 2 "general_operand" "ri,rm")))
6245 (clobber (reg:CC 17))]
6246 "TARGET_PARTIAL_REG_STALL
6247 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6249 switch (get_attr_type (insn))
6252 if (operands[2] == const1_rtx)
6253 return "inc{w}\t%0";
6254 else if (operands[2] == constm1_rtx)
6255 return "dec{w}\t%0";
6259 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6260 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6261 if (GET_CODE (operands[2]) == CONST_INT
6262 && (INTVAL (operands[2]) == 128
6263 || (INTVAL (operands[2]) < 0
6264 && INTVAL (operands[2]) != -128)))
6266 operands[2] = GEN_INT (-INTVAL (operands[2]));
6267 return "sub{w}\t{%2, %0|%0, %2}";
6269 return "add{w}\t{%2, %0|%0, %2}";
6273 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6274 (const_string "incdec")
6275 (const_string "alu")))
6276 (set_attr "mode" "HI")])
6278 (define_insn "*addhi_2"
6281 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6282 (match_operand:HI 2 "general_operand" "rmni,rni"))
6284 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6285 (plus:HI (match_dup 1) (match_dup 2)))]
6286 "ix86_match_ccmode (insn, CCGOCmode)
6287 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6289 switch (get_attr_type (insn))
6292 if (operands[2] == const1_rtx)
6293 return "inc{w}\t%0";
6294 else if (operands[2] == constm1_rtx)
6295 return "dec{w}\t%0";
6299 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6300 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6301 if (GET_CODE (operands[2]) == CONST_INT
6302 && (INTVAL (operands[2]) == 128
6303 || (INTVAL (operands[2]) < 0
6304 && INTVAL (operands[2]) != -128)))
6306 operands[2] = GEN_INT (-INTVAL (operands[2]));
6307 return "sub{w}\t{%2, %0|%0, %2}";
6309 return "add{w}\t{%2, %0|%0, %2}";
6313 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6314 (const_string "incdec")
6315 (const_string "alu")))
6316 (set_attr "mode" "HI")])
6318 (define_insn "*addhi_3"
6320 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6321 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6322 (clobber (match_scratch:HI 0 "=r"))]
6323 "ix86_match_ccmode (insn, CCZmode)
6324 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6326 switch (get_attr_type (insn))
6329 if (operands[2] == const1_rtx)
6330 return "inc{w}\t%0";
6331 else if (operands[2] == constm1_rtx)
6332 return "dec{w}\t%0";
6336 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6337 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6338 if (GET_CODE (operands[2]) == CONST_INT
6339 && (INTVAL (operands[2]) == 128
6340 || (INTVAL (operands[2]) < 0
6341 && INTVAL (operands[2]) != -128)))
6343 operands[2] = GEN_INT (-INTVAL (operands[2]));
6344 return "sub{w}\t{%2, %0|%0, %2}";
6346 return "add{w}\t{%2, %0|%0, %2}";
6350 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6351 (const_string "incdec")
6352 (const_string "alu")))
6353 (set_attr "mode" "HI")])
6355 ; See comments above addsi_3_imm for details.
6356 (define_insn "*addhi_4"
6358 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6359 (match_operand:HI 2 "const_int_operand" "n")))
6360 (clobber (match_scratch:HI 0 "=rm"))]
6361 "ix86_match_ccmode (insn, CCGCmode)
6362 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6364 switch (get_attr_type (insn))
6367 if (operands[2] == constm1_rtx)
6368 return "inc{w}\t%0";
6369 else if (operands[2] == const1_rtx)
6370 return "dec{w}\t%0";
6375 if (! rtx_equal_p (operands[0], operands[1]))
6377 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6378 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6379 if ((INTVAL (operands[2]) == -128
6380 || (INTVAL (operands[2]) > 0
6381 && INTVAL (operands[2]) != 128)))
6382 return "sub{w}\t{%2, %0|%0, %2}";
6383 operands[2] = GEN_INT (-INTVAL (operands[2]));
6384 return "add{w}\t{%2, %0|%0, %2}";
6388 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6389 (const_string "incdec")
6390 (const_string "alu")))
6391 (set_attr "mode" "SI")])
6394 (define_insn "*addhi_5"
6397 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6398 (match_operand:HI 2 "general_operand" "rmni"))
6400 (clobber (match_scratch:HI 0 "=r"))]
6401 "ix86_match_ccmode (insn, CCGOCmode)
6402 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6404 switch (get_attr_type (insn))
6407 if (operands[2] == const1_rtx)
6408 return "inc{w}\t%0";
6409 else if (operands[2] == constm1_rtx)
6410 return "dec{w}\t%0";
6414 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6415 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6416 if (GET_CODE (operands[2]) == CONST_INT
6417 && (INTVAL (operands[2]) == 128
6418 || (INTVAL (operands[2]) < 0
6419 && INTVAL (operands[2]) != -128)))
6421 operands[2] = GEN_INT (-INTVAL (operands[2]));
6422 return "sub{w}\t{%2, %0|%0, %2}";
6424 return "add{w}\t{%2, %0|%0, %2}";
6428 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6429 (const_string "incdec")
6430 (const_string "alu")))
6431 (set_attr "mode" "HI")])
6433 (define_expand "addqi3"
6434 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6435 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6436 (match_operand:QI 2 "general_operand" "")))
6437 (clobber (reg:CC 17))])]
6438 "TARGET_QIMODE_MATH"
6439 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6441 ;; %%% Potential partial reg stall on alternative 2. What to do?
6442 (define_insn "*addqi_1_lea"
6443 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6444 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6445 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6446 (clobber (reg:CC 17))]
6447 "!TARGET_PARTIAL_REG_STALL
6448 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6450 int widen = (which_alternative == 2);
6451 switch (get_attr_type (insn))
6456 if (operands[2] == const1_rtx)
6457 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6458 else if (operands[2] == constm1_rtx)
6459 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6463 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6464 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6465 if (GET_CODE (operands[2]) == CONST_INT
6466 && (INTVAL (operands[2]) == 128
6467 || (INTVAL (operands[2]) < 0
6468 && INTVAL (operands[2]) != -128)))
6470 operands[2] = GEN_INT (-INTVAL (operands[2]));
6472 return "sub{l}\t{%2, %k0|%k0, %2}";
6474 return "sub{b}\t{%2, %0|%0, %2}";
6477 return "add{l}\t{%k2, %k0|%k0, %k2}";
6479 return "add{b}\t{%2, %0|%0, %2}";
6483 (if_then_else (eq_attr "alternative" "3")
6484 (const_string "lea")
6485 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6486 (const_string "incdec")
6487 (const_string "alu"))))
6488 (set_attr "mode" "QI,QI,SI,SI")])
6490 (define_insn "*addqi_1"
6491 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6492 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6493 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6494 (clobber (reg:CC 17))]
6495 "TARGET_PARTIAL_REG_STALL
6496 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6498 int widen = (which_alternative == 2);
6499 switch (get_attr_type (insn))
6502 if (operands[2] == const1_rtx)
6503 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6504 else if (operands[2] == constm1_rtx)
6505 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6509 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6510 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6511 if (GET_CODE (operands[2]) == CONST_INT
6512 && (INTVAL (operands[2]) == 128
6513 || (INTVAL (operands[2]) < 0
6514 && INTVAL (operands[2]) != -128)))
6516 operands[2] = GEN_INT (-INTVAL (operands[2]));
6518 return "sub{l}\t{%2, %k0|%k0, %2}";
6520 return "sub{b}\t{%2, %0|%0, %2}";
6523 return "add{l}\t{%k2, %k0|%k0, %k2}";
6525 return "add{b}\t{%2, %0|%0, %2}";
6529 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6530 (const_string "incdec")
6531 (const_string "alu")))
6532 (set_attr "mode" "QI,QI,SI")])
6534 (define_insn "*addqi_1_slp"
6535 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6536 (plus:QI (match_dup 0)
6537 (match_operand:QI 1 "general_operand" "qn,qnm")))
6538 (clobber (reg:CC 17))]
6539 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6540 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6542 switch (get_attr_type (insn))
6545 if (operands[1] == const1_rtx)
6546 return "inc{b}\t%0";
6547 else if (operands[1] == constm1_rtx)
6548 return "dec{b}\t%0";
6552 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6553 if (GET_CODE (operands[1]) == CONST_INT
6554 && INTVAL (operands[1]) < 0)
6556 operands[2] = GEN_INT (-INTVAL (operands[2]));
6557 return "sub{b}\t{%1, %0|%0, %1}";
6559 return "add{b}\t{%1, %0|%0, %1}";
6563 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6564 (const_string "incdec")
6565 (const_string "alu1")))
6566 (set_attr "mode" "QI")])
6568 (define_insn "*addqi_2"
6571 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6572 (match_operand:QI 2 "general_operand" "qmni,qni"))
6574 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6575 (plus:QI (match_dup 1) (match_dup 2)))]
6576 "ix86_match_ccmode (insn, CCGOCmode)
6577 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6579 switch (get_attr_type (insn))
6582 if (operands[2] == const1_rtx)
6583 return "inc{b}\t%0";
6584 else if (operands[2] == constm1_rtx
6585 || (GET_CODE (operands[2]) == CONST_INT
6586 && INTVAL (operands[2]) == 255))
6587 return "dec{b}\t%0";
6591 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6592 if (GET_CODE (operands[2]) == CONST_INT
6593 && INTVAL (operands[2]) < 0)
6595 operands[2] = GEN_INT (-INTVAL (operands[2]));
6596 return "sub{b}\t{%2, %0|%0, %2}";
6598 return "add{b}\t{%2, %0|%0, %2}";
6602 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6603 (const_string "incdec")
6604 (const_string "alu")))
6605 (set_attr "mode" "QI")])
6607 (define_insn "*addqi_3"
6609 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6610 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6611 (clobber (match_scratch:QI 0 "=q"))]
6612 "ix86_match_ccmode (insn, CCZmode)
6613 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6615 switch (get_attr_type (insn))
6618 if (operands[2] == const1_rtx)
6619 return "inc{b}\t%0";
6620 else if (operands[2] == constm1_rtx
6621 || (GET_CODE (operands[2]) == CONST_INT
6622 && INTVAL (operands[2]) == 255))
6623 return "dec{b}\t%0";
6627 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6628 if (GET_CODE (operands[2]) == CONST_INT
6629 && INTVAL (operands[2]) < 0)
6631 operands[2] = GEN_INT (-INTVAL (operands[2]));
6632 return "sub{b}\t{%2, %0|%0, %2}";
6634 return "add{b}\t{%2, %0|%0, %2}";
6638 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6639 (const_string "incdec")
6640 (const_string "alu")))
6641 (set_attr "mode" "QI")])
6643 ; See comments above addsi_3_imm for details.
6644 (define_insn "*addqi_4"
6646 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6647 (match_operand:QI 2 "const_int_operand" "n")))
6648 (clobber (match_scratch:QI 0 "=qm"))]
6649 "ix86_match_ccmode (insn, CCGCmode)
6650 && (INTVAL (operands[2]) & 0xff) != 0x80"
6652 switch (get_attr_type (insn))
6655 if (operands[2] == constm1_rtx
6656 || (GET_CODE (operands[2]) == CONST_INT
6657 && INTVAL (operands[2]) == 255))
6658 return "inc{b}\t%0";
6659 else if (operands[2] == const1_rtx)
6660 return "dec{b}\t%0";
6665 if (! rtx_equal_p (operands[0], operands[1]))
6667 if (INTVAL (operands[2]) < 0)
6669 operands[2] = GEN_INT (-INTVAL (operands[2]));
6670 return "add{b}\t{%2, %0|%0, %2}";
6672 return "sub{b}\t{%2, %0|%0, %2}";
6676 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6677 (const_string "incdec")
6678 (const_string "alu")))
6679 (set_attr "mode" "QI")])
6682 (define_insn "*addqi_5"
6685 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6686 (match_operand:QI 2 "general_operand" "qmni"))
6688 (clobber (match_scratch:QI 0 "=q"))]
6689 "ix86_match_ccmode (insn, CCGOCmode)
6690 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6692 switch (get_attr_type (insn))
6695 if (operands[2] == const1_rtx)
6696 return "inc{b}\t%0";
6697 else if (operands[2] == constm1_rtx
6698 || (GET_CODE (operands[2]) == CONST_INT
6699 && INTVAL (operands[2]) == 255))
6700 return "dec{b}\t%0";
6704 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6705 if (GET_CODE (operands[2]) == CONST_INT
6706 && INTVAL (operands[2]) < 0)
6708 operands[2] = GEN_INT (-INTVAL (operands[2]));
6709 return "sub{b}\t{%2, %0|%0, %2}";
6711 return "add{b}\t{%2, %0|%0, %2}";
6715 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6716 (const_string "incdec")
6717 (const_string "alu")))
6718 (set_attr "mode" "QI")])
6721 (define_insn "addqi_ext_1"
6722 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6727 (match_operand 1 "ext_register_operand" "0")
6730 (match_operand:QI 2 "general_operand" "Qmn")))
6731 (clobber (reg:CC 17))]
6734 switch (get_attr_type (insn))
6737 if (operands[2] == const1_rtx)
6738 return "inc{b}\t%h0";
6739 else if (operands[2] == constm1_rtx
6740 || (GET_CODE (operands[2]) == CONST_INT
6741 && INTVAL (operands[2]) == 255))
6742 return "dec{b}\t%h0";
6746 return "add{b}\t{%2, %h0|%h0, %2}";
6750 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6751 (const_string "incdec")
6752 (const_string "alu")))
6753 (set_attr "mode" "QI")])
6755 (define_insn "*addqi_ext_1_rex64"
6756 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6761 (match_operand 1 "ext_register_operand" "0")
6764 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6765 (clobber (reg:CC 17))]
6768 switch (get_attr_type (insn))
6771 if (operands[2] == const1_rtx)
6772 return "inc{b}\t%h0";
6773 else if (operands[2] == constm1_rtx
6774 || (GET_CODE (operands[2]) == CONST_INT
6775 && INTVAL (operands[2]) == 255))
6776 return "dec{b}\t%h0";
6780 return "add{b}\t{%2, %h0|%h0, %2}";
6784 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6785 (const_string "incdec")
6786 (const_string "alu")))
6787 (set_attr "mode" "QI")])
6789 (define_insn "*addqi_ext_2"
6790 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6795 (match_operand 1 "ext_register_operand" "%0")
6799 (match_operand 2 "ext_register_operand" "Q")
6802 (clobber (reg:CC 17))]
6804 "add{b}\t{%h2, %h0|%h0, %h2}"
6805 [(set_attr "type" "alu")
6806 (set_attr "mode" "QI")])
6808 ;; The patterns that match these are at the end of this file.
6810 (define_expand "addxf3"
6811 [(set (match_operand:XF 0 "register_operand" "")
6812 (plus:XF (match_operand:XF 1 "register_operand" "")
6813 (match_operand:XF 2 "register_operand" "")))]
6814 "!TARGET_64BIT && TARGET_80387"
6817 (define_expand "addtf3"
6818 [(set (match_operand:TF 0 "register_operand" "")
6819 (plus:TF (match_operand:TF 1 "register_operand" "")
6820 (match_operand:TF 2 "register_operand" "")))]
6824 (define_expand "adddf3"
6825 [(set (match_operand:DF 0 "register_operand" "")
6826 (plus:DF (match_operand:DF 1 "register_operand" "")
6827 (match_operand:DF 2 "nonimmediate_operand" "")))]
6828 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6831 (define_expand "addsf3"
6832 [(set (match_operand:SF 0 "register_operand" "")
6833 (plus:SF (match_operand:SF 1 "register_operand" "")
6834 (match_operand:SF 2 "nonimmediate_operand" "")))]
6835 "TARGET_80387 || TARGET_SSE_MATH"
6838 ;; Subtract instructions
6840 ;; %%% splits for subsidi3
6842 (define_expand "subdi3"
6843 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6844 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6845 (match_operand:DI 2 "x86_64_general_operand" "")))
6846 (clobber (reg:CC 17))])]
6848 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6850 (define_insn "*subdi3_1"
6851 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6852 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6853 (match_operand:DI 2 "general_operand" "roiF,riF")))
6854 (clobber (reg:CC 17))]
6855 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6859 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6860 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6861 (match_operand:DI 2 "general_operand" "")))
6862 (clobber (reg:CC 17))]
6863 "!TARGET_64BIT && reload_completed"
6864 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6865 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6866 (parallel [(set (match_dup 3)
6867 (minus:SI (match_dup 4)
6868 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6870 (clobber (reg:CC 17))])]
6871 "split_di (operands+0, 1, operands+0, operands+3);
6872 split_di (operands+1, 1, operands+1, operands+4);
6873 split_di (operands+2, 1, operands+2, operands+5);")
6875 (define_insn "subdi3_carry_rex64"
6876 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6877 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6878 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6879 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6880 (clobber (reg:CC 17))]
6881 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6882 "sbb{q}\t{%2, %0|%0, %2}"
6883 [(set_attr "type" "alu")
6884 (set_attr "pent_pair" "pu")
6885 (set_attr "ppro_uops" "few")
6886 (set_attr "mode" "DI")])
6888 (define_insn "*subdi_1_rex64"
6889 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6890 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6891 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6892 (clobber (reg:CC 17))]
6893 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6894 "sub{q}\t{%2, %0|%0, %2}"
6895 [(set_attr "type" "alu")
6896 (set_attr "mode" "DI")])
6898 (define_insn "*subdi_2_rex64"
6901 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6902 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6904 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6905 (minus:DI (match_dup 1) (match_dup 2)))]
6906 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6907 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6908 "sub{q}\t{%2, %0|%0, %2}"
6909 [(set_attr "type" "alu")
6910 (set_attr "mode" "DI")])
6912 (define_insn "*subdi_3_rex63"
6914 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6915 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6916 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6917 (minus:DI (match_dup 1) (match_dup 2)))]
6918 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6919 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6920 "sub{q}\t{%2, %0|%0, %2}"
6921 [(set_attr "type" "alu")
6922 (set_attr "mode" "DI")])
6924 (define_insn "subqi3_carry"
6925 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
6926 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6927 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6928 (match_operand:QI 2 "general_operand" "ri,rm"))))
6929 (clobber (reg:CC 17))]
6930 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6931 "sbb{b}\t{%2, %0|%0, %2}"
6932 [(set_attr "type" "alu")
6933 (set_attr "pent_pair" "pu")
6934 (set_attr "ppro_uops" "few")
6935 (set_attr "mode" "QI")])
6937 (define_insn "subhi3_carry"
6938 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6939 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6940 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6941 (match_operand:HI 2 "general_operand" "ri,rm"))))
6942 (clobber (reg:CC 17))]
6943 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6944 "sbb{w}\t{%2, %0|%0, %2}"
6945 [(set_attr "type" "alu")
6946 (set_attr "pent_pair" "pu")
6947 (set_attr "ppro_uops" "few")
6948 (set_attr "mode" "HI")])
6950 (define_insn "subsi3_carry"
6951 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6952 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6953 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6954 (match_operand:SI 2 "general_operand" "ri,rm"))))
6955 (clobber (reg:CC 17))]
6956 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6957 "sbb{l}\t{%2, %0|%0, %2}"
6958 [(set_attr "type" "alu")
6959 (set_attr "pent_pair" "pu")
6960 (set_attr "ppro_uops" "few")
6961 (set_attr "mode" "SI")])
6963 (define_insn "subsi3_carry_zext"
6964 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6966 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6967 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6968 (match_operand:SI 2 "general_operand" "ri,rm")))))
6969 (clobber (reg:CC 17))]
6970 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6971 "sbb{l}\t{%2, %k0|%k0, %2}"
6972 [(set_attr "type" "alu")
6973 (set_attr "pent_pair" "pu")
6974 (set_attr "ppro_uops" "few")
6975 (set_attr "mode" "SI")])
6977 (define_expand "subsi3"
6978 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6979 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6980 (match_operand:SI 2 "general_operand" "")))
6981 (clobber (reg:CC 17))])]
6983 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6985 (define_insn "*subsi_1"
6986 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6987 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6988 (match_operand:SI 2 "general_operand" "ri,rm")))
6989 (clobber (reg:CC 17))]
6990 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6991 "sub{l}\t{%2, %0|%0, %2}"
6992 [(set_attr "type" "alu")
6993 (set_attr "mode" "SI")])
6995 (define_insn "*subsi_1_zext"
6996 [(set (match_operand:DI 0 "register_operand" "=r")
6998 (minus:SI (match_operand:SI 1 "register_operand" "0")
6999 (match_operand:SI 2 "general_operand" "rim"))))
7000 (clobber (reg:CC 17))]
7001 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7002 "sub{l}\t{%2, %k0|%k0, %2}"
7003 [(set_attr "type" "alu")
7004 (set_attr "mode" "SI")])
7006 (define_insn "*subsi_2"
7009 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7010 (match_operand:SI 2 "general_operand" "ri,rm"))
7012 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7013 (minus:SI (match_dup 1) (match_dup 2)))]
7014 "ix86_match_ccmode (insn, CCGOCmode)
7015 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7016 "sub{l}\t{%2, %0|%0, %2}"
7017 [(set_attr "type" "alu")
7018 (set_attr "mode" "SI")])
7020 (define_insn "*subsi_2_zext"
7023 (minus:SI (match_operand:SI 1 "register_operand" "0")
7024 (match_operand:SI 2 "general_operand" "rim"))
7026 (set (match_operand:DI 0 "register_operand" "=r")
7028 (minus:SI (match_dup 1)
7030 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7031 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7032 "sub{l}\t{%2, %k0|%k0, %2}"
7033 [(set_attr "type" "alu")
7034 (set_attr "mode" "SI")])
7036 (define_insn "*subsi_3"
7038 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7039 (match_operand:SI 2 "general_operand" "ri,rm")))
7040 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7041 (minus:SI (match_dup 1) (match_dup 2)))]
7042 "ix86_match_ccmode (insn, CCmode)
7043 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7044 "sub{l}\t{%2, %0|%0, %2}"
7045 [(set_attr "type" "alu")
7046 (set_attr "mode" "SI")])
7048 (define_insn "*subsi_3_zext"
7050 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
7051 (match_operand:SI 2 "general_operand" "rim")))
7052 (set (match_operand:DI 0 "register_operand" "=r")
7054 (minus:SI (match_dup 1)
7056 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7057 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7058 "sub{q}\t{%2, %0|%0, %2}"
7059 [(set_attr "type" "alu")
7060 (set_attr "mode" "DI")])
7062 (define_expand "subhi3"
7063 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7064 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7065 (match_operand:HI 2 "general_operand" "")))
7066 (clobber (reg:CC 17))])]
7067 "TARGET_HIMODE_MATH"
7068 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7070 (define_insn "*subhi_1"
7071 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7072 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7073 (match_operand:HI 2 "general_operand" "ri,rm")))
7074 (clobber (reg:CC 17))]
7075 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7076 "sub{w}\t{%2, %0|%0, %2}"
7077 [(set_attr "type" "alu")
7078 (set_attr "mode" "HI")])
7080 (define_insn "*subhi_2"
7083 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7084 (match_operand:HI 2 "general_operand" "ri,rm"))
7086 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7087 (minus:HI (match_dup 1) (match_dup 2)))]
7088 "ix86_match_ccmode (insn, CCGOCmode)
7089 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7090 "sub{w}\t{%2, %0|%0, %2}"
7091 [(set_attr "type" "alu")
7092 (set_attr "mode" "HI")])
7094 (define_insn "*subhi_3"
7096 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7097 (match_operand:HI 2 "general_operand" "ri,rm")))
7098 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7099 (minus:HI (match_dup 1) (match_dup 2)))]
7100 "ix86_match_ccmode (insn, CCmode)
7101 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7102 "sub{w}\t{%2, %0|%0, %2}"
7103 [(set_attr "type" "alu")
7104 (set_attr "mode" "HI")])
7106 (define_expand "subqi3"
7107 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7108 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7109 (match_operand:QI 2 "general_operand" "")))
7110 (clobber (reg:CC 17))])]
7111 "TARGET_QIMODE_MATH"
7112 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7114 (define_insn "*subqi_1"
7115 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7116 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7117 (match_operand:QI 2 "general_operand" "qn,qmn")))
7118 (clobber (reg:CC 17))]
7119 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7120 "sub{b}\t{%2, %0|%0, %2}"
7121 [(set_attr "type" "alu")
7122 (set_attr "mode" "QI")])
7124 (define_insn "*subqi_1_slp"
7125 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7126 (minus:QI (match_dup 0)
7127 (match_operand:QI 1 "general_operand" "qn,qmn")))
7128 (clobber (reg:CC 17))]
7129 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
7130 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7131 "sub{b}\t{%1, %0|%0, %1}"
7132 [(set_attr "type" "alu1")
7133 (set_attr "mode" "QI")])
7135 (define_insn "*subqi_2"
7138 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7139 (match_operand:QI 2 "general_operand" "qi,qm"))
7141 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7142 (minus:HI (match_dup 1) (match_dup 2)))]
7143 "ix86_match_ccmode (insn, CCGOCmode)
7144 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7145 "sub{b}\t{%2, %0|%0, %2}"
7146 [(set_attr "type" "alu")
7147 (set_attr "mode" "QI")])
7149 (define_insn "*subqi_3"
7151 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7152 (match_operand:QI 2 "general_operand" "qi,qm")))
7153 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7154 (minus:HI (match_dup 1) (match_dup 2)))]
7155 "ix86_match_ccmode (insn, CCmode)
7156 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7157 "sub{b}\t{%2, %0|%0, %2}"
7158 [(set_attr "type" "alu")
7159 (set_attr "mode" "QI")])
7161 ;; The patterns that match these are at the end of this file.
7163 (define_expand "subxf3"
7164 [(set (match_operand:XF 0 "register_operand" "")
7165 (minus:XF (match_operand:XF 1 "register_operand" "")
7166 (match_operand:XF 2 "register_operand" "")))]
7167 "!TARGET_64BIT && TARGET_80387"
7170 (define_expand "subtf3"
7171 [(set (match_operand:TF 0 "register_operand" "")
7172 (minus:TF (match_operand:TF 1 "register_operand" "")
7173 (match_operand:TF 2 "register_operand" "")))]
7177 (define_expand "subdf3"
7178 [(set (match_operand:DF 0 "register_operand" "")
7179 (minus:DF (match_operand:DF 1 "register_operand" "")
7180 (match_operand:DF 2 "nonimmediate_operand" "")))]
7181 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7184 (define_expand "subsf3"
7185 [(set (match_operand:SF 0 "register_operand" "")
7186 (minus:SF (match_operand:SF 1 "register_operand" "")
7187 (match_operand:SF 2 "nonimmediate_operand" "")))]
7188 "TARGET_80387 || TARGET_SSE_MATH"
7191 ;; Multiply instructions
7193 (define_expand "muldi3"
7194 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7195 (mult:DI (match_operand:DI 1 "register_operand" "")
7196 (match_operand:DI 2 "x86_64_general_operand" "")))
7197 (clobber (reg:CC 17))])]
7201 (define_insn "*muldi3_1_rex64"
7202 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7203 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
7204 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7205 (clobber (reg:CC 17))]
7207 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7209 imul{q}\t{%2, %1, %0|%0, %1, %2}
7210 imul{q}\t{%2, %1, %0|%0, %1, %2}
7211 imul{q}\t{%2, %0|%0, %2}"
7212 [(set_attr "type" "imul")
7213 (set_attr "prefix_0f" "0,0,1")
7214 (set (attr "athlon_decode")
7215 (cond [(eq_attr "cpu" "athlon")
7216 (const_string "vector")
7217 (eq_attr "alternative" "1")
7218 (const_string "vector")
7219 (and (eq_attr "alternative" "2")
7220 (match_operand 1 "memory_operand" ""))
7221 (const_string "vector")]
7222 (const_string "direct")))
7223 (set_attr "mode" "DI")])
7225 (define_expand "mulsi3"
7226 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7227 (mult:SI (match_operand:SI 1 "register_operand" "")
7228 (match_operand:SI 2 "general_operand" "")))
7229 (clobber (reg:CC 17))])]
7233 (define_insn "*mulsi3_1"
7234 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7235 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7236 (match_operand:SI 2 "general_operand" "K,i,mr")))
7237 (clobber (reg:CC 17))]
7238 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7240 imul{l}\t{%2, %1, %0|%0, %1, %2}
7241 imul{l}\t{%2, %1, %0|%0, %1, %2}
7242 imul{l}\t{%2, %0|%0, %2}"
7243 [(set_attr "type" "imul")
7244 (set_attr "prefix_0f" "0,0,1")
7245 (set (attr "athlon_decode")
7246 (cond [(eq_attr "cpu" "athlon")
7247 (const_string "vector")
7248 (eq_attr "alternative" "1")
7249 (const_string "vector")
7250 (and (eq_attr "alternative" "2")
7251 (match_operand 1 "memory_operand" ""))
7252 (const_string "vector")]
7253 (const_string "direct")))
7254 (set_attr "mode" "SI")])
7256 (define_insn "*mulsi3_1_zext"
7257 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7259 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7260 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7261 (clobber (reg:CC 17))]
7263 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7265 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7266 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7267 imul{l}\t{%2, %k0|%k0, %2}"
7268 [(set_attr "type" "imul")
7269 (set_attr "prefix_0f" "0,0,1")
7270 (set (attr "athlon_decode")
7271 (cond [(eq_attr "cpu" "athlon")
7272 (const_string "vector")
7273 (eq_attr "alternative" "1")
7274 (const_string "vector")
7275 (and (eq_attr "alternative" "2")
7276 (match_operand 1 "memory_operand" ""))
7277 (const_string "vector")]
7278 (const_string "direct")))
7279 (set_attr "mode" "SI")])
7281 (define_expand "mulhi3"
7282 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7283 (mult:HI (match_operand:HI 1 "register_operand" "")
7284 (match_operand:HI 2 "general_operand" "")))
7285 (clobber (reg:CC 17))])]
7286 "TARGET_HIMODE_MATH"
7289 (define_insn "*mulhi3_1"
7290 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7291 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7292 (match_operand:HI 2 "general_operand" "K,i,mr")))
7293 (clobber (reg:CC 17))]
7294 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7296 imul{w}\t{%2, %1, %0|%0, %1, %2}
7297 imul{w}\t{%2, %1, %0|%0, %1, %2}
7298 imul{w}\t{%2, %0|%0, %2}"
7299 [(set_attr "type" "imul")
7300 (set_attr "prefix_0f" "0,0,1")
7301 (set (attr "athlon_decode")
7302 (cond [(eq_attr "cpu" "athlon")
7303 (const_string "vector")
7304 (eq_attr "alternative" "1,2")
7305 (const_string "vector")]
7306 (const_string "direct")))
7307 (set_attr "mode" "HI")])
7309 (define_expand "mulqi3"
7310 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7311 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7312 (match_operand:QI 2 "register_operand" "")))
7313 (clobber (reg:CC 17))])]
7314 "TARGET_QIMODE_MATH"
7317 (define_insn "*mulqi3_1"
7318 [(set (match_operand:QI 0 "register_operand" "=a")
7319 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7320 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7321 (clobber (reg:CC 17))]
7323 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7325 [(set_attr "type" "imul")
7326 (set_attr "length_immediate" "0")
7327 (set (attr "athlon_decode")
7328 (if_then_else (eq_attr "cpu" "athlon")
7329 (const_string "vector")
7330 (const_string "direct")))
7331 (set_attr "mode" "QI")])
7333 (define_expand "umulqihi3"
7334 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7335 (mult:HI (zero_extend:HI
7336 (match_operand:QI 1 "nonimmediate_operand" ""))
7338 (match_operand:QI 2 "register_operand" ""))))
7339 (clobber (reg:CC 17))])]
7340 "TARGET_QIMODE_MATH"
7343 (define_insn "*umulqihi3_1"
7344 [(set (match_operand:HI 0 "register_operand" "=a")
7345 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7346 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7347 (clobber (reg:CC 17))]
7349 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7351 [(set_attr "type" "imul")
7352 (set_attr "length_immediate" "0")
7353 (set (attr "athlon_decode")
7354 (if_then_else (eq_attr "cpu" "athlon")
7355 (const_string "vector")
7356 (const_string "direct")))
7357 (set_attr "mode" "QI")])
7359 (define_expand "mulqihi3"
7360 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7361 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7362 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7363 (clobber (reg:CC 17))])]
7364 "TARGET_QIMODE_MATH"
7367 (define_insn "*mulqihi3_insn"
7368 [(set (match_operand:HI 0 "register_operand" "=a")
7369 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7370 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7371 (clobber (reg:CC 17))]
7373 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7375 [(set_attr "type" "imul")
7376 (set_attr "length_immediate" "0")
7377 (set (attr "athlon_decode")
7378 (if_then_else (eq_attr "cpu" "athlon")
7379 (const_string "vector")
7380 (const_string "direct")))
7381 (set_attr "mode" "QI")])
7383 (define_expand "umulditi3"
7384 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7385 (mult:TI (zero_extend:TI
7386 (match_operand:DI 1 "nonimmediate_operand" ""))
7388 (match_operand:DI 2 "register_operand" ""))))
7389 (clobber (reg:CC 17))])]
7393 (define_insn "*umulditi3_insn"
7394 [(set (match_operand:TI 0 "register_operand" "=A")
7395 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7396 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7397 (clobber (reg:CC 17))]
7399 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7401 [(set_attr "type" "imul")
7402 (set_attr "ppro_uops" "few")
7403 (set_attr "length_immediate" "0")
7404 (set (attr "athlon_decode")
7405 (if_then_else (eq_attr "cpu" "athlon")
7406 (const_string "vector")
7407 (const_string "double")))
7408 (set_attr "mode" "DI")])
7410 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7411 (define_expand "umulsidi3"
7412 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7413 (mult:DI (zero_extend:DI
7414 (match_operand:SI 1 "nonimmediate_operand" ""))
7416 (match_operand:SI 2 "register_operand" ""))))
7417 (clobber (reg:CC 17))])]
7421 (define_insn "*umulsidi3_insn"
7422 [(set (match_operand:DI 0 "register_operand" "=A")
7423 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7424 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7425 (clobber (reg:CC 17))]
7427 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7429 [(set_attr "type" "imul")
7430 (set_attr "ppro_uops" "few")
7431 (set_attr "length_immediate" "0")
7432 (set (attr "athlon_decode")
7433 (if_then_else (eq_attr "cpu" "athlon")
7434 (const_string "vector")
7435 (const_string "double")))
7436 (set_attr "mode" "SI")])
7438 (define_expand "mulditi3"
7439 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7440 (mult:TI (sign_extend:TI
7441 (match_operand:DI 1 "nonimmediate_operand" ""))
7443 (match_operand:DI 2 "register_operand" ""))))
7444 (clobber (reg:CC 17))])]
7448 (define_insn "*mulditi3_insn"
7449 [(set (match_operand:TI 0 "register_operand" "=A")
7450 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7451 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7452 (clobber (reg:CC 17))]
7454 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7456 [(set_attr "type" "imul")
7457 (set_attr "length_immediate" "0")
7458 (set (attr "athlon_decode")
7459 (if_then_else (eq_attr "cpu" "athlon")
7460 (const_string "vector")
7461 (const_string "double")))
7462 (set_attr "mode" "DI")])
7464 (define_expand "mulsidi3"
7465 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7466 (mult:DI (sign_extend:DI
7467 (match_operand:SI 1 "nonimmediate_operand" ""))
7469 (match_operand:SI 2 "register_operand" ""))))
7470 (clobber (reg:CC 17))])]
7474 (define_insn "*mulsidi3_insn"
7475 [(set (match_operand:DI 0 "register_operand" "=A")
7476 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7477 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7478 (clobber (reg:CC 17))]
7480 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7482 [(set_attr "type" "imul")
7483 (set_attr "length_immediate" "0")
7484 (set (attr "athlon_decode")
7485 (if_then_else (eq_attr "cpu" "athlon")
7486 (const_string "vector")
7487 (const_string "double")))
7488 (set_attr "mode" "SI")])
7490 (define_expand "umuldi3_highpart"
7491 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7494 (mult:TI (zero_extend:TI
7495 (match_operand:DI 1 "nonimmediate_operand" ""))
7497 (match_operand:DI 2 "register_operand" "")))
7499 (clobber (match_scratch:DI 3 ""))
7500 (clobber (reg:CC 17))])]
7504 (define_insn "*umuldi3_highpart_rex64"
7505 [(set (match_operand:DI 0 "register_operand" "=d")
7508 (mult:TI (zero_extend:TI
7509 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7511 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7513 (clobber (match_scratch:DI 3 "=1"))
7514 (clobber (reg:CC 17))]
7516 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7518 [(set_attr "type" "imul")
7519 (set_attr "ppro_uops" "few")
7520 (set_attr "length_immediate" "0")
7521 (set (attr "athlon_decode")
7522 (if_then_else (eq_attr "cpu" "athlon")
7523 (const_string "vector")
7524 (const_string "double")))
7525 (set_attr "mode" "DI")])
7527 (define_expand "umulsi3_highpart"
7528 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7531 (mult:DI (zero_extend:DI
7532 (match_operand:SI 1 "nonimmediate_operand" ""))
7534 (match_operand:SI 2 "register_operand" "")))
7536 (clobber (match_scratch:SI 3 ""))
7537 (clobber (reg:CC 17))])]
7541 (define_insn "*umulsi3_highpart_insn"
7542 [(set (match_operand:SI 0 "register_operand" "=d")
7545 (mult:DI (zero_extend:DI
7546 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7548 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7550 (clobber (match_scratch:SI 3 "=1"))
7551 (clobber (reg:CC 17))]
7552 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7554 [(set_attr "type" "imul")
7555 (set_attr "ppro_uops" "few")
7556 (set_attr "length_immediate" "0")
7557 (set (attr "athlon_decode")
7558 (if_then_else (eq_attr "cpu" "athlon")
7559 (const_string "vector")
7560 (const_string "double")))
7561 (set_attr "mode" "SI")])
7563 (define_insn "*umulsi3_highpart_zext"
7564 [(set (match_operand:DI 0 "register_operand" "=d")
7565 (zero_extend:DI (truncate:SI
7567 (mult:DI (zero_extend:DI
7568 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7570 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7572 (clobber (match_scratch:SI 3 "=1"))
7573 (clobber (reg:CC 17))]
7575 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7577 [(set_attr "type" "imul")
7578 (set_attr "ppro_uops" "few")
7579 (set_attr "length_immediate" "0")
7580 (set (attr "athlon_decode")
7581 (if_then_else (eq_attr "cpu" "athlon")
7582 (const_string "vector")
7583 (const_string "double")))
7584 (set_attr "mode" "SI")])
7586 (define_expand "smuldi3_highpart"
7587 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7590 (mult:TI (sign_extend:TI
7591 (match_operand:DI 1 "nonimmediate_operand" ""))
7593 (match_operand:DI 2 "register_operand" "")))
7595 (clobber (match_scratch:DI 3 ""))
7596 (clobber (reg:CC 17))])]
7600 (define_insn "*smuldi3_highpart_rex64"
7601 [(set (match_operand:DI 0 "register_operand" "=d")
7604 (mult:TI (sign_extend:TI
7605 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7607 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7609 (clobber (match_scratch:DI 3 "=1"))
7610 (clobber (reg:CC 17))]
7612 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7614 [(set_attr "type" "imul")
7615 (set_attr "ppro_uops" "few")
7616 (set (attr "athlon_decode")
7617 (if_then_else (eq_attr "cpu" "athlon")
7618 (const_string "vector")
7619 (const_string "double")))
7620 (set_attr "mode" "DI")])
7622 (define_expand "smulsi3_highpart"
7623 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7626 (mult:DI (sign_extend:DI
7627 (match_operand:SI 1 "nonimmediate_operand" ""))
7629 (match_operand:SI 2 "register_operand" "")))
7631 (clobber (match_scratch:SI 3 ""))
7632 (clobber (reg:CC 17))])]
7636 (define_insn "*smulsi3_highpart_insn"
7637 [(set (match_operand:SI 0 "register_operand" "=d")
7640 (mult:DI (sign_extend:DI
7641 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7643 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7645 (clobber (match_scratch:SI 3 "=1"))
7646 (clobber (reg:CC 17))]
7647 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7649 [(set_attr "type" "imul")
7650 (set_attr "ppro_uops" "few")
7651 (set (attr "athlon_decode")
7652 (if_then_else (eq_attr "cpu" "athlon")
7653 (const_string "vector")
7654 (const_string "double")))
7655 (set_attr "mode" "SI")])
7657 (define_insn "*smulsi3_highpart_zext"
7658 [(set (match_operand:DI 0 "register_operand" "=d")
7659 (zero_extend:DI (truncate:SI
7661 (mult:DI (sign_extend:DI
7662 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7664 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7666 (clobber (match_scratch:SI 3 "=1"))
7667 (clobber (reg:CC 17))]
7669 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7671 [(set_attr "type" "imul")
7672 (set_attr "ppro_uops" "few")
7673 (set (attr "athlon_decode")
7674 (if_then_else (eq_attr "cpu" "athlon")
7675 (const_string "vector")
7676 (const_string "double")))
7677 (set_attr "mode" "SI")])
7679 ;; The patterns that match these are at the end of this file.
7681 (define_expand "mulxf3"
7682 [(set (match_operand:XF 0 "register_operand" "")
7683 (mult:XF (match_operand:XF 1 "register_operand" "")
7684 (match_operand:XF 2 "register_operand" "")))]
7685 "!TARGET_64BIT && TARGET_80387"
7688 (define_expand "multf3"
7689 [(set (match_operand:TF 0 "register_operand" "")
7690 (mult:TF (match_operand:TF 1 "register_operand" "")
7691 (match_operand:TF 2 "register_operand" "")))]
7695 (define_expand "muldf3"
7696 [(set (match_operand:DF 0 "register_operand" "")
7697 (mult:DF (match_operand:DF 1 "register_operand" "")
7698 (match_operand:DF 2 "nonimmediate_operand" "")))]
7699 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7702 (define_expand "mulsf3"
7703 [(set (match_operand:SF 0 "register_operand" "")
7704 (mult:SF (match_operand:SF 1 "register_operand" "")
7705 (match_operand:SF 2 "nonimmediate_operand" "")))]
7706 "TARGET_80387 || TARGET_SSE_MATH"
7709 ;; Divide instructions
7711 (define_insn "divqi3"
7712 [(set (match_operand:QI 0 "register_operand" "=a")
7713 (div:QI (match_operand:HI 1 "register_operand" "0")
7714 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7715 (clobber (reg:CC 17))]
7716 "TARGET_QIMODE_MATH"
7718 [(set_attr "type" "idiv")
7719 (set_attr "mode" "QI")
7720 (set_attr "ppro_uops" "few")])
7722 (define_insn "udivqi3"
7723 [(set (match_operand:QI 0 "register_operand" "=a")
7724 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7725 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7726 (clobber (reg:CC 17))]
7727 "TARGET_QIMODE_MATH"
7729 [(set_attr "type" "idiv")
7730 (set_attr "mode" "QI")
7731 (set_attr "ppro_uops" "few")])
7733 ;; The patterns that match these are at the end of this file.
7735 (define_expand "divxf3"
7736 [(set (match_operand:XF 0 "register_operand" "")
7737 (div:XF (match_operand:XF 1 "register_operand" "")
7738 (match_operand:XF 2 "register_operand" "")))]
7739 "!TARGET_64BIT && TARGET_80387"
7742 (define_expand "divtf3"
7743 [(set (match_operand:TF 0 "register_operand" "")
7744 (div:TF (match_operand:TF 1 "register_operand" "")
7745 (match_operand:TF 2 "register_operand" "")))]
7749 (define_expand "divdf3"
7750 [(set (match_operand:DF 0 "register_operand" "")
7751 (div:DF (match_operand:DF 1 "register_operand" "")
7752 (match_operand:DF 2 "nonimmediate_operand" "")))]
7753 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7756 (define_expand "divsf3"
7757 [(set (match_operand:SF 0 "register_operand" "")
7758 (div:SF (match_operand:SF 1 "register_operand" "")
7759 (match_operand:SF 2 "nonimmediate_operand" "")))]
7760 "TARGET_80387 || TARGET_SSE_MATH"
7763 ;; Remainder instructions.
7765 (define_expand "divmoddi4"
7766 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7767 (div:DI (match_operand:DI 1 "register_operand" "")
7768 (match_operand:DI 2 "nonimmediate_operand" "")))
7769 (set (match_operand:DI 3 "register_operand" "")
7770 (mod:DI (match_dup 1) (match_dup 2)))
7771 (clobber (reg:CC 17))])]
7775 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7776 ;; Penalize eax case slightly because it results in worse scheduling
7778 (define_insn "*divmoddi4_nocltd_rex64"
7779 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7780 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7781 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7782 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7783 (mod:DI (match_dup 2) (match_dup 3)))
7784 (clobber (reg:CC 17))]
7785 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7787 [(set_attr "type" "multi")])
7789 (define_insn "*divmoddi4_cltd_rex64"
7790 [(set (match_operand:DI 0 "register_operand" "=a")
7791 (div:DI (match_operand:DI 2 "register_operand" "a")
7792 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7793 (set (match_operand:DI 1 "register_operand" "=&d")
7794 (mod:DI (match_dup 2) (match_dup 3)))
7795 (clobber (reg:CC 17))]
7796 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7798 [(set_attr "type" "multi")])
7800 (define_insn "*divmoddi_noext_rex64"
7801 [(set (match_operand:DI 0 "register_operand" "=a")
7802 (div:DI (match_operand:DI 1 "register_operand" "0")
7803 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7804 (set (match_operand:DI 3 "register_operand" "=d")
7805 (mod:DI (match_dup 1) (match_dup 2)))
7806 (use (match_operand:DI 4 "register_operand" "3"))
7807 (clobber (reg:CC 17))]
7810 [(set_attr "type" "idiv")
7811 (set_attr "mode" "DI")
7812 (set_attr "ppro_uops" "few")])
7815 [(set (match_operand:DI 0 "register_operand" "")
7816 (div:DI (match_operand:DI 1 "register_operand" "")
7817 (match_operand:DI 2 "nonimmediate_operand" "")))
7818 (set (match_operand:DI 3 "register_operand" "")
7819 (mod:DI (match_dup 1) (match_dup 2)))
7820 (clobber (reg:CC 17))]
7821 "TARGET_64BIT && reload_completed"
7822 [(parallel [(set (match_dup 3)
7823 (ashiftrt:DI (match_dup 4) (const_int 63)))
7824 (clobber (reg:CC 17))])
7825 (parallel [(set (match_dup 0)
7826 (div:DI (reg:DI 0) (match_dup 2)))
7828 (mod:DI (reg:DI 0) (match_dup 2)))
7830 (clobber (reg:CC 17))])]
7832 /* Avoid use of cltd in favor of a mov+shift. */
7833 if (!TARGET_USE_CLTD && !optimize_size)
7835 if (true_regnum (operands[1]))
7836 emit_move_insn (operands[0], operands[1]);
7838 emit_move_insn (operands[3], operands[1]);
7839 operands[4] = operands[3];
7843 if (true_regnum (operands[1]))
7845 operands[4] = operands[1];
7850 (define_expand "divmodsi4"
7851 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7852 (div:SI (match_operand:SI 1 "register_operand" "")
7853 (match_operand:SI 2 "nonimmediate_operand" "")))
7854 (set (match_operand:SI 3 "register_operand" "")
7855 (mod:SI (match_dup 1) (match_dup 2)))
7856 (clobber (reg:CC 17))])]
7860 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7861 ;; Penalize eax case slightly because it results in worse scheduling
7863 (define_insn "*divmodsi4_nocltd"
7864 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7865 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7866 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7867 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7868 (mod:SI (match_dup 2) (match_dup 3)))
7869 (clobber (reg:CC 17))]
7870 "!optimize_size && !TARGET_USE_CLTD"
7872 [(set_attr "type" "multi")])
7874 (define_insn "*divmodsi4_cltd"
7875 [(set (match_operand:SI 0 "register_operand" "=a")
7876 (div:SI (match_operand:SI 2 "register_operand" "a")
7877 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7878 (set (match_operand:SI 1 "register_operand" "=&d")
7879 (mod:SI (match_dup 2) (match_dup 3)))
7880 (clobber (reg:CC 17))]
7881 "optimize_size || TARGET_USE_CLTD"
7883 [(set_attr "type" "multi")])
7885 (define_insn "*divmodsi_noext"
7886 [(set (match_operand:SI 0 "register_operand" "=a")
7887 (div:SI (match_operand:SI 1 "register_operand" "0")
7888 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7889 (set (match_operand:SI 3 "register_operand" "=d")
7890 (mod:SI (match_dup 1) (match_dup 2)))
7891 (use (match_operand:SI 4 "register_operand" "3"))
7892 (clobber (reg:CC 17))]
7895 [(set_attr "type" "idiv")
7896 (set_attr "mode" "SI")
7897 (set_attr "ppro_uops" "few")])
7900 [(set (match_operand:SI 0 "register_operand" "")
7901 (div:SI (match_operand:SI 1 "register_operand" "")
7902 (match_operand:SI 2 "nonimmediate_operand" "")))
7903 (set (match_operand:SI 3 "register_operand" "")
7904 (mod:SI (match_dup 1) (match_dup 2)))
7905 (clobber (reg:CC 17))]
7907 [(parallel [(set (match_dup 3)
7908 (ashiftrt:SI (match_dup 4) (const_int 31)))
7909 (clobber (reg:CC 17))])
7910 (parallel [(set (match_dup 0)
7911 (div:SI (reg:SI 0) (match_dup 2)))
7913 (mod:SI (reg:SI 0) (match_dup 2)))
7915 (clobber (reg:CC 17))])]
7917 /* Avoid use of cltd in favor of a mov+shift. */
7918 if (!TARGET_USE_CLTD && !optimize_size)
7920 if (true_regnum (operands[1]))
7921 emit_move_insn (operands[0], operands[1]);
7923 emit_move_insn (operands[3], operands[1]);
7924 operands[4] = operands[3];
7928 if (true_regnum (operands[1]))
7930 operands[4] = operands[1];
7934 (define_insn "divmodhi4"
7935 [(set (match_operand:HI 0 "register_operand" "=a")
7936 (div:HI (match_operand:HI 1 "register_operand" "0")
7937 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7938 (set (match_operand:HI 3 "register_operand" "=&d")
7939 (mod:HI (match_dup 1) (match_dup 2)))
7940 (clobber (reg:CC 17))]
7941 "TARGET_HIMODE_MATH"
7943 [(set_attr "type" "multi")
7944 (set_attr "length_immediate" "0")
7945 (set_attr "mode" "SI")])
7947 (define_insn "udivmoddi4"
7948 [(set (match_operand:DI 0 "register_operand" "=a")
7949 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7950 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7951 (set (match_operand:DI 3 "register_operand" "=&d")
7952 (umod:DI (match_dup 1) (match_dup 2)))
7953 (clobber (reg:CC 17))]
7955 "xor{q}\t%3, %3\;div{q}\t%2"
7956 [(set_attr "type" "multi")
7957 (set_attr "length_immediate" "0")
7958 (set_attr "mode" "DI")])
7960 (define_insn "*udivmoddi4_noext"
7961 [(set (match_operand:DI 0 "register_operand" "=a")
7962 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7963 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7964 (set (match_operand:DI 3 "register_operand" "=d")
7965 (umod:DI (match_dup 1) (match_dup 2)))
7967 (clobber (reg:CC 17))]
7970 [(set_attr "type" "idiv")
7971 (set_attr "ppro_uops" "few")
7972 (set_attr "mode" "DI")])
7975 [(set (match_operand:DI 0 "register_operand" "")
7976 (udiv:DI (match_operand:DI 1 "register_operand" "")
7977 (match_operand:DI 2 "nonimmediate_operand" "")))
7978 (set (match_operand:DI 3 "register_operand" "")
7979 (umod:DI (match_dup 1) (match_dup 2)))
7980 (clobber (reg:CC 17))]
7981 "TARGET_64BIT && reload_completed"
7982 [(set (match_dup 3) (const_int 0))
7983 (parallel [(set (match_dup 0)
7984 (udiv:DI (match_dup 1) (match_dup 2)))
7986 (umod:DI (match_dup 1) (match_dup 2)))
7988 (clobber (reg:CC 17))])]
7991 (define_insn "udivmodsi4"
7992 [(set (match_operand:SI 0 "register_operand" "=a")
7993 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7994 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7995 (set (match_operand:SI 3 "register_operand" "=&d")
7996 (umod:SI (match_dup 1) (match_dup 2)))
7997 (clobber (reg:CC 17))]
7999 "xor{l}\t%3, %3\;div{l}\t%2"
8000 [(set_attr "type" "multi")
8001 (set_attr "length_immediate" "0")
8002 (set_attr "mode" "SI")])
8004 (define_insn "*udivmodsi4_noext"
8005 [(set (match_operand:SI 0 "register_operand" "=a")
8006 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8007 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8008 (set (match_operand:SI 3 "register_operand" "=d")
8009 (umod:SI (match_dup 1) (match_dup 2)))
8011 (clobber (reg:CC 17))]
8014 [(set_attr "type" "idiv")
8015 (set_attr "ppro_uops" "few")
8016 (set_attr "mode" "SI")])
8019 [(set (match_operand:SI 0 "register_operand" "")
8020 (udiv:SI (match_operand:SI 1 "register_operand" "")
8021 (match_operand:SI 2 "nonimmediate_operand" "")))
8022 (set (match_operand:SI 3 "register_operand" "")
8023 (umod:SI (match_dup 1) (match_dup 2)))
8024 (clobber (reg:CC 17))]
8026 [(set (match_dup 3) (const_int 0))
8027 (parallel [(set (match_dup 0)
8028 (udiv:SI (match_dup 1) (match_dup 2)))
8030 (umod:SI (match_dup 1) (match_dup 2)))
8032 (clobber (reg:CC 17))])]
8035 (define_expand "udivmodhi4"
8036 [(set (match_dup 4) (const_int 0))
8037 (parallel [(set (match_operand:HI 0 "register_operand" "")
8038 (udiv:HI (match_operand:HI 1 "register_operand" "")
8039 (match_operand:HI 2 "nonimmediate_operand" "")))
8040 (set (match_operand:HI 3 "register_operand" "")
8041 (umod:HI (match_dup 1) (match_dup 2)))
8043 (clobber (reg:CC 17))])]
8044 "TARGET_HIMODE_MATH"
8045 "operands[4] = gen_reg_rtx (HImode);")
8047 (define_insn "*udivmodhi_noext"
8048 [(set (match_operand:HI 0 "register_operand" "=a")
8049 (udiv:HI (match_operand:HI 1 "register_operand" "0")
8050 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8051 (set (match_operand:HI 3 "register_operand" "=d")
8052 (umod:HI (match_dup 1) (match_dup 2)))
8053 (use (match_operand:HI 4 "register_operand" "3"))
8054 (clobber (reg:CC 17))]
8057 [(set_attr "type" "idiv")
8058 (set_attr "mode" "HI")
8059 (set_attr "ppro_uops" "few")])
8061 ;; We can not use div/idiv for double division, because it causes
8062 ;; "division by zero" on the overflow and that's not what we expect
8063 ;; from truncate. Because true (non truncating) double division is
8064 ;; never generated, we can't create this insn anyway.
8067 ; [(set (match_operand:SI 0 "register_operand" "=a")
8069 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
8071 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
8072 ; (set (match_operand:SI 3 "register_operand" "=d")
8074 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
8075 ; (clobber (reg:CC 17))]
8077 ; "div{l}\t{%2, %0|%0, %2}"
8078 ; [(set_attr "type" "idiv")
8079 ; (set_attr "ppro_uops" "few")])
8081 ;;- Logical AND instructions
8083 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
8084 ;; Note that this excludes ah.
8086 (define_insn "*testdi_1_rex64"
8089 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
8090 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
8092 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8093 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8095 test{l}\t{%k1, %k0|%k0, %k1}
8096 test{l}\t{%k1, %k0|%k0, %k1}
8097 test{q}\t{%1, %0|%0, %1}
8098 test{q}\t{%1, %0|%0, %1}
8099 test{q}\t{%1, %0|%0, %1}"
8100 [(set_attr "type" "test")
8101 (set_attr "modrm" "0,1,0,1,1")
8102 (set_attr "mode" "SI,SI,DI,DI,DI")
8103 (set_attr "pent_pair" "uv,np,uv,np,uv")])
8105 (define_insn "testsi_1"
8108 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
8109 (match_operand:SI 1 "general_operand" "in,in,rin"))
8111 "ix86_match_ccmode (insn, CCNOmode)
8112 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8113 "test{l}\t{%1, %0|%0, %1}"
8114 [(set_attr "type" "test")
8115 (set_attr "modrm" "0,1,1")
8116 (set_attr "mode" "SI")
8117 (set_attr "pent_pair" "uv,np,uv")])
8119 (define_expand "testsi_ccno_1"
8122 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
8123 (match_operand:SI 1 "nonmemory_operand" ""))
8128 (define_insn "*testhi_1"
8130 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
8131 (match_operand:HI 1 "general_operand" "n,n,rn"))
8133 "ix86_match_ccmode (insn, CCNOmode)
8134 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8135 "test{w}\t{%1, %0|%0, %1}"
8136 [(set_attr "type" "test")
8137 (set_attr "modrm" "0,1,1")
8138 (set_attr "mode" "HI")
8139 (set_attr "pent_pair" "uv,np,uv")])
8141 (define_expand "testqi_ccz_1"
8143 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8144 (match_operand:QI 1 "nonmemory_operand" ""))
8149 (define_insn "*testqi_1"
8151 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
8152 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
8154 "ix86_match_ccmode (insn, CCNOmode)
8155 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8157 if (which_alternative == 3)
8159 if (GET_CODE (operands[1]) == CONST_INT
8160 && (INTVAL (operands[1]) & 0xffffff00))
8161 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8162 return "test{l}\t{%1, %k0|%k0, %1}";
8164 return "test{b}\t{%1, %0|%0, %1}";
8166 [(set_attr "type" "test")
8167 (set_attr "modrm" "0,1,1,1")
8168 (set_attr "mode" "QI,QI,QI,SI")
8169 (set_attr "pent_pair" "uv,np,uv,np")])
8171 (define_expand "testqi_ext_ccno_0"
8176 (match_operand 0 "ext_register_operand" "")
8179 (match_operand 1 "const_int_operand" ""))
8184 (define_insn "*testqi_ext_0"
8189 (match_operand 0 "ext_register_operand" "Q")
8192 (match_operand 1 "const_int_operand" "n"))
8194 "ix86_match_ccmode (insn, CCNOmode)"
8195 "test{b}\t{%1, %h0|%h0, %1}"
8196 [(set_attr "type" "test")
8197 (set_attr "mode" "QI")
8198 (set_attr "length_immediate" "1")
8199 (set_attr "pent_pair" "np")])
8201 (define_insn "*testqi_ext_1"
8206 (match_operand 0 "ext_register_operand" "Q")
8210 (match_operand:QI 1 "general_operand" "Qm")))
8212 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8213 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8214 "test{b}\t{%1, %h0|%h0, %1}"
8215 [(set_attr "type" "test")
8216 (set_attr "mode" "QI")])
8218 (define_insn "*testqi_ext_1_rex64"
8223 (match_operand 0 "ext_register_operand" "Q")
8227 (match_operand:QI 1 "register_operand" "Q")))
8229 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8230 "test{b}\t{%1, %h0|%h0, %1}"
8231 [(set_attr "type" "test")
8232 (set_attr "mode" "QI")])
8234 (define_insn "*testqi_ext_2"
8239 (match_operand 0 "ext_register_operand" "Q")
8243 (match_operand 1 "ext_register_operand" "Q")
8247 "ix86_match_ccmode (insn, CCNOmode)"
8248 "test{b}\t{%h1, %h0|%h0, %h1}"
8249 [(set_attr "type" "test")
8250 (set_attr "mode" "QI")])
8252 ;; Combine likes to form bit extractions for some tests. Humor it.
8253 (define_insn "*testqi_ext_3"
8255 (compare (zero_extract:SI
8256 (match_operand 0 "nonimmediate_operand" "rm")
8257 (match_operand:SI 1 "const_int_operand" "")
8258 (match_operand:SI 2 "const_int_operand" ""))
8260 "ix86_match_ccmode (insn, CCNOmode)
8261 && (GET_MODE (operands[0]) == SImode
8262 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8263 || GET_MODE (operands[0]) == HImode
8264 || GET_MODE (operands[0]) == QImode)"
8267 (define_insn "*testqi_ext_3_rex64"
8269 (compare (zero_extract:DI
8270 (match_operand 0 "nonimmediate_operand" "rm")
8271 (match_operand:DI 1 "const_int_operand" "")
8272 (match_operand:DI 2 "const_int_operand" ""))
8275 && ix86_match_ccmode (insn, CCNOmode)
8276 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8277 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8278 /* Ensure that resulting mask is zero or sign extended operand. */
8279 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8280 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8281 && INTVAL (operands[1]) > 32))
8282 && (GET_MODE (operands[0]) == SImode
8283 || GET_MODE (operands[0]) == DImode
8284 || GET_MODE (operands[0]) == HImode
8285 || GET_MODE (operands[0]) == QImode)"
8290 (compare (zero_extract
8291 (match_operand 0 "nonimmediate_operand" "")
8292 (match_operand 1 "const_int_operand" "")
8293 (match_operand 2 "const_int_operand" ""))
8295 "ix86_match_ccmode (insn, CCNOmode)"
8296 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8298 HOST_WIDE_INT len = INTVAL (operands[1]);
8299 HOST_WIDE_INT pos = INTVAL (operands[2]);
8301 enum machine_mode mode, submode;
8303 mode = GET_MODE (operands[0]);
8304 if (GET_CODE (operands[0]) == MEM)
8306 /* ??? Combine likes to put non-volatile mem extractions in QImode
8307 no matter the size of the test. So find a mode that works. */
8308 if (! MEM_VOLATILE_P (operands[0]))
8310 mode = smallest_mode_for_size (pos + len, MODE_INT);
8311 operands[0] = adjust_address (operands[0], mode, 0);
8314 else if (GET_CODE (operands[0]) == SUBREG
8315 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8316 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8317 && pos + len <= GET_MODE_BITSIZE (submode))
8319 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8321 operands[0] = SUBREG_REG (operands[0]);
8323 else if (mode == HImode && pos + len <= 8)
8325 /* Small HImode tests can be converted to QImode. */
8327 operands[0] = gen_lowpart (QImode, operands[0]);
8330 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8331 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8333 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8336 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8337 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8338 ;; this is relatively important trick.
8339 ;; Do the conversion only post-reload to avoid limiting of the register class
8344 (and (match_operand 0 "register_operand" "")
8345 (match_operand 1 "const_int_operand" ""))
8348 && QI_REG_P (operands[0])
8349 && ((ix86_match_ccmode (insn, CCZmode)
8350 && !(INTVAL (operands[1]) & ~(255 << 8)))
8351 || (ix86_match_ccmode (insn, CCNOmode)
8352 && !(INTVAL (operands[1]) & ~(127 << 8))))
8353 && GET_MODE (operands[0]) != QImode"
8356 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8359 "operands[0] = gen_lowpart (SImode, operands[0]);
8360 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8365 (and (match_operand 0 "nonimmediate_operand" "")
8366 (match_operand 1 "const_int_operand" ""))
8369 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8370 && ((ix86_match_ccmode (insn, CCZmode)
8371 && !(INTVAL (operands[1]) & ~255))
8372 || (ix86_match_ccmode (insn, CCNOmode)
8373 && !(INTVAL (operands[1]) & ~127)))
8374 && GET_MODE (operands[0]) != QImode"
8377 (and:QI (match_dup 0)
8380 "operands[0] = gen_lowpart (QImode, operands[0]);
8381 operands[1] = gen_lowpart (QImode, operands[1]);")
8384 ;; %%% This used to optimize known byte-wide and operations to memory,
8385 ;; and sometimes to QImode registers. If this is considered useful,
8386 ;; it should be done with splitters.
8388 (define_expand "anddi3"
8389 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8390 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8391 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8392 (clobber (reg:CC 17))]
8394 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8396 (define_insn "*anddi_1_rex64"
8397 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8398 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8399 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8400 (clobber (reg:CC 17))]
8401 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8403 switch (get_attr_type (insn))
8407 enum machine_mode mode;
8409 if (GET_CODE (operands[2]) != CONST_INT)
8411 if (INTVAL (operands[2]) == 0xff)
8413 else if (INTVAL (operands[2]) == 0xffff)
8418 operands[1] = gen_lowpart (mode, operands[1]);
8420 return "movz{bq|x}\t{%1,%0|%0, %1}";
8422 return "movz{wq|x}\t{%1,%0|%0, %1}";
8426 if (! rtx_equal_p (operands[0], operands[1]))
8428 if (get_attr_mode (insn) == MODE_SI)
8429 return "and{l}\t{%k2, %k0|%k0, %k2}";
8431 return "and{q}\t{%2, %0|%0, %2}";
8434 [(set_attr "type" "alu,alu,alu,imovx")
8435 (set_attr "length_immediate" "*,*,*,0")
8436 (set_attr "mode" "SI,DI,DI,DI")])
8438 (define_insn "*anddi_2"
8440 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8441 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8443 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8444 (and:DI (match_dup 1) (match_dup 2)))]
8445 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8446 && ix86_binary_operator_ok (AND, DImode, operands)"
8448 and{l}\t{%k2, %k0|%k0, %k2}
8449 and{q}\t{%2, %0|%0, %2}
8450 and{q}\t{%2, %0|%0, %2}"
8451 [(set_attr "type" "alu")
8452 (set_attr "mode" "SI,DI,DI")])
8454 (define_expand "andsi3"
8455 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8456 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8457 (match_operand:SI 2 "general_operand" "")))
8458 (clobber (reg:CC 17))]
8460 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8462 (define_insn "*andsi_1"
8463 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8464 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8465 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8466 (clobber (reg:CC 17))]
8467 "ix86_binary_operator_ok (AND, SImode, operands)"
8469 switch (get_attr_type (insn))
8473 enum machine_mode mode;
8475 if (GET_CODE (operands[2]) != CONST_INT)
8477 if (INTVAL (operands[2]) == 0xff)
8479 else if (INTVAL (operands[2]) == 0xffff)
8484 operands[1] = gen_lowpart (mode, operands[1]);
8486 return "movz{bl|x}\t{%1,%0|%0, %1}";
8488 return "movz{wl|x}\t{%1,%0|%0, %1}";
8492 if (! rtx_equal_p (operands[0], operands[1]))
8494 return "and{l}\t{%2, %0|%0, %2}";
8497 [(set_attr "type" "alu,alu,imovx")
8498 (set_attr "length_immediate" "*,*,0")
8499 (set_attr "mode" "SI")])
8502 [(set (match_operand 0 "register_operand" "")
8504 (const_int -65536)))
8505 (clobber (reg:CC 17))]
8506 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8507 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8508 "operands[1] = gen_lowpart (HImode, operands[0]);")
8511 [(set (match_operand 0 "ext_register_operand" "")
8514 (clobber (reg:CC 17))]
8515 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8516 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8517 "operands[1] = gen_lowpart (QImode, operands[0]);")
8520 [(set (match_operand 0 "ext_register_operand" "")
8522 (const_int -65281)))
8523 (clobber (reg:CC 17))]
8524 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8525 [(parallel [(set (zero_extract:SI (match_dup 0)
8529 (zero_extract:SI (match_dup 0)
8532 (zero_extract:SI (match_dup 0)
8535 (clobber (reg:CC 17))])]
8536 "operands[0] = gen_lowpart (SImode, operands[0]);")
8538 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8539 (define_insn "*andsi_1_zext"
8540 [(set (match_operand:DI 0 "register_operand" "=r")
8542 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8543 (match_operand:SI 2 "general_operand" "rim"))))
8544 (clobber (reg:CC 17))]
8545 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8546 "and{l}\t{%2, %k0|%k0, %2}"
8547 [(set_attr "type" "alu")
8548 (set_attr "mode" "SI")])
8550 (define_insn "*andsi_2"
8552 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8553 (match_operand:SI 2 "general_operand" "rim,ri"))
8555 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8556 (and:SI (match_dup 1) (match_dup 2)))]
8557 "ix86_match_ccmode (insn, CCNOmode)
8558 && ix86_binary_operator_ok (AND, SImode, operands)"
8559 "and{l}\t{%2, %0|%0, %2}"
8560 [(set_attr "type" "alu")
8561 (set_attr "mode" "SI")])
8563 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8564 (define_insn "*andsi_2_zext"
8566 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8567 (match_operand:SI 2 "general_operand" "rim"))
8569 (set (match_operand:DI 0 "register_operand" "=r")
8570 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8571 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8572 && ix86_binary_operator_ok (AND, SImode, operands)"
8573 "and{l}\t{%2, %k0|%k0, %2}"
8574 [(set_attr "type" "alu")
8575 (set_attr "mode" "SI")])
8577 (define_expand "andhi3"
8578 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8579 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8580 (match_operand:HI 2 "general_operand" "")))
8581 (clobber (reg:CC 17))]
8582 "TARGET_HIMODE_MATH"
8583 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8585 (define_insn "*andhi_1"
8586 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8587 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8588 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8589 (clobber (reg:CC 17))]
8590 "ix86_binary_operator_ok (AND, HImode, operands)"
8592 switch (get_attr_type (insn))
8595 if (GET_CODE (operands[2]) != CONST_INT)
8597 if (INTVAL (operands[2]) == 0xff)
8598 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8602 if (! rtx_equal_p (operands[0], operands[1]))
8605 return "and{w}\t{%2, %0|%0, %2}";
8608 [(set_attr "type" "alu,alu,imovx")
8609 (set_attr "length_immediate" "*,*,0")
8610 (set_attr "mode" "HI,HI,SI")])
8612 (define_insn "*andhi_2"
8614 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8615 (match_operand:HI 2 "general_operand" "rim,ri"))
8617 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8618 (and:HI (match_dup 1) (match_dup 2)))]
8619 "ix86_match_ccmode (insn, CCNOmode)
8620 && ix86_binary_operator_ok (AND, HImode, operands)"
8621 "and{w}\t{%2, %0|%0, %2}"
8622 [(set_attr "type" "alu")
8623 (set_attr "mode" "HI")])
8625 (define_expand "andqi3"
8626 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8627 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8628 (match_operand:QI 2 "general_operand" "")))
8629 (clobber (reg:CC 17))]
8630 "TARGET_QIMODE_MATH"
8631 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8633 ;; %%% Potential partial reg stall on alternative 2. What to do?
8634 (define_insn "*andqi_1"
8635 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8636 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8637 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8638 (clobber (reg:CC 17))]
8639 "ix86_binary_operator_ok (AND, QImode, operands)"
8641 and{b}\t{%2, %0|%0, %2}
8642 and{b}\t{%2, %0|%0, %2}
8643 and{l}\t{%k2, %k0|%k0, %k2}"
8644 [(set_attr "type" "alu")
8645 (set_attr "mode" "QI,QI,SI")])
8647 (define_insn "*andqi_1_slp"
8648 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8649 (and:QI (match_dup 0)
8650 (match_operand:QI 1 "general_operand" "qi,qmi")))
8651 (clobber (reg:CC 17))]
8652 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8653 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8654 "and{b}\t{%1, %0|%0, %1}"
8655 [(set_attr "type" "alu1")
8656 (set_attr "mode" "QI")])
8658 (define_insn "*andqi_2"
8661 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8662 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8664 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8665 (and:QI (match_dup 1) (match_dup 2)))]
8666 "ix86_match_ccmode (insn, CCNOmode)
8667 && ix86_binary_operator_ok (AND, QImode, operands)"
8669 if (which_alternative == 2)
8671 if (GET_CODE (operands[2]) == CONST_INT
8672 && (INTVAL (operands[2]) & 0xffffff00))
8673 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8674 return "and{l}\t{%2, %k0|%k0, %2}";
8676 return "and{b}\t{%2, %0|%0, %2}";
8678 [(set_attr "type" "alu")
8679 (set_attr "mode" "QI,QI,SI")])
8681 (define_insn "*andqi_2_slp"
8684 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8685 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8687 (set (strict_low_part (match_dup 0))
8688 (and:QI (match_dup 0) (match_dup 1)))]
8689 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8690 && ix86_match_ccmode (insn, CCNOmode)
8691 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8692 "and{b}\t{%1, %0|%0, %1}"
8693 [(set_attr "type" "alu1")
8694 (set_attr "mode" "QI")])
8696 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8697 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8698 ;; for a QImode operand, which of course failed.
8700 (define_insn "andqi_ext_0"
8701 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8706 (match_operand 1 "ext_register_operand" "0")
8709 (match_operand 2 "const_int_operand" "n")))
8710 (clobber (reg:CC 17))]
8712 "and{b}\t{%2, %h0|%h0, %2}"
8713 [(set_attr "type" "alu")
8714 (set_attr "length_immediate" "1")
8715 (set_attr "mode" "QI")])
8717 ;; Generated by peephole translating test to and. This shows up
8718 ;; often in fp comparisons.
8720 (define_insn "*andqi_ext_0_cc"
8725 (match_operand 1 "ext_register_operand" "0")
8728 (match_operand 2 "const_int_operand" "n"))
8730 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8739 "ix86_match_ccmode (insn, CCNOmode)"
8740 "and{b}\t{%2, %h0|%h0, %2}"
8741 [(set_attr "type" "alu")
8742 (set_attr "length_immediate" "1")
8743 (set_attr "mode" "QI")])
8745 (define_insn "*andqi_ext_1"
8746 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8751 (match_operand 1 "ext_register_operand" "0")
8755 (match_operand:QI 2 "general_operand" "Qm"))))
8756 (clobber (reg:CC 17))]
8758 "and{b}\t{%2, %h0|%h0, %2}"
8759 [(set_attr "type" "alu")
8760 (set_attr "length_immediate" "0")
8761 (set_attr "mode" "QI")])
8763 (define_insn "*andqi_ext_1_rex64"
8764 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8769 (match_operand 1 "ext_register_operand" "0")
8773 (match_operand 2 "ext_register_operand" "Q"))))
8774 (clobber (reg:CC 17))]
8776 "and{b}\t{%2, %h0|%h0, %2}"
8777 [(set_attr "type" "alu")
8778 (set_attr "length_immediate" "0")
8779 (set_attr "mode" "QI")])
8781 (define_insn "*andqi_ext_2"
8782 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8787 (match_operand 1 "ext_register_operand" "%0")
8791 (match_operand 2 "ext_register_operand" "Q")
8794 (clobber (reg:CC 17))]
8796 "and{b}\t{%h2, %h0|%h0, %h2}"
8797 [(set_attr "type" "alu")
8798 (set_attr "length_immediate" "0")
8799 (set_attr "mode" "QI")])
8801 ;; Convert wide AND instructions with immediate operand to shorter QImode
8802 ;; equivalents when possible.
8803 ;; Don't do the splitting with memory operands, since it introduces risk
8804 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8805 ;; for size, but that can (should?) be handled by generic code instead.
8807 [(set (match_operand 0 "register_operand" "")
8808 (and (match_operand 1 "register_operand" "")
8809 (match_operand 2 "const_int_operand" "")))
8810 (clobber (reg:CC 17))]
8812 && QI_REG_P (operands[0])
8813 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8814 && !(~INTVAL (operands[2]) & ~(255 << 8))
8815 && GET_MODE (operands[0]) != QImode"
8816 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8817 (and:SI (zero_extract:SI (match_dup 1)
8818 (const_int 8) (const_int 8))
8820 (clobber (reg:CC 17))])]
8821 "operands[0] = gen_lowpart (SImode, operands[0]);
8822 operands[1] = gen_lowpart (SImode, operands[1]);
8823 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8825 ;; Since AND can be encoded with sign extended immediate, this is only
8826 ;; profitable when 7th bit is not set.
8828 [(set (match_operand 0 "register_operand" "")
8829 (and (match_operand 1 "general_operand" "")
8830 (match_operand 2 "const_int_operand" "")))
8831 (clobber (reg:CC 17))]
8833 && ANY_QI_REG_P (operands[0])
8834 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8835 && !(~INTVAL (operands[2]) & ~255)
8836 && !(INTVAL (operands[2]) & 128)
8837 && GET_MODE (operands[0]) != QImode"
8838 [(parallel [(set (strict_low_part (match_dup 0))
8839 (and:QI (match_dup 1)
8841 (clobber (reg:CC 17))])]
8842 "operands[0] = gen_lowpart (QImode, operands[0]);
8843 operands[1] = gen_lowpart (QImode, operands[1]);
8844 operands[2] = gen_lowpart (QImode, operands[2]);")
8846 ;; Logical inclusive OR instructions
8848 ;; %%% This used to optimize known byte-wide and operations to memory.
8849 ;; If this is considered useful, it should be done with splitters.
8851 (define_expand "iordi3"
8852 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8853 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8854 (match_operand:DI 2 "x86_64_general_operand" "")))
8855 (clobber (reg:CC 17))]
8857 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8859 (define_insn "*iordi_1_rex64"
8860 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8861 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8862 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8863 (clobber (reg:CC 17))]
8865 && ix86_binary_operator_ok (IOR, DImode, operands)"
8866 "or{q}\t{%2, %0|%0, %2}"
8867 [(set_attr "type" "alu")
8868 (set_attr "mode" "DI")])
8870 (define_insn "*iordi_2_rex64"
8872 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8873 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8875 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8876 (ior:DI (match_dup 1) (match_dup 2)))]
8878 && ix86_match_ccmode (insn, CCNOmode)
8879 && ix86_binary_operator_ok (IOR, DImode, operands)"
8880 "or{q}\t{%2, %0|%0, %2}"
8881 [(set_attr "type" "alu")
8882 (set_attr "mode" "DI")])
8884 (define_insn "*iordi_3_rex64"
8886 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8887 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8889 (clobber (match_scratch:DI 0 "=r"))]
8891 && ix86_match_ccmode (insn, CCNOmode)
8892 && ix86_binary_operator_ok (IOR, DImode, operands)"
8893 "or{q}\t{%2, %0|%0, %2}"
8894 [(set_attr "type" "alu")
8895 (set_attr "mode" "DI")])
8898 (define_expand "iorsi3"
8899 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8900 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8901 (match_operand:SI 2 "general_operand" "")))
8902 (clobber (reg:CC 17))]
8904 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8906 (define_insn "*iorsi_1"
8907 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8908 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8909 (match_operand:SI 2 "general_operand" "ri,rmi")))
8910 (clobber (reg:CC 17))]
8911 "ix86_binary_operator_ok (IOR, SImode, operands)"
8912 "or{l}\t{%2, %0|%0, %2}"
8913 [(set_attr "type" "alu")
8914 (set_attr "mode" "SI")])
8916 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8917 (define_insn "*iorsi_1_zext"
8918 [(set (match_operand:DI 0 "register_operand" "=rm")
8920 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8921 (match_operand:SI 2 "general_operand" "rim"))))
8922 (clobber (reg:CC 17))]
8923 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8924 "or{l}\t{%2, %k0|%k0, %2}"
8925 [(set_attr "type" "alu")
8926 (set_attr "mode" "SI")])
8928 (define_insn "*iorsi_1_zext_imm"
8929 [(set (match_operand:DI 0 "register_operand" "=rm")
8930 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8931 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8932 (clobber (reg:CC 17))]
8934 "or{l}\t{%2, %k0|%k0, %2}"
8935 [(set_attr "type" "alu")
8936 (set_attr "mode" "SI")])
8938 (define_insn "*iorsi_2"
8940 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8941 (match_operand:SI 2 "general_operand" "rim,ri"))
8943 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8944 (ior:SI (match_dup 1) (match_dup 2)))]
8945 "ix86_match_ccmode (insn, CCNOmode)
8946 && ix86_binary_operator_ok (IOR, SImode, operands)"
8947 "or{l}\t{%2, %0|%0, %2}"
8948 [(set_attr "type" "alu")
8949 (set_attr "mode" "SI")])
8951 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8952 ;; ??? Special case for immediate operand is missing - it is tricky.
8953 (define_insn "*iorsi_2_zext"
8955 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8956 (match_operand:SI 2 "general_operand" "rim"))
8958 (set (match_operand:DI 0 "register_operand" "=r")
8959 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8960 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8961 && ix86_binary_operator_ok (IOR, SImode, operands)"
8962 "or{l}\t{%2, %k0|%k0, %2}"
8963 [(set_attr "type" "alu")
8964 (set_attr "mode" "SI")])
8966 (define_insn "*iorsi_2_zext_imm"
8968 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8969 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8971 (set (match_operand:DI 0 "register_operand" "=r")
8972 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8973 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8974 && ix86_binary_operator_ok (IOR, SImode, operands)"
8975 "or{l}\t{%2, %k0|%k0, %2}"
8976 [(set_attr "type" "alu")
8977 (set_attr "mode" "SI")])
8979 (define_insn "*iorsi_3"
8981 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8982 (match_operand:SI 2 "general_operand" "rim"))
8984 (clobber (match_scratch:SI 0 "=r"))]
8985 "ix86_match_ccmode (insn, CCNOmode)
8986 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8987 "or{l}\t{%2, %0|%0, %2}"
8988 [(set_attr "type" "alu")
8989 (set_attr "mode" "SI")])
8991 (define_expand "iorhi3"
8992 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8993 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8994 (match_operand:HI 2 "general_operand" "")))
8995 (clobber (reg:CC 17))]
8996 "TARGET_HIMODE_MATH"
8997 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8999 (define_insn "*iorhi_1"
9000 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9001 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9002 (match_operand:HI 2 "general_operand" "rmi,ri")))
9003 (clobber (reg:CC 17))]
9004 "ix86_binary_operator_ok (IOR, HImode, operands)"
9005 "or{w}\t{%2, %0|%0, %2}"
9006 [(set_attr "type" "alu")
9007 (set_attr "mode" "HI")])
9009 (define_insn "*iorhi_2"
9011 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9012 (match_operand:HI 2 "general_operand" "rim,ri"))
9014 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9015 (ior:HI (match_dup 1) (match_dup 2)))]
9016 "ix86_match_ccmode (insn, CCNOmode)
9017 && ix86_binary_operator_ok (IOR, HImode, operands)"
9018 "or{w}\t{%2, %0|%0, %2}"
9019 [(set_attr "type" "alu")
9020 (set_attr "mode" "HI")])
9022 (define_insn "*iorhi_3"
9024 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9025 (match_operand:HI 2 "general_operand" "rim"))
9027 (clobber (match_scratch:HI 0 "=r"))]
9028 "ix86_match_ccmode (insn, CCNOmode)
9029 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9030 "or{w}\t{%2, %0|%0, %2}"
9031 [(set_attr "type" "alu")
9032 (set_attr "mode" "HI")])
9034 (define_expand "iorqi3"
9035 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9036 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
9037 (match_operand:QI 2 "general_operand" "")))
9038 (clobber (reg:CC 17))]
9039 "TARGET_QIMODE_MATH"
9040 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
9042 ;; %%% Potential partial reg stall on alternative 2. What to do?
9043 (define_insn "*iorqi_1"
9044 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9045 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9046 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9047 (clobber (reg:CC 17))]
9048 "ix86_binary_operator_ok (IOR, QImode, operands)"
9050 or{b}\t{%2, %0|%0, %2}
9051 or{b}\t{%2, %0|%0, %2}
9052 or{l}\t{%k2, %k0|%k0, %k2}"
9053 [(set_attr "type" "alu")
9054 (set_attr "mode" "QI,QI,SI")])
9056 (define_insn "*iorqi_1_slp"
9057 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
9058 (ior:QI (match_dup 0)
9059 (match_operand:QI 1 "general_operand" "qmi,qi")))
9060 (clobber (reg:CC 17))]
9061 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9062 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9063 "or{b}\t{%1, %0|%0, %1}"
9064 [(set_attr "type" "alu1")
9065 (set_attr "mode" "QI")])
9067 (define_insn "*iorqi_2"
9069 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9070 (match_operand:QI 2 "general_operand" "qim,qi"))
9072 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9073 (ior:QI (match_dup 1) (match_dup 2)))]
9074 "ix86_match_ccmode (insn, CCNOmode)
9075 && ix86_binary_operator_ok (IOR, QImode, operands)"
9076 "or{b}\t{%2, %0|%0, %2}"
9077 [(set_attr "type" "alu")
9078 (set_attr "mode" "QI")])
9080 (define_insn "*iorqi_2_slp"
9082 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9083 (match_operand:QI 1 "general_operand" "qim,qi"))
9085 (set (strict_low_part (match_dup 0))
9086 (ior:QI (match_dup 0) (match_dup 1)))]
9087 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9088 && ix86_match_ccmode (insn, CCNOmode)
9089 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9090 "or{b}\t{%1, %0|%0, %1}"
9091 [(set_attr "type" "alu1")
9092 (set_attr "mode" "QI")])
9094 (define_insn "*iorqi_3"
9096 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9097 (match_operand:QI 2 "general_operand" "qim"))
9099 (clobber (match_scratch:QI 0 "=q"))]
9100 "ix86_match_ccmode (insn, CCNOmode)
9101 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9102 "or{b}\t{%2, %0|%0, %2}"
9103 [(set_attr "type" "alu")
9104 (set_attr "mode" "QI")])
9106 (define_insn "iorqi_ext_0"
9107 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9112 (match_operand 1 "ext_register_operand" "0")
9115 (match_operand 2 "const_int_operand" "n")))
9116 (clobber (reg:CC 17))]
9117 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9118 "or{b}\t{%2, %h0|%h0, %2}"
9119 [(set_attr "type" "alu")
9120 (set_attr "length_immediate" "1")
9121 (set_attr "mode" "QI")])
9123 (define_insn "*iorqi_ext_1"
9124 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9129 (match_operand 1 "ext_register_operand" "0")
9133 (match_operand:QI 2 "general_operand" "Qm"))))
9134 (clobber (reg:CC 17))]
9136 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9137 "or{b}\t{%2, %h0|%h0, %2}"
9138 [(set_attr "type" "alu")
9139 (set_attr "length_immediate" "0")
9140 (set_attr "mode" "QI")])
9142 (define_insn "*iorqi_ext_1_rex64"
9143 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9148 (match_operand 1 "ext_register_operand" "0")
9152 (match_operand 2 "ext_register_operand" "Q"))))
9153 (clobber (reg:CC 17))]
9155 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9156 "or{b}\t{%2, %h0|%h0, %2}"
9157 [(set_attr "type" "alu")
9158 (set_attr "length_immediate" "0")
9159 (set_attr "mode" "QI")])
9161 (define_insn "*iorqi_ext_2"
9162 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9166 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9169 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9172 (clobber (reg:CC 17))]
9173 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9174 "ior{b}\t{%h2, %h0|%h0, %h2}"
9175 [(set_attr "type" "alu")
9176 (set_attr "length_immediate" "0")
9177 (set_attr "mode" "QI")])
9180 [(set (match_operand 0 "register_operand" "")
9181 (ior (match_operand 1 "register_operand" "")
9182 (match_operand 2 "const_int_operand" "")))
9183 (clobber (reg:CC 17))]
9185 && QI_REG_P (operands[0])
9186 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9187 && !(INTVAL (operands[2]) & ~(255 << 8))
9188 && GET_MODE (operands[0]) != QImode"
9189 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9190 (ior:SI (zero_extract:SI (match_dup 1)
9191 (const_int 8) (const_int 8))
9193 (clobber (reg:CC 17))])]
9194 "operands[0] = gen_lowpart (SImode, operands[0]);
9195 operands[1] = gen_lowpart (SImode, operands[1]);
9196 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9198 ;; Since OR can be encoded with sign extended immediate, this is only
9199 ;; profitable when 7th bit is set.
9201 [(set (match_operand 0 "register_operand" "")
9202 (ior (match_operand 1 "general_operand" "")
9203 (match_operand 2 "const_int_operand" "")))
9204 (clobber (reg:CC 17))]
9206 && ANY_QI_REG_P (operands[0])
9207 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9208 && !(INTVAL (operands[2]) & ~255)
9209 && (INTVAL (operands[2]) & 128)
9210 && GET_MODE (operands[0]) != QImode"
9211 [(parallel [(set (strict_low_part (match_dup 0))
9212 (ior:QI (match_dup 1)
9214 (clobber (reg:CC 17))])]
9215 "operands[0] = gen_lowpart (QImode, operands[0]);
9216 operands[1] = gen_lowpart (QImode, operands[1]);
9217 operands[2] = gen_lowpart (QImode, operands[2]);")
9219 ;; Logical XOR instructions
9221 ;; %%% This used to optimize known byte-wide and operations to memory.
9222 ;; If this is considered useful, it should be done with splitters.
9224 (define_expand "xordi3"
9225 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9226 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9227 (match_operand:DI 2 "x86_64_general_operand" "")))
9228 (clobber (reg:CC 17))]
9230 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9232 (define_insn "*xordi_1_rex64"
9233 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9234 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9235 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9236 (clobber (reg:CC 17))]
9238 && ix86_binary_operator_ok (XOR, DImode, operands)"
9240 xor{q}\t{%2, %0|%0, %2}
9241 xor{q}\t{%2, %0|%0, %2}"
9242 [(set_attr "type" "alu")
9243 (set_attr "mode" "DI,DI")])
9245 (define_insn "*xordi_2_rex64"
9247 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9248 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9250 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9251 (xor:DI (match_dup 1) (match_dup 2)))]
9253 && ix86_match_ccmode (insn, CCNOmode)
9254 && ix86_binary_operator_ok (XOR, DImode, operands)"
9256 xor{q}\t{%2, %0|%0, %2}
9257 xor{q}\t{%2, %0|%0, %2}"
9258 [(set_attr "type" "alu")
9259 (set_attr "mode" "DI,DI")])
9261 (define_insn "*xordi_3_rex64"
9263 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9264 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9266 (clobber (match_scratch:DI 0 "=r"))]
9268 && ix86_match_ccmode (insn, CCNOmode)
9269 && ix86_binary_operator_ok (XOR, DImode, operands)"
9270 "xor{q}\t{%2, %0|%0, %2}"
9271 [(set_attr "type" "alu")
9272 (set_attr "mode" "DI")])
9274 (define_expand "xorsi3"
9275 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9276 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9277 (match_operand:SI 2 "general_operand" "")))
9278 (clobber (reg:CC 17))]
9280 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9282 (define_insn "*xorsi_1"
9283 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9284 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9285 (match_operand:SI 2 "general_operand" "ri,rm")))
9286 (clobber (reg:CC 17))]
9287 "ix86_binary_operator_ok (XOR, SImode, operands)"
9288 "xor{l}\t{%2, %0|%0, %2}"
9289 [(set_attr "type" "alu")
9290 (set_attr "mode" "SI")])
9292 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9293 ;; Add speccase for immediates
9294 (define_insn "*xorsi_1_zext"
9295 [(set (match_operand:DI 0 "register_operand" "=r")
9297 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9298 (match_operand:SI 2 "general_operand" "rim"))))
9299 (clobber (reg:CC 17))]
9300 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9301 "xor{l}\t{%2, %k0|%k0, %2}"
9302 [(set_attr "type" "alu")
9303 (set_attr "mode" "SI")])
9305 (define_insn "*xorsi_1_zext_imm"
9306 [(set (match_operand:DI 0 "register_operand" "=r")
9307 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9308 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9309 (clobber (reg:CC 17))]
9310 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9311 "xor{l}\t{%2, %k0|%k0, %2}"
9312 [(set_attr "type" "alu")
9313 (set_attr "mode" "SI")])
9315 (define_insn "*xorsi_2"
9317 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9318 (match_operand:SI 2 "general_operand" "rim,ri"))
9320 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9321 (xor:SI (match_dup 1) (match_dup 2)))]
9322 "ix86_match_ccmode (insn, CCNOmode)
9323 && ix86_binary_operator_ok (XOR, SImode, operands)"
9324 "xor{l}\t{%2, %0|%0, %2}"
9325 [(set_attr "type" "alu")
9326 (set_attr "mode" "SI")])
9328 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9329 ;; ??? Special case for immediate operand is missing - it is tricky.
9330 (define_insn "*xorsi_2_zext"
9332 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9333 (match_operand:SI 2 "general_operand" "rim"))
9335 (set (match_operand:DI 0 "register_operand" "=r")
9336 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9337 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9338 && ix86_binary_operator_ok (XOR, SImode, operands)"
9339 "xor{l}\t{%2, %k0|%k0, %2}"
9340 [(set_attr "type" "alu")
9341 (set_attr "mode" "SI")])
9343 (define_insn "*xorsi_2_zext_imm"
9345 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9346 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9348 (set (match_operand:DI 0 "register_operand" "=r")
9349 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9350 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9351 && ix86_binary_operator_ok (XOR, SImode, operands)"
9352 "xor{l}\t{%2, %k0|%k0, %2}"
9353 [(set_attr "type" "alu")
9354 (set_attr "mode" "SI")])
9356 (define_insn "*xorsi_3"
9358 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9359 (match_operand:SI 2 "general_operand" "rim"))
9361 (clobber (match_scratch:SI 0 "=r"))]
9362 "ix86_match_ccmode (insn, CCNOmode)
9363 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9364 "xor{l}\t{%2, %0|%0, %2}"
9365 [(set_attr "type" "alu")
9366 (set_attr "mode" "SI")])
9368 (define_expand "xorhi3"
9369 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9370 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9371 (match_operand:HI 2 "general_operand" "")))
9372 (clobber (reg:CC 17))]
9373 "TARGET_HIMODE_MATH"
9374 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9376 (define_insn "*xorhi_1"
9377 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9378 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9379 (match_operand:HI 2 "general_operand" "rmi,ri")))
9380 (clobber (reg:CC 17))]
9381 "ix86_binary_operator_ok (XOR, HImode, operands)"
9382 "xor{w}\t{%2, %0|%0, %2}"
9383 [(set_attr "type" "alu")
9384 (set_attr "mode" "HI")])
9386 (define_insn "*xorhi_2"
9388 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9389 (match_operand:HI 2 "general_operand" "rim,ri"))
9391 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9392 (xor:HI (match_dup 1) (match_dup 2)))]
9393 "ix86_match_ccmode (insn, CCNOmode)
9394 && ix86_binary_operator_ok (XOR, HImode, operands)"
9395 "xor{w}\t{%2, %0|%0, %2}"
9396 [(set_attr "type" "alu")
9397 (set_attr "mode" "HI")])
9399 (define_insn "*xorhi_3"
9401 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9402 (match_operand:HI 2 "general_operand" "rim"))
9404 (clobber (match_scratch:HI 0 "=r"))]
9405 "ix86_match_ccmode (insn, CCNOmode)
9406 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9407 "xor{w}\t{%2, %0|%0, %2}"
9408 [(set_attr "type" "alu")
9409 (set_attr "mode" "HI")])
9411 (define_expand "xorqi3"
9412 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9413 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9414 (match_operand:QI 2 "general_operand" "")))
9415 (clobber (reg:CC 17))]
9416 "TARGET_QIMODE_MATH"
9417 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9419 ;; %%% Potential partial reg stall on alternative 2. What to do?
9420 (define_insn "*xorqi_1"
9421 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9422 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9423 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9424 (clobber (reg:CC 17))]
9425 "ix86_binary_operator_ok (XOR, QImode, operands)"
9427 xor{b}\t{%2, %0|%0, %2}
9428 xor{b}\t{%2, %0|%0, %2}
9429 xor{l}\t{%k2, %k0|%k0, %k2}"
9430 [(set_attr "type" "alu")
9431 (set_attr "mode" "QI,QI,SI")])
9433 (define_insn "*xorqi_1_slp"
9434 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9435 (xor:QI (match_dup 0)
9436 (match_operand:QI 1 "general_operand" "qi,qmi")))
9437 (clobber (reg:CC 17))]
9438 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9439 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9440 "xor{b}\t{%1, %0|%0, %1}"
9441 [(set_attr "type" "alu1")
9442 (set_attr "mode" "QI")])
9444 (define_insn "xorqi_ext_0"
9445 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9450 (match_operand 1 "ext_register_operand" "0")
9453 (match_operand 2 "const_int_operand" "n")))
9454 (clobber (reg:CC 17))]
9455 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9456 "xor{b}\t{%2, %h0|%h0, %2}"
9457 [(set_attr "type" "alu")
9458 (set_attr "length_immediate" "1")
9459 (set_attr "mode" "QI")])
9461 (define_insn "*xorqi_ext_1"
9462 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9467 (match_operand 1 "ext_register_operand" "0")
9471 (match_operand:QI 2 "general_operand" "Qm"))))
9472 (clobber (reg:CC 17))]
9474 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9475 "xor{b}\t{%2, %h0|%h0, %2}"
9476 [(set_attr "type" "alu")
9477 (set_attr "length_immediate" "0")
9478 (set_attr "mode" "QI")])
9480 (define_insn "*xorqi_ext_1_rex64"
9481 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9486 (match_operand 1 "ext_register_operand" "0")
9490 (match_operand 2 "ext_register_operand" "Q"))))
9491 (clobber (reg:CC 17))]
9493 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9494 "xor{b}\t{%2, %h0|%h0, %2}"
9495 [(set_attr "type" "alu")
9496 (set_attr "length_immediate" "0")
9497 (set_attr "mode" "QI")])
9499 (define_insn "*xorqi_ext_2"
9500 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9504 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9507 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9510 (clobber (reg:CC 17))]
9511 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9512 "xor{b}\t{%h2, %h0|%h0, %h2}"
9513 [(set_attr "type" "alu")
9514 (set_attr "length_immediate" "0")
9515 (set_attr "mode" "QI")])
9517 (define_insn "*xorqi_cc_1"
9520 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9521 (match_operand:QI 2 "general_operand" "qim,qi"))
9523 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9524 (xor:QI (match_dup 1) (match_dup 2)))]
9525 "ix86_match_ccmode (insn, CCNOmode)
9526 && ix86_binary_operator_ok (XOR, QImode, operands)"
9527 "xor{b}\t{%2, %0|%0, %2}"
9528 [(set_attr "type" "alu")
9529 (set_attr "mode" "QI")])
9531 (define_insn "*xorqi_2_slp"
9533 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9534 (match_operand:QI 1 "general_operand" "qim,qi"))
9536 (set (strict_low_part (match_dup 0))
9537 (xor:QI (match_dup 0) (match_dup 1)))]
9538 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9539 && ix86_match_ccmode (insn, CCNOmode)
9540 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9541 "xor{b}\t{%1, %0|%0, %1}"
9542 [(set_attr "type" "alu1")
9543 (set_attr "mode" "QI")])
9545 (define_insn "*xorqi_cc_2"
9548 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9549 (match_operand:QI 2 "general_operand" "qim"))
9551 (clobber (match_scratch:QI 0 "=q"))]
9552 "ix86_match_ccmode (insn, CCNOmode)
9553 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9554 "xor{b}\t{%2, %0|%0, %2}"
9555 [(set_attr "type" "alu")
9556 (set_attr "mode" "QI")])
9558 (define_insn "*xorqi_cc_ext_1"
9563 (match_operand 1 "ext_register_operand" "0")
9566 (match_operand:QI 2 "general_operand" "qmn"))
9568 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9572 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9574 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9575 "xor{b}\t{%2, %h0|%h0, %2}"
9576 [(set_attr "type" "alu")
9577 (set_attr "mode" "QI")])
9579 (define_insn "*xorqi_cc_ext_1_rex64"
9584 (match_operand 1 "ext_register_operand" "0")
9587 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9589 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9593 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9595 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9596 "xor{b}\t{%2, %h0|%h0, %2}"
9597 [(set_attr "type" "alu")
9598 (set_attr "mode" "QI")])
9600 (define_expand "xorqi_cc_ext_1"
9606 (match_operand 1 "ext_register_operand" "")
9609 (match_operand:QI 2 "general_operand" ""))
9611 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9615 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9621 [(set (match_operand 0 "register_operand" "")
9622 (xor (match_operand 1 "register_operand" "")
9623 (match_operand 2 "const_int_operand" "")))
9624 (clobber (reg:CC 17))]
9626 && QI_REG_P (operands[0])
9627 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9628 && !(INTVAL (operands[2]) & ~(255 << 8))
9629 && GET_MODE (operands[0]) != QImode"
9630 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9631 (xor:SI (zero_extract:SI (match_dup 1)
9632 (const_int 8) (const_int 8))
9634 (clobber (reg:CC 17))])]
9635 "operands[0] = gen_lowpart (SImode, operands[0]);
9636 operands[1] = gen_lowpart (SImode, operands[1]);
9637 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9639 ;; Since XOR can be encoded with sign extended immediate, this is only
9640 ;; profitable when 7th bit is set.
9642 [(set (match_operand 0 "register_operand" "")
9643 (xor (match_operand 1 "general_operand" "")
9644 (match_operand 2 "const_int_operand" "")))
9645 (clobber (reg:CC 17))]
9647 && ANY_QI_REG_P (operands[0])
9648 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9649 && !(INTVAL (operands[2]) & ~255)
9650 && (INTVAL (operands[2]) & 128)
9651 && GET_MODE (operands[0]) != QImode"
9652 [(parallel [(set (strict_low_part (match_dup 0))
9653 (xor:QI (match_dup 1)
9655 (clobber (reg:CC 17))])]
9656 "operands[0] = gen_lowpart (QImode, operands[0]);
9657 operands[1] = gen_lowpart (QImode, operands[1]);
9658 operands[2] = gen_lowpart (QImode, operands[2]);")
9660 ;; Negation instructions
9662 (define_expand "negdi2"
9663 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9664 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9665 (clobber (reg:CC 17))])]
9667 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9669 (define_insn "*negdi2_1"
9670 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9671 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9672 (clobber (reg:CC 17))]
9674 && ix86_unary_operator_ok (NEG, DImode, operands)"
9678 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9679 (neg:DI (match_operand:DI 1 "general_operand" "")))
9680 (clobber (reg:CC 17))]
9681 "!TARGET_64BIT && reload_completed"
9684 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9685 (set (match_dup 0) (neg:SI (match_dup 2)))])
9688 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9691 (clobber (reg:CC 17))])
9694 (neg:SI (match_dup 1)))
9695 (clobber (reg:CC 17))])]
9696 "split_di (operands+1, 1, operands+2, operands+3);
9697 split_di (operands+0, 1, operands+0, operands+1);")
9699 (define_insn "*negdi2_1_rex64"
9700 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9701 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9702 (clobber (reg:CC 17))]
9703 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9705 [(set_attr "type" "negnot")
9706 (set_attr "mode" "DI")])
9708 ;; The problem with neg is that it does not perform (compare x 0),
9709 ;; it really performs (compare 0 x), which leaves us with the zero
9710 ;; flag being the only useful item.
9712 (define_insn "*negdi2_cmpz_rex64"
9714 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9716 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9717 (neg:DI (match_dup 1)))]
9718 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9720 [(set_attr "type" "negnot")
9721 (set_attr "mode" "DI")])
9724 (define_expand "negsi2"
9725 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9726 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9727 (clobber (reg:CC 17))])]
9729 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9731 (define_insn "*negsi2_1"
9732 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9733 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9734 (clobber (reg:CC 17))]
9735 "ix86_unary_operator_ok (NEG, SImode, operands)"
9737 [(set_attr "type" "negnot")
9738 (set_attr "mode" "SI")])
9740 ;; Combine is quite creative about this pattern.
9741 (define_insn "*negsi2_1_zext"
9742 [(set (match_operand:DI 0 "register_operand" "=r")
9743 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9746 (clobber (reg:CC 17))]
9747 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9749 [(set_attr "type" "negnot")
9750 (set_attr "mode" "SI")])
9752 ;; The problem with neg is that it does not perform (compare x 0),
9753 ;; it really performs (compare 0 x), which leaves us with the zero
9754 ;; flag being the only useful item.
9756 (define_insn "*negsi2_cmpz"
9758 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9760 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9761 (neg:SI (match_dup 1)))]
9762 "ix86_unary_operator_ok (NEG, SImode, operands)"
9764 [(set_attr "type" "negnot")
9765 (set_attr "mode" "SI")])
9767 (define_insn "*negsi2_cmpz_zext"
9769 (compare:CCZ (lshiftrt:DI
9771 (match_operand:DI 1 "register_operand" "0")
9775 (set (match_operand:DI 0 "register_operand" "=r")
9776 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9779 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9781 [(set_attr "type" "negnot")
9782 (set_attr "mode" "SI")])
9784 (define_expand "neghi2"
9785 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9786 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9787 (clobber (reg:CC 17))])]
9788 "TARGET_HIMODE_MATH"
9789 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9791 (define_insn "*neghi2_1"
9792 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9793 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9794 (clobber (reg:CC 17))]
9795 "ix86_unary_operator_ok (NEG, HImode, operands)"
9797 [(set_attr "type" "negnot")
9798 (set_attr "mode" "HI")])
9800 (define_insn "*neghi2_cmpz"
9802 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9804 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9805 (neg:HI (match_dup 1)))]
9806 "ix86_unary_operator_ok (NEG, HImode, operands)"
9808 [(set_attr "type" "negnot")
9809 (set_attr "mode" "HI")])
9811 (define_expand "negqi2"
9812 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9813 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9814 (clobber (reg:CC 17))])]
9815 "TARGET_QIMODE_MATH"
9816 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9818 (define_insn "*negqi2_1"
9819 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9820 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9821 (clobber (reg:CC 17))]
9822 "ix86_unary_operator_ok (NEG, QImode, operands)"
9824 [(set_attr "type" "negnot")
9825 (set_attr "mode" "QI")])
9827 (define_insn "*negqi2_cmpz"
9829 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9831 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9832 (neg:QI (match_dup 1)))]
9833 "ix86_unary_operator_ok (NEG, QImode, operands)"
9835 [(set_attr "type" "negnot")
9836 (set_attr "mode" "QI")])
9838 ;; Changing of sign for FP values is doable using integer unit too.
9840 (define_expand "negsf2"
9841 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9842 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9843 (clobber (reg:CC 17))])]
9847 /* In case operand is in memory, we will not use SSE. */
9848 if (memory_operand (operands[0], VOIDmode)
9849 && rtx_equal_p (operands[0], operands[1]))
9850 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9853 /* Using SSE is tricky, since we need bitwise negation of -0
9855 rtx reg = gen_reg_rtx (SFmode);
9856 rtx dest = operands[0];
9857 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9859 operands[1] = force_reg (SFmode, operands[1]);
9860 operands[0] = force_reg (SFmode, operands[0]);
9861 reg = force_reg (V4SFmode,
9862 gen_rtx_CONST_VECTOR (V4SFmode,
9863 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9864 CONST0_RTX (SFmode),
9865 CONST0_RTX (SFmode))));
9866 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9867 if (dest != operands[0])
9868 emit_move_insn (dest, operands[0]);
9872 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9874 (define_insn "negsf2_memory"
9875 [(set (match_operand:SF 0 "memory_operand" "=m")
9876 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9877 (clobber (reg:CC 17))]
9878 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9881 (define_insn "negsf2_ifs"
9882 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9883 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9884 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9885 (clobber (reg:CC 17))]
9887 && (reload_in_progress || reload_completed
9888 || (register_operand (operands[0], VOIDmode)
9889 && register_operand (operands[1], VOIDmode)))"
9893 [(set (match_operand:SF 0 "memory_operand" "")
9894 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9895 (use (match_operand:SF 2 "" ""))
9896 (clobber (reg:CC 17))]
9898 [(parallel [(set (match_dup 0)
9899 (neg:SF (match_dup 1)))
9900 (clobber (reg:CC 17))])])
9903 [(set (match_operand:SF 0 "register_operand" "")
9904 (neg:SF (match_operand:SF 1 "register_operand" "")))
9905 (use (match_operand:V4SF 2 "" ""))
9906 (clobber (reg:CC 17))]
9907 "reload_completed && !SSE_REG_P (operands[0])"
9908 [(parallel [(set (match_dup 0)
9909 (neg:SF (match_dup 1)))
9910 (clobber (reg:CC 17))])])
9913 [(set (match_operand:SF 0 "register_operand" "")
9914 (neg:SF (match_operand:SF 1 "register_operand" "")))
9915 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9916 (clobber (reg:CC 17))]
9917 "reload_completed && SSE_REG_P (operands[0])"
9918 [(set (subreg:TI (match_dup 0) 0)
9919 (xor:TI (match_dup 1)
9922 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9923 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9924 if (operands_match_p (operands[0], operands[2]))
9928 operands[1] = operands[2];
9934 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9935 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9937 (define_insn "*negsf2_if"
9938 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9939 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9940 (clobber (reg:CC 17))]
9941 "TARGET_80387 && !TARGET_SSE
9942 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9946 [(set (match_operand:SF 0 "fp_register_operand" "")
9947 (neg:SF (match_operand:SF 1 "register_operand" "")))
9948 (clobber (reg:CC 17))]
9949 "TARGET_80387 && reload_completed"
9951 (neg:SF (match_dup 1)))]
9955 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9956 (neg:SF (match_operand:SF 1 "register_operand" "")))
9957 (clobber (reg:CC 17))]
9958 "TARGET_80387 && reload_completed"
9959 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9960 (clobber (reg:CC 17))])]
9961 "operands[1] = gen_int_mode (0x80000000, SImode);
9962 operands[0] = gen_lowpart (SImode, operands[0]);")
9965 [(set (match_operand 0 "memory_operand" "")
9966 (neg (match_operand 1 "memory_operand" "")))
9967 (clobber (reg:CC 17))]
9968 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9969 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9970 (clobber (reg:CC 17))])]
9972 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9974 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9977 operands[0] = adjust_address (operands[0], QImode, size - 1);
9978 operands[1] = gen_int_mode (0x80, QImode);
9981 (define_expand "negdf2"
9982 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9983 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9984 (clobber (reg:CC 17))])]
9988 /* In case operand is in memory, we will not use SSE. */
9989 if (memory_operand (operands[0], VOIDmode)
9990 && rtx_equal_p (operands[0], operands[1]))
9991 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
9994 /* Using SSE is tricky, since we need bitwise negation of -0
9997 #if HOST_BITS_PER_WIDE_INT >= 64
9998 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
10000 rtx imm = immed_double_const (0, 0x80000000, DImode);
10002 rtx dest = operands[0];
10004 operands[1] = force_reg (DFmode, operands[1]);
10005 operands[0] = force_reg (DFmode, operands[0]);
10006 imm = gen_lowpart (DFmode, imm);
10007 reg = force_reg (V2DFmode,
10008 gen_rtx_CONST_VECTOR (V2DFmode,
10009 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10010 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
10011 if (dest != operands[0])
10012 emit_move_insn (dest, operands[0]);
10016 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
10018 (define_insn "negdf2_memory"
10019 [(set (match_operand:DF 0 "memory_operand" "=m")
10020 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
10021 (clobber (reg:CC 17))]
10022 "ix86_unary_operator_ok (NEG, DFmode, operands)"
10025 (define_insn "negdf2_ifs"
10026 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
10027 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10028 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10029 (clobber (reg:CC 17))]
10030 "!TARGET_64BIT && TARGET_SSE2
10031 && (reload_in_progress || reload_completed
10032 || (register_operand (operands[0], VOIDmode)
10033 && register_operand (operands[1], VOIDmode)))"
10036 (define_insn "*negdf2_ifs_rex64"
10037 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
10038 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10039 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10040 (clobber (reg:CC 17))]
10041 "TARGET_64BIT && TARGET_SSE2
10042 && (reload_in_progress || reload_completed
10043 || (register_operand (operands[0], VOIDmode)
10044 && register_operand (operands[1], VOIDmode)))"
10048 [(set (match_operand:DF 0 "memory_operand" "")
10049 (neg:DF (match_operand:DF 1 "memory_operand" "")))
10050 (use (match_operand:V2DF 2 "" ""))
10051 (clobber (reg:CC 17))]
10053 [(parallel [(set (match_dup 0)
10054 (neg:DF (match_dup 1)))
10055 (clobber (reg:CC 17))])])
10058 [(set (match_operand:DF 0 "register_operand" "")
10059 (neg:DF (match_operand:DF 1 "register_operand" "")))
10060 (use (match_operand:V2DF 2 "" ""))
10061 (clobber (reg:CC 17))]
10062 "reload_completed && !SSE_REG_P (operands[0])
10063 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
10064 [(parallel [(set (match_dup 0)
10065 (neg:DF (match_dup 1)))
10066 (clobber (reg:CC 17))])])
10069 [(set (match_operand:DF 0 "register_operand" "")
10070 (neg:DF (match_operand:DF 1 "register_operand" "")))
10071 (use (match_operand:V2DF 2 "" ""))
10072 (clobber (reg:CC 17))]
10073 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
10074 [(parallel [(set (match_dup 0)
10075 (xor:DI (match_dup 1) (match_dup 2)))
10076 (clobber (reg:CC 17))])]
10077 "operands[0] = gen_lowpart (DImode, operands[0]);
10078 operands[1] = gen_lowpart (DImode, operands[1]);
10079 operands[2] = gen_lowpart (DImode, operands[2]);")
10082 [(set (match_operand:DF 0 "register_operand" "")
10083 (neg:DF (match_operand:DF 1 "register_operand" "")))
10084 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10085 (clobber (reg:CC 17))]
10086 "reload_completed && SSE_REG_P (operands[0])"
10087 [(set (subreg:TI (match_dup 0) 0)
10088 (xor:TI (match_dup 1)
10091 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10092 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10093 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10094 /* Avoid possible reformatting on the operands. */
10095 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10096 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10097 if (operands_match_p (operands[0], operands[2]))
10101 operands[1] = operands[2];
10106 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10107 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10109 (define_insn "*negdf2_if"
10110 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10111 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10112 (clobber (reg:CC 17))]
10113 "!TARGET_64BIT && TARGET_80387
10114 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10117 ;; FIXME: We should to allow integer registers here. Problem is that
10118 ;; we need another scratch register to get constant from.
10119 ;; Forcing constant to mem if no register available in peep2 should be
10120 ;; safe even for PIC mode, because of RIP relative addressing.
10121 (define_insn "*negdf2_if_rex64"
10122 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10123 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10124 (clobber (reg:CC 17))]
10125 "TARGET_64BIT && TARGET_80387
10126 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10130 [(set (match_operand:DF 0 "fp_register_operand" "")
10131 (neg:DF (match_operand:DF 1 "register_operand" "")))
10132 (clobber (reg:CC 17))]
10133 "TARGET_80387 && reload_completed"
10134 [(set (match_dup 0)
10135 (neg:DF (match_dup 1)))]
10139 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10140 (neg:DF (match_operand:DF 1 "register_operand" "")))
10141 (clobber (reg:CC 17))]
10142 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10143 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
10144 (clobber (reg:CC 17))])]
10145 "operands[4] = gen_int_mode (0x80000000, SImode);
10146 split_di (operands+0, 1, operands+2, operands+3);")
10148 (define_expand "negxf2"
10149 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10150 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10151 (clobber (reg:CC 17))])]
10152 "!TARGET_64BIT && TARGET_80387"
10153 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
10155 (define_expand "negtf2"
10156 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10157 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10158 (clobber (reg:CC 17))])]
10160 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
10162 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10163 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10165 (define_insn "*negxf2_if"
10166 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10167 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10168 (clobber (reg:CC 17))]
10169 "!TARGET_64BIT && TARGET_80387
10170 && ix86_unary_operator_ok (NEG, XFmode, operands)"
10174 [(set (match_operand:XF 0 "fp_register_operand" "")
10175 (neg:XF (match_operand:XF 1 "register_operand" "")))
10176 (clobber (reg:CC 17))]
10177 "TARGET_80387 && reload_completed"
10178 [(set (match_dup 0)
10179 (neg:XF (match_dup 1)))]
10183 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10184 (neg:XF (match_operand:XF 1 "register_operand" "")))
10185 (clobber (reg:CC 17))]
10186 "TARGET_80387 && reload_completed"
10187 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10188 (clobber (reg:CC 17))])]
10189 "operands[1] = GEN_INT (0x8000);
10190 operands[0] = gen_rtx_REG (SImode,
10191 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10193 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10194 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10196 (define_insn "*negtf2_if"
10197 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10198 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10199 (clobber (reg:CC 17))]
10200 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
10204 [(set (match_operand:TF 0 "fp_register_operand" "")
10205 (neg:TF (match_operand:TF 1 "register_operand" "")))
10206 (clobber (reg:CC 17))]
10207 "TARGET_80387 && reload_completed"
10208 [(set (match_dup 0)
10209 (neg:TF (match_dup 1)))]
10213 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
10214 (neg:TF (match_operand:TF 1 "register_operand" "")))
10215 (clobber (reg:CC 17))]
10216 "TARGET_80387 && reload_completed"
10217 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10218 (clobber (reg:CC 17))])]
10219 "operands[1] = GEN_INT (0x8000);
10220 operands[0] = gen_rtx_REG (SImode,
10221 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10223 ;; Conditionalize these after reload. If they matches before reload, we
10224 ;; lose the clobber and ability to use integer instructions.
10226 (define_insn "*negsf2_1"
10227 [(set (match_operand:SF 0 "register_operand" "=f")
10228 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10229 "TARGET_80387 && reload_completed"
10231 [(set_attr "type" "fsgn")
10232 (set_attr "mode" "SF")
10233 (set_attr "ppro_uops" "few")])
10235 (define_insn "*negdf2_1"
10236 [(set (match_operand:DF 0 "register_operand" "=f")
10237 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10238 "TARGET_80387 && reload_completed"
10240 [(set_attr "type" "fsgn")
10241 (set_attr "mode" "DF")
10242 (set_attr "ppro_uops" "few")])
10244 (define_insn "*negextendsfdf2"
10245 [(set (match_operand:DF 0 "register_operand" "=f")
10246 (neg:DF (float_extend:DF
10247 (match_operand:SF 1 "register_operand" "0"))))]
10250 [(set_attr "type" "fsgn")
10251 (set_attr "mode" "DF")
10252 (set_attr "ppro_uops" "few")])
10254 (define_insn "*negxf2_1"
10255 [(set (match_operand:XF 0 "register_operand" "=f")
10256 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10257 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10259 [(set_attr "type" "fsgn")
10260 (set_attr "mode" "XF")
10261 (set_attr "ppro_uops" "few")])
10263 (define_insn "*negextenddfxf2"
10264 [(set (match_operand:XF 0 "register_operand" "=f")
10265 (neg:XF (float_extend:XF
10266 (match_operand:DF 1 "register_operand" "0"))))]
10267 "!TARGET_64BIT && TARGET_80387"
10269 [(set_attr "type" "fsgn")
10270 (set_attr "mode" "XF")
10271 (set_attr "ppro_uops" "few")])
10273 (define_insn "*negextendsfxf2"
10274 [(set (match_operand:XF 0 "register_operand" "=f")
10275 (neg:XF (float_extend:XF
10276 (match_operand:SF 1 "register_operand" "0"))))]
10277 "!TARGET_64BIT && TARGET_80387"
10279 [(set_attr "type" "fsgn")
10280 (set_attr "mode" "XF")
10281 (set_attr "ppro_uops" "few")])
10283 (define_insn "*negtf2_1"
10284 [(set (match_operand:TF 0 "register_operand" "=f")
10285 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
10286 "TARGET_80387 && reload_completed"
10288 [(set_attr "type" "fsgn")
10289 (set_attr "mode" "XF")
10290 (set_attr "ppro_uops" "few")])
10292 (define_insn "*negextenddftf2"
10293 [(set (match_operand:TF 0 "register_operand" "=f")
10294 (neg:TF (float_extend:TF
10295 (match_operand:DF 1 "register_operand" "0"))))]
10298 [(set_attr "type" "fsgn")
10299 (set_attr "mode" "XF")
10300 (set_attr "ppro_uops" "few")])
10302 (define_insn "*negextendsftf2"
10303 [(set (match_operand:TF 0 "register_operand" "=f")
10304 (neg:TF (float_extend:TF
10305 (match_operand:SF 1 "register_operand" "0"))))]
10308 [(set_attr "type" "fsgn")
10309 (set_attr "mode" "XF")
10310 (set_attr "ppro_uops" "few")])
10312 ;; Absolute value instructions
10314 (define_expand "abssf2"
10315 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10316 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10317 (clobber (reg:CC 17))])]
10321 /* In case operand is in memory, we will not use SSE. */
10322 if (memory_operand (operands[0], VOIDmode)
10323 && rtx_equal_p (operands[0], operands[1]))
10324 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10327 /* Using SSE is tricky, since we need bitwise negation of -0
10329 rtx reg = gen_reg_rtx (V4SFmode);
10330 rtx dest = operands[0];
10333 operands[1] = force_reg (SFmode, operands[1]);
10334 operands[0] = force_reg (SFmode, operands[0]);
10335 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10336 reg = force_reg (V4SFmode,
10337 gen_rtx_CONST_VECTOR (V4SFmode,
10338 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10339 CONST0_RTX (SFmode),
10340 CONST0_RTX (SFmode))));
10341 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10342 if (dest != operands[0])
10343 emit_move_insn (dest, operands[0]);
10347 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10349 (define_insn "abssf2_memory"
10350 [(set (match_operand:SF 0 "memory_operand" "=m")
10351 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10352 (clobber (reg:CC 17))]
10353 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10356 (define_insn "abssf2_ifs"
10357 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10358 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10359 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10360 (clobber (reg:CC 17))]
10362 && (reload_in_progress || reload_completed
10363 || (register_operand (operands[0], VOIDmode)
10364 && register_operand (operands[1], VOIDmode)))"
10368 [(set (match_operand:SF 0 "memory_operand" "")
10369 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10370 (use (match_operand:V4SF 2 "" ""))
10371 (clobber (reg:CC 17))]
10373 [(parallel [(set (match_dup 0)
10374 (abs:SF (match_dup 1)))
10375 (clobber (reg:CC 17))])])
10378 [(set (match_operand:SF 0 "register_operand" "")
10379 (abs:SF (match_operand:SF 1 "register_operand" "")))
10380 (use (match_operand:V4SF 2 "" ""))
10381 (clobber (reg:CC 17))]
10382 "reload_completed && !SSE_REG_P (operands[0])"
10383 [(parallel [(set (match_dup 0)
10384 (abs:SF (match_dup 1)))
10385 (clobber (reg:CC 17))])])
10388 [(set (match_operand:SF 0 "register_operand" "")
10389 (abs:SF (match_operand:SF 1 "register_operand" "")))
10390 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10391 (clobber (reg:CC 17))]
10392 "reload_completed && SSE_REG_P (operands[0])"
10393 [(set (subreg:TI (match_dup 0) 0)
10394 (and:TI (match_dup 1)
10397 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10398 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10399 if (operands_match_p (operands[0], operands[2]))
10403 operands[1] = operands[2];
10408 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10409 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10411 (define_insn "*abssf2_if"
10412 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10413 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10414 (clobber (reg:CC 17))]
10415 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10419 [(set (match_operand:SF 0 "fp_register_operand" "")
10420 (abs:SF (match_operand:SF 1 "register_operand" "")))
10421 (clobber (reg:CC 17))]
10422 "TARGET_80387 && reload_completed"
10423 [(set (match_dup 0)
10424 (abs:SF (match_dup 1)))]
10428 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10429 (abs:SF (match_operand:SF 1 "register_operand" "")))
10430 (clobber (reg:CC 17))]
10431 "TARGET_80387 && reload_completed"
10432 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10433 (clobber (reg:CC 17))])]
10434 "operands[1] = gen_int_mode (~0x80000000, SImode);
10435 operands[0] = gen_lowpart (SImode, operands[0]);")
10438 [(set (match_operand 0 "memory_operand" "")
10439 (abs (match_operand 1 "memory_operand" "")))
10440 (clobber (reg:CC 17))]
10441 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10442 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10443 (clobber (reg:CC 17))])]
10445 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10447 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
10450 operands[0] = adjust_address (operands[0], QImode, size - 1);
10451 operands[1] = gen_int_mode (~0x80, QImode);
10454 (define_expand "absdf2"
10455 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10456 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10457 (clobber (reg:CC 17))])]
10461 /* In case operand is in memory, we will not use SSE. */
10462 if (memory_operand (operands[0], VOIDmode)
10463 && rtx_equal_p (operands[0], operands[1]))
10464 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10467 /* Using SSE is tricky, since we need bitwise negation of -0
10469 rtx reg = gen_reg_rtx (V2DFmode);
10470 #if HOST_BITS_PER_WIDE_INT >= 64
10471 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10473 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10475 rtx dest = operands[0];
10477 operands[1] = force_reg (DFmode, operands[1]);
10478 operands[0] = force_reg (DFmode, operands[0]);
10480 /* Produce LONG_DOUBLE with the proper immediate argument. */
10481 imm = gen_lowpart (DFmode, imm);
10482 reg = force_reg (V2DFmode,
10483 gen_rtx_CONST_VECTOR (V2DFmode,
10484 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10485 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10486 if (dest != operands[0])
10487 emit_move_insn (dest, operands[0]);
10491 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10493 (define_insn "absdf2_memory"
10494 [(set (match_operand:DF 0 "memory_operand" "=m")
10495 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10496 (clobber (reg:CC 17))]
10497 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10500 (define_insn "absdf2_ifs"
10501 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10502 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10503 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10504 (clobber (reg:CC 17))]
10505 "!TARGET_64BIT && TARGET_SSE2
10506 && (reload_in_progress || reload_completed
10507 || (register_operand (operands[0], VOIDmode)
10508 && register_operand (operands[1], VOIDmode)))"
10511 (define_insn "*absdf2_ifs_rex64"
10512 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10513 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10514 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10515 (clobber (reg:CC 17))]
10516 "TARGET_64BIT && TARGET_SSE2
10517 && (reload_in_progress || reload_completed
10518 || (register_operand (operands[0], VOIDmode)
10519 && register_operand (operands[1], VOIDmode)))"
10523 [(set (match_operand:DF 0 "memory_operand" "")
10524 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10525 (use (match_operand:V2DF 2 "" ""))
10526 (clobber (reg:CC 17))]
10528 [(parallel [(set (match_dup 0)
10529 (abs:DF (match_dup 1)))
10530 (clobber (reg:CC 17))])])
10533 [(set (match_operand:DF 0 "register_operand" "")
10534 (abs:DF (match_operand:DF 1 "register_operand" "")))
10535 (use (match_operand:V2DF 2 "" ""))
10536 (clobber (reg:CC 17))]
10537 "reload_completed && !SSE_REG_P (operands[0])"
10538 [(parallel [(set (match_dup 0)
10539 (abs:DF (match_dup 1)))
10540 (clobber (reg:CC 17))])])
10543 [(set (match_operand:DF 0 "register_operand" "")
10544 (abs:DF (match_operand:DF 1 "register_operand" "")))
10545 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10546 (clobber (reg:CC 17))]
10547 "reload_completed && SSE_REG_P (operands[0])"
10548 [(set (subreg:TI (match_dup 0) 0)
10549 (and:TI (match_dup 1)
10552 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10553 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10554 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10555 /* Avoid possible reformatting on the operands. */
10556 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10557 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10558 if (operands_match_p (operands[0], operands[2]))
10562 operands[1] = operands[2];
10568 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10569 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10571 (define_insn "*absdf2_if"
10572 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10573 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10574 (clobber (reg:CC 17))]
10575 "!TARGET_64BIT && TARGET_80387
10576 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10579 ;; FIXME: We should to allow integer registers here. Problem is that
10580 ;; we need another scratch register to get constant from.
10581 ;; Forcing constant to mem if no register available in peep2 should be
10582 ;; safe even for PIC mode, because of RIP relative addressing.
10583 (define_insn "*absdf2_if_rex64"
10584 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10585 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10586 (clobber (reg:CC 17))]
10587 "TARGET_64BIT && TARGET_80387
10588 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10592 [(set (match_operand:DF 0 "fp_register_operand" "")
10593 (abs:DF (match_operand:DF 1 "register_operand" "")))
10594 (clobber (reg:CC 17))]
10595 "TARGET_80387 && reload_completed"
10596 [(set (match_dup 0)
10597 (abs:DF (match_dup 1)))]
10601 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10602 (abs:DF (match_operand:DF 1 "register_operand" "")))
10603 (clobber (reg:CC 17))]
10604 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10605 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10606 (clobber (reg:CC 17))])]
10607 "operands[4] = gen_int_mode (~0x80000000, SImode);
10608 split_di (operands+0, 1, operands+2, operands+3);")
10610 (define_expand "absxf2"
10611 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10612 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10613 (clobber (reg:CC 17))])]
10614 "!TARGET_64BIT && TARGET_80387"
10615 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10617 (define_expand "abstf2"
10618 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10619 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10620 (clobber (reg:CC 17))])]
10622 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10624 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10625 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10627 (define_insn "*absxf2_if"
10628 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10629 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10630 (clobber (reg:CC 17))]
10631 "!TARGET_64BIT && TARGET_80387
10632 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10636 [(set (match_operand:XF 0 "fp_register_operand" "")
10637 (abs:XF (match_operand:XF 1 "register_operand" "")))
10638 (clobber (reg:CC 17))]
10639 "TARGET_80387 && reload_completed"
10640 [(set (match_dup 0)
10641 (abs:XF (match_dup 1)))]
10645 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10646 (abs:XF (match_operand:XF 1 "register_operand" "")))
10647 (clobber (reg:CC 17))]
10648 "TARGET_80387 && reload_completed"
10649 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10650 (clobber (reg:CC 17))])]
10651 "operands[1] = GEN_INT (~0x8000);
10652 operands[0] = gen_rtx_REG (SImode,
10653 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10655 (define_insn "*abstf2_if"
10656 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10657 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10658 (clobber (reg:CC 17))]
10659 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10663 [(set (match_operand:TF 0 "fp_register_operand" "")
10664 (abs:TF (match_operand:TF 1 "register_operand" "")))
10665 (clobber (reg:CC 17))]
10666 "TARGET_80387 && reload_completed"
10667 [(set (match_dup 0)
10668 (abs:TF (match_dup 1)))]
10672 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10673 (abs:TF (match_operand:TF 1 "register_operand" "")))
10674 (clobber (reg:CC 17))]
10675 "TARGET_80387 && reload_completed"
10676 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10677 (clobber (reg:CC 17))])]
10678 "operands[1] = GEN_INT (~0x8000);
10679 operands[0] = gen_rtx_REG (SImode,
10680 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10682 (define_insn "*abssf2_1"
10683 [(set (match_operand:SF 0 "register_operand" "=f")
10684 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10685 "TARGET_80387 && reload_completed"
10687 [(set_attr "type" "fsgn")
10688 (set_attr "mode" "SF")])
10690 (define_insn "*absdf2_1"
10691 [(set (match_operand:DF 0 "register_operand" "=f")
10692 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10693 "TARGET_80387 && reload_completed"
10695 [(set_attr "type" "fsgn")
10696 (set_attr "mode" "DF")])
10698 (define_insn "*absextendsfdf2"
10699 [(set (match_operand:DF 0 "register_operand" "=f")
10700 (abs:DF (float_extend:DF
10701 (match_operand:SF 1 "register_operand" "0"))))]
10704 [(set_attr "type" "fsgn")
10705 (set_attr "mode" "DF")])
10707 (define_insn "*absxf2_1"
10708 [(set (match_operand:XF 0 "register_operand" "=f")
10709 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10710 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10712 [(set_attr "type" "fsgn")
10713 (set_attr "mode" "DF")])
10715 (define_insn "*absextenddfxf2"
10716 [(set (match_operand:XF 0 "register_operand" "=f")
10717 (abs:XF (float_extend:XF
10718 (match_operand:DF 1 "register_operand" "0"))))]
10719 "!TARGET_64BIT && TARGET_80387"
10721 [(set_attr "type" "fsgn")
10722 (set_attr "mode" "XF")])
10724 (define_insn "*absextendsfxf2"
10725 [(set (match_operand:XF 0 "register_operand" "=f")
10726 (abs:XF (float_extend:XF
10727 (match_operand:SF 1 "register_operand" "0"))))]
10728 "!TARGET_64BIT && TARGET_80387"
10730 [(set_attr "type" "fsgn")
10731 (set_attr "mode" "XF")])
10733 (define_insn "*abstf2_1"
10734 [(set (match_operand:TF 0 "register_operand" "=f")
10735 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10736 "TARGET_80387 && reload_completed"
10738 [(set_attr "type" "fsgn")
10739 (set_attr "mode" "DF")])
10741 (define_insn "*absextenddftf2"
10742 [(set (match_operand:TF 0 "register_operand" "=f")
10743 (abs:TF (float_extend:TF
10744 (match_operand:DF 1 "register_operand" "0"))))]
10747 [(set_attr "type" "fsgn")
10748 (set_attr "mode" "XF")])
10750 (define_insn "*absextendsftf2"
10751 [(set (match_operand:TF 0 "register_operand" "=f")
10752 (abs:TF (float_extend:TF
10753 (match_operand:SF 1 "register_operand" "0"))))]
10756 [(set_attr "type" "fsgn")
10757 (set_attr "mode" "XF")])
10759 ;; One complement instructions
10761 (define_expand "one_cmpldi2"
10762 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10763 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10765 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10767 (define_insn "*one_cmpldi2_1_rex64"
10768 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10769 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10770 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10772 [(set_attr "type" "negnot")
10773 (set_attr "mode" "DI")])
10775 (define_insn "*one_cmpldi2_2_rex64"
10777 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10779 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10780 (not:DI (match_dup 1)))]
10781 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10782 && ix86_unary_operator_ok (NOT, DImode, operands)"
10784 [(set_attr "type" "alu1")
10785 (set_attr "mode" "DI")])
10789 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10791 (set (match_operand:DI 0 "nonimmediate_operand" "")
10792 (not:DI (match_dup 1)))]
10793 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10794 [(parallel [(set (reg:CCNO 17)
10795 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10798 (xor:DI (match_dup 1) (const_int -1)))])]
10801 (define_expand "one_cmplsi2"
10802 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10803 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10805 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10807 (define_insn "*one_cmplsi2_1"
10808 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10809 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10810 "ix86_unary_operator_ok (NOT, SImode, operands)"
10812 [(set_attr "type" "negnot")
10813 (set_attr "mode" "SI")])
10815 ;; ??? Currently never generated - xor is used instead.
10816 (define_insn "*one_cmplsi2_1_zext"
10817 [(set (match_operand:DI 0 "register_operand" "=r")
10818 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10819 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10821 [(set_attr "type" "negnot")
10822 (set_attr "mode" "SI")])
10824 (define_insn "*one_cmplsi2_2"
10826 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10828 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10829 (not:SI (match_dup 1)))]
10830 "ix86_match_ccmode (insn, CCNOmode)
10831 && ix86_unary_operator_ok (NOT, SImode, operands)"
10833 [(set_attr "type" "alu1")
10834 (set_attr "mode" "SI")])
10838 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10840 (set (match_operand:SI 0 "nonimmediate_operand" "")
10841 (not:SI (match_dup 1)))]
10842 "ix86_match_ccmode (insn, CCNOmode)"
10843 [(parallel [(set (reg:CCNO 17)
10844 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10847 (xor:SI (match_dup 1) (const_int -1)))])]
10850 ;; ??? Currently never generated - xor is used instead.
10851 (define_insn "*one_cmplsi2_2_zext"
10853 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10855 (set (match_operand:DI 0 "register_operand" "=r")
10856 (zero_extend:DI (not:SI (match_dup 1))))]
10857 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10858 && ix86_unary_operator_ok (NOT, SImode, operands)"
10860 [(set_attr "type" "alu1")
10861 (set_attr "mode" "SI")])
10865 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10867 (set (match_operand:DI 0 "register_operand" "")
10868 (zero_extend:DI (not:SI (match_dup 1))))]
10869 "ix86_match_ccmode (insn, CCNOmode)"
10870 [(parallel [(set (reg:CCNO 17)
10871 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10874 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10877 (define_expand "one_cmplhi2"
10878 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10879 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10880 "TARGET_HIMODE_MATH"
10881 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10883 (define_insn "*one_cmplhi2_1"
10884 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10885 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10886 "ix86_unary_operator_ok (NOT, HImode, operands)"
10888 [(set_attr "type" "negnot")
10889 (set_attr "mode" "HI")])
10891 (define_insn "*one_cmplhi2_2"
10893 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10895 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10896 (not:HI (match_dup 1)))]
10897 "ix86_match_ccmode (insn, CCNOmode)
10898 && ix86_unary_operator_ok (NEG, HImode, operands)"
10900 [(set_attr "type" "alu1")
10901 (set_attr "mode" "HI")])
10905 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10907 (set (match_operand:HI 0 "nonimmediate_operand" "")
10908 (not:HI (match_dup 1)))]
10909 "ix86_match_ccmode (insn, CCNOmode)"
10910 [(parallel [(set (reg:CCNO 17)
10911 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10914 (xor:HI (match_dup 1) (const_int -1)))])]
10917 ;; %%% Potential partial reg stall on alternative 1. What to do?
10918 (define_expand "one_cmplqi2"
10919 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10920 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10921 "TARGET_QIMODE_MATH"
10922 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10924 (define_insn "*one_cmplqi2_1"
10925 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10926 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10927 "ix86_unary_operator_ok (NOT, QImode, operands)"
10931 [(set_attr "type" "negnot")
10932 (set_attr "mode" "QI,SI")])
10934 (define_insn "*one_cmplqi2_2"
10936 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10938 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10939 (not:QI (match_dup 1)))]
10940 "ix86_match_ccmode (insn, CCNOmode)
10941 && ix86_unary_operator_ok (NOT, QImode, operands)"
10943 [(set_attr "type" "alu1")
10944 (set_attr "mode" "QI")])
10948 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10950 (set (match_operand:QI 0 "nonimmediate_operand" "")
10951 (not:QI (match_dup 1)))]
10952 "ix86_match_ccmode (insn, CCNOmode)"
10953 [(parallel [(set (reg:CCNO 17)
10954 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10957 (xor:QI (match_dup 1) (const_int -1)))])]
10960 ;; Arithmetic shift instructions
10962 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10963 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10964 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10965 ;; from the assembler input.
10967 ;; This instruction shifts the target reg/mem as usual, but instead of
10968 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10969 ;; is a left shift double, bits are taken from the high order bits of
10970 ;; reg, else if the insn is a shift right double, bits are taken from the
10971 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10972 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10974 ;; Since sh[lr]d does not change the `reg' operand, that is done
10975 ;; separately, making all shifts emit pairs of shift double and normal
10976 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10977 ;; support a 63 bit shift, each shift where the count is in a reg expands
10978 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10980 ;; If the shift count is a constant, we need never emit more than one
10981 ;; shift pair, instead using moves and sign extension for counts greater
10984 (define_expand "ashldi3"
10985 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10986 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10987 (match_operand:QI 2 "nonmemory_operand" "")))
10988 (clobber (reg:CC 17))])]
10991 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
10993 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
10996 ix86_expand_binary_operator (ASHIFT, DImode, operands);
11000 (define_insn "*ashldi3_1_rex64"
11001 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
11002 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
11003 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
11004 (clobber (reg:CC 17))]
11005 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11007 switch (get_attr_type (insn))
11010 if (operands[2] != const1_rtx)
11012 if (!rtx_equal_p (operands[0], operands[1]))
11014 return "add{q}\t{%0, %0|%0, %0}";
11017 if (GET_CODE (operands[2]) != CONST_INT
11018 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
11020 operands[1] = gen_rtx_MULT (DImode, operands[1],
11021 GEN_INT (1 << INTVAL (operands[2])));
11022 return "lea{q}\t{%a1, %0|%0, %a1}";
11025 if (REG_P (operands[2]))
11026 return "sal{q}\t{%b2, %0|%0, %b2}";
11027 else if (GET_CODE (operands[2]) == CONST_INT
11028 && INTVAL (operands[2]) == 1
11029 && (TARGET_SHIFT1 || optimize_size))
11030 return "sal{q}\t%0";
11032 return "sal{q}\t{%2, %0|%0, %2}";
11035 [(set (attr "type")
11036 (cond [(eq_attr "alternative" "1")
11037 (const_string "lea")
11038 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11040 (match_operand 0 "register_operand" ""))
11041 (match_operand 2 "const1_operand" ""))
11042 (const_string "alu")
11044 (const_string "ishift")))
11045 (set_attr "mode" "DI")])
11047 ;; Convert lea to the lea pattern to avoid flags dependency.
11049 [(set (match_operand:DI 0 "register_operand" "")
11050 (ashift:DI (match_operand:DI 1 "register_operand" "")
11051 (match_operand:QI 2 "immediate_operand" "")))
11052 (clobber (reg:CC 17))]
11053 "TARGET_64BIT && reload_completed
11054 && true_regnum (operands[0]) != true_regnum (operands[1])"
11055 [(set (match_dup 0)
11056 (mult:DI (match_dup 1)
11058 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
11060 ;; This pattern can't accept a variable shift count, since shifts by
11061 ;; zero don't affect the flags. We assume that shifts by constant
11062 ;; zero are optimized away.
11063 (define_insn "*ashldi3_cmp_rex64"
11066 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11067 (match_operand:QI 2 "immediate_operand" "e"))
11069 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11070 (ashift:DI (match_dup 1) (match_dup 2)))]
11071 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11072 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11074 switch (get_attr_type (insn))
11077 if (operands[2] != const1_rtx)
11079 return "add{q}\t{%0, %0|%0, %0}";
11082 if (REG_P (operands[2]))
11083 return "sal{q}\t{%b2, %0|%0, %b2}";
11084 else if (GET_CODE (operands[2]) == CONST_INT
11085 && INTVAL (operands[2]) == 1
11086 && (TARGET_SHIFT1 || optimize_size))
11087 return "sal{q}\t%0";
11089 return "sal{q}\t{%2, %0|%0, %2}";
11092 [(set (attr "type")
11093 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11095 (match_operand 0 "register_operand" ""))
11096 (match_operand 2 "const1_operand" ""))
11097 (const_string "alu")
11099 (const_string "ishift")))
11100 (set_attr "mode" "DI")])
11102 (define_insn "ashldi3_1"
11103 [(set (match_operand:DI 0 "register_operand" "=r")
11104 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11105 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11106 (clobber (match_scratch:SI 3 "=&r"))
11107 (clobber (reg:CC 17))]
11108 "!TARGET_64BIT && TARGET_CMOVE"
11110 [(set_attr "type" "multi")])
11112 (define_insn "*ashldi3_2"
11113 [(set (match_operand:DI 0 "register_operand" "=r")
11114 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11115 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11116 (clobber (reg:CC 17))]
11119 [(set_attr "type" "multi")])
11122 [(set (match_operand:DI 0 "register_operand" "")
11123 (ashift:DI (match_operand:DI 1 "register_operand" "")
11124 (match_operand:QI 2 "nonmemory_operand" "")))
11125 (clobber (match_scratch:SI 3 ""))
11126 (clobber (reg:CC 17))]
11127 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11129 "ix86_split_ashldi (operands, operands[3]); DONE;")
11132 [(set (match_operand:DI 0 "register_operand" "")
11133 (ashift:DI (match_operand:DI 1 "register_operand" "")
11134 (match_operand:QI 2 "nonmemory_operand" "")))
11135 (clobber (reg:CC 17))]
11136 "!TARGET_64BIT && reload_completed"
11138 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
11140 (define_insn "x86_shld_1"
11141 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11142 (ior:SI (ashift:SI (match_dup 0)
11143 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11144 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
11145 (minus:QI (const_int 32) (match_dup 2)))))
11146 (clobber (reg:CC 17))]
11149 shld{l}\t{%2, %1, %0|%0, %1, %2}
11150 shld{l}\t{%s2%1, %0|%0, %1, %2}"
11151 [(set_attr "type" "ishift")
11152 (set_attr "prefix_0f" "1")
11153 (set_attr "mode" "SI")
11154 (set_attr "pent_pair" "np")
11155 (set_attr "athlon_decode" "vector")
11156 (set_attr "ppro_uops" "few")])
11158 (define_expand "x86_shift_adj_1"
11160 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11163 (set (match_operand:SI 0 "register_operand" "")
11164 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11165 (match_operand:SI 1 "register_operand" "")
11168 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11169 (match_operand:SI 3 "register_operand" "r")
11174 (define_expand "x86_shift_adj_2"
11175 [(use (match_operand:SI 0 "register_operand" ""))
11176 (use (match_operand:SI 1 "register_operand" ""))
11177 (use (match_operand:QI 2 "register_operand" ""))]
11180 rtx label = gen_label_rtx ();
11183 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11185 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11186 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11187 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11188 gen_rtx_LABEL_REF (VOIDmode, label),
11190 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11191 JUMP_LABEL (tmp) = label;
11193 emit_move_insn (operands[0], operands[1]);
11194 emit_move_insn (operands[1], const0_rtx);
11196 emit_label (label);
11197 LABEL_NUSES (label) = 1;
11202 (define_expand "ashlsi3"
11203 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11204 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
11205 (match_operand:QI 2 "nonmemory_operand" "")))
11206 (clobber (reg:CC 17))]
11208 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
11210 (define_insn "*ashlsi3_1"
11211 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
11212 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
11213 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11214 (clobber (reg:CC 17))]
11215 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11217 switch (get_attr_type (insn))
11220 if (operands[2] != const1_rtx)
11222 if (!rtx_equal_p (operands[0], operands[1]))
11224 return "add{l}\t{%0, %0|%0, %0}";
11230 if (REG_P (operands[2]))
11231 return "sal{l}\t{%b2, %0|%0, %b2}";
11232 else if (GET_CODE (operands[2]) == CONST_INT
11233 && INTVAL (operands[2]) == 1
11234 && (TARGET_SHIFT1 || optimize_size))
11235 return "sal{l}\t%0";
11237 return "sal{l}\t{%2, %0|%0, %2}";
11240 [(set (attr "type")
11241 (cond [(eq_attr "alternative" "1")
11242 (const_string "lea")
11243 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11245 (match_operand 0 "register_operand" ""))
11246 (match_operand 2 "const1_operand" ""))
11247 (const_string "alu")
11249 (const_string "ishift")))
11250 (set_attr "mode" "SI")])
11252 ;; Convert lea to the lea pattern to avoid flags dependency.
11254 [(set (match_operand 0 "register_operand" "")
11255 (ashift (match_operand 1 "index_register_operand" "")
11256 (match_operand:QI 2 "const_int_operand" "")))
11257 (clobber (reg:CC 17))]
11259 && true_regnum (operands[0]) != true_regnum (operands[1])"
11263 operands[0] = gen_lowpart (SImode, operands[0]);
11264 operands[1] = gen_lowpart (Pmode, operands[1]);
11265 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11266 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11267 if (Pmode != SImode)
11268 pat = gen_rtx_SUBREG (SImode, pat, 0);
11269 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11273 ;; Rare case of shifting RSP is handled by generating move and shift
11275 [(set (match_operand 0 "register_operand" "")
11276 (ashift (match_operand 1 "register_operand" "")
11277 (match_operand:QI 2 "const_int_operand" "")))
11278 (clobber (reg:CC 17))]
11280 && true_regnum (operands[0]) != true_regnum (operands[1])"
11284 emit_move_insn (operands[1], operands[0]);
11285 pat = gen_rtx_SET (VOIDmode, operands[0],
11286 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11287 operands[0], operands[2]));
11288 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11289 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11293 (define_insn "*ashlsi3_1_zext"
11294 [(set (match_operand:DI 0 "register_operand" "=r,r")
11295 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
11296 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11297 (clobber (reg:CC 17))]
11298 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11300 switch (get_attr_type (insn))
11303 if (operands[2] != const1_rtx)
11305 return "add{l}\t{%k0, %k0|%k0, %k0}";
11311 if (REG_P (operands[2]))
11312 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11313 else if (GET_CODE (operands[2]) == CONST_INT
11314 && INTVAL (operands[2]) == 1
11315 && (TARGET_SHIFT1 || optimize_size))
11316 return "sal{l}\t%k0";
11318 return "sal{l}\t{%2, %k0|%k0, %2}";
11321 [(set (attr "type")
11322 (cond [(eq_attr "alternative" "1")
11323 (const_string "lea")
11324 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11326 (match_operand 2 "const1_operand" ""))
11327 (const_string "alu")
11329 (const_string "ishift")))
11330 (set_attr "mode" "SI")])
11332 ;; Convert lea to the lea pattern to avoid flags dependency.
11334 [(set (match_operand:DI 0 "register_operand" "")
11335 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11336 (match_operand:QI 2 "const_int_operand" ""))))
11337 (clobber (reg:CC 17))]
11338 "TARGET_64BIT && reload_completed
11339 && true_regnum (operands[0]) != true_regnum (operands[1])"
11340 [(set (match_dup 0) (zero_extend:DI
11341 (subreg:SI (mult:SI (match_dup 1)
11342 (match_dup 2)) 0)))]
11344 operands[1] = gen_lowpart (Pmode, operands[1]);
11345 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11348 ;; This pattern can't accept a variable shift count, since shifts by
11349 ;; zero don't affect the flags. We assume that shifts by constant
11350 ;; zero are optimized away.
11351 (define_insn "*ashlsi3_cmp"
11354 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11355 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11357 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11358 (ashift:SI (match_dup 1) (match_dup 2)))]
11359 "ix86_match_ccmode (insn, CCGOCmode)
11360 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11362 switch (get_attr_type (insn))
11365 if (operands[2] != const1_rtx)
11367 return "add{l}\t{%0, %0|%0, %0}";
11370 if (REG_P (operands[2]))
11371 return "sal{l}\t{%b2, %0|%0, %b2}";
11372 else if (GET_CODE (operands[2]) == CONST_INT
11373 && INTVAL (operands[2]) == 1
11374 && (TARGET_SHIFT1 || optimize_size))
11375 return "sal{l}\t%0";
11377 return "sal{l}\t{%2, %0|%0, %2}";
11380 [(set (attr "type")
11381 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11383 (match_operand 0 "register_operand" ""))
11384 (match_operand 2 "const1_operand" ""))
11385 (const_string "alu")
11387 (const_string "ishift")))
11388 (set_attr "mode" "SI")])
11390 (define_insn "*ashlsi3_cmp_zext"
11393 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11394 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11396 (set (match_operand:DI 0 "register_operand" "=r")
11397 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11398 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11399 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11401 switch (get_attr_type (insn))
11404 if (operands[2] != const1_rtx)
11406 return "add{l}\t{%k0, %k0|%k0, %k0}";
11409 if (REG_P (operands[2]))
11410 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11411 else if (GET_CODE (operands[2]) == CONST_INT
11412 && INTVAL (operands[2]) == 1
11413 && (TARGET_SHIFT1 || optimize_size))
11414 return "sal{l}\t%k0";
11416 return "sal{l}\t{%2, %k0|%k0, %2}";
11419 [(set (attr "type")
11420 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11422 (match_operand 2 "const1_operand" ""))
11423 (const_string "alu")
11425 (const_string "ishift")))
11426 (set_attr "mode" "SI")])
11428 (define_expand "ashlhi3"
11429 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11430 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11431 (match_operand:QI 2 "nonmemory_operand" "")))
11432 (clobber (reg:CC 17))]
11433 "TARGET_HIMODE_MATH"
11434 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11436 (define_insn "*ashlhi3_1_lea"
11437 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11438 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11439 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11440 (clobber (reg:CC 17))]
11441 "!TARGET_PARTIAL_REG_STALL
11442 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11444 switch (get_attr_type (insn))
11449 if (operands[2] != const1_rtx)
11451 return "add{w}\t{%0, %0|%0, %0}";
11454 if (REG_P (operands[2]))
11455 return "sal{w}\t{%b2, %0|%0, %b2}";
11456 else if (GET_CODE (operands[2]) == CONST_INT
11457 && INTVAL (operands[2]) == 1
11458 && (TARGET_SHIFT1 || optimize_size))
11459 return "sal{w}\t%0";
11461 return "sal{w}\t{%2, %0|%0, %2}";
11464 [(set (attr "type")
11465 (cond [(eq_attr "alternative" "1")
11466 (const_string "lea")
11467 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11469 (match_operand 0 "register_operand" ""))
11470 (match_operand 2 "const1_operand" ""))
11471 (const_string "alu")
11473 (const_string "ishift")))
11474 (set_attr "mode" "HI,SI")])
11476 (define_insn "*ashlhi3_1"
11477 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11478 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11479 (match_operand:QI 2 "nonmemory_operand" "cI")))
11480 (clobber (reg:CC 17))]
11481 "TARGET_PARTIAL_REG_STALL
11482 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11484 switch (get_attr_type (insn))
11487 if (operands[2] != const1_rtx)
11489 return "add{w}\t{%0, %0|%0, %0}";
11492 if (REG_P (operands[2]))
11493 return "sal{w}\t{%b2, %0|%0, %b2}";
11494 else if (GET_CODE (operands[2]) == CONST_INT
11495 && INTVAL (operands[2]) == 1
11496 && (TARGET_SHIFT1 || optimize_size))
11497 return "sal{w}\t%0";
11499 return "sal{w}\t{%2, %0|%0, %2}";
11502 [(set (attr "type")
11503 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11505 (match_operand 0 "register_operand" ""))
11506 (match_operand 2 "const1_operand" ""))
11507 (const_string "alu")
11509 (const_string "ishift")))
11510 (set_attr "mode" "HI")])
11512 ;; This pattern can't accept a variable shift count, since shifts by
11513 ;; zero don't affect the flags. We assume that shifts by constant
11514 ;; zero are optimized away.
11515 (define_insn "*ashlhi3_cmp"
11518 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11519 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11521 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11522 (ashift:HI (match_dup 1) (match_dup 2)))]
11523 "ix86_match_ccmode (insn, CCGOCmode)
11524 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11526 switch (get_attr_type (insn))
11529 if (operands[2] != const1_rtx)
11531 return "add{w}\t{%0, %0|%0, %0}";
11534 if (REG_P (operands[2]))
11535 return "sal{w}\t{%b2, %0|%0, %b2}";
11536 else if (GET_CODE (operands[2]) == CONST_INT
11537 && INTVAL (operands[2]) == 1
11538 && (TARGET_SHIFT1 || optimize_size))
11539 return "sal{w}\t%0";
11541 return "sal{w}\t{%2, %0|%0, %2}";
11544 [(set (attr "type")
11545 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11547 (match_operand 0 "register_operand" ""))
11548 (match_operand 2 "const1_operand" ""))
11549 (const_string "alu")
11551 (const_string "ishift")))
11552 (set_attr "mode" "HI")])
11554 (define_expand "ashlqi3"
11555 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11556 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11557 (match_operand:QI 2 "nonmemory_operand" "")))
11558 (clobber (reg:CC 17))]
11559 "TARGET_QIMODE_MATH"
11560 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11562 ;; %%% Potential partial reg stall on alternative 2. What to do?
11564 (define_insn "*ashlqi3_1_lea"
11565 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11566 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11567 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11568 (clobber (reg:CC 17))]
11569 "!TARGET_PARTIAL_REG_STALL
11570 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11572 switch (get_attr_type (insn))
11577 if (operands[2] != const1_rtx)
11579 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11580 return "add{l}\t{%k0, %k0|%k0, %k0}";
11582 return "add{b}\t{%0, %0|%0, %0}";
11585 if (REG_P (operands[2]))
11587 if (get_attr_mode (insn) == MODE_SI)
11588 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11590 return "sal{b}\t{%b2, %0|%0, %b2}";
11592 else if (GET_CODE (operands[2]) == CONST_INT
11593 && INTVAL (operands[2]) == 1
11594 && (TARGET_SHIFT1 || optimize_size))
11596 if (get_attr_mode (insn) == MODE_SI)
11597 return "sal{l}\t%0";
11599 return "sal{b}\t%0";
11603 if (get_attr_mode (insn) == MODE_SI)
11604 return "sal{l}\t{%2, %k0|%k0, %2}";
11606 return "sal{b}\t{%2, %0|%0, %2}";
11610 [(set (attr "type")
11611 (cond [(eq_attr "alternative" "2")
11612 (const_string "lea")
11613 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11615 (match_operand 0 "register_operand" ""))
11616 (match_operand 2 "const1_operand" ""))
11617 (const_string "alu")
11619 (const_string "ishift")))
11620 (set_attr "mode" "QI,SI,SI")])
11622 (define_insn "*ashlqi3_1"
11623 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11624 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11625 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11626 (clobber (reg:CC 17))]
11627 "TARGET_PARTIAL_REG_STALL
11628 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11630 switch (get_attr_type (insn))
11633 if (operands[2] != const1_rtx)
11635 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11636 return "add{l}\t{%k0, %k0|%k0, %k0}";
11638 return "add{b}\t{%0, %0|%0, %0}";
11641 if (REG_P (operands[2]))
11643 if (get_attr_mode (insn) == MODE_SI)
11644 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11646 return "sal{b}\t{%b2, %0|%0, %b2}";
11648 else if (GET_CODE (operands[2]) == CONST_INT
11649 && INTVAL (operands[2]) == 1
11650 && (TARGET_SHIFT1 || optimize_size))
11652 if (get_attr_mode (insn) == MODE_SI)
11653 return "sal{l}\t%0";
11655 return "sal{b}\t%0";
11659 if (get_attr_mode (insn) == MODE_SI)
11660 return "sal{l}\t{%2, %k0|%k0, %2}";
11662 return "sal{b}\t{%2, %0|%0, %2}";
11666 [(set (attr "type")
11667 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11669 (match_operand 0 "register_operand" ""))
11670 (match_operand 2 "const1_operand" ""))
11671 (const_string "alu")
11673 (const_string "ishift")))
11674 (set_attr "mode" "QI,SI")])
11676 ;; This pattern can't accept a variable shift count, since shifts by
11677 ;; zero don't affect the flags. We assume that shifts by constant
11678 ;; zero are optimized away.
11679 (define_insn "*ashlqi3_cmp"
11682 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11683 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11685 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11686 (ashift:QI (match_dup 1) (match_dup 2)))]
11687 "ix86_match_ccmode (insn, CCGOCmode)
11688 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11690 switch (get_attr_type (insn))
11693 if (operands[2] != const1_rtx)
11695 return "add{b}\t{%0, %0|%0, %0}";
11698 if (REG_P (operands[2]))
11699 return "sal{b}\t{%b2, %0|%0, %b2}";
11700 else if (GET_CODE (operands[2]) == CONST_INT
11701 && INTVAL (operands[2]) == 1
11702 && (TARGET_SHIFT1 || optimize_size))
11703 return "sal{b}\t%0";
11705 return "sal{b}\t{%2, %0|%0, %2}";
11708 [(set (attr "type")
11709 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11711 (match_operand 0 "register_operand" ""))
11712 (match_operand 2 "const1_operand" ""))
11713 (const_string "alu")
11715 (const_string "ishift")))
11716 (set_attr "mode" "QI")])
11718 ;; See comment above `ashldi3' about how this works.
11720 (define_expand "ashrdi3"
11721 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11722 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11723 (match_operand:QI 2 "nonmemory_operand" "")))
11724 (clobber (reg:CC 17))])]
11727 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11729 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11732 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11736 (define_insn "ashrdi3_63_rex64"
11737 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11738 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11739 (match_operand:DI 2 "const_int_operand" "i,i")))
11740 (clobber (reg:CC 17))]
11741 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11742 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11745 sar{q}\t{%2, %0|%0, %2}"
11746 [(set_attr "type" "imovx,ishift")
11747 (set_attr "prefix_0f" "0,*")
11748 (set_attr "length_immediate" "0,*")
11749 (set_attr "modrm" "0,1")
11750 (set_attr "mode" "DI")])
11752 (define_insn "*ashrdi3_1_one_bit_rex64"
11753 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11754 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11755 (match_operand:QI 2 "const_int_1_operand" "")))
11756 (clobber (reg:CC 17))]
11757 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11758 && (TARGET_SHIFT1 || optimize_size)"
11760 [(set_attr "type" "ishift")
11761 (set (attr "length")
11762 (if_then_else (match_operand:DI 0 "register_operand" "")
11764 (const_string "*")))])
11766 (define_insn "*ashrdi3_1_rex64"
11767 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11768 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11769 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11770 (clobber (reg:CC 17))]
11771 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11773 sar{q}\t{%2, %0|%0, %2}
11774 sar{q}\t{%b2, %0|%0, %b2}"
11775 [(set_attr "type" "ishift")
11776 (set_attr "mode" "DI")])
11778 ;; This pattern can't accept a variable shift count, since shifts by
11779 ;; zero don't affect the flags. We assume that shifts by constant
11780 ;; zero are optimized away.
11781 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11784 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11785 (match_operand:QI 2 "const_int_1_operand" ""))
11787 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11788 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11789 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11790 && (TARGET_SHIFT1 || optimize_size)
11791 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11793 [(set_attr "type" "ishift")
11794 (set (attr "length")
11795 (if_then_else (match_operand:DI 0 "register_operand" "")
11797 (const_string "*")))])
11799 ;; This pattern can't accept a variable shift count, since shifts by
11800 ;; zero don't affect the flags. We assume that shifts by constant
11801 ;; zero are optimized away.
11802 (define_insn "*ashrdi3_cmp_rex64"
11805 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11806 (match_operand:QI 2 "const_int_operand" "n"))
11808 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11809 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11810 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11811 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11812 "sar{q}\t{%2, %0|%0, %2}"
11813 [(set_attr "type" "ishift")
11814 (set_attr "mode" "DI")])
11817 (define_insn "ashrdi3_1"
11818 [(set (match_operand:DI 0 "register_operand" "=r")
11819 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11820 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11821 (clobber (match_scratch:SI 3 "=&r"))
11822 (clobber (reg:CC 17))]
11823 "!TARGET_64BIT && TARGET_CMOVE"
11825 [(set_attr "type" "multi")])
11827 (define_insn "*ashrdi3_2"
11828 [(set (match_operand:DI 0 "register_operand" "=r")
11829 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11830 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11831 (clobber (reg:CC 17))]
11834 [(set_attr "type" "multi")])
11837 [(set (match_operand:DI 0 "register_operand" "")
11838 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11839 (match_operand:QI 2 "nonmemory_operand" "")))
11840 (clobber (match_scratch:SI 3 ""))
11841 (clobber (reg:CC 17))]
11842 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11844 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11847 [(set (match_operand:DI 0 "register_operand" "")
11848 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11849 (match_operand:QI 2 "nonmemory_operand" "")))
11850 (clobber (reg:CC 17))]
11851 "!TARGET_64BIT && reload_completed"
11853 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11855 (define_insn "x86_shrd_1"
11856 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11857 (ior:SI (ashiftrt:SI (match_dup 0)
11858 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11859 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11860 (minus:QI (const_int 32) (match_dup 2)))))
11861 (clobber (reg:CC 17))]
11864 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11865 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11866 [(set_attr "type" "ishift")
11867 (set_attr "prefix_0f" "1")
11868 (set_attr "pent_pair" "np")
11869 (set_attr "ppro_uops" "few")
11870 (set_attr "mode" "SI")])
11872 (define_expand "x86_shift_adj_3"
11873 [(use (match_operand:SI 0 "register_operand" ""))
11874 (use (match_operand:SI 1 "register_operand" ""))
11875 (use (match_operand:QI 2 "register_operand" ""))]
11878 rtx label = gen_label_rtx ();
11881 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11883 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11884 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11885 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11886 gen_rtx_LABEL_REF (VOIDmode, label),
11888 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11889 JUMP_LABEL (tmp) = label;
11891 emit_move_insn (operands[0], operands[1]);
11892 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11894 emit_label (label);
11895 LABEL_NUSES (label) = 1;
11900 (define_insn "ashrsi3_31"
11901 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11902 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11903 (match_operand:SI 2 "const_int_operand" "i,i")))
11904 (clobber (reg:CC 17))]
11905 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11906 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11909 sar{l}\t{%2, %0|%0, %2}"
11910 [(set_attr "type" "imovx,ishift")
11911 (set_attr "prefix_0f" "0,*")
11912 (set_attr "length_immediate" "0,*")
11913 (set_attr "modrm" "0,1")
11914 (set_attr "mode" "SI")])
11916 (define_insn "*ashrsi3_31_zext"
11917 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11918 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11919 (match_operand:SI 2 "const_int_operand" "i,i"))))
11920 (clobber (reg:CC 17))]
11921 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11922 && INTVAL (operands[2]) == 31
11923 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11926 sar{l}\t{%2, %k0|%k0, %2}"
11927 [(set_attr "type" "imovx,ishift")
11928 (set_attr "prefix_0f" "0,*")
11929 (set_attr "length_immediate" "0,*")
11930 (set_attr "modrm" "0,1")
11931 (set_attr "mode" "SI")])
11933 (define_expand "ashrsi3"
11934 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11935 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11936 (match_operand:QI 2 "nonmemory_operand" "")))
11937 (clobber (reg:CC 17))]
11939 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11941 (define_insn "*ashrsi3_1_one_bit"
11942 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11943 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11944 (match_operand:QI 2 "const_int_1_operand" "")))
11945 (clobber (reg:CC 17))]
11946 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11947 && (TARGET_SHIFT1 || optimize_size)"
11949 [(set_attr "type" "ishift")
11950 (set (attr "length")
11951 (if_then_else (match_operand:SI 0 "register_operand" "")
11953 (const_string "*")))])
11955 (define_insn "*ashrsi3_1_one_bit_zext"
11956 [(set (match_operand:DI 0 "register_operand" "=r")
11957 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11958 (match_operand:QI 2 "const_int_1_operand" ""))))
11959 (clobber (reg:CC 17))]
11960 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11961 && (TARGET_SHIFT1 || optimize_size)"
11963 [(set_attr "type" "ishift")
11964 (set_attr "length" "2")])
11966 (define_insn "*ashrsi3_1"
11967 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11968 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11969 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11970 (clobber (reg:CC 17))]
11971 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11973 sar{l}\t{%2, %0|%0, %2}
11974 sar{l}\t{%b2, %0|%0, %b2}"
11975 [(set_attr "type" "ishift")
11976 (set_attr "mode" "SI")])
11978 (define_insn "*ashrsi3_1_zext"
11979 [(set (match_operand:DI 0 "register_operand" "=r,r")
11980 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11981 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11982 (clobber (reg:CC 17))]
11983 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11985 sar{l}\t{%2, %k0|%k0, %2}
11986 sar{l}\t{%b2, %k0|%k0, %b2}"
11987 [(set_attr "type" "ishift")
11988 (set_attr "mode" "SI")])
11990 ;; This pattern can't accept a variable shift count, since shifts by
11991 ;; zero don't affect the flags. We assume that shifts by constant
11992 ;; zero are optimized away.
11993 (define_insn "*ashrsi3_one_bit_cmp"
11996 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11997 (match_operand:QI 2 "const_int_1_operand" ""))
11999 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12000 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12001 "ix86_match_ccmode (insn, CCGOCmode)
12002 && (TARGET_SHIFT1 || optimize_size)
12003 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12005 [(set_attr "type" "ishift")
12006 (set (attr "length")
12007 (if_then_else (match_operand:SI 0 "register_operand" "")
12009 (const_string "*")))])
12011 (define_insn "*ashrsi3_one_bit_cmp_zext"
12014 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12015 (match_operand:QI 2 "const_int_1_operand" ""))
12017 (set (match_operand:DI 0 "register_operand" "=r")
12018 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12019 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
12020 && (TARGET_SHIFT1 || optimize_size)
12021 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12023 [(set_attr "type" "ishift")
12024 (set_attr "length" "2")])
12026 ;; This pattern can't accept a variable shift count, since shifts by
12027 ;; zero don't affect the flags. We assume that shifts by constant
12028 ;; zero are optimized away.
12029 (define_insn "*ashrsi3_cmp"
12032 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12033 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12035 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12036 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12037 "ix86_match_ccmode (insn, CCGOCmode)
12038 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12039 "sar{l}\t{%2, %0|%0, %2}"
12040 [(set_attr "type" "ishift")
12041 (set_attr "mode" "SI")])
12043 (define_insn "*ashrsi3_cmp_zext"
12046 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12047 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12049 (set (match_operand:DI 0 "register_operand" "=r")
12050 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12051 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12052 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12053 "sar{l}\t{%2, %k0|%k0, %2}"
12054 [(set_attr "type" "ishift")
12055 (set_attr "mode" "SI")])
12057 (define_expand "ashrhi3"
12058 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12059 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12060 (match_operand:QI 2 "nonmemory_operand" "")))
12061 (clobber (reg:CC 17))]
12062 "TARGET_HIMODE_MATH"
12063 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
12065 (define_insn "*ashrhi3_1_one_bit"
12066 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12067 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12068 (match_operand:QI 2 "const_int_1_operand" "")))
12069 (clobber (reg:CC 17))]
12070 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
12071 && (TARGET_SHIFT1 || optimize_size)"
12073 [(set_attr "type" "ishift")
12074 (set (attr "length")
12075 (if_then_else (match_operand 0 "register_operand" "")
12077 (const_string "*")))])
12079 (define_insn "*ashrhi3_1"
12080 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12081 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12082 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12083 (clobber (reg:CC 17))]
12084 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12086 sar{w}\t{%2, %0|%0, %2}
12087 sar{w}\t{%b2, %0|%0, %b2}"
12088 [(set_attr "type" "ishift")
12089 (set_attr "mode" "HI")])
12091 ;; This pattern can't accept a variable shift count, since shifts by
12092 ;; zero don't affect the flags. We assume that shifts by constant
12093 ;; zero are optimized away.
12094 (define_insn "*ashrhi3_one_bit_cmp"
12097 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12098 (match_operand:QI 2 "const_int_1_operand" ""))
12100 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12101 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12102 "ix86_match_ccmode (insn, CCGOCmode)
12103 && (TARGET_SHIFT1 || optimize_size)
12104 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12106 [(set_attr "type" "ishift")
12107 (set (attr "length")
12108 (if_then_else (match_operand 0 "register_operand" "")
12110 (const_string "*")))])
12112 ;; This pattern can't accept a variable shift count, since shifts by
12113 ;; zero don't affect the flags. We assume that shifts by constant
12114 ;; zero are optimized away.
12115 (define_insn "*ashrhi3_cmp"
12118 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12119 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12121 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12122 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12123 "ix86_match_ccmode (insn, CCGOCmode)
12124 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12125 "sar{w}\t{%2, %0|%0, %2}"
12126 [(set_attr "type" "ishift")
12127 (set_attr "mode" "HI")])
12129 (define_expand "ashrqi3"
12130 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12131 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12132 (match_operand:QI 2 "nonmemory_operand" "")))
12133 (clobber (reg:CC 17))]
12134 "TARGET_QIMODE_MATH"
12135 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
12137 (define_insn "*ashrqi3_1_one_bit"
12138 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12139 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12140 (match_operand:QI 2 "const_int_1_operand" "")))
12141 (clobber (reg:CC 17))]
12142 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12143 && (TARGET_SHIFT1 || optimize_size)"
12145 [(set_attr "type" "ishift")
12146 (set (attr "length")
12147 (if_then_else (match_operand 0 "register_operand" "")
12149 (const_string "*")))])
12151 (define_insn "*ashrqi3_1_one_bit_slp"
12152 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12153 (ashiftrt:QI (match_dup 0)
12154 (match_operand:QI 1 "const_int_1_operand" "")))
12155 (clobber (reg:CC 17))]
12156 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12157 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
12158 && (TARGET_SHIFT1 || optimize_size)"
12160 [(set_attr "type" "ishift1")
12161 (set (attr "length")
12162 (if_then_else (match_operand 0 "register_operand" "")
12164 (const_string "*")))])
12166 (define_insn "*ashrqi3_1"
12167 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12168 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12169 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12170 (clobber (reg:CC 17))]
12171 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12173 sar{b}\t{%2, %0|%0, %2}
12174 sar{b}\t{%b2, %0|%0, %b2}"
12175 [(set_attr "type" "ishift")
12176 (set_attr "mode" "QI")])
12178 (define_insn "*ashrqi3_1_slp"
12179 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12180 (ashiftrt:QI (match_dup 0)
12181 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12182 (clobber (reg:CC 17))]
12183 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12184 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12186 sar{b}\t{%1, %0|%0, %1}
12187 sar{b}\t{%b1, %0|%0, %b1}"
12188 [(set_attr "type" "ishift1")
12189 (set_attr "mode" "QI")])
12191 ;; This pattern can't accept a variable shift count, since shifts by
12192 ;; zero don't affect the flags. We assume that shifts by constant
12193 ;; zero are optimized away.
12194 (define_insn "*ashrqi3_one_bit_cmp"
12197 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12198 (match_operand:QI 2 "const_int_1_operand" "I"))
12200 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12201 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12202 "ix86_match_ccmode (insn, CCGOCmode)
12203 && (TARGET_SHIFT1 || optimize_size)
12204 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12206 [(set_attr "type" "ishift")
12207 (set (attr "length")
12208 (if_then_else (match_operand 0 "register_operand" "")
12210 (const_string "*")))])
12212 ;; This pattern can't accept a variable shift count, since shifts by
12213 ;; zero don't affect the flags. We assume that shifts by constant
12214 ;; zero are optimized away.
12215 (define_insn "*ashrqi3_cmp"
12218 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12219 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12221 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12222 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12223 "ix86_match_ccmode (insn, CCGOCmode)
12224 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12225 "sar{b}\t{%2, %0|%0, %2}"
12226 [(set_attr "type" "ishift")
12227 (set_attr "mode" "QI")])
12229 ;; Logical shift instructions
12231 ;; See comment above `ashldi3' about how this works.
12233 (define_expand "lshrdi3"
12234 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
12235 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12236 (match_operand:QI 2 "nonmemory_operand" "")))
12237 (clobber (reg:CC 17))])]
12240 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
12242 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
12245 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
12249 (define_insn "*lshrdi3_1_one_bit_rex64"
12250 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12251 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12252 (match_operand:QI 2 "const_int_1_operand" "")))
12253 (clobber (reg:CC 17))]
12254 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12255 && (TARGET_SHIFT1 || optimize_size)"
12257 [(set_attr "type" "ishift")
12258 (set (attr "length")
12259 (if_then_else (match_operand:DI 0 "register_operand" "")
12261 (const_string "*")))])
12263 (define_insn "*lshrdi3_1_rex64"
12264 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12265 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12266 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12267 (clobber (reg:CC 17))]
12268 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12270 shr{q}\t{%2, %0|%0, %2}
12271 shr{q}\t{%b2, %0|%0, %b2}"
12272 [(set_attr "type" "ishift")
12273 (set_attr "mode" "DI")])
12275 ;; This pattern can't accept a variable shift count, since shifts by
12276 ;; zero don't affect the flags. We assume that shifts by constant
12277 ;; zero are optimized away.
12278 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12281 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12282 (match_operand:QI 2 "const_int_1_operand" ""))
12284 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12285 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12286 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12287 && (TARGET_SHIFT1 || optimize_size)
12288 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12290 [(set_attr "type" "ishift")
12291 (set (attr "length")
12292 (if_then_else (match_operand:DI 0 "register_operand" "")
12294 (const_string "*")))])
12296 ;; This pattern can't accept a variable shift count, since shifts by
12297 ;; zero don't affect the flags. We assume that shifts by constant
12298 ;; zero are optimized away.
12299 (define_insn "*lshrdi3_cmp_rex64"
12302 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12303 (match_operand:QI 2 "const_int_operand" "e"))
12305 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12306 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12307 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12308 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12309 "shr{q}\t{%2, %0|%0, %2}"
12310 [(set_attr "type" "ishift")
12311 (set_attr "mode" "DI")])
12313 (define_insn "lshrdi3_1"
12314 [(set (match_operand:DI 0 "register_operand" "=r")
12315 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12316 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12317 (clobber (match_scratch:SI 3 "=&r"))
12318 (clobber (reg:CC 17))]
12319 "!TARGET_64BIT && TARGET_CMOVE"
12321 [(set_attr "type" "multi")])
12323 (define_insn "*lshrdi3_2"
12324 [(set (match_operand:DI 0 "register_operand" "=r")
12325 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12326 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12327 (clobber (reg:CC 17))]
12330 [(set_attr "type" "multi")])
12333 [(set (match_operand:DI 0 "register_operand" "")
12334 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12335 (match_operand:QI 2 "nonmemory_operand" "")))
12336 (clobber (match_scratch:SI 3 ""))
12337 (clobber (reg:CC 17))]
12338 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
12340 "ix86_split_lshrdi (operands, operands[3]); DONE;")
12343 [(set (match_operand:DI 0 "register_operand" "")
12344 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12345 (match_operand:QI 2 "nonmemory_operand" "")))
12346 (clobber (reg:CC 17))]
12347 "!TARGET_64BIT && reload_completed"
12349 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
12351 (define_expand "lshrsi3"
12352 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12353 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12354 (match_operand:QI 2 "nonmemory_operand" "")))
12355 (clobber (reg:CC 17))]
12357 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12359 (define_insn "*lshrsi3_1_one_bit"
12360 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12361 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12362 (match_operand:QI 2 "const_int_1_operand" "")))
12363 (clobber (reg:CC 17))]
12364 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12365 && (TARGET_SHIFT1 || optimize_size)"
12367 [(set_attr "type" "ishift")
12368 (set (attr "length")
12369 (if_then_else (match_operand:SI 0 "register_operand" "")
12371 (const_string "*")))])
12373 (define_insn "*lshrsi3_1_one_bit_zext"
12374 [(set (match_operand:DI 0 "register_operand" "=r")
12375 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12376 (match_operand:QI 2 "const_int_1_operand" "")))
12377 (clobber (reg:CC 17))]
12378 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12379 && (TARGET_SHIFT1 || optimize_size)"
12381 [(set_attr "type" "ishift")
12382 (set_attr "length" "2")])
12384 (define_insn "*lshrsi3_1"
12385 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12386 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12387 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12388 (clobber (reg:CC 17))]
12389 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12391 shr{l}\t{%2, %0|%0, %2}
12392 shr{l}\t{%b2, %0|%0, %b2}"
12393 [(set_attr "type" "ishift")
12394 (set_attr "mode" "SI")])
12396 (define_insn "*lshrsi3_1_zext"
12397 [(set (match_operand:DI 0 "register_operand" "=r,r")
12399 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12400 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12401 (clobber (reg:CC 17))]
12402 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12404 shr{l}\t{%2, %k0|%k0, %2}
12405 shr{l}\t{%b2, %k0|%k0, %b2}"
12406 [(set_attr "type" "ishift")
12407 (set_attr "mode" "SI")])
12409 ;; This pattern can't accept a variable shift count, since shifts by
12410 ;; zero don't affect the flags. We assume that shifts by constant
12411 ;; zero are optimized away.
12412 (define_insn "*lshrsi3_one_bit_cmp"
12415 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12416 (match_operand:QI 2 "const_int_1_operand" ""))
12418 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12419 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12420 "ix86_match_ccmode (insn, CCGOCmode)
12421 && (TARGET_SHIFT1 || optimize_size)
12422 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12424 [(set_attr "type" "ishift")
12425 (set (attr "length")
12426 (if_then_else (match_operand:SI 0 "register_operand" "")
12428 (const_string "*")))])
12430 (define_insn "*lshrsi3_cmp_one_bit_zext"
12433 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12434 (match_operand:QI 2 "const_int_1_operand" ""))
12436 (set (match_operand:DI 0 "register_operand" "=r")
12437 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12438 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12439 && (TARGET_SHIFT1 || optimize_size)
12440 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12442 [(set_attr "type" "ishift")
12443 (set_attr "length" "2")])
12445 ;; This pattern can't accept a variable shift count, since shifts by
12446 ;; zero don't affect the flags. We assume that shifts by constant
12447 ;; zero are optimized away.
12448 (define_insn "*lshrsi3_cmp"
12451 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12452 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12454 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12455 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12456 "ix86_match_ccmode (insn, CCGOCmode)
12457 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12458 "shr{l}\t{%2, %0|%0, %2}"
12459 [(set_attr "type" "ishift")
12460 (set_attr "mode" "SI")])
12462 (define_insn "*lshrsi3_cmp_zext"
12465 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12466 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12468 (set (match_operand:DI 0 "register_operand" "=r")
12469 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12470 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12471 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12472 "shr{l}\t{%2, %k0|%k0, %2}"
12473 [(set_attr "type" "ishift")
12474 (set_attr "mode" "SI")])
12476 (define_expand "lshrhi3"
12477 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12478 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12479 (match_operand:QI 2 "nonmemory_operand" "")))
12480 (clobber (reg:CC 17))]
12481 "TARGET_HIMODE_MATH"
12482 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12484 (define_insn "*lshrhi3_1_one_bit"
12485 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12486 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12487 (match_operand:QI 2 "const_int_1_operand" "")))
12488 (clobber (reg:CC 17))]
12489 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12490 && (TARGET_SHIFT1 || optimize_size)"
12492 [(set_attr "type" "ishift")
12493 (set (attr "length")
12494 (if_then_else (match_operand 0 "register_operand" "")
12496 (const_string "*")))])
12498 (define_insn "*lshrhi3_1"
12499 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12500 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12501 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12502 (clobber (reg:CC 17))]
12503 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12505 shr{w}\t{%2, %0|%0, %2}
12506 shr{w}\t{%b2, %0|%0, %b2}"
12507 [(set_attr "type" "ishift")
12508 (set_attr "mode" "HI")])
12510 ;; This pattern can't accept a variable shift count, since shifts by
12511 ;; zero don't affect the flags. We assume that shifts by constant
12512 ;; zero are optimized away.
12513 (define_insn "*lshrhi3_one_bit_cmp"
12516 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12517 (match_operand:QI 2 "const_int_1_operand" ""))
12519 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12520 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12521 "ix86_match_ccmode (insn, CCGOCmode)
12522 && (TARGET_SHIFT1 || optimize_size)
12523 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12525 [(set_attr "type" "ishift")
12526 (set (attr "length")
12527 (if_then_else (match_operand:SI 0 "register_operand" "")
12529 (const_string "*")))])
12531 ;; This pattern can't accept a variable shift count, since shifts by
12532 ;; zero don't affect the flags. We assume that shifts by constant
12533 ;; zero are optimized away.
12534 (define_insn "*lshrhi3_cmp"
12537 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12538 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12540 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12541 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12542 "ix86_match_ccmode (insn, CCGOCmode)
12543 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12544 "shr{w}\t{%2, %0|%0, %2}"
12545 [(set_attr "type" "ishift")
12546 (set_attr "mode" "HI")])
12548 (define_expand "lshrqi3"
12549 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12550 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12551 (match_operand:QI 2 "nonmemory_operand" "")))
12552 (clobber (reg:CC 17))]
12553 "TARGET_QIMODE_MATH"
12554 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12556 (define_insn "*lshrqi3_1_one_bit"
12557 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12558 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12559 (match_operand:QI 2 "const_int_1_operand" "")))
12560 (clobber (reg:CC 17))]
12561 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12562 && (TARGET_SHIFT1 || optimize_size)"
12564 [(set_attr "type" "ishift")
12565 (set (attr "length")
12566 (if_then_else (match_operand 0 "register_operand" "")
12568 (const_string "*")))])
12570 (define_insn "*lshrqi3_1_one_bit_slp"
12571 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12572 (lshiftrt:QI (match_dup 0)
12573 (match_operand:QI 1 "const_int_1_operand" "")))
12574 (clobber (reg:CC 17))]
12575 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12576 && (TARGET_SHIFT1 || optimize_size)"
12578 [(set_attr "type" "ishift1")
12579 (set (attr "length")
12580 (if_then_else (match_operand 0 "register_operand" "")
12582 (const_string "*")))])
12584 (define_insn "*lshrqi3_1"
12585 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12586 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12587 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12588 (clobber (reg:CC 17))]
12589 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12591 shr{b}\t{%2, %0|%0, %2}
12592 shr{b}\t{%b2, %0|%0, %b2}"
12593 [(set_attr "type" "ishift")
12594 (set_attr "mode" "QI")])
12596 (define_insn "*lshrqi3_1_slp"
12597 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12598 (lshiftrt:QI (match_dup 0)
12599 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12600 (clobber (reg:CC 17))]
12601 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12602 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12604 shr{b}\t{%1, %0|%0, %1}
12605 shr{b}\t{%b1, %0|%0, %b1}"
12606 [(set_attr "type" "ishift1")
12607 (set_attr "mode" "QI")])
12609 ;; This pattern can't accept a variable shift count, since shifts by
12610 ;; zero don't affect the flags. We assume that shifts by constant
12611 ;; zero are optimized away.
12612 (define_insn "*lshrqi2_one_bit_cmp"
12615 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12616 (match_operand:QI 2 "const_int_1_operand" ""))
12618 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12619 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12620 "ix86_match_ccmode (insn, CCGOCmode)
12621 && (TARGET_SHIFT1 || optimize_size)
12622 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12624 [(set_attr "type" "ishift")
12625 (set (attr "length")
12626 (if_then_else (match_operand:SI 0 "register_operand" "")
12628 (const_string "*")))])
12630 ;; This pattern can't accept a variable shift count, since shifts by
12631 ;; zero don't affect the flags. We assume that shifts by constant
12632 ;; zero are optimized away.
12633 (define_insn "*lshrqi2_cmp"
12636 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12637 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12639 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12640 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12641 "ix86_match_ccmode (insn, CCGOCmode)
12642 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12643 "shr{b}\t{%2, %0|%0, %2}"
12644 [(set_attr "type" "ishift")
12645 (set_attr "mode" "QI")])
12647 ;; Rotate instructions
12649 (define_expand "rotldi3"
12650 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12651 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12652 (match_operand:QI 2 "nonmemory_operand" "")))
12653 (clobber (reg:CC 17))]
12655 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12657 (define_insn "*rotlsi3_1_one_bit_rex64"
12658 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12659 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12660 (match_operand:QI 2 "const_int_1_operand" "")))
12661 (clobber (reg:CC 17))]
12662 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12663 && (TARGET_SHIFT1 || optimize_size)"
12665 [(set_attr "type" "rotate")
12666 (set (attr "length")
12667 (if_then_else (match_operand:DI 0 "register_operand" "")
12669 (const_string "*")))])
12671 (define_insn "*rotldi3_1_rex64"
12672 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12673 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12674 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12675 (clobber (reg:CC 17))]
12676 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12678 rol{q}\t{%2, %0|%0, %2}
12679 rol{q}\t{%b2, %0|%0, %b2}"
12680 [(set_attr "type" "rotate")
12681 (set_attr "mode" "DI")])
12683 (define_expand "rotlsi3"
12684 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12685 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12686 (match_operand:QI 2 "nonmemory_operand" "")))
12687 (clobber (reg:CC 17))]
12689 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12691 (define_insn "*rotlsi3_1_one_bit"
12692 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12693 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12694 (match_operand:QI 2 "const_int_1_operand" "")))
12695 (clobber (reg:CC 17))]
12696 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12697 && (TARGET_SHIFT1 || optimize_size)"
12699 [(set_attr "type" "rotate")
12700 (set (attr "length")
12701 (if_then_else (match_operand:SI 0 "register_operand" "")
12703 (const_string "*")))])
12705 (define_insn "*rotlsi3_1_one_bit_zext"
12706 [(set (match_operand:DI 0 "register_operand" "=r")
12708 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12709 (match_operand:QI 2 "const_int_1_operand" ""))))
12710 (clobber (reg:CC 17))]
12711 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12712 && (TARGET_SHIFT1 || optimize_size)"
12714 [(set_attr "type" "rotate")
12715 (set_attr "length" "2")])
12717 (define_insn "*rotlsi3_1"
12718 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12719 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12720 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12721 (clobber (reg:CC 17))]
12722 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12724 rol{l}\t{%2, %0|%0, %2}
12725 rol{l}\t{%b2, %0|%0, %b2}"
12726 [(set_attr "type" "rotate")
12727 (set_attr "mode" "SI")])
12729 (define_insn "*rotlsi3_1_zext"
12730 [(set (match_operand:DI 0 "register_operand" "=r,r")
12732 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12733 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12734 (clobber (reg:CC 17))]
12735 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12737 rol{l}\t{%2, %k0|%k0, %2}
12738 rol{l}\t{%b2, %k0|%k0, %b2}"
12739 [(set_attr "type" "rotate")
12740 (set_attr "mode" "SI")])
12742 (define_expand "rotlhi3"
12743 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12744 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12745 (match_operand:QI 2 "nonmemory_operand" "")))
12746 (clobber (reg:CC 17))]
12747 "TARGET_HIMODE_MATH"
12748 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12750 (define_insn "*rotlhi3_1_one_bit"
12751 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12752 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12753 (match_operand:QI 2 "const_int_1_operand" "")))
12754 (clobber (reg:CC 17))]
12755 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12756 && (TARGET_SHIFT1 || optimize_size)"
12758 [(set_attr "type" "rotate")
12759 (set (attr "length")
12760 (if_then_else (match_operand 0 "register_operand" "")
12762 (const_string "*")))])
12764 (define_insn "*rotlhi3_1"
12765 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12766 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12767 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12768 (clobber (reg:CC 17))]
12769 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12771 rol{w}\t{%2, %0|%0, %2}
12772 rol{w}\t{%b2, %0|%0, %b2}"
12773 [(set_attr "type" "rotate")
12774 (set_attr "mode" "HI")])
12776 (define_expand "rotlqi3"
12777 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12778 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12779 (match_operand:QI 2 "nonmemory_operand" "")))
12780 (clobber (reg:CC 17))]
12781 "TARGET_QIMODE_MATH"
12782 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12784 (define_insn "*rotlqi3_1_one_bit_slp"
12785 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12786 (rotate:QI (match_dup 0)
12787 (match_operand:QI 1 "const_int_1_operand" "")))
12788 (clobber (reg:CC 17))]
12789 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12790 && (TARGET_SHIFT1 || optimize_size)"
12792 [(set_attr "type" "rotate1")
12793 (set (attr "length")
12794 (if_then_else (match_operand 0 "register_operand" "")
12796 (const_string "*")))])
12798 (define_insn "*rotlqi3_1_one_bit"
12799 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12800 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12801 (match_operand:QI 2 "const_int_1_operand" "")))
12802 (clobber (reg:CC 17))]
12803 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12804 && (TARGET_SHIFT1 || optimize_size)"
12806 [(set_attr "type" "rotate")
12807 (set (attr "length")
12808 (if_then_else (match_operand 0 "register_operand" "")
12810 (const_string "*")))])
12812 (define_insn "*rotlqi3_1_slp"
12813 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12814 (rotate:QI (match_dup 0)
12815 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12816 (clobber (reg:CC 17))]
12817 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12818 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12820 rol{b}\t{%1, %0|%0, %1}
12821 rol{b}\t{%b1, %0|%0, %b1}"
12822 [(set_attr "type" "rotate1")
12823 (set_attr "mode" "QI")])
12825 (define_insn "*rotlqi3_1"
12826 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12827 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12828 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12829 (clobber (reg:CC 17))]
12830 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12832 rol{b}\t{%2, %0|%0, %2}
12833 rol{b}\t{%b2, %0|%0, %b2}"
12834 [(set_attr "type" "rotate")
12835 (set_attr "mode" "QI")])
12837 (define_expand "rotrdi3"
12838 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12839 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12840 (match_operand:QI 2 "nonmemory_operand" "")))
12841 (clobber (reg:CC 17))]
12843 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12845 (define_insn "*rotrdi3_1_one_bit_rex64"
12846 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12847 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12848 (match_operand:QI 2 "const_int_1_operand" "")))
12849 (clobber (reg:CC 17))]
12850 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12851 && (TARGET_SHIFT1 || optimize_size)"
12853 [(set_attr "type" "rotate")
12854 (set (attr "length")
12855 (if_then_else (match_operand:DI 0 "register_operand" "")
12857 (const_string "*")))])
12859 (define_insn "*rotrdi3_1_rex64"
12860 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12861 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12862 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12863 (clobber (reg:CC 17))]
12864 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12866 ror{q}\t{%2, %0|%0, %2}
12867 ror{q}\t{%b2, %0|%0, %b2}"
12868 [(set_attr "type" "rotate")
12869 (set_attr "mode" "DI")])
12871 (define_expand "rotrsi3"
12872 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12873 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12874 (match_operand:QI 2 "nonmemory_operand" "")))
12875 (clobber (reg:CC 17))]
12877 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12879 (define_insn "*rotrsi3_1_one_bit"
12880 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12881 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12882 (match_operand:QI 2 "const_int_1_operand" "")))
12883 (clobber (reg:CC 17))]
12884 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12885 && (TARGET_SHIFT1 || optimize_size)"
12887 [(set_attr "type" "rotate")
12888 (set (attr "length")
12889 (if_then_else (match_operand:SI 0 "register_operand" "")
12891 (const_string "*")))])
12893 (define_insn "*rotrsi3_1_one_bit_zext"
12894 [(set (match_operand:DI 0 "register_operand" "=r")
12896 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12897 (match_operand:QI 2 "const_int_1_operand" ""))))
12898 (clobber (reg:CC 17))]
12899 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12900 && (TARGET_SHIFT1 || optimize_size)"
12902 [(set_attr "type" "rotate")
12903 (set (attr "length")
12904 (if_then_else (match_operand:SI 0 "register_operand" "")
12906 (const_string "*")))])
12908 (define_insn "*rotrsi3_1"
12909 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12910 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12911 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12912 (clobber (reg:CC 17))]
12913 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12915 ror{l}\t{%2, %0|%0, %2}
12916 ror{l}\t{%b2, %0|%0, %b2}"
12917 [(set_attr "type" "rotate")
12918 (set_attr "mode" "SI")])
12920 (define_insn "*rotrsi3_1_zext"
12921 [(set (match_operand:DI 0 "register_operand" "=r,r")
12923 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12924 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12925 (clobber (reg:CC 17))]
12926 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12928 ror{l}\t{%2, %k0|%k0, %2}
12929 ror{l}\t{%b2, %k0|%k0, %b2}"
12930 [(set_attr "type" "rotate")
12931 (set_attr "mode" "SI")])
12933 (define_expand "rotrhi3"
12934 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12935 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12936 (match_operand:QI 2 "nonmemory_operand" "")))
12937 (clobber (reg:CC 17))]
12938 "TARGET_HIMODE_MATH"
12939 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12941 (define_insn "*rotrhi3_one_bit"
12942 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12943 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12944 (match_operand:QI 2 "const_int_1_operand" "")))
12945 (clobber (reg:CC 17))]
12946 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12947 && (TARGET_SHIFT1 || optimize_size)"
12949 [(set_attr "type" "rotate")
12950 (set (attr "length")
12951 (if_then_else (match_operand 0 "register_operand" "")
12953 (const_string "*")))])
12955 (define_insn "*rotrhi3"
12956 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12957 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12958 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12959 (clobber (reg:CC 17))]
12960 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12962 ror{w}\t{%2, %0|%0, %2}
12963 ror{w}\t{%b2, %0|%0, %b2}"
12964 [(set_attr "type" "rotate")
12965 (set_attr "mode" "HI")])
12967 (define_expand "rotrqi3"
12968 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12969 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12970 (match_operand:QI 2 "nonmemory_operand" "")))
12971 (clobber (reg:CC 17))]
12972 "TARGET_QIMODE_MATH"
12973 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12975 (define_insn "*rotrqi3_1_one_bit"
12976 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12977 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12978 (match_operand:QI 2 "const_int_1_operand" "")))
12979 (clobber (reg:CC 17))]
12980 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12981 && (TARGET_SHIFT1 || optimize_size)"
12983 [(set_attr "type" "rotate")
12984 (set (attr "length")
12985 (if_then_else (match_operand 0 "register_operand" "")
12987 (const_string "*")))])
12989 (define_insn "*rotrqi3_1_one_bit_slp"
12990 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12991 (rotatert:QI (match_dup 0)
12992 (match_operand:QI 1 "const_int_1_operand" "")))
12993 (clobber (reg:CC 17))]
12994 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12995 && (TARGET_SHIFT1 || optimize_size)"
12997 [(set_attr "type" "rotate1")
12998 (set (attr "length")
12999 (if_then_else (match_operand 0 "register_operand" "")
13001 (const_string "*")))])
13003 (define_insn "*rotrqi3_1"
13004 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13005 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13006 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13007 (clobber (reg:CC 17))]
13008 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13010 ror{b}\t{%2, %0|%0, %2}
13011 ror{b}\t{%b2, %0|%0, %b2}"
13012 [(set_attr "type" "rotate")
13013 (set_attr "mode" "QI")])
13015 (define_insn "*rotrqi3_1_slp"
13016 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13017 (rotatert:QI (match_dup 0)
13018 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13019 (clobber (reg:CC 17))]
13020 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13021 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
13023 ror{b}\t{%1, %0|%0, %1}
13024 ror{b}\t{%b1, %0|%0, %b1}"
13025 [(set_attr "type" "rotate1")
13026 (set_attr "mode" "QI")])
13028 ;; Bit set / bit test instructions
13030 (define_expand "extv"
13031 [(set (match_operand:SI 0 "register_operand" "")
13032 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
13033 (match_operand:SI 2 "immediate_operand" "")
13034 (match_operand:SI 3 "immediate_operand" "")))]
13037 /* Handle extractions from %ah et al. */
13038 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13041 /* From mips.md: extract_bit_field doesn't verify that our source
13042 matches the predicate, so check it again here. */
13043 if (! register_operand (operands[1], VOIDmode))
13047 (define_expand "extzv"
13048 [(set (match_operand:SI 0 "register_operand" "")
13049 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
13050 (match_operand:SI 2 "immediate_operand" "")
13051 (match_operand:SI 3 "immediate_operand" "")))]
13054 /* Handle extractions from %ah et al. */
13055 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13058 /* From mips.md: extract_bit_field doesn't verify that our source
13059 matches the predicate, so check it again here. */
13060 if (! register_operand (operands[1], VOIDmode))
13064 (define_expand "insv"
13065 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
13066 (match_operand:SI 1 "immediate_operand" "")
13067 (match_operand:SI 2 "immediate_operand" ""))
13068 (match_operand:SI 3 "register_operand" ""))]
13071 /* Handle extractions from %ah et al. */
13072 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
13075 /* From mips.md: insert_bit_field doesn't verify that our source
13076 matches the predicate, so check it again here. */
13077 if (! register_operand (operands[0], VOIDmode))
13081 ;; %%% bts, btr, btc, bt.
13083 ;; Store-flag instructions.
13085 ;; For all sCOND expanders, also expand the compare or test insn that
13086 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
13088 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
13089 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
13090 ;; way, which can later delete the movzx if only QImode is needed.
13092 (define_expand "seq"
13093 [(set (match_operand:QI 0 "register_operand" "")
13094 (eq:QI (reg:CC 17) (const_int 0)))]
13096 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
13098 (define_expand "sne"
13099 [(set (match_operand:QI 0 "register_operand" "")
13100 (ne:QI (reg:CC 17) (const_int 0)))]
13102 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
13104 (define_expand "sgt"
13105 [(set (match_operand:QI 0 "register_operand" "")
13106 (gt:QI (reg:CC 17) (const_int 0)))]
13108 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
13110 (define_expand "sgtu"
13111 [(set (match_operand:QI 0 "register_operand" "")
13112 (gtu:QI (reg:CC 17) (const_int 0)))]
13114 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
13116 (define_expand "slt"
13117 [(set (match_operand:QI 0 "register_operand" "")
13118 (lt:QI (reg:CC 17) (const_int 0)))]
13120 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
13122 (define_expand "sltu"
13123 [(set (match_operand:QI 0 "register_operand" "")
13124 (ltu:QI (reg:CC 17) (const_int 0)))]
13126 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
13128 (define_expand "sge"
13129 [(set (match_operand:QI 0 "register_operand" "")
13130 (ge:QI (reg:CC 17) (const_int 0)))]
13132 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
13134 (define_expand "sgeu"
13135 [(set (match_operand:QI 0 "register_operand" "")
13136 (geu:QI (reg:CC 17) (const_int 0)))]
13138 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
13140 (define_expand "sle"
13141 [(set (match_operand:QI 0 "register_operand" "")
13142 (le:QI (reg:CC 17) (const_int 0)))]
13144 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
13146 (define_expand "sleu"
13147 [(set (match_operand:QI 0 "register_operand" "")
13148 (leu:QI (reg:CC 17) (const_int 0)))]
13150 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
13152 (define_expand "sunordered"
13153 [(set (match_operand:QI 0 "register_operand" "")
13154 (unordered:QI (reg:CC 17) (const_int 0)))]
13155 "TARGET_80387 || TARGET_SSE"
13156 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
13158 (define_expand "sordered"
13159 [(set (match_operand:QI 0 "register_operand" "")
13160 (ordered:QI (reg:CC 17) (const_int 0)))]
13162 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
13164 (define_expand "suneq"
13165 [(set (match_operand:QI 0 "register_operand" "")
13166 (uneq:QI (reg:CC 17) (const_int 0)))]
13167 "TARGET_80387 || TARGET_SSE"
13168 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
13170 (define_expand "sunge"
13171 [(set (match_operand:QI 0 "register_operand" "")
13172 (unge:QI (reg:CC 17) (const_int 0)))]
13173 "TARGET_80387 || TARGET_SSE"
13174 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
13176 (define_expand "sungt"
13177 [(set (match_operand:QI 0 "register_operand" "")
13178 (ungt:QI (reg:CC 17) (const_int 0)))]
13179 "TARGET_80387 || TARGET_SSE"
13180 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
13182 (define_expand "sunle"
13183 [(set (match_operand:QI 0 "register_operand" "")
13184 (unle:QI (reg:CC 17) (const_int 0)))]
13185 "TARGET_80387 || TARGET_SSE"
13186 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
13188 (define_expand "sunlt"
13189 [(set (match_operand:QI 0 "register_operand" "")
13190 (unlt:QI (reg:CC 17) (const_int 0)))]
13191 "TARGET_80387 || TARGET_SSE"
13192 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
13194 (define_expand "sltgt"
13195 [(set (match_operand:QI 0 "register_operand" "")
13196 (ltgt:QI (reg:CC 17) (const_int 0)))]
13197 "TARGET_80387 || TARGET_SSE"
13198 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
13200 (define_insn "*setcc_1"
13201 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13202 (match_operator:QI 1 "ix86_comparison_operator"
13203 [(reg 17) (const_int 0)]))]
13206 [(set_attr "type" "setcc")
13207 (set_attr "mode" "QI")])
13209 (define_insn "setcc_2"
13210 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13211 (match_operator:QI 1 "ix86_comparison_operator"
13212 [(reg 17) (const_int 0)]))]
13215 [(set_attr "type" "setcc")
13216 (set_attr "mode" "QI")])
13218 ;; In general it is not safe to assume too much about CCmode registers,
13219 ;; so simplify-rtx stops when it sees a second one. Under certain
13220 ;; conditions this is safe on x86, so help combine not create
13227 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13228 (ne:QI (match_operator 1 "ix86_comparison_operator"
13229 [(reg 17) (const_int 0)])
13232 [(set (match_dup 0) (match_dup 1))]
13234 PUT_MODE (operands[1], QImode);
13238 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13239 (ne:QI (match_operator 1 "ix86_comparison_operator"
13240 [(reg 17) (const_int 0)])
13243 [(set (match_dup 0) (match_dup 1))]
13245 PUT_MODE (operands[1], QImode);
13249 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13250 (eq:QI (match_operator 1 "ix86_comparison_operator"
13251 [(reg 17) (const_int 0)])
13254 [(set (match_dup 0) (match_dup 1))]
13256 rtx new_op1 = copy_rtx (operands[1]);
13257 operands[1] = new_op1;
13258 PUT_MODE (new_op1, QImode);
13259 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13260 GET_MODE (XEXP (new_op1, 0))));
13262 /* Make sure that (a) the CCmode we have for the flags is strong
13263 enough for the reversed compare or (b) we have a valid FP compare. */
13264 if (! ix86_comparison_operator (new_op1, VOIDmode))
13269 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13270 (eq:QI (match_operator 1 "ix86_comparison_operator"
13271 [(reg 17) (const_int 0)])
13274 [(set (match_dup 0) (match_dup 1))]
13276 rtx new_op1 = copy_rtx (operands[1]);
13277 operands[1] = new_op1;
13278 PUT_MODE (new_op1, QImode);
13279 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13280 GET_MODE (XEXP (new_op1, 0))));
13282 /* Make sure that (a) the CCmode we have for the flags is strong
13283 enough for the reversed compare or (b) we have a valid FP compare. */
13284 if (! ix86_comparison_operator (new_op1, VOIDmode))
13288 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
13289 ;; subsequent logical operations are used to imitate conditional moves.
13290 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
13291 ;; it directly. Further holding this value in pseudo register might bring
13292 ;; problem in implicit normalization in spill code.
13293 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
13294 ;; instructions after reload by splitting the conditional move patterns.
13296 (define_insn "*sse_setccsf"
13297 [(set (match_operand:SF 0 "register_operand" "=x")
13298 (match_operator:SF 1 "sse_comparison_operator"
13299 [(match_operand:SF 2 "register_operand" "0")
13300 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
13301 "TARGET_SSE && reload_completed"
13302 "cmp%D1ss\t{%3, %0|%0, %3}"
13303 [(set_attr "type" "ssecmp")
13304 (set_attr "mode" "SF")])
13306 (define_insn "*sse_setccdf"
13307 [(set (match_operand:DF 0 "register_operand" "=Y")
13308 (match_operator:DF 1 "sse_comparison_operator"
13309 [(match_operand:DF 2 "register_operand" "0")
13310 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
13311 "TARGET_SSE2 && reload_completed"
13312 "cmp%D1sd\t{%3, %0|%0, %3}"
13313 [(set_attr "type" "ssecmp")
13314 (set_attr "mode" "DF")])
13316 ;; Basic conditional jump instructions.
13317 ;; We ignore the overflow flag for signed branch instructions.
13319 ;; For all bCOND expanders, also expand the compare or test insn that
13320 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
13322 (define_expand "beq"
13324 (if_then_else (match_dup 1)
13325 (label_ref (match_operand 0 "" ""))
13328 "ix86_expand_branch (EQ, operands[0]); DONE;")
13330 (define_expand "bne"
13332 (if_then_else (match_dup 1)
13333 (label_ref (match_operand 0 "" ""))
13336 "ix86_expand_branch (NE, operands[0]); DONE;")
13338 (define_expand "bgt"
13340 (if_then_else (match_dup 1)
13341 (label_ref (match_operand 0 "" ""))
13344 "ix86_expand_branch (GT, operands[0]); DONE;")
13346 (define_expand "bgtu"
13348 (if_then_else (match_dup 1)
13349 (label_ref (match_operand 0 "" ""))
13352 "ix86_expand_branch (GTU, operands[0]); DONE;")
13354 (define_expand "blt"
13356 (if_then_else (match_dup 1)
13357 (label_ref (match_operand 0 "" ""))
13360 "ix86_expand_branch (LT, operands[0]); DONE;")
13362 (define_expand "bltu"
13364 (if_then_else (match_dup 1)
13365 (label_ref (match_operand 0 "" ""))
13368 "ix86_expand_branch (LTU, operands[0]); DONE;")
13370 (define_expand "bge"
13372 (if_then_else (match_dup 1)
13373 (label_ref (match_operand 0 "" ""))
13376 "ix86_expand_branch (GE, operands[0]); DONE;")
13378 (define_expand "bgeu"
13380 (if_then_else (match_dup 1)
13381 (label_ref (match_operand 0 "" ""))
13384 "ix86_expand_branch (GEU, operands[0]); DONE;")
13386 (define_expand "ble"
13388 (if_then_else (match_dup 1)
13389 (label_ref (match_operand 0 "" ""))
13392 "ix86_expand_branch (LE, operands[0]); DONE;")
13394 (define_expand "bleu"
13396 (if_then_else (match_dup 1)
13397 (label_ref (match_operand 0 "" ""))
13400 "ix86_expand_branch (LEU, operands[0]); DONE;")
13402 (define_expand "bunordered"
13404 (if_then_else (match_dup 1)
13405 (label_ref (match_operand 0 "" ""))
13407 "TARGET_80387 || TARGET_SSE"
13408 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13410 (define_expand "bordered"
13412 (if_then_else (match_dup 1)
13413 (label_ref (match_operand 0 "" ""))
13415 "TARGET_80387 || TARGET_SSE"
13416 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13418 (define_expand "buneq"
13420 (if_then_else (match_dup 1)
13421 (label_ref (match_operand 0 "" ""))
13423 "TARGET_80387 || TARGET_SSE"
13424 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13426 (define_expand "bunge"
13428 (if_then_else (match_dup 1)
13429 (label_ref (match_operand 0 "" ""))
13431 "TARGET_80387 || TARGET_SSE"
13432 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13434 (define_expand "bungt"
13436 (if_then_else (match_dup 1)
13437 (label_ref (match_operand 0 "" ""))
13439 "TARGET_80387 || TARGET_SSE"
13440 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13442 (define_expand "bunle"
13444 (if_then_else (match_dup 1)
13445 (label_ref (match_operand 0 "" ""))
13447 "TARGET_80387 || TARGET_SSE"
13448 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13450 (define_expand "bunlt"
13452 (if_then_else (match_dup 1)
13453 (label_ref (match_operand 0 "" ""))
13455 "TARGET_80387 || TARGET_SSE"
13456 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13458 (define_expand "bltgt"
13460 (if_then_else (match_dup 1)
13461 (label_ref (match_operand 0 "" ""))
13463 "TARGET_80387 || TARGET_SSE"
13464 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13466 (define_insn "*jcc_1"
13468 (if_then_else (match_operator 1 "ix86_comparison_operator"
13469 [(reg 17) (const_int 0)])
13470 (label_ref (match_operand 0 "" ""))
13474 [(set_attr "type" "ibr")
13475 (set_attr "modrm" "0")
13476 (set (attr "length")
13477 (if_then_else (and (ge (minus (match_dup 0) (pc))
13479 (lt (minus (match_dup 0) (pc))
13484 (define_insn "*jcc_2"
13486 (if_then_else (match_operator 1 "ix86_comparison_operator"
13487 [(reg 17) (const_int 0)])
13489 (label_ref (match_operand 0 "" ""))))]
13492 [(set_attr "type" "ibr")
13493 (set_attr "modrm" "0")
13494 (set (attr "length")
13495 (if_then_else (and (ge (minus (match_dup 0) (pc))
13497 (lt (minus (match_dup 0) (pc))
13502 ;; In general it is not safe to assume too much about CCmode registers,
13503 ;; so simplify-rtx stops when it sees a second one. Under certain
13504 ;; conditions this is safe on x86, so help combine not create
13512 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13513 [(reg 17) (const_int 0)])
13515 (label_ref (match_operand 1 "" ""))
13519 (if_then_else (match_dup 0)
13520 (label_ref (match_dup 1))
13523 PUT_MODE (operands[0], VOIDmode);
13528 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13529 [(reg 17) (const_int 0)])
13531 (label_ref (match_operand 1 "" ""))
13535 (if_then_else (match_dup 0)
13536 (label_ref (match_dup 1))
13539 rtx new_op0 = copy_rtx (operands[0]);
13540 operands[0] = new_op0;
13541 PUT_MODE (new_op0, VOIDmode);
13542 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13543 GET_MODE (XEXP (new_op0, 0))));
13545 /* Make sure that (a) the CCmode we have for the flags is strong
13546 enough for the reversed compare or (b) we have a valid FP compare. */
13547 if (! ix86_comparison_operator (new_op0, VOIDmode))
13551 ;; Define combination compare-and-branch fp compare instructions to use
13552 ;; during early optimization. Splitting the operation apart early makes
13553 ;; for bad code when we want to reverse the operation.
13555 (define_insn "*fp_jcc_1"
13557 (if_then_else (match_operator 0 "comparison_operator"
13558 [(match_operand 1 "register_operand" "f")
13559 (match_operand 2 "register_operand" "f")])
13560 (label_ref (match_operand 3 "" ""))
13562 (clobber (reg:CCFP 18))
13563 (clobber (reg:CCFP 17))]
13564 "TARGET_CMOVE && TARGET_80387
13565 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13566 && FLOAT_MODE_P (GET_MODE (operands[1]))
13567 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13568 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13571 (define_insn "*fp_jcc_1_sse"
13573 (if_then_else (match_operator 0 "comparison_operator"
13574 [(match_operand 1 "register_operand" "f#x,x#f")
13575 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13576 (label_ref (match_operand 3 "" ""))
13578 (clobber (reg:CCFP 18))
13579 (clobber (reg:CCFP 17))]
13581 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13582 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13583 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13586 (define_insn "*fp_jcc_1_sse_only"
13588 (if_then_else (match_operator 0 "comparison_operator"
13589 [(match_operand 1 "register_operand" "x")
13590 (match_operand 2 "nonimmediate_operand" "xm")])
13591 (label_ref (match_operand 3 "" ""))
13593 (clobber (reg:CCFP 18))
13594 (clobber (reg:CCFP 17))]
13595 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13596 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13597 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13600 (define_insn "*fp_jcc_2"
13602 (if_then_else (match_operator 0 "comparison_operator"
13603 [(match_operand 1 "register_operand" "f")
13604 (match_operand 2 "register_operand" "f")])
13606 (label_ref (match_operand 3 "" ""))))
13607 (clobber (reg:CCFP 18))
13608 (clobber (reg:CCFP 17))]
13609 "TARGET_CMOVE && TARGET_80387
13610 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13611 && FLOAT_MODE_P (GET_MODE (operands[1]))
13612 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13613 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13616 (define_insn "*fp_jcc_2_sse"
13618 (if_then_else (match_operator 0 "comparison_operator"
13619 [(match_operand 1 "register_operand" "f#x,x#f")
13620 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13622 (label_ref (match_operand 3 "" ""))))
13623 (clobber (reg:CCFP 18))
13624 (clobber (reg:CCFP 17))]
13626 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13627 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13628 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13631 (define_insn "*fp_jcc_2_sse_only"
13633 (if_then_else (match_operator 0 "comparison_operator"
13634 [(match_operand 1 "register_operand" "x")
13635 (match_operand 2 "nonimmediate_operand" "xm")])
13637 (label_ref (match_operand 3 "" ""))))
13638 (clobber (reg:CCFP 18))
13639 (clobber (reg:CCFP 17))]
13640 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13641 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13642 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13645 (define_insn "*fp_jcc_3"
13647 (if_then_else (match_operator 0 "comparison_operator"
13648 [(match_operand 1 "register_operand" "f")
13649 (match_operand 2 "nonimmediate_operand" "fm")])
13650 (label_ref (match_operand 3 "" ""))
13652 (clobber (reg:CCFP 18))
13653 (clobber (reg:CCFP 17))
13654 (clobber (match_scratch:HI 4 "=a"))]
13656 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13657 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13658 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13659 && SELECT_CC_MODE (GET_CODE (operands[0]),
13660 operands[1], operands[2]) == CCFPmode
13661 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13664 (define_insn "*fp_jcc_4"
13666 (if_then_else (match_operator 0 "comparison_operator"
13667 [(match_operand 1 "register_operand" "f")
13668 (match_operand 2 "nonimmediate_operand" "fm")])
13670 (label_ref (match_operand 3 "" ""))))
13671 (clobber (reg:CCFP 18))
13672 (clobber (reg:CCFP 17))
13673 (clobber (match_scratch:HI 4 "=a"))]
13675 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13676 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13677 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13678 && SELECT_CC_MODE (GET_CODE (operands[0]),
13679 operands[1], operands[2]) == CCFPmode
13680 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13683 (define_insn "*fp_jcc_5"
13685 (if_then_else (match_operator 0 "comparison_operator"
13686 [(match_operand 1 "register_operand" "f")
13687 (match_operand 2 "register_operand" "f")])
13688 (label_ref (match_operand 3 "" ""))
13690 (clobber (reg:CCFP 18))
13691 (clobber (reg:CCFP 17))
13692 (clobber (match_scratch:HI 4 "=a"))]
13694 && FLOAT_MODE_P (GET_MODE (operands[1]))
13695 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13696 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13699 (define_insn "*fp_jcc_6"
13701 (if_then_else (match_operator 0 "comparison_operator"
13702 [(match_operand 1 "register_operand" "f")
13703 (match_operand 2 "register_operand" "f")])
13705 (label_ref (match_operand 3 "" ""))))
13706 (clobber (reg:CCFP 18))
13707 (clobber (reg:CCFP 17))
13708 (clobber (match_scratch:HI 4 "=a"))]
13710 && FLOAT_MODE_P (GET_MODE (operands[1]))
13711 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13712 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13717 (if_then_else (match_operator 0 "comparison_operator"
13718 [(match_operand 1 "register_operand" "")
13719 (match_operand 2 "nonimmediate_operand" "")])
13720 (match_operand 3 "" "")
13721 (match_operand 4 "" "")))
13722 (clobber (reg:CCFP 18))
13723 (clobber (reg:CCFP 17))]
13727 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13728 operands[3], operands[4], NULL_RTX);
13734 (if_then_else (match_operator 0 "comparison_operator"
13735 [(match_operand 1 "register_operand" "")
13736 (match_operand 2 "nonimmediate_operand" "")])
13737 (match_operand 3 "" "")
13738 (match_operand 4 "" "")))
13739 (clobber (reg:CCFP 18))
13740 (clobber (reg:CCFP 17))
13741 (clobber (match_scratch:HI 5 "=a"))]
13744 (if_then_else (match_dup 6)
13748 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13749 operands[3], operands[4], operands[5]);
13753 ;; Unconditional and other jump instructions
13755 (define_insn "jump"
13757 (label_ref (match_operand 0 "" "")))]
13760 [(set_attr "type" "ibr")
13761 (set (attr "length")
13762 (if_then_else (and (ge (minus (match_dup 0) (pc))
13764 (lt (minus (match_dup 0) (pc))
13768 (set_attr "modrm" "0")])
13770 (define_expand "indirect_jump"
13771 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13775 (define_insn "*indirect_jump"
13776 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13779 [(set_attr "type" "ibr")
13780 (set_attr "length_immediate" "0")])
13782 (define_insn "*indirect_jump_rtx64"
13783 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13786 [(set_attr "type" "ibr")
13787 (set_attr "length_immediate" "0")])
13789 (define_expand "tablejump"
13790 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13791 (use (label_ref (match_operand 1 "" "")))])]
13794 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13795 relative. Convert the relative address to an absolute address. */
13799 enum rtx_code code;
13805 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13807 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13811 op1 = pic_offset_table_rtx;
13816 op0 = pic_offset_table_rtx;
13820 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13825 (define_insn "*tablejump_1"
13826 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13827 (use (label_ref (match_operand 1 "" "")))]
13830 [(set_attr "type" "ibr")
13831 (set_attr "length_immediate" "0")])
13833 (define_insn "*tablejump_1_rtx64"
13834 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13835 (use (label_ref (match_operand 1 "" "")))]
13838 [(set_attr "type" "ibr")
13839 (set_attr "length_immediate" "0")])
13841 ;; Loop instruction
13843 ;; This is all complicated by the fact that since this is a jump insn
13844 ;; we must handle our own reloads.
13846 (define_expand "doloop_end"
13847 [(use (match_operand 0 "" "")) ; loop pseudo
13848 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13849 (use (match_operand 2 "" "")) ; max iterations
13850 (use (match_operand 3 "" "")) ; loop level
13851 (use (match_operand 4 "" ""))] ; label
13852 "!TARGET_64BIT && TARGET_USE_LOOP"
13855 /* Only use cloop on innermost loops. */
13856 if (INTVAL (operands[3]) > 1)
13858 if (GET_MODE (operands[0]) != SImode)
13860 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13865 (define_insn "doloop_end_internal"
13867 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13869 (label_ref (match_operand 0 "" ""))
13871 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13872 (plus:SI (match_dup 1)
13874 (clobber (match_scratch:SI 3 "=X,X,r"))
13875 (clobber (reg:CC 17))]
13876 "!TARGET_64BIT && TARGET_USE_LOOP"
13878 if (which_alternative != 0)
13880 if (get_attr_length (insn) == 2)
13881 return "%+loop\t%l0";
13883 return "dec{l}\t%1\;%+jne\t%l0";
13885 [(set_attr "ppro_uops" "many")
13886 (set (attr "length")
13887 (if_then_else (and (eq_attr "alternative" "0")
13888 (and (ge (minus (match_dup 0) (pc))
13890 (lt (minus (match_dup 0) (pc))
13894 ;; We don't know the type before shorten branches. Optimistically expect
13895 ;; the loop instruction to match.
13896 (set (attr "type") (const_string "ibr"))])
13900 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13902 (match_operand 0 "" "")
13905 (plus:SI (match_dup 1)
13907 (clobber (match_scratch:SI 2 ""))
13908 (clobber (reg:CC 17))]
13909 "!TARGET_64BIT && TARGET_USE_LOOP
13910 && reload_completed
13911 && REGNO (operands[1]) != 2"
13912 [(parallel [(set (reg:CCZ 17)
13913 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13915 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13916 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13923 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13925 (match_operand 0 "" "")
13927 (set (match_operand:SI 2 "nonimmediate_operand" "")
13928 (plus:SI (match_dup 1)
13930 (clobber (match_scratch:SI 3 ""))
13931 (clobber (reg:CC 17))]
13932 "!TARGET_64BIT && TARGET_USE_LOOP
13933 && reload_completed
13934 && (! REG_P (operands[2])
13935 || ! rtx_equal_p (operands[1], operands[2]))"
13936 [(set (match_dup 3) (match_dup 1))
13937 (parallel [(set (reg:CCZ 17)
13938 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13940 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13941 (set (match_dup 2) (match_dup 3))
13942 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13947 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13950 [(set (reg 17) (match_operand 0 "" ""))
13951 (set (match_operand:QI 1 "register_operand" "")
13952 (match_operator:QI 2 "ix86_comparison_operator"
13953 [(reg 17) (const_int 0)]))
13954 (set (match_operand 3 "q_regs_operand" "")
13955 (zero_extend (match_dup 1)))]
13956 "(peep2_reg_dead_p (3, operands[1])
13957 || operands_match_p (operands[1], operands[3]))
13958 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13959 [(set (match_dup 4) (match_dup 0))
13960 (set (strict_low_part (match_dup 5))
13963 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13964 operands[5] = gen_lowpart (QImode, operands[3]);
13965 ix86_expand_clear (operands[3]);
13968 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13971 [(set (reg 17) (match_operand 0 "" ""))
13972 (set (match_operand:QI 1 "register_operand" "")
13973 (match_operator:QI 2 "ix86_comparison_operator"
13974 [(reg 17) (const_int 0)]))
13975 (parallel [(set (match_operand 3 "q_regs_operand" "")
13976 (zero_extend (match_dup 1)))
13977 (clobber (reg:CC 17))])]
13978 "(peep2_reg_dead_p (3, operands[1])
13979 || operands_match_p (operands[1], operands[3]))
13980 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13981 [(set (match_dup 4) (match_dup 0))
13982 (set (strict_low_part (match_dup 5))
13985 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13986 operands[5] = gen_lowpart (QImode, operands[3]);
13987 ix86_expand_clear (operands[3]);
13990 ;; Call instructions.
13992 ;; The predicates normally associated with named expanders are not properly
13993 ;; checked for calls. This is a bug in the generic code, but it isn't that
13994 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13996 ;; Call subroutine returning no value.
13998 (define_expand "call_pop"
13999 [(parallel [(call (match_operand:QI 0 "" "")
14000 (match_operand:SI 1 "" ""))
14002 (plus:SI (reg:SI 7)
14003 (match_operand:SI 3 "" "")))])]
14006 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
14010 (define_insn "*call_pop_0"
14011 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
14012 (match_operand:SI 1 "" ""))
14013 (set (reg:SI 7) (plus:SI (reg:SI 7)
14014 (match_operand:SI 2 "immediate_operand" "")))]
14017 if (SIBLING_CALL_P (insn))
14020 return "call\t%P0";
14022 [(set_attr "type" "call")])
14024 (define_insn "*call_pop_1"
14025 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14026 (match_operand:SI 1 "" ""))
14027 (set (reg:SI 7) (plus:SI (reg:SI 7)
14028 (match_operand:SI 2 "immediate_operand" "i")))]
14031 if (constant_call_address_operand (operands[0], Pmode))
14033 if (SIBLING_CALL_P (insn))
14036 return "call\t%P0";
14038 if (SIBLING_CALL_P (insn))
14041 return "call\t%A0";
14043 [(set_attr "type" "call")])
14045 (define_expand "call"
14046 [(call (match_operand:QI 0 "" "")
14047 (match_operand 1 "" ""))
14048 (use (match_operand 2 "" ""))]
14051 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
14055 (define_expand "sibcall"
14056 [(call (match_operand:QI 0 "" "")
14057 (match_operand 1 "" ""))
14058 (use (match_operand 2 "" ""))]
14061 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
14065 (define_insn "*call_0"
14066 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
14067 (match_operand 1 "" ""))]
14070 if (SIBLING_CALL_P (insn))
14073 return "call\t%P0";
14075 [(set_attr "type" "call")])
14077 (define_insn "*call_1"
14078 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14079 (match_operand 1 "" ""))]
14080 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
14082 if (constant_call_address_operand (operands[0], QImode))
14083 return "call\t%P0";
14084 return "call\t%A0";
14086 [(set_attr "type" "call")])
14088 (define_insn "*sibcall_1"
14089 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
14090 (match_operand 1 "" ""))]
14091 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
14093 if (constant_call_address_operand (operands[0], QImode))
14097 [(set_attr "type" "call")])
14099 (define_insn "*call_1_rex64"
14100 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
14101 (match_operand 1 "" ""))]
14102 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
14104 if (constant_call_address_operand (operands[0], QImode))
14105 return "call\t%P0";
14106 return "call\t%A0";
14108 [(set_attr "type" "call")])
14110 (define_insn "*sibcall_1_rex64"
14111 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
14112 (match_operand 1 "" ""))]
14113 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14115 [(set_attr "type" "call")])
14117 (define_insn "*sibcall_1_rex64_v"
14118 [(call (mem:QI (reg:DI 40))
14119 (match_operand 0 "" ""))]
14120 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14122 [(set_attr "type" "call")])
14125 ;; Call subroutine, returning value in operand 0
14127 (define_expand "call_value_pop"
14128 [(parallel [(set (match_operand 0 "" "")
14129 (call (match_operand:QI 1 "" "")
14130 (match_operand:SI 2 "" "")))
14132 (plus:SI (reg:SI 7)
14133 (match_operand:SI 4 "" "")))])]
14136 ix86_expand_call (operands[0], operands[1], operands[2],
14137 operands[3], operands[4], 0);
14141 (define_expand "call_value"
14142 [(set (match_operand 0 "" "")
14143 (call (match_operand:QI 1 "" "")
14144 (match_operand:SI 2 "" "")))
14145 (use (match_operand:SI 3 "" ""))]
14146 ;; Operand 2 not used on the i386.
14149 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
14153 (define_expand "sibcall_value"
14154 [(set (match_operand 0 "" "")
14155 (call (match_operand:QI 1 "" "")
14156 (match_operand:SI 2 "" "")))
14157 (use (match_operand:SI 3 "" ""))]
14158 ;; Operand 2 not used on the i386.
14161 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
14165 ;; Call subroutine returning any type.
14167 (define_expand "untyped_call"
14168 [(parallel [(call (match_operand 0 "" "")
14170 (match_operand 1 "" "")
14171 (match_operand 2 "" "")])]
14176 /* In order to give reg-stack an easier job in validating two
14177 coprocessor registers as containing a possible return value,
14178 simply pretend the untyped call returns a complex long double
14181 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
14182 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
14183 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
14186 for (i = 0; i < XVECLEN (operands[2], 0); i++)
14188 rtx set = XVECEXP (operands[2], 0, i);
14189 emit_move_insn (SET_DEST (set), SET_SRC (set));
14192 /* The optimizer does not know that the call sets the function value
14193 registers we stored in the result block. We avoid problems by
14194 claiming that all hard registers are used and clobbered at this
14196 emit_insn (gen_blockage (const0_rtx));
14201 ;; Prologue and epilogue instructions
14203 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
14204 ;; all of memory. This blocks insns from being moved across this point.
14206 (define_insn "blockage"
14207 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
14210 [(set_attr "length" "0")])
14212 ;; Insn emitted into the body of a function to return from a function.
14213 ;; This is only done if the function's epilogue is known to be simple.
14214 ;; See comments for ix86_can_use_return_insn_p in i386.c.
14216 (define_expand "return"
14218 "ix86_can_use_return_insn_p ()"
14220 if (current_function_pops_args)
14222 rtx popc = GEN_INT (current_function_pops_args);
14223 emit_jump_insn (gen_return_pop_internal (popc));
14228 (define_insn "return_internal"
14232 [(set_attr "length" "1")
14233 (set_attr "length_immediate" "0")
14234 (set_attr "modrm" "0")])
14236 (define_insn "return_pop_internal"
14238 (use (match_operand:SI 0 "const_int_operand" ""))]
14241 [(set_attr "length" "3")
14242 (set_attr "length_immediate" "2")
14243 (set_attr "modrm" "0")])
14245 (define_insn "return_indirect_internal"
14247 (use (match_operand:SI 0 "register_operand" "r"))]
14250 [(set_attr "type" "ibr")
14251 (set_attr "length_immediate" "0")])
14257 [(set_attr "length" "1")
14258 (set_attr "length_immediate" "0")
14259 (set_attr "modrm" "0")
14260 (set_attr "ppro_uops" "one")])
14262 (define_expand "prologue"
14265 "ix86_expand_prologue (); DONE;")
14267 (define_insn "set_got"
14268 [(set (match_operand:SI 0 "register_operand" "=r")
14269 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
14270 (clobber (reg:CC 17))]
14272 { return output_set_got (operands[0]); }
14273 [(set_attr "type" "multi")
14274 (set_attr "length" "12")])
14276 (define_expand "epilogue"
14279 "ix86_expand_epilogue (1); DONE;")
14281 (define_expand "sibcall_epilogue"
14284 "ix86_expand_epilogue (0); DONE;")
14286 (define_expand "eh_return"
14287 [(use (match_operand 0 "register_operand" ""))
14288 (use (match_operand 1 "register_operand" ""))]
14291 rtx tmp, sa = operands[0], ra = operands[1];
14293 /* Tricky bit: we write the address of the handler to which we will
14294 be returning into someone else's stack frame, one word below the
14295 stack address we wish to restore. */
14296 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
14297 tmp = plus_constant (tmp, -UNITS_PER_WORD);
14298 tmp = gen_rtx_MEM (Pmode, tmp);
14299 emit_move_insn (tmp, ra);
14301 if (Pmode == SImode)
14302 emit_insn (gen_eh_return_si (sa));
14304 emit_insn (gen_eh_return_di (sa));
14309 (define_insn_and_split "eh_return_si"
14310 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
14311 UNSPECV_EH_RETURN)]
14316 "ix86_expand_epilogue (2); DONE;")
14318 (define_insn_and_split "eh_return_di"
14319 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
14320 UNSPECV_EH_RETURN)]
14325 "ix86_expand_epilogue (2); DONE;")
14327 (define_insn "leave"
14328 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
14329 (set (reg:SI 6) (mem:SI (reg:SI 6)))
14330 (clobber (mem:BLK (scratch)))]
14333 [(set_attr "type" "leave")])
14335 (define_insn "leave_rex64"
14336 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
14337 (set (reg:DI 6) (mem:DI (reg:DI 6)))
14338 (clobber (mem:BLK (scratch)))]
14341 [(set_attr "type" "leave")])
14343 (define_expand "ffssi2"
14345 [(set (match_operand:SI 0 "register_operand" "")
14346 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
14347 (clobber (match_scratch:SI 2 ""))
14348 (clobber (reg:CC 17))])]
14352 (define_insn_and_split "*ffs_cmove"
14353 [(set (match_operand:SI 0 "register_operand" "=r")
14354 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14355 (clobber (match_scratch:SI 2 "=&r"))
14356 (clobber (reg:CC 17))]
14359 "&& reload_completed"
14360 [(set (match_dup 2) (const_int -1))
14361 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14362 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14363 (set (match_dup 0) (if_then_else:SI
14364 (eq (reg:CCZ 17) (const_int 0))
14367 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14368 (clobber (reg:CC 17))])]
14371 (define_insn_and_split "*ffs_no_cmove"
14372 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14373 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14374 (clobber (match_scratch:SI 2 "=&r"))
14375 (clobber (reg:CC 17))]
14379 [(parallel [(set (match_dup 2) (const_int 0))
14380 (clobber (reg:CC 17))])
14381 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14382 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14383 (set (strict_low_part (match_dup 3))
14384 (eq:QI (reg:CCZ 17) (const_int 0)))
14385 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14386 (clobber (reg:CC 17))])
14387 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14388 (clobber (reg:CC 17))])
14389 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14390 (clobber (reg:CC 17))])]
14392 operands[3] = gen_lowpart (QImode, operands[2]);
14395 (define_insn "*ffssi_1"
14397 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14399 (set (match_operand:SI 0 "register_operand" "=r")
14400 (ctz:SI (match_dup 1)))]
14402 "bsf{l}\t{%1, %0|%0, %1}"
14403 [(set_attr "prefix_0f" "1")
14404 (set_attr "ppro_uops" "few")])
14406 (define_insn "ctzsi2"
14407 [(set (match_operand:SI 0 "register_operand" "=r")
14408 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14409 (clobber (reg:CC 17))]
14411 "bsf{l}\t{%1, %0|%0, %1}"
14412 [(set_attr "prefix_0f" "1")
14413 (set_attr "ppro_uops" "few")])
14415 (define_expand "clzsi2"
14417 [(set (match_operand:SI 0 "register_operand" "")
14418 (minus:SI (const_int 31)
14419 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14420 (clobber (reg:CC 17))])
14422 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14423 (clobber (reg:CC 17))])]
14427 (define_insn "*bsr"
14428 [(set (match_operand:SI 0 "register_operand" "=r")
14429 (minus:SI (const_int 31)
14430 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14431 (clobber (reg:CC 17))]
14433 "bsr{l}\t{%1, %0|%0, %1}"
14434 [(set_attr "prefix_0f" "1")
14435 (set_attr "ppro_uops" "few")])
14437 ;; Thread-local storage patterns for ELF.
14439 ;; Note that these code sequences must appear exactly as shown
14440 ;; in order to allow linker relaxation.
14442 (define_insn "*tls_global_dynamic_32_gnu"
14443 [(set (match_operand:SI 0 "register_operand" "=a")
14444 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14445 (match_operand:SI 2 "tls_symbolic_operand" "")
14446 (match_operand:SI 3 "call_insn_operand" "")]
14448 (clobber (match_scratch:SI 4 "=d"))
14449 (clobber (match_scratch:SI 5 "=c"))
14450 (clobber (reg:CC 17))]
14451 "!TARGET_64BIT && TARGET_GNU_TLS"
14452 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14453 [(set_attr "type" "multi")
14454 (set_attr "length" "12")])
14456 (define_insn "*tls_global_dynamic_32_sun"
14457 [(set (match_operand:SI 0 "register_operand" "=a")
14458 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14459 (match_operand:SI 2 "tls_symbolic_operand" "")
14460 (match_operand:SI 3 "call_insn_operand" "")]
14462 (clobber (match_scratch:SI 4 "=d"))
14463 (clobber (match_scratch:SI 5 "=c"))
14464 (clobber (reg:CC 17))]
14465 "!TARGET_64BIT && TARGET_SUN_TLS"
14466 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14467 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14468 [(set_attr "type" "multi")
14469 (set_attr "length" "14")])
14471 (define_expand "tls_global_dynamic_32"
14472 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14475 (match_operand:SI 1 "tls_symbolic_operand" "")
14478 (clobber (match_scratch:SI 4 ""))
14479 (clobber (match_scratch:SI 5 ""))
14480 (clobber (reg:CC 17))])]
14484 operands[2] = pic_offset_table_rtx;
14487 operands[2] = gen_reg_rtx (Pmode);
14488 emit_insn (gen_set_got (operands[2]));
14490 operands[3] = ix86_tls_get_addr ();
14493 (define_insn "*tls_global_dynamic_64"
14494 [(set (match_operand:DI 0 "register_operand" "=a")
14495 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14496 (match_operand:DI 3 "" "")))
14497 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14500 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14501 [(set_attr "type" "multi")
14502 (set_attr "length" "16")])
14504 (define_expand "tls_global_dynamic_64"
14505 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14506 (call (mem:QI (match_dup 2)) (const_int 0)))
14507 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14511 operands[2] = ix86_tls_get_addr ();
14514 (define_insn "*tls_local_dynamic_base_32_gnu"
14515 [(set (match_operand:SI 0 "register_operand" "=a")
14516 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14517 (match_operand:SI 2 "call_insn_operand" "")]
14518 UNSPEC_TLS_LD_BASE))
14519 (clobber (match_scratch:SI 3 "=d"))
14520 (clobber (match_scratch:SI 4 "=c"))
14521 (clobber (reg:CC 17))]
14522 "!TARGET_64BIT && TARGET_GNU_TLS"
14523 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14524 [(set_attr "type" "multi")
14525 (set_attr "length" "11")])
14527 (define_insn "*tls_local_dynamic_base_32_sun"
14528 [(set (match_operand:SI 0 "register_operand" "=a")
14529 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14530 (match_operand:SI 2 "call_insn_operand" "")]
14531 UNSPEC_TLS_LD_BASE))
14532 (clobber (match_scratch:SI 3 "=d"))
14533 (clobber (match_scratch:SI 4 "=c"))
14534 (clobber (reg:CC 17))]
14535 "!TARGET_64BIT && TARGET_SUN_TLS"
14536 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14537 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14538 [(set_attr "type" "multi")
14539 (set_attr "length" "13")])
14541 (define_expand "tls_local_dynamic_base_32"
14542 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14543 (unspec:SI [(match_dup 1) (match_dup 2)]
14544 UNSPEC_TLS_LD_BASE))
14545 (clobber (match_scratch:SI 3 ""))
14546 (clobber (match_scratch:SI 4 ""))
14547 (clobber (reg:CC 17))])]
14551 operands[1] = pic_offset_table_rtx;
14554 operands[1] = gen_reg_rtx (Pmode);
14555 emit_insn (gen_set_got (operands[1]));
14557 operands[2] = ix86_tls_get_addr ();
14560 (define_insn "*tls_local_dynamic_base_64"
14561 [(set (match_operand:DI 0 "register_operand" "=a")
14562 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14563 (match_operand:DI 2 "" "")))
14564 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14566 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14567 [(set_attr "type" "multi")
14568 (set_attr "length" "12")])
14570 (define_expand "tls_local_dynamic_base_64"
14571 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14572 (call (mem:QI (match_dup 1)) (const_int 0)))
14573 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14576 operands[1] = ix86_tls_get_addr ();
14579 ;; Local dynamic of a single variable is a lose. Show combine how
14580 ;; to convert that back to global dynamic.
14582 (define_insn_and_split "*tls_local_dynamic_32_once"
14583 [(set (match_operand:SI 0 "register_operand" "=a")
14584 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14585 (match_operand:SI 2 "call_insn_operand" "")]
14586 UNSPEC_TLS_LD_BASE)
14587 (const:SI (unspec:SI
14588 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14590 (clobber (match_scratch:SI 4 "=d"))
14591 (clobber (match_scratch:SI 5 "=c"))
14592 (clobber (reg:CC 17))]
14596 [(parallel [(set (match_dup 0)
14597 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14599 (clobber (match_dup 4))
14600 (clobber (match_dup 5))
14601 (clobber (reg:CC 17))])]
14604 ;; These patterns match the binary 387 instructions for addM3, subM3,
14605 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14606 ;; SFmode. The first is the normal insn, the second the same insn but
14607 ;; with one operand a conversion, and the third the same insn but with
14608 ;; the other operand a conversion. The conversion may be SFmode or
14609 ;; SImode if the target mode DFmode, but only SImode if the target mode
14612 ;; Gcc is slightly more smart about handling normal two address instructions
14613 ;; so use special patterns for add and mull.
14614 (define_insn "*fop_sf_comm_nosse"
14615 [(set (match_operand:SF 0 "register_operand" "=f")
14616 (match_operator:SF 3 "binary_fp_operator"
14617 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14618 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14619 "TARGET_80387 && !TARGET_SSE_MATH
14620 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14621 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14622 "* return output_387_binary_op (insn, operands);"
14623 [(set (attr "type")
14624 (if_then_else (match_operand:SF 3 "mult_operator" "")
14625 (const_string "fmul")
14626 (const_string "fop")))
14627 (set_attr "mode" "SF")])
14629 (define_insn "*fop_sf_comm"
14630 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14631 (match_operator:SF 3 "binary_fp_operator"
14632 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14633 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14634 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14635 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14636 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14637 "* return output_387_binary_op (insn, operands);"
14638 [(set (attr "type")
14639 (if_then_else (eq_attr "alternative" "1")
14640 (if_then_else (match_operand:SF 3 "mult_operator" "")
14641 (const_string "ssemul")
14642 (const_string "sseadd"))
14643 (if_then_else (match_operand:SF 3 "mult_operator" "")
14644 (const_string "fmul")
14645 (const_string "fop"))))
14646 (set_attr "mode" "SF")])
14648 (define_insn "*fop_sf_comm_sse"
14649 [(set (match_operand:SF 0 "register_operand" "=x")
14650 (match_operator:SF 3 "binary_fp_operator"
14651 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14652 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14653 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14654 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14655 "* return output_387_binary_op (insn, operands);"
14656 [(set (attr "type")
14657 (if_then_else (match_operand:SF 3 "mult_operator" "")
14658 (const_string "ssemul")
14659 (const_string "sseadd")))
14660 (set_attr "mode" "SF")])
14662 (define_insn "*fop_df_comm_nosse"
14663 [(set (match_operand:DF 0 "register_operand" "=f")
14664 (match_operator:DF 3 "binary_fp_operator"
14665 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14666 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14667 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14668 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14669 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14670 "* return output_387_binary_op (insn, operands);"
14671 [(set (attr "type")
14672 (if_then_else (match_operand:SF 3 "mult_operator" "")
14673 (const_string "fmul")
14674 (const_string "fop")))
14675 (set_attr "mode" "DF")])
14677 (define_insn "*fop_df_comm"
14678 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14679 (match_operator:DF 3 "binary_fp_operator"
14680 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14681 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14682 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14683 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14684 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14685 "* return output_387_binary_op (insn, operands);"
14686 [(set (attr "type")
14687 (if_then_else (eq_attr "alternative" "1")
14688 (if_then_else (match_operand:SF 3 "mult_operator" "")
14689 (const_string "ssemul")
14690 (const_string "sseadd"))
14691 (if_then_else (match_operand:SF 3 "mult_operator" "")
14692 (const_string "fmul")
14693 (const_string "fop"))))
14694 (set_attr "mode" "DF")])
14696 (define_insn "*fop_df_comm_sse"
14697 [(set (match_operand:DF 0 "register_operand" "=Y")
14698 (match_operator:DF 3 "binary_fp_operator"
14699 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14700 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14701 "TARGET_SSE2 && TARGET_SSE_MATH
14702 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14703 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14704 "* return output_387_binary_op (insn, operands);"
14705 [(set (attr "type")
14706 (if_then_else (match_operand:SF 3 "mult_operator" "")
14707 (const_string "ssemul")
14708 (const_string "sseadd")))
14709 (set_attr "mode" "DF")])
14711 (define_insn "*fop_xf_comm"
14712 [(set (match_operand:XF 0 "register_operand" "=f")
14713 (match_operator:XF 3 "binary_fp_operator"
14714 [(match_operand:XF 1 "register_operand" "%0")
14715 (match_operand:XF 2 "register_operand" "f")]))]
14716 "!TARGET_64BIT && TARGET_80387
14717 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14718 "* return output_387_binary_op (insn, operands);"
14719 [(set (attr "type")
14720 (if_then_else (match_operand:XF 3 "mult_operator" "")
14721 (const_string "fmul")
14722 (const_string "fop")))
14723 (set_attr "mode" "XF")])
14725 (define_insn "*fop_tf_comm"
14726 [(set (match_operand:TF 0 "register_operand" "=f")
14727 (match_operator:TF 3 "binary_fp_operator"
14728 [(match_operand:TF 1 "register_operand" "%0")
14729 (match_operand:TF 2 "register_operand" "f")]))]
14730 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14731 "* return output_387_binary_op (insn, operands);"
14732 [(set (attr "type")
14733 (if_then_else (match_operand:TF 3 "mult_operator" "")
14734 (const_string "fmul")
14735 (const_string "fop")))
14736 (set_attr "mode" "XF")])
14738 (define_insn "*fop_sf_1_nosse"
14739 [(set (match_operand:SF 0 "register_operand" "=f,f")
14740 (match_operator:SF 3 "binary_fp_operator"
14741 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14742 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14743 "TARGET_80387 && !TARGET_SSE_MATH
14744 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14745 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14746 "* return output_387_binary_op (insn, operands);"
14747 [(set (attr "type")
14748 (cond [(match_operand:SF 3 "mult_operator" "")
14749 (const_string "fmul")
14750 (match_operand:SF 3 "div_operator" "")
14751 (const_string "fdiv")
14753 (const_string "fop")))
14754 (set_attr "mode" "SF")])
14756 (define_insn "*fop_sf_1"
14757 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14758 (match_operator:SF 3 "binary_fp_operator"
14759 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14760 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14761 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14762 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14763 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14764 "* return output_387_binary_op (insn, operands);"
14765 [(set (attr "type")
14766 (cond [(and (eq_attr "alternative" "2")
14767 (match_operand:SF 3 "mult_operator" ""))
14768 (const_string "ssemul")
14769 (and (eq_attr "alternative" "2")
14770 (match_operand:SF 3 "div_operator" ""))
14771 (const_string "ssediv")
14772 (eq_attr "alternative" "2")
14773 (const_string "sseadd")
14774 (match_operand:SF 3 "mult_operator" "")
14775 (const_string "fmul")
14776 (match_operand:SF 3 "div_operator" "")
14777 (const_string "fdiv")
14779 (const_string "fop")))
14780 (set_attr "mode" "SF")])
14782 (define_insn "*fop_sf_1_sse"
14783 [(set (match_operand:SF 0 "register_operand" "=x")
14784 (match_operator:SF 3 "binary_fp_operator"
14785 [(match_operand:SF 1 "register_operand" "0")
14786 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14788 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14789 "* return output_387_binary_op (insn, operands);"
14790 [(set (attr "type")
14791 (cond [(match_operand:SF 3 "mult_operator" "")
14792 (const_string "ssemul")
14793 (match_operand:SF 3 "div_operator" "")
14794 (const_string "ssediv")
14796 (const_string "sseadd")))
14797 (set_attr "mode" "SF")])
14799 ;; ??? Add SSE splitters for these!
14800 (define_insn "*fop_sf_2"
14801 [(set (match_operand:SF 0 "register_operand" "=f,f")
14802 (match_operator:SF 3 "binary_fp_operator"
14803 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14804 (match_operand:SF 2 "register_operand" "0,0")]))]
14805 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14806 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14807 [(set (attr "type")
14808 (cond [(match_operand:SF 3 "mult_operator" "")
14809 (const_string "fmul")
14810 (match_operand:SF 3 "div_operator" "")
14811 (const_string "fdiv")
14813 (const_string "fop")))
14814 (set_attr "fp_int_src" "true")
14815 (set_attr "ppro_uops" "many")
14816 (set_attr "mode" "SI")])
14818 (define_insn "*fop_sf_3"
14819 [(set (match_operand:SF 0 "register_operand" "=f,f")
14820 (match_operator:SF 3 "binary_fp_operator"
14821 [(match_operand:SF 1 "register_operand" "0,0")
14822 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14823 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14824 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14825 [(set (attr "type")
14826 (cond [(match_operand:SF 3 "mult_operator" "")
14827 (const_string "fmul")
14828 (match_operand:SF 3 "div_operator" "")
14829 (const_string "fdiv")
14831 (const_string "fop")))
14832 (set_attr "fp_int_src" "true")
14833 (set_attr "ppro_uops" "many")
14834 (set_attr "mode" "SI")])
14836 (define_insn "*fop_df_1_nosse"
14837 [(set (match_operand:DF 0 "register_operand" "=f,f")
14838 (match_operator:DF 3 "binary_fp_operator"
14839 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14840 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14841 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14842 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14843 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14844 "* return output_387_binary_op (insn, operands);"
14845 [(set (attr "type")
14846 (cond [(match_operand:DF 3 "mult_operator" "")
14847 (const_string "fmul")
14848 (match_operand:DF 3 "div_operator" "")
14849 (const_string "fdiv")
14851 (const_string "fop")))
14852 (set_attr "mode" "DF")])
14855 (define_insn "*fop_df_1"
14856 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14857 (match_operator:DF 3 "binary_fp_operator"
14858 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14859 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14860 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14861 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14862 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14863 "* return output_387_binary_op (insn, operands);"
14864 [(set (attr "type")
14865 (cond [(and (eq_attr "alternative" "2")
14866 (match_operand:SF 3 "mult_operator" ""))
14867 (const_string "ssemul")
14868 (and (eq_attr "alternative" "2")
14869 (match_operand:SF 3 "div_operator" ""))
14870 (const_string "ssediv")
14871 (eq_attr "alternative" "2")
14872 (const_string "sseadd")
14873 (match_operand:DF 3 "mult_operator" "")
14874 (const_string "fmul")
14875 (match_operand:DF 3 "div_operator" "")
14876 (const_string "fdiv")
14878 (const_string "fop")))
14879 (set_attr "mode" "DF")])
14881 (define_insn "*fop_df_1_sse"
14882 [(set (match_operand:DF 0 "register_operand" "=Y")
14883 (match_operator:DF 3 "binary_fp_operator"
14884 [(match_operand:DF 1 "register_operand" "0")
14885 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14886 "TARGET_SSE2 && TARGET_SSE_MATH
14887 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14888 "* return output_387_binary_op (insn, operands);"
14889 [(set_attr "mode" "DF")
14891 (cond [(match_operand:SF 3 "mult_operator" "")
14892 (const_string "ssemul")
14893 (match_operand:SF 3 "div_operator" "")
14894 (const_string "ssediv")
14896 (const_string "sseadd")))])
14898 ;; ??? Add SSE splitters for these!
14899 (define_insn "*fop_df_2"
14900 [(set (match_operand:DF 0 "register_operand" "=f,f")
14901 (match_operator:DF 3 "binary_fp_operator"
14902 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14903 (match_operand:DF 2 "register_operand" "0,0")]))]
14904 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14905 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14906 [(set (attr "type")
14907 (cond [(match_operand:DF 3 "mult_operator" "")
14908 (const_string "fmul")
14909 (match_operand:DF 3 "div_operator" "")
14910 (const_string "fdiv")
14912 (const_string "fop")))
14913 (set_attr "fp_int_src" "true")
14914 (set_attr "ppro_uops" "many")
14915 (set_attr "mode" "SI")])
14917 (define_insn "*fop_df_3"
14918 [(set (match_operand:DF 0 "register_operand" "=f,f")
14919 (match_operator:DF 3 "binary_fp_operator"
14920 [(match_operand:DF 1 "register_operand" "0,0")
14921 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14922 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14923 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14924 [(set (attr "type")
14925 (cond [(match_operand:DF 3 "mult_operator" "")
14926 (const_string "fmul")
14927 (match_operand:DF 3 "div_operator" "")
14928 (const_string "fdiv")
14930 (const_string "fop")))
14931 (set_attr "fp_int_src" "true")
14932 (set_attr "ppro_uops" "many")
14933 (set_attr "mode" "SI")])
14935 (define_insn "*fop_df_4"
14936 [(set (match_operand:DF 0 "register_operand" "=f,f")
14937 (match_operator:DF 3 "binary_fp_operator"
14938 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14939 (match_operand:DF 2 "register_operand" "0,f")]))]
14940 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14941 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14942 "* return output_387_binary_op (insn, operands);"
14943 [(set (attr "type")
14944 (cond [(match_operand:DF 3 "mult_operator" "")
14945 (const_string "fmul")
14946 (match_operand:DF 3 "div_operator" "")
14947 (const_string "fdiv")
14949 (const_string "fop")))
14950 (set_attr "mode" "SF")])
14952 (define_insn "*fop_df_5"
14953 [(set (match_operand:DF 0 "register_operand" "=f,f")
14954 (match_operator:DF 3 "binary_fp_operator"
14955 [(match_operand:DF 1 "register_operand" "0,f")
14957 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14958 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14959 "* return output_387_binary_op (insn, operands);"
14960 [(set (attr "type")
14961 (cond [(match_operand:DF 3 "mult_operator" "")
14962 (const_string "fmul")
14963 (match_operand:DF 3 "div_operator" "")
14964 (const_string "fdiv")
14966 (const_string "fop")))
14967 (set_attr "mode" "SF")])
14969 (define_insn "*fop_df_6"
14970 [(set (match_operand:DF 0 "register_operand" "=f,f")
14971 (match_operator:DF 3 "binary_fp_operator"
14973 (match_operand:SF 1 "register_operand" "0,f"))
14975 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14976 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14977 "* return output_387_binary_op (insn, operands);"
14978 [(set (attr "type")
14979 (cond [(match_operand:DF 3 "mult_operator" "")
14980 (const_string "fmul")
14981 (match_operand:DF 3 "div_operator" "")
14982 (const_string "fdiv")
14984 (const_string "fop")))
14985 (set_attr "mode" "SF")])
14987 (define_insn "*fop_xf_1"
14988 [(set (match_operand:XF 0 "register_operand" "=f,f")
14989 (match_operator:XF 3 "binary_fp_operator"
14990 [(match_operand:XF 1 "register_operand" "0,f")
14991 (match_operand:XF 2 "register_operand" "f,0")]))]
14992 "!TARGET_64BIT && TARGET_80387
14993 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14994 "* return output_387_binary_op (insn, operands);"
14995 [(set (attr "type")
14996 (cond [(match_operand:XF 3 "mult_operator" "")
14997 (const_string "fmul")
14998 (match_operand:XF 3 "div_operator" "")
14999 (const_string "fdiv")
15001 (const_string "fop")))
15002 (set_attr "mode" "XF")])
15004 (define_insn "*fop_tf_1"
15005 [(set (match_operand:TF 0 "register_operand" "=f,f")
15006 (match_operator:TF 3 "binary_fp_operator"
15007 [(match_operand:TF 1 "register_operand" "0,f")
15008 (match_operand:TF 2 "register_operand" "f,0")]))]
15010 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15011 "* return output_387_binary_op (insn, operands);"
15012 [(set (attr "type")
15013 (cond [(match_operand:TF 3 "mult_operator" "")
15014 (const_string "fmul")
15015 (match_operand:TF 3 "div_operator" "")
15016 (const_string "fdiv")
15018 (const_string "fop")))
15019 (set_attr "mode" "XF")])
15021 (define_insn "*fop_xf_2"
15022 [(set (match_operand:XF 0 "register_operand" "=f,f")
15023 (match_operator:XF 3 "binary_fp_operator"
15024 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15025 (match_operand:XF 2 "register_operand" "0,0")]))]
15026 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15027 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15028 [(set (attr "type")
15029 (cond [(match_operand:XF 3 "mult_operator" "")
15030 (const_string "fmul")
15031 (match_operand:XF 3 "div_operator" "")
15032 (const_string "fdiv")
15034 (const_string "fop")))
15035 (set_attr "fp_int_src" "true")
15036 (set_attr "mode" "SI")
15037 (set_attr "ppro_uops" "many")])
15039 (define_insn "*fop_tf_2"
15040 [(set (match_operand:TF 0 "register_operand" "=f,f")
15041 (match_operator:TF 3 "binary_fp_operator"
15042 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15043 (match_operand:TF 2 "register_operand" "0,0")]))]
15044 "TARGET_80387 && TARGET_USE_FIOP"
15045 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15046 [(set (attr "type")
15047 (cond [(match_operand:TF 3 "mult_operator" "")
15048 (const_string "fmul")
15049 (match_operand:TF 3 "div_operator" "")
15050 (const_string "fdiv")
15052 (const_string "fop")))
15053 (set_attr "fp_int_src" "true")
15054 (set_attr "mode" "SI")
15055 (set_attr "ppro_uops" "many")])
15057 (define_insn "*fop_xf_3"
15058 [(set (match_operand:XF 0 "register_operand" "=f,f")
15059 (match_operator:XF 3 "binary_fp_operator"
15060 [(match_operand:XF 1 "register_operand" "0,0")
15061 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15062 "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
15063 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15064 [(set (attr "type")
15065 (cond [(match_operand:XF 3 "mult_operator" "")
15066 (const_string "fmul")
15067 (match_operand:XF 3 "div_operator" "")
15068 (const_string "fdiv")
15070 (const_string "fop")))
15071 (set_attr "fp_int_src" "true")
15072 (set_attr "mode" "SI")
15073 (set_attr "ppro_uops" "many")])
15075 (define_insn "*fop_tf_3"
15076 [(set (match_operand:TF 0 "register_operand" "=f,f")
15077 (match_operator:TF 3 "binary_fp_operator"
15078 [(match_operand:TF 1 "register_operand" "0,0")
15079 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15080 "TARGET_80387 && TARGET_USE_FIOP"
15081 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15082 [(set (attr "type")
15083 (cond [(match_operand:TF 3 "mult_operator" "")
15084 (const_string "fmul")
15085 (match_operand:TF 3 "div_operator" "")
15086 (const_string "fdiv")
15088 (const_string "fop")))
15089 (set_attr "fp_int_src" "true")
15090 (set_attr "mode" "SI")
15091 (set_attr "ppro_uops" "many")])
15093 (define_insn "*fop_xf_4"
15094 [(set (match_operand:XF 0 "register_operand" "=f,f")
15095 (match_operator:XF 3 "binary_fp_operator"
15096 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
15097 (match_operand:XF 2 "register_operand" "0,f")]))]
15098 "!TARGET_64BIT && TARGET_80387"
15099 "* return output_387_binary_op (insn, operands);"
15100 [(set (attr "type")
15101 (cond [(match_operand:XF 3 "mult_operator" "")
15102 (const_string "fmul")
15103 (match_operand:XF 3 "div_operator" "")
15104 (const_string "fdiv")
15106 (const_string "fop")))
15107 (set_attr "mode" "SF")])
15109 (define_insn "*fop_tf_4"
15110 [(set (match_operand:TF 0 "register_operand" "=f,f")
15111 (match_operator:TF 3 "binary_fp_operator"
15112 [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
15113 (match_operand:TF 2 "register_operand" "0,f")]))]
15115 "* return output_387_binary_op (insn, operands);"
15116 [(set (attr "type")
15117 (cond [(match_operand:TF 3 "mult_operator" "")
15118 (const_string "fmul")
15119 (match_operand:TF 3 "div_operator" "")
15120 (const_string "fdiv")
15122 (const_string "fop")))
15123 (set_attr "mode" "SF")])
15125 (define_insn "*fop_xf_5"
15126 [(set (match_operand:XF 0 "register_operand" "=f,f")
15127 (match_operator:XF 3 "binary_fp_operator"
15128 [(match_operand:XF 1 "register_operand" "0,f")
15130 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15131 "!TARGET_64BIT && TARGET_80387"
15132 "* return output_387_binary_op (insn, operands);"
15133 [(set (attr "type")
15134 (cond [(match_operand:XF 3 "mult_operator" "")
15135 (const_string "fmul")
15136 (match_operand:XF 3 "div_operator" "")
15137 (const_string "fdiv")
15139 (const_string "fop")))
15140 (set_attr "mode" "SF")])
15142 (define_insn "*fop_tf_5"
15143 [(set (match_operand:TF 0 "register_operand" "=f,f")
15144 (match_operator:TF 3 "binary_fp_operator"
15145 [(match_operand:TF 1 "register_operand" "0,f")
15147 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15149 "* return output_387_binary_op (insn, operands);"
15150 [(set (attr "type")
15151 (cond [(match_operand:TF 3 "mult_operator" "")
15152 (const_string "fmul")
15153 (match_operand:TF 3 "div_operator" "")
15154 (const_string "fdiv")
15156 (const_string "fop")))
15157 (set_attr "mode" "SF")])
15159 (define_insn "*fop_xf_6"
15160 [(set (match_operand:XF 0 "register_operand" "=f,f")
15161 (match_operator:XF 3 "binary_fp_operator"
15163 (match_operand 1 "register_operand" "0,f"))
15165 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15166 "!TARGET_64BIT && TARGET_80387"
15167 "* return output_387_binary_op (insn, operands);"
15168 [(set (attr "type")
15169 (cond [(match_operand:XF 3 "mult_operator" "")
15170 (const_string "fmul")
15171 (match_operand:XF 3 "div_operator" "")
15172 (const_string "fdiv")
15174 (const_string "fop")))
15175 (set_attr "mode" "SF")])
15177 (define_insn "*fop_tf_6"
15178 [(set (match_operand:TF 0 "register_operand" "=f,f")
15179 (match_operator:TF 3 "binary_fp_operator"
15181 (match_operand 1 "register_operand" "0,f"))
15183 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15185 "* return output_387_binary_op (insn, operands);"
15186 [(set (attr "type")
15187 (cond [(match_operand:TF 3 "mult_operator" "")
15188 (const_string "fmul")
15189 (match_operand:TF 3 "div_operator" "")
15190 (const_string "fdiv")
15192 (const_string "fop")))
15193 (set_attr "mode" "SF")])
15196 [(set (match_operand 0 "register_operand" "")
15197 (match_operator 3 "binary_fp_operator"
15198 [(float (match_operand:SI 1 "register_operand" ""))
15199 (match_operand 2 "register_operand" "")]))]
15200 "TARGET_80387 && reload_completed
15201 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15204 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
15205 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15206 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15207 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15208 GET_MODE (operands[3]),
15211 ix86_free_from_memory (GET_MODE (operands[1]));
15216 [(set (match_operand 0 "register_operand" "")
15217 (match_operator 3 "binary_fp_operator"
15218 [(match_operand 1 "register_operand" "")
15219 (float (match_operand:SI 2 "register_operand" ""))]))]
15220 "TARGET_80387 && reload_completed
15221 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15224 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
15225 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15226 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15227 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15228 GET_MODE (operands[3]),
15231 ix86_free_from_memory (GET_MODE (operands[2]));
15235 ;; FPU special functions.
15237 (define_expand "sqrtsf2"
15238 [(set (match_operand:SF 0 "register_operand" "")
15239 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
15240 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
15242 if (!TARGET_SSE_MATH)
15243 operands[1] = force_reg (SFmode, operands[1]);
15246 (define_insn "sqrtsf2_1"
15247 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
15248 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
15249 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15250 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15253 sqrtss\t{%1, %0|%0, %1}"
15254 [(set_attr "type" "fpspc,sse")
15255 (set_attr "mode" "SF,SF")
15256 (set_attr "athlon_decode" "direct,*")])
15258 (define_insn "sqrtsf2_1_sse_only"
15259 [(set (match_operand:SF 0 "register_operand" "=x")
15260 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
15261 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15262 "sqrtss\t{%1, %0|%0, %1}"
15263 [(set_attr "type" "sse")
15264 (set_attr "mode" "SF")
15265 (set_attr "athlon_decode" "*")])
15267 (define_insn "sqrtsf2_i387"
15268 [(set (match_operand:SF 0 "register_operand" "=f")
15269 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
15270 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15271 && !TARGET_SSE_MATH"
15273 [(set_attr "type" "fpspc")
15274 (set_attr "mode" "SF")
15275 (set_attr "athlon_decode" "direct")])
15277 (define_expand "sqrtdf2"
15278 [(set (match_operand:DF 0 "register_operand" "")
15279 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
15280 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
15281 || (TARGET_SSE2 && TARGET_SSE_MATH)"
15283 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
15284 operands[1] = force_reg (DFmode, operands[1]);
15287 (define_insn "sqrtdf2_1"
15288 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
15289 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
15290 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15291 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15294 sqrtsd\t{%1, %0|%0, %1}"
15295 [(set_attr "type" "fpspc,sse")
15296 (set_attr "mode" "DF,DF")
15297 (set_attr "athlon_decode" "direct,*")])
15299 (define_insn "sqrtdf2_1_sse_only"
15300 [(set (match_operand:DF 0 "register_operand" "=Y")
15301 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
15302 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15303 "sqrtsd\t{%1, %0|%0, %1}"
15304 [(set_attr "type" "sse")
15305 (set_attr "mode" "DF")
15306 (set_attr "athlon_decode" "*")])
15308 (define_insn "sqrtdf2_i387"
15309 [(set (match_operand:DF 0 "register_operand" "=f")
15310 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
15311 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15312 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
15314 [(set_attr "type" "fpspc")
15315 (set_attr "mode" "DF")
15316 (set_attr "athlon_decode" "direct")])
15318 (define_insn "*sqrtextendsfdf2"
15319 [(set (match_operand:DF 0 "register_operand" "=f")
15320 (sqrt:DF (float_extend:DF
15321 (match_operand:SF 1 "register_operand" "0"))))]
15322 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15323 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15325 [(set_attr "type" "fpspc")
15326 (set_attr "mode" "DF")
15327 (set_attr "athlon_decode" "direct")])
15329 (define_insn "sqrtxf2"
15330 [(set (match_operand:XF 0 "register_operand" "=f")
15331 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
15332 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15333 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15335 [(set_attr "type" "fpspc")
15336 (set_attr "mode" "XF")
15337 (set_attr "athlon_decode" "direct")])
15339 (define_insn "sqrttf2"
15340 [(set (match_operand:TF 0 "register_operand" "=f")
15341 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
15342 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15343 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15345 [(set_attr "type" "fpspc")
15346 (set_attr "mode" "XF")
15347 (set_attr "athlon_decode" "direct")])
15349 (define_insn "*sqrtextenddfxf2"
15350 [(set (match_operand:XF 0 "register_operand" "=f")
15351 (sqrt:XF (float_extend:XF
15352 (match_operand:DF 1 "register_operand" "0"))))]
15353 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15355 [(set_attr "type" "fpspc")
15356 (set_attr "mode" "XF")
15357 (set_attr "athlon_decode" "direct")])
15359 (define_insn "*sqrtextenddftf2"
15360 [(set (match_operand:TF 0 "register_operand" "=f")
15361 (sqrt:TF (float_extend:TF
15362 (match_operand:DF 1 "register_operand" "0"))))]
15363 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15365 [(set_attr "type" "fpspc")
15366 (set_attr "mode" "XF")
15367 (set_attr "athlon_decode" "direct")])
15369 (define_insn "*sqrtextendsfxf2"
15370 [(set (match_operand:XF 0 "register_operand" "=f")
15371 (sqrt:XF (float_extend:XF
15372 (match_operand:SF 1 "register_operand" "0"))))]
15373 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15375 [(set_attr "type" "fpspc")
15376 (set_attr "mode" "XF")
15377 (set_attr "athlon_decode" "direct")])
15379 (define_insn "*sqrtextendsftf2"
15380 [(set (match_operand:TF 0 "register_operand" "=f")
15381 (sqrt:TF (float_extend:TF
15382 (match_operand:SF 1 "register_operand" "0"))))]
15383 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15385 [(set_attr "type" "fpspc")
15386 (set_attr "mode" "XF")
15387 (set_attr "athlon_decode" "direct")])
15389 (define_insn "sindf2"
15390 [(set (match_operand:DF 0 "register_operand" "=f")
15391 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15392 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15393 && flag_unsafe_math_optimizations"
15395 [(set_attr "type" "fpspc")
15396 (set_attr "mode" "DF")])
15398 (define_insn "sinsf2"
15399 [(set (match_operand:SF 0 "register_operand" "=f")
15400 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15401 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15402 && flag_unsafe_math_optimizations"
15404 [(set_attr "type" "fpspc")
15405 (set_attr "mode" "SF")])
15407 (define_insn "*sinextendsfdf2"
15408 [(set (match_operand:DF 0 "register_operand" "=f")
15409 (unspec:DF [(float_extend:DF
15410 (match_operand:SF 1 "register_operand" "0"))]
15412 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15413 && flag_unsafe_math_optimizations"
15415 [(set_attr "type" "fpspc")
15416 (set_attr "mode" "DF")])
15418 (define_insn "sinxf2"
15419 [(set (match_operand:XF 0 "register_operand" "=f")
15420 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15421 "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15422 && flag_unsafe_math_optimizations"
15424 [(set_attr "type" "fpspc")
15425 (set_attr "mode" "XF")])
15427 (define_insn "sintf2"
15428 [(set (match_operand:TF 0 "register_operand" "=f")
15429 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
15430 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15431 && flag_unsafe_math_optimizations"
15433 [(set_attr "type" "fpspc")
15434 (set_attr "mode" "XF")])
15436 (define_insn "cosdf2"
15437 [(set (match_operand:DF 0 "register_operand" "=f")
15438 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15439 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15440 && flag_unsafe_math_optimizations"
15442 [(set_attr "type" "fpspc")
15443 (set_attr "mode" "DF")])
15445 (define_insn "cossf2"
15446 [(set (match_operand:SF 0 "register_operand" "=f")
15447 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15448 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15449 && flag_unsafe_math_optimizations"
15451 [(set_attr "type" "fpspc")
15452 (set_attr "mode" "SF")])
15454 (define_insn "*cosextendsfdf2"
15455 [(set (match_operand:DF 0 "register_operand" "=f")
15456 (unspec:DF [(float_extend:DF
15457 (match_operand:SF 1 "register_operand" "0"))]
15459 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15460 && flag_unsafe_math_optimizations"
15462 [(set_attr "type" "fpspc")
15463 (set_attr "mode" "DF")])
15465 (define_insn "cosxf2"
15466 [(set (match_operand:XF 0 "register_operand" "=f")
15467 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15468 "!TARGET_64BIT && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15469 && flag_unsafe_math_optimizations"
15471 [(set_attr "type" "fpspc")
15472 (set_attr "mode" "XF")])
15474 (define_insn "costf2"
15475 [(set (match_operand:TF 0 "register_operand" "=f")
15476 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
15477 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15478 && flag_unsafe_math_optimizations"
15480 [(set_attr "type" "fpspc")
15481 (set_attr "mode" "XF")])
15483 (define_insn "atan2df3"
15484 [(set (match_operand:DF 0 "register_operand" "=f")
15485 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15486 (match_operand:DF 1 "register_operand" "u")]
15488 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15489 && flag_unsafe_math_optimizations"
15491 [(set_attr "type" "fpspc")
15492 (set_attr "mode" "DF")])
15494 (define_insn "atan2sf3"
15495 [(set (match_operand:SF 0 "register_operand" "=f")
15496 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15497 (match_operand:SF 1 "register_operand" "u")]
15499 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15500 && flag_unsafe_math_optimizations"
15502 [(set_attr "type" "fpspc")
15503 (set_attr "mode" "SF")])
15505 (define_insn "atan2xf3"
15506 [(set (match_operand:XF 0 "register_operand" "=f")
15507 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15508 (match_operand:XF 1 "register_operand" "u")]
15510 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15511 && flag_unsafe_math_optimizations"
15513 [(set_attr "type" "fpspc")
15514 (set_attr "mode" "XF")])
15516 (define_insn "atan2tf3"
15517 [(set (match_operand:TF 0 "register_operand" "=f")
15518 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15519 (match_operand:TF 1 "register_operand" "u")]
15521 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15522 && flag_unsafe_math_optimizations"
15524 [(set_attr "type" "fpspc")
15525 (set_attr "mode" "XF")])
15527 ;; Block operation instructions
15530 [(set (reg:SI 19) (const_int 0))]
15533 [(set_attr "type" "cld")])
15535 (define_expand "movstrsi"
15536 [(use (match_operand:BLK 0 "memory_operand" ""))
15537 (use (match_operand:BLK 1 "memory_operand" ""))
15538 (use (match_operand:SI 2 "nonmemory_operand" ""))
15539 (use (match_operand:SI 3 "const_int_operand" ""))]
15542 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15548 (define_expand "movstrdi"
15549 [(use (match_operand:BLK 0 "memory_operand" ""))
15550 (use (match_operand:BLK 1 "memory_operand" ""))
15551 (use (match_operand:DI 2 "nonmemory_operand" ""))
15552 (use (match_operand:DI 3 "const_int_operand" ""))]
15555 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15561 ;; Most CPUs don't like single string operations
15562 ;; Handle this case here to simplify previous expander.
15564 (define_expand "strmovdi_rex64"
15565 [(set (match_dup 2)
15566 (mem:DI (match_operand:DI 1 "register_operand" "")))
15567 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
15569 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15570 (clobber (reg:CC 17))])
15571 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
15572 (clobber (reg:CC 17))])]
15575 if (TARGET_SINGLE_STRINGOP || optimize_size)
15577 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
15582 operands[2] = gen_reg_rtx (DImode);
15586 (define_expand "strmovsi"
15587 [(set (match_dup 2)
15588 (mem:SI (match_operand:SI 1 "register_operand" "")))
15589 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
15591 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15592 (clobber (reg:CC 17))])
15593 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
15594 (clobber (reg:CC 17))])]
15599 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
15602 if (TARGET_SINGLE_STRINGOP || optimize_size)
15604 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
15609 operands[2] = gen_reg_rtx (SImode);
15612 (define_expand "strmovsi_rex64"
15613 [(set (match_dup 2)
15614 (mem:SI (match_operand:DI 1 "register_operand" "")))
15615 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
15617 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15618 (clobber (reg:CC 17))])
15619 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
15620 (clobber (reg:CC 17))])]
15623 if (TARGET_SINGLE_STRINGOP || optimize_size)
15625 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
15630 operands[2] = gen_reg_rtx (SImode);
15633 (define_expand "strmovhi"
15634 [(set (match_dup 2)
15635 (mem:HI (match_operand:SI 1 "register_operand" "")))
15636 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
15638 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
15639 (clobber (reg:CC 17))])
15640 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
15641 (clobber (reg:CC 17))])]
15646 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
15649 if (TARGET_SINGLE_STRINGOP || optimize_size)
15651 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
15656 operands[2] = gen_reg_rtx (HImode);
15659 (define_expand "strmovhi_rex64"
15660 [(set (match_dup 2)
15661 (mem:HI (match_operand:DI 1 "register_operand" "")))
15662 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
15664 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
15665 (clobber (reg:CC 17))])
15666 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
15667 (clobber (reg:CC 17))])]
15670 if (TARGET_SINGLE_STRINGOP || optimize_size)
15672 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
15677 operands[2] = gen_reg_rtx (HImode);
15680 (define_expand "strmovqi"
15681 [(set (match_dup 2)
15682 (mem:QI (match_operand:SI 1 "register_operand" "")))
15683 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
15685 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
15686 (clobber (reg:CC 17))])
15687 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
15688 (clobber (reg:CC 17))])]
15693 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
15696 if (TARGET_SINGLE_STRINGOP || optimize_size)
15698 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
15703 operands[2] = gen_reg_rtx (QImode);
15706 (define_expand "strmovqi_rex64"
15707 [(set (match_dup 2)
15708 (mem:QI (match_operand:DI 1 "register_operand" "")))
15709 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
15711 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
15712 (clobber (reg:CC 17))])
15713 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
15714 (clobber (reg:CC 17))])]
15717 if (TARGET_SINGLE_STRINGOP || optimize_size)
15719 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
15724 operands[2] = gen_reg_rtx (QImode);
15727 (define_insn "strmovdi_rex_1"
15728 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
15729 (mem:DI (match_operand:DI 3 "register_operand" "1")))
15730 (set (match_operand:DI 0 "register_operand" "=D")
15731 (plus:DI (match_dup 2)
15733 (set (match_operand:DI 1 "register_operand" "=S")
15734 (plus:DI (match_dup 3)
15737 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15739 [(set_attr "type" "str")
15740 (set_attr "mode" "DI")
15741 (set_attr "memory" "both")])
15743 (define_insn "strmovsi_1"
15744 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
15745 (mem:SI (match_operand:SI 3 "register_operand" "1")))
15746 (set (match_operand:SI 0 "register_operand" "=D")
15747 (plus:SI (match_dup 2)
15749 (set (match_operand:SI 1 "register_operand" "=S")
15750 (plus:SI (match_dup 3)
15753 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15755 [(set_attr "type" "str")
15756 (set_attr "mode" "SI")
15757 (set_attr "memory" "both")])
15759 (define_insn "strmovsi_rex_1"
15760 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
15761 (mem:SI (match_operand:DI 3 "register_operand" "1")))
15762 (set (match_operand:DI 0 "register_operand" "=D")
15763 (plus:DI (match_dup 2)
15765 (set (match_operand:DI 1 "register_operand" "=S")
15766 (plus:DI (match_dup 3)
15769 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15771 [(set_attr "type" "str")
15772 (set_attr "mode" "SI")
15773 (set_attr "memory" "both")])
15775 (define_insn "strmovhi_1"
15776 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
15777 (mem:HI (match_operand:SI 3 "register_operand" "1")))
15778 (set (match_operand:SI 0 "register_operand" "=D")
15779 (plus:SI (match_dup 2)
15781 (set (match_operand:SI 1 "register_operand" "=S")
15782 (plus:SI (match_dup 3)
15785 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15787 [(set_attr "type" "str")
15788 (set_attr "memory" "both")
15789 (set_attr "mode" "HI")])
15791 (define_insn "strmovhi_rex_1"
15792 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
15793 (mem:HI (match_operand:DI 3 "register_operand" "1")))
15794 (set (match_operand:DI 0 "register_operand" "=D")
15795 (plus:DI (match_dup 2)
15797 (set (match_operand:DI 1 "register_operand" "=S")
15798 (plus:DI (match_dup 3)
15801 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15803 [(set_attr "type" "str")
15804 (set_attr "memory" "both")
15805 (set_attr "mode" "HI")])
15807 (define_insn "strmovqi_1"
15808 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
15809 (mem:QI (match_operand:SI 3 "register_operand" "1")))
15810 (set (match_operand:SI 0 "register_operand" "=D")
15811 (plus:SI (match_dup 2)
15813 (set (match_operand:SI 1 "register_operand" "=S")
15814 (plus:SI (match_dup 3)
15817 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15819 [(set_attr "type" "str")
15820 (set_attr "memory" "both")
15821 (set_attr "mode" "QI")])
15823 (define_insn "strmovqi_rex_1"
15824 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
15825 (mem:QI (match_operand:DI 3 "register_operand" "1")))
15826 (set (match_operand:DI 0 "register_operand" "=D")
15827 (plus:DI (match_dup 2)
15829 (set (match_operand:DI 1 "register_operand" "=S")
15830 (plus:DI (match_dup 3)
15833 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
15835 [(set_attr "type" "str")
15836 (set_attr "memory" "both")
15837 (set_attr "mode" "QI")])
15839 (define_insn "rep_movdi_rex64"
15840 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15841 (set (match_operand:DI 0 "register_operand" "=D")
15842 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15844 (match_operand:DI 3 "register_operand" "0")))
15845 (set (match_operand:DI 1 "register_operand" "=S")
15846 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
15847 (match_operand:DI 4 "register_operand" "1")))
15848 (set (mem:BLK (match_dup 3))
15849 (mem:BLK (match_dup 4)))
15850 (use (match_dup 5))
15853 "{rep\;movsq|rep movsq}"
15854 [(set_attr "type" "str")
15855 (set_attr "prefix_rep" "1")
15856 (set_attr "memory" "both")
15857 (set_attr "mode" "DI")])
15859 (define_insn "rep_movsi"
15860 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15861 (set (match_operand:SI 0 "register_operand" "=D")
15862 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
15864 (match_operand:SI 3 "register_operand" "0")))
15865 (set (match_operand:SI 1 "register_operand" "=S")
15866 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
15867 (match_operand:SI 4 "register_operand" "1")))
15868 (set (mem:BLK (match_dup 3))
15869 (mem:BLK (match_dup 4)))
15870 (use (match_dup 5))
15873 "{rep\;movsl|rep movsd}"
15874 [(set_attr "type" "str")
15875 (set_attr "prefix_rep" "1")
15876 (set_attr "memory" "both")
15877 (set_attr "mode" "SI")])
15879 (define_insn "rep_movsi_rex64"
15880 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15881 (set (match_operand:DI 0 "register_operand" "=D")
15882 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
15884 (match_operand:DI 3 "register_operand" "0")))
15885 (set (match_operand:DI 1 "register_operand" "=S")
15886 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
15887 (match_operand:DI 4 "register_operand" "1")))
15888 (set (mem:BLK (match_dup 3))
15889 (mem:BLK (match_dup 4)))
15890 (use (match_dup 5))
15893 "{rep\;movsl|rep movsd}"
15894 [(set_attr "type" "str")
15895 (set_attr "prefix_rep" "1")
15896 (set_attr "memory" "both")
15897 (set_attr "mode" "SI")])
15899 (define_insn "rep_movqi"
15900 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
15901 (set (match_operand:SI 0 "register_operand" "=D")
15902 (plus:SI (match_operand:SI 3 "register_operand" "0")
15903 (match_operand:SI 5 "register_operand" "2")))
15904 (set (match_operand:SI 1 "register_operand" "=S")
15905 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
15906 (set (mem:BLK (match_dup 3))
15907 (mem:BLK (match_dup 4)))
15908 (use (match_dup 5))
15911 "{rep\;movsb|rep movsb}"
15912 [(set_attr "type" "str")
15913 (set_attr "prefix_rep" "1")
15914 (set_attr "memory" "both")
15915 (set_attr "mode" "SI")])
15917 (define_insn "rep_movqi_rex64"
15918 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
15919 (set (match_operand:DI 0 "register_operand" "=D")
15920 (plus:DI (match_operand:DI 3 "register_operand" "0")
15921 (match_operand:DI 5 "register_operand" "2")))
15922 (set (match_operand:DI 1 "register_operand" "=S")
15923 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
15924 (set (mem:BLK (match_dup 3))
15925 (mem:BLK (match_dup 4)))
15926 (use (match_dup 5))
15929 "{rep\;movsb|rep movsb}"
15930 [(set_attr "type" "str")
15931 (set_attr "prefix_rep" "1")
15932 (set_attr "memory" "both")
15933 (set_attr "mode" "SI")])
15935 (define_expand "clrstrsi"
15936 [(use (match_operand:BLK 0 "memory_operand" ""))
15937 (use (match_operand:SI 1 "nonmemory_operand" ""))
15938 (use (match_operand 2 "const_int_operand" ""))]
15941 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15947 (define_expand "clrstrdi"
15948 [(use (match_operand:BLK 0 "memory_operand" ""))
15949 (use (match_operand:DI 1 "nonmemory_operand" ""))
15950 (use (match_operand 2 "const_int_operand" ""))]
15953 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
15959 ;; Most CPUs don't like single string operations
15960 ;; Handle this case here to simplify previous expander.
15962 (define_expand "strsetdi_rex64"
15963 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
15964 (match_operand:DI 1 "register_operand" ""))
15965 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15966 (clobber (reg:CC 17))])]
15969 if (TARGET_SINGLE_STRINGOP || optimize_size)
15971 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
15976 (define_expand "strsetsi"
15977 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
15978 (match_operand:SI 1 "register_operand" ""))
15979 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15980 (clobber (reg:CC 17))])]
15985 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
15988 else if (TARGET_SINGLE_STRINGOP || optimize_size)
15990 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
15995 (define_expand "strsetsi_rex64"
15996 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
15997 (match_operand:SI 1 "register_operand" ""))
15998 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
15999 (clobber (reg:CC 17))])]
16002 if (TARGET_SINGLE_STRINGOP || optimize_size)
16004 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
16009 (define_expand "strsethi"
16010 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
16011 (match_operand:HI 1 "register_operand" ""))
16012 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
16013 (clobber (reg:CC 17))])]
16018 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
16021 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16023 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
16028 (define_expand "strsethi_rex64"
16029 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
16030 (match_operand:HI 1 "register_operand" ""))
16031 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
16032 (clobber (reg:CC 17))])]
16035 if (TARGET_SINGLE_STRINGOP || optimize_size)
16037 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
16042 (define_expand "strsetqi"
16043 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
16044 (match_operand:QI 1 "register_operand" ""))
16045 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
16046 (clobber (reg:CC 17))])]
16051 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
16054 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16056 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
16061 (define_expand "strsetqi_rex64"
16062 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
16063 (match_operand:QI 1 "register_operand" ""))
16064 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
16065 (clobber (reg:CC 17))])]
16068 if (TARGET_SINGLE_STRINGOP || optimize_size)
16070 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
16075 (define_insn "strsetdi_rex_1"
16076 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16077 (match_operand:SI 2 "register_operand" "a"))
16078 (set (match_operand:DI 0 "register_operand" "=D")
16079 (plus:DI (match_dup 1)
16082 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16084 [(set_attr "type" "str")
16085 (set_attr "memory" "store")
16086 (set_attr "mode" "DI")])
16088 (define_insn "strsetsi_1"
16089 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16090 (match_operand:SI 2 "register_operand" "a"))
16091 (set (match_operand:SI 0 "register_operand" "=D")
16092 (plus:SI (match_dup 1)
16095 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16097 [(set_attr "type" "str")
16098 (set_attr "memory" "store")
16099 (set_attr "mode" "SI")])
16101 (define_insn "strsetsi_rex_1"
16102 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16103 (match_operand:SI 2 "register_operand" "a"))
16104 (set (match_operand:DI 0 "register_operand" "=D")
16105 (plus:DI (match_dup 1)
16108 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16110 [(set_attr "type" "str")
16111 (set_attr "memory" "store")
16112 (set_attr "mode" "SI")])
16114 (define_insn "strsethi_1"
16115 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16116 (match_operand:HI 2 "register_operand" "a"))
16117 (set (match_operand:SI 0 "register_operand" "=D")
16118 (plus:SI (match_dup 1)
16121 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16123 [(set_attr "type" "str")
16124 (set_attr "memory" "store")
16125 (set_attr "mode" "HI")])
16127 (define_insn "strsethi_rex_1"
16128 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16129 (match_operand:HI 2 "register_operand" "a"))
16130 (set (match_operand:DI 0 "register_operand" "=D")
16131 (plus:DI (match_dup 1)
16134 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16136 [(set_attr "type" "str")
16137 (set_attr "memory" "store")
16138 (set_attr "mode" "HI")])
16140 (define_insn "strsetqi_1"
16141 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16142 (match_operand:QI 2 "register_operand" "a"))
16143 (set (match_operand:SI 0 "register_operand" "=D")
16144 (plus:SI (match_dup 1)
16147 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16149 [(set_attr "type" "str")
16150 (set_attr "memory" "store")
16151 (set_attr "mode" "QI")])
16153 (define_insn "strsetqi_rex_1"
16154 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16155 (match_operand:QI 2 "register_operand" "a"))
16156 (set (match_operand:DI 0 "register_operand" "=D")
16157 (plus:DI (match_dup 1)
16160 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16162 [(set_attr "type" "str")
16163 (set_attr "memory" "store")
16164 (set_attr "mode" "QI")])
16166 (define_insn "rep_stosdi_rex64"
16167 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16168 (set (match_operand:DI 0 "register_operand" "=D")
16169 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16171 (match_operand:DI 3 "register_operand" "0")))
16172 (set (mem:BLK (match_dup 3))
16174 (use (match_operand:DI 2 "register_operand" "a"))
16175 (use (match_dup 4))
16178 "{rep\;stosq|rep stosq}"
16179 [(set_attr "type" "str")
16180 (set_attr "prefix_rep" "1")
16181 (set_attr "memory" "store")
16182 (set_attr "mode" "DI")])
16184 (define_insn "rep_stossi"
16185 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16186 (set (match_operand:SI 0 "register_operand" "=D")
16187 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16189 (match_operand:SI 3 "register_operand" "0")))
16190 (set (mem:BLK (match_dup 3))
16192 (use (match_operand:SI 2 "register_operand" "a"))
16193 (use (match_dup 4))
16196 "{rep\;stosl|rep stosd}"
16197 [(set_attr "type" "str")
16198 (set_attr "prefix_rep" "1")
16199 (set_attr "memory" "store")
16200 (set_attr "mode" "SI")])
16202 (define_insn "rep_stossi_rex64"
16203 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16204 (set (match_operand:DI 0 "register_operand" "=D")
16205 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16207 (match_operand:DI 3 "register_operand" "0")))
16208 (set (mem:BLK (match_dup 3))
16210 (use (match_operand:SI 2 "register_operand" "a"))
16211 (use (match_dup 4))
16214 "{rep\;stosl|rep stosd}"
16215 [(set_attr "type" "str")
16216 (set_attr "prefix_rep" "1")
16217 (set_attr "memory" "store")
16218 (set_attr "mode" "SI")])
16220 (define_insn "rep_stosqi"
16221 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16222 (set (match_operand:SI 0 "register_operand" "=D")
16223 (plus:SI (match_operand:SI 3 "register_operand" "0")
16224 (match_operand:SI 4 "register_operand" "1")))
16225 (set (mem:BLK (match_dup 3))
16227 (use (match_operand:QI 2 "register_operand" "a"))
16228 (use (match_dup 4))
16231 "{rep\;stosb|rep stosb}"
16232 [(set_attr "type" "str")
16233 (set_attr "prefix_rep" "1")
16234 (set_attr "memory" "store")
16235 (set_attr "mode" "QI")])
16237 (define_insn "rep_stosqi_rex64"
16238 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16239 (set (match_operand:DI 0 "register_operand" "=D")
16240 (plus:DI (match_operand:DI 3 "register_operand" "0")
16241 (match_operand:DI 4 "register_operand" "1")))
16242 (set (mem:BLK (match_dup 3))
16244 (use (match_operand:QI 2 "register_operand" "a"))
16245 (use (match_dup 4))
16248 "{rep\;stosb|rep stosb}"
16249 [(set_attr "type" "str")
16250 (set_attr "prefix_rep" "1")
16251 (set_attr "memory" "store")
16252 (set_attr "mode" "QI")])
16254 (define_expand "cmpstrsi"
16255 [(set (match_operand:SI 0 "register_operand" "")
16256 (compare:SI (match_operand:BLK 1 "general_operand" "")
16257 (match_operand:BLK 2 "general_operand" "")))
16258 (use (match_operand 3 "general_operand" ""))
16259 (use (match_operand 4 "immediate_operand" ""))]
16262 rtx addr1, addr2, out, outlow, count, countreg, align;
16264 /* Can't use this if the user has appropriated esi or edi. */
16265 if (global_regs[4] || global_regs[5])
16269 if (GET_CODE (out) != REG)
16270 out = gen_reg_rtx (SImode);
16272 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16273 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16275 count = operands[3];
16276 countreg = ix86_zero_extend_to_Pmode (count);
16278 /* %%% Iff we are testing strict equality, we can use known alignment
16279 to good advantage. This may be possible with combine, particularly
16280 once cc0 is dead. */
16281 align = operands[4];
16283 emit_insn (gen_cld ());
16284 if (GET_CODE (count) == CONST_INT)
16286 if (INTVAL (count) == 0)
16288 emit_move_insn (operands[0], const0_rtx);
16292 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
16293 addr1, addr2, countreg));
16295 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
16296 addr1, addr2, countreg));
16302 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
16303 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
16304 addr1, addr2, countreg));
16308 emit_insn (gen_cmpsi_1 (countreg, countreg));
16309 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
16310 addr1, addr2, countreg));
16314 outlow = gen_lowpart (QImode, out);
16315 emit_insn (gen_cmpintqi (outlow));
16316 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16318 if (operands[0] != out)
16319 emit_move_insn (operands[0], out);
16324 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16326 (define_expand "cmpintqi"
16327 [(set (match_dup 1)
16328 (gtu:QI (reg:CC 17) (const_int 0)))
16330 (ltu:QI (reg:CC 17) (const_int 0)))
16331 (parallel [(set (match_operand:QI 0 "register_operand" "")
16332 (minus:QI (match_dup 1)
16334 (clobber (reg:CC 17))])]
16336 "operands[1] = gen_reg_rtx (QImode);
16337 operands[2] = gen_reg_rtx (QImode);")
16339 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16340 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16342 (define_insn "cmpstrqi_nz_1"
16344 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16345 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
16346 (use (match_operand:SI 6 "register_operand" "2"))
16347 (use (match_operand:SI 3 "immediate_operand" "i"))
16349 (clobber (match_operand:SI 0 "register_operand" "=S"))
16350 (clobber (match_operand:SI 1 "register_operand" "=D"))
16351 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16354 [(set_attr "type" "str")
16355 (set_attr "mode" "QI")
16356 (set_attr "prefix_rep" "1")])
16358 (define_insn "cmpstrqi_nz_rex_1"
16360 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16361 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
16362 (use (match_operand:DI 6 "register_operand" "2"))
16363 (use (match_operand:SI 3 "immediate_operand" "i"))
16365 (clobber (match_operand:DI 0 "register_operand" "=S"))
16366 (clobber (match_operand:DI 1 "register_operand" "=D"))
16367 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16370 [(set_attr "type" "str")
16371 (set_attr "mode" "QI")
16372 (set_attr "prefix_rep" "1")])
16374 ;; The same, but the count is not known to not be zero.
16376 (define_insn "cmpstrqi_1"
16378 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16380 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16381 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16383 (use (match_operand:SI 3 "immediate_operand" "i"))
16386 (clobber (match_operand:SI 0 "register_operand" "=S"))
16387 (clobber (match_operand:SI 1 "register_operand" "=D"))
16388 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16391 [(set_attr "type" "str")
16392 (set_attr "mode" "QI")
16393 (set_attr "prefix_rep" "1")])
16395 (define_insn "cmpstrqi_rex_1"
16397 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16399 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16400 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16402 (use (match_operand:SI 3 "immediate_operand" "i"))
16405 (clobber (match_operand:DI 0 "register_operand" "=S"))
16406 (clobber (match_operand:DI 1 "register_operand" "=D"))
16407 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16410 [(set_attr "type" "str")
16411 (set_attr "mode" "QI")
16412 (set_attr "prefix_rep" "1")])
16414 (define_expand "strlensi"
16415 [(set (match_operand:SI 0 "register_operand" "")
16416 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16417 (match_operand:QI 2 "immediate_operand" "")
16418 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16421 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16427 (define_expand "strlendi"
16428 [(set (match_operand:DI 0 "register_operand" "")
16429 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16430 (match_operand:QI 2 "immediate_operand" "")
16431 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16434 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16440 (define_insn "strlenqi_1"
16441 [(set (match_operand:SI 0 "register_operand" "=&c")
16442 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16443 (match_operand:QI 2 "register_operand" "a")
16444 (match_operand:SI 3 "immediate_operand" "i")
16445 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16447 (clobber (match_operand:SI 1 "register_operand" "=D"))
16448 (clobber (reg:CC 17))]
16451 [(set_attr "type" "str")
16452 (set_attr "mode" "QI")
16453 (set_attr "prefix_rep" "1")])
16455 (define_insn "strlenqi_rex_1"
16456 [(set (match_operand:DI 0 "register_operand" "=&c")
16457 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16458 (match_operand:QI 2 "register_operand" "a")
16459 (match_operand:DI 3 "immediate_operand" "i")
16460 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16462 (clobber (match_operand:DI 1 "register_operand" "=D"))
16463 (clobber (reg:CC 17))]
16466 [(set_attr "type" "str")
16467 (set_attr "mode" "QI")
16468 (set_attr "prefix_rep" "1")])
16470 ;; Peephole optimizations to clean up after cmpstr*. This should be
16471 ;; handled in combine, but it is not currently up to the task.
16472 ;; When used for their truth value, the cmpstr* expanders generate
16481 ;; The intermediate three instructions are unnecessary.
16483 ;; This one handles cmpstr*_nz_1...
16487 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16488 (mem:BLK (match_operand 5 "register_operand" ""))))
16489 (use (match_operand 6 "register_operand" ""))
16490 (use (match_operand:SI 3 "immediate_operand" ""))
16492 (clobber (match_operand 0 "register_operand" ""))
16493 (clobber (match_operand 1 "register_operand" ""))
16494 (clobber (match_operand 2 "register_operand" ""))])
16495 (set (match_operand:QI 7 "register_operand" "")
16496 (gtu:QI (reg:CC 17) (const_int 0)))
16497 (set (match_operand:QI 8 "register_operand" "")
16498 (ltu:QI (reg:CC 17) (const_int 0)))
16500 (compare (match_dup 7) (match_dup 8)))
16502 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16505 (compare:CC (mem:BLK (match_dup 4))
16506 (mem:BLK (match_dup 5))))
16507 (use (match_dup 6))
16508 (use (match_dup 3))
16510 (clobber (match_dup 0))
16511 (clobber (match_dup 1))
16512 (clobber (match_dup 2))])]
16515 ;; ...and this one handles cmpstr*_1.
16519 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16521 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16522 (mem:BLK (match_operand 5 "register_operand" "")))
16524 (use (match_operand:SI 3 "immediate_operand" ""))
16527 (clobber (match_operand 0 "register_operand" ""))
16528 (clobber (match_operand 1 "register_operand" ""))
16529 (clobber (match_operand 2 "register_operand" ""))])
16530 (set (match_operand:QI 7 "register_operand" "")
16531 (gtu:QI (reg:CC 17) (const_int 0)))
16532 (set (match_operand:QI 8 "register_operand" "")
16533 (ltu:QI (reg:CC 17) (const_int 0)))
16535 (compare (match_dup 7) (match_dup 8)))
16537 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16540 (if_then_else:CC (ne (match_dup 6)
16542 (compare:CC (mem:BLK (match_dup 4))
16543 (mem:BLK (match_dup 5)))
16545 (use (match_dup 3))
16548 (clobber (match_dup 0))
16549 (clobber (match_dup 1))
16550 (clobber (match_dup 2))])]
16555 ;; Conditional move instructions.
16557 (define_expand "movdicc"
16558 [(set (match_operand:DI 0 "register_operand" "")
16559 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16560 (match_operand:DI 2 "general_operand" "")
16561 (match_operand:DI 3 "general_operand" "")))]
16563 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16565 (define_insn "x86_movdicc_0_m1_rex64"
16566 [(set (match_operand:DI 0 "register_operand" "=r")
16567 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16570 (clobber (reg:CC 17))]
16573 ; Since we don't have the proper number of operands for an alu insn,
16574 ; fill in all the blanks.
16575 [(set_attr "type" "alu")
16576 (set_attr "pent_pair" "pu")
16577 (set_attr "memory" "none")
16578 (set_attr "imm_disp" "false")
16579 (set_attr "mode" "DI")
16580 (set_attr "length_immediate" "0")])
16582 (define_insn "movdicc_c_rex64"
16583 [(set (match_operand:DI 0 "register_operand" "=r,r")
16584 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16585 [(reg 17) (const_int 0)])
16586 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16587 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16588 "TARGET_64BIT && TARGET_CMOVE
16589 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16591 cmov%O2%C1\t{%2, %0|%0, %2}
16592 cmov%O2%c1\t{%3, %0|%0, %3}"
16593 [(set_attr "type" "icmov")
16594 (set_attr "mode" "DI")])
16596 (define_expand "movsicc"
16597 [(set (match_operand:SI 0 "register_operand" "")
16598 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16599 (match_operand:SI 2 "general_operand" "")
16600 (match_operand:SI 3 "general_operand" "")))]
16602 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16604 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16605 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16606 ;; So just document what we're doing explicitly.
16608 (define_insn "x86_movsicc_0_m1"
16609 [(set (match_operand:SI 0 "register_operand" "=r")
16610 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16613 (clobber (reg:CC 17))]
16616 ; Since we don't have the proper number of operands for an alu insn,
16617 ; fill in all the blanks.
16618 [(set_attr "type" "alu")
16619 (set_attr "pent_pair" "pu")
16620 (set_attr "memory" "none")
16621 (set_attr "imm_disp" "false")
16622 (set_attr "mode" "SI")
16623 (set_attr "length_immediate" "0")])
16625 (define_insn "*movsicc_noc"
16626 [(set (match_operand:SI 0 "register_operand" "=r,r")
16627 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
16628 [(reg 17) (const_int 0)])
16629 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
16630 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
16632 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16634 cmov%O2%C1\t{%2, %0|%0, %2}
16635 cmov%O2%c1\t{%3, %0|%0, %3}"
16636 [(set_attr "type" "icmov")
16637 (set_attr "mode" "SI")])
16639 (define_expand "movhicc"
16640 [(set (match_operand:HI 0 "register_operand" "")
16641 (if_then_else:HI (match_operand 1 "comparison_operator" "")
16642 (match_operand:HI 2 "general_operand" "")
16643 (match_operand:HI 3 "general_operand" "")))]
16644 "TARGET_HIMODE_MATH"
16645 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16647 (define_insn "*movhicc_noc"
16648 [(set (match_operand:HI 0 "register_operand" "=r,r")
16649 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
16650 [(reg 17) (const_int 0)])
16651 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
16652 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
16654 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16656 cmov%O2%C1\t{%2, %0|%0, %2}
16657 cmov%O2%c1\t{%3, %0|%0, %3}"
16658 [(set_attr "type" "icmov")
16659 (set_attr "mode" "HI")])
16661 (define_expand "movqicc"
16662 [(set (match_operand:QI 0 "register_operand" "")
16663 (if_then_else:QI (match_operand 1 "comparison_operator" "")
16664 (match_operand:QI 2 "general_operand" "")
16665 (match_operand:QI 3 "general_operand" "")))]
16666 "TARGET_QIMODE_MATH"
16667 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16669 (define_insn_and_split "*movqicc_noc"
16670 [(set (match_operand:QI 0 "register_operand" "=r,r")
16671 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
16672 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16673 (match_operand:QI 2 "register_operand" "r,0")
16674 (match_operand:QI 3 "register_operand" "0,r")))]
16675 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
16677 "&& reload_completed"
16678 [(set (match_dup 0)
16679 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16682 "operands[0] = gen_lowpart (SImode, operands[0]);
16683 operands[2] = gen_lowpart (SImode, operands[2]);
16684 operands[3] = gen_lowpart (SImode, operands[3]);"
16685 [(set_attr "type" "icmov")
16686 (set_attr "mode" "SI")])
16688 (define_expand "movsfcc"
16689 [(set (match_operand:SF 0 "register_operand" "")
16690 (if_then_else:SF (match_operand 1 "comparison_operator" "")
16691 (match_operand:SF 2 "register_operand" "")
16692 (match_operand:SF 3 "register_operand" "")))]
16694 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16696 (define_insn "*movsfcc_1"
16697 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16698 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
16699 [(reg 17) (const_int 0)])
16700 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16701 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16703 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16705 fcmov%F1\t{%2, %0|%0, %2}
16706 fcmov%f1\t{%3, %0|%0, %3}
16707 cmov%O2%C1\t{%2, %0|%0, %2}
16708 cmov%O2%c1\t{%3, %0|%0, %3}"
16709 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16710 (set_attr "mode" "SF,SF,SI,SI")])
16712 (define_expand "movdfcc"
16713 [(set (match_operand:DF 0 "register_operand" "")
16714 (if_then_else:DF (match_operand 1 "comparison_operator" "")
16715 (match_operand:DF 2 "register_operand" "")
16716 (match_operand:DF 3 "register_operand" "")))]
16718 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16720 (define_insn "*movdfcc_1"
16721 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
16722 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16723 [(reg 17) (const_int 0)])
16724 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
16725 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
16726 "!TARGET_64BIT && TARGET_CMOVE
16727 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16729 fcmov%F1\t{%2, %0|%0, %2}
16730 fcmov%f1\t{%3, %0|%0, %3}
16733 [(set_attr "type" "fcmov,fcmov,multi,multi")
16734 (set_attr "mode" "DF")])
16736 (define_insn "*movdfcc_1_rex64"
16737 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
16738 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16739 [(reg 17) (const_int 0)])
16740 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
16741 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
16742 "TARGET_64BIT && TARGET_CMOVE
16743 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16745 fcmov%F1\t{%2, %0|%0, %2}
16746 fcmov%f1\t{%3, %0|%0, %3}
16747 cmov%O2%C1\t{%2, %0|%0, %2}
16748 cmov%O2%c1\t{%3, %0|%0, %3}"
16749 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
16750 (set_attr "mode" "DF")])
16753 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
16754 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
16755 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
16756 (match_operand:DF 2 "nonimmediate_operand" "")
16757 (match_operand:DF 3 "nonimmediate_operand" "")))]
16758 "!TARGET_64BIT && reload_completed"
16759 [(set (match_dup 2)
16760 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16764 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
16767 "split_di (operands+2, 1, operands+5, operands+6);
16768 split_di (operands+3, 1, operands+7, operands+8);
16769 split_di (operands, 1, operands+2, operands+3);")
16771 (define_expand "movxfcc"
16772 [(set (match_operand:XF 0 "register_operand" "")
16773 (if_then_else:XF (match_operand 1 "comparison_operator" "")
16774 (match_operand:XF 2 "register_operand" "")
16775 (match_operand:XF 3 "register_operand" "")))]
16776 "!TARGET_64BIT && TARGET_CMOVE"
16777 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16779 (define_expand "movtfcc"
16780 [(set (match_operand:TF 0 "register_operand" "")
16781 (if_then_else:TF (match_operand 1 "comparison_operator" "")
16782 (match_operand:TF 2 "register_operand" "")
16783 (match_operand:TF 3 "register_operand" "")))]
16785 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
16787 (define_insn "*movxfcc_1"
16788 [(set (match_operand:XF 0 "register_operand" "=f,f")
16789 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
16790 [(reg 17) (const_int 0)])
16791 (match_operand:XF 2 "register_operand" "f,0")
16792 (match_operand:XF 3 "register_operand" "0,f")))]
16793 "!TARGET_64BIT && TARGET_CMOVE"
16795 fcmov%F1\t{%2, %0|%0, %2}
16796 fcmov%f1\t{%3, %0|%0, %3}"
16797 [(set_attr "type" "fcmov")
16798 (set_attr "mode" "XF")])
16800 (define_insn "*movtfcc_1"
16801 [(set (match_operand:TF 0 "register_operand" "=f,f")
16802 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
16803 [(reg 17) (const_int 0)])
16804 (match_operand:TF 2 "register_operand" "f,0")
16805 (match_operand:TF 3 "register_operand" "0,f")))]
16808 fcmov%F1\t{%2, %0|%0, %2}
16809 fcmov%f1\t{%3, %0|%0, %3}"
16810 [(set_attr "type" "fcmov")
16811 (set_attr "mode" "XF")])
16813 (define_expand "minsf3"
16815 (set (match_operand:SF 0 "register_operand" "")
16816 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16817 (match_operand:SF 2 "nonimmediate_operand" ""))
16820 (clobber (reg:CC 17))])]
16824 (define_insn "*minsf"
16825 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
16826 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
16827 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
16830 (clobber (reg:CC 17))]
16831 "TARGET_SSE && TARGET_IEEE_FP"
16834 (define_insn "*minsf_nonieee"
16835 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
16836 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
16837 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
16840 (clobber (reg:CC 17))]
16841 "TARGET_SSE && !TARGET_IEEE_FP
16842 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16846 [(set (match_operand:SF 0 "register_operand" "")
16847 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16848 (match_operand:SF 2 "nonimmediate_operand" ""))
16849 (match_operand:SF 3 "register_operand" "")
16850 (match_operand:SF 4 "nonimmediate_operand" "")))
16851 (clobber (reg:CC 17))]
16852 "SSE_REG_P (operands[0]) && reload_completed
16853 && ((operands_match_p (operands[1], operands[3])
16854 && operands_match_p (operands[2], operands[4]))
16855 || (operands_match_p (operands[1], operands[4])
16856 && operands_match_p (operands[2], operands[3])))"
16857 [(set (match_dup 0)
16858 (if_then_else:SF (lt (match_dup 1)
16863 ;; Conditional addition patterns
16864 (define_expand "addqicc"
16865 [(match_operand:QI 0 "register_operand" "")
16866 (match_operand 1 "comparison_operator" "")
16867 (match_operand:QI 2 "register_operand" "")
16868 (match_operand:QI 3 "const_int_operand" "")]
16870 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16872 (define_expand "addhicc"
16873 [(match_operand:HI 0 "register_operand" "")
16874 (match_operand 1 "comparison_operator" "")
16875 (match_operand:HI 2 "register_operand" "")
16876 (match_operand:HI 3 "const_int_operand" "")]
16878 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16880 (define_expand "addsicc"
16881 [(match_operand:SI 0 "register_operand" "")
16882 (match_operand 1 "comparison_operator" "")
16883 (match_operand:SI 2 "register_operand" "")
16884 (match_operand:SI 3 "const_int_operand" "")]
16886 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16888 (define_expand "adddicc"
16889 [(match_operand:DI 0 "register_operand" "")
16890 (match_operand 1 "comparison_operator" "")
16891 (match_operand:DI 2 "register_operand" "")
16892 (match_operand:DI 3 "const_int_operand" "")]
16894 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
16896 ;; We can't represent the LT test directly. Do this by swapping the operands.
16899 [(set (match_operand:SF 0 "fp_register_operand" "")
16900 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
16901 (match_operand:SF 2 "register_operand" ""))
16902 (match_operand:SF 3 "register_operand" "")
16903 (match_operand:SF 4 "register_operand" "")))
16904 (clobber (reg:CC 17))]
16906 && ((operands_match_p (operands[1], operands[3])
16907 && operands_match_p (operands[2], operands[4]))
16908 || (operands_match_p (operands[1], operands[4])
16909 && operands_match_p (operands[2], operands[3])))"
16910 [(set (reg:CCFP 17)
16911 (compare:CCFP (match_dup 2)
16914 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
16918 (define_insn "*minsf_sse"
16919 [(set (match_operand:SF 0 "register_operand" "=x")
16920 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
16921 (match_operand:SF 2 "nonimmediate_operand" "xm"))
16924 "TARGET_SSE && reload_completed"
16925 "minss\t{%2, %0|%0, %2}"
16926 [(set_attr "type" "sse")
16927 (set_attr "mode" "SF")])
16929 (define_expand "mindf3"
16931 (set (match_operand:DF 0 "register_operand" "")
16932 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16933 (match_operand:DF 2 "nonimmediate_operand" ""))
16936 (clobber (reg:CC 17))])]
16937 "TARGET_SSE2 && TARGET_SSE_MATH"
16940 (define_insn "*mindf"
16941 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
16942 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
16943 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
16946 (clobber (reg:CC 17))]
16947 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
16950 (define_insn "*mindf_nonieee"
16951 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
16952 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
16953 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
16956 (clobber (reg:CC 17))]
16957 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
16958 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
16962 [(set (match_operand:DF 0 "register_operand" "")
16963 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16964 (match_operand:DF 2 "nonimmediate_operand" ""))
16965 (match_operand:DF 3 "register_operand" "")
16966 (match_operand:DF 4 "nonimmediate_operand" "")))
16967 (clobber (reg:CC 17))]
16968 "SSE_REG_P (operands[0]) && reload_completed
16969 && ((operands_match_p (operands[1], operands[3])
16970 && operands_match_p (operands[2], operands[4]))
16971 || (operands_match_p (operands[1], operands[4])
16972 && operands_match_p (operands[2], operands[3])))"
16973 [(set (match_dup 0)
16974 (if_then_else:DF (lt (match_dup 1)
16979 ;; We can't represent the LT test directly. Do this by swapping the operands.
16981 [(set (match_operand:DF 0 "fp_register_operand" "")
16982 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
16983 (match_operand:DF 2 "register_operand" ""))
16984 (match_operand:DF 3 "register_operand" "")
16985 (match_operand:DF 4 "register_operand" "")))
16986 (clobber (reg:CC 17))]
16988 && ((operands_match_p (operands[1], operands[3])
16989 && operands_match_p (operands[2], operands[4]))
16990 || (operands_match_p (operands[1], operands[4])
16991 && operands_match_p (operands[2], operands[3])))"
16992 [(set (reg:CCFP 17)
16993 (compare:CCFP (match_dup 2)
16996 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
17000 (define_insn "*mindf_sse"
17001 [(set (match_operand:DF 0 "register_operand" "=Y")
17002 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17003 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17006 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17007 "minsd\t{%2, %0|%0, %2}"
17008 [(set_attr "type" "sse")
17009 (set_attr "mode" "DF")])
17011 (define_expand "maxsf3"
17013 (set (match_operand:SF 0 "register_operand" "")
17014 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17015 (match_operand:SF 2 "nonimmediate_operand" ""))
17018 (clobber (reg:CC 17))])]
17022 (define_insn "*maxsf"
17023 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17024 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17025 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17028 (clobber (reg:CC 17))]
17029 "TARGET_SSE && TARGET_IEEE_FP"
17032 (define_insn "*maxsf_nonieee"
17033 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17034 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17035 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17038 (clobber (reg:CC 17))]
17039 "TARGET_SSE && !TARGET_IEEE_FP
17040 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17044 [(set (match_operand:SF 0 "register_operand" "")
17045 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17046 (match_operand:SF 2 "nonimmediate_operand" ""))
17047 (match_operand:SF 3 "register_operand" "")
17048 (match_operand:SF 4 "nonimmediate_operand" "")))
17049 (clobber (reg:CC 17))]
17050 "SSE_REG_P (operands[0]) && reload_completed
17051 && ((operands_match_p (operands[1], operands[3])
17052 && operands_match_p (operands[2], operands[4]))
17053 || (operands_match_p (operands[1], operands[4])
17054 && operands_match_p (operands[2], operands[3])))"
17055 [(set (match_dup 0)
17056 (if_then_else:SF (gt (match_dup 1)
17062 [(set (match_operand:SF 0 "fp_register_operand" "")
17063 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17064 (match_operand:SF 2 "register_operand" ""))
17065 (match_operand:SF 3 "register_operand" "")
17066 (match_operand:SF 4 "register_operand" "")))
17067 (clobber (reg:CC 17))]
17069 && ((operands_match_p (operands[1], operands[3])
17070 && operands_match_p (operands[2], operands[4]))
17071 || (operands_match_p (operands[1], operands[4])
17072 && operands_match_p (operands[2], operands[3])))"
17073 [(set (reg:CCFP 17)
17074 (compare:CCFP (match_dup 1)
17077 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
17081 (define_insn "*maxsf_sse"
17082 [(set (match_operand:SF 0 "register_operand" "=x")
17083 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17084 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17087 "TARGET_SSE && reload_completed"
17088 "maxss\t{%2, %0|%0, %2}"
17089 [(set_attr "type" "sse")
17090 (set_attr "mode" "SF")])
17092 (define_expand "maxdf3"
17094 (set (match_operand:DF 0 "register_operand" "")
17095 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17096 (match_operand:DF 2 "nonimmediate_operand" ""))
17099 (clobber (reg:CC 17))])]
17100 "TARGET_SSE2 && TARGET_SSE_MATH"
17103 (define_insn "*maxdf"
17104 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17105 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17106 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17109 (clobber (reg:CC 17))]
17110 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17113 (define_insn "*maxdf_nonieee"
17114 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17115 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17116 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17119 (clobber (reg:CC 17))]
17120 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17121 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17125 [(set (match_operand:DF 0 "register_operand" "")
17126 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17127 (match_operand:DF 2 "nonimmediate_operand" ""))
17128 (match_operand:DF 3 "register_operand" "")
17129 (match_operand:DF 4 "nonimmediate_operand" "")))
17130 (clobber (reg:CC 17))]
17131 "SSE_REG_P (operands[0]) && reload_completed
17132 && ((operands_match_p (operands[1], operands[3])
17133 && operands_match_p (operands[2], operands[4]))
17134 || (operands_match_p (operands[1], operands[4])
17135 && operands_match_p (operands[2], operands[3])))"
17136 [(set (match_dup 0)
17137 (if_then_else:DF (gt (match_dup 1)
17143 [(set (match_operand:DF 0 "fp_register_operand" "")
17144 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17145 (match_operand:DF 2 "register_operand" ""))
17146 (match_operand:DF 3 "register_operand" "")
17147 (match_operand:DF 4 "register_operand" "")))
17148 (clobber (reg:CC 17))]
17150 && ((operands_match_p (operands[1], operands[3])
17151 && operands_match_p (operands[2], operands[4]))
17152 || (operands_match_p (operands[1], operands[4])
17153 && operands_match_p (operands[2], operands[3])))"
17154 [(set (reg:CCFP 17)
17155 (compare:CCFP (match_dup 1)
17158 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
17162 (define_insn "*maxdf_sse"
17163 [(set (match_operand:DF 0 "register_operand" "=Y")
17164 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17165 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17168 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17169 "maxsd\t{%2, %0|%0, %2}"
17170 [(set_attr "type" "sse")
17171 (set_attr "mode" "DF")])
17173 ;; Misc patterns (?)
17175 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17176 ;; Otherwise there will be nothing to keep
17178 ;; [(set (reg ebp) (reg esp))]
17179 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17180 ;; (clobber (eflags)]
17181 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17183 ;; in proper program order.
17184 (define_expand "pro_epilogue_adjust_stack"
17185 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
17186 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17187 (match_operand:SI 2 "immediate_operand" "i,i")))
17188 (clobber (reg:CC 17))
17189 (clobber (mem:BLK (scratch)))])]
17194 emit_insn (gen_pro_epilogue_adjust_stack_rex64
17195 (operands[0], operands[1], operands[2]));
17200 (define_insn "*pro_epilogue_adjust_stack_1"
17201 [(set (match_operand:SI 0 "register_operand" "=r,r")
17202 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17203 (match_operand:SI 2 "immediate_operand" "i,i")))
17204 (clobber (reg:CC 17))
17205 (clobber (mem:BLK (scratch)))]
17208 switch (get_attr_type (insn))
17211 return "mov{l}\t{%1, %0|%0, %1}";
17214 if (GET_CODE (operands[2]) == CONST_INT
17215 && (INTVAL (operands[2]) == 128
17216 || (INTVAL (operands[2]) < 0
17217 && INTVAL (operands[2]) != -128)))
17219 operands[2] = GEN_INT (-INTVAL (operands[2]));
17220 return "sub{l}\t{%2, %0|%0, %2}";
17222 return "add{l}\t{%2, %0|%0, %2}";
17225 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17226 return "lea{l}\t{%a2, %0|%0, %a2}";
17232 [(set (attr "type")
17233 (cond [(eq_attr "alternative" "0")
17234 (const_string "alu")
17235 (match_operand:SI 2 "const0_operand" "")
17236 (const_string "imov")
17238 (const_string "lea")))
17239 (set_attr "mode" "SI")])
17241 (define_insn "pro_epilogue_adjust_stack_rex64"
17242 [(set (match_operand:DI 0 "register_operand" "=r,r")
17243 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
17244 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
17245 (clobber (reg:CC 17))
17246 (clobber (mem:BLK (scratch)))]
17249 switch (get_attr_type (insn))
17252 return "mov{q}\t{%1, %0|%0, %1}";
17255 if (GET_CODE (operands[2]) == CONST_INT
17256 && (INTVAL (operands[2]) == 128
17257 || (INTVAL (operands[2]) < 0
17258 && INTVAL (operands[2]) != -128)))
17260 operands[2] = GEN_INT (-INTVAL (operands[2]));
17261 return "sub{q}\t{%2, %0|%0, %2}";
17263 return "add{q}\t{%2, %0|%0, %2}";
17266 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17267 return "lea{q}\t{%a2, %0|%0, %a2}";
17273 [(set (attr "type")
17274 (cond [(eq_attr "alternative" "0")
17275 (const_string "alu")
17276 (match_operand:DI 2 "const0_operand" "")
17277 (const_string "imov")
17279 (const_string "lea")))
17280 (set_attr "mode" "DI")])
17283 ;; Placeholder for the conditional moves. This one is split either to SSE
17284 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
17285 ;; fact is that compares supported by the cmp??ss instructions are exactly
17286 ;; swapped of those supported by cmove sequence.
17287 ;; The EQ/NE comparisons also needs bit care, since they are not directly
17288 ;; supported by i387 comparisons and we do need to emit two conditional moves
17291 (define_insn "sse_movsfcc"
17292 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
17293 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17294 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
17295 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
17296 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
17297 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
17298 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17299 (clobber (reg:CC 17))]
17301 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17302 /* Avoid combine from being smart and converting min/max
17303 instruction patterns into conditional moves. */
17304 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17305 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17306 || !rtx_equal_p (operands[4], operands[2])
17307 || !rtx_equal_p (operands[5], operands[3]))
17308 && (!TARGET_IEEE_FP
17309 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17312 (define_insn "sse_movsfcc_eq"
17313 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
17314 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
17315 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
17316 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
17317 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
17318 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
17319 (clobber (reg:CC 17))]
17321 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17324 (define_insn "sse_movdfcc"
17325 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
17326 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17327 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
17328 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
17329 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
17330 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
17331 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17332 (clobber (reg:CC 17))]
17334 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17335 /* Avoid combine from being smart and converting min/max
17336 instruction patterns into conditional moves. */
17337 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17338 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17339 || !rtx_equal_p (operands[4], operands[2])
17340 || !rtx_equal_p (operands[5], operands[3]))
17341 && (!TARGET_IEEE_FP
17342 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17345 (define_insn "sse_movdfcc_eq"
17346 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
17347 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
17348 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
17349 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
17350 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
17351 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
17352 (clobber (reg:CC 17))]
17354 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17357 ;; For non-sse moves just expand the usual cmove sequence.
17359 [(set (match_operand 0 "register_operand" "")
17360 (if_then_else (match_operator 1 "comparison_operator"
17361 [(match_operand 4 "nonimmediate_operand" "")
17362 (match_operand 5 "register_operand" "")])
17363 (match_operand 2 "nonimmediate_operand" "")
17364 (match_operand 3 "nonimmediate_operand" "")))
17365 (clobber (match_operand 6 "" ""))
17366 (clobber (reg:CC 17))]
17367 "!SSE_REG_P (operands[0]) && reload_completed
17368 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17371 ix86_compare_op0 = operands[5];
17372 ix86_compare_op1 = operands[4];
17373 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17374 VOIDmode, operands[5], operands[4]);
17375 ix86_expand_fp_movcc (operands);
17379 ;; Split SSE based conditional move into sequence:
17380 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17381 ;; and op2, op0 - zero op2 if comparison was false
17382 ;; nand op0, op3 - load op3 to op0 if comparison was false
17383 ;; or op2, op0 - get the nonzero one into the result.
17385 [(set (match_operand 0 "register_operand" "")
17386 (if_then_else (match_operator 1 "sse_comparison_operator"
17387 [(match_operand 4 "register_operand" "")
17388 (match_operand 5 "nonimmediate_operand" "")])
17389 (match_operand 2 "register_operand" "")
17390 (match_operand 3 "register_operand" "")))
17391 (clobber (match_operand 6 "" ""))
17392 (clobber (reg:CC 17))]
17393 "SSE_REG_P (operands[0]) && reload_completed"
17394 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17395 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17396 (subreg:TI (match_dup 4) 0)))
17397 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17398 (subreg:TI (match_dup 3) 0)))
17399 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17400 (subreg:TI (match_dup 7) 0)))]
17402 if (GET_MODE (operands[2]) == DFmode
17403 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17405 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17406 emit_insn (gen_sse2_unpcklpd (op, op, op));
17407 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17408 emit_insn (gen_sse2_unpcklpd (op, op, op));
17411 /* If op2 == op3, op3 would be clobbered before it is used. */
17412 if (operands_match_p (operands[2], operands[3]))
17414 emit_move_insn (operands[0], operands[2]);
17418 PUT_MODE (operands[1], GET_MODE (operands[0]));
17419 if (operands_match_p (operands[0], operands[4]))
17420 operands[6] = operands[4], operands[7] = operands[2];
17422 operands[6] = operands[2], operands[7] = operands[4];
17425 ;; Special case of conditional move we can handle effectively.
17426 ;; Do not brother with the integer/floating point case, since these are
17427 ;; bot considerably slower, unlike in the generic case.
17428 (define_insn "*sse_movsfcc_const0_1"
17429 [(set (match_operand:SF 0 "register_operand" "=&x")
17430 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17431 [(match_operand:SF 4 "register_operand" "0")
17432 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17433 (match_operand:SF 2 "register_operand" "x")
17434 (match_operand:SF 3 "const0_operand" "X")))]
17438 (define_insn "*sse_movsfcc_const0_2"
17439 [(set (match_operand:SF 0 "register_operand" "=&x")
17440 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17441 [(match_operand:SF 4 "register_operand" "0")
17442 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17443 (match_operand:SF 2 "const0_operand" "X")
17444 (match_operand:SF 3 "register_operand" "x")))]
17448 (define_insn "*sse_movsfcc_const0_3"
17449 [(set (match_operand:SF 0 "register_operand" "=&x")
17450 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17451 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17452 (match_operand:SF 5 "register_operand" "0")])
17453 (match_operand:SF 2 "register_operand" "x")
17454 (match_operand:SF 3 "const0_operand" "X")))]
17458 (define_insn "*sse_movsfcc_const0_4"
17459 [(set (match_operand:SF 0 "register_operand" "=&x")
17460 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17461 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17462 (match_operand:SF 5 "register_operand" "0")])
17463 (match_operand:SF 2 "const0_operand" "X")
17464 (match_operand:SF 3 "register_operand" "x")))]
17468 (define_insn "*sse_movdfcc_const0_1"
17469 [(set (match_operand:DF 0 "register_operand" "=&Y")
17470 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17471 [(match_operand:DF 4 "register_operand" "0")
17472 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17473 (match_operand:DF 2 "register_operand" "Y")
17474 (match_operand:DF 3 "const0_operand" "X")))]
17478 (define_insn "*sse_movdfcc_const0_2"
17479 [(set (match_operand:DF 0 "register_operand" "=&Y")
17480 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17481 [(match_operand:DF 4 "register_operand" "0")
17482 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17483 (match_operand:DF 2 "const0_operand" "X")
17484 (match_operand:DF 3 "register_operand" "Y")))]
17488 (define_insn "*sse_movdfcc_const0_3"
17489 [(set (match_operand:DF 0 "register_operand" "=&Y")
17490 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17491 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17492 (match_operand:DF 5 "register_operand" "0")])
17493 (match_operand:DF 2 "register_operand" "Y")
17494 (match_operand:DF 3 "const0_operand" "X")))]
17498 (define_insn "*sse_movdfcc_const0_4"
17499 [(set (match_operand:DF 0 "register_operand" "=&Y")
17500 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17501 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17502 (match_operand:DF 5 "register_operand" "0")])
17503 (match_operand:DF 2 "const0_operand" "X")
17504 (match_operand:DF 3 "register_operand" "Y")))]
17509 [(set (match_operand 0 "register_operand" "")
17510 (if_then_else (match_operator 1 "comparison_operator"
17511 [(match_operand 4 "nonimmediate_operand" "")
17512 (match_operand 5 "nonimmediate_operand" "")])
17513 (match_operand 2 "nonmemory_operand" "")
17514 (match_operand 3 "nonmemory_operand" "")))]
17515 "SSE_REG_P (operands[0]) && reload_completed
17516 && (const0_operand (operands[2], GET_MODE (operands[0]))
17517 || const0_operand (operands[3], GET_MODE (operands[0])))"
17518 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17519 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17522 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17523 && GET_MODE (operands[2]) == DFmode)
17525 if (REG_P (operands[2]))
17527 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17528 emit_insn (gen_sse2_unpcklpd (op, op, op));
17530 if (REG_P (operands[3]))
17532 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17533 emit_insn (gen_sse2_unpcklpd (op, op, op));
17536 PUT_MODE (operands[1], GET_MODE (operands[0]));
17537 if (!sse_comparison_operator (operands[1], VOIDmode)
17538 || !rtx_equal_p (operands[0], operands[4]))
17540 rtx tmp = operands[5];
17541 operands[5] = operands[4];
17543 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17545 if (!rtx_equal_p (operands[0], operands[4]))
17547 if (const0_operand (operands[2], GET_MODE (operands[0])))
17549 operands[7] = operands[3];
17550 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17555 operands[7] = operands[2];
17556 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17558 operands[7] = simplify_gen_subreg (TImode, operands[7],
17559 GET_MODE (operands[7]), 0);
17562 (define_expand "allocate_stack_worker"
17563 [(match_operand:SI 0 "register_operand" "")]
17564 "TARGET_STACK_PROBE"
17567 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17569 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17573 (define_insn "allocate_stack_worker_1"
17574 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17575 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17576 (clobber (match_dup 0))
17577 (clobber (reg:CC 17))]
17578 "!TARGET_64BIT && TARGET_STACK_PROBE"
17580 [(set_attr "type" "multi")
17581 (set_attr "length" "5")])
17583 (define_insn "allocate_stack_worker_rex64"
17584 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17585 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17586 (clobber (match_dup 0))
17587 (clobber (reg:CC 17))]
17588 "TARGET_64BIT && TARGET_STACK_PROBE"
17590 [(set_attr "type" "multi")
17591 (set_attr "length" "5")])
17593 (define_expand "allocate_stack"
17594 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17595 (minus:SI (reg:SI 7)
17596 (match_operand:SI 1 "general_operand" "")))
17597 (clobber (reg:CC 17))])
17598 (parallel [(set (reg:SI 7)
17599 (minus:SI (reg:SI 7) (match_dup 1)))
17600 (clobber (reg:CC 17))])]
17601 "TARGET_STACK_PROBE"
17603 #ifdef CHECK_STACK_LIMIT
17604 if (GET_CODE (operands[1]) == CONST_INT
17605 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17606 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17610 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17613 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
17617 (define_expand "builtin_setjmp_receiver"
17618 [(label_ref (match_operand 0 "" ""))]
17619 "!TARGET_64BIT && flag_pic"
17621 emit_insn (gen_set_got (pic_offset_table_rtx));
17625 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
17628 [(set (match_operand 0 "register_operand" "")
17629 (match_operator 3 "promotable_binary_operator"
17630 [(match_operand 1 "register_operand" "")
17631 (match_operand 2 "aligned_operand" "")]))
17632 (clobber (reg:CC 17))]
17633 "! TARGET_PARTIAL_REG_STALL && reload_completed
17634 && ((GET_MODE (operands[0]) == HImode
17635 && ((!optimize_size && !TARGET_FAST_PREFIX)
17636 || GET_CODE (operands[2]) != CONST_INT
17637 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
17638 || (GET_MODE (operands[0]) == QImode
17639 && (TARGET_PROMOTE_QImode || optimize_size)))"
17640 [(parallel [(set (match_dup 0)
17641 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
17642 (clobber (reg:CC 17))])]
17643 "operands[0] = gen_lowpart (SImode, operands[0]);
17644 operands[1] = gen_lowpart (SImode, operands[1]);
17645 if (GET_CODE (operands[3]) != ASHIFT)
17646 operands[2] = gen_lowpart (SImode, operands[2]);
17647 PUT_MODE (operands[3], SImode);")
17649 ; Promote the QImode tests, as i386 has encoding of the AND
17650 ; instruction with 32-bit sign-extended immediate and thus the
17651 ; instruction size is unchanged, except in the %eax case for
17652 ; which it is increased by one byte, hence the ! optimize_size.
17655 (compare (and (match_operand 1 "aligned_operand" "")
17656 (match_operand 2 "const_int_operand" ""))
17658 (set (match_operand 0 "register_operand" "")
17659 (and (match_dup 1) (match_dup 2)))]
17660 "! TARGET_PARTIAL_REG_STALL && reload_completed
17661 /* Ensure that the operand will remain sign-extended immediate. */
17662 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
17664 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
17665 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
17666 [(parallel [(set (reg:CCNO 17)
17667 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
17670 (and:SI (match_dup 1) (match_dup 2)))])]
17672 = gen_int_mode (INTVAL (operands[2])
17673 & GET_MODE_MASK (GET_MODE (operands[0])),
17675 operands[0] = gen_lowpart (SImode, operands[0]);
17676 operands[1] = gen_lowpart (SImode, operands[1]);")
17678 ; Don't promote the QImode tests, as i386 doesn't have encoding of
17679 ; the TEST instruction with 32-bit sign-extended immediate and thus
17680 ; the instruction size would at least double, which is not what we
17681 ; want even with ! optimize_size.
17684 (compare (and (match_operand:HI 0 "aligned_operand" "")
17685 (match_operand:HI 1 "const_int_operand" ""))
17687 "! TARGET_PARTIAL_REG_STALL && reload_completed
17688 /* Ensure that the operand will remain sign-extended immediate. */
17689 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
17690 && ! TARGET_FAST_PREFIX
17691 && ! optimize_size"
17692 [(set (reg:CCNO 17)
17693 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
17696 = gen_int_mode (INTVAL (operands[1])
17697 & GET_MODE_MASK (GET_MODE (operands[0])),
17699 operands[0] = gen_lowpart (SImode, operands[0]);")
17702 [(set (match_operand 0 "register_operand" "")
17703 (neg (match_operand 1 "register_operand" "")))
17704 (clobber (reg:CC 17))]
17705 "! TARGET_PARTIAL_REG_STALL && reload_completed
17706 && (GET_MODE (operands[0]) == HImode
17707 || (GET_MODE (operands[0]) == QImode
17708 && (TARGET_PROMOTE_QImode || optimize_size)))"
17709 [(parallel [(set (match_dup 0)
17710 (neg:SI (match_dup 1)))
17711 (clobber (reg:CC 17))])]
17712 "operands[0] = gen_lowpart (SImode, operands[0]);
17713 operands[1] = gen_lowpart (SImode, operands[1]);")
17716 [(set (match_operand 0 "register_operand" "")
17717 (not (match_operand 1 "register_operand" "")))]
17718 "! TARGET_PARTIAL_REG_STALL && reload_completed
17719 && (GET_MODE (operands[0]) == HImode
17720 || (GET_MODE (operands[0]) == QImode
17721 && (TARGET_PROMOTE_QImode || optimize_size)))"
17722 [(set (match_dup 0)
17723 (not:SI (match_dup 1)))]
17724 "operands[0] = gen_lowpart (SImode, operands[0]);
17725 operands[1] = gen_lowpart (SImode, operands[1]);")
17728 [(set (match_operand 0 "register_operand" "")
17729 (if_then_else (match_operator 1 "comparison_operator"
17730 [(reg 17) (const_int 0)])
17731 (match_operand 2 "register_operand" "")
17732 (match_operand 3 "register_operand" "")))]
17733 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
17734 && (GET_MODE (operands[0]) == HImode
17735 || (GET_MODE (operands[0]) == QImode
17736 && (TARGET_PROMOTE_QImode || optimize_size)))"
17737 [(set (match_dup 0)
17738 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
17739 "operands[0] = gen_lowpart (SImode, operands[0]);
17740 operands[2] = gen_lowpart (SImode, operands[2]);
17741 operands[3] = gen_lowpart (SImode, operands[3]);")
17744 ;; RTL Peephole optimizations, run before sched2. These primarily look to
17745 ;; transform a complex memory operation into two memory to register operations.
17747 ;; Don't push memory operands
17749 [(set (match_operand:SI 0 "push_operand" "")
17750 (match_operand:SI 1 "memory_operand" ""))
17751 (match_scratch:SI 2 "r")]
17752 "! optimize_size && ! TARGET_PUSH_MEMORY"
17753 [(set (match_dup 2) (match_dup 1))
17754 (set (match_dup 0) (match_dup 2))]
17758 [(set (match_operand:DI 0 "push_operand" "")
17759 (match_operand:DI 1 "memory_operand" ""))
17760 (match_scratch:DI 2 "r")]
17761 "! optimize_size && ! TARGET_PUSH_MEMORY"
17762 [(set (match_dup 2) (match_dup 1))
17763 (set (match_dup 0) (match_dup 2))]
17766 ;; We need to handle SFmode only, because DFmode and XFmode is split to
17769 [(set (match_operand:SF 0 "push_operand" "")
17770 (match_operand:SF 1 "memory_operand" ""))
17771 (match_scratch:SF 2 "r")]
17772 "! optimize_size && ! TARGET_PUSH_MEMORY"
17773 [(set (match_dup 2) (match_dup 1))
17774 (set (match_dup 0) (match_dup 2))]
17778 [(set (match_operand:HI 0 "push_operand" "")
17779 (match_operand:HI 1 "memory_operand" ""))
17780 (match_scratch:HI 2 "r")]
17781 "! optimize_size && ! TARGET_PUSH_MEMORY"
17782 [(set (match_dup 2) (match_dup 1))
17783 (set (match_dup 0) (match_dup 2))]
17787 [(set (match_operand:QI 0 "push_operand" "")
17788 (match_operand:QI 1 "memory_operand" ""))
17789 (match_scratch:QI 2 "q")]
17790 "! optimize_size && ! TARGET_PUSH_MEMORY"
17791 [(set (match_dup 2) (match_dup 1))
17792 (set (match_dup 0) (match_dup 2))]
17795 ;; Don't move an immediate directly to memory when the instruction
17798 [(match_scratch:SI 1 "r")
17799 (set (match_operand:SI 0 "memory_operand" "")
17802 && ! TARGET_USE_MOV0
17803 && TARGET_SPLIT_LONG_MOVES
17804 && get_attr_length (insn) >= ix86_cost->large_insn
17805 && peep2_regno_dead_p (0, FLAGS_REG)"
17806 [(parallel [(set (match_dup 1) (const_int 0))
17807 (clobber (reg:CC 17))])
17808 (set (match_dup 0) (match_dup 1))]
17812 [(match_scratch:HI 1 "r")
17813 (set (match_operand:HI 0 "memory_operand" "")
17816 && ! TARGET_USE_MOV0
17817 && TARGET_SPLIT_LONG_MOVES
17818 && get_attr_length (insn) >= ix86_cost->large_insn
17819 && peep2_regno_dead_p (0, FLAGS_REG)"
17820 [(parallel [(set (match_dup 2) (const_int 0))
17821 (clobber (reg:CC 17))])
17822 (set (match_dup 0) (match_dup 1))]
17823 "operands[2] = gen_lowpart (SImode, operands[1]);")
17826 [(match_scratch:QI 1 "q")
17827 (set (match_operand:QI 0 "memory_operand" "")
17830 && ! TARGET_USE_MOV0
17831 && TARGET_SPLIT_LONG_MOVES
17832 && get_attr_length (insn) >= ix86_cost->large_insn
17833 && peep2_regno_dead_p (0, FLAGS_REG)"
17834 [(parallel [(set (match_dup 2) (const_int 0))
17835 (clobber (reg:CC 17))])
17836 (set (match_dup 0) (match_dup 1))]
17837 "operands[2] = gen_lowpart (SImode, operands[1]);")
17840 [(match_scratch:SI 2 "r")
17841 (set (match_operand:SI 0 "memory_operand" "")
17842 (match_operand:SI 1 "immediate_operand" ""))]
17844 && get_attr_length (insn) >= ix86_cost->large_insn
17845 && TARGET_SPLIT_LONG_MOVES"
17846 [(set (match_dup 2) (match_dup 1))
17847 (set (match_dup 0) (match_dup 2))]
17851 [(match_scratch:HI 2 "r")
17852 (set (match_operand:HI 0 "memory_operand" "")
17853 (match_operand:HI 1 "immediate_operand" ""))]
17854 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17855 && TARGET_SPLIT_LONG_MOVES"
17856 [(set (match_dup 2) (match_dup 1))
17857 (set (match_dup 0) (match_dup 2))]
17861 [(match_scratch:QI 2 "q")
17862 (set (match_operand:QI 0 "memory_operand" "")
17863 (match_operand:QI 1 "immediate_operand" ""))]
17864 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
17865 && TARGET_SPLIT_LONG_MOVES"
17866 [(set (match_dup 2) (match_dup 1))
17867 (set (match_dup 0) (match_dup 2))]
17870 ;; Don't compare memory with zero, load and use a test instead.
17873 (compare (match_operand:SI 0 "memory_operand" "")
17875 (match_scratch:SI 3 "r")]
17876 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
17877 [(set (match_dup 3) (match_dup 0))
17878 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
17881 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
17882 ;; Don't split NOTs with a displacement operand, because resulting XOR
17883 ;; will not be pairable anyway.
17885 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
17886 ;; represented using a modRM byte. The XOR replacement is long decoded,
17887 ;; so this split helps here as well.
17889 ;; Note: Can't do this as a regular split because we can't get proper
17890 ;; lifetime information then.
17893 [(set (match_operand:SI 0 "nonimmediate_operand" "")
17894 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
17896 && peep2_regno_dead_p (0, FLAGS_REG)
17897 && ((TARGET_PENTIUM
17898 && (GET_CODE (operands[0]) != MEM
17899 || !memory_displacement_operand (operands[0], SImode)))
17900 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
17901 [(parallel [(set (match_dup 0)
17902 (xor:SI (match_dup 1) (const_int -1)))
17903 (clobber (reg:CC 17))])]
17907 [(set (match_operand:HI 0 "nonimmediate_operand" "")
17908 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
17910 && peep2_regno_dead_p (0, FLAGS_REG)
17911 && ((TARGET_PENTIUM
17912 && (GET_CODE (operands[0]) != MEM
17913 || !memory_displacement_operand (operands[0], HImode)))
17914 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
17915 [(parallel [(set (match_dup 0)
17916 (xor:HI (match_dup 1) (const_int -1)))
17917 (clobber (reg:CC 17))])]
17921 [(set (match_operand:QI 0 "nonimmediate_operand" "")
17922 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
17924 && peep2_regno_dead_p (0, FLAGS_REG)
17925 && ((TARGET_PENTIUM
17926 && (GET_CODE (operands[0]) != MEM
17927 || !memory_displacement_operand (operands[0], QImode)))
17928 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
17929 [(parallel [(set (match_dup 0)
17930 (xor:QI (match_dup 1) (const_int -1)))
17931 (clobber (reg:CC 17))])]
17934 ;; Non pairable "test imm, reg" instructions can be translated to
17935 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
17936 ;; byte opcode instead of two, have a short form for byte operands),
17937 ;; so do it for other CPUs as well. Given that the value was dead,
17938 ;; this should not create any new dependencies. Pass on the sub-word
17939 ;; versions if we're concerned about partial register stalls.
17943 (compare (and:SI (match_operand:SI 0 "register_operand" "")
17944 (match_operand:SI 1 "immediate_operand" ""))
17946 "ix86_match_ccmode (insn, CCNOmode)
17947 && (true_regnum (operands[0]) != 0
17948 || (GET_CODE (operands[1]) == CONST_INT
17949 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
17950 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17952 [(set (reg:CCNO 17)
17953 (compare:CCNO (and:SI (match_dup 0)
17957 (and:SI (match_dup 0) (match_dup 1)))])]
17960 ;; We don't need to handle HImode case, because it will be promoted to SImode
17961 ;; on ! TARGET_PARTIAL_REG_STALL
17965 (compare (and:QI (match_operand:QI 0 "register_operand" "")
17966 (match_operand:QI 1 "immediate_operand" ""))
17968 "! TARGET_PARTIAL_REG_STALL
17969 && ix86_match_ccmode (insn, CCNOmode)
17970 && true_regnum (operands[0]) != 0
17971 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17973 [(set (reg:CCNO 17)
17974 (compare:CCNO (and:QI (match_dup 0)
17978 (and:QI (match_dup 0) (match_dup 1)))])]
17986 (match_operand 0 "ext_register_operand" "")
17989 (match_operand 1 "const_int_operand" ""))
17991 "! TARGET_PARTIAL_REG_STALL
17992 && ix86_match_ccmode (insn, CCNOmode)
17993 && true_regnum (operands[0]) != 0
17994 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
17995 [(parallel [(set (reg:CCNO 17)
18004 (set (zero_extract:SI (match_dup 0)
18015 ;; Don't do logical operations with memory inputs.
18017 [(match_scratch:SI 2 "r")
18018 (parallel [(set (match_operand:SI 0 "register_operand" "")
18019 (match_operator:SI 3 "arith_or_logical_operator"
18021 (match_operand:SI 1 "memory_operand" "")]))
18022 (clobber (reg:CC 17))])]
18023 "! optimize_size && ! TARGET_READ_MODIFY"
18024 [(set (match_dup 2) (match_dup 1))
18025 (parallel [(set (match_dup 0)
18026 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18027 (clobber (reg:CC 17))])]
18031 [(match_scratch:SI 2 "r")
18032 (parallel [(set (match_operand:SI 0 "register_operand" "")
18033 (match_operator:SI 3 "arith_or_logical_operator"
18034 [(match_operand:SI 1 "memory_operand" "")
18036 (clobber (reg:CC 17))])]
18037 "! optimize_size && ! TARGET_READ_MODIFY"
18038 [(set (match_dup 2) (match_dup 1))
18039 (parallel [(set (match_dup 0)
18040 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18041 (clobber (reg:CC 17))])]
18044 ; Don't do logical operations with memory outputs
18046 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18047 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18048 ; the same decoder scheduling characteristics as the original.
18051 [(match_scratch:SI 2 "r")
18052 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18053 (match_operator:SI 3 "arith_or_logical_operator"
18055 (match_operand:SI 1 "nonmemory_operand" "")]))
18056 (clobber (reg:CC 17))])]
18057 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18058 [(set (match_dup 2) (match_dup 0))
18059 (parallel [(set (match_dup 2)
18060 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18061 (clobber (reg:CC 17))])
18062 (set (match_dup 0) (match_dup 2))]
18066 [(match_scratch:SI 2 "r")
18067 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18068 (match_operator:SI 3 "arith_or_logical_operator"
18069 [(match_operand:SI 1 "nonmemory_operand" "")
18071 (clobber (reg:CC 17))])]
18072 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18073 [(set (match_dup 2) (match_dup 0))
18074 (parallel [(set (match_dup 2)
18075 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18076 (clobber (reg:CC 17))])
18077 (set (match_dup 0) (match_dup 2))]
18080 ;; Attempt to always use XOR for zeroing registers.
18082 [(set (match_operand 0 "register_operand" "")
18084 "(GET_MODE (operands[0]) == QImode
18085 || GET_MODE (operands[0]) == HImode
18086 || GET_MODE (operands[0]) == SImode
18087 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18088 && (! TARGET_USE_MOV0 || optimize_size)
18089 && peep2_regno_dead_p (0, FLAGS_REG)"
18090 [(parallel [(set (match_dup 0) (const_int 0))
18091 (clobber (reg:CC 17))])]
18092 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18096 [(set (strict_low_part (match_operand 0 "register_operand" ""))
18098 "(GET_MODE (operands[0]) == QImode
18099 || GET_MODE (operands[0]) == HImode)
18100 && (! TARGET_USE_MOV0 || optimize_size)
18101 && peep2_regno_dead_p (0, FLAGS_REG)"
18102 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
18103 (clobber (reg:CC 17))])])
18105 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
18107 [(set (match_operand 0 "register_operand" "")
18109 "(GET_MODE (operands[0]) == HImode
18110 || GET_MODE (operands[0]) == SImode
18111 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18112 && (optimize_size || TARGET_PENTIUM)
18113 && peep2_regno_dead_p (0, FLAGS_REG)"
18114 [(parallel [(set (match_dup 0) (const_int -1))
18115 (clobber (reg:CC 17))])]
18116 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18119 ;; Attempt to convert simple leas to adds. These can be created by
18122 [(set (match_operand:SI 0 "register_operand" "")
18123 (plus:SI (match_dup 0)
18124 (match_operand:SI 1 "nonmemory_operand" "")))]
18125 "peep2_regno_dead_p (0, FLAGS_REG)"
18126 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
18127 (clobber (reg:CC 17))])]
18131 [(set (match_operand:SI 0 "register_operand" "")
18132 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
18133 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
18134 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
18135 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
18136 (clobber (reg:CC 17))])]
18137 "operands[2] = gen_lowpart (SImode, operands[2]);")
18140 [(set (match_operand:DI 0 "register_operand" "")
18141 (plus:DI (match_dup 0)
18142 (match_operand:DI 1 "x86_64_general_operand" "")))]
18143 "peep2_regno_dead_p (0, FLAGS_REG)"
18144 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
18145 (clobber (reg:CC 17))])]
18149 [(set (match_operand:SI 0 "register_operand" "")
18150 (mult:SI (match_dup 0)
18151 (match_operand:SI 1 "const_int_operand" "")))]
18152 "exact_log2 (INTVAL (operands[1])) >= 0
18153 && peep2_regno_dead_p (0, FLAGS_REG)"
18154 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18155 (clobber (reg:CC 17))])]
18156 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18159 [(set (match_operand:DI 0 "register_operand" "")
18160 (mult:DI (match_dup 0)
18161 (match_operand:DI 1 "const_int_operand" "")))]
18162 "exact_log2 (INTVAL (operands[1])) >= 0
18163 && peep2_regno_dead_p (0, FLAGS_REG)"
18164 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
18165 (clobber (reg:CC 17))])]
18166 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18169 [(set (match_operand:SI 0 "register_operand" "")
18170 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
18171 (match_operand:DI 2 "const_int_operand" "")) 0))]
18172 "exact_log2 (INTVAL (operands[2])) >= 0
18173 && REGNO (operands[0]) == REGNO (operands[1])
18174 && peep2_regno_dead_p (0, FLAGS_REG)"
18175 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18176 (clobber (reg:CC 17))])]
18177 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
18179 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
18180 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
18181 ;; many CPUs it is also faster, since special hardware to avoid esp
18182 ;; dependencies is present.
18184 ;; While some of these conversions may be done using splitters, we use peepholes
18185 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
18187 ;; Convert prologue esp subtractions to push.
18188 ;; We need register to push. In order to keep verify_flow_info happy we have
18190 ;; - use scratch and clobber it in order to avoid dependencies
18191 ;; - use already live register
18192 ;; We can't use the second way right now, since there is no reliable way how to
18193 ;; verify that given register is live. First choice will also most likely in
18194 ;; fewer dependencies. On the place of esp adjustments it is very likely that
18195 ;; call clobbered registers are dead. We may want to use base pointer as an
18196 ;; alternative when no register is available later.
18199 [(match_scratch:SI 0 "r")
18200 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18201 (clobber (reg:CC 17))
18202 (clobber (mem:BLK (scratch)))])]
18203 "optimize_size || !TARGET_SUB_ESP_4"
18204 [(clobber (match_dup 0))
18205 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18206 (clobber (mem:BLK (scratch)))])])
18209 [(match_scratch:SI 0 "r")
18210 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18211 (clobber (reg:CC 17))
18212 (clobber (mem:BLK (scratch)))])]
18213 "optimize_size || !TARGET_SUB_ESP_8"
18214 [(clobber (match_dup 0))
18215 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18216 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18217 (clobber (mem:BLK (scratch)))])])
18219 ;; Convert esp subtractions to push.
18221 [(match_scratch:SI 0 "r")
18222 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18223 (clobber (reg:CC 17))])]
18224 "optimize_size || !TARGET_SUB_ESP_4"
18225 [(clobber (match_dup 0))
18226 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18229 [(match_scratch:SI 0 "r")
18230 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18231 (clobber (reg:CC 17))])]
18232 "optimize_size || !TARGET_SUB_ESP_8"
18233 [(clobber (match_dup 0))
18234 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18235 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18237 ;; Convert epilogue deallocator to pop.
18239 [(match_scratch:SI 0 "r")
18240 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18241 (clobber (reg:CC 17))
18242 (clobber (mem:BLK (scratch)))])]
18243 "optimize_size || !TARGET_ADD_ESP_4"
18244 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18245 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18246 (clobber (mem:BLK (scratch)))])]
18249 ;; Two pops case is tricky, since pop causes dependency on destination register.
18250 ;; We use two registers if available.
18252 [(match_scratch:SI 0 "r")
18253 (match_scratch:SI 1 "r")
18254 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18255 (clobber (reg:CC 17))
18256 (clobber (mem:BLK (scratch)))])]
18257 "optimize_size || !TARGET_ADD_ESP_8"
18258 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18259 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18260 (clobber (mem:BLK (scratch)))])
18261 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18262 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18266 [(match_scratch:SI 0 "r")
18267 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18268 (clobber (reg:CC 17))
18269 (clobber (mem:BLK (scratch)))])]
18271 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18272 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18273 (clobber (mem:BLK (scratch)))])
18274 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18275 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18278 ;; Convert esp additions to pop.
18280 [(match_scratch:SI 0 "r")
18281 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18282 (clobber (reg:CC 17))])]
18284 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18285 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18288 ;; Two pops case is tricky, since pop causes dependency on destination register.
18289 ;; We use two registers if available.
18291 [(match_scratch:SI 0 "r")
18292 (match_scratch:SI 1 "r")
18293 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18294 (clobber (reg:CC 17))])]
18296 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18297 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18298 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18299 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18303 [(match_scratch:SI 0 "r")
18304 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18305 (clobber (reg:CC 17))])]
18307 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18308 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18309 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18310 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18313 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
18314 ;; required and register dies.
18317 (compare (match_operand:SI 0 "register_operand" "")
18318 (match_operand:SI 1 "incdec_operand" "")))]
18319 "ix86_match_ccmode (insn, CCGCmode)
18320 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18321 [(parallel [(set (reg:CCGC 17)
18322 (compare:CCGC (match_dup 0)
18324 (clobber (match_dup 0))])]
18329 (compare (match_operand:HI 0 "register_operand" "")
18330 (match_operand:HI 1 "incdec_operand" "")))]
18331 "ix86_match_ccmode (insn, CCGCmode)
18332 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18333 [(parallel [(set (reg:CCGC 17)
18334 (compare:CCGC (match_dup 0)
18336 (clobber (match_dup 0))])]
18341 (compare (match_operand:QI 0 "register_operand" "")
18342 (match_operand:QI 1 "incdec_operand" "")))]
18343 "ix86_match_ccmode (insn, CCGCmode)
18344 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18345 [(parallel [(set (reg:CCGC 17)
18346 (compare:CCGC (match_dup 0)
18348 (clobber (match_dup 0))])]
18351 ;; Convert compares with 128 to shorter add -128
18354 (compare (match_operand:SI 0 "register_operand" "")
18356 "ix86_match_ccmode (insn, CCGCmode)
18357 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18358 [(parallel [(set (reg:CCGC 17)
18359 (compare:CCGC (match_dup 0)
18361 (clobber (match_dup 0))])]
18366 (compare (match_operand:HI 0 "register_operand" "")
18368 "ix86_match_ccmode (insn, CCGCmode)
18369 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18370 [(parallel [(set (reg:CCGC 17)
18371 (compare:CCGC (match_dup 0)
18373 (clobber (match_dup 0))])]
18377 [(match_scratch:DI 0 "r")
18378 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18379 (clobber (reg:CC 17))
18380 (clobber (mem:BLK (scratch)))])]
18381 "optimize_size || !TARGET_SUB_ESP_4"
18382 [(clobber (match_dup 0))
18383 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18384 (clobber (mem:BLK (scratch)))])])
18387 [(match_scratch:DI 0 "r")
18388 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18389 (clobber (reg:CC 17))
18390 (clobber (mem:BLK (scratch)))])]
18391 "optimize_size || !TARGET_SUB_ESP_8"
18392 [(clobber (match_dup 0))
18393 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18394 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18395 (clobber (mem:BLK (scratch)))])])
18397 ;; Convert esp subtractions to push.
18399 [(match_scratch:DI 0 "r")
18400 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18401 (clobber (reg:CC 17))])]
18402 "optimize_size || !TARGET_SUB_ESP_4"
18403 [(clobber (match_dup 0))
18404 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18407 [(match_scratch:DI 0 "r")
18408 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18409 (clobber (reg:CC 17))])]
18410 "optimize_size || !TARGET_SUB_ESP_8"
18411 [(clobber (match_dup 0))
18412 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18413 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18415 ;; Convert epilogue deallocator to pop.
18417 [(match_scratch:DI 0 "r")
18418 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18419 (clobber (reg:CC 17))
18420 (clobber (mem:BLK (scratch)))])]
18421 "optimize_size || !TARGET_ADD_ESP_4"
18422 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18423 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18424 (clobber (mem:BLK (scratch)))])]
18427 ;; Two pops case is tricky, since pop causes dependency on destination register.
18428 ;; We use two registers if available.
18430 [(match_scratch:DI 0 "r")
18431 (match_scratch:DI 1 "r")
18432 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18433 (clobber (reg:CC 17))
18434 (clobber (mem:BLK (scratch)))])]
18435 "optimize_size || !TARGET_ADD_ESP_8"
18436 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18437 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18438 (clobber (mem:BLK (scratch)))])
18439 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18440 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18444 [(match_scratch:DI 0 "r")
18445 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18446 (clobber (reg:CC 17))
18447 (clobber (mem:BLK (scratch)))])]
18449 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18450 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18451 (clobber (mem:BLK (scratch)))])
18452 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18453 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18456 ;; Convert esp additions to pop.
18458 [(match_scratch:DI 0 "r")
18459 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18460 (clobber (reg:CC 17))])]
18462 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18463 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18466 ;; Two pops case is tricky, since pop causes dependency on destination register.
18467 ;; We use two registers if available.
18469 [(match_scratch:DI 0 "r")
18470 (match_scratch:DI 1 "r")
18471 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18472 (clobber (reg:CC 17))])]
18474 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18475 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18476 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18477 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18481 [(match_scratch:DI 0 "r")
18482 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18483 (clobber (reg:CC 17))])]
18485 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18486 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18487 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18488 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18491 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18492 ;; imul $32bit_imm, reg, reg is direct decoded.
18494 [(match_scratch:DI 3 "r")
18495 (parallel [(set (match_operand:DI 0 "register_operand" "")
18496 (mult:DI (match_operand:DI 1 "memory_operand" "")
18497 (match_operand:DI 2 "immediate_operand" "")))
18498 (clobber (reg:CC 17))])]
18499 "TARGET_K8 && !optimize_size
18500 && (GET_CODE (operands[2]) != CONST_INT
18501 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18502 [(set (match_dup 3) (match_dup 1))
18503 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18504 (clobber (reg:CC 17))])]
18508 [(match_scratch:SI 3 "r")
18509 (parallel [(set (match_operand:SI 0 "register_operand" "")
18510 (mult:SI (match_operand:SI 1 "memory_operand" "")
18511 (match_operand:SI 2 "immediate_operand" "")))
18512 (clobber (reg:CC 17))])]
18513 "TARGET_K8 && !optimize_size
18514 && (GET_CODE (operands[2]) != CONST_INT
18515 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18516 [(set (match_dup 3) (match_dup 1))
18517 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18518 (clobber (reg:CC 17))])]
18522 [(match_scratch:SI 3 "r")
18523 (parallel [(set (match_operand:DI 0 "register_operand" "")
18525 (mult:SI (match_operand:SI 1 "memory_operand" "")
18526 (match_operand:SI 2 "immediate_operand" ""))))
18527 (clobber (reg:CC 17))])]
18528 "TARGET_K8 && !optimize_size
18529 && (GET_CODE (operands[2]) != CONST_INT
18530 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18531 [(set (match_dup 3) (match_dup 1))
18532 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18533 (clobber (reg:CC 17))])]
18536 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18537 ;; Convert it into imul reg, reg
18538 ;; It would be better to force assembler to encode instruction using long
18539 ;; immediate, but there is apparently no way to do so.
18541 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18542 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18543 (match_operand:DI 2 "const_int_operand" "")))
18544 (clobber (reg:CC 17))])
18545 (match_scratch:DI 3 "r")]
18546 "TARGET_K8 && !optimize_size
18547 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18548 [(set (match_dup 3) (match_dup 2))
18549 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18550 (clobber (reg:CC 17))])]
18552 if (!rtx_equal_p (operands[0], operands[1]))
18553 emit_move_insn (operands[0], operands[1]);
18557 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18558 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18559 (match_operand:SI 2 "const_int_operand" "")))
18560 (clobber (reg:CC 17))])
18561 (match_scratch:SI 3 "r")]
18562 "TARGET_K8 && !optimize_size
18563 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18564 [(set (match_dup 3) (match_dup 2))
18565 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18566 (clobber (reg:CC 17))])]
18568 if (!rtx_equal_p (operands[0], operands[1]))
18569 emit_move_insn (operands[0], operands[1]);
18573 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18574 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18575 (match_operand:HI 2 "immediate_operand" "")))
18576 (clobber (reg:CC 17))])
18577 (match_scratch:HI 3 "r")]
18578 "TARGET_K8 && !optimize_size"
18579 [(set (match_dup 3) (match_dup 2))
18580 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18581 (clobber (reg:CC 17))])]
18583 if (!rtx_equal_p (operands[0], operands[1]))
18584 emit_move_insn (operands[0], operands[1]);
18587 ;; Call-value patterns last so that the wildcard operand does not
18588 ;; disrupt insn-recog's switch tables.
18590 (define_insn "*call_value_pop_0"
18591 [(set (match_operand 0 "" "")
18592 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18593 (match_operand:SI 2 "" "")))
18594 (set (reg:SI 7) (plus:SI (reg:SI 7)
18595 (match_operand:SI 3 "immediate_operand" "")))]
18598 if (SIBLING_CALL_P (insn))
18601 return "call\t%P1";
18603 [(set_attr "type" "callv")])
18605 (define_insn "*call_value_pop_1"
18606 [(set (match_operand 0 "" "")
18607 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18608 (match_operand:SI 2 "" "")))
18609 (set (reg:SI 7) (plus:SI (reg:SI 7)
18610 (match_operand:SI 3 "immediate_operand" "i")))]
18613 if (constant_call_address_operand (operands[1], QImode))
18615 if (SIBLING_CALL_P (insn))
18618 return "call\t%P1";
18620 if (SIBLING_CALL_P (insn))
18623 return "call\t%A1";
18625 [(set_attr "type" "callv")])
18627 (define_insn "*call_value_0"
18628 [(set (match_operand 0 "" "")
18629 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18630 (match_operand:SI 2 "" "")))]
18633 if (SIBLING_CALL_P (insn))
18636 return "call\t%P1";
18638 [(set_attr "type" "callv")])
18640 (define_insn "*call_value_0_rex64"
18641 [(set (match_operand 0 "" "")
18642 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18643 (match_operand:DI 2 "const_int_operand" "")))]
18646 if (SIBLING_CALL_P (insn))
18649 return "call\t%P1";
18651 [(set_attr "type" "callv")])
18653 (define_insn "*call_value_1"
18654 [(set (match_operand 0 "" "")
18655 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18656 (match_operand:SI 2 "" "")))]
18657 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
18659 if (constant_call_address_operand (operands[1], QImode))
18660 return "call\t%P1";
18661 return "call\t%*%1";
18663 [(set_attr "type" "callv")])
18665 (define_insn "*sibcall_value_1"
18666 [(set (match_operand 0 "" "")
18667 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
18668 (match_operand:SI 2 "" "")))]
18669 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
18671 if (constant_call_address_operand (operands[1], QImode))
18673 return "jmp\t%*%1";
18675 [(set_attr "type" "callv")])
18677 (define_insn "*call_value_1_rex64"
18678 [(set (match_operand 0 "" "")
18679 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
18680 (match_operand:DI 2 "" "")))]
18681 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
18683 if (constant_call_address_operand (operands[1], QImode))
18684 return "call\t%P1";
18685 return "call\t%A1";
18687 [(set_attr "type" "callv")])
18689 (define_insn "*sibcall_value_1_rex64"
18690 [(set (match_operand 0 "" "")
18691 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
18692 (match_operand:DI 2 "" "")))]
18693 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18695 [(set_attr "type" "callv")])
18697 (define_insn "*sibcall_value_1_rex64_v"
18698 [(set (match_operand 0 "" "")
18699 (call (mem:QI (reg:DI 40))
18700 (match_operand:DI 1 "" "")))]
18701 "SIBLING_CALL_P (insn) && TARGET_64BIT"
18703 [(set_attr "type" "callv")])
18705 (define_insn "trap"
18706 [(trap_if (const_int 1) (const_int 5))]
18710 ;;; ix86 doesn't have conditional trap instructions, but we fake them
18711 ;;; for the sake of bounds checking. By emitting bounds checks as
18712 ;;; conditional traps rather than as conditional jumps around
18713 ;;; unconditional traps we avoid introducing spurious basic-block
18714 ;;; boundaries and facilitate elimination of redundant checks. In
18715 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
18718 ;;; FIXME: Static branch prediction rules for ix86 are such that
18719 ;;; forward conditional branches predict as untaken. As implemented
18720 ;;; below, pseudo conditional traps violate that rule. We should use
18721 ;;; .pushsection/.popsection to place all of the `int 5's in a special
18722 ;;; section loaded at the end of the text segment and branch forward
18723 ;;; there on bounds-failure, and then jump back immediately (in case
18724 ;;; the system chooses to ignore bounds violations, or to report
18725 ;;; violations and continue execution).
18727 (define_expand "conditional_trap"
18728 [(trap_if (match_operator 0 "comparison_operator"
18729 [(match_dup 2) (const_int 0)])
18730 (match_operand 1 "const_int_operand" ""))]
18733 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
18734 ix86_expand_compare (GET_CODE (operands[0]),
18740 (define_insn "*conditional_trap_1"
18741 [(trap_if (match_operator 0 "comparison_operator"
18742 [(reg 17) (const_int 0)])
18743 (match_operand 1 "const_int_operand" ""))]
18746 operands[2] = gen_label_rtx ();
18747 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
18748 (*targetm.asm_out.internal_label) (asm_out_file, "L",
18749 CODE_LABEL_NUMBER (operands[2]));
18753 ;; Pentium III SIMD instructions.
18755 ;; Moves for SSE/MMX regs.
18757 (define_insn "movv4sf_internal"
18758 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
18759 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
18763 movaps\t{%1, %0|%0, %1}
18764 movaps\t{%1, %0|%0, %1}"
18765 [(set_attr "type" "ssemov")
18766 (set_attr "mode" "V4SF")])
18769 [(set (match_operand:V4SF 0 "register_operand" "")
18770 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
18772 [(set (match_dup 0)
18774 (vec_duplicate:V4SF (match_dup 1))
18778 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
18779 operands[2] = CONST0_RTX (V4SFmode);
18782 (define_insn "movv4si_internal"
18783 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
18784 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
18787 switch (which_alternative)
18790 if (get_attr_mode (insn) == MODE_V4SF)
18791 return "xorps\t%0, %0";
18793 return "pxor\t%0, %0";
18796 if (get_attr_mode (insn) == MODE_V4SF)
18797 return "movaps\t{%1, %0|%0, %1}";
18799 return "movdqa\t{%1, %0|%0, %1}";
18804 [(set_attr "type" "ssemov")
18806 (cond [(eq_attr "alternative" "0,1")
18808 (ne (symbol_ref "optimize_size")
18810 (const_string "V4SF")
18811 (const_string "TI"))
18812 (eq_attr "alternative" "2")
18814 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18816 (ne (symbol_ref "optimize_size")
18818 (const_string "V4SF")
18819 (const_string "TI"))]
18820 (const_string "TI")))])
18822 (define_insn "movv2di_internal"
18823 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
18824 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
18827 switch (which_alternative)
18830 if (get_attr_mode (insn) == MODE_V4SF)
18831 return "xorps\t%0, %0";
18833 return "pxor\t%0, %0";
18836 if (get_attr_mode (insn) == MODE_V4SF)
18837 return "movaps\t{%1, %0|%0, %1}";
18839 return "movdqa\t{%1, %0|%0, %1}";
18844 [(set_attr "type" "ssemov")
18846 (cond [(eq_attr "alternative" "0,1")
18848 (ne (symbol_ref "optimize_size")
18850 (const_string "V4SF")
18851 (const_string "TI"))
18852 (eq_attr "alternative" "2")
18854 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18856 (ne (symbol_ref "optimize_size")
18858 (const_string "V4SF")
18859 (const_string "TI"))]
18860 (const_string "TI")))])
18863 [(set (match_operand:V2DF 0 "register_operand" "")
18864 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
18866 [(set (match_dup 0)
18868 (vec_duplicate:V2DF (match_dup 1))
18872 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
18873 operands[2] = CONST0_RTX (V2DFmode);
18876 (define_insn "movv8qi_internal"
18877 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
18878 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
18880 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18883 movq\t{%1, %0|%0, %1}
18884 movq\t{%1, %0|%0, %1}"
18885 [(set_attr "type" "mmxmov")
18886 (set_attr "mode" "DI")])
18888 (define_insn "movv4hi_internal"
18889 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
18890 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
18892 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18895 movq\t{%1, %0|%0, %1}
18896 movq\t{%1, %0|%0, %1}"
18897 [(set_attr "type" "mmxmov")
18898 (set_attr "mode" "DI")])
18900 (define_insn "movv2si_internal"
18901 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
18902 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
18904 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18907 movq\t{%1, %0|%0, %1}
18908 movq\t{%1, %0|%0, %1}"
18909 [(set_attr "type" "mmxcvt")
18910 (set_attr "mode" "DI")])
18912 (define_insn "movv2sf_internal"
18913 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
18914 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
18916 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18919 movq\t{%1, %0|%0, %1}
18920 movq\t{%1, %0|%0, %1}"
18921 [(set_attr "type" "mmxcvt")
18922 (set_attr "mode" "DI")])
18924 (define_expand "movti"
18925 [(set (match_operand:TI 0 "nonimmediate_operand" "")
18926 (match_operand:TI 1 "nonimmediate_operand" ""))]
18927 "TARGET_SSE || TARGET_64BIT"
18930 ix86_expand_move (TImode, operands);
18932 ix86_expand_vector_move (TImode, operands);
18936 (define_insn "movv2df_internal"
18937 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
18938 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
18940 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18942 switch (which_alternative)
18945 if (get_attr_mode (insn) == MODE_V4SF)
18946 return "xorps\t%0, %0";
18948 return "xorpd\t%0, %0";
18951 if (get_attr_mode (insn) == MODE_V4SF)
18952 return "movaps\t{%1, %0|%0, %1}";
18954 return "movapd\t{%1, %0|%0, %1}";
18959 [(set_attr "type" "ssemov")
18961 (cond [(eq_attr "alternative" "0,1")
18963 (ne (symbol_ref "optimize_size")
18965 (const_string "V4SF")
18966 (const_string "V2DF"))
18967 (eq_attr "alternative" "2")
18969 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
18971 (ne (symbol_ref "optimize_size")
18973 (const_string "V4SF")
18974 (const_string "V2DF"))]
18975 (const_string "V2DF")))])
18977 (define_insn "movv8hi_internal"
18978 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
18979 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
18981 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
18983 switch (which_alternative)
18986 if (get_attr_mode (insn) == MODE_V4SF)
18987 return "xorps\t%0, %0";
18989 return "pxor\t%0, %0";
18992 if (get_attr_mode (insn) == MODE_V4SF)
18993 return "movaps\t{%1, %0|%0, %1}";
18995 return "movdqa\t{%1, %0|%0, %1}";
19000 [(set_attr "type" "ssemov")
19002 (cond [(eq_attr "alternative" "0,1")
19004 (ne (symbol_ref "optimize_size")
19006 (const_string "V4SF")
19007 (const_string "TI"))
19008 (eq_attr "alternative" "2")
19010 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19012 (ne (symbol_ref "optimize_size")
19014 (const_string "V4SF")
19015 (const_string "TI"))]
19016 (const_string "TI")))])
19018 (define_insn "movv16qi_internal"
19019 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
19020 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
19022 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19024 switch (which_alternative)
19027 if (get_attr_mode (insn) == MODE_V4SF)
19028 return "xorps\t%0, %0";
19030 return "pxor\t%0, %0";
19033 if (get_attr_mode (insn) == MODE_V4SF)
19034 return "movaps\t{%1, %0|%0, %1}";
19036 return "movdqa\t{%1, %0|%0, %1}";
19041 [(set_attr "type" "ssemov")
19043 (cond [(eq_attr "alternative" "0,1")
19045 (ne (symbol_ref "optimize_size")
19047 (const_string "V4SF")
19048 (const_string "TI"))
19049 (eq_attr "alternative" "2")
19051 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19053 (ne (symbol_ref "optimize_size")
19055 (const_string "V4SF")
19056 (const_string "TI"))]
19057 (const_string "TI")))])
19059 (define_expand "movv2df"
19060 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
19061 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
19064 ix86_expand_vector_move (V2DFmode, operands);
19068 (define_expand "movv8hi"
19069 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
19070 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
19073 ix86_expand_vector_move (V8HImode, operands);
19077 (define_expand "movv16qi"
19078 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
19079 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
19082 ix86_expand_vector_move (V16QImode, operands);
19086 (define_expand "movv4sf"
19087 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19088 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
19091 ix86_expand_vector_move (V4SFmode, operands);
19095 (define_expand "movv4si"
19096 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
19097 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
19100 ix86_expand_vector_move (V4SImode, operands);
19104 (define_expand "movv2di"
19105 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
19106 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
19109 ix86_expand_vector_move (V2DImode, operands);
19113 (define_expand "movv2si"
19114 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
19115 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
19118 ix86_expand_vector_move (V2SImode, operands);
19122 (define_expand "movv4hi"
19123 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
19124 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
19127 ix86_expand_vector_move (V4HImode, operands);
19131 (define_expand "movv8qi"
19132 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
19133 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
19136 ix86_expand_vector_move (V8QImode, operands);
19140 (define_expand "movv2sf"
19141 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19142 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19145 ix86_expand_vector_move (V2SFmode, operands);
19149 (define_insn "*pushti"
19150 [(set (match_operand:TI 0 "push_operand" "=<")
19151 (match_operand:TI 1 "register_operand" "x"))]
19155 (define_insn "*pushv2df"
19156 [(set (match_operand:V2DF 0 "push_operand" "=<")
19157 (match_operand:V2DF 1 "register_operand" "x"))]
19161 (define_insn "*pushv2di"
19162 [(set (match_operand:V2DI 0 "push_operand" "=<")
19163 (match_operand:V2DI 1 "register_operand" "x"))]
19167 (define_insn "*pushv8hi"
19168 [(set (match_operand:V8HI 0 "push_operand" "=<")
19169 (match_operand:V8HI 1 "register_operand" "x"))]
19173 (define_insn "*pushv16qi"
19174 [(set (match_operand:V16QI 0 "push_operand" "=<")
19175 (match_operand:V16QI 1 "register_operand" "x"))]
19179 (define_insn "*pushv4sf"
19180 [(set (match_operand:V4SF 0 "push_operand" "=<")
19181 (match_operand:V4SF 1 "register_operand" "x"))]
19185 (define_insn "*pushv4si"
19186 [(set (match_operand:V4SI 0 "push_operand" "=<")
19187 (match_operand:V4SI 1 "register_operand" "x"))]
19191 (define_insn "*pushv2si"
19192 [(set (match_operand:V2SI 0 "push_operand" "=<")
19193 (match_operand:V2SI 1 "register_operand" "y"))]
19197 (define_insn "*pushv4hi"
19198 [(set (match_operand:V4HI 0 "push_operand" "=<")
19199 (match_operand:V4HI 1 "register_operand" "y"))]
19203 (define_insn "*pushv8qi"
19204 [(set (match_operand:V8QI 0 "push_operand" "=<")
19205 (match_operand:V8QI 1 "register_operand" "y"))]
19209 (define_insn "*pushv2sf"
19210 [(set (match_operand:V2SF 0 "push_operand" "=<")
19211 (match_operand:V2SF 1 "register_operand" "y"))]
19216 [(set (match_operand 0 "push_operand" "")
19217 (match_operand 1 "register_operand" ""))]
19218 "!TARGET_64BIT && reload_completed
19219 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19220 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
19221 (set (match_dup 2) (match_dup 1))]
19222 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19223 stack_pointer_rtx);
19224 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19227 [(set (match_operand 0 "push_operand" "")
19228 (match_operand 1 "register_operand" ""))]
19229 "TARGET_64BIT && reload_completed
19230 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19231 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
19232 (set (match_dup 2) (match_dup 1))]
19233 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19234 stack_pointer_rtx);
19235 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19238 (define_insn "movti_internal"
19239 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19240 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19241 "TARGET_SSE && !TARGET_64BIT
19242 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19244 switch (which_alternative)
19247 if (get_attr_mode (insn) == MODE_V4SF)
19248 return "xorps\t%0, %0";
19250 return "pxor\t%0, %0";
19253 if (get_attr_mode (insn) == MODE_V4SF)
19254 return "movaps\t{%1, %0|%0, %1}";
19256 return "movdqa\t{%1, %0|%0, %1}";
19261 [(set_attr "type" "ssemov,ssemov,ssemov")
19263 (cond [(eq_attr "alternative" "0,1")
19265 (ne (symbol_ref "optimize_size")
19267 (const_string "V4SF")
19268 (const_string "TI"))
19269 (eq_attr "alternative" "2")
19271 (ne (symbol_ref "optimize_size")
19273 (const_string "V4SF")
19274 (const_string "TI"))]
19275 (const_string "TI")))])
19277 (define_insn "*movti_rex64"
19278 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
19279 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
19281 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19283 switch (which_alternative)
19289 if (get_attr_mode (insn) == MODE_V4SF)
19290 return "xorps\t%0, %0";
19292 return "pxor\t%0, %0";
19295 if (get_attr_mode (insn) == MODE_V4SF)
19296 return "movaps\t{%1, %0|%0, %1}";
19298 return "movdqa\t{%1, %0|%0, %1}";
19303 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19305 (cond [(eq_attr "alternative" "2,3")
19307 (ne (symbol_ref "optimize_size")
19309 (const_string "V4SF")
19310 (const_string "TI"))
19311 (eq_attr "alternative" "4")
19313 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19315 (ne (symbol_ref "optimize_size")
19317 (const_string "V4SF")
19318 (const_string "TI"))]
19319 (const_string "DI")))])
19322 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19323 (match_operand:TI 1 "general_operand" ""))]
19324 "reload_completed && !SSE_REG_P (operands[0])
19325 && !SSE_REG_P (operands[1])"
19327 "ix86_split_long_move (operands); DONE;")
19329 ;; These two patterns are useful for specifying exactly whether to use
19330 ;; movaps or movups
19331 (define_insn "sse_movaps"
19332 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19333 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19336 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19337 "movaps\t{%1, %0|%0, %1}"
19338 [(set_attr "type" "ssemov,ssemov")
19339 (set_attr "mode" "V4SF")])
19341 (define_insn "sse_movups"
19342 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19343 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19346 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19347 "movups\t{%1, %0|%0, %1}"
19348 [(set_attr "type" "ssecvt,ssecvt")
19349 (set_attr "mode" "V4SF")])
19352 ;; SSE Strange Moves.
19354 (define_insn "sse_movmskps"
19355 [(set (match_operand:SI 0 "register_operand" "=r")
19356 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19359 "movmskps\t{%1, %0|%0, %1}"
19360 [(set_attr "type" "ssecvt")
19361 (set_attr "mode" "V4SF")])
19363 (define_insn "mmx_pmovmskb"
19364 [(set (match_operand:SI 0 "register_operand" "=r")
19365 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19367 "TARGET_SSE || TARGET_3DNOW_A"
19368 "pmovmskb\t{%1, %0|%0, %1}"
19369 [(set_attr "type" "ssecvt")
19370 (set_attr "mode" "V4SF")])
19373 (define_insn "mmx_maskmovq"
19374 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19375 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19376 (match_operand:V8QI 2 "register_operand" "y")]
19378 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19379 ;; @@@ check ordering of operands in intel/nonintel syntax
19380 "maskmovq\t{%2, %1|%1, %2}"
19381 [(set_attr "type" "mmxcvt")
19382 (set_attr "mode" "DI")])
19384 (define_insn "mmx_maskmovq_rex"
19385 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19386 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19387 (match_operand:V8QI 2 "register_operand" "y")]
19389 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19390 ;; @@@ check ordering of operands in intel/nonintel syntax
19391 "maskmovq\t{%2, %1|%1, %2}"
19392 [(set_attr "type" "mmxcvt")
19393 (set_attr "mode" "DI")])
19395 (define_insn "sse_movntv4sf"
19396 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19397 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19400 "movntps\t{%1, %0|%0, %1}"
19401 [(set_attr "type" "ssemov")
19402 (set_attr "mode" "V4SF")])
19404 (define_insn "sse_movntdi"
19405 [(set (match_operand:DI 0 "memory_operand" "=m")
19406 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19408 "TARGET_SSE || TARGET_3DNOW_A"
19409 "movntq\t{%1, %0|%0, %1}"
19410 [(set_attr "type" "mmxmov")
19411 (set_attr "mode" "DI")])
19413 (define_insn "sse_movhlps"
19414 [(set (match_operand:V4SF 0 "register_operand" "=x")
19416 (match_operand:V4SF 1 "register_operand" "0")
19417 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19418 (parallel [(const_int 2)
19424 "movhlps\t{%2, %0|%0, %2}"
19425 [(set_attr "type" "ssecvt")
19426 (set_attr "mode" "V4SF")])
19428 (define_insn "sse_movlhps"
19429 [(set (match_operand:V4SF 0 "register_operand" "=x")
19431 (match_operand:V4SF 1 "register_operand" "0")
19432 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19433 (parallel [(const_int 2)
19439 "movlhps\t{%2, %0|%0, %2}"
19440 [(set_attr "type" "ssecvt")
19441 (set_attr "mode" "V4SF")])
19443 (define_insn "sse_movhps"
19444 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19446 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19447 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19450 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19451 "movhps\t{%2, %0|%0, %2}"
19452 [(set_attr "type" "ssecvt")
19453 (set_attr "mode" "V4SF")])
19455 (define_insn "sse_movlps"
19456 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19458 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19459 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19462 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19463 "movlps\t{%2, %0|%0, %2}"
19464 [(set_attr "type" "ssecvt")
19465 (set_attr "mode" "V4SF")])
19467 (define_expand "sse_loadss"
19468 [(match_operand:V4SF 0 "register_operand" "")
19469 (match_operand:SF 1 "memory_operand" "")]
19472 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19473 CONST0_RTX (V4SFmode)));
19477 (define_insn "sse_loadss_1"
19478 [(set (match_operand:V4SF 0 "register_operand" "=x")
19480 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19481 (match_operand:V4SF 2 "const0_operand" "X")
19484 "movss\t{%1, %0|%0, %1}"
19485 [(set_attr "type" "ssemov")
19486 (set_attr "mode" "SF")])
19488 (define_insn "sse_movss"
19489 [(set (match_operand:V4SF 0 "register_operand" "=x")
19491 (match_operand:V4SF 1 "register_operand" "0")
19492 (match_operand:V4SF 2 "register_operand" "x")
19495 "movss\t{%2, %0|%0, %2}"
19496 [(set_attr "type" "ssemov")
19497 (set_attr "mode" "SF")])
19499 (define_insn "sse_storess"
19500 [(set (match_operand:SF 0 "memory_operand" "=m")
19502 (match_operand:V4SF 1 "register_operand" "x")
19503 (parallel [(const_int 0)])))]
19505 "movss\t{%1, %0|%0, %1}"
19506 [(set_attr "type" "ssemov")
19507 (set_attr "mode" "SF")])
19509 (define_insn "sse_shufps"
19510 [(set (match_operand:V4SF 0 "register_operand" "=x")
19511 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19512 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19513 (match_operand:SI 3 "immediate_operand" "i")]
19516 ;; @@@ check operand order for intel/nonintel syntax
19517 "shufps\t{%3, %2, %0|%0, %2, %3}"
19518 [(set_attr "type" "ssecvt")
19519 (set_attr "mode" "V4SF")])
19524 (define_insn "addv4sf3"
19525 [(set (match_operand:V4SF 0 "register_operand" "=x")
19526 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19527 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19529 "addps\t{%2, %0|%0, %2}"
19530 [(set_attr "type" "sseadd")
19531 (set_attr "mode" "V4SF")])
19533 (define_insn "vmaddv4sf3"
19534 [(set (match_operand:V4SF 0 "register_operand" "=x")
19536 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19537 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19541 "addss\t{%2, %0|%0, %2}"
19542 [(set_attr "type" "sseadd")
19543 (set_attr "mode" "SF")])
19545 (define_insn "subv4sf3"
19546 [(set (match_operand:V4SF 0 "register_operand" "=x")
19547 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19548 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19550 "subps\t{%2, %0|%0, %2}"
19551 [(set_attr "type" "sseadd")
19552 (set_attr "mode" "V4SF")])
19554 (define_insn "vmsubv4sf3"
19555 [(set (match_operand:V4SF 0 "register_operand" "=x")
19557 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19558 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19562 "subss\t{%2, %0|%0, %2}"
19563 [(set_attr "type" "sseadd")
19564 (set_attr "mode" "SF")])
19566 (define_insn "mulv4sf3"
19567 [(set (match_operand:V4SF 0 "register_operand" "=x")
19568 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19569 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19571 "mulps\t{%2, %0|%0, %2}"
19572 [(set_attr "type" "ssemul")
19573 (set_attr "mode" "V4SF")])
19575 (define_insn "vmmulv4sf3"
19576 [(set (match_operand:V4SF 0 "register_operand" "=x")
19578 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19579 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19583 "mulss\t{%2, %0|%0, %2}"
19584 [(set_attr "type" "ssemul")
19585 (set_attr "mode" "SF")])
19587 (define_insn "divv4sf3"
19588 [(set (match_operand:V4SF 0 "register_operand" "=x")
19589 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19590 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19592 "divps\t{%2, %0|%0, %2}"
19593 [(set_attr "type" "ssediv")
19594 (set_attr "mode" "V4SF")])
19596 (define_insn "vmdivv4sf3"
19597 [(set (match_operand:V4SF 0 "register_operand" "=x")
19599 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
19600 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19604 "divss\t{%2, %0|%0, %2}"
19605 [(set_attr "type" "ssediv")
19606 (set_attr "mode" "SF")])
19609 ;; SSE square root/reciprocal
19611 (define_insn "rcpv4sf2"
19612 [(set (match_operand:V4SF 0 "register_operand" "=x")
19614 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
19616 "rcpps\t{%1, %0|%0, %1}"
19617 [(set_attr "type" "sse")
19618 (set_attr "mode" "V4SF")])
19620 (define_insn "vmrcpv4sf2"
19621 [(set (match_operand:V4SF 0 "register_operand" "=x")
19623 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19625 (match_operand:V4SF 2 "register_operand" "0")
19628 "rcpss\t{%1, %0|%0, %1}"
19629 [(set_attr "type" "sse")
19630 (set_attr "mode" "SF")])
19632 (define_insn "rsqrtv4sf2"
19633 [(set (match_operand:V4SF 0 "register_operand" "=x")
19635 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
19637 "rsqrtps\t{%1, %0|%0, %1}"
19638 [(set_attr "type" "sse")
19639 (set_attr "mode" "V4SF")])
19641 (define_insn "vmrsqrtv4sf2"
19642 [(set (match_operand:V4SF 0 "register_operand" "=x")
19644 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
19646 (match_operand:V4SF 2 "register_operand" "0")
19649 "rsqrtss\t{%1, %0|%0, %1}"
19650 [(set_attr "type" "sse")
19651 (set_attr "mode" "SF")])
19653 (define_insn "sqrtv4sf2"
19654 [(set (match_operand:V4SF 0 "register_operand" "=x")
19655 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
19657 "sqrtps\t{%1, %0|%0, %1}"
19658 [(set_attr "type" "sse")
19659 (set_attr "mode" "V4SF")])
19661 (define_insn "vmsqrtv4sf2"
19662 [(set (match_operand:V4SF 0 "register_operand" "=x")
19664 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
19665 (match_operand:V4SF 2 "register_operand" "0")
19668 "sqrtss\t{%1, %0|%0, %1}"
19669 [(set_attr "type" "sse")
19670 (set_attr "mode" "SF")])
19672 ;; SSE logical operations.
19674 ;; SSE defines logical operations on floating point values. This brings
19675 ;; interesting challenge to RTL representation where logicals are only valid
19676 ;; on integral types. We deal with this by representing the floating point
19677 ;; logical as logical on arguments casted to TImode as this is what hardware
19678 ;; really does. Unfortunately hardware requires the type information to be
19679 ;; present and thus we must avoid subregs from being simplified and eliminated
19680 ;; in later compilation phases.
19682 ;; We have following variants from each instruction:
19683 ;; sse_andsf3 - the operation taking V4SF vector operands
19684 ;; and doing TImode cast on them
19685 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
19686 ;; TImode, since backend insist on eliminating casts
19687 ;; on memory operands
19688 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
19689 ;; We can not accept memory operand here as instruction reads
19690 ;; whole scalar. This is generated only post reload by GCC
19691 ;; scalar float operations that expands to logicals (fabs)
19692 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
19693 ;; memory operand. Eventually combine can be able
19694 ;; to synthesize these using splitter.
19695 ;; sse2_anddf3, *sse2_anddf3_memory
19698 ;; These are not called andti3 etc. because we really really don't want
19699 ;; the compiler to widen DImode ands to TImode ands and then try to move
19700 ;; into DImode subregs of SSE registers, and them together, and move out
19701 ;; of DImode subregs again!
19702 ;; SSE1 single precision floating point logical operation
19703 (define_expand "sse_andv4sf3"
19704 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19705 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19706 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19710 (define_insn "*sse_andv4sf3"
19711 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19712 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19713 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19715 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19716 "andps\t{%2, %0|%0, %2}"
19717 [(set_attr "type" "sselog")
19718 (set_attr "mode" "V4SF")])
19720 (define_insn "*sse_andsf3"
19721 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19722 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19723 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19725 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19726 "andps\t{%2, %0|%0, %2}"
19727 [(set_attr "type" "sselog")
19728 (set_attr "mode" "V4SF")])
19730 (define_expand "sse_nandv4sf3"
19731 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19732 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
19733 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19737 (define_insn "*sse_nandv4sf3"
19738 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19739 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19740 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19742 "andnps\t{%2, %0|%0, %2}"
19743 [(set_attr "type" "sselog")
19744 (set_attr "mode" "V4SF")])
19746 (define_insn "*sse_nandsf3"
19747 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19748 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19749 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19751 "andnps\t{%2, %0|%0, %2}"
19752 [(set_attr "type" "sselog")
19753 (set_attr "mode" "V4SF")])
19755 (define_expand "sse_iorv4sf3"
19756 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19757 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19758 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19762 (define_insn "*sse_iorv4sf3"
19763 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19764 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19765 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19767 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19768 "orps\t{%2, %0|%0, %2}"
19769 [(set_attr "type" "sselog")
19770 (set_attr "mode" "V4SF")])
19772 (define_insn "*sse_iorsf3"
19773 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19774 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19775 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19777 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19778 "orps\t{%2, %0|%0, %2}"
19779 [(set_attr "type" "sselog")
19780 (set_attr "mode" "V4SF")])
19782 (define_expand "sse_xorv4sf3"
19783 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
19784 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
19785 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
19787 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19790 (define_insn "*sse_xorv4sf3"
19791 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
19792 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19793 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19795 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19796 "xorps\t{%2, %0|%0, %2}"
19797 [(set_attr "type" "sselog")
19798 (set_attr "mode" "V4SF")])
19800 (define_insn "*sse_xorsf3"
19801 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
19802 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19803 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19805 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19806 "xorps\t{%2, %0|%0, %2}"
19807 [(set_attr "type" "sselog")
19808 (set_attr "mode" "V4SF")])
19810 ;; SSE2 double precision floating point logical operation
19812 (define_expand "sse2_andv2df3"
19813 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19814 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19815 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19819 (define_insn "*sse2_andv2df3"
19820 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19821 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19822 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19824 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19825 "andpd\t{%2, %0|%0, %2}"
19826 [(set_attr "type" "sselog")
19827 (set_attr "mode" "V2DF")])
19829 (define_insn "*sse2_andv2df3"
19830 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19831 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19832 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19834 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19835 "andpd\t{%2, %0|%0, %2}"
19836 [(set_attr "type" "sselog")
19837 (set_attr "mode" "V2DF")])
19839 (define_expand "sse2_nandv2df3"
19840 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19841 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
19842 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19846 (define_insn "*sse2_nandv2df3"
19847 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19848 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19849 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19851 "andnpd\t{%2, %0|%0, %2}"
19852 [(set_attr "type" "sselog")
19853 (set_attr "mode" "V2DF")])
19855 (define_insn "*sse_nandti3_df"
19856 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
19857 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19858 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
19860 "andnpd\t{%2, %0|%0, %2}"
19861 [(set_attr "type" "sselog")
19862 (set_attr "mode" "V2DF")])
19864 (define_expand "sse2_iorv2df3"
19865 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19866 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
19867 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19871 (define_insn "*sse2_iorv2df3"
19872 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19873 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19874 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19876 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19877 "orpd\t{%2, %0|%0, %2}"
19878 [(set_attr "type" "sselog")
19879 (set_attr "mode" "V2DF")])
19881 (define_insn "*sse2_iordf3"
19882 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19883 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19884 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19886 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19887 "orpd\t{%2, %0|%0, %2}"
19888 [(set_attr "type" "sselog")
19889 (set_attr "mode" "V2DF")])
19891 (define_expand "sse2_xorv2df3"
19892 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
19893 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
19894 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
19898 (define_insn "*sse2_xorv2df3"
19899 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
19900 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19901 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19903 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19904 "xorpd\t{%2, %0|%0, %2}"
19905 [(set_attr "type" "sselog")
19906 (set_attr "mode" "V2DF")])
19908 (define_insn "*sse2_xordf3"
19909 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
19910 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19911 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19913 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19914 "xorpd\t{%2, %0|%0, %2}"
19915 [(set_attr "type" "sselog")
19916 (set_attr "mode" "V2DF")])
19918 ;; SSE2 integral logicals. These patterns must always come after floating
19919 ;; point ones since we don't want compiler to use integer opcodes on floating
19920 ;; point SSE values to avoid matching of subregs in the match_operand.
19921 (define_insn "*sse2_andti3"
19922 [(set (match_operand:TI 0 "register_operand" "=x")
19923 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19924 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19926 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19927 "pand\t{%2, %0|%0, %2}"
19928 [(set_attr "type" "sselog")
19929 (set_attr "mode" "TI")])
19931 (define_insn "sse2_andv2di3"
19932 [(set (match_operand:V2DI 0 "register_operand" "=x")
19933 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19934 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19936 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19937 "pand\t{%2, %0|%0, %2}"
19938 [(set_attr "type" "sselog")
19939 (set_attr "mode" "TI")])
19941 (define_insn "*sse2_nandti3"
19942 [(set (match_operand:TI 0 "register_operand" "=x")
19943 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
19944 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19946 "pandn\t{%2, %0|%0, %2}"
19947 [(set_attr "type" "sselog")
19948 (set_attr "mode" "TI")])
19950 (define_insn "sse2_nandv2di3"
19951 [(set (match_operand:V2DI 0 "register_operand" "=x")
19952 (and:V2DI (not:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "0"))
19953 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19955 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19956 "pandn\t{%2, %0|%0, %2}"
19957 [(set_attr "type" "sselog")
19958 (set_attr "mode" "TI")])
19960 (define_insn "*sse2_iorti3"
19961 [(set (match_operand:TI 0 "register_operand" "=x")
19962 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19963 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19965 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19966 "por\t{%2, %0|%0, %2}"
19967 [(set_attr "type" "sselog")
19968 (set_attr "mode" "TI")])
19970 (define_insn "sse2_iorv2di3"
19971 [(set (match_operand:V2DI 0 "register_operand" "=x")
19972 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19973 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19975 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19976 "por\t{%2, %0|%0, %2}"
19977 [(set_attr "type" "sselog")
19978 (set_attr "mode" "TI")])
19980 (define_insn "*sse2_xorti3"
19981 [(set (match_operand:TI 0 "register_operand" "=x")
19982 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
19983 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
19985 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19986 "pxor\t{%2, %0|%0, %2}"
19987 [(set_attr "type" "sselog")
19988 (set_attr "mode" "TI")])
19990 (define_insn "sse2_xorv2di3"
19991 [(set (match_operand:V2DI 0 "register_operand" "=x")
19992 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
19993 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
19995 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
19996 "pxor\t{%2, %0|%0, %2}"
19997 [(set_attr "type" "sselog")
19998 (set_attr "mode" "TI")])
20000 ;; Use xor, but don't show input operands so they aren't live before
20002 (define_insn "sse_clrv4sf"
20003 [(set (match_operand:V4SF 0 "register_operand" "=x")
20004 (match_operand:V4SF 1 "const0_operand" "X"))]
20007 if (get_attr_mode (insn) == MODE_TI)
20008 return "pxor\t{%0, %0|%0, %0}";
20010 return "xorps\t{%0, %0|%0, %0}";
20012 [(set_attr "type" "sselog")
20013 (set_attr "memory" "none")
20016 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
20018 (ne (symbol_ref "TARGET_SSE2")
20020 (eq (symbol_ref "optimize_size")
20022 (const_string "TI")
20023 (const_string "V4SF")))])
20025 ;; Use xor, but don't show input operands so they aren't live before
20027 (define_insn "sse_clrv2df"
20028 [(set (match_operand:V2DF 0 "register_operand" "=x")
20029 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
20031 "xorpd\t{%0, %0|%0, %0}"
20032 [(set_attr "type" "sselog")
20033 (set_attr "memory" "none")
20034 (set_attr "mode" "V4SF")])
20036 ;; SSE mask-generating compares
20038 (define_insn "maskcmpv4sf3"
20039 [(set (match_operand:V4SI 0 "register_operand" "=x")
20040 (match_operator:V4SI 3 "sse_comparison_operator"
20041 [(match_operand:V4SF 1 "register_operand" "0")
20042 (match_operand:V4SF 2 "register_operand" "x")]))]
20044 "cmp%D3ps\t{%2, %0|%0, %2}"
20045 [(set_attr "type" "ssecmp")
20046 (set_attr "mode" "V4SF")])
20048 (define_insn "maskncmpv4sf3"
20049 [(set (match_operand:V4SI 0 "register_operand" "=x")
20051 (match_operator:V4SI 3 "sse_comparison_operator"
20052 [(match_operand:V4SF 1 "register_operand" "0")
20053 (match_operand:V4SF 2 "register_operand" "x")])))]
20056 if (GET_CODE (operands[3]) == UNORDERED)
20057 return "cmpordps\t{%2, %0|%0, %2}";
20059 return "cmpn%D3ps\t{%2, %0|%0, %2}";
20061 [(set_attr "type" "ssecmp")
20062 (set_attr "mode" "V4SF")])
20064 (define_insn "vmmaskcmpv4sf3"
20065 [(set (match_operand:V4SI 0 "register_operand" "=x")
20067 (match_operator:V4SI 3 "sse_comparison_operator"
20068 [(match_operand:V4SF 1 "register_operand" "0")
20069 (match_operand:V4SF 2 "register_operand" "x")])
20070 (subreg:V4SI (match_dup 1) 0)
20073 "cmp%D3ss\t{%2, %0|%0, %2}"
20074 [(set_attr "type" "ssecmp")
20075 (set_attr "mode" "SF")])
20077 (define_insn "vmmaskncmpv4sf3"
20078 [(set (match_operand:V4SI 0 "register_operand" "=x")
20081 (match_operator:V4SI 3 "sse_comparison_operator"
20082 [(match_operand:V4SF 1 "register_operand" "0")
20083 (match_operand:V4SF 2 "register_operand" "x")]))
20084 (subreg:V4SI (match_dup 1) 0)
20088 if (GET_CODE (operands[3]) == UNORDERED)
20089 return "cmpordss\t{%2, %0|%0, %2}";
20091 return "cmpn%D3ss\t{%2, %0|%0, %2}";
20093 [(set_attr "type" "ssecmp")
20094 (set_attr "mode" "SF")])
20096 (define_insn "sse_comi"
20097 [(set (reg:CCFP 17)
20098 (compare:CCFP (vec_select:SF
20099 (match_operand:V4SF 0 "register_operand" "x")
20100 (parallel [(const_int 0)]))
20102 (match_operand:V4SF 1 "register_operand" "x")
20103 (parallel [(const_int 0)]))))]
20105 "comiss\t{%1, %0|%0, %1}"
20106 [(set_attr "type" "ssecomi")
20107 (set_attr "mode" "SF")])
20109 (define_insn "sse_ucomi"
20110 [(set (reg:CCFPU 17)
20111 (compare:CCFPU (vec_select:SF
20112 (match_operand:V4SF 0 "register_operand" "x")
20113 (parallel [(const_int 0)]))
20115 (match_operand:V4SF 1 "register_operand" "x")
20116 (parallel [(const_int 0)]))))]
20118 "ucomiss\t{%1, %0|%0, %1}"
20119 [(set_attr "type" "ssecomi")
20120 (set_attr "mode" "SF")])
20125 (define_insn "sse_unpckhps"
20126 [(set (match_operand:V4SF 0 "register_operand" "=x")
20128 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20129 (parallel [(const_int 2)
20133 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20134 (parallel [(const_int 0)
20140 "unpckhps\t{%2, %0|%0, %2}"
20141 [(set_attr "type" "ssecvt")
20142 (set_attr "mode" "V4SF")])
20144 (define_insn "sse_unpcklps"
20145 [(set (match_operand:V4SF 0 "register_operand" "=x")
20147 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20148 (parallel [(const_int 0)
20152 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20153 (parallel [(const_int 2)
20159 "unpcklps\t{%2, %0|%0, %2}"
20160 [(set_attr "type" "ssecvt")
20161 (set_attr "mode" "V4SF")])
20166 (define_insn "smaxv4sf3"
20167 [(set (match_operand:V4SF 0 "register_operand" "=x")
20168 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20169 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20171 "maxps\t{%2, %0|%0, %2}"
20172 [(set_attr "type" "sse")
20173 (set_attr "mode" "V4SF")])
20175 (define_insn "vmsmaxv4sf3"
20176 [(set (match_operand:V4SF 0 "register_operand" "=x")
20178 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20179 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20183 "maxss\t{%2, %0|%0, %2}"
20184 [(set_attr "type" "sse")
20185 (set_attr "mode" "SF")])
20187 (define_insn "sminv4sf3"
20188 [(set (match_operand:V4SF 0 "register_operand" "=x")
20189 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20190 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20192 "minps\t{%2, %0|%0, %2}"
20193 [(set_attr "type" "sse")
20194 (set_attr "mode" "V4SF")])
20196 (define_insn "vmsminv4sf3"
20197 [(set (match_operand:V4SF 0 "register_operand" "=x")
20199 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20200 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20204 "minss\t{%2, %0|%0, %2}"
20205 [(set_attr "type" "sse")
20206 (set_attr "mode" "SF")])
20208 ;; SSE <-> integer/MMX conversions
20210 (define_insn "cvtpi2ps"
20211 [(set (match_operand:V4SF 0 "register_operand" "=x")
20213 (match_operand:V4SF 1 "register_operand" "0")
20214 (vec_duplicate:V4SF
20215 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
20218 "cvtpi2ps\t{%2, %0|%0, %2}"
20219 [(set_attr "type" "ssecvt")
20220 (set_attr "mode" "V4SF")])
20222 (define_insn "cvtps2pi"
20223 [(set (match_operand:V2SI 0 "register_operand" "=y")
20225 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20226 (parallel [(const_int 0) (const_int 1)])))]
20228 "cvtps2pi\t{%1, %0|%0, %1}"
20229 [(set_attr "type" "ssecvt")
20230 (set_attr "mode" "V4SF")])
20232 (define_insn "cvttps2pi"
20233 [(set (match_operand:V2SI 0 "register_operand" "=y")
20235 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20237 (parallel [(const_int 0) (const_int 1)])))]
20239 "cvttps2pi\t{%1, %0|%0, %1}"
20240 [(set_attr "type" "ssecvt")
20241 (set_attr "mode" "SF")])
20243 (define_insn "cvtsi2ss"
20244 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20246 (match_operand:V4SF 1 "register_operand" "0,0")
20247 (vec_duplicate:V4SF
20248 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20251 "cvtsi2ss\t{%2, %0|%0, %2}"
20252 [(set_attr "type" "sseicvt")
20253 (set_attr "athlon_decode" "vector,double")
20254 (set_attr "mode" "SF")])
20256 (define_insn "cvtsi2ssq"
20257 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20259 (match_operand:V4SF 1 "register_operand" "0,0")
20260 (vec_duplicate:V4SF
20261 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20263 "TARGET_SSE && TARGET_64BIT"
20264 "cvtsi2ssq\t{%2, %0|%0, %2}"
20265 [(set_attr "type" "sseicvt")
20266 (set_attr "athlon_decode" "vector,double")
20267 (set_attr "mode" "SF")])
20269 (define_insn "cvtss2si"
20270 [(set (match_operand:SI 0 "register_operand" "=r,r")
20272 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20273 (parallel [(const_int 0)])))]
20275 "cvtss2si\t{%1, %0|%0, %1}"
20276 [(set_attr "type" "sseicvt")
20277 (set_attr "athlon_decode" "double,vector")
20278 (set_attr "mode" "SI")])
20280 (define_insn "cvtss2siq"
20281 [(set (match_operand:DI 0 "register_operand" "=r,r")
20283 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20284 (parallel [(const_int 0)])))]
20286 "cvtss2siq\t{%1, %0|%0, %1}"
20287 [(set_attr "type" "sseicvt")
20288 (set_attr "athlon_decode" "double,vector")
20289 (set_attr "mode" "DI")])
20291 (define_insn "cvttss2si"
20292 [(set (match_operand:SI 0 "register_operand" "=r,r")
20294 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20296 (parallel [(const_int 0)])))]
20298 "cvttss2si\t{%1, %0|%0, %1}"
20299 [(set_attr "type" "sseicvt")
20300 (set_attr "mode" "SF")
20301 (set_attr "athlon_decode" "double,vector")])
20303 (define_insn "cvttss2siq"
20304 [(set (match_operand:DI 0 "register_operand" "=r,r")
20306 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20308 (parallel [(const_int 0)])))]
20309 "TARGET_SSE && TARGET_64BIT"
20310 "cvttss2siq\t{%1, %0|%0, %1}"
20311 [(set_attr "type" "sseicvt")
20312 (set_attr "mode" "SF")
20313 (set_attr "athlon_decode" "double,vector")])
20320 (define_insn "addv8qi3"
20321 [(set (match_operand:V8QI 0 "register_operand" "=y")
20322 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20323 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20325 "paddb\t{%2, %0|%0, %2}"
20326 [(set_attr "type" "mmxadd")
20327 (set_attr "mode" "DI")])
20329 (define_insn "addv4hi3"
20330 [(set (match_operand:V4HI 0 "register_operand" "=y")
20331 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20332 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20334 "paddw\t{%2, %0|%0, %2}"
20335 [(set_attr "type" "mmxadd")
20336 (set_attr "mode" "DI")])
20338 (define_insn "addv2si3"
20339 [(set (match_operand:V2SI 0 "register_operand" "=y")
20340 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20341 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20343 "paddd\t{%2, %0|%0, %2}"
20344 [(set_attr "type" "mmxadd")
20345 (set_attr "mode" "DI")])
20347 (define_insn "mmx_adddi3"
20348 [(set (match_operand:DI 0 "register_operand" "=y")
20350 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20351 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20354 "paddq\t{%2, %0|%0, %2}"
20355 [(set_attr "type" "mmxadd")
20356 (set_attr "mode" "DI")])
20358 (define_insn "ssaddv8qi3"
20359 [(set (match_operand:V8QI 0 "register_operand" "=y")
20360 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20361 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20363 "paddsb\t{%2, %0|%0, %2}"
20364 [(set_attr "type" "mmxadd")
20365 (set_attr "mode" "DI")])
20367 (define_insn "ssaddv4hi3"
20368 [(set (match_operand:V4HI 0 "register_operand" "=y")
20369 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20370 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20372 "paddsw\t{%2, %0|%0, %2}"
20373 [(set_attr "type" "mmxadd")
20374 (set_attr "mode" "DI")])
20376 (define_insn "usaddv8qi3"
20377 [(set (match_operand:V8QI 0 "register_operand" "=y")
20378 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20379 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20381 "paddusb\t{%2, %0|%0, %2}"
20382 [(set_attr "type" "mmxadd")
20383 (set_attr "mode" "DI")])
20385 (define_insn "usaddv4hi3"
20386 [(set (match_operand:V4HI 0 "register_operand" "=y")
20387 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20388 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20390 "paddusw\t{%2, %0|%0, %2}"
20391 [(set_attr "type" "mmxadd")
20392 (set_attr "mode" "DI")])
20394 (define_insn "subv8qi3"
20395 [(set (match_operand:V8QI 0 "register_operand" "=y")
20396 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20397 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20399 "psubb\t{%2, %0|%0, %2}"
20400 [(set_attr "type" "mmxadd")
20401 (set_attr "mode" "DI")])
20403 (define_insn "subv4hi3"
20404 [(set (match_operand:V4HI 0 "register_operand" "=y")
20405 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20406 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20408 "psubw\t{%2, %0|%0, %2}"
20409 [(set_attr "type" "mmxadd")
20410 (set_attr "mode" "DI")])
20412 (define_insn "subv2si3"
20413 [(set (match_operand:V2SI 0 "register_operand" "=y")
20414 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20415 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20417 "psubd\t{%2, %0|%0, %2}"
20418 [(set_attr "type" "mmxadd")
20419 (set_attr "mode" "DI")])
20421 (define_insn "mmx_subdi3"
20422 [(set (match_operand:DI 0 "register_operand" "=y")
20424 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20425 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20428 "psubq\t{%2, %0|%0, %2}"
20429 [(set_attr "type" "mmxadd")
20430 (set_attr "mode" "DI")])
20432 (define_insn "sssubv8qi3"
20433 [(set (match_operand:V8QI 0 "register_operand" "=y")
20434 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20435 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20437 "psubsb\t{%2, %0|%0, %2}"
20438 [(set_attr "type" "mmxadd")
20439 (set_attr "mode" "DI")])
20441 (define_insn "sssubv4hi3"
20442 [(set (match_operand:V4HI 0 "register_operand" "=y")
20443 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20444 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20446 "psubsw\t{%2, %0|%0, %2}"
20447 [(set_attr "type" "mmxadd")
20448 (set_attr "mode" "DI")])
20450 (define_insn "ussubv8qi3"
20451 [(set (match_operand:V8QI 0 "register_operand" "=y")
20452 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20453 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20455 "psubusb\t{%2, %0|%0, %2}"
20456 [(set_attr "type" "mmxadd")
20457 (set_attr "mode" "DI")])
20459 (define_insn "ussubv4hi3"
20460 [(set (match_operand:V4HI 0 "register_operand" "=y")
20461 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20462 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20464 "psubusw\t{%2, %0|%0, %2}"
20465 [(set_attr "type" "mmxadd")
20466 (set_attr "mode" "DI")])
20468 (define_insn "mulv4hi3"
20469 [(set (match_operand:V4HI 0 "register_operand" "=y")
20470 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20471 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20473 "pmullw\t{%2, %0|%0, %2}"
20474 [(set_attr "type" "mmxmul")
20475 (set_attr "mode" "DI")])
20477 (define_insn "smulv4hi3_highpart"
20478 [(set (match_operand:V4HI 0 "register_operand" "=y")
20481 (mult:V4SI (sign_extend:V4SI
20482 (match_operand:V4HI 1 "register_operand" "0"))
20484 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20487 "pmulhw\t{%2, %0|%0, %2}"
20488 [(set_attr "type" "mmxmul")
20489 (set_attr "mode" "DI")])
20491 (define_insn "umulv4hi3_highpart"
20492 [(set (match_operand:V4HI 0 "register_operand" "=y")
20495 (mult:V4SI (zero_extend:V4SI
20496 (match_operand:V4HI 1 "register_operand" "0"))
20498 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20500 "TARGET_SSE || TARGET_3DNOW_A"
20501 "pmulhuw\t{%2, %0|%0, %2}"
20502 [(set_attr "type" "mmxmul")
20503 (set_attr "mode" "DI")])
20505 (define_insn "mmx_pmaddwd"
20506 [(set (match_operand:V2SI 0 "register_operand" "=y")
20510 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20511 (parallel [(const_int 0) (const_int 2)])))
20513 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20514 (parallel [(const_int 0) (const_int 2)]))))
20516 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20517 (parallel [(const_int 1)
20519 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20520 (parallel [(const_int 1)
20521 (const_int 3)]))))))]
20523 "pmaddwd\t{%2, %0|%0, %2}"
20524 [(set_attr "type" "mmxmul")
20525 (set_attr "mode" "DI")])
20528 ;; MMX logical operations
20529 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20530 ;; normal code that also wants to use the FPU from getting broken.
20531 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20532 (define_insn "mmx_iordi3"
20533 [(set (match_operand:DI 0 "register_operand" "=y")
20535 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20536 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20539 "por\t{%2, %0|%0, %2}"
20540 [(set_attr "type" "mmxadd")
20541 (set_attr "mode" "DI")])
20543 (define_insn "mmx_xordi3"
20544 [(set (match_operand:DI 0 "register_operand" "=y")
20546 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20547 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20550 "pxor\t{%2, %0|%0, %2}"
20551 [(set_attr "type" "mmxadd")
20552 (set_attr "mode" "DI")
20553 (set_attr "memory" "none")])
20555 ;; Same as pxor, but don't show input operands so that we don't think
20557 (define_insn "mmx_clrdi"
20558 [(set (match_operand:DI 0 "register_operand" "=y")
20559 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20561 "pxor\t{%0, %0|%0, %0}"
20562 [(set_attr "type" "mmxadd")
20563 (set_attr "mode" "DI")
20564 (set_attr "memory" "none")])
20566 (define_insn "mmx_anddi3"
20567 [(set (match_operand:DI 0 "register_operand" "=y")
20569 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20570 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20573 "pand\t{%2, %0|%0, %2}"
20574 [(set_attr "type" "mmxadd")
20575 (set_attr "mode" "DI")])
20577 (define_insn "mmx_nanddi3"
20578 [(set (match_operand:DI 0 "register_operand" "=y")
20580 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20581 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20584 "pandn\t{%2, %0|%0, %2}"
20585 [(set_attr "type" "mmxadd")
20586 (set_attr "mode" "DI")])
20589 ;; MMX unsigned averages/sum of absolute differences
20591 (define_insn "mmx_uavgv8qi3"
20592 [(set (match_operand:V8QI 0 "register_operand" "=y")
20594 (plus:V8QI (plus:V8QI
20595 (match_operand:V8QI 1 "register_operand" "0")
20596 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
20597 (const_vector:V8QI [(const_int 1)
20606 "TARGET_SSE || TARGET_3DNOW_A"
20607 "pavgb\t{%2, %0|%0, %2}"
20608 [(set_attr "type" "mmxshft")
20609 (set_attr "mode" "DI")])
20611 (define_insn "mmx_uavgv4hi3"
20612 [(set (match_operand:V4HI 0 "register_operand" "=y")
20614 (plus:V4HI (plus:V4HI
20615 (match_operand:V4HI 1 "register_operand" "0")
20616 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
20617 (const_vector:V4HI [(const_int 1)
20622 "TARGET_SSE || TARGET_3DNOW_A"
20623 "pavgw\t{%2, %0|%0, %2}"
20624 [(set_attr "type" "mmxshft")
20625 (set_attr "mode" "DI")])
20627 (define_insn "mmx_psadbw"
20628 [(set (match_operand:DI 0 "register_operand" "=y")
20629 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
20630 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
20632 "TARGET_SSE || TARGET_3DNOW_A"
20633 "psadbw\t{%2, %0|%0, %2}"
20634 [(set_attr "type" "mmxshft")
20635 (set_attr "mode" "DI")])
20638 ;; MMX insert/extract/shuffle
20640 (define_insn "mmx_pinsrw"
20641 [(set (match_operand:V4HI 0 "register_operand" "=y")
20642 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
20643 (vec_duplicate:V4HI
20644 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
20645 (match_operand:SI 3 "immediate_operand" "i")))]
20646 "TARGET_SSE || TARGET_3DNOW_A"
20647 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
20648 [(set_attr "type" "mmxcvt")
20649 (set_attr "mode" "DI")])
20651 (define_insn "mmx_pextrw"
20652 [(set (match_operand:SI 0 "register_operand" "=r")
20653 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
20655 [(match_operand:SI 2 "immediate_operand" "i")]))))]
20656 "TARGET_SSE || TARGET_3DNOW_A"
20657 "pextrw\t{%2, %1, %0|%0, %1, %2}"
20658 [(set_attr "type" "mmxcvt")
20659 (set_attr "mode" "DI")])
20661 (define_insn "mmx_pshufw"
20662 [(set (match_operand:V4HI 0 "register_operand" "=y")
20663 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
20664 (match_operand:SI 2 "immediate_operand" "i")]
20666 "TARGET_SSE || TARGET_3DNOW_A"
20667 "pshufw\t{%2, %1, %0|%0, %1, %2}"
20668 [(set_attr "type" "mmxcvt")
20669 (set_attr "mode" "DI")])
20672 ;; MMX mask-generating comparisons
20674 (define_insn "eqv8qi3"
20675 [(set (match_operand:V8QI 0 "register_operand" "=y")
20676 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
20677 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20679 "pcmpeqb\t{%2, %0|%0, %2}"
20680 [(set_attr "type" "mmxcmp")
20681 (set_attr "mode" "DI")])
20683 (define_insn "eqv4hi3"
20684 [(set (match_operand:V4HI 0 "register_operand" "=y")
20685 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
20686 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20688 "pcmpeqw\t{%2, %0|%0, %2}"
20689 [(set_attr "type" "mmxcmp")
20690 (set_attr "mode" "DI")])
20692 (define_insn "eqv2si3"
20693 [(set (match_operand:V2SI 0 "register_operand" "=y")
20694 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
20695 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20697 "pcmpeqd\t{%2, %0|%0, %2}"
20698 [(set_attr "type" "mmxcmp")
20699 (set_attr "mode" "DI")])
20701 (define_insn "gtv8qi3"
20702 [(set (match_operand:V8QI 0 "register_operand" "=y")
20703 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
20704 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20706 "pcmpgtb\t{%2, %0|%0, %2}"
20707 [(set_attr "type" "mmxcmp")
20708 (set_attr "mode" "DI")])
20710 (define_insn "gtv4hi3"
20711 [(set (match_operand:V4HI 0 "register_operand" "=y")
20712 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20713 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20715 "pcmpgtw\t{%2, %0|%0, %2}"
20716 [(set_attr "type" "mmxcmp")
20717 (set_attr "mode" "DI")])
20719 (define_insn "gtv2si3"
20720 [(set (match_operand:V2SI 0 "register_operand" "=y")
20721 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20722 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20724 "pcmpgtd\t{%2, %0|%0, %2}"
20725 [(set_attr "type" "mmxcmp")
20726 (set_attr "mode" "DI")])
20729 ;; MMX max/min insns
20731 (define_insn "umaxv8qi3"
20732 [(set (match_operand:V8QI 0 "register_operand" "=y")
20733 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
20734 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20735 "TARGET_SSE || TARGET_3DNOW_A"
20736 "pmaxub\t{%2, %0|%0, %2}"
20737 [(set_attr "type" "mmxadd")
20738 (set_attr "mode" "DI")])
20740 (define_insn "smaxv4hi3"
20741 [(set (match_operand:V4HI 0 "register_operand" "=y")
20742 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
20743 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20744 "TARGET_SSE || TARGET_3DNOW_A"
20745 "pmaxsw\t{%2, %0|%0, %2}"
20746 [(set_attr "type" "mmxadd")
20747 (set_attr "mode" "DI")])
20749 (define_insn "uminv8qi3"
20750 [(set (match_operand:V8QI 0 "register_operand" "=y")
20751 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
20752 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20753 "TARGET_SSE || TARGET_3DNOW_A"
20754 "pminub\t{%2, %0|%0, %2}"
20755 [(set_attr "type" "mmxadd")
20756 (set_attr "mode" "DI")])
20758 (define_insn "sminv4hi3"
20759 [(set (match_operand:V4HI 0 "register_operand" "=y")
20760 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
20761 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20762 "TARGET_SSE || TARGET_3DNOW_A"
20763 "pminsw\t{%2, %0|%0, %2}"
20764 [(set_attr "type" "mmxadd")
20765 (set_attr "mode" "DI")])
20770 (define_insn "ashrv4hi3"
20771 [(set (match_operand:V4HI 0 "register_operand" "=y")
20772 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20773 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20775 "psraw\t{%2, %0|%0, %2}"
20776 [(set_attr "type" "mmxshft")
20777 (set_attr "mode" "DI")])
20779 (define_insn "ashrv2si3"
20780 [(set (match_operand:V2SI 0 "register_operand" "=y")
20781 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20782 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20784 "psrad\t{%2, %0|%0, %2}"
20785 [(set_attr "type" "mmxshft")
20786 (set_attr "mode" "DI")])
20788 (define_insn "lshrv4hi3"
20789 [(set (match_operand:V4HI 0 "register_operand" "=y")
20790 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
20791 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20793 "psrlw\t{%2, %0|%0, %2}"
20794 [(set_attr "type" "mmxshft")
20795 (set_attr "mode" "DI")])
20797 (define_insn "lshrv2si3"
20798 [(set (match_operand:V2SI 0 "register_operand" "=y")
20799 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
20800 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20802 "psrld\t{%2, %0|%0, %2}"
20803 [(set_attr "type" "mmxshft")
20804 (set_attr "mode" "DI")])
20806 ;; See logical MMX insns.
20807 (define_insn "mmx_lshrdi3"
20808 [(set (match_operand:DI 0 "register_operand" "=y")
20810 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
20811 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20814 "psrlq\t{%2, %0|%0, %2}"
20815 [(set_attr "type" "mmxshft")
20816 (set_attr "mode" "DI")])
20818 (define_insn "ashlv4hi3"
20819 [(set (match_operand:V4HI 0 "register_operand" "=y")
20820 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
20821 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20823 "psllw\t{%2, %0|%0, %2}"
20824 [(set_attr "type" "mmxshft")
20825 (set_attr "mode" "DI")])
20827 (define_insn "ashlv2si3"
20828 [(set (match_operand:V2SI 0 "register_operand" "=y")
20829 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
20830 (match_operand:DI 2 "nonmemory_operand" "yi")))]
20832 "pslld\t{%2, %0|%0, %2}"
20833 [(set_attr "type" "mmxshft")
20834 (set_attr "mode" "DI")])
20836 ;; See logical MMX insns.
20837 (define_insn "mmx_ashldi3"
20838 [(set (match_operand:DI 0 "register_operand" "=y")
20840 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
20841 (match_operand:DI 2 "nonmemory_operand" "yi"))]
20844 "psllq\t{%2, %0|%0, %2}"
20845 [(set_attr "type" "mmxshft")
20846 (set_attr "mode" "DI")])
20849 ;; MMX pack/unpack insns.
20851 (define_insn "mmx_packsswb"
20852 [(set (match_operand:V8QI 0 "register_operand" "=y")
20854 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20855 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20857 "packsswb\t{%2, %0|%0, %2}"
20858 [(set_attr "type" "mmxshft")
20859 (set_attr "mode" "DI")])
20861 (define_insn "mmx_packssdw"
20862 [(set (match_operand:V4HI 0 "register_operand" "=y")
20864 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
20865 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
20867 "packssdw\t{%2, %0|%0, %2}"
20868 [(set_attr "type" "mmxshft")
20869 (set_attr "mode" "DI")])
20871 (define_insn "mmx_packuswb"
20872 [(set (match_operand:V8QI 0 "register_operand" "=y")
20874 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
20875 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
20877 "packuswb\t{%2, %0|%0, %2}"
20878 [(set_attr "type" "mmxshft")
20879 (set_attr "mode" "DI")])
20881 (define_insn "mmx_punpckhbw"
20882 [(set (match_operand:V8QI 0 "register_operand" "=y")
20884 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20885 (parallel [(const_int 4)
20893 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20894 (parallel [(const_int 0)
20904 "punpckhbw\t{%2, %0|%0, %2}"
20905 [(set_attr "type" "mmxcvt")
20906 (set_attr "mode" "DI")])
20908 (define_insn "mmx_punpckhwd"
20909 [(set (match_operand:V4HI 0 "register_operand" "=y")
20911 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20912 (parallel [(const_int 0)
20916 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20917 (parallel [(const_int 2)
20923 "punpckhwd\t{%2, %0|%0, %2}"
20924 [(set_attr "type" "mmxcvt")
20925 (set_attr "mode" "DI")])
20927 (define_insn "mmx_punpckhdq"
20928 [(set (match_operand:V2SI 0 "register_operand" "=y")
20930 (match_operand:V2SI 1 "register_operand" "0")
20931 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
20932 (parallel [(const_int 1)
20936 "punpckhdq\t{%2, %0|%0, %2}"
20937 [(set_attr "type" "mmxcvt")
20938 (set_attr "mode" "DI")])
20940 (define_insn "mmx_punpcklbw"
20941 [(set (match_operand:V8QI 0 "register_operand" "=y")
20943 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
20944 (parallel [(const_int 0)
20952 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
20953 (parallel [(const_int 4)
20963 "punpcklbw\t{%2, %0|%0, %2}"
20964 [(set_attr "type" "mmxcvt")
20965 (set_attr "mode" "DI")])
20967 (define_insn "mmx_punpcklwd"
20968 [(set (match_operand:V4HI 0 "register_operand" "=y")
20970 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
20971 (parallel [(const_int 2)
20975 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
20976 (parallel [(const_int 0)
20982 "punpcklwd\t{%2, %0|%0, %2}"
20983 [(set_attr "type" "mmxcvt")
20984 (set_attr "mode" "DI")])
20986 (define_insn "mmx_punpckldq"
20987 [(set (match_operand:V2SI 0 "register_operand" "=y")
20989 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
20990 (parallel [(const_int 1)
20992 (match_operand:V2SI 2 "register_operand" "y")
20995 "punpckldq\t{%2, %0|%0, %2}"
20996 [(set_attr "type" "mmxcvt")
20997 (set_attr "mode" "DI")])
21000 ;; Miscellaneous stuff
21002 (define_insn "emms"
21003 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21004 (clobber (reg:XF 8))
21005 (clobber (reg:XF 9))
21006 (clobber (reg:XF 10))
21007 (clobber (reg:XF 11))
21008 (clobber (reg:XF 12))
21009 (clobber (reg:XF 13))
21010 (clobber (reg:XF 14))
21011 (clobber (reg:XF 15))
21012 (clobber (reg:DI 29))
21013 (clobber (reg:DI 30))
21014 (clobber (reg:DI 31))
21015 (clobber (reg:DI 32))
21016 (clobber (reg:DI 33))
21017 (clobber (reg:DI 34))
21018 (clobber (reg:DI 35))
21019 (clobber (reg:DI 36))]
21022 [(set_attr "type" "mmx")
21023 (set_attr "memory" "unknown")])
21025 (define_insn "ldmxcsr"
21026 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
21030 [(set_attr "type" "sse")
21031 (set_attr "memory" "load")])
21033 (define_insn "stmxcsr"
21034 [(set (match_operand:SI 0 "memory_operand" "=m")
21035 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
21038 [(set_attr "type" "sse")
21039 (set_attr "memory" "store")])
21041 (define_expand "sfence"
21042 [(set (match_dup 0)
21043 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21044 "TARGET_SSE || TARGET_3DNOW_A"
21046 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21047 MEM_VOLATILE_P (operands[0]) = 1;
21050 (define_insn "*sfence_insn"
21051 [(set (match_operand:BLK 0 "" "")
21052 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21053 "TARGET_SSE || TARGET_3DNOW_A"
21055 [(set_attr "type" "sse")
21056 (set_attr "memory" "unknown")])
21058 (define_expand "sse_prologue_save"
21059 [(parallel [(set (match_operand:BLK 0 "" "")
21060 (unspec:BLK [(reg:DI 21)
21067 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21068 (use (match_operand:DI 1 "register_operand" ""))
21069 (use (match_operand:DI 2 "immediate_operand" ""))
21070 (use (label_ref:DI (match_operand 3 "" "")))])]
21074 (define_insn "*sse_prologue_save_insn"
21075 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21076 (match_operand:DI 4 "const_int_operand" "n")))
21077 (unspec:BLK [(reg:DI 21)
21084 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21085 (use (match_operand:DI 1 "register_operand" "r"))
21086 (use (match_operand:DI 2 "const_int_operand" "i"))
21087 (use (label_ref:DI (match_operand 3 "" "X")))]
21089 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21090 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21094 operands[0] = gen_rtx_MEM (Pmode,
21095 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21096 output_asm_insn (\"jmp\\t%A1\", operands);
21097 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21099 operands[4] = adjust_address (operands[0], DImode, i*16);
21100 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21101 PUT_MODE (operands[4], TImode);
21102 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21103 output_asm_insn (\"rex\", operands);
21104 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21106 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21107 CODE_LABEL_NUMBER (operands[3]));
21111 [(set_attr "type" "other")
21112 (set_attr "length_immediate" "0")
21113 (set_attr "length_address" "0")
21114 (set_attr "length" "135")
21115 (set_attr "memory" "store")
21116 (set_attr "modrm" "0")
21117 (set_attr "mode" "DI")])
21119 ;; 3Dnow! instructions
21121 (define_insn "addv2sf3"
21122 [(set (match_operand:V2SF 0 "register_operand" "=y")
21123 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21124 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21126 "pfadd\\t{%2, %0|%0, %2}"
21127 [(set_attr "type" "mmxadd")
21128 (set_attr "mode" "V2SF")])
21130 (define_insn "subv2sf3"
21131 [(set (match_operand:V2SF 0 "register_operand" "=y")
21132 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21133 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21135 "pfsub\\t{%2, %0|%0, %2}"
21136 [(set_attr "type" "mmxadd")
21137 (set_attr "mode" "V2SF")])
21139 (define_insn "subrv2sf3"
21140 [(set (match_operand:V2SF 0 "register_operand" "=y")
21141 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
21142 (match_operand:V2SF 1 "register_operand" "0")))]
21144 "pfsubr\\t{%2, %0|%0, %2}"
21145 [(set_attr "type" "mmxadd")
21146 (set_attr "mode" "V2SF")])
21148 (define_insn "gtv2sf3"
21149 [(set (match_operand:V2SI 0 "register_operand" "=y")
21150 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
21151 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21153 "pfcmpgt\\t{%2, %0|%0, %2}"
21154 [(set_attr "type" "mmxcmp")
21155 (set_attr "mode" "V2SF")])
21157 (define_insn "gev2sf3"
21158 [(set (match_operand:V2SI 0 "register_operand" "=y")
21159 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
21160 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21162 "pfcmpge\\t{%2, %0|%0, %2}"
21163 [(set_attr "type" "mmxcmp")
21164 (set_attr "mode" "V2SF")])
21166 (define_insn "eqv2sf3"
21167 [(set (match_operand:V2SI 0 "register_operand" "=y")
21168 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
21169 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21171 "pfcmpeq\\t{%2, %0|%0, %2}"
21172 [(set_attr "type" "mmxcmp")
21173 (set_attr "mode" "V2SF")])
21175 (define_insn "pfmaxv2sf3"
21176 [(set (match_operand:V2SF 0 "register_operand" "=y")
21177 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
21178 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21180 "pfmax\\t{%2, %0|%0, %2}"
21181 [(set_attr "type" "mmxadd")
21182 (set_attr "mode" "V2SF")])
21184 (define_insn "pfminv2sf3"
21185 [(set (match_operand:V2SF 0 "register_operand" "=y")
21186 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
21187 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21189 "pfmin\\t{%2, %0|%0, %2}"
21190 [(set_attr "type" "mmxadd")
21191 (set_attr "mode" "V2SF")])
21193 (define_insn "mulv2sf3"
21194 [(set (match_operand:V2SF 0 "register_operand" "=y")
21195 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
21196 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21198 "pfmul\\t{%2, %0|%0, %2}"
21199 [(set_attr "type" "mmxmul")
21200 (set_attr "mode" "V2SF")])
21202 (define_insn "femms"
21203 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
21204 (clobber (reg:XF 8))
21205 (clobber (reg:XF 9))
21206 (clobber (reg:XF 10))
21207 (clobber (reg:XF 11))
21208 (clobber (reg:XF 12))
21209 (clobber (reg:XF 13))
21210 (clobber (reg:XF 14))
21211 (clobber (reg:XF 15))
21212 (clobber (reg:DI 29))
21213 (clobber (reg:DI 30))
21214 (clobber (reg:DI 31))
21215 (clobber (reg:DI 32))
21216 (clobber (reg:DI 33))
21217 (clobber (reg:DI 34))
21218 (clobber (reg:DI 35))
21219 (clobber (reg:DI 36))]
21222 [(set_attr "type" "mmx")
21223 (set_attr "memory" "none")])
21225 (define_insn "pf2id"
21226 [(set (match_operand:V2SI 0 "register_operand" "=y")
21227 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
21229 "pf2id\\t{%1, %0|%0, %1}"
21230 [(set_attr "type" "mmxcvt")
21231 (set_attr "mode" "V2SF")])
21233 (define_insn "pf2iw"
21234 [(set (match_operand:V2SI 0 "register_operand" "=y")
21237 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
21239 "pf2iw\\t{%1, %0|%0, %1}"
21240 [(set_attr "type" "mmxcvt")
21241 (set_attr "mode" "V2SF")])
21243 (define_insn "pfacc"
21244 [(set (match_operand:V2SF 0 "register_operand" "=y")
21247 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21248 (parallel [(const_int 0)]))
21249 (vec_select:SF (match_dup 1)
21250 (parallel [(const_int 1)])))
21252 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21253 (parallel [(const_int 0)]))
21254 (vec_select:SF (match_dup 2)
21255 (parallel [(const_int 1)])))))]
21257 "pfacc\\t{%2, %0|%0, %2}"
21258 [(set_attr "type" "mmxadd")
21259 (set_attr "mode" "V2SF")])
21261 (define_insn "pfnacc"
21262 [(set (match_operand:V2SF 0 "register_operand" "=y")
21265 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21266 (parallel [(const_int 0)]))
21267 (vec_select:SF (match_dup 1)
21268 (parallel [(const_int 1)])))
21270 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21271 (parallel [(const_int 0)]))
21272 (vec_select:SF (match_dup 2)
21273 (parallel [(const_int 1)])))))]
21275 "pfnacc\\t{%2, %0|%0, %2}"
21276 [(set_attr "type" "mmxadd")
21277 (set_attr "mode" "V2SF")])
21279 (define_insn "pfpnacc"
21280 [(set (match_operand:V2SF 0 "register_operand" "=y")
21283 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21284 (parallel [(const_int 0)]))
21285 (vec_select:SF (match_dup 1)
21286 (parallel [(const_int 1)])))
21288 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21289 (parallel [(const_int 0)]))
21290 (vec_select:SF (match_dup 2)
21291 (parallel [(const_int 1)])))))]
21293 "pfpnacc\\t{%2, %0|%0, %2}"
21294 [(set_attr "type" "mmxadd")
21295 (set_attr "mode" "V2SF")])
21297 (define_insn "pi2fw"
21298 [(set (match_operand:V2SF 0 "register_operand" "=y")
21303 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21304 (parallel [(const_int 0)]))))
21307 (vec_select:SI (match_dup 1)
21308 (parallel [(const_int 1)])))))))]
21310 "pi2fw\\t{%1, %0|%0, %1}"
21311 [(set_attr "type" "mmxcvt")
21312 (set_attr "mode" "V2SF")])
21314 (define_insn "floatv2si2"
21315 [(set (match_operand:V2SF 0 "register_operand" "=y")
21316 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21318 "pi2fd\\t{%1, %0|%0, %1}"
21319 [(set_attr "type" "mmxcvt")
21320 (set_attr "mode" "V2SF")])
21322 ;; This insn is identical to pavgb in operation, but the opcode is
21323 ;; different. To avoid accidentally matching pavgb, use an unspec.
21325 (define_insn "pavgusb"
21326 [(set (match_operand:V8QI 0 "register_operand" "=y")
21328 [(match_operand:V8QI 1 "register_operand" "0")
21329 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21332 "pavgusb\\t{%2, %0|%0, %2}"
21333 [(set_attr "type" "mmxshft")
21334 (set_attr "mode" "TI")])
21336 ;; 3DNow reciprocal and sqrt
21338 (define_insn "pfrcpv2sf2"
21339 [(set (match_operand:V2SF 0 "register_operand" "=y")
21340 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21343 "pfrcp\\t{%1, %0|%0, %1}"
21344 [(set_attr "type" "mmx")
21345 (set_attr "mode" "TI")])
21347 (define_insn "pfrcpit1v2sf3"
21348 [(set (match_operand:V2SF 0 "register_operand" "=y")
21349 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21350 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21353 "pfrcpit1\\t{%2, %0|%0, %2}"
21354 [(set_attr "type" "mmx")
21355 (set_attr "mode" "TI")])
21357 (define_insn "pfrcpit2v2sf3"
21358 [(set (match_operand:V2SF 0 "register_operand" "=y")
21359 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21360 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21363 "pfrcpit2\\t{%2, %0|%0, %2}"
21364 [(set_attr "type" "mmx")
21365 (set_attr "mode" "TI")])
21367 (define_insn "pfrsqrtv2sf2"
21368 [(set (match_operand:V2SF 0 "register_operand" "=y")
21369 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21372 "pfrsqrt\\t{%1, %0|%0, %1}"
21373 [(set_attr "type" "mmx")
21374 (set_attr "mode" "TI")])
21376 (define_insn "pfrsqit1v2sf3"
21377 [(set (match_operand:V2SF 0 "register_operand" "=y")
21378 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21379 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21382 "pfrsqit1\\t{%2, %0|%0, %2}"
21383 [(set_attr "type" "mmx")
21384 (set_attr "mode" "TI")])
21386 (define_insn "pmulhrwv4hi3"
21387 [(set (match_operand:V4HI 0 "register_operand" "=y")
21393 (match_operand:V4HI 1 "register_operand" "0"))
21395 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21396 (const_vector:V4SI [(const_int 32768)
21399 (const_int 32768)]))
21402 "pmulhrw\\t{%2, %0|%0, %2}"
21403 [(set_attr "type" "mmxmul")
21404 (set_attr "mode" "TI")])
21406 (define_insn "pswapdv2si2"
21407 [(set (match_operand:V2SI 0 "register_operand" "=y")
21408 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21409 (parallel [(const_int 1) (const_int 0)])))]
21411 "pswapd\\t{%1, %0|%0, %1}"
21412 [(set_attr "type" "mmxcvt")
21413 (set_attr "mode" "TI")])
21415 (define_insn "pswapdv2sf2"
21416 [(set (match_operand:V2SF 0 "register_operand" "=y")
21417 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21418 (parallel [(const_int 1) (const_int 0)])))]
21420 "pswapd\\t{%1, %0|%0, %1}"
21421 [(set_attr "type" "mmxcvt")
21422 (set_attr "mode" "TI")])
21424 (define_expand "prefetch"
21425 [(prefetch (match_operand 0 "address_operand" "")
21426 (match_operand:SI 1 "const_int_operand" "")
21427 (match_operand:SI 2 "const_int_operand" ""))]
21428 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21430 int rw = INTVAL (operands[1]);
21431 int locality = INTVAL (operands[2]);
21433 if (rw != 0 && rw != 1)
21435 if (locality < 0 || locality > 3)
21437 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21440 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21441 suported by SSE counterpart or the SSE prefetch is not available
21442 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21444 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21445 operands[2] = GEN_INT (3);
21447 operands[1] = const0_rtx;
21450 (define_insn "*prefetch_sse"
21451 [(prefetch (match_operand:SI 0 "address_operand" "p")
21453 (match_operand:SI 1 "const_int_operand" ""))]
21454 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21456 static const char * const patterns[4] = {
21457 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21460 int locality = INTVAL (operands[1]);
21461 if (locality < 0 || locality > 3)
21464 return patterns[locality];
21466 [(set_attr "type" "sse")
21467 (set_attr "memory" "none")])
21469 (define_insn "*prefetch_sse_rex"
21470 [(prefetch (match_operand:DI 0 "address_operand" "p")
21472 (match_operand:SI 1 "const_int_operand" ""))]
21473 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21475 static const char * const patterns[4] = {
21476 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21479 int locality = INTVAL (operands[1]);
21480 if (locality < 0 || locality > 3)
21483 return patterns[locality];
21485 [(set_attr "type" "sse")
21486 (set_attr "memory" "none")])
21488 (define_insn "*prefetch_3dnow"
21489 [(prefetch (match_operand:SI 0 "address_operand" "p")
21490 (match_operand:SI 1 "const_int_operand" "n")
21492 "TARGET_3DNOW && !TARGET_64BIT"
21494 if (INTVAL (operands[1]) == 0)
21495 return "prefetch\t%a0";
21497 return "prefetchw\t%a0";
21499 [(set_attr "type" "mmx")
21500 (set_attr "memory" "none")])
21502 (define_insn "*prefetch_3dnow_rex"
21503 [(prefetch (match_operand:DI 0 "address_operand" "p")
21504 (match_operand:SI 1 "const_int_operand" "n")
21506 "TARGET_3DNOW && TARGET_64BIT"
21508 if (INTVAL (operands[1]) == 0)
21509 return "prefetch\t%a0";
21511 return "prefetchw\t%a0";
21513 [(set_attr "type" "mmx")
21514 (set_attr "memory" "none")])
21518 (define_insn "addv2df3"
21519 [(set (match_operand:V2DF 0 "register_operand" "=x")
21520 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21521 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21523 "addpd\t{%2, %0|%0, %2}"
21524 [(set_attr "type" "sseadd")
21525 (set_attr "mode" "V2DF")])
21527 (define_insn "vmaddv2df3"
21528 [(set (match_operand:V2DF 0 "register_operand" "=x")
21529 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21530 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21534 "addsd\t{%2, %0|%0, %2}"
21535 [(set_attr "type" "sseadd")
21536 (set_attr "mode" "DF")])
21538 (define_insn "subv2df3"
21539 [(set (match_operand:V2DF 0 "register_operand" "=x")
21540 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21541 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21543 "subpd\t{%2, %0|%0, %2}"
21544 [(set_attr "type" "sseadd")
21545 (set_attr "mode" "V2DF")])
21547 (define_insn "vmsubv2df3"
21548 [(set (match_operand:V2DF 0 "register_operand" "=x")
21549 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21550 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21554 "subsd\t{%2, %0|%0, %2}"
21555 [(set_attr "type" "sseadd")
21556 (set_attr "mode" "DF")])
21558 (define_insn "mulv2df3"
21559 [(set (match_operand:V2DF 0 "register_operand" "=x")
21560 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21561 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21563 "mulpd\t{%2, %0|%0, %2}"
21564 [(set_attr "type" "ssemul")
21565 (set_attr "mode" "V2DF")])
21567 (define_insn "vmmulv2df3"
21568 [(set (match_operand:V2DF 0 "register_operand" "=x")
21569 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21570 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21574 "mulsd\t{%2, %0|%0, %2}"
21575 [(set_attr "type" "ssemul")
21576 (set_attr "mode" "DF")])
21578 (define_insn "divv2df3"
21579 [(set (match_operand:V2DF 0 "register_operand" "=x")
21580 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21581 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21583 "divpd\t{%2, %0|%0, %2}"
21584 [(set_attr "type" "ssediv")
21585 (set_attr "mode" "V2DF")])
21587 (define_insn "vmdivv2df3"
21588 [(set (match_operand:V2DF 0 "register_operand" "=x")
21589 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21590 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21594 "divsd\t{%2, %0|%0, %2}"
21595 [(set_attr "type" "ssediv")
21596 (set_attr "mode" "DF")])
21600 (define_insn "smaxv2df3"
21601 [(set (match_operand:V2DF 0 "register_operand" "=x")
21602 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21603 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21605 "maxpd\t{%2, %0|%0, %2}"
21606 [(set_attr "type" "sseadd")
21607 (set_attr "mode" "V2DF")])
21609 (define_insn "vmsmaxv2df3"
21610 [(set (match_operand:V2DF 0 "register_operand" "=x")
21611 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
21612 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21616 "maxsd\t{%2, %0|%0, %2}"
21617 [(set_attr "type" "sseadd")
21618 (set_attr "mode" "DF")])
21620 (define_insn "sminv2df3"
21621 [(set (match_operand:V2DF 0 "register_operand" "=x")
21622 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21623 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21625 "minpd\t{%2, %0|%0, %2}"
21626 [(set_attr "type" "sseadd")
21627 (set_attr "mode" "V2DF")])
21629 (define_insn "vmsminv2df3"
21630 [(set (match_operand:V2DF 0 "register_operand" "=x")
21631 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
21632 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21636 "minsd\t{%2, %0|%0, %2}"
21637 [(set_attr "type" "sseadd")
21638 (set_attr "mode" "DF")])
21639 ;; SSE2 square root. There doesn't appear to be an extension for the
21640 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
21642 (define_insn "sqrtv2df2"
21643 [(set (match_operand:V2DF 0 "register_operand" "=x")
21644 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
21646 "sqrtpd\t{%1, %0|%0, %1}"
21647 [(set_attr "type" "sse")
21648 (set_attr "mode" "V2DF")])
21650 (define_insn "vmsqrtv2df2"
21651 [(set (match_operand:V2DF 0 "register_operand" "=x")
21652 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
21653 (match_operand:V2DF 2 "register_operand" "0")
21656 "sqrtsd\t{%1, %0|%0, %1}"
21657 [(set_attr "type" "sse")
21658 (set_attr "mode" "SF")])
21660 ;; SSE mask-generating compares
21662 (define_insn "maskcmpv2df3"
21663 [(set (match_operand:V2DI 0 "register_operand" "=x")
21664 (match_operator:V2DI 3 "sse_comparison_operator"
21665 [(match_operand:V2DF 1 "register_operand" "0")
21666 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
21668 "cmp%D3pd\t{%2, %0|%0, %2}"
21669 [(set_attr "type" "ssecmp")
21670 (set_attr "mode" "V2DF")])
21672 (define_insn "maskncmpv2df3"
21673 [(set (match_operand:V2DI 0 "register_operand" "=x")
21675 (match_operator:V2DI 3 "sse_comparison_operator"
21676 [(match_operand:V2DF 1 "register_operand" "0")
21677 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
21680 if (GET_CODE (operands[3]) == UNORDERED)
21681 return "cmpordps\t{%2, %0|%0, %2}";
21683 return "cmpn%D3pd\t{%2, %0|%0, %2}";
21685 [(set_attr "type" "ssecmp")
21686 (set_attr "mode" "V2DF")])
21688 (define_insn "vmmaskcmpv2df3"
21689 [(set (match_operand:V2DI 0 "register_operand" "=x")
21691 (match_operator:V2DI 3 "sse_comparison_operator"
21692 [(match_operand:V2DF 1 "register_operand" "0")
21693 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
21694 (subreg:V2DI (match_dup 1) 0)
21697 "cmp%D3sd\t{%2, %0|%0, %2}"
21698 [(set_attr "type" "ssecmp")
21699 (set_attr "mode" "DF")])
21701 (define_insn "vmmaskncmpv2df3"
21702 [(set (match_operand:V2DI 0 "register_operand" "=x")
21705 (match_operator:V2DI 3 "sse_comparison_operator"
21706 [(match_operand:V2DF 1 "register_operand" "0")
21707 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
21708 (subreg:V2DI (match_dup 1) 0)
21712 if (GET_CODE (operands[3]) == UNORDERED)
21713 return "cmpordsd\t{%2, %0|%0, %2}";
21715 return "cmpn%D3sd\t{%2, %0|%0, %2}";
21717 [(set_attr "type" "ssecmp")
21718 (set_attr "mode" "DF")])
21720 (define_insn "sse2_comi"
21721 [(set (reg:CCFP 17)
21722 (compare:CCFP (vec_select:DF
21723 (match_operand:V2DF 0 "register_operand" "x")
21724 (parallel [(const_int 0)]))
21726 (match_operand:V2DF 1 "register_operand" "x")
21727 (parallel [(const_int 0)]))))]
21729 "comisd\t{%1, %0|%0, %1}"
21730 [(set_attr "type" "ssecomi")
21731 (set_attr "mode" "DF")])
21733 (define_insn "sse2_ucomi"
21734 [(set (reg:CCFPU 17)
21735 (compare:CCFPU (vec_select:DF
21736 (match_operand:V2DF 0 "register_operand" "x")
21737 (parallel [(const_int 0)]))
21739 (match_operand:V2DF 1 "register_operand" "x")
21740 (parallel [(const_int 0)]))))]
21742 "ucomisd\t{%1, %0|%0, %1}"
21743 [(set_attr "type" "ssecomi")
21744 (set_attr "mode" "DF")])
21746 ;; SSE Strange Moves.
21748 (define_insn "sse2_movmskpd"
21749 [(set (match_operand:SI 0 "register_operand" "=r")
21750 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
21753 "movmskpd\t{%1, %0|%0, %1}"
21754 [(set_attr "type" "ssecvt")
21755 (set_attr "mode" "V2DF")])
21757 (define_insn "sse2_pmovmskb"
21758 [(set (match_operand:SI 0 "register_operand" "=r")
21759 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
21762 "pmovmskb\t{%1, %0|%0, %1}"
21763 [(set_attr "type" "ssecvt")
21764 (set_attr "mode" "V2DF")])
21766 (define_insn "sse2_maskmovdqu"
21767 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
21768 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21769 (match_operand:V16QI 2 "register_operand" "x")]
21772 ;; @@@ check ordering of operands in intel/nonintel syntax
21773 "maskmovdqu\t{%2, %1|%1, %2}"
21774 [(set_attr "type" "ssecvt")
21775 (set_attr "mode" "TI")])
21777 (define_insn "sse2_maskmovdqu_rex64"
21778 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
21779 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
21780 (match_operand:V16QI 2 "register_operand" "x")]
21783 ;; @@@ check ordering of operands in intel/nonintel syntax
21784 "maskmovdqu\t{%2, %1|%1, %2}"
21785 [(set_attr "type" "ssecvt")
21786 (set_attr "mode" "TI")])
21788 (define_insn "sse2_movntv2df"
21789 [(set (match_operand:V2DF 0 "memory_operand" "=m")
21790 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
21793 "movntpd\t{%1, %0|%0, %1}"
21794 [(set_attr "type" "ssecvt")
21795 (set_attr "mode" "V2DF")])
21797 (define_insn "sse2_movntv2di"
21798 [(set (match_operand:V2DI 0 "memory_operand" "=m")
21799 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
21802 "movntdq\t{%1, %0|%0, %1}"
21803 [(set_attr "type" "ssecvt")
21804 (set_attr "mode" "TI")])
21806 (define_insn "sse2_movntsi"
21807 [(set (match_operand:SI 0 "memory_operand" "=m")
21808 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
21811 "movnti\t{%1, %0|%0, %1}"
21812 [(set_attr "type" "ssecvt")
21813 (set_attr "mode" "V2DF")])
21815 ;; SSE <-> integer/MMX conversions
21817 ;; Conversions between SI and SF
21819 (define_insn "cvtdq2ps"
21820 [(set (match_operand:V4SF 0 "register_operand" "=x")
21821 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
21823 "cvtdq2ps\t{%1, %0|%0, %1}"
21824 [(set_attr "type" "ssecvt")
21825 (set_attr "mode" "V2DF")])
21827 (define_insn "cvtps2dq"
21828 [(set (match_operand:V4SI 0 "register_operand" "=x")
21829 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
21831 "cvtps2dq\t{%1, %0|%0, %1}"
21832 [(set_attr "type" "ssecvt")
21833 (set_attr "mode" "TI")])
21835 (define_insn "cvttps2dq"
21836 [(set (match_operand:V4SI 0 "register_operand" "=x")
21837 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
21840 "cvttps2dq\t{%1, %0|%0, %1}"
21841 [(set_attr "type" "ssecvt")
21842 (set_attr "mode" "TI")])
21844 ;; Conversions between SI and DF
21846 (define_insn "cvtdq2pd"
21847 [(set (match_operand:V2DF 0 "register_operand" "=x")
21848 (float:V2DF (vec_select:V2SI
21849 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
21852 (const_int 1)]))))]
21854 "cvtdq2pd\t{%1, %0|%0, %1}"
21855 [(set_attr "type" "ssecvt")
21856 (set_attr "mode" "V2DF")])
21858 (define_insn "cvtpd2dq"
21859 [(set (match_operand:V4SI 0 "register_operand" "=x")
21861 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
21862 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21864 "cvtpd2dq\t{%1, %0|%0, %1}"
21865 [(set_attr "type" "ssecvt")
21866 (set_attr "mode" "TI")])
21868 (define_insn "cvttpd2dq"
21869 [(set (match_operand:V4SI 0 "register_operand" "=x")
21871 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21873 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
21875 "cvttpd2dq\t{%1, %0|%0, %1}"
21876 [(set_attr "type" "ssecvt")
21877 (set_attr "mode" "TI")])
21879 (define_insn "cvtpd2pi"
21880 [(set (match_operand:V2SI 0 "register_operand" "=y")
21881 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
21883 "cvtpd2pi\t{%1, %0|%0, %1}"
21884 [(set_attr "type" "ssecvt")
21885 (set_attr "mode" "TI")])
21887 (define_insn "cvttpd2pi"
21888 [(set (match_operand:V2SI 0 "register_operand" "=y")
21889 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
21892 "cvttpd2pi\t{%1, %0|%0, %1}"
21893 [(set_attr "type" "ssecvt")
21894 (set_attr "mode" "TI")])
21896 (define_insn "cvtpi2pd"
21897 [(set (match_operand:V2DF 0 "register_operand" "=x")
21898 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21900 "cvtpi2pd\t{%1, %0|%0, %1}"
21901 [(set_attr "type" "ssecvt")
21902 (set_attr "mode" "TI")])
21904 ;; Conversions between SI and DF
21906 (define_insn "cvtsd2si"
21907 [(set (match_operand:SI 0 "register_operand" "=r,r")
21908 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21909 (parallel [(const_int 0)]))))]
21911 "cvtsd2si\t{%1, %0|%0, %1}"
21912 [(set_attr "type" "sseicvt")
21913 (set_attr "athlon_decode" "double,vector")
21914 (set_attr "mode" "SI")])
21916 (define_insn "cvtsd2siq"
21917 [(set (match_operand:DI 0 "register_operand" "=r,r")
21918 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
21919 (parallel [(const_int 0)]))))]
21920 "TARGET_SSE2 && TARGET_64BIT"
21921 "cvtsd2siq\t{%1, %0|%0, %1}"
21922 [(set_attr "type" "sseicvt")
21923 (set_attr "athlon_decode" "double,vector")
21924 (set_attr "mode" "DI")])
21926 (define_insn "cvttsd2si"
21927 [(set (match_operand:SI 0 "register_operand" "=r,r")
21928 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21929 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21931 "cvttsd2si\t{%1, %0|%0, %1}"
21932 [(set_attr "type" "sseicvt")
21933 (set_attr "mode" "SI")
21934 (set_attr "athlon_decode" "double,vector")])
21936 (define_insn "cvttsd2siq"
21937 [(set (match_operand:DI 0 "register_operand" "=r,r")
21938 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
21939 (parallel [(const_int 0)]))] UNSPEC_FIX))]
21940 "TARGET_SSE2 && TARGET_64BIT"
21941 "cvttsd2siq\t{%1, %0|%0, %1}"
21942 [(set_attr "type" "sseicvt")
21943 (set_attr "mode" "DI")
21944 (set_attr "athlon_decode" "double,vector")])
21946 (define_insn "cvtsi2sd"
21947 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21948 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21949 (vec_duplicate:V2DF
21951 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
21954 "cvtsi2sd\t{%2, %0|%0, %2}"
21955 [(set_attr "type" "sseicvt")
21956 (set_attr "mode" "DF")
21957 (set_attr "athlon_decode" "double,direct")])
21959 (define_insn "cvtsi2sdq"
21960 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
21961 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
21962 (vec_duplicate:V2DF
21964 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
21966 "TARGET_SSE2 && TARGET_64BIT"
21967 "cvtsi2sdq\t{%2, %0|%0, %2}"
21968 [(set_attr "type" "sseicvt")
21969 (set_attr "mode" "DF")
21970 (set_attr "athlon_decode" "double,direct")])
21972 ;; Conversions between SF and DF
21974 (define_insn "cvtsd2ss"
21975 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
21976 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
21977 (vec_duplicate:V4SF
21978 (float_truncate:V2SF
21979 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
21982 "cvtsd2ss\t{%2, %0|%0, %2}"
21983 [(set_attr "type" "ssecvt")
21984 (set_attr "athlon_decode" "vector,double")
21985 (set_attr "mode" "SF")])
21987 (define_insn "cvtss2sd"
21988 [(set (match_operand:V2DF 0 "register_operand" "=x")
21989 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
21992 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
21993 (parallel [(const_int 0)
21997 "cvtss2sd\t{%2, %0|%0, %2}"
21998 [(set_attr "type" "ssecvt")
21999 (set_attr "mode" "DF")])
22001 (define_insn "cvtpd2ps"
22002 [(set (match_operand:V4SF 0 "register_operand" "=x")
22005 (subreg:V2SI (float_truncate:V2SF
22006 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22007 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22009 "cvtpd2ps\t{%1, %0|%0, %1}"
22010 [(set_attr "type" "ssecvt")
22011 (set_attr "mode" "V4SF")])
22013 (define_insn "cvtps2pd"
22014 [(set (match_operand:V2DF 0 "register_operand" "=x")
22016 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
22017 (parallel [(const_int 0)
22018 (const_int 1)]))))]
22020 "cvtps2pd\t{%1, %0|%0, %1}"
22021 [(set_attr "type" "ssecvt")
22022 (set_attr "mode" "V2DF")])
22024 ;; SSE2 variants of MMX insns
22028 (define_insn "addv16qi3"
22029 [(set (match_operand:V16QI 0 "register_operand" "=x")
22030 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22031 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22033 "paddb\t{%2, %0|%0, %2}"
22034 [(set_attr "type" "sseiadd")
22035 (set_attr "mode" "TI")])
22037 (define_insn "addv8hi3"
22038 [(set (match_operand:V8HI 0 "register_operand" "=x")
22039 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22040 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22042 "paddw\t{%2, %0|%0, %2}"
22043 [(set_attr "type" "sseiadd")
22044 (set_attr "mode" "TI")])
22046 (define_insn "addv4si3"
22047 [(set (match_operand:V4SI 0 "register_operand" "=x")
22048 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
22049 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22051 "paddd\t{%2, %0|%0, %2}"
22052 [(set_attr "type" "sseiadd")
22053 (set_attr "mode" "TI")])
22055 (define_insn "addv2di3"
22056 [(set (match_operand:V2DI 0 "register_operand" "=x")
22057 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
22058 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22060 "paddq\t{%2, %0|%0, %2}"
22061 [(set_attr "type" "sseiadd")
22062 (set_attr "mode" "TI")])
22064 (define_insn "ssaddv16qi3"
22065 [(set (match_operand:V16QI 0 "register_operand" "=x")
22066 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22067 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22069 "paddsb\t{%2, %0|%0, %2}"
22070 [(set_attr "type" "sseiadd")
22071 (set_attr "mode" "TI")])
22073 (define_insn "ssaddv8hi3"
22074 [(set (match_operand:V8HI 0 "register_operand" "=x")
22075 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22076 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22078 "paddsw\t{%2, %0|%0, %2}"
22079 [(set_attr "type" "sseiadd")
22080 (set_attr "mode" "TI")])
22082 (define_insn "usaddv16qi3"
22083 [(set (match_operand:V16QI 0 "register_operand" "=x")
22084 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22085 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22087 "paddusb\t{%2, %0|%0, %2}"
22088 [(set_attr "type" "sseiadd")
22089 (set_attr "mode" "TI")])
22091 (define_insn "usaddv8hi3"
22092 [(set (match_operand:V8HI 0 "register_operand" "=x")
22093 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22094 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22096 "paddusw\t{%2, %0|%0, %2}"
22097 [(set_attr "type" "sseiadd")
22098 (set_attr "mode" "TI")])
22100 (define_insn "subv16qi3"
22101 [(set (match_operand:V16QI 0 "register_operand" "=x")
22102 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22103 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22105 "psubb\t{%2, %0|%0, %2}"
22106 [(set_attr "type" "sseiadd")
22107 (set_attr "mode" "TI")])
22109 (define_insn "subv8hi3"
22110 [(set (match_operand:V8HI 0 "register_operand" "=x")
22111 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22112 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22114 "psubw\t{%2, %0|%0, %2}"
22115 [(set_attr "type" "sseiadd")
22116 (set_attr "mode" "TI")])
22118 (define_insn "subv4si3"
22119 [(set (match_operand:V4SI 0 "register_operand" "=x")
22120 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
22121 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22123 "psubd\t{%2, %0|%0, %2}"
22124 [(set_attr "type" "sseiadd")
22125 (set_attr "mode" "TI")])
22127 (define_insn "subv2di3"
22128 [(set (match_operand:V2DI 0 "register_operand" "=x")
22129 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
22130 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22132 "psubq\t{%2, %0|%0, %2}"
22133 [(set_attr "type" "sseiadd")
22134 (set_attr "mode" "TI")])
22136 (define_insn "sssubv16qi3"
22137 [(set (match_operand:V16QI 0 "register_operand" "=x")
22138 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22139 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22141 "psubsb\t{%2, %0|%0, %2}"
22142 [(set_attr "type" "sseiadd")
22143 (set_attr "mode" "TI")])
22145 (define_insn "sssubv8hi3"
22146 [(set (match_operand:V8HI 0 "register_operand" "=x")
22147 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22148 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22150 "psubsw\t{%2, %0|%0, %2}"
22151 [(set_attr "type" "sseiadd")
22152 (set_attr "mode" "TI")])
22154 (define_insn "ussubv16qi3"
22155 [(set (match_operand:V16QI 0 "register_operand" "=x")
22156 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22157 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22159 "psubusb\t{%2, %0|%0, %2}"
22160 [(set_attr "type" "sseiadd")
22161 (set_attr "mode" "TI")])
22163 (define_insn "ussubv8hi3"
22164 [(set (match_operand:V8HI 0 "register_operand" "=x")
22165 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22166 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22168 "psubusw\t{%2, %0|%0, %2}"
22169 [(set_attr "type" "sseiadd")
22170 (set_attr "mode" "TI")])
22172 (define_insn "mulv8hi3"
22173 [(set (match_operand:V8HI 0 "register_operand" "=x")
22174 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
22175 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22177 "pmullw\t{%2, %0|%0, %2}"
22178 [(set_attr "type" "sseimul")
22179 (set_attr "mode" "TI")])
22181 (define_insn "smulv8hi3_highpart"
22182 [(set (match_operand:V8HI 0 "register_operand" "=x")
22185 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22186 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22189 "pmulhw\t{%2, %0|%0, %2}"
22190 [(set_attr "type" "sseimul")
22191 (set_attr "mode" "TI")])
22193 (define_insn "umulv8hi3_highpart"
22194 [(set (match_operand:V8HI 0 "register_operand" "=x")
22197 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22198 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22201 "pmulhuw\t{%2, %0|%0, %2}"
22202 [(set_attr "type" "sseimul")
22203 (set_attr "mode" "TI")])
22205 (define_insn "sse2_umulsidi3"
22206 [(set (match_operand:DI 0 "register_operand" "=y")
22207 (mult:DI (zero_extend:DI (vec_select:SI
22208 (match_operand:V2SI 1 "register_operand" "0")
22209 (parallel [(const_int 0)])))
22210 (zero_extend:DI (vec_select:SI
22211 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
22212 (parallel [(const_int 0)])))))]
22214 "pmuludq\t{%2, %0|%0, %2}"
22215 [(set_attr "type" "sseimul")
22216 (set_attr "mode" "TI")])
22218 (define_insn "sse2_umulv2siv2di3"
22219 [(set (match_operand:V2DI 0 "register_operand" "=x")
22220 (mult:V2DI (zero_extend:V2DI
22222 (match_operand:V4SI 1 "register_operand" "0")
22223 (parallel [(const_int 0) (const_int 2)])))
22226 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
22227 (parallel [(const_int 0) (const_int 2)])))))]
22229 "pmuludq\t{%2, %0|%0, %2}"
22230 [(set_attr "type" "sseimul")
22231 (set_attr "mode" "TI")])
22233 (define_insn "sse2_pmaddwd"
22234 [(set (match_operand:V4SI 0 "register_operand" "=x")
22237 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
22238 (parallel [(const_int 0)
22242 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
22243 (parallel [(const_int 0)
22248 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22249 (parallel [(const_int 1)
22253 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22254 (parallel [(const_int 1)
22257 (const_int 7)]))))))]
22259 "pmaddwd\t{%2, %0|%0, %2}"
22260 [(set_attr "type" "sseiadd")
22261 (set_attr "mode" "TI")])
22263 ;; Same as pxor, but don't show input operands so that we don't think
22265 (define_insn "sse2_clrti"
22266 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22269 if (get_attr_mode (insn) == MODE_TI)
22270 return "pxor\t%0, %0";
22272 return "xorps\t%0, %0";
22274 [(set_attr "type" "ssemov")
22275 (set_attr "memory" "none")
22278 (ne (symbol_ref "optimize_size")
22280 (const_string "V4SF")
22281 (const_string "TI")))])
22283 ;; MMX unsigned averages/sum of absolute differences
22285 (define_insn "sse2_uavgv16qi3"
22286 [(set (match_operand:V16QI 0 "register_operand" "=x")
22288 (plus:V16QI (plus:V16QI
22289 (match_operand:V16QI 1 "register_operand" "0")
22290 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22291 (const_vector:V16QI [(const_int 1) (const_int 1)
22292 (const_int 1) (const_int 1)
22293 (const_int 1) (const_int 1)
22294 (const_int 1) (const_int 1)
22295 (const_int 1) (const_int 1)
22296 (const_int 1) (const_int 1)
22297 (const_int 1) (const_int 1)
22298 (const_int 1) (const_int 1)]))
22301 "pavgb\t{%2, %0|%0, %2}"
22302 [(set_attr "type" "sseiadd")
22303 (set_attr "mode" "TI")])
22305 (define_insn "sse2_uavgv8hi3"
22306 [(set (match_operand:V8HI 0 "register_operand" "=x")
22308 (plus:V8HI (plus:V8HI
22309 (match_operand:V8HI 1 "register_operand" "0")
22310 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22311 (const_vector:V8HI [(const_int 1) (const_int 1)
22312 (const_int 1) (const_int 1)
22313 (const_int 1) (const_int 1)
22314 (const_int 1) (const_int 1)]))
22317 "pavgw\t{%2, %0|%0, %2}"
22318 [(set_attr "type" "sseiadd")
22319 (set_attr "mode" "TI")])
22321 ;; @@@ this isn't the right representation.
22322 (define_insn "sse2_psadbw"
22323 [(set (match_operand:V2DI 0 "register_operand" "=x")
22324 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22325 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22328 "psadbw\t{%2, %0|%0, %2}"
22329 [(set_attr "type" "sseiadd")
22330 (set_attr "mode" "TI")])
22333 ;; MMX insert/extract/shuffle
22335 (define_insn "sse2_pinsrw"
22336 [(set (match_operand:V8HI 0 "register_operand" "=x")
22337 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22338 (vec_duplicate:V8HI
22340 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22341 (match_operand:SI 3 "immediate_operand" "i")))]
22343 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22344 [(set_attr "type" "ssecvt")
22345 (set_attr "mode" "TI")])
22347 (define_insn "sse2_pextrw"
22348 [(set (match_operand:SI 0 "register_operand" "=r")
22350 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22352 [(match_operand:SI 2 "immediate_operand" "i")]))))]
22354 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22355 [(set_attr "type" "ssecvt")
22356 (set_attr "mode" "TI")])
22358 (define_insn "sse2_pshufd"
22359 [(set (match_operand:V4SI 0 "register_operand" "=x")
22360 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22361 (match_operand:SI 2 "immediate_operand" "i")]
22364 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22365 [(set_attr "type" "ssecvt")
22366 (set_attr "mode" "TI")])
22368 (define_insn "sse2_pshuflw"
22369 [(set (match_operand:V8HI 0 "register_operand" "=x")
22370 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22371 (match_operand:SI 2 "immediate_operand" "i")]
22374 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22375 [(set_attr "type" "ssecvt")
22376 (set_attr "mode" "TI")])
22378 (define_insn "sse2_pshufhw"
22379 [(set (match_operand:V8HI 0 "register_operand" "=x")
22380 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22381 (match_operand:SI 2 "immediate_operand" "i")]
22384 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22385 [(set_attr "type" "ssecvt")
22386 (set_attr "mode" "TI")])
22388 ;; MMX mask-generating comparisons
22390 (define_insn "eqv16qi3"
22391 [(set (match_operand:V16QI 0 "register_operand" "=x")
22392 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22393 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22395 "pcmpeqb\t{%2, %0|%0, %2}"
22396 [(set_attr "type" "ssecmp")
22397 (set_attr "mode" "TI")])
22399 (define_insn "eqv8hi3"
22400 [(set (match_operand:V8HI 0 "register_operand" "=x")
22401 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22402 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22404 "pcmpeqw\t{%2, %0|%0, %2}"
22405 [(set_attr "type" "ssecmp")
22406 (set_attr "mode" "TI")])
22408 (define_insn "eqv4si3"
22409 [(set (match_operand:V4SI 0 "register_operand" "=x")
22410 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22411 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22413 "pcmpeqd\t{%2, %0|%0, %2}"
22414 [(set_attr "type" "ssecmp")
22415 (set_attr "mode" "TI")])
22417 (define_insn "gtv16qi3"
22418 [(set (match_operand:V16QI 0 "register_operand" "=x")
22419 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22420 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22422 "pcmpgtb\t{%2, %0|%0, %2}"
22423 [(set_attr "type" "ssecmp")
22424 (set_attr "mode" "TI")])
22426 (define_insn "gtv8hi3"
22427 [(set (match_operand:V8HI 0 "register_operand" "=x")
22428 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22429 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22431 "pcmpgtw\t{%2, %0|%0, %2}"
22432 [(set_attr "type" "ssecmp")
22433 (set_attr "mode" "TI")])
22435 (define_insn "gtv4si3"
22436 [(set (match_operand:V4SI 0 "register_operand" "=x")
22437 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22438 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22440 "pcmpgtd\t{%2, %0|%0, %2}"
22441 [(set_attr "type" "ssecmp")
22442 (set_attr "mode" "TI")])
22445 ;; MMX max/min insns
22447 (define_insn "umaxv16qi3"
22448 [(set (match_operand:V16QI 0 "register_operand" "=x")
22449 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22450 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22452 "pmaxub\t{%2, %0|%0, %2}"
22453 [(set_attr "type" "sseiadd")
22454 (set_attr "mode" "TI")])
22456 (define_insn "smaxv8hi3"
22457 [(set (match_operand:V8HI 0 "register_operand" "=x")
22458 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22459 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22461 "pmaxsw\t{%2, %0|%0, %2}"
22462 [(set_attr "type" "sseiadd")
22463 (set_attr "mode" "TI")])
22465 (define_insn "uminv16qi3"
22466 [(set (match_operand:V16QI 0 "register_operand" "=x")
22467 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22468 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22470 "pminub\t{%2, %0|%0, %2}"
22471 [(set_attr "type" "sseiadd")
22472 (set_attr "mode" "TI")])
22474 (define_insn "sminv8hi3"
22475 [(set (match_operand:V8HI 0 "register_operand" "=x")
22476 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22477 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22479 "pminsw\t{%2, %0|%0, %2}"
22480 [(set_attr "type" "sseiadd")
22481 (set_attr "mode" "TI")])
22486 (define_insn "ashrv8hi3"
22487 [(set (match_operand:V8HI 0 "register_operand" "=x")
22488 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22489 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22491 "psraw\t{%2, %0|%0, %2}"
22492 [(set_attr "type" "sseishft")
22493 (set_attr "mode" "TI")])
22495 (define_insn "ashrv4si3"
22496 [(set (match_operand:V4SI 0 "register_operand" "=x")
22497 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22498 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22500 "psrad\t{%2, %0|%0, %2}"
22501 [(set_attr "type" "sseishft")
22502 (set_attr "mode" "TI")])
22504 (define_insn "lshrv8hi3"
22505 [(set (match_operand:V8HI 0 "register_operand" "=x")
22506 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22507 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22509 "psrlw\t{%2, %0|%0, %2}"
22510 [(set_attr "type" "sseishft")
22511 (set_attr "mode" "TI")])
22513 (define_insn "lshrv4si3"
22514 [(set (match_operand:V4SI 0 "register_operand" "=x")
22515 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22516 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22518 "psrld\t{%2, %0|%0, %2}"
22519 [(set_attr "type" "sseishft")
22520 (set_attr "mode" "TI")])
22522 (define_insn "lshrv2di3"
22523 [(set (match_operand:V2DI 0 "register_operand" "=x")
22524 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22525 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22527 "psrlq\t{%2, %0|%0, %2}"
22528 [(set_attr "type" "sseishft")
22529 (set_attr "mode" "TI")])
22531 (define_insn "ashlv8hi3"
22532 [(set (match_operand:V8HI 0 "register_operand" "=x")
22533 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22534 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22536 "psllw\t{%2, %0|%0, %2}"
22537 [(set_attr "type" "sseishft")
22538 (set_attr "mode" "TI")])
22540 (define_insn "ashlv4si3"
22541 [(set (match_operand:V4SI 0 "register_operand" "=x")
22542 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22543 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22545 "pslld\t{%2, %0|%0, %2}"
22546 [(set_attr "type" "sseishft")
22547 (set_attr "mode" "TI")])
22549 (define_insn "ashlv2di3"
22550 [(set (match_operand:V2DI 0 "register_operand" "=x")
22551 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22552 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22554 "psllq\t{%2, %0|%0, %2}"
22555 [(set_attr "type" "sseishft")
22556 (set_attr "mode" "TI")])
22558 (define_insn "ashrv8hi3_ti"
22559 [(set (match_operand:V8HI 0 "register_operand" "=x")
22560 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22561 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22563 "psraw\t{%2, %0|%0, %2}"
22564 [(set_attr "type" "sseishft")
22565 (set_attr "mode" "TI")])
22567 (define_insn "ashrv4si3_ti"
22568 [(set (match_operand:V4SI 0 "register_operand" "=x")
22569 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22570 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22572 "psrad\t{%2, %0|%0, %2}"
22573 [(set_attr "type" "sseishft")
22574 (set_attr "mode" "TI")])
22576 (define_insn "lshrv8hi3_ti"
22577 [(set (match_operand:V8HI 0 "register_operand" "=x")
22578 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22579 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22581 "psrlw\t{%2, %0|%0, %2}"
22582 [(set_attr "type" "sseishft")
22583 (set_attr "mode" "TI")])
22585 (define_insn "lshrv4si3_ti"
22586 [(set (match_operand:V4SI 0 "register_operand" "=x")
22587 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22588 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22590 "psrld\t{%2, %0|%0, %2}"
22591 [(set_attr "type" "sseishft")
22592 (set_attr "mode" "TI")])
22594 (define_insn "lshrv2di3_ti"
22595 [(set (match_operand:V2DI 0 "register_operand" "=x")
22596 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22597 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22599 "psrlq\t{%2, %0|%0, %2}"
22600 [(set_attr "type" "sseishft")
22601 (set_attr "mode" "TI")])
22603 (define_insn "ashlv8hi3_ti"
22604 [(set (match_operand:V8HI 0 "register_operand" "=x")
22605 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22606 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22608 "psllw\t{%2, %0|%0, %2}"
22609 [(set_attr "type" "sseishft")
22610 (set_attr "mode" "TI")])
22612 (define_insn "ashlv4si3_ti"
22613 [(set (match_operand:V4SI 0 "register_operand" "=x")
22614 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22615 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22617 "pslld\t{%2, %0|%0, %2}"
22618 [(set_attr "type" "sseishft")
22619 (set_attr "mode" "TI")])
22621 (define_insn "ashlv2di3_ti"
22622 [(set (match_operand:V2DI 0 "register_operand" "=x")
22623 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22624 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22626 "psllq\t{%2, %0|%0, %2}"
22627 [(set_attr "type" "sseishft")
22628 (set_attr "mode" "TI")])
22630 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
22631 ;; we wouldn't need here it since we never generate TImode arithmetic.
22633 ;; There has to be some kind of prize for the weirdest new instruction...
22634 (define_insn "sse2_ashlti3"
22635 [(set (match_operand:TI 0 "register_operand" "=x")
22637 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
22638 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22639 (const_int 8)))] UNSPEC_NOP))]
22641 "pslldq\t{%2, %0|%0, %2}"
22642 [(set_attr "type" "sseishft")
22643 (set_attr "mode" "TI")])
22645 (define_insn "sse2_lshrti3"
22646 [(set (match_operand:TI 0 "register_operand" "=x")
22648 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
22649 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
22650 (const_int 8)))] UNSPEC_NOP))]
22652 "psrldq\t{%2, %0|%0, %2}"
22653 [(set_attr "type" "sseishft")
22654 (set_attr "mode" "TI")])
22658 (define_insn "sse2_unpckhpd"
22659 [(set (match_operand:V2DF 0 "register_operand" "=x")
22661 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22662 (parallel [(const_int 1)]))
22663 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22664 (parallel [(const_int 0)]))))]
22666 "unpckhpd\t{%2, %0|%0, %2}"
22667 [(set_attr "type" "ssecvt")
22668 (set_attr "mode" "TI")])
22670 (define_insn "sse2_unpcklpd"
22671 [(set (match_operand:V2DF 0 "register_operand" "=x")
22673 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
22674 (parallel [(const_int 0)]))
22675 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
22676 (parallel [(const_int 1)]))))]
22678 "unpcklpd\t{%2, %0|%0, %2}"
22679 [(set_attr "type" "ssecvt")
22680 (set_attr "mode" "TI")])
22682 ;; MMX pack/unpack insns.
22684 (define_insn "sse2_packsswb"
22685 [(set (match_operand:V16QI 0 "register_operand" "=x")
22687 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22688 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22690 "packsswb\t{%2, %0|%0, %2}"
22691 [(set_attr "type" "ssecvt")
22692 (set_attr "mode" "TI")])
22694 (define_insn "sse2_packssdw"
22695 [(set (match_operand:V8HI 0 "register_operand" "=x")
22697 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
22698 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
22700 "packssdw\t{%2, %0|%0, %2}"
22701 [(set_attr "type" "ssecvt")
22702 (set_attr "mode" "TI")])
22704 (define_insn "sse2_packuswb"
22705 [(set (match_operand:V16QI 0 "register_operand" "=x")
22707 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
22708 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
22710 "packuswb\t{%2, %0|%0, %2}"
22711 [(set_attr "type" "ssecvt")
22712 (set_attr "mode" "TI")])
22714 (define_insn "sse2_punpckhbw"
22715 [(set (match_operand:V16QI 0 "register_operand" "=x")
22717 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22718 (parallel [(const_int 8) (const_int 0)
22719 (const_int 9) (const_int 1)
22720 (const_int 10) (const_int 2)
22721 (const_int 11) (const_int 3)
22722 (const_int 12) (const_int 4)
22723 (const_int 13) (const_int 5)
22724 (const_int 14) (const_int 6)
22725 (const_int 15) (const_int 7)]))
22726 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22727 (parallel [(const_int 0) (const_int 8)
22728 (const_int 1) (const_int 9)
22729 (const_int 2) (const_int 10)
22730 (const_int 3) (const_int 11)
22731 (const_int 4) (const_int 12)
22732 (const_int 5) (const_int 13)
22733 (const_int 6) (const_int 14)
22734 (const_int 7) (const_int 15)]))
22735 (const_int 21845)))]
22737 "punpckhbw\t{%2, %0|%0, %2}"
22738 [(set_attr "type" "ssecvt")
22739 (set_attr "mode" "TI")])
22741 (define_insn "sse2_punpckhwd"
22742 [(set (match_operand:V8HI 0 "register_operand" "=x")
22744 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22745 (parallel [(const_int 4) (const_int 0)
22746 (const_int 5) (const_int 1)
22747 (const_int 6) (const_int 2)
22748 (const_int 7) (const_int 3)]))
22749 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22750 (parallel [(const_int 0) (const_int 4)
22751 (const_int 1) (const_int 5)
22752 (const_int 2) (const_int 6)
22753 (const_int 3) (const_int 7)]))
22756 "punpckhwd\t{%2, %0|%0, %2}"
22757 [(set_attr "type" "ssecvt")
22758 (set_attr "mode" "TI")])
22760 (define_insn "sse2_punpckhdq"
22761 [(set (match_operand:V4SI 0 "register_operand" "=x")
22763 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22764 (parallel [(const_int 2) (const_int 0)
22765 (const_int 3) (const_int 1)]))
22766 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22767 (parallel [(const_int 0) (const_int 2)
22768 (const_int 1) (const_int 3)]))
22771 "punpckhdq\t{%2, %0|%0, %2}"
22772 [(set_attr "type" "ssecvt")
22773 (set_attr "mode" "TI")])
22775 (define_insn "sse2_punpcklbw"
22776 [(set (match_operand:V16QI 0 "register_operand" "=x")
22778 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
22779 (parallel [(const_int 0) (const_int 8)
22780 (const_int 1) (const_int 9)
22781 (const_int 2) (const_int 10)
22782 (const_int 3) (const_int 11)
22783 (const_int 4) (const_int 12)
22784 (const_int 5) (const_int 13)
22785 (const_int 6) (const_int 14)
22786 (const_int 7) (const_int 15)]))
22787 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
22788 (parallel [(const_int 8) (const_int 0)
22789 (const_int 9) (const_int 1)
22790 (const_int 10) (const_int 2)
22791 (const_int 11) (const_int 3)
22792 (const_int 12) (const_int 4)
22793 (const_int 13) (const_int 5)
22794 (const_int 14) (const_int 6)
22795 (const_int 15) (const_int 7)]))
22796 (const_int 21845)))]
22798 "punpcklbw\t{%2, %0|%0, %2}"
22799 [(set_attr "type" "ssecvt")
22800 (set_attr "mode" "TI")])
22802 (define_insn "sse2_punpcklwd"
22803 [(set (match_operand:V8HI 0 "register_operand" "=x")
22805 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
22806 (parallel [(const_int 0) (const_int 4)
22807 (const_int 1) (const_int 5)
22808 (const_int 2) (const_int 6)
22809 (const_int 3) (const_int 7)]))
22810 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
22811 (parallel [(const_int 4) (const_int 0)
22812 (const_int 5) (const_int 1)
22813 (const_int 6) (const_int 2)
22814 (const_int 7) (const_int 3)]))
22817 "punpcklwd\t{%2, %0|%0, %2}"
22818 [(set_attr "type" "ssecvt")
22819 (set_attr "mode" "TI")])
22821 (define_insn "sse2_punpckldq"
22822 [(set (match_operand:V4SI 0 "register_operand" "=x")
22824 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
22825 (parallel [(const_int 0) (const_int 2)
22826 (const_int 1) (const_int 3)]))
22827 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
22828 (parallel [(const_int 2) (const_int 0)
22829 (const_int 3) (const_int 1)]))
22832 "punpckldq\t{%2, %0|%0, %2}"
22833 [(set_attr "type" "ssecvt")
22834 (set_attr "mode" "TI")])
22836 (define_insn "sse2_punpcklqdq"
22837 [(set (match_operand:V2DI 0 "register_operand" "=x")
22839 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22840 (parallel [(const_int 1)
22842 (match_operand:V2DI 1 "register_operand" "0")
22845 "punpcklqdq\t{%2, %0|%0, %2}"
22846 [(set_attr "type" "ssecvt")
22847 (set_attr "mode" "TI")])
22849 (define_insn "sse2_punpckhqdq"
22850 [(set (match_operand:V2DI 0 "register_operand" "=x")
22852 (match_operand:V2DI 1 "register_operand" "0")
22853 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
22854 (parallel [(const_int 1)
22858 "punpckhqdq\t{%2, %0|%0, %2}"
22859 [(set_attr "type" "ssecvt")
22860 (set_attr "mode" "TI")])
22864 (define_insn "sse2_movapd"
22865 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22866 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22869 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22870 "movapd\t{%1, %0|%0, %1}"
22871 [(set_attr "type" "ssemov")
22872 (set_attr "mode" "V2DF")])
22874 (define_insn "sse2_movupd"
22875 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22876 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
22879 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22880 "movupd\t{%1, %0|%0, %1}"
22881 [(set_attr "type" "ssecvt")
22882 (set_attr "mode" "V2DF")])
22884 (define_insn "sse2_movdqa"
22885 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22886 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22889 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22890 "movdqa\t{%1, %0|%0, %1}"
22891 [(set_attr "type" "ssemov")
22892 (set_attr "mode" "TI")])
22894 (define_insn "sse2_movdqu"
22895 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
22896 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
22899 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
22900 "movdqu\t{%1, %0|%0, %1}"
22901 [(set_attr "type" "ssecvt")
22902 (set_attr "mode" "TI")])
22904 (define_insn "sse2_movdq2q"
22905 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
22906 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
22907 (parallel [(const_int 0)])))]
22908 "TARGET_SSE2 && !TARGET_64BIT"
22910 movq\t{%1, %0|%0, %1}
22911 movdq2q\t{%1, %0|%0, %1}"
22912 [(set_attr "type" "ssecvt")
22913 (set_attr "mode" "TI")])
22915 (define_insn "sse2_movdq2q_rex64"
22916 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
22917 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
22918 (parallel [(const_int 0)])))]
22919 "TARGET_SSE2 && TARGET_64BIT"
22921 movq\t{%1, %0|%0, %1}
22922 movdq2q\t{%1, %0|%0, %1}
22923 movd\t{%1, %0|%0, %1}"
22924 [(set_attr "type" "ssecvt")
22925 (set_attr "mode" "TI")])
22927 (define_insn "sse2_movq2dq"
22928 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
22929 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
22931 "TARGET_SSE2 && !TARGET_64BIT"
22933 movq\t{%1, %0|%0, %1}
22934 movq2dq\t{%1, %0|%0, %1}"
22935 [(set_attr "type" "ssecvt,ssemov")
22936 (set_attr "mode" "TI")])
22938 (define_insn "sse2_movq2dq_rex64"
22939 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
22940 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
22942 "TARGET_SSE2 && TARGET_64BIT"
22944 movq\t{%1, %0|%0, %1}
22945 movq2dq\t{%1, %0|%0, %1}
22946 movd\t{%1, %0|%0, %1}"
22947 [(set_attr "type" "ssecvt,ssemov,ssecvt")
22948 (set_attr "mode" "TI")])
22950 (define_insn "sse2_movq"
22951 [(set (match_operand:V2DI 0 "register_operand" "=x")
22952 (vec_concat:V2DI (vec_select:DI
22953 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
22954 (parallel [(const_int 0)]))
22957 "movq\t{%1, %0|%0, %1}"
22958 [(set_attr "type" "ssemov")
22959 (set_attr "mode" "TI")])
22961 (define_insn "sse2_loadd"
22962 [(set (match_operand:V4SI 0 "register_operand" "=x")
22964 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
22965 (const_vector:V4SI [(const_int 0)
22971 "movd\t{%1, %0|%0, %1}"
22972 [(set_attr "type" "ssemov")
22973 (set_attr "mode" "TI")])
22975 (define_insn "sse2_stored"
22976 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
22978 (match_operand:V4SI 1 "register_operand" "x")
22979 (parallel [(const_int 0)])))]
22981 "movd\t{%1, %0|%0, %1}"
22982 [(set_attr "type" "ssemov")
22983 (set_attr "mode" "TI")])
22985 (define_insn "sse2_movhpd"
22986 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22988 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
22989 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
22991 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
22992 "movhpd\t{%2, %0|%0, %2}"
22993 [(set_attr "type" "ssecvt")
22994 (set_attr "mode" "V2DF")])
22996 (define_insn "sse2_movlpd"
22997 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
22999 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23000 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23002 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23003 "movlpd\t{%2, %0|%0, %2}"
23004 [(set_attr "type" "ssecvt")
23005 (set_attr "mode" "V2DF")])
23007 (define_expand "sse2_loadsd"
23008 [(match_operand:V2DF 0 "register_operand" "")
23009 (match_operand:DF 1 "memory_operand" "")]
23012 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23013 CONST0_RTX (V2DFmode)));
23017 (define_insn "sse2_loadsd_1"
23018 [(set (match_operand:V2DF 0 "register_operand" "=x")
23020 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
23021 (match_operand:V2DF 2 "const0_operand" "X")
23024 "movsd\t{%1, %0|%0, %1}"
23025 [(set_attr "type" "ssecvt")
23026 (set_attr "mode" "DF")])
23028 (define_insn "sse2_movsd"
23029 [(set (match_operand:V2DF 0 "register_operand" "=x")
23031 (match_operand:V2DF 1 "register_operand" "0")
23032 (match_operand:V2DF 2 "register_operand" "x")
23035 "movsd\t{%2, %0|%0, %2}"
23036 [(set_attr "type" "ssecvt")
23037 (set_attr "mode" "DF")])
23039 (define_insn "sse2_storesd"
23040 [(set (match_operand:DF 0 "memory_operand" "=m")
23042 (match_operand:V2DF 1 "register_operand" "x")
23043 (parallel [(const_int 0)])))]
23045 "movsd\t{%1, %0|%0, %1}"
23046 [(set_attr "type" "ssecvt")
23047 (set_attr "mode" "DF")])
23049 (define_insn "sse2_shufpd"
23050 [(set (match_operand:V2DF 0 "register_operand" "=x")
23051 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23052 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
23053 (match_operand:SI 3 "immediate_operand" "i")]
23056 ;; @@@ check operand order for intel/nonintel syntax
23057 "shufpd\t{%3, %2, %0|%0, %2, %3}"
23058 [(set_attr "type" "ssecvt")
23059 (set_attr "mode" "V2DF")])
23061 (define_insn "sse2_clflush"
23062 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
23066 [(set_attr "type" "sse")
23067 (set_attr "memory" "unknown")])
23069 (define_expand "sse2_mfence"
23070 [(set (match_dup 0)
23071 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23074 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23075 MEM_VOLATILE_P (operands[0]) = 1;
23078 (define_insn "*mfence_insn"
23079 [(set (match_operand:BLK 0 "" "")
23080 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23083 [(set_attr "type" "sse")
23084 (set_attr "memory" "unknown")])
23086 (define_expand "sse2_lfence"
23087 [(set (match_dup 0)
23088 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23091 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23092 MEM_VOLATILE_P (operands[0]) = 1;
23095 (define_insn "*lfence_insn"
23096 [(set (match_operand:BLK 0 "" "")
23097 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23100 [(set_attr "type" "sse")
23101 (set_attr "memory" "unknown")])